MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.h

   1 /** @file
   2   x64 Long Mode Virtual Memory Management Definitions
   3
   4   References:
   5     1) IA-32 Intel(R) Architecture Software Developer's Manual Volume 1:Basic Architecture, Intel
   6     2) IA-32 Intel(R) Architecture Software Developer's Manual Volume 2:Instruction Set Reference, Intel
   7     3) IA-32 Intel(R) Architecture Software Developer's Manual Volume 3:System Programmer's Guide, Intel
   8     4) AMD64 Architecture Programmer's Manual Volume 2: System Programming
   9
  10 Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
  11 Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
  12
  13 SPDX-License-Identifier: BSD-2-Clause-Patent
  14
  15 **/
  16
  17 #ifndef _VIRTUAL_MEMORY_H_
  18 #define _VIRTUAL_MEMORY_H_
  19
  20 #define SYS_CODE64_SEL  0x38
  21
  22 #pragma pack(1)
  23
  24 typedef union {
  25   struct {
  26     UINT32    LimitLow    : 16;
  27     UINT32    BaseLow     : 16;
  28     UINT32    BaseMid     : 8;
  29     UINT32    Type        : 4;
  30     UINT32    System      : 1;
  31     UINT32    Dpl         : 2;
  32     UINT32    Present     : 1;
  33     UINT32    LimitHigh   : 4;
  34     UINT32    Software    : 1;
  35     UINT32    Reserved    : 1;
  36     UINT32    DefaultSize : 1;
  37     UINT32    Granularity : 1;
  38     UINT32    BaseHigh    : 8;
  39   } Bits;
  40   UINT64    Uint64;
  41 } IA32_GDT;
  42
  43 typedef struct {
  44   IA32_IDT_GATE_DESCRIPTOR    Ia32IdtEntry;
  45   UINT32                      Offset32To63;
  46   UINT32                      Reserved;
  47 } X64_IDT_GATE_DESCRIPTOR;
  48
  49 //
  50 // Page-Map Level-4 Offset (PML4) and
  51 // Page-Directory-Pointer Offset (PDPE) entries 4K & 2MB
  52 //
  53
  54 typedef union {
  55   struct {
  56     UINT64    Present              : 1;  // 0 = Not present in memory, 1 = Present in memory
  57     UINT64    ReadWrite            : 1;  // 0 = Read-Only, 1= Read/Write
  58     UINT64    UserSupervisor       : 1;  // 0 = Supervisor, 1=User
  59     UINT64    WriteThrough         : 1;  // 0 = Write-Back caching, 1=Write-Through caching
  60     UINT64    CacheDisabled        : 1;  // 0 = Cached, 1=Non-Cached
  61     UINT64    Accessed             : 1;  // 0 = Not accessed, 1 = Accessed (set by CPU)
  62     UINT64    Reserved             : 1;  // Reserved
  63     UINT64    MustBeZero           : 2;  // Must Be Zero
  64     UINT64    Available            : 3;  // Available for use by system software
  65     UINT64    PageTableBaseAddress : 40; // Page Table Base Address
  66     UINT64    AvabilableHigh       : 11; // Available for use by system software
  67     UINT64    Nx                   : 1;  // No Execute bit
  68   } Bits;
  69   UINT64    Uint64;
  70 } PAGE_MAP_AND_DIRECTORY_POINTER;
  71
  72 //
  73 // Page Table Entry 4KB
  74 //
  75 typedef union {
  76   struct {
  77     UINT64    Present              : 1;  // 0 = Not present in memory, 1 = Present in memory
  78     UINT64    ReadWrite            : 1;  // 0 = Read-Only, 1= Read/Write
  79     UINT64    UserSupervisor       : 1;  // 0 = Supervisor, 1=User
  80     UINT64    WriteThrough         : 1;  // 0 = Write-Back caching, 1=Write-Through caching
  81     UINT64    CacheDisabled        : 1;  // 0 = Cached, 1=Non-Cached
  82     UINT64    Accessed             : 1;  // 0 = Not accessed, 1 = Accessed (set by CPU)
  83     UINT64    Dirty                : 1;  // 0 = Not Dirty, 1 = written by processor on access to page
  84     UINT64    PAT                  : 1;  //
  85     UINT64    Global               : 1;  // 0 = Not global page, 1 = global page TLB not cleared on CR3 write
  86     UINT64    Available            : 3;  // Available for use by system software
  87     UINT64    PageTableBaseAddress : 40; // Page Table Base Address
  88     UINT64    AvabilableHigh       : 11; // Available for use by system software
  89     UINT64    Nx                   : 1;  // 0 = Execute Code, 1 = No Code Execution
  90   } Bits;
  91   UINT64    Uint64;
  92 } PAGE_TABLE_4K_ENTRY;
  93
  94 //
  95 // Page Table Entry 2MB
  96 //
  97 typedef union {
  98   struct {
  99     UINT64    Present              : 1;  // 0 = Not present in memory, 1 = Present in memory
 100     UINT64    ReadWrite            : 1;  // 0 = Read-Only, 1= Read/Write
 101     UINT64    UserSupervisor       : 1;  // 0 = Supervisor, 1=User
 102     UINT64    WriteThrough         : 1;  // 0 = Write-Back caching, 1=Write-Through caching
 103     UINT64    CacheDisabled        : 1;  // 0 = Cached, 1=Non-Cached
 104     UINT64    Accessed             : 1;  // 0 = Not accessed, 1 = Accessed (set by CPU)
 105     UINT64    Dirty                : 1;  // 0 = Not Dirty, 1 = written by processor on access to page
 106     UINT64    MustBe1              : 1;  // Must be 1
 107     UINT64    Global               : 1;  // 0 = Not global page, 1 = global page TLB not cleared on CR3 write
 108     UINT64    Available            : 3;  // Available for use by system software
 109     UINT64    PAT                  : 1;  //
 110     UINT64    MustBeZero           : 8;  // Must be zero;
 111     UINT64    PageTableBaseAddress : 31; // Page Table Base Address
 112     UINT64    AvabilableHigh       : 11; // Available for use by system software
 113     UINT64    Nx                   : 1;  // 0 = Execute Code, 1 = No Code Execution
 114   } Bits;
 115   UINT64    Uint64;
 116 } PAGE_TABLE_ENTRY;
 117
 118 //
 119 // Page Table Entry 1GB
 120 //
 121 typedef union {
 122   struct {
 123     UINT64    Present              : 1;  // 0 = Not present in memory, 1 = Present in memory
 124     UINT64    ReadWrite            : 1;  // 0 = Read-Only, 1= Read/Write
 125     UINT64    UserSupervisor       : 1;  // 0 = Supervisor, 1=User
 126     UINT64    WriteThrough         : 1;  // 0 = Write-Back caching, 1=Write-Through caching
 127     UINT64    CacheDisabled        : 1;  // 0 = Cached, 1=Non-Cached
 128     UINT64    Accessed             : 1;  // 0 = Not accessed, 1 = Accessed (set by CPU)
 129     UINT64    Dirty                : 1;  // 0 = Not Dirty, 1 = written by processor on access to page
 130     UINT64    MustBe1              : 1;  // Must be 1
 131     UINT64    Global               : 1;  // 0 = Not global page, 1 = global page TLB not cleared on CR3 write
 132     UINT64    Available            : 3;  // Available for use by system software
 133     UINT64    PAT                  : 1;  //
 134     UINT64    MustBeZero           : 17; // Must be zero;
 135     UINT64    PageTableBaseAddress : 22; // Page Table Base Address
 136     UINT64    AvabilableHigh       : 11; // Available for use by system software
 137     UINT64    Nx                   : 1;  // 0 = Execute Code, 1 = No Code Execution
 138   } Bits;
 139   UINT64    Uint64;
 140 } PAGE_TABLE_1G_ENTRY;
 141
 142 #pragma pack()
 143
 144 #define CR0_WP  BIT16
 145
 146 #define IA32_PG_P   BIT0
 147 #define IA32_PG_RW  BIT1
 148 #define IA32_PG_PS  BIT7
 149
 150 #define PAGING_PAE_INDEX_MASK  0x1FF
 151
 152 #define PAGING_4K_ADDRESS_MASK_64  0x000FFFFFFFFFF000ull
 153 #define PAGING_2M_ADDRESS_MASK_64  0x000FFFFFFFE00000ull
 154 #define PAGING_1G_ADDRESS_MASK_64  0x000FFFFFC0000000ull
 155
 156 #define PAGING_L1_ADDRESS_SHIFT  12
 157 #define PAGING_L2_ADDRESS_SHIFT  21
 158 #define PAGING_L3_ADDRESS_SHIFT  30
 159 #define PAGING_L4_ADDRESS_SHIFT  39
 160
 161 #define PAGING_PML4E_NUMBER  4
 162
 163 #define PAGE_TABLE_POOL_ALIGNMENT   BASE_2MB
 164 #define PAGE_TABLE_POOL_UNIT_SIZE   SIZE_2MB
 165 #define PAGE_TABLE_POOL_UNIT_PAGES  EFI_SIZE_TO_PAGES (PAGE_TABLE_POOL_UNIT_SIZE)
 166 #define PAGE_TABLE_POOL_ALIGN_MASK  \
 167   (~(EFI_PHYSICAL_ADDRESS)(PAGE_TABLE_POOL_ALIGNMENT - 1))
 168
 169 typedef struct {
 170   VOID     *NextPool;
 171   UINTN    Offset;
 172   UINTN    FreePages;
 173 } PAGE_TABLE_POOL;
 174
 175 /**
 176   Check if Execute Disable Bit (IA32_EFER.NXE) should be enabled or not.
 177
 178   @retval TRUE    IA32_EFER.NXE should be enabled.
 179   @retval FALSE   IA32_EFER.NXE should not be enabled.
 180
 181 **/
 182 BOOLEAN
 183 IsEnableNonExecNeeded (
 184   VOID
 185   );
 186
 187 /**
 188   Enable Execute Disable Bit.
 189
 190 **/
 191 VOID
 192 EnableExecuteDisableBit (
 193   VOID
 194   );
 195
 196 /**
 197   Split 2M page to 4K.
 198
 199   @param[in]      PhysicalAddress       Start physical address the 2M page covered.
 200   @param[in, out] PageEntry2M           Pointer to 2M page entry.
 201   @param[in]      StackBase             Stack base address.
 202   @param[in]      StackSize             Stack size.
 203   @param[in]      GhcbBase              GHCB page area base address.
 204   @param[in]      GhcbSize              GHCB page area size.
 205
 206 **/
 207 VOID
 208 Split2MPageTo4K (
 209   IN EFI_PHYSICAL_ADDRESS  PhysicalAddress,
 210   IN OUT UINT64            *PageEntry2M,
 211   IN EFI_PHYSICAL_ADDRESS  StackBase,
 212   IN UINTN                 StackSize,
 213   IN EFI_PHYSICAL_ADDRESS  GhcbBase,
 214   IN UINTN                 GhcbSize
 215   );
 216
 217 /**
 218   Allocates and fills in the Page Directory and Page Table Entries to
 219   establish a 1:1 Virtual to Physical mapping.
 220
 221   @param[in] StackBase  Stack base address.
 222   @param[in] StackSize  Stack size.
 223   @param[in] GhcbBase   GHCB page area base address.
 224   @param[in] GhcbSize   GHCB page area size.
 225
 226   @return The address of 4 level page map.
 227
 228 **/
 229 UINTN
 230 CreateIdentityMappingPageTables (
 231   IN EFI_PHYSICAL_ADDRESS  StackBase,
 232   IN UINTN                 StackSize,
 233   IN EFI_PHYSICAL_ADDRESS  GhcbBase,
 234   IN UINTN                 GhcbkSize
 235   );
 236
 237 /**
 238
 239   Fix up the vector number in the vector code.
 240
 241   @param VectorBase   Base address of the vector handler.
 242   @param VectorNum    Index of vector.
 243
 244 **/
 245 VOID
 246 EFIAPI
 247 AsmVectorFixup (
 248   VOID   *VectorBase,
 249   UINT8  VectorNum
 250   );
 251
 252 /**
 253
 254   Get the information of vector template.
 255
 256   @param TemplateBase   Base address of the template code.
 257
 258   @return               Size of the Template code.
 259
 260 **/
 261 UINTN
 262 EFIAPI
 263 AsmGetVectorTemplatInfo (
 264   OUT   VOID  **TemplateBase
 265   );
 266
 267 /**
 268   Clear legacy memory located at the first 4K-page.
 269
 270   This function traverses the whole HOB list to check if memory from 0 to 4095
 271   exists and has not been allocated, and then clear it if so.
 272
 273   @param HobStart         The start of HobList passed to DxeCore.
 274
 275 **/
 276 VOID
 277 ClearFirst4KPage (
 278   IN  VOID  *HobStart
 279   );
 280
 281 /**
 282   Return configure status of NULL pointer detection feature.
 283
 284   @return TRUE   NULL pointer detection feature is enabled
 285   @return FALSE  NULL pointer detection feature is disabled
 286 **/
 287 BOOLEAN
 288 IsNullDetectionEnabled (
 289   VOID
 290   );
 291
 292 /**
 293   Prevent the memory pages used for page table from been overwritten.
 294
 295   @param[in] PageTableBase    Base address of page table (CR3).
 296   @param[in] Level4Paging     Level 4 paging flag.
 297
 298 **/
 299 VOID
 300 EnablePageTableProtection (
 301   IN  UINTN    PageTableBase,
 302   IN  BOOLEAN  Level4Paging
 303   );
 304
 305 /**
 306   This API provides a way to allocate memory for page table.
 307
 308   This API can be called more than once to allocate memory for page tables.
 309
 310   Allocates the number of 4KB pages and returns a pointer to the allocated
 311   buffer. The buffer returned is aligned on a 4KB boundary.
 312
 313   If Pages is 0, then NULL is returned.
 314   If there is not enough memory remaining to satisfy the request, then NULL is
 315   returned.
 316
 317   @param  Pages                 The number of 4 KB pages to allocate.
 318
 319   @return A pointer to the allocated buffer or NULL if allocation fails.
 320
 321 **/
 322 VOID *
 323 AllocatePageTableMemory (
 324   IN UINTN  Pages
 325   );
 326
 327 #endif