3 Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
5 This program and the accompanying materials
6 are licensed and made available under the terms and conditions
7 of the BSD License which accompanies this distribution. The
8 full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
16 #ifndef _CAPSULE_PEIM_H_
17 #define _CAPSULE_PEIM_H_
20 #include <Uefi/UefiSpec.h>
22 #include <Ppi/Capsule.h>
23 #include <Ppi/LoadFile.h>
24 #include <Ppi/ReadOnlyVariable2.h>
25 #include <Guid/CapsuleVendor.h>
27 #include <Library/BaseLib.h>
28 #include <Library/DebugLib.h>
29 #include <Library/PeimEntryPoint.h>
30 #include <Library/PeiServicesLib.h>
31 #include <Library/BaseMemoryLib.h>
32 #include <Library/HobLib.h>
33 #include <Library/PeiServicesTablePointerLib.h>
34 #include <Library/PrintLib.h>
35 #include <Library/PeCoffLib.h>
36 #include <Library/PeCoffGetEntryPointLib.h>
37 #include <Library/PcdLib.h>
38 #include <Library/ReportStatusCodeLib.h>
39 #include <Library/DebugAgentLib.h>
40 #include <IndustryStandard/PeImage.h>
41 #include "Common/CommonHeader.h"
48 // Page-Map Level-4 Offset (PML4) and
49 // Page-Directory-Pointer Offset (PDPE) entries 4K & 2MB
54 UINT64 Present
:1; // 0 = Not present in memory, 1 = Present in memory
55 UINT64 ReadWrite
:1; // 0 = Read-Only, 1= Read/Write
56 UINT64 UserSupervisor
:1; // 0 = Supervisor, 1=User
57 UINT64 WriteThrough
:1; // 0 = Write-Back caching, 1=Write-Through caching
58 UINT64 CacheDisabled
:1; // 0 = Cached, 1=Non-Cached
59 UINT64 Accessed
:1; // 0 = Not accessed, 1 = Accessed (set by CPU)
60 UINT64 Reserved
:1; // Reserved
61 UINT64 MustBeZero
:2; // Must Be Zero
62 UINT64 Available
:3; // Available for use by system software
63 UINT64 PageTableBaseAddress
:40; // Page Table Base Address
64 UINT64 AvabilableHigh
:11; // Available for use by system software
65 UINT64 Nx
:1; // No Execute bit
68 } PAGE_MAP_AND_DIRECTORY_POINTER
;
71 // Page Table Entry 2MB
75 UINT64 Present
:1; // 0 = Not present in memory, 1 = Present in memory
76 UINT64 ReadWrite
:1; // 0 = Read-Only, 1= Read/Write
77 UINT64 UserSupervisor
:1; // 0 = Supervisor, 1=User
78 UINT64 WriteThrough
:1; // 0 = Write-Back caching, 1=Write-Through caching
79 UINT64 CacheDisabled
:1; // 0 = Cached, 1=Non-Cached
80 UINT64 Accessed
:1; // 0 = Not accessed, 1 = Accessed (set by CPU)
81 UINT64 Dirty
:1; // 0 = Not Dirty, 1 = written by processor on access to page
82 UINT64 MustBe1
:1; // Must be 1
83 UINT64 Global
:1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write
84 UINT64 Available
:3; // Available for use by system software
86 UINT64 MustBeZero
:8; // Must be zero;
87 UINT64 PageTableBaseAddress
:31; // Page Table Base Address
88 UINT64 AvabilableHigh
:11; // Available for use by system software
89 UINT64 Nx
:1; // 0 = Execute Code, 1 = No Code Execution
95 // Page Table Entry 1GB
99 UINT64 Present
:1; // 0 = Not present in memory, 1 = Present in memory
100 UINT64 ReadWrite
:1; // 0 = Read-Only, 1= Read/Write
101 UINT64 UserSupervisor
:1; // 0 = Supervisor, 1=User
102 UINT64 WriteThrough
:1; // 0 = Write-Back caching, 1=Write-Through caching
103 UINT64 CacheDisabled
:1; // 0 = Cached, 1=Non-Cached
104 UINT64 Accessed
:1; // 0 = Not accessed, 1 = Accessed (set by CPU)
105 UINT64 Dirty
:1; // 0 = Not Dirty, 1 = written by processor on access to page
106 UINT64 MustBe1
:1; // Must be 1
107 UINT64 Global
:1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write
108 UINT64 Available
:3; // Available for use by system software
110 UINT64 MustBeZero
:17; // Must be zero;
111 UINT64 PageTableBaseAddress
:22; // Page Table Base Address
112 UINT64 AvabilableHigh
:11; // Available for use by system software
113 UINT64 Nx
:1; // 0 = Execute Code, 1 = No Code Execution
116 } PAGE_TABLE_1G_ENTRY
;
123 SWITCH_32_TO_64_CONTEXT
*EntrypointContext
,
124 SWITCH_64_TO_32_CONTEXT
*ReturnContext