MdeModulePkg/Universal/CapsulePei/Capsule.h

   1 /** @file
   2
   3 Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
   4
   5 SPDX-License-Identifier: BSD-2-Clause-Patent
   6
   7 **/
   8
   9 #ifndef _CAPSULE_PEIM_H_
  10 #define _CAPSULE_PEIM_H_
  11
  12 #include <PiPei.h>
  13 #include <Uefi/UefiSpec.h>
  14
  15 #include <Ppi/Capsule.h>
  16 #include <Ppi/LoadFile.h>
  17 #include <Ppi/ReadOnlyVariable2.h>
  18 #include <Guid/CapsuleVendor.h>
  19
  20 #include <Library/BaseLib.h>
  21 #include <Library/DebugLib.h>
  22 #include <Library/PeimEntryPoint.h>
  23 #include <Library/PeiServicesLib.h>
  24 #include <Library/BaseMemoryLib.h>
  25 #include <Library/HobLib.h>
  26 #include <Library/PeiServicesTablePointerLib.h>
  27 #include <Library/PrintLib.h>
  28 #include <Library/PeCoffLib.h>
  29 #include <Library/PeCoffGetEntryPointLib.h>
  30 #include <Library/PcdLib.h>
  31 #include <Library/ReportStatusCodeLib.h>
  32 #include <Library/DebugAgentLib.h>
  33 #include <Library/MemoryAllocationLib.h>
  34 #include <IndustryStandard/PeImage.h>
  35 #include "Common/CommonHeader.h"
  36
  37 #ifdef MDE_CPU_IA32
  38
  39   #pragma pack(1)
  40
  41 //
  42 // Page-Map Level-4 Offset (PML4) and
  43 // Page-Directory-Pointer Offset (PDPE) entries 4K & 2MB
  44 //
  45
  46 typedef union {
  47   struct {
  48     UINT64    Present              : 1;  // 0 = Not present in memory, 1 = Present in memory
  49     UINT64    ReadWrite            : 1;  // 0 = Read-Only, 1= Read/Write
  50     UINT64    UserSupervisor       : 1;  // 0 = Supervisor, 1=User
  51     UINT64    WriteThrough         : 1;  // 0 = Write-Back caching, 1=Write-Through caching
  52     UINT64    CacheDisabled        : 1;  // 0 = Cached, 1=Non-Cached
  53     UINT64    Accessed             : 1;  // 0 = Not accessed, 1 = Accessed (set by CPU)
  54     UINT64    Reserved             : 1;  // Reserved
  55     UINT64    MustBeZero           : 2;  // Must Be Zero
  56     UINT64    Available            : 3;  // Available for use by system software
  57     UINT64    PageTableBaseAddress : 40; // Page Table Base Address
  58     UINT64    AvabilableHigh       : 11; // Available for use by system software
  59     UINT64    Nx                   : 1;  // No Execute bit
  60   } Bits;
  61   UINT64    Uint64;
  62 } PAGE_MAP_AND_DIRECTORY_POINTER;
  63
  64 //
  65 // Page Table Entry 2MB
  66 //
  67 typedef union {
  68   struct {
  69     UINT64    Present              : 1;  // 0 = Not present in memory, 1 = Present in memory
  70     UINT64    ReadWrite            : 1;  // 0 = Read-Only, 1= Read/Write
  71     UINT64    UserSupervisor       : 1;  // 0 = Supervisor, 1=User
  72     UINT64    WriteThrough         : 1;  // 0 = Write-Back caching, 1=Write-Through caching
  73     UINT64    CacheDisabled        : 1;  // 0 = Cached, 1=Non-Cached
  74     UINT64    Accessed             : 1;  // 0 = Not accessed, 1 = Accessed (set by CPU)
  75     UINT64    Dirty                : 1;  // 0 = Not Dirty, 1 = written by processor on access to page
  76     UINT64    MustBe1              : 1;  // Must be 1
  77     UINT64    Global               : 1;  // 0 = Not global page, 1 = global page TLB not cleared on CR3 write
  78     UINT64    Available            : 3;  // Available for use by system software
  79     UINT64    PAT                  : 1;  //
  80     UINT64    MustBeZero           : 8;  // Must be zero;
  81     UINT64    PageTableBaseAddress : 31; // Page Table Base Address
  82     UINT64    AvabilableHigh       : 11; // Available for use by system software
  83     UINT64    Nx                   : 1;  // 0 = Execute Code, 1 = No Code Execution
  84   } Bits;
  85   UINT64    Uint64;
  86 } PAGE_TABLE_ENTRY;
  87
  88 //
  89 // Page Table Entry 1GB
  90 //
  91 typedef union {
  92   struct {
  93     UINT64    Present              : 1;  // 0 = Not present in memory, 1 = Present in memory
  94     UINT64    ReadWrite            : 1;  // 0 = Read-Only, 1= Read/Write
  95     UINT64    UserSupervisor       : 1;  // 0 = Supervisor, 1=User
  96     UINT64    WriteThrough         : 1;  // 0 = Write-Back caching, 1=Write-Through caching
  97     UINT64    CacheDisabled        : 1;  // 0 = Cached, 1=Non-Cached
  98     UINT64    Accessed             : 1;  // 0 = Not accessed, 1 = Accessed (set by CPU)
  99     UINT64    Dirty                : 1;  // 0 = Not Dirty, 1 = written by processor on access to page
 100     UINT64    MustBe1              : 1;  // Must be 1
 101     UINT64    Global               : 1;  // 0 = Not global page, 1 = global page TLB not cleared on CR3 write
 102     UINT64    Available            : 3;  // Available for use by system software
 103     UINT64    PAT                  : 1;  //
 104     UINT64    MustBeZero           : 17; // Must be zero;
 105     UINT64    PageTableBaseAddress : 22; // Page Table Base Address
 106     UINT64    AvabilableHigh       : 11; // Available for use by system software
 107     UINT64    Nx                   : 1;  // 0 = Execute Code, 1 = No Code Execution
 108   } Bits;
 109   UINT64    Uint64;
 110 } PAGE_TABLE_1G_ENTRY;
 111
 112   #pragma pack()
 113
 114 typedef
 115 EFI_STATUS
 116 (*COALESCE_ENTRY) (
 117   SWITCH_32_TO_64_CONTEXT  *EntrypointContext,
 118   SWITCH_64_TO_32_CONTEXT  *ReturnContext
 119   );
 120
 121 #endif
 122
 123 #endif