2 Support for the latest PCI standard.
4 Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
5 (C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>
6 This program and the accompanying materials
7 are licensed and made available under the terms and conditions of the BSD License
8 which accompanies this distribution. The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
16 #ifndef _PCIEXPRESS21_H_
17 #define _PCIEXPRESS21_H_
19 #include <IndustryStandard/Pci30.h>
23 /// PCI Express Capability Structure
28 UINT16 DevicePortType
: 4;
29 UINT16 SlotImplemented
: 1;
30 UINT16 InterruptMessageNumber
: 5;
35 } PCI_REG_PCIE_CAPABILITY
;
37 #define PCIE_DEVICE_PORT_TYPE_PCIE_ENDPOINT 0
38 #define PCIE_DEVICE_PORT_TYPE_LEGACY_PCIE_ENDPOINT 1
39 #define PCIE_DEVICE_PORT_TYPE_ROOT_PORT 4
40 #define PCIE_DEVICE_PORT_TYPE_UPSTREAM_PORT 5
41 #define PCIE_DEVICE_PORT_TYPE_DOWNSTREAM_PORT 6
42 #define PCIE_DEVICE_PORT_TYPE_PCIE_TO_PCI_BRIDGE 7
43 #define PCIE_DEVICE_PORT_TYPE_PCI_TO_PCIE_BRIDGE 8
44 #define PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX_INTEGRATED_ENDPOINT 9
45 #define PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX_EVENT_COLLECTOR 10
49 UINT32 MaxPayloadSize
: 3;
50 UINT32 PhantomFunctions
: 2;
51 UINT32 ExtendedTagField
: 1;
52 UINT32 EndpointL0sAcceptableLatency
: 3;
53 UINT32 EndpointL1AcceptableLatency
: 3;
55 UINT32 RoleBasedErrorReporting
: 1;
57 UINT32 CapturedSlotPowerLimitValue
: 8;
58 UINT32 CapturedSlotPowerLimitScale
: 2;
59 UINT32 FunctionLevelReset
: 1;
63 } PCI_REG_PCIE_DEVICE_CAPABILITY
;
67 UINT16 CorrectableError
: 1;
68 UINT16 NonFatalError
: 1;
69 UINT16 FatalError
: 1;
70 UINT16 UnsupportedRequest
: 1;
71 UINT16 RelaxedOrdering
: 1;
72 UINT16 MaxPayloadSize
: 3;
73 UINT16 ExtendedTagField
: 1;
74 UINT16 PhantomFunctions
: 1;
77 UINT16 MaxReadRequestSize
: 3;
78 UINT16 BridgeConfigurationRetryOrFunctionLevelReset
: 1;
81 } PCI_REG_PCIE_DEVICE_CONTROL
;
85 UINT16 CorrectableError
: 1;
86 UINT16 NonFatalError
: 1;
87 UINT16 FatalError
: 1;
88 UINT16 UnsupportedRequest
: 1;
90 UINT16 TransactionsPending
: 1;
94 } PCI_REG_PCIE_DEVICE_STATUS
;
98 UINT32 MaxLinkSpeed
: 4;
99 UINT32 MaxLinkWidth
: 6;
101 UINT32 L0sExitLatency
: 3;
102 UINT32 L1ExitLatency
: 3;
103 UINT32 ClockPowerManagement
: 1;
104 UINT32 SurpriseDownError
: 1;
105 UINT32 DataLinkLayerLinkActive
: 1;
106 UINT32 LinkBandwidthNotification
: 1;
107 UINT32 AspmOptionalityCompliance
: 1;
109 UINT32 PortNumber
: 8;
112 } PCI_REG_PCIE_LINK_CAPABILITY
;
114 #define PCIE_LINK_ASPM_L0S BIT0
115 #define PCIE_LINK_ASPM_L1 BIT1
119 UINT16 AspmControl
: 2;
121 UINT16 ReadCompletionBoundary
: 1;
122 UINT16 LinkDisable
: 1;
123 UINT16 RetrainLink
: 1;
124 UINT16 CommonClockConfiguration
: 1;
125 UINT16 ExtendedSynch
: 1;
126 UINT16 ClockPowerManagement
: 1;
127 UINT16 HardwareAutonomousWidthDisable
: 1;
128 UINT16 LinkBandwidthManagementInterrupt
: 1;
129 UINT16 LinkAutonomousBandwidthInterrupt
: 1;
132 } PCI_REG_PCIE_LINK_CONTROL
;
136 UINT16 CurrentLinkSpeed
: 4;
137 UINT16 NegotiatedLinkWidth
: 6;
138 UINT16 Undefined
: 1;
139 UINT16 LinkTraining
: 1;
140 UINT16 SlotClockConfiguration
: 1;
141 UINT16 DataLinkLayerLinkActive
: 1;
142 UINT16 LinkBandwidthManagement
: 1;
143 UINT16 LinkAutonomousBandwidth
: 1;
146 } PCI_REG_PCIE_LINK_STATUS
;
150 UINT32 AttentionButton
: 1;
151 UINT32 PowerController
: 1;
152 UINT32 MrlSensor
: 1;
153 UINT32 AttentionIndicator
: 1;
154 UINT32 PowerIndicator
: 1;
155 UINT32 HotPlugSurprise
: 1;
156 UINT32 HotPlugCapable
: 1;
157 UINT32 SlotPowerLimitValue
: 8;
158 UINT32 SlotPowerLimitScale
: 2;
159 UINT32 ElectromechanicalInterlock
: 1;
160 UINT32 NoCommandCompleted
: 1;
161 UINT32 PhysicalSlotNumber
: 13;
164 } PCI_REG_PCIE_SLOT_CAPABILITY
;
168 UINT32 AttentionButtonPressed
: 1;
169 UINT32 PowerFaultDetected
: 1;
170 UINT32 MrlSensorChanged
: 1;
171 UINT32 PresenceDetectChanged
: 1;
172 UINT32 CommandCompletedInterrupt
: 1;
173 UINT32 HotPlugInterrupt
: 1;
174 UINT32 AttentionIndicator
: 2;
175 UINT32 PowerIndicator
: 2;
176 UINT32 PowerController
: 1;
177 UINT32 ElectromechanicalInterlock
: 1;
178 UINT32 DataLinkLayerStateChanged
: 1;
182 } PCI_REG_PCIE_SLOT_CONTROL
;
186 UINT16 AttentionButtonPressed
: 1;
187 UINT16 PowerFaultDetected
: 1;
188 UINT16 MrlSensorChanged
: 1;
189 UINT16 PresenceDetectChanged
: 1;
190 UINT16 CommandCompleted
: 1;
191 UINT16 MrlSensor
: 1;
192 UINT16 PresenceDetect
: 1;
193 UINT16 ElectromechanicalInterlock
: 1;
194 UINT16 DataLinkLayerStateChanged
: 1;
198 } PCI_REG_PCIE_SLOT_STATUS
;
202 UINT16 SystemErrorOnCorrectableError
: 1;
203 UINT16 SystemErrorOnNonFatalError
: 1;
204 UINT16 SystemErrorOnFatalError
: 1;
205 UINT16 PmeInterrupt
: 1;
206 UINT16 CrsSoftwareVisibility
: 1;
207 UINT16 Reserved
: 11;
210 } PCI_REG_PCIE_ROOT_CONTROL
;
214 UINT16 CrsSoftwareVisibility
: 1;
215 UINT16 Reserved
: 15;
218 } PCI_REG_PCIE_ROOT_CAPABILITY
;
222 UINT32 PmeRequesterId
: 16;
223 UINT32 PmeStatus
: 1;
224 UINT32 PmePending
: 1;
225 UINT32 Reserved
: 14;
228 } PCI_REG_PCIE_ROOT_STATUS
;
232 UINT32 CompletionTimeoutRanges
: 4;
233 UINT32 CompletionTimeoutDisable
: 1;
234 UINT32 AriForwarding
: 1;
235 UINT32 AtomicOpRouting
: 1;
236 UINT32 AtomicOp32Completer
: 1;
237 UINT32 AtomicOp64Completer
: 1;
238 UINT32 Cas128Completer
: 1;
239 UINT32 NoRoEnabledPrPrPassing
: 1;
240 UINT32 LtrMechanism
: 1;
241 UINT32 TphCompleter
: 2;
244 UINT32 ExtendedFmtField
: 1;
245 UINT32 EndEndTlpPrefix
: 1;
246 UINT32 MaxEndEndTlpPrefixes
: 2;
247 UINT32 Reserved2
: 8;
250 } PCI_REG_PCIE_DEVICE_CAPABILITY2
;
252 #define PCIE_DEVICE_CAPABILITY_OBFF_MESSAGE BIT0
253 #define PCIE_DEVICE_CAPABILITY_OBFF_WAKE BIT1
257 UINT16 CompletionTimeoutValue
: 4;
258 UINT16 CompletionTimeoutDisable
: 1;
259 UINT16 AriForwarding
: 1;
260 UINT16 AtomicOpRequester
: 1;
261 UINT16 AtomicOpEgressBlocking
: 1;
262 UINT16 IdoRequest
: 1;
263 UINT16 IdoCompletion
: 1;
264 UINT16 LtrMechanism
: 2;
267 UINT16 EndEndTlpPrefixBlocking
: 1;
270 } PCI_REG_PCIE_DEVICE_CONTROL2
;
272 #define PCIE_COMPLETION_TIMEOUT_50US_50MS 0
273 #define PCIE_COMPLETION_TIMEOUT_50US_100US 1
274 #define PCIE_COMPLETION_TIMEOUT_1MS_10MS 2
275 #define PCIE_COMPLETION_TIMEOUT_16MS_55MS 5
276 #define PCIE_COMPLETION_TIMEOUT_65MS_210MS 6
277 #define PCIE_COMPLETION_TIMEOUT_260MS_900MS 9
278 #define PCIE_COMPLETION_TIMEOUT_1S_3_5S 10
279 #define PCIE_COMPLETION_TIMEOUT_4S_13S 13
280 #define PCIE_COMPLETION_TIMEOUT_17S_64S 14
282 #define PCIE_DEVICE_CONTROL_OBFF_DISABLED 0
283 #define PCIE_DEVICE_CONTROL_OBFF_MESSAGE_A 1
284 #define PCIE_DEVICE_CONTROL_OBFF_MESSAGE_B 2
285 #define PCIE_DEVICE_CONTROL_OBFF_WAKE 3
290 UINT32 LinkSpeedsVector
: 7;
291 UINT32 Crosslink
: 1;
292 UINT32 Reserved2
: 23;
295 } PCI_REG_PCIE_LINK_CAPABILITY2
;
299 UINT16 TargetLinkSpeed
: 4;
300 UINT16 EnterCompliance
: 1;
301 UINT16 HardwareAutonomousSpeedDisable
: 1;
302 UINT16 SelectableDeemphasis
: 1;
303 UINT16 TransmitMargin
: 3;
304 UINT16 EnterModifiedCompliance
: 1;
305 UINT16 ComplianceSos
: 1;
306 UINT16 CompliancePresetDeemphasis
: 4;
309 } PCI_REG_PCIE_LINK_CONTROL2
;
313 UINT16 CurrentDeemphasisLevel
: 1;
314 UINT16 EqualizationComplete
: 1;
315 UINT16 EqualizationPhase1Successful
: 1;
316 UINT16 EqualizationPhase2Successful
: 1;
317 UINT16 EqualizationPhase3Successful
: 1;
318 UINT16 LinkEqualizationRequest
: 1;
319 UINT16 Reserved
: 10;
322 } PCI_REG_PCIE_LINK_STATUS2
;
325 EFI_PCI_CAPABILITY_HDR Hdr
;
326 PCI_REG_PCIE_CAPABILITY Capability
;
327 PCI_REG_PCIE_DEVICE_CAPABILITY DeviceCapability
;
328 PCI_REG_PCIE_DEVICE_CONTROL DeviceControl
;
329 PCI_REG_PCIE_DEVICE_STATUS DeviceStatus
;
330 PCI_REG_PCIE_LINK_CAPABILITY LinkCapability
;
331 PCI_REG_PCIE_LINK_CONTROL LinkControl
;
332 PCI_REG_PCIE_LINK_STATUS LinkStatus
;
333 PCI_REG_PCIE_SLOT_CAPABILITY SlotCapability
;
334 PCI_REG_PCIE_SLOT_CONTROL SlotControl
;
335 PCI_REG_PCIE_SLOT_STATUS SlotStatus
;
336 PCI_REG_PCIE_ROOT_CONTROL RootControl
;
337 PCI_REG_PCIE_ROOT_CAPABILITY RootCapability
;
338 PCI_REG_PCIE_ROOT_STATUS RootStatus
;
339 PCI_REG_PCIE_DEVICE_CAPABILITY2 DeviceCapability2
;
340 PCI_REG_PCIE_DEVICE_CONTROL2 DeviceControl2
;
341 UINT16 DeviceStatus2
;
342 PCI_REG_PCIE_LINK_CAPABILITY2 LinkCapability2
;
343 PCI_REG_PCIE_LINK_CONTROL2 LinkControl2
;
344 PCI_REG_PCIE_LINK_STATUS2 LinkStatus2
;
345 UINT32 SlotCapability2
;
348 } PCI_CAPABILITY_PCIEXP
;
350 #define EFI_PCIE_CAPABILITY_BASE_OFFSET 0x100
351 #define EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL_ARI_HIERARCHY 0x10
352 #define EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_OFFSET 0x24
353 #define EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_ARI_FORWARDING 0x20
354 #define EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_OFFSET 0x28
355 #define EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_ARI_FORWARDING 0x20
360 #define EFI_PCIE_CAPABILITY_ID_ARI 0x0E
361 #define EFI_PCIE_CAPABILITY_ID_ATS 0x0F
362 #define EFI_PCIE_CAPABILITY_ID_SRIOV 0x10
363 #define EFI_PCIE_CAPABILITY_ID_MRIOV 0x11
366 UINT32 CapabilityHeader
;
373 UINT8 FunctionDependencyLink
;
375 UINT16 FirstVFOffset
;
379 UINT32 SupportedPageSize
;
380 UINT32 SystemPageSize
;
382 UINT32 VFMigrationStateArrayOffset
;
383 } SR_IOV_CAPABILITY_REGISTER
;
385 #define EFI_PCIE_CAPABILITY_ID_SRIOV_CAPABILITIES 0x04
386 #define EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL 0x08
387 #define EFI_PCIE_CAPABILITY_ID_SRIOV_STATUS 0x0A
388 #define EFI_PCIE_CAPABILITY_ID_SRIOV_INITIALVFS 0x0C
389 #define EFI_PCIE_CAPABILITY_ID_SRIOV_TOTALVFS 0x0E
390 #define EFI_PCIE_CAPABILITY_ID_SRIOV_NUMVFS 0x10
391 #define EFI_PCIE_CAPABILITY_ID_SRIOV_FUNCTION_DEPENDENCY_LINK 0x12
392 #define EFI_PCIE_CAPABILITY_ID_SRIOV_FIRSTVF 0x14
393 #define EFI_PCIE_CAPABILITY_ID_SRIOV_VFSTRIDE 0x16
394 #define EFI_PCIE_CAPABILITY_ID_SRIOV_VFDEVICEID 0x1A
395 #define EFI_PCIE_CAPABILITY_ID_SRIOV_SUPPORTED_PAGE_SIZE 0x1C
396 #define EFI_PCIE_CAPABILITY_ID_SRIOV_SYSTEM_PAGE_SIZE 0x20
397 #define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR0 0x24
398 #define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR1 0x28
399 #define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR2 0x2C
400 #define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR3 0x30
401 #define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR4 0x34
402 #define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR5 0x38
403 #define EFI_PCIE_CAPABILITY_ID_SRIOV_VF_MIGRATION_STATE 0x3C
406 UINT32 CapabilityId
:16;
407 UINT32 CapabilityVersion
:4;
408 UINT32 NextCapabilityOffset
:12;
409 } PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER
;
411 #define PCI_EXP_EXT_HDR PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER
413 #define PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_ID 0x0001
414 #define PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_VER1 0x1
415 #define PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_VER2 0x2
419 UINT32 Undefined
: 1;
421 UINT32 DataLinkProtocolError
: 1;
422 UINT32 SurpriseDownError
: 1;
423 UINT32 Reserved2
: 6;
424 UINT32 PoisonedTlp
: 1;
425 UINT32 FlowControlProtocolError
: 1;
426 UINT32 CompletionTimeout
: 1;
427 UINT32 CompleterAbort
: 1;
428 UINT32 UnexpectedCompletion
: 1;
429 UINT32 ReceiverOverflow
: 1;
430 UINT32 MalformedTlp
: 1;
431 UINT32 EcrcError
: 1;
432 UINT32 UnsupportedRequestError
: 1;
433 UINT32 AcsVoilation
: 1;
434 UINT32 UncorrectableInternalError
: 1;
435 UINT32 McBlockedTlp
: 1;
436 UINT32 AtomicOpEgressBlocked
: 1;
437 UINT32 TlpPrefixBlockedError
: 1;
438 UINT32 Reserved3
: 6;
441 } PCI_EXPRESS_REG_UNCORRECTABLE_ERROR
;
444 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header
;
445 PCI_EXPRESS_REG_UNCORRECTABLE_ERROR UncorrectableErrorStatus
;
446 PCI_EXPRESS_REG_UNCORRECTABLE_ERROR UncorrectableErrorMask
;
447 PCI_EXPRESS_REG_UNCORRECTABLE_ERROR UncorrectableErrorSeverity
;
448 UINT32 CorrectableErrorStatus
;
449 UINT32 CorrectableErrorMask
;
450 UINT32 AdvancedErrorCapabilitiesAndControl
;
452 UINT32 RootErrorCommand
;
453 UINT32 RootErrorStatus
;
454 UINT16 ErrorSourceIdentification
;
455 UINT16 CorrectableErrorSourceIdentification
;
456 UINT32 TlpPrefixLog
[4];
457 } PCI_EXPRESS_EXTENDED_CAPABILITIES_ADVANCED_ERROR_REPORTING
;
459 #define PCI_EXPRESS_EXTENDED_CAPABILITY_VIRTUAL_CHANNEL_ID 0x0002
460 #define PCI_EXPRESS_EXTENDED_CAPABILITY_VIRTUAL_CHANNEL_MFVC 0x0009
461 #define PCI_EXPRESS_EXTENDED_CAPABILITY_VIRTUAL_CHANNEL_VER1 0x1
464 UINT32 VcResourceCapability
:24;
465 UINT32 PortArbTableOffset
:8;
466 UINT32 VcResourceControl
;
468 UINT16 VcResourceStatus
;
469 } PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_VC
;
472 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header
;
473 UINT32 ExtendedVcCount
:3;
474 UINT32 PortVcCapability1
:29;
475 UINT32 PortVcCapability2
:24;
476 UINT32 VcArbTableOffset
:8;
477 UINT16 PortVcControl
;
479 PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_VC Capability
[1];
480 } PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY
;
482 #define PCI_EXPRESS_EXTENDED_CAPABILITY_SERIAL_NUMBER_ID 0x0003
483 #define PCI_EXPRESS_EXTENDED_CAPABILITY_SERIAL_NUMBER_VER1 0x1
486 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header
;
488 } PCI_EXPRESS_EXTENDED_CAPABILITIES_SERIAL_NUMBER
;
490 #define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_ID 0x0005
491 #define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_VER1 0x1
494 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header
;
495 UINT32 ElementSelfDescription
;
498 } PCI_EXPRESS_EXTENDED_CAPABILITIES_LINK_DECLARATION
;
500 #define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_GET_LINK_COUNT(LINK_DECLARATION) (UINT8)(((LINK_DECLARATION->ElementSelfDescription)&0x0000ff00)>>8)
502 #define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_CONTROL_ID 0x0006
503 #define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_CONTROL_VER1 0x1
506 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header
;
507 UINT32 RootComplexLinkCapabilities
;
508 UINT16 RootComplexLinkControl
;
509 UINT16 RootComplexLinkStatus
;
510 } PCI_EXPRESS_EXTENDED_CAPABILITIES_INTERNAL_LINK_CONTROL
;
512 #define PCI_EXPRESS_EXTENDED_CAPABILITY_POWER_BUDGETING_ID 0x0004
513 #define PCI_EXPRESS_EXTENDED_CAPABILITY_POWER_BUDGETING_VER1 0x1
516 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header
;
520 UINT32 PowerBudgetCapability
:1;
523 } PCI_EXPRESS_EXTENDED_CAPABILITIES_POWER_BUDGETING
;
525 #define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_ID 0x000D
526 #define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_VER1 0x1
529 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header
;
530 UINT16 AcsCapability
;
532 UINT8 EgressControlVectorArray
[1];
533 } PCI_EXPRESS_EXTENDED_CAPABILITIES_ACS_EXTENDED
;
535 #define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_GET_EGRES_CONTROL(ACS_EXTENDED) (UINT8)(((ACS_EXTENDED->AcsCapability)&0x00000020))
536 #define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_GET_EGRES_VECTOR_SIZE(ACS_EXTENDED) (UINT8)(((ACS_EXTENDED->AcsCapability)&0x0000FF00))
538 #define PCI_EXPRESS_EXTENDED_CAPABILITY_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION_ID 0x0007
539 #define PCI_EXPRESS_EXTENDED_CAPABILITY_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION_VER1 0x1
542 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header
;
543 UINT32 AssociationBitmap
;
544 } PCI_EXPRESS_EXTENDED_CAPABILITIES_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION
;
546 #define PCI_EXPRESS_EXTENDED_CAPABILITY_MULTI_FUNCTION_VIRTUAL_CHANNEL_ID 0x0008
547 #define PCI_EXPRESS_EXTENDED_CAPABILITY_MULTI_FUNCTION_VIRTUAL_CHANNEL_VER1 0x1
549 typedef PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTI_FUNCTION_VIRTUAL_CHANNEL_CAPABILITY
;
551 #define PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_ID 0x000B
552 #define PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_VER1 0x1
555 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header
;
556 UINT32 VendorSpecificHeader
;
557 UINT8 VendorSpecific
[1];
558 } PCI_EXPRESS_EXTENDED_CAPABILITIES_VENDOR_SPECIFIC
;
560 #define PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_GET_SIZE(VENDOR) (UINT16)(((VENDOR->VendorSpecificHeader)&0xFFF00000)>>20)
562 #define PCI_EXPRESS_EXTENDED_CAPABILITY_RCRB_HEADER_ID 0x000A
563 #define PCI_EXPRESS_EXTENDED_CAPABILITY_RCRB_HEADER_VER1 0x1
566 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header
;
569 UINT32 RcrbCapabilities
;
572 } PCI_EXPRESS_EXTENDED_CAPABILITIES_RCRB_HEADER
;
574 #define PCI_EXPRESS_EXTENDED_CAPABILITY_MULTICAST_ID 0x0012
575 #define PCI_EXPRESS_EXTENDED_CAPABILITY_MULTICAST_VER1 0x1
578 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header
;
579 UINT16 MultiCastCapability
;
580 UINT16 MulticastControl
;
581 UINT64 McBaseAddress
;
582 UINT64 McReceiveAddress
;
584 UINT64 McBlockUntranslated
;
586 } PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTICAST
;
588 #define PCI_EXPRESS_EXTENDED_CAPABILITY_RESIZABLE_BAR_ID 0x0015
589 #define PCI_EXPRESS_EXTENDED_CAPABILITY_RESIZABLE_BAR_VER1 0x1
592 UINT32 ResizableBarCapability
;
593 UINT16 ResizableBarControl
;
595 } PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY
;
598 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header
;
599 PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY Capability
[1];
600 } PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR
;
602 #define GET_NUMBER_RESIZABLE_BARS(x) (((x->Capability[0].ResizableBarControl) & 0xE0) >> 5)
604 #define PCI_EXPRESS_EXTENDED_CAPABILITY_ARI_CAPABILITY_ID 0x000E
605 #define PCI_EXPRESS_EXTENDED_CAPABILITY_ARI_CAPABILITY_VER1 0x1
608 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header
;
609 UINT16 AriCapability
;
611 } PCI_EXPRESS_EXTENDED_CAPABILITIES_ARI_CAPABILITY
;
613 #define PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_ID 0x0016
614 #define PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_VER1 0x1
617 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header
;
618 UINT32 DpaCapability
;
619 UINT32 DpaLatencyIndicator
;
622 UINT8 DpaPowerAllocationArray
[1];
623 } PCI_EXPRESS_EXTENDED_CAPABILITIES_DYNAMIC_POWER_ALLOCATION
;
625 #define PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_GET_SUBSTATE_MAX(POWER) (UINT16)(((POWER->DpaCapability)&0x0000000F))
628 #define PCI_EXPRESS_EXTENDED_CAPABILITY_LATENCE_TOLERANCE_REPORTING_ID 0x0018
629 #define PCI_EXPRESS_EXTENDED_CAPABILITY_LATENCE_TOLERANCE_REPORTING_VER1 0x1
632 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header
;
633 UINT16 MaxSnoopLatency
;
634 UINT16 MaxNoSnoopLatency
;
635 } PCI_EXPRESS_EXTENDED_CAPABILITIES_LATENCE_TOLERANCE_REPORTING
;
637 #define PCI_EXPRESS_EXTENDED_CAPABILITY_TPH_ID 0x0017
638 #define PCI_EXPRESS_EXTENDED_CAPABILITY_TPH_VER1 0x1
641 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header
;
642 UINT32 TphRequesterCapability
;
643 UINT32 TphRequesterControl
;
644 UINT16 TphStTable
[1];
645 } PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH
;
647 #define GET_TPH_TABLE_SIZE(x) ((x->TphRequesterCapability & 0x7FF0000)>>16) * sizeof(UINT16)