2 Support for the latest PCI standard.
4 Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
5 This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
15 #ifndef _PCIEXPRESS21_H_
16 #define _PCIEXPRESS21_H_
18 #define EFI_PCIE_CAPABILITY_BASE_OFFSET 0x100
19 #define EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL_ARI_HIERARCHY 0x10
20 #define EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_OFFSET 0x24
21 #define EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_ARI_FORWARDING 0x20
22 #define EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_OFFSET 0x28
23 #define EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_ARI_FORWARDING 0x20
28 #define EFI_PCIE_CAPABILITY_ID_ARI 0x0E
29 #define EFI_PCIE_CAPABILITY_ID_ATS 0x0F
30 #define EFI_PCIE_CAPABILITY_ID_SRIOV 0x10
31 #define EFI_PCIE_CAPABILITY_ID_MRIOV 0x11
34 UINT32 CapabilityHeader
;
41 UINT8 FunctionDependencyLink
;
47 UINT32 SupportedPageSize
;
48 UINT32 SystemPageSize
;
50 UINT32 VFMigrationStateArrayOffset
;
51 } SR_IOV_CAPABILITY_REGISTER
;
53 #define EFI_PCIE_CAPABILITY_ID_SRIOV_CAPABILITIES 0x04
54 #define EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL 0x08
55 #define EFI_PCIE_CAPABILITY_ID_SRIOV_STATUS 0x0A
56 #define EFI_PCIE_CAPABILITY_ID_SRIOV_INITIALVFS 0x0C
57 #define EFI_PCIE_CAPABILITY_ID_SRIOV_TOTALVFS 0x0E
58 #define EFI_PCIE_CAPABILITY_ID_SRIOV_NUMVFS 0x10
59 #define EFI_PCIE_CAPABILITY_ID_SRIOV_FUNCTION_DEPENDENCY_LINK 0x12
60 #define EFI_PCIE_CAPABILITY_ID_SRIOV_FIRSTVF 0x14
61 #define EFI_PCIE_CAPABILITY_ID_SRIOV_VFSTRIDE 0x16
62 #define EFI_PCIE_CAPABILITY_ID_SRIOV_VFDEVICEID 0x1A
63 #define EFI_PCIE_CAPABILITY_ID_SRIOV_SUPPORTED_PAGE_SIZE 0x1C
64 #define EFI_PCIE_CAPABILITY_ID_SRIOV_SYSTEM_PAGE_SIZE 0x20
65 #define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR0 0x24
66 #define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR1 0x28
67 #define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR2 0x2C
68 #define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR3 0x30
69 #define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR4 0x34
70 #define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR5 0x38
71 #define EFI_PCIE_CAPABILITY_ID_SRIOV_VF_MIGRATION_STATE 0x3C
74 UINT32 CapabilityId
:16;
75 UINT32 CapabilityVersion
:4;
76 UINT32 NextCapabilityOffset
:12;
77 } PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER
;
79 #define PCI_EXP_EXT_HDR PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER
81 #define PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_ID 0x0001
82 #define PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_VER1 0x1
83 #define PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_VER2 0x2
86 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header
;
87 UINT32 UncorrectableErrorStatus
;
88 UINT32 UncorrectableErrorMask
;
89 UINT32 UncorrectableErrorSeverity
;
90 UINT32 CorrectableErrorStatus
;
91 UINT32 CorrectableErrorMask
;
92 UINT32 AdvancedErrorCapabilitiesAndControl
;
94 UINT32 RootErrorCommand
;
95 UINT32 RootErrorStatus
;
96 UINT16 ErrorSourceIdentification
;
97 UINT16 CorrectableErrorSourceIdentification
;
98 UINT32 TlpPrefixLog
[4];
99 } PCI_EXPRESS_EXTENDED_CAPABILITIES_ADVANCED_ERROR_REPORTING
;
101 #define PCI_EXPRESS_EXTENDED_CAPABILITY_VIRTUAL_CHANNEL_ID 0x0002
102 #define PCI_EXPRESS_EXTENDED_CAPABILITY_VIRTUAL_CHANNEL_MFVC 0x0009
103 #define PCI_EXPRESS_EXTENDED_CAPABILITY_VIRTUAL_CHANNEL_VER1 0x1
106 UINT32 VcResourceCapability
:24;
107 UINT32 PortArbTableOffset
:8;
108 UINT32 VcResourceControl
;
110 UINT16 VcResourceStatus
;
111 } PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_VC
;
114 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header
;
115 UINT32 ExtendedVcCount
:3;
116 UINT32 PortVcCapability1
:29;
117 UINT32 PortVcCapability2
:24;
118 UINT32 VcArbTableOffset
:8;
119 UINT16 PortVcControl
;
121 PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_VC Capability
[1];
122 } PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY
;
124 #define PCI_EXPRESS_EXTENDED_CAPABILITY_SERIAL_NUMBER_ID 0x0003
125 #define PCI_EXPRESS_EXTENDED_CAPABILITY_SERIAL_NUMBER_VER1 0x1
128 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header
;
130 } PCI_EXPRESS_EXTENDED_CAPABILITIES_SERIAL_NUMBER
;
132 #define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_ID 0x0005
133 #define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_VER1 0x1
136 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header
;
137 UINT32 ElementSelfDescription
;
140 } PCI_EXPRESS_EXTENDED_CAPABILITIES_LINK_DECLARATION
;
142 #define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_GET_LINK_COUNT(LINK_DECLARATION) (UINT8)(((LINK_DECLARATION->ElementSelfDescription)&0x0000ff00)>>8)
144 #define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_CONTROL_ID 0x0006
145 #define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_CONTROL_VER1 0x1
148 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header
;
149 UINT32 RootComplexLinkCapabilities
;
150 UINT16 RootComplexLinkControl
;
151 UINT16 RootComplexLinkStatus
;
152 } PCI_EXPRESS_EXTENDED_CAPABILITIES_INTERNAL_LINK_CONTROL
;
154 #define PCI_EXPRESS_EXTENDED_CAPABILITY_POWER_BUDGETING_ID 0x0004
155 #define PCI_EXPRESS_EXTENDED_CAPABILITY_POWER_BUDGETING_VER1 0x1
158 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header
;
162 UINT32 PowerBudgetCapability
:1;
165 } PCI_EXPRESS_EXTENDED_CAPABILITIES_POWER_BUDGETING
;
167 #define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_ID 0x000D
168 #define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_VER1 0x1
171 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header
;
172 UINT16 AcsCapability
;
174 UINT8 EgressControlVectorArray
[1];
175 } PCI_EXPRESS_EXTENDED_CAPABILITIES_ACS_EXTENDED
;
177 #define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_GET_EGRES_CONTROL(ACS_EXTENDED) (UINT8)(((ACS_EXTENDED->AcsCapability)&0x00000020))
178 #define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_GET_EGRES_VECTOR_SIZE(ACS_EXTENDED) (UINT8)(((ACS_EXTENDED->AcsCapability)&0x0000FF00))
180 #define PCI_EXPRESS_EXTENDED_CAPABILITY_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION_ID 0x0007
181 #define PCI_EXPRESS_EXTENDED_CAPABILITY_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION_VER1 0x1
184 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header
;
185 UINT32 AssociationBitmap
;
186 } PCI_EXPRESS_EXTENDED_CAPABILITIES_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION
;
188 #define PCI_EXPRESS_EXTENDED_CAPABILITY_MULTI_FUNCTION_VIRTUAL_CHANNEL_ID 0x0008
189 #define PCI_EXPRESS_EXTENDED_CAPABILITY_MULTI_FUNCTION_VIRTUAL_CHANNEL_VER1 0x1
191 typedef PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTI_FUNCTION_VIRTUAL_CHANNEL_CAPABILITY
;
193 #define PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_ID 0x000B
194 #define PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_VER1 0x1
197 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header
;
198 UINT32 VendorSpecificHeader
;
199 UINT8 VendorSpecific
[1];
200 } PCI_EXPRESS_EXTENDED_CAPABILITIES_VENDOR_SPECIFIC
;
202 #define PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_GET_SIZE(VENDOR) (UINT16)(((VENDOR->VendorSpecificHeader)&0xFFF00000)>>20)
204 #define PCI_EXPRESS_EXTENDED_CAPABILITY_RCRB_HEADER_ID 0x000A
205 #define PCI_EXPRESS_EXTENDED_CAPABILITY_RCRB_HEADER_VER1 0x1
208 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header
;
211 UINT32 RcrbCapabilities
;
214 } PCI_EXPRESS_EXTENDED_CAPABILITIES_RCRB_HEADER
;
216 #define PCI_EXPRESS_EXTENDED_CAPABILITY_MULTICAST_ID 0x0012
217 #define PCI_EXPRESS_EXTENDED_CAPABILITY_MULTICAST_VER1 0x1
220 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header
;
221 UINT16 MultiCastCapability
;
222 UINT16 MulticastControl
;
223 UINT64 McBaseAddress
;
224 UINT64 McReceiveAddress
;
226 UINT64 McBlockUntranslated
;
228 } PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTICAST
;
230 #define PCI_EXPRESS_EXTENDED_CAPABILITY_RESIZABLE_BAR_ID 0x0015
231 #define PCI_EXPRESS_EXTENDED_CAPABILITY_RESIZABLE_BAR_VER1 0x1
234 UINT32 ResizableBarCapability
;
235 UINT16 ResizableBarControl
;
237 } PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY
;
240 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header
;
241 PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY Capability
[1];
242 } PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR
;
244 #define GET_NUMBER_RESIZABLE_BARS(x) (((x->Capability[0].ResizableBarControl) & 0xE0) >> 5)
246 #define PCI_EXPRESS_EXTENDED_CAPABILITY_ARI_CAPABILITY_ID 0x000E
247 #define PCI_EXPRESS_EXTENDED_CAPABILITY_ARI_CAPABILITY_VER1 0x1
250 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header
;
251 UINT16 AriCapability
;
253 } PCI_EXPRESS_EXTENDED_CAPABILITIES_ARI_CAPABILITY
;
255 #define PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_ID 0x0016
256 #define PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_VER1 0x1
259 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header
;
260 UINT32 DpaCapability
;
261 UINT32 DpaLatencyIndicator
;
264 UINT8 DpaPowerAllocationArray
[1];
265 } PCI_EXPRESS_EXTENDED_CAPABILITIES_DYNAMIC_POWER_ALLOCATION
;
267 #define PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_GET_SUBSTATE_MAX(POWER) (UINT16)(((POWER->DpaCapability)&0x0000000F))
270 #define PCI_EXPRESS_EXTENDED_CAPABILITY_LATENCE_TOLERANCE_REPORTING_ID 0x0018
271 #define PCI_EXPRESS_EXTENDED_CAPABILITY_LATENCE_TOLERANCE_REPORTING_VER1 0x1
274 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header
;
275 UINT16 MaxSnoopLatency
;
276 UINT16 MaxNoSnoopLatency
;
277 } PCI_EXPRESS_EXTENDED_CAPABILITIES_LATENCE_TOLERANCE_REPORTING
;
279 #define PCI_EXPRESS_EXTENDED_CAPABILITY_TPH_ID 0x0017
280 #define PCI_EXPRESS_EXTENDED_CAPABILITY_TPH_VER1 0x1
283 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header
;
284 UINT32 TphRequesterCapability
;
285 UINT32 TphRequesterControl
;
286 UINT16 TphStTable
[1];
287 } PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH
;
289 #define GET_TPH_TABLE_SIZE(x) ((x->TphRequesterCapability & 0x7FF0000)>>16) * sizeof(UINT16)