2 Main SAL API's defined in Intel Itanium Processor Family System Abstraction
3 Layer Specification Revision 3.2 (December 2003)
5 Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
6 This program and the accompanying materials are licensed and made available under
7 the terms and conditions of the BSD License that accompanies this distribution.
8 The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php.
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
20 /// SAL return status type
22 typedef INTN EFI_SAL_STATUS
;
25 /// Call completed without error.
27 #define EFI_SAL_SUCCESS ((EFI_SAL_STATUS) 0)
29 /// Call completed without error, but some information was lost due to overflow.
31 #define EFI_SAL_OVERFLOW ((EFI_SAL_STATUS) 1)
33 /// Call completed without error; effect a warm boot of the system to complete the update.
35 #define EFI_SAL_WARM_BOOT_NEEDED ((EFI_SAL_STATUS) 2)
37 /// More information is available for retrieval.
39 #define EFI_SAL_MORE_RECORDS ((EFI_SAL_STATUS) 3)
43 #define EFI_SAL_NOT_IMPLEMENTED ((EFI_SAL_STATUS) - 1)
47 #define EFI_SAL_INVALID_ARGUMENT ((EFI_SAL_STATUS) - 2)
49 /// Call completed without error.
51 #define EFI_SAL_ERROR ((EFI_SAL_STATUS) - 3)
53 /// Virtual address not registered.
55 #define EFI_SAL_VIRTUAL_ADDRESS_ERROR ((EFI_SAL_STATUS) - 4)
57 /// No information available.
59 #define EFI_SAL_NO_INFORMATION ((EFI_SAL_STATUS) - 5)
61 /// Scratch buffer required.
63 #define EFI_SAL_NOT_ENOUGH_SCRATCH ((EFI_SAL_STATUS) - 9)
66 /// Return registers from SAL.
70 /// SAL return status value in r8.
72 EFI_SAL_STATUS Status
;
74 /// SAL returned value in r9.
78 /// SAL returned value in r10.
82 /// SAL returned value in r11.
88 Prototype of SAL procedures.
90 @param FunctionId Functional identifier.
91 The upper 32 bits are ignored and only the lower 32 bits
92 are used. The following functional identifiers are defined:
93 0x01XXXXXX - Architected SAL functional group.
94 0x02XXXXXX to 0x03XXXXXX - OEM SAL functional group. Each OEM is
95 allowed to use the entire range in the 0x02XXXXXX to 0x03XXXXXX range.
96 0x04XXXXXX to 0xFFFFFFFF - Reserved.
97 @param Arg1 The first parameter of the architected/OEM specific SAL functions.
98 @param Arg2 The second parameter of the architected/OEM specific SAL functions.
99 @param Arg3 The third parameter passed to the ESAL function based.
100 @param Arg4 The fourth parameter passed to the ESAL function based.
101 @param Arg5 The fifth parameter passed to the ESAL function based.
102 @param Arg6 The sixth parameter passed to the ESAL function.
103 @param Arg7 The seventh parameter passed to the ESAL function based.
105 @return r8 Return status: positive number indicates successful,
106 negative number indicates failure.
107 r9 Other return parameter in r9.
108 r10 Other return parameter in r10.
109 r11 Other return parameter in r11.
115 IN UINT64 FunctionId
,
126 // SAL Procedure FunctionId definition
130 /// Register software code locations with SAL.
132 #define EFI_SAL_SET_VECTORS 0x01000000
134 /// Return Machine State information obtained by SAL.
136 #define EFI_SAL_GET_STATE_INFO 0x01000001
138 /// Obtain size of Machine State information.
140 #define EFI_SAL_GET_STATE_INFO_SIZE 0x01000002
142 /// Clear Machine State information.
144 #define EFI_SAL_CLEAR_STATE_INFO 0x01000003
146 /// Cause the processor to go into a spin loop within SAL.
148 #define EFI_SAL_MC_RENDEZ 0x01000004
150 /// Register the machine check interface layer with SAL.
152 #define EFI_SAL_MC_SET_PARAMS 0x01000005
154 /// Register the physical addresses of locations needed by SAL.
156 #define EFI_SAL_REGISTER_PHYSICAL_ADDR 0x01000006
158 /// Flush the instruction or data caches.
160 #define EFI_SAL_CACHE_FLUSH 0x01000008
162 /// Initialize the instruction and data caches.
164 #define EFI_SAL_CACHE_INIT 0x01000009
166 /// Read from the PCI configuration space.
168 #define EFI_SAL_PCI_CONFIG_READ 0x01000010
170 /// Write to the PCI configuration space.
172 #define EFI_SAL_PCI_CONFIG_WRITE 0x01000011
174 /// Return the base frequency of the platform.
176 #define EFI_SAL_FREQ_BASE 0x01000012
178 /// Returns information on the physical processor mapping within the platform.
180 #define EFI_SAL_PHYSICAL_ID_INFO 0x01000013
182 /// Update the contents of firmware blocks.
184 #define EFI_SAL_UPDATE_PAL 0x01000020
186 #define EFI_SAL_FUNCTION_ID_MASK 0x0000ffff
187 #define EFI_SAL_MAX_SAL_FUNCTION_ID 0x00000021
190 // SAL Procedure parameter definitions
191 // Not much point in using typedefs or enums because all params
192 // are UINT64 and the entry point is common
196 // Parameter of EFI_SAL_SET_VECTORS
200 #define EFI_SAL_SET_MCA_VECTOR 0x0
201 #define EFI_SAL_SET_INIT_VECTOR 0x1
202 #define EFI_SAL_SET_BOOT_RENDEZ_VECTOR 0x2
204 /// The format of a length_cs_n argument.
208 UINT64 ChecksumValid
: 1;
209 UINT64 Reserved1
: 7;
210 UINT64 ByteChecksum
: 8;
211 UINT64 Reserved2
: 16;
212 } SAL_SET_VECTORS_CS_N
;
215 // Parameter of EFI_SAL_GET_STATE_INFO, EFI_SAL_GET_STATE_INFO_SIZE, and EFI_SAL_CLEAR_STATE_INFO
217 // Type of information
219 #define EFI_SAL_MCA_STATE_INFO 0x0
220 #define EFI_SAL_INIT_STATE_INFO 0x1
221 #define EFI_SAL_CMC_STATE_INFO 0x2
222 #define EFI_SAL_CP_STATE_INFO 0x3
225 // Parameter of EFI_SAL_MC_SET_PARAMS
227 // Unsigned 64-bit integer value for the parameter type of the machine check interface
229 #define EFI_SAL_MC_SET_RENDEZ_PARAM 0x1
230 #define EFI_SAL_MC_SET_WAKEUP_PARAM 0x2
231 #define EFI_SAL_MC_SET_CPE_PARAM 0x3
233 // Unsigned 64-bit integer value indicating whether interrupt vector or
234 // memory address is specified
236 #define EFI_SAL_MC_SET_INTR_PARAM 0x1
237 #define EFI_SAL_MC_SET_MEM_PARAM 0x2
240 // Parameter of EFI_SAL_REGISTER_PAL_PHYSICAL_ADDR
242 // The encoded value of the entity whose physical address is registered
244 #define EFI_SAL_REGISTER_PAL_ADDR 0x0
247 // Parameter of EFI_SAL_CACHE_FLUSH
249 // Unsigned 64-bit integer denoting type of cache flush operation
251 #define EFI_SAL_FLUSH_I_CACHE 0x01
252 #define EFI_SAL_FLUSH_D_CACHE 0x02
253 #define EFI_SAL_FLUSH_BOTH_CACHE 0x03
254 #define EFI_SAL_FLUSH_MAKE_COHERENT 0x04
257 // Parameter of EFI_SAL_PCI_CONFIG_READ and EFI_SAL_PCI_CONFIG_WRITE
261 #define EFI_SAL_PCI_CONFIG_ONE_BYTE 0x1
262 #define EFI_SAL_PCI_CONFIG_TWO_BYTES 0x2
263 #define EFI_SAL_PCI_CONFIG_FOUR_BYTES 0x4
265 // The type of PCI configuration address
267 #define EFI_SAL_PCI_COMPATIBLE_ADDRESS 0x0
268 #define EFI_SAL_PCI_EXTENDED_REGISTER_ADDRESS 0x1
270 /// The format of PCI Compatible Address.
278 UINT64 Reserved
: 32;
281 /// The format of Extended Register Address.
285 UINT64 ExtendedRegister
: 4;
290 UINT64 Reserved
: 20;
291 } SAL_PCI_EXTENDED_REGISTER_ADDRESS
;
294 // Parameter of EFI_SAL_FREQ_BASE
296 // Unsigned 64-bit integer specifying the type of clock source
298 #define EFI_SAL_CPU_INPUT_FREQ_BASE 0x0
299 #define EFI_SAL_PLATFORM_IT_FREQ_BASE 0x1
300 #define EFI_SAL_PLATFORM_RTC_FREQ_BASE 0x2
303 // Parameter and return value of EFI_SAL_UPDATE_PAL
305 // Return parameter provides additional information on the
306 // failure when the status field contains a value of -3,
309 #define EFI_SAL_UPDATE_BAD_PAL_VERSION ((UINT64) -1)
310 #define EFI_SAL_UPDATE_PAL_AUTH_FAIL ((UINT64) -2)
311 #define EFI_SAL_UPDATE_PAL_BAD_TYPE ((UINT64) -3)
312 #define EFI_SAL_UPDATE_PAL_READONLY ((UINT64) -4)
313 #define EFI_SAL_UPDATE_PAL_WRITE_FAIL ((UINT64) -10)
314 #define EFI_SAL_UPDATE_PAL_ERASE_FAIL ((UINT64) -11)
315 #define EFI_SAL_UPDATE_PAL_READ_FAIL ((UINT64) -12)
316 #define EFI_SAL_UPDATE_PAL_CANT_FIT ((UINT64) -13)
318 /// 64-byte header of update data block.
328 } SAL_UPDATE_PAL_DATA_BLOCK
;
330 /// Data structure pointed by the parameter param_buf.
331 /// It is a 16-byte aligned data structure in memory with a length of 32 bytes
332 /// that describes the new firmware. This information is organized in the form
333 /// of a linked list with each element describing one firmware component.
335 typedef struct _SAL_UPDATE_PAL_INFO_BLOCK
{
336 struct _SAL_UPDATE_PAL_INFO_BLOCK
*Next
;
337 struct SAL_UPDATE_PAL_DATA_BLOCK
*DataBlock
;
340 } SAL_UPDATE_PAL_INFO_BLOCK
;
343 /// SAL System Table Definitions.
348 /// The ASCII string representation of "SST_" that confirms the presence of the table.
352 /// The length of the entire table in bytes, starting from offset zero and including the
353 /// header and all entries indicated by the EntryCount field.
357 /// The revision number of the Itanium Processor Family System Abstraction Layer
358 /// Specification supported by the SAL implementation, in binary coded decimal (BCD) format.
362 /// The number of entries in the variable portion of the table.
366 /// A modulo checksum of the entire table and the entries following this table.
370 /// Unused, must be zero.
374 /// Version Number of the SAL_A firmware implementation in BCD format.
378 /// Version Number of the SAL_B firmware implementation in BCD format.
382 /// An ASCII identification string which uniquely identifies the manufacturer
383 /// of the system hardware.
387 /// An ASCII identification string which uniquely identifies a family of
388 /// compatible products from the manufacturer.
392 /// Unused, must be zero.
395 } SAL_SYSTEM_TABLE_HEADER
;
397 #define EFI_SAL_ST_HEADER_SIGNATURE "SST_"
398 #define EFI_SAL_REVISION 0x0320
402 #define EFI_SAL_ST_ENTRY_POINT 0
403 #define EFI_SAL_ST_MEMORY_DESCRIPTOR 1
404 #define EFI_SAL_ST_PLATFORM_FEATURES 2
405 #define EFI_SAL_ST_TR_USAGE 3
406 #define EFI_SAL_ST_PTC 4
407 #define EFI_SAL_ST_AP_WAKEUP 5
410 // SAL System Type Sizes
412 #define EFI_SAL_ST_ENTRY_POINT_SIZE 48
413 #define EFI_SAL_ST_MEMORY_DESCRIPTOR_SIZE 32
414 #define EFI_SAL_ST_PLATFORM_FEATURES_SIZE 16
415 #define EFI_SAL_ST_TR_USAGE_SIZE 32
416 #define EFI_SAL_ST_PTC_SIZE 16
417 #define EFI_SAL_ST_AP_WAKEUP_SIZE 16
420 /// Format of Entrypoint Descriptor Entry.
423 UINT8 Type
; ///< Type here should be 0.
427 UINT64 SalGlobalDataPointer
;
429 } SAL_ST_ENTRY_POINT_DESCRIPTOR
;
432 /// Format of Platform Features Descriptor Entry.
435 UINT8 Type
; ///< Type here should be 2.
436 UINT8 PlatformFeatures
;
438 } SAL_ST_PLATFORM_FEATURES
;
441 // Value of Platform Feature List
443 #define SAL_PLAT_FEAT_BUS_LOCK 0x01
444 #define SAL_PLAT_FEAT_PLAT_IPI_HINT 0x02
445 #define SAL_PLAT_FEAT_PROC_IPI_HINT 0x04
448 /// Format of Translation Register Descriptor Entry.
451 UINT8 Type
; ///< Type here should be 3.
455 UINT64 VirtualAddress
;
456 UINT64 EncodedPageSize
;
458 } SAL_ST_TR_DECRIPTOR
;
461 // Type of Translation Register
463 #define EFI_SAL_ST_TR_USAGE_INSTRUCTION 00
464 #define EFI_SAL_ST_TR_USAGE_DATA 01
467 /// Definition of Coherence Domain Information.
470 UINT64 NumberOfProcessors
;
471 UINT64 LocalIDRegister
;
472 } SAL_COHERENCE_DOMAIN_INFO
;
475 /// Format of Purge Translation Cache Coherence Domain Entry.
478 UINT8 Type
; ///< Type here should be 4.
480 UINT32 NumberOfDomains
;
481 SAL_COHERENCE_DOMAIN_INFO
*DomainInformation
;
482 } SAL_ST_CACHE_COHERENCE_DECRIPTOR
;
485 /// Format of Application Processor Wake-Up Descriptor Entry.
488 UINT8 Type
; ///< Type here should be 5.
491 UINT64 ExternalInterruptVector
;
492 } SAL_ST_AP_WAKEUP_DECRIPTOR
;
495 /// Format of Firmware Interface Table (FIT) Entry.
503 UINT8 CheckSumValid
: 1;
509 #define EFI_SAL_FIT_FIT_HEADER_TYPE 0x00
510 #define EFI_SAL_FIT_PAL_B_TYPE 0x01
512 // Type from 0x02 to 0x0D is reserved.
514 #define EFI_SAL_FIT_PROCESSOR_SPECIFIC_PAL_A_TYPE 0x0E
515 #define EFI_SAL_FIT_PAL_A_TYPE 0x0F
517 // OEM-defined type range is from 0x10 to 0x7E.
518 // Here we defined the PEI_CORE type as 0x10
520 #define EFI_SAL_FIT_PEI_CORE_TYPE 0x10
521 #define EFI_SAL_FIT_UNUSED_TYPE 0x7F
526 #define EFI_SAL_FIT_ENTRY_PTR (0x100000000 - 32) // 4GB - 24
527 #define EFI_SAL_FIT_PALA_ENTRY (0x100000000 - 48) // 4GB - 32
528 #define EFI_SAL_FIT_PALB_TYPE 01
531 // Following definitions are for Error Record Structure
535 /// Format of TimeStamp field in Record Header.
548 /// Definition of Record Header.
554 UINT8 ValidationBits
;
556 SAL_TIME_STAMP TimeStamp
;
557 UINT8 OemPlatformId
[16];
560 /// Definition of Section Header.
565 UINT8 ErrorRecoveryInfo
;
567 UINT32 SectionLength
;
571 /// GUID of Processor Machine Check Errors.
573 #define SAL_PROCESSOR_ERROR_RECORD_INFO \
575 0xe429faf1, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
578 // Bit masks for valid bits of MOD_ERROR_INFO
580 #define CHECK_INFO_VALID_BIT_MASK 0x1
581 #define REQUESTOR_ID_VALID_BIT_MASK 0x2
582 #define RESPONDER_ID_VALID_BIT_MASK 0x4
583 #define TARGER_ID_VALID_BIT_MASK 0x8
584 #define PRECISE_IP_VALID_BIT_MASK 0x10
586 /// Definition of MOD_ERROR_INFO_STRUCT.
589 UINT64 InfoValid
: 1;
591 UINT64 RespValid
: 1;
592 UINT64 TargetValid
: 1;
594 UINT64 Reserved
: 59;
602 /// Definition of CPUID_INFO_STRUCT.
614 // Bit masks for PSI_STATIC_STRUCT.ValidFieldBits
616 #define MIN_STATE_VALID_BIT_MASK 0x1
617 #define BR_VALID_BIT_MASK 0x2
618 #define CR_VALID_BIT_MASK 0x4
619 #define AR_VALID_BIT_MASK 0x8
620 #define RR_VALID_BIT_MASK 0x10
621 #define FR_VALID_BIT_MASK 0x20
623 /// Definition of PSI_STATIC_STRUCT.
626 UINT64 ValidFieldBits
;
627 UINT8 MinStateInfo
[1024];
635 // Bit masks for SAL_PROCESSOR_ERROR_RECORD.ValidationBits
637 #define PROC_ERROR_MAP_VALID_BIT_MASK 0x1
638 #define PROC_STATE_PARAMETER_VALID_BIT_MASK 0x2
639 #define PROC_CR_LID_VALID_BIT_MASK 0x4
640 #define PROC_STATIC_STRUCT_VALID_BIT_MASK 0x8
641 #define CPU_INFO_VALID_BIT_MASK 0x1000000
643 /// Definition of Processor Machine Check Error Record.
646 SAL_SEC_HEADER SectionHeader
;
647 UINT64 ValidationBits
;
649 UINT64 ProcStateParameter
;
651 MOD_ERROR_INFO CacheError
[15];
652 MOD_ERROR_INFO TlbError
[15];
653 MOD_ERROR_INFO BusError
[15];
654 MOD_ERROR_INFO RegFileCheck
[15];
655 MOD_ERROR_INFO MsCheck
[15];
657 PSI_STATIC_STRUCT PsiValidData
;
658 } SAL_PROCESSOR_ERROR_RECORD
;
661 /// GUID of Platform Memory Device Error Info.
663 #define SAL_MEMORY_ERROR_RECORD_INFO \
665 0xe429faf2, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
668 // Bit masks for SAL_MEMORY_ERROR_RECORD.ValidationBits
670 #define MEMORY_ERROR_STATUS_VALID_BIT_MASK 0x1
671 #define MEMORY_PHYSICAL_ADDRESS_VALID_BIT_MASK 0x2
672 #define MEMORY_ADDR_BIT_MASK 0x4
673 #define MEMORY_NODE_VALID_BIT_MASK 0x8
674 #define MEMORY_CARD_VALID_BIT_MASK 0x10
675 #define MEMORY_MODULE_VALID_BIT_MASK 0x20
676 #define MEMORY_BANK_VALID_BIT_MASK 0x40
677 #define MEMORY_DEVICE_VALID_BIT_MASK 0x80
678 #define MEMORY_ROW_VALID_BIT_MASK 0x100
679 #define MEMORY_COLUMN_VALID_BIT_MASK 0x200
680 #define MEMORY_BIT_POSITION_VALID_BIT_MASK 0x400
681 #define MEMORY_PLATFORM_REQUESTOR_ID_VALID_BIT_MASK 0x800
682 #define MEMORY_PLATFORM_RESPONDER_ID_VALID_BIT_MASK 0x1000
683 #define MEMORY_PLATFORM_TARGET_VALID_BIT_MASK 0x2000
684 #define MEMORY_PLATFORM_BUS_SPECIFIC_DATA_VALID_BIT_MASK 0x4000
685 #define MEMORY_PLATFORM_OEM_ID_VALID_BIT_MASK 0x8000
686 #define MEMORY_PLATFORM_OEM_DATA_STRUCT_VALID_BIT_MASK 0x10000
688 /// Definition of Platform Memory Device Error Info Record.
691 SAL_SEC_HEADER SectionHeader
;
692 UINT64 ValidationBits
;
693 UINT64 MemErrorStatus
;
694 UINT64 MemPhysicalAddress
;
695 UINT64 MemPhysicalAddressMask
;
703 UINT16 MemBitPosition
;
704 UINT64 ModRequestorId
;
705 UINT64 ModResponderId
;
707 UINT64 BusSpecificData
;
708 UINT8 MemPlatformOemId
[16];
709 } SAL_MEMORY_ERROR_RECORD
;
712 /// GUID of Platform PCI Bus Error Info.
714 #define SAL_PCI_BUS_ERROR_RECORD_INFO \
716 0xe429faf4, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
719 // Bit masks for SAL_PCI_BUS_ERROR_RECORD.ValidationBits
721 #define PCI_BUS_ERROR_STATUS_VALID_BIT_MASK 0x1
722 #define PCI_BUS_ERROR_TYPE_VALID_BIT_MASK 0x2
723 #define PCI_BUS_ID_VALID_BIT_MASK 0x4
724 #define PCI_BUS_ADDRESS_VALID_BIT_MASK 0x8
725 #define PCI_BUS_DATA_VALID_BIT_MASK 0x10
726 #define PCI_BUS_CMD_VALID_BIT_MASK 0x20
727 #define PCI_BUS_REQUESTOR_ID_VALID_BIT_MASK 0x40
728 #define PCI_BUS_RESPONDER_ID_VALID_BIT_MASK 0x80
729 #define PCI_BUS_TARGET_VALID_BIT_MASK 0x100
730 #define PCI_BUS_OEM_ID_VALID_BIT_MASK 0x200
731 #define PCI_BUS_OEM_DATA_STRUCT_VALID_BIT_MASK 0x400
734 /// Designated PCI Bus identifier.
742 /// Definition of Platform PCI Bus Error Info Record.
745 SAL_SEC_HEADER SectionHeader
;
746 UINT64 ValidationBits
;
747 UINT64 PciBusErrorStatus
;
748 UINT16 PciBusErrorType
;
751 UINT64 PciBusAddress
;
753 UINT64 PciBusCommand
;
754 UINT64 PciBusRequestorId
;
755 UINT64 PciBusResponderId
;
756 UINT64 PciBusTargetId
;
757 UINT8 PciBusOemId
[16];
758 } SAL_PCI_BUS_ERROR_RECORD
;
761 /// GUID of Platform PCI Component Error Info.
763 #define SAL_PCI_COMP_ERROR_RECORD_INFO \
765 0xe429faf6, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
768 // Bit masks for SAL_PCI_COMPONENT_ERROR_RECORD.ValidationBits
770 #define PCI_COMP_ERROR_STATUS_VALID_BIT_MASK 0x1
771 #define PCI_COMP_INFO_VALID_BIT_MASK 0x2
772 #define PCI_COMP_MEM_NUM_VALID_BIT_MASK 0x4
773 #define PCI_COMP_IO_NUM_VALID_BIT_MASK 0x8
774 #define PCI_COMP_REG_DATA_PAIR_VALID_BIT_MASK 0x10
775 #define PCI_COMP_OEM_DATA_STRUCT_VALID_BIT_MASK 0x20
777 /// Format of PCI Component Information to identify the device.
783 UINT8 FunctionNumber
;
790 /// Definition of Platform PCI Component Error Info.
793 SAL_SEC_HEADER SectionHeader
;
794 UINT64 ValidationBits
;
795 UINT64 PciComponentErrorStatus
;
796 PCI_COMP_INFO PciComponentInfo
;
797 UINT32 PciComponentMemNum
;
798 UINT32 PciComponentIoNum
;
799 UINT8 PciBusOemId
[16];
800 } SAL_PCI_COMPONENT_ERROR_RECORD
;
803 /// Platform SEL Device Error Info.
805 #define SAL_SEL_DEVICE_ERROR_RECORD_INFO \
807 0xe429faf3, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
810 // Bit masks for SAL_SEL_DEVICE_ERROR_RECORD.ValidationBits
812 #define SEL_RECORD_ID_VALID_BIT_MASK 0x1;
813 #define SEL_RECORD_TYPE_VALID_BIT_MASK 0x2;
814 #define SEL_GENERATOR_ID_VALID_BIT_MASK 0x4;
815 #define SEL_EVM_REV_VALID_BIT_MASK 0x8;
816 #define SEL_SENSOR_TYPE_VALID_BIT_MASK 0x10;
817 #define SEL_SENSOR_NUM_VALID_BIT_MASK 0x20;
818 #define SEL_EVENT_DIR_TYPE_VALID_BIT_MASK 0x40;
819 #define SEL_EVENT_DATA1_VALID_BIT_MASK 0x80;
820 #define SEL_EVENT_DATA2_VALID_BIT_MASK 0x100;
821 #define SEL_EVENT_DATA3_VALID_BIT_MASK 0x200;
823 /// Definition of Platform SEL Device Error Info Record.
826 SAL_SEC_HEADER SectionHeader
;
827 UINT64 ValidationBits
;
839 } SAL_SEL_DEVICE_ERROR_RECORD
;
842 /// GUID of Platform SMBIOS Device Error Info.
844 #define SAL_SMBIOS_ERROR_RECORD_INFO \
846 0xe429faf5, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
849 // Bit masks for SAL_SMBIOS_DEVICE_ERROR_RECORD.ValidationBits
851 #define SMBIOS_EVENT_TYPE_VALID_BIT_MASK 0x1
852 #define SMBIOS_LENGTH_VALID_BIT_MASK 0x2
853 #define SMBIOS_TIME_STAMP_VALID_BIT_MASK 0x4
854 #define SMBIOS_DATA_VALID_BIT_MASK 0x8
856 /// Definition of Platform SMBIOS Device Error Info Record.
859 SAL_SEC_HEADER SectionHeader
;
860 UINT64 ValidationBits
;
861 UINT8 SmbiosEventType
;
863 UINT8 SmbiosBcdTimeStamp
[6];
864 } SAL_SMBIOS_DEVICE_ERROR_RECORD
;
867 /// GUID of Platform Specific Error Info.
869 #define SAL_PLATFORM_ERROR_RECORD_INFO \
871 0xe429faf7, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
874 // Bit masks for SAL_PLATFORM_SPECIFIC_ERROR_RECORD.ValidationBits
876 #define PLATFORM_ERROR_STATUS_VALID_BIT_MASK 0x1
877 #define PLATFORM_REQUESTOR_ID_VALID_BIT_MASK 0x2
878 #define PLATFORM_RESPONDER_ID_VALID_BIT_MASK 0x4
879 #define PLATFORM_TARGET_VALID_BIT_MASK 0x8
880 #define PLATFORM_SPECIFIC_DATA_VALID_BIT_MASK 0x10
881 #define PLATFORM_OEM_ID_VALID_BIT_MASK 0x20
882 #define PLATFORM_OEM_DATA_STRUCT_VALID_BIT_MASK 0x40
883 #define PLATFORM_OEM_DEVICE_PATH_VALID_BIT_MASK 0x80
885 /// Definition of Platform Specific Error Info Record.
888 SAL_SEC_HEADER SectionHeader
;
889 UINT64 ValidationBits
;
890 UINT64 PlatformErrorStatus
;
891 UINT64 PlatformRequestorId
;
892 UINT64 PlatformResponderId
;
893 UINT64 PlatformTargetId
;
894 UINT64 PlatformBusSpecificData
;
895 UINT8 OemComponentId
[16];
896 } SAL_PLATFORM_SPECIFIC_ERROR_RECORD
;
899 /// Union of all the possible SAL Error Record Types.
902 SAL_RECORD_HEADER
*RecordHeader
;
903 SAL_PROCESSOR_ERROR_RECORD
*SalProcessorRecord
;
904 SAL_PCI_BUS_ERROR_RECORD
*SalPciBusRecord
;
905 SAL_PCI_COMPONENT_ERROR_RECORD
*SalPciComponentRecord
;
906 SAL_SEL_DEVICE_ERROR_RECORD
*ImpiRecord
;
907 SAL_SMBIOS_DEVICE_ERROR_RECORD
*SmbiosRecord
;
908 SAL_PLATFORM_SPECIFIC_ERROR_RECORD
*PlatformRecord
;
909 SAL_MEMORY_ERROR_RECORD
*MemoryRecord
;
911 } SAL_ERROR_RECORDS_POINTERS
;