2 This file contains definitions for SPD DDR4.
4 Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
5 This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
13 @par Revision Reference:
14 - Serial Presence Detect (SPD) for DDR4 SDRAM Modules Document Release 4
15 http://www.jedec.org/standards-documents/docs/spd412l-4
18 #ifndef _SDRAM_SPD_DDR4_H_
19 #define _SDRAM_SPD_DDR4_H_
21 #pragma pack (push, 1)
25 UINT8 BytesUsed
: 4; ///< Bits 3:0
26 UINT8 BytesTotal
: 3; ///< Bits 6:4
27 UINT8 CrcCoverage
: 1; ///< Bits 7:7
30 } SPD4_DEVICE_DESCRIPTION_STRUCT
;
34 UINT8 Minor
: 4; ///< Bits 3:0
35 UINT8 Major
: 4; ///< Bits 7:4
38 } SPD4_REVISION_STRUCT
;
42 UINT8 Type
: 8; ///< Bits 7:0
45 } SPD4_DRAM_DEVICE_TYPE_STRUCT
;
49 UINT8 ModuleType
: 4; ///< Bits 3:0
50 UINT8 HybridMedia
: 3; ///< Bits 6:4
51 UINT8 Hybrid
: 1; ///< Bits 7:7
54 } SPD4_MODULE_TYPE_STRUCT
;
58 UINT8 Density
: 4; ///< Bits 3:0
59 UINT8 BankAddress
: 2; ///< Bits 5:4
60 UINT8 BankGroup
: 2; ///< Bits 7:6
63 } SPD4_SDRAM_DENSITY_BANKS_STRUCT
;
67 UINT8 ColumnAddress
: 3; ///< Bits 2:0
68 UINT8 RowAddress
: 3; ///< Bits 5:3
69 UINT8 Reserved
: 2; ///< Bits 7:6
72 } SPD4_SDRAM_ADDRESSING_STRUCT
;
76 UINT8 SignalLoading
: 2; ///< Bits 1:0
77 UINT8 Reserved
: 2; ///< Bits 3:2
78 UINT8 DieCount
: 3; ///< Bits 6:4
79 UINT8 SdramPackageType
: 1; ///< Bits 7:7
82 } SPD4_PRIMARY_SDRAM_PACKAGE_TYPE_STRUCT
;
86 UINT8 MaximumActivateCount
: 4; ///< Bits 3:0
87 UINT8 MaximumActivateWindow
: 2; ///< Bits 5:4
88 UINT8 Reserved
: 2; ///< Bits 7:6
91 } SPD4_SDRAM_OPTIONAL_FEATURES_STRUCT
;
95 UINT8 Reserved
: 8; ///< Bits 7:0
98 } SPD4_SDRAM_THERMAL_REFRESH_STRUCT
;
102 UINT8 Reserved
: 5; ///< Bits 4:0
103 UINT8 SoftPPR
: 1; ///< Bits 5:5
104 UINT8 PostPackageRepair
: 2; ///< Bits 7:6
107 } SPD4_OTHER_SDRAM_OPTIONAL_FEATURES_STRUCT
;
111 UINT8 SignalLoading
: 2; ///< Bits 1:0
112 UINT8 DRAMDensityRatio
: 2; ///< Bits 3:2
113 UINT8 DieCount
: 3; ///< Bits 6:4
114 UINT8 SdramPackageType
: 1; ///< Bits 7:7
117 } SPD4_SECONDARY_SDRAM_PACKAGE_TYPE_STRUCT
;
121 UINT8 OperationAt1_20
: 1; ///< Bits 0:0
122 UINT8 EndurantAt1_20
: 1; ///< Bits 1:1
123 UINT8 Reserved
: 6; ///< Bits 7:2
126 } SPD4_MODULE_NOMINAL_VOLTAGE_STRUCT
;
130 UINT8 SdramDeviceWidth
: 3; ///< Bits 2:0
131 UINT8 RankCount
: 3; ///< Bits 5:3
132 UINT8 RankMix
: 1; ///< Bits 6:6
133 UINT8 Reserved
: 1; ///< Bits 7:7
136 } SPD4_MODULE_ORGANIZATION_STRUCT
;
140 UINT8 PrimaryBusWidth
: 3; ///< Bits 2:0
141 UINT8 BusWidthExtension
: 2; ///< Bits 4:3
142 UINT8 Reserved
: 3; ///< Bits 7:5
145 } SPD4_MODULE_MEMORY_BUS_WIDTH_STRUCT
;
149 UINT8 Reserved
: 7; ///< Bits 6:0
150 UINT8 ThermalSensorPresence
: 1; ///< Bits 7:7
153 } SPD4_MODULE_THERMAL_SENSOR_STRUCT
;
157 UINT8 ExtendedBaseModuleType
: 4; ///< Bits 3:0
158 UINT8 Reserved
: 4; ///< Bits 7:4
161 } SPD4_EXTENDED_MODULE_TYPE_STRUCT
;
165 UINT8 Fine
: 2; ///< Bits 1:0
166 UINT8 Medium
: 2; ///< Bits 3:2
167 UINT8 Reserved
: 4; ///< Bits 7:4
170 } SPD4_TIMEBASE_STRUCT
;
174 UINT8 tCKmin
: 8; ///< Bits 7:0
177 } SPD4_TCK_MIN_MTB_STRUCT
;
181 UINT8 tCKmax
: 8; ///< Bits 7:0
184 } SPD4_TCK_MAX_MTB_STRUCT
;
188 UINT32 Cl7
: 1; ///< Bits 0:0
189 UINT32 Cl8
: 1; ///< Bits 1:1
190 UINT32 Cl9
: 1; ///< Bits 2:2
191 UINT32 Cl10
: 1; ///< Bits 3:3
192 UINT32 Cl11
: 1; ///< Bits 4:4
193 UINT32 Cl12
: 1; ///< Bits 5:5
194 UINT32 Cl13
: 1; ///< Bits 6:6
195 UINT32 Cl14
: 1; ///< Bits 7:7
196 UINT32 Cl15
: 1; ///< Bits 8:8
197 UINT32 Cl16
: 1; ///< Bits 9:9
198 UINT32 Cl17
: 1; ///< Bits 10:10
199 UINT32 Cl18
: 1; ///< Bits 11:11
200 UINT32 Cl19
: 1; ///< Bits 12:12
201 UINT32 Cl20
: 1; ///< Bits 13:13
202 UINT32 Cl21
: 1; ///< Bits 14:14
203 UINT32 Cl22
: 1; ///< Bits 15:15
204 UINT32 Cl23
: 1; ///< Bits 16:16
205 UINT32 Cl24
: 1; ///< Bits 17:17
206 UINT32 Cl25
: 1; ///< Bits 18:18
207 UINT32 Cl26
: 1; ///< Bits 19:19
208 UINT32 Cl27
: 1; ///< Bits 20:20
209 UINT32 Cl28
: 1; ///< Bits 21:21
210 UINT32 Cl29
: 1; ///< Bits 22:22
211 UINT32 Cl30
: 1; ///< Bits 23:23
212 UINT32 Cl31
: 1; ///< Bits 24:24
213 UINT32 Cl32
: 1; ///< Bits 25:25
214 UINT32 Cl33
: 1; ///< Bits 26:26
215 UINT32 Cl34
: 1; ///< Bits 27:27
216 UINT32 Cl35
: 1; ///< Bits 28:28
217 UINT32 Cl36
: 1; ///< Bits 29:29
218 UINT32 Reserved
: 1; ///< Bits 30:30
219 UINT32 ClRange
: 1; ///< Bits 31:31
222 UINT32 Cl23
: 1; ///< Bits 0:0
223 UINT32 Cl24
: 1; ///< Bits 1:1
224 UINT32 Cl25
: 1; ///< Bits 2:2
225 UINT32 Cl26
: 1; ///< Bits 3:3
226 UINT32 Cl27
: 1; ///< Bits 4:4
227 UINT32 Cl28
: 1; ///< Bits 5:5
228 UINT32 Cl29
: 1; ///< Bits 6:6
229 UINT32 Cl30
: 1; ///< Bits 7:7
230 UINT32 Cl31
: 1; ///< Bits 8:8
231 UINT32 Cl32
: 1; ///< Bits 9:9
232 UINT32 Cl33
: 1; ///< Bits 10:10
233 UINT32 Cl34
: 1; ///< Bits 11:11
234 UINT32 Cl35
: 1; ///< Bits 12:12
235 UINT32 Cl36
: 1; ///< Bits 13:13
236 UINT32 Cl37
: 1; ///< Bits 14:14
237 UINT32 Cl38
: 1; ///< Bits 15:15
238 UINT32 Cl39
: 1; ///< Bits 16:16
239 UINT32 Cl40
: 1; ///< Bits 17:17
240 UINT32 Cl41
: 1; ///< Bits 18:18
241 UINT32 Cl42
: 1; ///< Bits 19:19
242 UINT32 Cl43
: 1; ///< Bits 20:20
243 UINT32 Cl44
: 1; ///< Bits 21:21
244 UINT32 Cl45
: 1; ///< Bits 22:22
245 UINT32 Cl46
: 1; ///< Bits 23:23
246 UINT32 Cl47
: 1; ///< Bits 24:24
247 UINT32 Cl48
: 1; ///< Bits 25:25
248 UINT32 Cl49
: 1; ///< Bits 26:26
249 UINT32 Cl50
: 1; ///< Bits 27:27
250 UINT32 Cl51
: 1; ///< Bits 28:28
251 UINT32 Cl52
: 1; ///< Bits 29:29
252 UINT32 Reserved
: 1; ///< Bits 30:30
253 UINT32 ClRange
: 1; ///< Bits 31:31
258 } SPD4_CAS_LATENCIES_SUPPORTED_STRUCT
;
262 UINT8 tAAmin
: 8; ///< Bits 7:0
265 } SPD4_TAA_MIN_MTB_STRUCT
;
269 UINT8 tRCDmin
: 8; ///< Bits 7:0
272 } SPD4_TRCD_MIN_MTB_STRUCT
;
276 UINT8 tRPmin
: 8; ///< Bits 7:0
279 } SPD4_TRP_MIN_MTB_STRUCT
;
283 UINT8 tRASminUpper
: 4; ///< Bits 3:0
284 UINT8 tRCminUpper
: 4; ///< Bits 7:4
287 } SPD4_TRAS_TRC_MIN_MTB_STRUCT
;
291 UINT8 tRASmin
: 8; ///< Bits 7:0
294 } SPD4_TRAS_MIN_MTB_STRUCT
;
298 UINT8 tRCmin
: 8; ///< Bits 7:0
301 } SPD4_TRC_MIN_MTB_STRUCT
;
305 UINT16 tRFCmin
: 16; ///< Bits 15:0
309 } SPD4_TRFC_MIN_MTB_STRUCT
;
313 UINT8 tFAWminUpper
: 4; ///< Bits 3:0
314 UINT8 Reserved
: 4; ///< Bits 7:4
317 } SPD4_TFAW_MIN_MTB_UPPER_STRUCT
;
321 UINT8 tFAWmin
: 8; ///< Bits 7:0
324 } SPD4_TFAW_MIN_MTB_STRUCT
;
328 UINT8 tRRDmin
: 8; ///< Bits 7:0
331 } SPD4_TRRD_MIN_MTB_STRUCT
;
335 UINT8 tCCDmin
: 8; ///< Bits 7:0
338 } SPD4_TCCD_MIN_MTB_STRUCT
;
342 UINT8 tWRminMostSignificantNibble
: 4; ///< Bits 3:0
343 UINT8 Reserved
: 4; ///< Bits 7:4
346 } SPD4_TWR_UPPER_NIBBLE_STRUCT
;
350 UINT8 tWRmin
: 8; ///< Bits 7:0
353 } SPD4_TWR_MIN_MTB_STRUCT
;
357 UINT8 tWTR_SminMostSignificantNibble
: 4; ///< Bits 3:0
358 UINT8 tWTR_LminMostSignificantNibble
: 4; ///< Bits 7:4
361 } SPD4_TWTR_UPPER_NIBBLE_STRUCT
;
365 UINT8 tWTRmin
: 8; ///< Bits 7:0
368 } SPD4_TWTR_MIN_MTB_STRUCT
;
372 UINT8 BitOrderatSDRAM
: 5; ///< Bits 4:0
373 UINT8 WiredtoUpperLowerNibble
: 1; ///< Bits 5:5
374 UINT8 PackageRankMap
: 2; ///< Bits 7:6
377 } SPD4_CONNECTOR_BIT_MAPPING_BYTE_STRUCT
;
381 INT8 tCCDminFine
: 8; ///< Bits 7:0
384 } SPD4_TCCD_MIN_FTB_STRUCT
;
388 INT8 tRRDminFine
: 8; ///< Bits 7:0
391 } SPD4_TRRD_MIN_FTB_STRUCT
;
395 INT8 tRCminFine
: 8; ///< Bits 7:0
398 } SPD4_TRC_MIN_FTB_STRUCT
;
402 INT8 tRPminFine
: 8; ///< Bits 7:0
405 } SPD4_TRP_MIN_FTB_STRUCT
;
409 INT8 tRCDminFine
: 8; ///< Bits 7:0
412 } SPD4_TRCD_MIN_FTB_STRUCT
;
416 INT8 tAAminFine
: 8; ///< Bits 7:0
419 } SPD4_TAA_MIN_FTB_STRUCT
;
423 INT8 tCKmaxFine
: 8; ///< Bits 7:0
426 } SPD4_TCK_MAX_FTB_STRUCT
;
430 INT8 tCKminFine
: 8; ///< Bits 7:0
433 } SPD4_TCK_MIN_FTB_STRUCT
;
437 UINT8 Height
: 5; ///< Bits 4:0
438 UINT8 RawCardExtension
: 3; ///< Bits 7:5
441 } SPD4_UNBUF_MODULE_NOMINAL_HEIGHT
;
445 UINT8 FrontThickness
: 4; ///< Bits 3:0
446 UINT8 BackThickness
: 4; ///< Bits 7:4
449 } SPD4_UNBUF_MODULE_NOMINAL_THICKNESS
;
453 UINT8 Card
: 5; ///< Bits 4:0
454 UINT8 Revision
: 2; ///< Bits 6:5
455 UINT8 Extension
: 1; ///< Bits 7:7
458 } SPD4_UNBUF_REFERENCE_RAW_CARD
;
462 UINT8 MappingRank1
: 1; ///< Bits 0:0
463 UINT8 Reserved
: 7; ///< Bits 7:1
466 } SPD4_UNBUF_ADDRESS_MAPPING
;
470 UINT8 Height
: 5; ///< Bits 4:0
471 UINT8 Reserved
: 3; ///< Bits 7:5
474 } SPD4_RDIMM_MODULE_NOMINAL_HEIGHT
;
478 UINT8 FrontThickness
: 4; ///< Bits 3:0
479 UINT8 BackThickness
: 4; ///< Bits 7:4
482 } SPD4_RDIMM_MODULE_NOMINAL_THICKNESS
;
486 UINT8 Card
: 5; ///< Bits 4:0
487 UINT8 Revision
: 2; ///< Bits 6:5
488 UINT8 Extension
: 1; ///< Bits 7:7
491 } SPD4_RDIMM_REFERENCE_RAW_CARD
;
495 UINT8 RegisterCount
: 2; ///< Bits 1:0
496 UINT8 DramRowCount
: 2; ///< Bits 3:2
497 UINT8 RegisterType
: 4; ///< Bits 7:4
500 } SPD4_RDIMM_MODULE_ATTRIBUTES
;
504 UINT8 HeatSpreaderThermalCharacteristics
: 7; ///< Bits 6:0
505 UINT8 HeatSpreaderSolution
: 1; ///< Bits 7:7
508 } SPD4_RDIMM_THERMAL_HEAT_SPREADER_SOLUTION
;
512 UINT16 ContinuationCount
: 7; ///< Bits 6:0
513 UINT16 ContinuationParity
: 1; ///< Bits 7:7
514 UINT16 LastNonZeroByte
: 8; ///< Bits 15:8
518 } SPD4_MANUFACTURER_ID_CODE
;
522 UINT8 RegisterRevisionNumber
; ///< Bits 7:0
525 } SPD4_RDIMM_REGISTER_REVISION_NUMBER
;
529 UINT8 Rank1Mapping
: 1; ///< Bits 0:0
530 UINT8 Reserved
: 7; ///< Bits 7:1
533 } SPD4_RDIMM_ADDRESS_MAPPING_FROM_REGISTER_TO_DRAM
;
537 UINT8 Cke
: 2; ///< Bits 1:0
538 UINT8 Odt
: 2; ///< Bits 3:2
539 UINT8 CommandAddress
: 2; ///< Bits 5:4
540 UINT8 ChipSelect
: 2; ///< Bits 7:6
543 } SPD4_RDIMM_REGISTER_OUTPUT_DRIVE_STRENGTH_FOR_CONTROL_COMMAND_ADDRESS
;
547 UINT8 Y0Y2
: 2; ///< Bits 1:0
548 UINT8 Y1Y3
: 2; ///< Bits 3:2
549 UINT8 Reserved0
: 2; ///< Bits 5:4
550 UINT8 RcdOutputSlewRateControl
: 1; ///< Bits 6:6
551 UINT8 Reserved1
: 1; ///< Bits 7:7
554 } SPD4_RDIMM_REGISTER_OUTPUT_DRIVE_STRENGTH_FOR_CLOCK
;
558 UINT8 Height
: 5; ///< Bits 4:0
559 UINT8 Reserved
: 3; ///< Bits 7:5
562 } SPD4_LRDIMM_MODULE_NOMINAL_HEIGHT
;
566 UINT8 FrontThickness
: 4; ///< Bits 3:0
567 UINT8 BackThickness
: 4; ///< Bits 7:4
570 } SPD4_LRDIMM_MODULE_NOMINAL_THICKNESS
;
574 UINT8 Card
: 5; ///< Bits 4:0
575 UINT8 Revision
: 2; ///< Bits 6:5
576 UINT8 Extension
: 1; ///< Bits 7:7
579 } SPD4_LRDIMM_REFERENCE_RAW_CARD
;
583 UINT8 RegisterCount
: 2; ///< Bits 1:0
584 UINT8 DramRowCount
: 2; ///< Bits 3:2
585 UINT8 RegisterType
: 4; ///< Bits 7:4
588 } SPD4_LRDIMM_MODULE_ATTRIBUTES
;
592 UINT8 HeatSpreaderThermalCharacteristics
: 7; ///< Bits 6:0
593 UINT8 HeatSpreaderSolution
: 1; ///< Bits 7:7
596 } SPD4_LRDIMM_THERMAL_HEAT_SPREADER_SOLUTION
;
600 UINT8 RegisterRevisionNumber
; ///< Bits 7:0
603 } SPD4_LRDIMM_REGISTER_REVISION_NUMBER
;
607 UINT8 Rank1Mapping
: 1; ///< Bits 0:0
608 UINT8 Reserved
: 7; ///< Bits 7:1
611 } SPD4_LRDIMM_ADDRESS_MAPPING_FROM_REGISTER_TO_DRAM
;
615 UINT8 Cke
: 2; ///< Bits 1:0
616 UINT8 Odt
: 2; ///< Bits 3:2
617 UINT8 CommandAddress
: 2; ///< Bits 5:4
618 UINT8 ChipSelect
: 2; ///< Bits 7:6
621 } SPD4_LRDIMM_REGISTER_OUTPUT_DRIVE_STRENGTH_FOR_CONTROL_COMMAND_ADDRESS
;
625 UINT8 Y0Y2
: 2; ///< Bits 1:0
626 UINT8 Y1Y3
: 2; ///< Bits 3:2
627 UINT8 Reserved0
: 2; ///< Bits 5:4
628 UINT8 RcdOutputSlewRateControl
: 1; ///< Bits 6:6
629 UINT8 Reserved1
: 1; ///< Bits 7:7
632 } SPD4_LRDIMM_REGISTER_OUTPUT_DRIVE_STRENGTH_FOR_CLOCK
;
635 UINT8 DataBufferRevisionNumber
;
636 } SPD4_LRDIMM_DATA_BUFFER_REVISION_NUMBER
;
640 UINT8 DramVrefDQForPackageRank0
: 6; ///< Bits 5:0
641 UINT8 Reserved
: 2; ///< Bits 7:6
644 } SPD4_LRDIMM_DRAM_VREFDQ_FOR_PACKAGE_RANK
;
647 UINT8 DataBufferVrefDQforDramInterface
;
648 } SPD4_LRDIMM_DATA_BUFFER_VREFDQ_FOR_DRAM_INTERFACE
;
652 UINT8 DramInterfaceMdqDriveStrength
: 4; ///< Bits 3:0
653 UINT8 DramInterfaceMdqReadTerminationStrength
: 4; ///< Bits 7:4
656 } SPD4_LRDIMM_DATA_BUFFER_MDQ_DRIVE_STRENGTH_RTT_FOR_DATA_RATE
;
660 UINT8 DataRateLe1866
: 2; ///< Bits 1:0
661 UINT8 DataRateLe2400
: 2; ///< Bits 3:2
662 UINT8 DataRateLe3200
: 2; ///< Bits 5:4
663 UINT8 Reserved
: 2; ///< Bits 7:6
666 } SPD4_LRDIMM_DRAM_DRIVE_STRENGTH
;
670 UINT8 Rtt_Nom
: 3; ///< Bits 2:0
671 UINT8 Rtt_WR
: 3; ///< Bits 5:3
672 UINT8 Reserved
: 2; ///< Bits 7:6
675 } SPD4_LRDIMM_DRAM_ODT_RTT_WR_RTT_NOM_FOR_DATA_RATE
;
679 UINT8 PackageRanks0_1
: 3; ///< Bits 2:0
680 UINT8 PackageRanks2_3
: 3; ///< Bits 5:3
681 UINT8 Reserved
: 2; ///< Bits 7:6
684 } SPD4_LRDIMM_DRAM_ODT_RTT_PARK_FOR_DATA_RATE
;
688 UINT8 Rank0
: 1; ///< Bits 0:0
689 UINT8 Rank1
: 1; ///< Bits 1:1
690 UINT8 Rank2
: 1; ///< Bits 2:2
691 UINT8 Rank3
: 1; ///< Bits 3:3
692 UINT8 DataBuffer
: 1; ///< Bits 4:4
693 UINT8 Reserved
: 3; ///< Bits 7:5
696 } SPD4_LRDIMM_DATA_BUFFER_VREFDQ_FOR_DRAM_INTERFACE_RANGE
;
700 UINT8 DataBufferGainAdjustment
: 1; ///< Bits 0:0
701 UINT8 DataBufferDfe
: 1; ///< Bits 1:1
702 UINT8 Reserved
: 6; ///< Bits 7:2
705 } SPD4_LRDIMM_DATA_BUFFER_DQ_DECISION_FEEDBACK_EQUALIZATION
;
707 typedef UINT16 SPD4_NVDIMM_MODULE_PRODUCT_IDENTIFIER
;
711 UINT16 ContinuationCount
: 7; ///< Bits 6:0
712 UINT16 ContinuationParity
: 1; ///< Bits 7:7
713 UINT16 LastNonZeroByte
: 8; ///< Bits 15:8
717 } SPD4_NVDIMM_SUBSYSTEM_CONTROLLER_MANUFACTURER_ID_CODE
;
719 typedef UINT16 SPD4_NVDIMM_SUBSYSTEM_CONTROLLER_IDENTIFIER
;
721 typedef UINT8 SPD4_NVDIMM_SUBSYSTEM_CONTROLLER_REVISION_CODE
;
725 UINT8 Card
: 5; ///< Bits 4:0
726 UINT8 Revision
: 2; ///< Bits 6:5
727 UINT8 Extension
: 1; ///< Bits 7:7
730 } SPD4_NVDIMM_REFERENCE_RAW_CARD
;
734 UINT8 Reserved
: 4; ///< Bits 3:0
735 UINT8 Extension
: 4; ///< Bits 7:4
738 } SPD4_NVDIMM_MODULE_CHARACTERISTICS
;
743 } SPD4_NVDIMM_HYBRID_MODULE_MEDIA_TYPES
;
745 typedef UINT8 SPD4_NVDIMM_MAXIMUM_NONVOLATILE_MEMORY_INITIALIZATION_TIME
;
749 UINT16 FunctionInterface
: 5; ///< Bits 4:0
750 UINT16 FunctionClass
: 5; ///< Bits 9:5
751 UINT16 BlockOffset
: 4; ///< Bits 13:10
752 UINT16 Reserved
: 1; ///< Bits 14:14
753 UINT16 Implemented
: 1; ///< Bits 15:15
757 } SPD4_NVDIMM_FUNCTION_INTERFACE_DESCRIPTOR
;
760 UINT8 Year
; ///< Year represented in BCD (00h = 2000)
761 UINT8 Week
; ///< Year represented in BCD (47h = week 47)
762 } SPD4_MANUFACTURING_DATE
;
766 UINT16 SerialNumber16
[2];
767 UINT8 SerialNumber8
[4];
768 } SPD4_MANUFACTURER_SERIAL_NUMBER
;
771 UINT8 Location
; ///< Module Manufacturing Location
772 } SPD4_MANUFACTURING_LOCATION
;
775 SPD4_MANUFACTURER_ID_CODE IdCode
; ///< Module Manufacturer ID Code
776 SPD4_MANUFACTURING_LOCATION Location
; ///< Module Manufacturing Location
777 SPD4_MANUFACTURING_DATE Date
; ///< Module Manufacturing Year, in BCD (range: 2000-2255)
778 SPD4_MANUFACTURER_SERIAL_NUMBER SerialNumber
; ///< Module Serial Number
779 } SPD4_UNIQUE_MODULE_ID
;
784 } SPD4_CYCLIC_REDUNDANCY_CODE
;
787 SPD4_DEVICE_DESCRIPTION_STRUCT Description
; ///< 0 Number of Serial PD Bytes Written / SPD Device Size / CRC Coverage 1, 2
788 SPD4_REVISION_STRUCT Revision
; ///< 1 SPD Revision
789 SPD4_DRAM_DEVICE_TYPE_STRUCT DramDeviceType
; ///< 2 DRAM Device Type
790 SPD4_MODULE_TYPE_STRUCT ModuleType
; ///< 3 Module Type
791 SPD4_SDRAM_DENSITY_BANKS_STRUCT SdramDensityAndBanks
; ///< 4 SDRAM Density and Banks
792 SPD4_SDRAM_ADDRESSING_STRUCT SdramAddressing
; ///< 5 SDRAM Addressing
793 SPD4_PRIMARY_SDRAM_PACKAGE_TYPE_STRUCT PrimarySdramPackageType
; ///< 6 Primary SDRAM Package Type
794 SPD4_SDRAM_OPTIONAL_FEATURES_STRUCT SdramOptionalFeatures
; ///< 7 SDRAM Optional Features
795 SPD4_SDRAM_THERMAL_REFRESH_STRUCT ThermalAndRefreshOptions
; ///< 8 SDRAM Thermal and Refresh Options
796 SPD4_OTHER_SDRAM_OPTIONAL_FEATURES_STRUCT OtherOptionalFeatures
; ///< 9 Other SDRAM Optional Features
797 SPD4_SECONDARY_SDRAM_PACKAGE_TYPE_STRUCT SecondarySdramPackageType
;///< 10 Secondary SDRAM Package Type
798 SPD4_MODULE_NOMINAL_VOLTAGE_STRUCT ModuleNominalVoltage
; ///< 11 Module Nominal Voltage, VDD
799 SPD4_MODULE_ORGANIZATION_STRUCT ModuleOrganization
; ///< 12 Module Organization
800 SPD4_MODULE_MEMORY_BUS_WIDTH_STRUCT ModuleMemoryBusWidth
; ///< 13 Module Memory Bus Width
801 SPD4_MODULE_THERMAL_SENSOR_STRUCT ModuleThermalSensor
; ///< 14 Module Thermal Sensor
802 SPD4_EXTENDED_MODULE_TYPE_STRUCT ExtendedModuleType
; ///< 15 Extended Module Type
803 UINT8 Reserved0
; ///< 16 Reserved
804 SPD4_TIMEBASE_STRUCT Timebase
; ///< 17 Timebases
805 SPD4_TCK_MIN_MTB_STRUCT tCKmin
; ///< 18 SDRAM Minimum Cycle Time (tCKmin)
806 SPD4_TCK_MAX_MTB_STRUCT tCKmax
; ///< 19 SDRAM Maximum Cycle Time (tCKmax)
807 SPD4_CAS_LATENCIES_SUPPORTED_STRUCT CasLatencies
; ///< 20-23 CAS Latencies Supported
808 SPD4_TAA_MIN_MTB_STRUCT tAAmin
; ///< 24 Minimum CAS Latency Time (tAAmin)
809 SPD4_TRCD_MIN_MTB_STRUCT tRCDmin
; ///< 25 Minimum RAS# to CAS# Delay Time (tRCDmin)
810 SPD4_TRP_MIN_MTB_STRUCT tRPmin
; ///< 26 Minimum Row Precharge Delay Time (tRPmin)
811 SPD4_TRAS_TRC_MIN_MTB_STRUCT tRASMintRCMinUpper
; ///< 27 Upper Nibbles for tRAS and tRC
812 SPD4_TRAS_MIN_MTB_STRUCT tRASmin
; ///< 28 Minimum Active to Precharge Delay Time (tRASmin), Least Significant Byte
813 SPD4_TRC_MIN_MTB_STRUCT tRCmin
; ///< 29 Minimum Active to Active/Refresh Delay Time (tRCmin), Least Significant Byte
814 SPD4_TRFC_MIN_MTB_STRUCT tRFC1min
; ///< 30-31 Minimum Refresh Recovery Delay Time (tRFC1min)
815 SPD4_TRFC_MIN_MTB_STRUCT tRFC2min
; ///< 32-33 Minimum Refresh Recovery Delay Time (tRFC2min)
816 SPD4_TRFC_MIN_MTB_STRUCT tRFC4min
; ///< 34-35 Minimum Refresh Recovery Delay Time (tRFC4min)
817 SPD4_TFAW_MIN_MTB_UPPER_STRUCT tFAWMinUpper
; ///< 36 Upper Nibble for tFAW
818 SPD4_TFAW_MIN_MTB_STRUCT tFAWmin
; ///< 37 Minimum Four Activate Window Delay Time (tFAWmin)
819 SPD4_TRRD_MIN_MTB_STRUCT tRRD_Smin
; ///< 38 Minimum Activate to Activate Delay Time (tRRD_Smin), different bank group
820 SPD4_TRRD_MIN_MTB_STRUCT tRRD_Lmin
; ///< 39 Minimum Activate to Activate Delay Time (tRRD_Lmin), same bank group
821 SPD4_TCCD_MIN_MTB_STRUCT tCCD_Lmin
; ///< 40 Minimum CAS to CAS Delay Time (tCCD_Lmin), Same Bank Group
822 SPD4_TWR_UPPER_NIBBLE_STRUCT tWRUpperNibble
; ///< 41 Upper Nibble for tWRmin
823 SPD4_TWR_MIN_MTB_STRUCT tWRmin
; ///< 42 Minimum Write Recovery Time (tWRmin)
824 SPD4_TWTR_UPPER_NIBBLE_STRUCT tWTRUpperNibble
; ///< 43 Upper Nibbles for tWTRmin
825 SPD4_TWTR_MIN_MTB_STRUCT tWTR_Smin
; ///< 44 Minimum Write to Read Time (tWTR_Smin), Different Bank Group
826 SPD4_TWTR_MIN_MTB_STRUCT tWTR_Lmin
; ///< 45 Minimum Write to Read Time (tWTR_Lmin), Same Bank Group
827 UINT8 Reserved1
[59 - 46 + 1]; ///< 46-59 Reserved
828 SPD4_CONNECTOR_BIT_MAPPING_BYTE_STRUCT BitMapping
[77 - 60 + 1]; ///< 60-77 Connector to SDRAM Bit Mapping
829 UINT8 Reserved2
[116 - 78 + 1]; ///< 78-116 Reserved
830 SPD4_TCCD_MIN_FTB_STRUCT tCCD_LminFine
; ///< 117 Fine Offset for Minimum CAS to CAS Delay Time (tCCD_Lmin), same bank group
831 SPD4_TRRD_MIN_FTB_STRUCT tRRD_LminFine
; ///< 118 Fine Offset for Minimum Activate to Activate Delay Time (tRRD_Lmin), different bank group
832 SPD4_TRRD_MIN_FTB_STRUCT tRRD_SminFine
; ///< 119 Fine Offset for Minimum Activate to Activate Delay Time (tRRD_Smin), same bank group
833 SPD4_TRC_MIN_FTB_STRUCT tRCminFine
; ///< 120 Fine Offset for Minimum Active to Active/Refresh Delay Time (tRCmin)
834 SPD4_TRP_MIN_FTB_STRUCT tRPminFine
; ///< 121 Fine Offset for Minimum Row Precharge Delay Time (tRPabmin)
835 SPD4_TRCD_MIN_FTB_STRUCT tRCDminFine
; ///< 122 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin)
836 SPD4_TAA_MIN_FTB_STRUCT tAAminFine
; ///< 123 Fine Offset for Minimum CAS Latency Time (tAAmin)
837 SPD4_TCK_MAX_FTB_STRUCT tCKmaxFine
; ///< 124 Fine Offset for SDRAM Minimum Cycle Time (tCKmax)
838 SPD4_TCK_MIN_FTB_STRUCT tCKminFine
; ///< 125 Fine Offset for SDRAM Maximum Cycle Time (tCKmin)
839 SPD4_CYCLIC_REDUNDANCY_CODE Crc
; ///< 126-127 Cyclical Redundancy Code (CRC)
843 SPD4_UNBUF_MODULE_NOMINAL_HEIGHT ModuleNominalHeight
; ///< 128 Module Nominal Height
844 SPD4_UNBUF_MODULE_NOMINAL_THICKNESS ModuleMaximumThickness
; ///< 129 Module Maximum Thickness
845 SPD4_UNBUF_REFERENCE_RAW_CARD ReferenceRawCardUsed
; ///< 130 Reference Raw Card Used
846 SPD4_UNBUF_ADDRESS_MAPPING AddressMappingEdgeConn
; ///< 131 Address Mapping from Edge Connector to DRAM
847 UINT8 Reserved
[253 - 132 + 1]; ///< 132-253 Reserved
848 SPD4_CYCLIC_REDUNDANCY_CODE Crc
; ///< 254-255 Cyclical Redundancy Code (CRC)
849 } SPD4_MODULE_UNBUFFERED
;
852 SPD4_RDIMM_MODULE_NOMINAL_HEIGHT ModuleNominalHeight
; ///< 128 Module Nominal Height
853 SPD4_RDIMM_MODULE_NOMINAL_THICKNESS ModuleMaximumThickness
; ///< 129 Module Maximum Thickness
854 SPD4_RDIMM_REFERENCE_RAW_CARD ReferenceRawCardUsed
; ///< 130 Reference Raw Card Used
855 SPD4_RDIMM_MODULE_ATTRIBUTES DimmModuleAttributes
; ///< 131 DIMM Module Attributes
856 SPD4_RDIMM_THERMAL_HEAT_SPREADER_SOLUTION DimmThermalHeatSpreaderSolution
; ///< 132 RDIMM Thermal Heat Spreader Solution
857 SPD4_MANUFACTURER_ID_CODE RegisterManufacturerIdCode
; ///< 133-134 Register Manufacturer ID Code
858 SPD4_RDIMM_REGISTER_REVISION_NUMBER RegisterRevisionNumber
; ///< 135 Register Revision Number
859 SPD4_RDIMM_ADDRESS_MAPPING_FROM_REGISTER_TO_DRAM AddressMappingFromRegisterToDRAM
; ///< 136 Address Mapping from Register to DRAM
860 SPD4_RDIMM_REGISTER_OUTPUT_DRIVE_STRENGTH_FOR_CONTROL_COMMAND_ADDRESS RegisterOutputDriveStrengthForControlCommandAddress
; ///< 137 Register Output Drive Strength for Control and Command Address
861 SPD4_RDIMM_REGISTER_OUTPUT_DRIVE_STRENGTH_FOR_CLOCK RegisterOutputDriveStrengthForClock
; ///< 138 Register Output Drive Strength for Clock
862 UINT8 Reserved
[253 - 139 + 1]; ///< 253-139 Reserved
863 SPD4_CYCLIC_REDUNDANCY_CODE Crc
; ///< 254-255 Cyclical Redundancy Code (CRC)
864 } SPD4_MODULE_REGISTERED
;
867 SPD4_LRDIMM_MODULE_NOMINAL_HEIGHT ModuleNominalHeight
; ///< 128 Module Nominal Height
868 SPD4_LRDIMM_MODULE_NOMINAL_THICKNESS ModuleMaximumThickness
; ///< 129 Module Maximum Thickness
869 SPD4_LRDIMM_REFERENCE_RAW_CARD ReferenceRawCardUsed
; ///< 130 Reference Raw Card Used
870 SPD4_LRDIMM_MODULE_ATTRIBUTES DimmModuleAttributes
; ///< 131 DIMM Module Attributes
871 SPD4_LRDIMM_THERMAL_HEAT_SPREADER_SOLUTION ThermalHeatSpreaderSolution
; ///< 132 RDIMM Thermal Heat Spreader Solution
872 SPD4_MANUFACTURER_ID_CODE RegisterManufacturerIdCode
; ///< 133-134 Register Manufacturer ID Code
873 SPD4_LRDIMM_REGISTER_REVISION_NUMBER RegisterRevisionNumber
; ///< 135 Register Revision Number
874 SPD4_LRDIMM_ADDRESS_MAPPING_FROM_REGISTER_TO_DRAM AddressMappingFromRegisterToDram
; ///< 136 Address Mapping from Register to DRAM
875 SPD4_LRDIMM_REGISTER_OUTPUT_DRIVE_STRENGTH_FOR_CONTROL_COMMAND_ADDRESS RegisterOutputDriveStrengthForControlCommandAddress
; ///< 137 Register Output Drive Strength for Control and Command Address
876 SPD4_LRDIMM_REGISTER_OUTPUT_DRIVE_STRENGTH_FOR_CLOCK RegisterOutputDriveStrengthForClock
; ///< 138 Register Output Drive Strength for Clock
877 SPD4_LRDIMM_DATA_BUFFER_REVISION_NUMBER DataBufferRevisionNumber
; ///< 139 Data Buffer Revision Number
878 SPD4_LRDIMM_DRAM_VREFDQ_FOR_PACKAGE_RANK DramVrefDQForPackageRank0
; ///< 140 DRAM VrefDQ for Package Rank 0
879 SPD4_LRDIMM_DRAM_VREFDQ_FOR_PACKAGE_RANK DramVrefDQForPackageRank1
; ///< 141 DRAM VrefDQ for Package Rank 1
880 SPD4_LRDIMM_DRAM_VREFDQ_FOR_PACKAGE_RANK DramVrefDQForPackageRank2
; ///< 142 DRAM VrefDQ for Package Rank 2
881 SPD4_LRDIMM_DRAM_VREFDQ_FOR_PACKAGE_RANK DramVrefDQForPackageRank3
; ///< 143 DRAM VrefDQ for Package Rank 3
882 SPD4_LRDIMM_DATA_BUFFER_VREFDQ_FOR_DRAM_INTERFACE DataBufferVrefDQForDramInterface
; ///< 144 Data Buffer VrefDQ for DRAM Interface
883 SPD4_LRDIMM_DATA_BUFFER_MDQ_DRIVE_STRENGTH_RTT_FOR_DATA_RATE DataBufferMdqDriveStrengthRttForDataRateLe1866
; ///< 145 Data Buffer MDQ Drive Strength and RTT for data rate <= 1866
884 SPD4_LRDIMM_DATA_BUFFER_MDQ_DRIVE_STRENGTH_RTT_FOR_DATA_RATE DataBufferMdqDriveStrengthRttForDataRateLe2400
; ///< 146 Data Buffer MDQ Drive Strength and RTT for data rate <=2400
885 SPD4_LRDIMM_DATA_BUFFER_MDQ_DRIVE_STRENGTH_RTT_FOR_DATA_RATE DataBufferMdqDriveStrengthRttForDataRateLe3200
; ///< 147 Data Buffer MDQ Drive Strength and RTT for data rate <=3200
886 SPD4_LRDIMM_DRAM_DRIVE_STRENGTH DramDriveStrength
; ///< 148 DRAM Drive Strength
887 SPD4_LRDIMM_DRAM_ODT_RTT_WR_RTT_NOM_FOR_DATA_RATE DramOdtRttWrRttNomForDataRateLe1866
; ///< 149 DRAM ODT (RTT_WR and RTT_NOM) for data rate <= 1866
888 SPD4_LRDIMM_DRAM_ODT_RTT_WR_RTT_NOM_FOR_DATA_RATE DramOdtRttWrRttNomForDataRateLe2400
; ///< 150 DRAM ODT (RTT_WR and RTT_NOM) for data rate <= 2400
889 SPD4_LRDIMM_DRAM_ODT_RTT_WR_RTT_NOM_FOR_DATA_RATE DramOdtRttWrRttNomForDataRateLe3200
; ///< 151 DRAM ODT (RTT_WR and RTT_NOM) for data rate <= 3200
890 SPD4_LRDIMM_DRAM_ODT_RTT_PARK_FOR_DATA_RATE DramOdtRttParkForDataRateLe1866
; ///< 152 DRAM ODT (RTT_PARK) for data rate <= 1866
891 SPD4_LRDIMM_DRAM_ODT_RTT_PARK_FOR_DATA_RATE DramOdtRttParkForDataRateLe2400
; ///< 153 DRAM ODT (RTT_PARK) for data rate <= 2400
892 SPD4_LRDIMM_DRAM_ODT_RTT_PARK_FOR_DATA_RATE DramOdtRttParkForDataRateLe3200
; ///< 154 DRAM ODT (RTT_PARK) for data rate <= 3200
893 SPD4_LRDIMM_DATA_BUFFER_VREFDQ_FOR_DRAM_INTERFACE_RANGE DataBufferVrefDQForDramInterfaceRange
; ///< 155 Data Buffer VrefDQ for DRAM Interface Range
894 SPD4_LRDIMM_DATA_BUFFER_DQ_DECISION_FEEDBACK_EQUALIZATION DataBufferDqDecisionFeedbackEqualization
; ///< 156 Data Buffer DQ Decision Feedback Equalization
895 UINT8 Reserved
[253 - 157 + 1]; ///< 253-132 Reserved
896 SPD4_CYCLIC_REDUNDANCY_CODE Crc
; ///< 254-255 Cyclical Redundancy Code (CRC)
897 } SPD4_MODULE_LOADREDUCED
;
900 UINT8 Reserved0
[191 - 128 + 1]; ///< 128-191 Reserved
901 SPD4_NVDIMM_MODULE_PRODUCT_IDENTIFIER ModuleProductIdentifier
; ///< 192-193 Module Product Identifier
902 SPD4_NVDIMM_SUBSYSTEM_CONTROLLER_MANUFACTURER_ID_CODE SubsystemControllerManufacturerIdCode
; ///< 194-195 Subsystem Controller Manufacturer's ID Code
903 SPD4_NVDIMM_SUBSYSTEM_CONTROLLER_IDENTIFIER SubsystemControllerIdentifier
; ///< 196-197 Subsystem Controller Identifier
904 SPD4_NVDIMM_SUBSYSTEM_CONTROLLER_REVISION_CODE SubsystemControllerRevisionCode
; ///< 198 Subsystem Controller Revision Code
905 SPD4_NVDIMM_REFERENCE_RAW_CARD ReferenceRawCardUsed
; ///< 199 Reference Raw Card Used
906 SPD4_NVDIMM_MODULE_CHARACTERISTICS ModuleCharacteristics
; ///< 200 Module Characteristics
907 SPD4_NVDIMM_HYBRID_MODULE_MEDIA_TYPES HybridModuleMediaTypes
; ///< 201-202 Hybrid Module Media Types
908 SPD4_NVDIMM_MAXIMUM_NONVOLATILE_MEMORY_INITIALIZATION_TIME MaximumNonVolatileMemoryInitializationTime
; ///< 203 Maximum Non-Volatile Memory Initialization Time
909 SPD4_NVDIMM_FUNCTION_INTERFACE_DESCRIPTOR FunctionInterfaceDescriptors
[8]; ///< 204-219 Function Interface Descriptors
910 UINT8 Reserved
[253 - 220 + 1]; ///< 220-253 Reserved
911 SPD4_CYCLIC_REDUNDANCY_CODE Crc
; ///< 254-255 Cyclical Redundancy Code (CRC)
912 } SPD4_MODULE_NVDIMM
;
915 SPD4_MODULE_UNBUFFERED Unbuffered
; ///< 128-255 Unbuffered Memory Module Types
916 SPD4_MODULE_REGISTERED Registered
; ///< 128-255 Registered Memory Module Types
917 SPD4_MODULE_LOADREDUCED LoadReduced
; ///< 128-255 Load Reduced Memory Module Types
918 SPD4_MODULE_NVDIMM NonVolatile
; ///< 128-255 Non-Volatile (NVDIMM-N) Hybrid Memory Parameters
919 } SPD4_MODULE_SPECIFIC
;
922 UINT8 ModulePartNumber
[348 - 329 + 1]; ///< 329-348 Module Part Number
923 } SPD4_MODULE_PART_NUMBER
;
926 UINT8 ManufacturerSpecificData
[381 - 353 + 1]; ///< 353-381 Manufacturer's Specific Data
927 } SPD4_MANUFACTURER_SPECIFIC
;
929 typedef UINT8 SPD4_MODULE_REVISION_CODE
;///< 349 Module Revision Code
930 typedef UINT8 SPD4_DRAM_STEPPING
; ///< 352 Dram Stepping
933 SPD4_UNIQUE_MODULE_ID ModuleId
; ///< 320-328 Unique Module ID
934 SPD4_MODULE_PART_NUMBER ModulePartNumber
; ///< 329-348 Module Part Number
935 SPD4_MODULE_REVISION_CODE ModuleRevisionCode
; ///< 349 Module Revision Code
936 SPD4_MANUFACTURER_ID_CODE DramIdCode
; ///< 350-351 Dram Manufacturer ID Code
937 SPD4_DRAM_STEPPING DramStepping
; ///< 352 Dram Stepping
938 SPD4_MANUFACTURER_SPECIFIC ManufacturerSpecificData
; ///< 353-381 Manufacturer's Specific Data
939 UINT8 Reserved
[2]; ///< 382-383 Reserved
940 } SPD4_MANUFACTURING_DATA
;
943 UINT8 Reserved
[511 - 384 + 1]; ///< 384-511 Unbuffered Memory Module Types
944 } SPD4_END_USER_SECTION
;
947 /// DDR4 Serial Presence Detect structure
950 SPD4_BASE_SECTION Base
; ///< 0-127 Base Configuration and DRAM Parameters
951 SPD4_MODULE_SPECIFIC Module
; ///< 128-255 Module-Specific Section
952 UINT8 Reserved
[319 - 256 + 1]; ///< 256-319 Reserved
953 SPD4_MANUFACTURING_DATA ManufactureInfo
; ///< 320-383 Manufacturing Information
954 SPD4_END_USER_SECTION EndUser
; ///< 384-511 End User Programmable