2 This file contains definitions for SPD DDR4.
4 Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
5 SPDX-License-Identifier: BSD-2-Clause-Patent
7 @par Revision Reference:
8 - Serial Presence Detect (SPD) for DDR4 SDRAM Modules Document Release 4
9 http://www.jedec.org/standards-documents/docs/spd412l-4
12 #ifndef _SDRAM_SPD_DDR4_H_
13 #define _SDRAM_SPD_DDR4_H_
15 #pragma pack (push, 1)
19 UINT8 BytesUsed
: 4; ///< Bits 3:0
20 UINT8 BytesTotal
: 3; ///< Bits 6:4
21 UINT8 CrcCoverage
: 1; ///< Bits 7:7
24 } SPD4_DEVICE_DESCRIPTION_STRUCT
;
28 UINT8 Minor
: 4; ///< Bits 3:0
29 UINT8 Major
: 4; ///< Bits 7:4
32 } SPD4_REVISION_STRUCT
;
36 UINT8 Type
: 8; ///< Bits 7:0
39 } SPD4_DRAM_DEVICE_TYPE_STRUCT
;
43 UINT8 ModuleType
: 4; ///< Bits 3:0
44 UINT8 HybridMedia
: 3; ///< Bits 6:4
45 UINT8 Hybrid
: 1; ///< Bits 7:7
48 } SPD4_MODULE_TYPE_STRUCT
;
52 UINT8 Density
: 4; ///< Bits 3:0
53 UINT8 BankAddress
: 2; ///< Bits 5:4
54 UINT8 BankGroup
: 2; ///< Bits 7:6
57 } SPD4_SDRAM_DENSITY_BANKS_STRUCT
;
61 UINT8 ColumnAddress
: 3; ///< Bits 2:0
62 UINT8 RowAddress
: 3; ///< Bits 5:3
63 UINT8 Reserved
: 2; ///< Bits 7:6
66 } SPD4_SDRAM_ADDRESSING_STRUCT
;
70 UINT8 SignalLoading
: 2; ///< Bits 1:0
71 UINT8 Reserved
: 2; ///< Bits 3:2
72 UINT8 DieCount
: 3; ///< Bits 6:4
73 UINT8 SdramPackageType
: 1; ///< Bits 7:7
76 } SPD4_PRIMARY_SDRAM_PACKAGE_TYPE_STRUCT
;
80 UINT8 MaximumActivateCount
: 4; ///< Bits 3:0
81 UINT8 MaximumActivateWindow
: 2; ///< Bits 5:4
82 UINT8 Reserved
: 2; ///< Bits 7:6
85 } SPD4_SDRAM_OPTIONAL_FEATURES_STRUCT
;
89 UINT8 Reserved
: 8; ///< Bits 7:0
92 } SPD4_SDRAM_THERMAL_REFRESH_STRUCT
;
96 UINT8 Reserved
: 5; ///< Bits 4:0
97 UINT8 SoftPPR
: 1; ///< Bits 5:5
98 UINT8 PostPackageRepair
: 2; ///< Bits 7:6
101 } SPD4_OTHER_SDRAM_OPTIONAL_FEATURES_STRUCT
;
105 UINT8 SignalLoading
: 2; ///< Bits 1:0
106 UINT8 DRAMDensityRatio
: 2; ///< Bits 3:2
107 UINT8 DieCount
: 3; ///< Bits 6:4
108 UINT8 SdramPackageType
: 1; ///< Bits 7:7
111 } SPD4_SECONDARY_SDRAM_PACKAGE_TYPE_STRUCT
;
115 UINT8 OperationAt1_20
: 1; ///< Bits 0:0
116 UINT8 EndurantAt1_20
: 1; ///< Bits 1:1
117 UINT8 Reserved
: 6; ///< Bits 7:2
120 } SPD4_MODULE_NOMINAL_VOLTAGE_STRUCT
;
124 UINT8 SdramDeviceWidth
: 3; ///< Bits 2:0
125 UINT8 RankCount
: 3; ///< Bits 5:3
126 UINT8 RankMix
: 1; ///< Bits 6:6
127 UINT8 Reserved
: 1; ///< Bits 7:7
130 } SPD4_MODULE_ORGANIZATION_STRUCT
;
134 UINT8 PrimaryBusWidth
: 3; ///< Bits 2:0
135 UINT8 BusWidthExtension
: 2; ///< Bits 4:3
136 UINT8 Reserved
: 3; ///< Bits 7:5
139 } SPD4_MODULE_MEMORY_BUS_WIDTH_STRUCT
;
143 UINT8 Reserved
: 7; ///< Bits 6:0
144 UINT8 ThermalSensorPresence
: 1; ///< Bits 7:7
147 } SPD4_MODULE_THERMAL_SENSOR_STRUCT
;
151 UINT8 ExtendedBaseModuleType
: 4; ///< Bits 3:0
152 UINT8 Reserved
: 4; ///< Bits 7:4
155 } SPD4_EXTENDED_MODULE_TYPE_STRUCT
;
159 UINT8 Fine
: 2; ///< Bits 1:0
160 UINT8 Medium
: 2; ///< Bits 3:2
161 UINT8 Reserved
: 4; ///< Bits 7:4
164 } SPD4_TIMEBASE_STRUCT
;
168 UINT8 tCKmin
: 8; ///< Bits 7:0
171 } SPD4_TCK_MIN_MTB_STRUCT
;
175 UINT8 tCKmax
: 8; ///< Bits 7:0
178 } SPD4_TCK_MAX_MTB_STRUCT
;
182 UINT32 Cl7
: 1; ///< Bits 0:0
183 UINT32 Cl8
: 1; ///< Bits 1:1
184 UINT32 Cl9
: 1; ///< Bits 2:2
185 UINT32 Cl10
: 1; ///< Bits 3:3
186 UINT32 Cl11
: 1; ///< Bits 4:4
187 UINT32 Cl12
: 1; ///< Bits 5:5
188 UINT32 Cl13
: 1; ///< Bits 6:6
189 UINT32 Cl14
: 1; ///< Bits 7:7
190 UINT32 Cl15
: 1; ///< Bits 8:8
191 UINT32 Cl16
: 1; ///< Bits 9:9
192 UINT32 Cl17
: 1; ///< Bits 10:10
193 UINT32 Cl18
: 1; ///< Bits 11:11
194 UINT32 Cl19
: 1; ///< Bits 12:12
195 UINT32 Cl20
: 1; ///< Bits 13:13
196 UINT32 Cl21
: 1; ///< Bits 14:14
197 UINT32 Cl22
: 1; ///< Bits 15:15
198 UINT32 Cl23
: 1; ///< Bits 16:16
199 UINT32 Cl24
: 1; ///< Bits 17:17
200 UINT32 Cl25
: 1; ///< Bits 18:18
201 UINT32 Cl26
: 1; ///< Bits 19:19
202 UINT32 Cl27
: 1; ///< Bits 20:20
203 UINT32 Cl28
: 1; ///< Bits 21:21
204 UINT32 Cl29
: 1; ///< Bits 22:22
205 UINT32 Cl30
: 1; ///< Bits 23:23
206 UINT32 Cl31
: 1; ///< Bits 24:24
207 UINT32 Cl32
: 1; ///< Bits 25:25
208 UINT32 Cl33
: 1; ///< Bits 26:26
209 UINT32 Cl34
: 1; ///< Bits 27:27
210 UINT32 Cl35
: 1; ///< Bits 28:28
211 UINT32 Cl36
: 1; ///< Bits 29:29
212 UINT32 Reserved
: 1; ///< Bits 30:30
213 UINT32 ClRange
: 1; ///< Bits 31:31
216 UINT32 Cl23
: 1; ///< Bits 0:0
217 UINT32 Cl24
: 1; ///< Bits 1:1
218 UINT32 Cl25
: 1; ///< Bits 2:2
219 UINT32 Cl26
: 1; ///< Bits 3:3
220 UINT32 Cl27
: 1; ///< Bits 4:4
221 UINT32 Cl28
: 1; ///< Bits 5:5
222 UINT32 Cl29
: 1; ///< Bits 6:6
223 UINT32 Cl30
: 1; ///< Bits 7:7
224 UINT32 Cl31
: 1; ///< Bits 8:8
225 UINT32 Cl32
: 1; ///< Bits 9:9
226 UINT32 Cl33
: 1; ///< Bits 10:10
227 UINT32 Cl34
: 1; ///< Bits 11:11
228 UINT32 Cl35
: 1; ///< Bits 12:12
229 UINT32 Cl36
: 1; ///< Bits 13:13
230 UINT32 Cl37
: 1; ///< Bits 14:14
231 UINT32 Cl38
: 1; ///< Bits 15:15
232 UINT32 Cl39
: 1; ///< Bits 16:16
233 UINT32 Cl40
: 1; ///< Bits 17:17
234 UINT32 Cl41
: 1; ///< Bits 18:18
235 UINT32 Cl42
: 1; ///< Bits 19:19
236 UINT32 Cl43
: 1; ///< Bits 20:20
237 UINT32 Cl44
: 1; ///< Bits 21:21
238 UINT32 Cl45
: 1; ///< Bits 22:22
239 UINT32 Cl46
: 1; ///< Bits 23:23
240 UINT32 Cl47
: 1; ///< Bits 24:24
241 UINT32 Cl48
: 1; ///< Bits 25:25
242 UINT32 Cl49
: 1; ///< Bits 26:26
243 UINT32 Cl50
: 1; ///< Bits 27:27
244 UINT32 Cl51
: 1; ///< Bits 28:28
245 UINT32 Cl52
: 1; ///< Bits 29:29
246 UINT32 Reserved
: 1; ///< Bits 30:30
247 UINT32 ClRange
: 1; ///< Bits 31:31
252 } SPD4_CAS_LATENCIES_SUPPORTED_STRUCT
;
256 UINT8 tAAmin
: 8; ///< Bits 7:0
259 } SPD4_TAA_MIN_MTB_STRUCT
;
263 UINT8 tRCDmin
: 8; ///< Bits 7:0
266 } SPD4_TRCD_MIN_MTB_STRUCT
;
270 UINT8 tRPmin
: 8; ///< Bits 7:0
273 } SPD4_TRP_MIN_MTB_STRUCT
;
277 UINT8 tRASminUpper
: 4; ///< Bits 3:0
278 UINT8 tRCminUpper
: 4; ///< Bits 7:4
281 } SPD4_TRAS_TRC_MIN_MTB_STRUCT
;
285 UINT8 tRASmin
: 8; ///< Bits 7:0
288 } SPD4_TRAS_MIN_MTB_STRUCT
;
292 UINT8 tRCmin
: 8; ///< Bits 7:0
295 } SPD4_TRC_MIN_MTB_STRUCT
;
299 UINT16 tRFCmin
: 16; ///< Bits 15:0
303 } SPD4_TRFC_MIN_MTB_STRUCT
;
307 UINT8 tFAWminUpper
: 4; ///< Bits 3:0
308 UINT8 Reserved
: 4; ///< Bits 7:4
311 } SPD4_TFAW_MIN_MTB_UPPER_STRUCT
;
315 UINT8 tFAWmin
: 8; ///< Bits 7:0
318 } SPD4_TFAW_MIN_MTB_STRUCT
;
322 UINT8 tRRDmin
: 8; ///< Bits 7:0
325 } SPD4_TRRD_MIN_MTB_STRUCT
;
329 UINT8 tCCDmin
: 8; ///< Bits 7:0
332 } SPD4_TCCD_MIN_MTB_STRUCT
;
336 UINT8 tWRminMostSignificantNibble
: 4; ///< Bits 3:0
337 UINT8 Reserved
: 4; ///< Bits 7:4
340 } SPD4_TWR_UPPER_NIBBLE_STRUCT
;
344 UINT8 tWRmin
: 8; ///< Bits 7:0
347 } SPD4_TWR_MIN_MTB_STRUCT
;
351 UINT8 tWTR_SminMostSignificantNibble
: 4; ///< Bits 3:0
352 UINT8 tWTR_LminMostSignificantNibble
: 4; ///< Bits 7:4
355 } SPD4_TWTR_UPPER_NIBBLE_STRUCT
;
359 UINT8 tWTRmin
: 8; ///< Bits 7:0
362 } SPD4_TWTR_MIN_MTB_STRUCT
;
366 UINT8 BitOrderatSDRAM
: 5; ///< Bits 4:0
367 UINT8 WiredtoUpperLowerNibble
: 1; ///< Bits 5:5
368 UINT8 PackageRankMap
: 2; ///< Bits 7:6
371 } SPD4_CONNECTOR_BIT_MAPPING_BYTE_STRUCT
;
375 INT8 tCCDminFine
: 8; ///< Bits 7:0
378 } SPD4_TCCD_MIN_FTB_STRUCT
;
382 INT8 tRRDminFine
: 8; ///< Bits 7:0
385 } SPD4_TRRD_MIN_FTB_STRUCT
;
389 INT8 tRCminFine
: 8; ///< Bits 7:0
392 } SPD4_TRC_MIN_FTB_STRUCT
;
396 INT8 tRPminFine
: 8; ///< Bits 7:0
399 } SPD4_TRP_MIN_FTB_STRUCT
;
403 INT8 tRCDminFine
: 8; ///< Bits 7:0
406 } SPD4_TRCD_MIN_FTB_STRUCT
;
410 INT8 tAAminFine
: 8; ///< Bits 7:0
413 } SPD4_TAA_MIN_FTB_STRUCT
;
417 INT8 tCKmaxFine
: 8; ///< Bits 7:0
420 } SPD4_TCK_MAX_FTB_STRUCT
;
424 INT8 tCKminFine
: 8; ///< Bits 7:0
427 } SPD4_TCK_MIN_FTB_STRUCT
;
431 UINT8 Height
: 5; ///< Bits 4:0
432 UINT8 RawCardExtension
: 3; ///< Bits 7:5
435 } SPD4_UNBUF_MODULE_NOMINAL_HEIGHT
;
439 UINT8 FrontThickness
: 4; ///< Bits 3:0
440 UINT8 BackThickness
: 4; ///< Bits 7:4
443 } SPD4_UNBUF_MODULE_NOMINAL_THICKNESS
;
447 UINT8 Card
: 5; ///< Bits 4:0
448 UINT8 Revision
: 2; ///< Bits 6:5
449 UINT8 Extension
: 1; ///< Bits 7:7
452 } SPD4_UNBUF_REFERENCE_RAW_CARD
;
456 UINT8 MappingRank1
: 1; ///< Bits 0:0
457 UINT8 Reserved
: 7; ///< Bits 7:1
460 } SPD4_UNBUF_ADDRESS_MAPPING
;
464 UINT8 Height
: 5; ///< Bits 4:0
465 UINT8 Reserved
: 3; ///< Bits 7:5
468 } SPD4_RDIMM_MODULE_NOMINAL_HEIGHT
;
472 UINT8 FrontThickness
: 4; ///< Bits 3:0
473 UINT8 BackThickness
: 4; ///< Bits 7:4
476 } SPD4_RDIMM_MODULE_NOMINAL_THICKNESS
;
480 UINT8 Card
: 5; ///< Bits 4:0
481 UINT8 Revision
: 2; ///< Bits 6:5
482 UINT8 Extension
: 1; ///< Bits 7:7
485 } SPD4_RDIMM_REFERENCE_RAW_CARD
;
489 UINT8 RegisterCount
: 2; ///< Bits 1:0
490 UINT8 DramRowCount
: 2; ///< Bits 3:2
491 UINT8 RegisterType
: 4; ///< Bits 7:4
494 } SPD4_RDIMM_MODULE_ATTRIBUTES
;
498 UINT8 HeatSpreaderThermalCharacteristics
: 7; ///< Bits 6:0
499 UINT8 HeatSpreaderSolution
: 1; ///< Bits 7:7
502 } SPD4_RDIMM_THERMAL_HEAT_SPREADER_SOLUTION
;
506 UINT16 ContinuationCount
: 7; ///< Bits 6:0
507 UINT16 ContinuationParity
: 1; ///< Bits 7:7
508 UINT16 LastNonZeroByte
: 8; ///< Bits 15:8
512 } SPD4_MANUFACTURER_ID_CODE
;
516 UINT8 RegisterRevisionNumber
; ///< Bits 7:0
519 } SPD4_RDIMM_REGISTER_REVISION_NUMBER
;
523 UINT8 Rank1Mapping
: 1; ///< Bits 0:0
524 UINT8 Reserved
: 7; ///< Bits 7:1
527 } SPD4_RDIMM_ADDRESS_MAPPING_FROM_REGISTER_TO_DRAM
;
531 UINT8 Cke
: 2; ///< Bits 1:0
532 UINT8 Odt
: 2; ///< Bits 3:2
533 UINT8 CommandAddress
: 2; ///< Bits 5:4
534 UINT8 ChipSelect
: 2; ///< Bits 7:6
537 } SPD4_RDIMM_REGISTER_OUTPUT_DRIVE_STRENGTH_FOR_CONTROL_COMMAND_ADDRESS
;
541 UINT8 Y0Y2
: 2; ///< Bits 1:0
542 UINT8 Y1Y3
: 2; ///< Bits 3:2
543 UINT8 Reserved0
: 2; ///< Bits 5:4
544 UINT8 RcdOutputSlewRateControl
: 1; ///< Bits 6:6
545 UINT8 Reserved1
: 1; ///< Bits 7:7
548 } SPD4_RDIMM_REGISTER_OUTPUT_DRIVE_STRENGTH_FOR_CLOCK
;
552 UINT8 Height
: 5; ///< Bits 4:0
553 UINT8 Reserved
: 3; ///< Bits 7:5
556 } SPD4_LRDIMM_MODULE_NOMINAL_HEIGHT
;
560 UINT8 FrontThickness
: 4; ///< Bits 3:0
561 UINT8 BackThickness
: 4; ///< Bits 7:4
564 } SPD4_LRDIMM_MODULE_NOMINAL_THICKNESS
;
568 UINT8 Card
: 5; ///< Bits 4:0
569 UINT8 Revision
: 2; ///< Bits 6:5
570 UINT8 Extension
: 1; ///< Bits 7:7
573 } SPD4_LRDIMM_REFERENCE_RAW_CARD
;
577 UINT8 RegisterCount
: 2; ///< Bits 1:0
578 UINT8 DramRowCount
: 2; ///< Bits 3:2
579 UINT8 RegisterType
: 4; ///< Bits 7:4
582 } SPD4_LRDIMM_MODULE_ATTRIBUTES
;
586 UINT8 HeatSpreaderThermalCharacteristics
: 7; ///< Bits 6:0
587 UINT8 HeatSpreaderSolution
: 1; ///< Bits 7:7
590 } SPD4_LRDIMM_THERMAL_HEAT_SPREADER_SOLUTION
;
594 UINT8 RegisterRevisionNumber
; ///< Bits 7:0
597 } SPD4_LRDIMM_REGISTER_REVISION_NUMBER
;
601 UINT8 Rank1Mapping
: 1; ///< Bits 0:0
602 UINT8 Reserved
: 7; ///< Bits 7:1
605 } SPD4_LRDIMM_ADDRESS_MAPPING_FROM_REGISTER_TO_DRAM
;
609 UINT8 Cke
: 2; ///< Bits 1:0
610 UINT8 Odt
: 2; ///< Bits 3:2
611 UINT8 CommandAddress
: 2; ///< Bits 5:4
612 UINT8 ChipSelect
: 2; ///< Bits 7:6
615 } SPD4_LRDIMM_REGISTER_OUTPUT_DRIVE_STRENGTH_FOR_CONTROL_COMMAND_ADDRESS
;
619 UINT8 Y0Y2
: 2; ///< Bits 1:0
620 UINT8 Y1Y3
: 2; ///< Bits 3:2
621 UINT8 Reserved0
: 2; ///< Bits 5:4
622 UINT8 RcdOutputSlewRateControl
: 1; ///< Bits 6:6
623 UINT8 Reserved1
: 1; ///< Bits 7:7
626 } SPD4_LRDIMM_REGISTER_OUTPUT_DRIVE_STRENGTH_FOR_CLOCK
;
629 UINT8 DataBufferRevisionNumber
;
630 } SPD4_LRDIMM_DATA_BUFFER_REVISION_NUMBER
;
634 UINT8 DramVrefDQForPackageRank0
: 6; ///< Bits 5:0
635 UINT8 Reserved
: 2; ///< Bits 7:6
638 } SPD4_LRDIMM_DRAM_VREFDQ_FOR_PACKAGE_RANK
;
641 UINT8 DataBufferVrefDQforDramInterface
;
642 } SPD4_LRDIMM_DATA_BUFFER_VREFDQ_FOR_DRAM_INTERFACE
;
646 UINT8 DramInterfaceMdqDriveStrength
: 4; ///< Bits 3:0
647 UINT8 DramInterfaceMdqReadTerminationStrength
: 4; ///< Bits 7:4
650 } SPD4_LRDIMM_DATA_BUFFER_MDQ_DRIVE_STRENGTH_RTT_FOR_DATA_RATE
;
654 UINT8 DataRateLe1866
: 2; ///< Bits 1:0
655 UINT8 DataRateLe2400
: 2; ///< Bits 3:2
656 UINT8 DataRateLe3200
: 2; ///< Bits 5:4
657 UINT8 Reserved
: 2; ///< Bits 7:6
660 } SPD4_LRDIMM_DRAM_DRIVE_STRENGTH
;
664 UINT8 Rtt_Nom
: 3; ///< Bits 2:0
665 UINT8 Rtt_WR
: 3; ///< Bits 5:3
666 UINT8 Reserved
: 2; ///< Bits 7:6
669 } SPD4_LRDIMM_DRAM_ODT_RTT_WR_RTT_NOM_FOR_DATA_RATE
;
673 UINT8 PackageRanks0_1
: 3; ///< Bits 2:0
674 UINT8 PackageRanks2_3
: 3; ///< Bits 5:3
675 UINT8 Reserved
: 2; ///< Bits 7:6
678 } SPD4_LRDIMM_DRAM_ODT_RTT_PARK_FOR_DATA_RATE
;
682 UINT8 Rank0
: 1; ///< Bits 0:0
683 UINT8 Rank1
: 1; ///< Bits 1:1
684 UINT8 Rank2
: 1; ///< Bits 2:2
685 UINT8 Rank3
: 1; ///< Bits 3:3
686 UINT8 DataBuffer
: 1; ///< Bits 4:4
687 UINT8 Reserved
: 3; ///< Bits 7:5
690 } SPD4_LRDIMM_DATA_BUFFER_VREFDQ_FOR_DRAM_INTERFACE_RANGE
;
694 UINT8 DataBufferGainAdjustment
: 1; ///< Bits 0:0
695 UINT8 DataBufferDfe
: 1; ///< Bits 1:1
696 UINT8 Reserved
: 6; ///< Bits 7:2
699 } SPD4_LRDIMM_DATA_BUFFER_DQ_DECISION_FEEDBACK_EQUALIZATION
;
701 typedef UINT16 SPD4_NVDIMM_MODULE_PRODUCT_IDENTIFIER
;
705 UINT16 ContinuationCount
: 7; ///< Bits 6:0
706 UINT16 ContinuationParity
: 1; ///< Bits 7:7
707 UINT16 LastNonZeroByte
: 8; ///< Bits 15:8
711 } SPD4_NVDIMM_SUBSYSTEM_CONTROLLER_MANUFACTURER_ID_CODE
;
713 typedef UINT16 SPD4_NVDIMM_SUBSYSTEM_CONTROLLER_IDENTIFIER
;
715 typedef UINT8 SPD4_NVDIMM_SUBSYSTEM_CONTROLLER_REVISION_CODE
;
719 UINT8 Card
: 5; ///< Bits 4:0
720 UINT8 Revision
: 2; ///< Bits 6:5
721 UINT8 Extension
: 1; ///< Bits 7:7
724 } SPD4_NVDIMM_REFERENCE_RAW_CARD
;
728 UINT8 Reserved
: 4; ///< Bits 3:0
729 UINT8 Extension
: 4; ///< Bits 7:4
732 } SPD4_NVDIMM_MODULE_CHARACTERISTICS
;
737 } SPD4_NVDIMM_HYBRID_MODULE_MEDIA_TYPES
;
739 typedef UINT8 SPD4_NVDIMM_MAXIMUM_NONVOLATILE_MEMORY_INITIALIZATION_TIME
;
743 UINT16 FunctionInterface
: 5; ///< Bits 4:0
744 UINT16 FunctionClass
: 5; ///< Bits 9:5
745 UINT16 BlockOffset
: 4; ///< Bits 13:10
746 UINT16 Reserved
: 1; ///< Bits 14:14
747 UINT16 Implemented
: 1; ///< Bits 15:15
751 } SPD4_NVDIMM_FUNCTION_INTERFACE_DESCRIPTOR
;
754 UINT8 Year
; ///< Year represented in BCD (00h = 2000)
755 UINT8 Week
; ///< Year represented in BCD (47h = week 47)
756 } SPD4_MANUFACTURING_DATE
;
760 UINT16 SerialNumber16
[2];
761 UINT8 SerialNumber8
[4];
762 } SPD4_MANUFACTURER_SERIAL_NUMBER
;
765 UINT8 Location
; ///< Module Manufacturing Location
766 } SPD4_MANUFACTURING_LOCATION
;
769 SPD4_MANUFACTURER_ID_CODE IdCode
; ///< Module Manufacturer ID Code
770 SPD4_MANUFACTURING_LOCATION Location
; ///< Module Manufacturing Location
771 SPD4_MANUFACTURING_DATE Date
; ///< Module Manufacturing Year, in BCD (range: 2000-2255)
772 SPD4_MANUFACTURER_SERIAL_NUMBER SerialNumber
; ///< Module Serial Number
773 } SPD4_UNIQUE_MODULE_ID
;
778 } SPD4_CYCLIC_REDUNDANCY_CODE
;
781 SPD4_DEVICE_DESCRIPTION_STRUCT Description
; ///< 0 Number of Serial PD Bytes Written / SPD Device Size / CRC Coverage 1, 2
782 SPD4_REVISION_STRUCT Revision
; ///< 1 SPD Revision
783 SPD4_DRAM_DEVICE_TYPE_STRUCT DramDeviceType
; ///< 2 DRAM Device Type
784 SPD4_MODULE_TYPE_STRUCT ModuleType
; ///< 3 Module Type
785 SPD4_SDRAM_DENSITY_BANKS_STRUCT SdramDensityAndBanks
; ///< 4 SDRAM Density and Banks
786 SPD4_SDRAM_ADDRESSING_STRUCT SdramAddressing
; ///< 5 SDRAM Addressing
787 SPD4_PRIMARY_SDRAM_PACKAGE_TYPE_STRUCT PrimarySdramPackageType
; ///< 6 Primary SDRAM Package Type
788 SPD4_SDRAM_OPTIONAL_FEATURES_STRUCT SdramOptionalFeatures
; ///< 7 SDRAM Optional Features
789 SPD4_SDRAM_THERMAL_REFRESH_STRUCT ThermalAndRefreshOptions
; ///< 8 SDRAM Thermal and Refresh Options
790 SPD4_OTHER_SDRAM_OPTIONAL_FEATURES_STRUCT OtherOptionalFeatures
; ///< 9 Other SDRAM Optional Features
791 SPD4_SECONDARY_SDRAM_PACKAGE_TYPE_STRUCT SecondarySdramPackageType
; ///< 10 Secondary SDRAM Package Type
792 SPD4_MODULE_NOMINAL_VOLTAGE_STRUCT ModuleNominalVoltage
; ///< 11 Module Nominal Voltage, VDD
793 SPD4_MODULE_ORGANIZATION_STRUCT ModuleOrganization
; ///< 12 Module Organization
794 SPD4_MODULE_MEMORY_BUS_WIDTH_STRUCT ModuleMemoryBusWidth
; ///< 13 Module Memory Bus Width
795 SPD4_MODULE_THERMAL_SENSOR_STRUCT ModuleThermalSensor
; ///< 14 Module Thermal Sensor
796 SPD4_EXTENDED_MODULE_TYPE_STRUCT ExtendedModuleType
; ///< 15 Extended Module Type
797 UINT8 Reserved0
; ///< 16 Reserved
798 SPD4_TIMEBASE_STRUCT Timebase
; ///< 17 Timebases
799 SPD4_TCK_MIN_MTB_STRUCT tCKmin
; ///< 18 SDRAM Minimum Cycle Time (tCKmin)
800 SPD4_TCK_MAX_MTB_STRUCT tCKmax
; ///< 19 SDRAM Maximum Cycle Time (tCKmax)
801 SPD4_CAS_LATENCIES_SUPPORTED_STRUCT CasLatencies
; ///< 20-23 CAS Latencies Supported
802 SPD4_TAA_MIN_MTB_STRUCT tAAmin
; ///< 24 Minimum CAS Latency Time (tAAmin)
803 SPD4_TRCD_MIN_MTB_STRUCT tRCDmin
; ///< 25 Minimum RAS# to CAS# Delay Time (tRCDmin)
804 SPD4_TRP_MIN_MTB_STRUCT tRPmin
; ///< 26 Minimum Row Precharge Delay Time (tRPmin)
805 SPD4_TRAS_TRC_MIN_MTB_STRUCT tRASMintRCMinUpper
; ///< 27 Upper Nibbles for tRAS and tRC
806 SPD4_TRAS_MIN_MTB_STRUCT tRASmin
; ///< 28 Minimum Active to Precharge Delay Time (tRASmin), Least Significant Byte
807 SPD4_TRC_MIN_MTB_STRUCT tRCmin
; ///< 29 Minimum Active to Active/Refresh Delay Time (tRCmin), Least Significant Byte
808 SPD4_TRFC_MIN_MTB_STRUCT tRFC1min
; ///< 30-31 Minimum Refresh Recovery Delay Time (tRFC1min)
809 SPD4_TRFC_MIN_MTB_STRUCT tRFC2min
; ///< 32-33 Minimum Refresh Recovery Delay Time (tRFC2min)
810 SPD4_TRFC_MIN_MTB_STRUCT tRFC4min
; ///< 34-35 Minimum Refresh Recovery Delay Time (tRFC4min)
811 SPD4_TFAW_MIN_MTB_UPPER_STRUCT tFAWMinUpper
; ///< 36 Upper Nibble for tFAW
812 SPD4_TFAW_MIN_MTB_STRUCT tFAWmin
; ///< 37 Minimum Four Activate Window Delay Time (tFAWmin)
813 SPD4_TRRD_MIN_MTB_STRUCT tRRD_Smin
; ///< 38 Minimum Activate to Activate Delay Time (tRRD_Smin), different bank group
814 SPD4_TRRD_MIN_MTB_STRUCT tRRD_Lmin
; ///< 39 Minimum Activate to Activate Delay Time (tRRD_Lmin), same bank group
815 SPD4_TCCD_MIN_MTB_STRUCT tCCD_Lmin
; ///< 40 Minimum CAS to CAS Delay Time (tCCD_Lmin), Same Bank Group
816 SPD4_TWR_UPPER_NIBBLE_STRUCT tWRUpperNibble
; ///< 41 Upper Nibble for tWRmin
817 SPD4_TWR_MIN_MTB_STRUCT tWRmin
; ///< 42 Minimum Write Recovery Time (tWRmin)
818 SPD4_TWTR_UPPER_NIBBLE_STRUCT tWTRUpperNibble
; ///< 43 Upper Nibbles for tWTRmin
819 SPD4_TWTR_MIN_MTB_STRUCT tWTR_Smin
; ///< 44 Minimum Write to Read Time (tWTR_Smin), Different Bank Group
820 SPD4_TWTR_MIN_MTB_STRUCT tWTR_Lmin
; ///< 45 Minimum Write to Read Time (tWTR_Lmin), Same Bank Group
821 UINT8 Reserved1
[59 - 46 + 1]; ///< 46-59 Reserved
822 SPD4_CONNECTOR_BIT_MAPPING_BYTE_STRUCT BitMapping
[77 - 60 + 1]; ///< 60-77 Connector to SDRAM Bit Mapping
823 UINT8 Reserved2
[116 - 78 + 1]; ///< 78-116 Reserved
824 SPD4_TCCD_MIN_FTB_STRUCT tCCD_LminFine
; ///< 117 Fine Offset for Minimum CAS to CAS Delay Time (tCCD_Lmin), same bank group
825 SPD4_TRRD_MIN_FTB_STRUCT tRRD_LminFine
; ///< 118 Fine Offset for Minimum Activate to Activate Delay Time (tRRD_Lmin), different bank group
826 SPD4_TRRD_MIN_FTB_STRUCT tRRD_SminFine
; ///< 119 Fine Offset for Minimum Activate to Activate Delay Time (tRRD_Smin), same bank group
827 SPD4_TRC_MIN_FTB_STRUCT tRCminFine
; ///< 120 Fine Offset for Minimum Active to Active/Refresh Delay Time (tRCmin)
828 SPD4_TRP_MIN_FTB_STRUCT tRPminFine
; ///< 121 Fine Offset for Minimum Row Precharge Delay Time (tRPabmin)
829 SPD4_TRCD_MIN_FTB_STRUCT tRCDminFine
; ///< 122 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin)
830 SPD4_TAA_MIN_FTB_STRUCT tAAminFine
; ///< 123 Fine Offset for Minimum CAS Latency Time (tAAmin)
831 SPD4_TCK_MAX_FTB_STRUCT tCKmaxFine
; ///< 124 Fine Offset for SDRAM Minimum Cycle Time (tCKmax)
832 SPD4_TCK_MIN_FTB_STRUCT tCKminFine
; ///< 125 Fine Offset for SDRAM Maximum Cycle Time (tCKmin)
833 SPD4_CYCLIC_REDUNDANCY_CODE Crc
; ///< 126-127 Cyclical Redundancy Code (CRC)
837 SPD4_UNBUF_MODULE_NOMINAL_HEIGHT ModuleNominalHeight
; ///< 128 Module Nominal Height
838 SPD4_UNBUF_MODULE_NOMINAL_THICKNESS ModuleMaximumThickness
; ///< 129 Module Maximum Thickness
839 SPD4_UNBUF_REFERENCE_RAW_CARD ReferenceRawCardUsed
; ///< 130 Reference Raw Card Used
840 SPD4_UNBUF_ADDRESS_MAPPING AddressMappingEdgeConn
; ///< 131 Address Mapping from Edge Connector to DRAM
841 UINT8 Reserved
[253 - 132 + 1]; ///< 132-253 Reserved
842 SPD4_CYCLIC_REDUNDANCY_CODE Crc
; ///< 254-255 Cyclical Redundancy Code (CRC)
843 } SPD4_MODULE_UNBUFFERED
;
846 SPD4_RDIMM_MODULE_NOMINAL_HEIGHT ModuleNominalHeight
; ///< 128 Module Nominal Height
847 SPD4_RDIMM_MODULE_NOMINAL_THICKNESS ModuleMaximumThickness
; ///< 129 Module Maximum Thickness
848 SPD4_RDIMM_REFERENCE_RAW_CARD ReferenceRawCardUsed
; ///< 130 Reference Raw Card Used
849 SPD4_RDIMM_MODULE_ATTRIBUTES DimmModuleAttributes
; ///< 131 DIMM Module Attributes
850 SPD4_RDIMM_THERMAL_HEAT_SPREADER_SOLUTION DimmThermalHeatSpreaderSolution
; ///< 132 RDIMM Thermal Heat Spreader Solution
851 SPD4_MANUFACTURER_ID_CODE RegisterManufacturerIdCode
; ///< 133-134 Register Manufacturer ID Code
852 SPD4_RDIMM_REGISTER_REVISION_NUMBER RegisterRevisionNumber
; ///< 135 Register Revision Number
853 SPD4_RDIMM_ADDRESS_MAPPING_FROM_REGISTER_TO_DRAM AddressMappingFromRegisterToDRAM
; ///< 136 Address Mapping from Register to DRAM
854 SPD4_RDIMM_REGISTER_OUTPUT_DRIVE_STRENGTH_FOR_CONTROL_COMMAND_ADDRESS RegisterOutputDriveStrengthForControlCommandAddress
; ///< 137 Register Output Drive Strength for Control and Command Address
855 SPD4_RDIMM_REGISTER_OUTPUT_DRIVE_STRENGTH_FOR_CLOCK RegisterOutputDriveStrengthForClock
; ///< 138 Register Output Drive Strength for Clock
856 UINT8 Reserved
[253 - 139 + 1]; ///< 253-139 Reserved
857 SPD4_CYCLIC_REDUNDANCY_CODE Crc
; ///< 254-255 Cyclical Redundancy Code (CRC)
858 } SPD4_MODULE_REGISTERED
;
861 SPD4_LRDIMM_MODULE_NOMINAL_HEIGHT ModuleNominalHeight
; ///< 128 Module Nominal Height
862 SPD4_LRDIMM_MODULE_NOMINAL_THICKNESS ModuleMaximumThickness
; ///< 129 Module Maximum Thickness
863 SPD4_LRDIMM_REFERENCE_RAW_CARD ReferenceRawCardUsed
; ///< 130 Reference Raw Card Used
864 SPD4_LRDIMM_MODULE_ATTRIBUTES DimmModuleAttributes
; ///< 131 DIMM Module Attributes
865 SPD4_LRDIMM_THERMAL_HEAT_SPREADER_SOLUTION ThermalHeatSpreaderSolution
; ///< 132 RDIMM Thermal Heat Spreader Solution
866 SPD4_MANUFACTURER_ID_CODE RegisterManufacturerIdCode
; ///< 133-134 Register Manufacturer ID Code
867 SPD4_LRDIMM_REGISTER_REVISION_NUMBER RegisterRevisionNumber
; ///< 135 Register Revision Number
868 SPD4_LRDIMM_ADDRESS_MAPPING_FROM_REGISTER_TO_DRAM AddressMappingFromRegisterToDram
; ///< 136 Address Mapping from Register to DRAM
869 SPD4_LRDIMM_REGISTER_OUTPUT_DRIVE_STRENGTH_FOR_CONTROL_COMMAND_ADDRESS RegisterOutputDriveStrengthForControlCommandAddress
; ///< 137 Register Output Drive Strength for Control and Command Address
870 SPD4_LRDIMM_REGISTER_OUTPUT_DRIVE_STRENGTH_FOR_CLOCK RegisterOutputDriveStrengthForClock
; ///< 138 Register Output Drive Strength for Clock
871 SPD4_LRDIMM_DATA_BUFFER_REVISION_NUMBER DataBufferRevisionNumber
; ///< 139 Data Buffer Revision Number
872 SPD4_LRDIMM_DRAM_VREFDQ_FOR_PACKAGE_RANK DramVrefDQForPackageRank0
; ///< 140 DRAM VrefDQ for Package Rank 0
873 SPD4_LRDIMM_DRAM_VREFDQ_FOR_PACKAGE_RANK DramVrefDQForPackageRank1
; ///< 141 DRAM VrefDQ for Package Rank 1
874 SPD4_LRDIMM_DRAM_VREFDQ_FOR_PACKAGE_RANK DramVrefDQForPackageRank2
; ///< 142 DRAM VrefDQ for Package Rank 2
875 SPD4_LRDIMM_DRAM_VREFDQ_FOR_PACKAGE_RANK DramVrefDQForPackageRank3
; ///< 143 DRAM VrefDQ for Package Rank 3
876 SPD4_LRDIMM_DATA_BUFFER_VREFDQ_FOR_DRAM_INTERFACE DataBufferVrefDQForDramInterface
; ///< 144 Data Buffer VrefDQ for DRAM Interface
877 SPD4_LRDIMM_DATA_BUFFER_MDQ_DRIVE_STRENGTH_RTT_FOR_DATA_RATE DataBufferMdqDriveStrengthRttForDataRateLe1866
; ///< 145 Data Buffer MDQ Drive Strength and RTT for data rate <= 1866
878 SPD4_LRDIMM_DATA_BUFFER_MDQ_DRIVE_STRENGTH_RTT_FOR_DATA_RATE DataBufferMdqDriveStrengthRttForDataRateLe2400
; ///< 146 Data Buffer MDQ Drive Strength and RTT for data rate <=2400
879 SPD4_LRDIMM_DATA_BUFFER_MDQ_DRIVE_STRENGTH_RTT_FOR_DATA_RATE DataBufferMdqDriveStrengthRttForDataRateLe3200
; ///< 147 Data Buffer MDQ Drive Strength and RTT for data rate <=3200
880 SPD4_LRDIMM_DRAM_DRIVE_STRENGTH DramDriveStrength
; ///< 148 DRAM Drive Strength
881 SPD4_LRDIMM_DRAM_ODT_RTT_WR_RTT_NOM_FOR_DATA_RATE DramOdtRttWrRttNomForDataRateLe1866
; ///< 149 DRAM ODT (RTT_WR and RTT_NOM) for data rate <= 1866
882 SPD4_LRDIMM_DRAM_ODT_RTT_WR_RTT_NOM_FOR_DATA_RATE DramOdtRttWrRttNomForDataRateLe2400
; ///< 150 DRAM ODT (RTT_WR and RTT_NOM) for data rate <= 2400
883 SPD4_LRDIMM_DRAM_ODT_RTT_WR_RTT_NOM_FOR_DATA_RATE DramOdtRttWrRttNomForDataRateLe3200
; ///< 151 DRAM ODT (RTT_WR and RTT_NOM) for data rate <= 3200
884 SPD4_LRDIMM_DRAM_ODT_RTT_PARK_FOR_DATA_RATE DramOdtRttParkForDataRateLe1866
; ///< 152 DRAM ODT (RTT_PARK) for data rate <= 1866
885 SPD4_LRDIMM_DRAM_ODT_RTT_PARK_FOR_DATA_RATE DramOdtRttParkForDataRateLe2400
; ///< 153 DRAM ODT (RTT_PARK) for data rate <= 2400
886 SPD4_LRDIMM_DRAM_ODT_RTT_PARK_FOR_DATA_RATE DramOdtRttParkForDataRateLe3200
; ///< 154 DRAM ODT (RTT_PARK) for data rate <= 3200
887 SPD4_LRDIMM_DATA_BUFFER_VREFDQ_FOR_DRAM_INTERFACE_RANGE DataBufferVrefDQForDramInterfaceRange
; ///< 155 Data Buffer VrefDQ for DRAM Interface Range
888 SPD4_LRDIMM_DATA_BUFFER_DQ_DECISION_FEEDBACK_EQUALIZATION DataBufferDqDecisionFeedbackEqualization
; ///< 156 Data Buffer DQ Decision Feedback Equalization
889 UINT8 Reserved
[253 - 157 + 1]; ///< 253-132 Reserved
890 SPD4_CYCLIC_REDUNDANCY_CODE Crc
; ///< 254-255 Cyclical Redundancy Code (CRC)
891 } SPD4_MODULE_LOADREDUCED
;
894 UINT8 Reserved0
[191 - 128 + 1]; ///< 128-191 Reserved
895 SPD4_NVDIMM_MODULE_PRODUCT_IDENTIFIER ModuleProductIdentifier
; ///< 192-193 Module Product Identifier
896 SPD4_NVDIMM_SUBSYSTEM_CONTROLLER_MANUFACTURER_ID_CODE SubsystemControllerManufacturerIdCode
; ///< 194-195 Subsystem Controller Manufacturer's ID Code
897 SPD4_NVDIMM_SUBSYSTEM_CONTROLLER_IDENTIFIER SubsystemControllerIdentifier
; ///< 196-197 Subsystem Controller Identifier
898 SPD4_NVDIMM_SUBSYSTEM_CONTROLLER_REVISION_CODE SubsystemControllerRevisionCode
; ///< 198 Subsystem Controller Revision Code
899 SPD4_NVDIMM_REFERENCE_RAW_CARD ReferenceRawCardUsed
; ///< 199 Reference Raw Card Used
900 SPD4_NVDIMM_MODULE_CHARACTERISTICS ModuleCharacteristics
; ///< 200 Module Characteristics
901 SPD4_NVDIMM_HYBRID_MODULE_MEDIA_TYPES HybridModuleMediaTypes
; ///< 201-202 Hybrid Module Media Types
902 SPD4_NVDIMM_MAXIMUM_NONVOLATILE_MEMORY_INITIALIZATION_TIME MaximumNonVolatileMemoryInitializationTime
; ///< 203 Maximum Non-Volatile Memory Initialization Time
903 SPD4_NVDIMM_FUNCTION_INTERFACE_DESCRIPTOR FunctionInterfaceDescriptors
[8]; ///< 204-219 Function Interface Descriptors
904 UINT8 Reserved
[253 - 220 + 1]; ///< 220-253 Reserved
905 SPD4_CYCLIC_REDUNDANCY_CODE Crc
; ///< 254-255 Cyclical Redundancy Code (CRC)
906 } SPD4_MODULE_NVDIMM
;
909 SPD4_MODULE_UNBUFFERED Unbuffered
; ///< 128-255 Unbuffered Memory Module Types
910 SPD4_MODULE_REGISTERED Registered
; ///< 128-255 Registered Memory Module Types
911 SPD4_MODULE_LOADREDUCED LoadReduced
; ///< 128-255 Load Reduced Memory Module Types
912 SPD4_MODULE_NVDIMM NonVolatile
; ///< 128-255 Non-Volatile (NVDIMM-N) Hybrid Memory Parameters
913 } SPD4_MODULE_SPECIFIC
;
916 UINT8 ModulePartNumber
[348 - 329 + 1]; ///< 329-348 Module Part Number
917 } SPD4_MODULE_PART_NUMBER
;
920 UINT8 ManufacturerSpecificData
[381 - 353 + 1]; ///< 353-381 Manufacturer's Specific Data
921 } SPD4_MANUFACTURER_SPECIFIC
;
923 typedef UINT8 SPD4_MODULE_REVISION_CODE
; ///< 349 Module Revision Code
924 typedef UINT8 SPD4_DRAM_STEPPING
; ///< 352 Dram Stepping
927 SPD4_UNIQUE_MODULE_ID ModuleId
; ///< 320-328 Unique Module ID
928 SPD4_MODULE_PART_NUMBER ModulePartNumber
; ///< 329-348 Module Part Number
929 SPD4_MODULE_REVISION_CODE ModuleRevisionCode
; ///< 349 Module Revision Code
930 SPD4_MANUFACTURER_ID_CODE DramIdCode
; ///< 350-351 Dram Manufacturer ID Code
931 SPD4_DRAM_STEPPING DramStepping
; ///< 352 Dram Stepping
932 SPD4_MANUFACTURER_SPECIFIC ManufacturerSpecificData
; ///< 353-381 Manufacturer's Specific Data
933 UINT8 Reserved
[2]; ///< 382-383 Reserved
934 } SPD4_MANUFACTURING_DATA
;
937 UINT8 Reserved
[511 - 384 + 1]; ///< 384-511 Unbuffered Memory Module Types
938 } SPD4_END_USER_SECTION
;
941 /// DDR4 Serial Presence Detect structure
944 SPD4_BASE_SECTION Base
; ///< 0-127 Base Configuration and DRAM Parameters
945 SPD4_MODULE_SPECIFIC Module
; ///< 128-255 Module-Specific Section
946 UINT8 Reserved
[319 - 256 + 1]; ///< 256-319 Reserved
947 SPD4_MANUFACTURING_DATA ManufactureInfo
; ///< 320-383 Manufacturing Information
948 SPD4_END_USER_SECTION EndUser
; ///< 384-511 End User Programmable