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2 Provides services to access PCI Configuration Space using the I/O ports 0xCF8 and 0xCFC.
4 This library is identical to the PCI Library, except the access method for performing PCI
5 configuration cycles must be through I/O ports 0xCF8 and 0xCFC. This library only allows
6 access to PCI Segment #0.
8 Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
9 SPDX-License-Identifier: BSD-2-Clause-Patent
13 #ifndef __PCI_CF8_LIB_H__
14 #define __PCI_CF8_LIB_H__
18 Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register to an
19 address that can be passed to the PCI Library functions.
21 Computes an address that is compatible with the PCI Library functions. The
22 unused upper bits of Bus, Device, Function and Register are stripped prior to
23 the generation of the address.
25 @param Bus PCI Bus number. Range 0..255.
26 @param Device PCI Device number. Range 0..31.
27 @param Function PCI Function number. Range 0..7.
28 @param Register PCI Register number. Range 0..255.
30 @return The encode PCI address.
33 #define PCI_CF8_LIB_ADDRESS(Bus,Device,Function,Offset) \
34 (((Offset) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))
37 Registers a PCI device so PCI configuration registers may be accessed after
38 SetVirtualAddressMap().
40 Registers the PCI device specified by Address so all the PCI configuration registers
41 associated with that PCI device may be accessed after SetVirtualAddressMap() is called.
43 If Address > 0x0FFFFFFF, then ASSERT().
44 If the register specified by Address >= 0x100, then ASSERT().
46 @param Address Address that encodes the PCI Bus, Device, Function and
49 @retval RETURN_SUCCESS The PCI device was registered for runtime access.
50 @retval RETURN_UNSUPPORTED An attempt was made to call this function
51 after ExitBootServices().
52 @retval RETURN_UNSUPPORTED The resources required to access the PCI device
53 at runtime could not be mapped.
54 @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to
55 complete the registration.
60 PciCf8RegisterForRuntimeAccess (
65 Reads an 8-bit PCI configuration register.
67 Reads and returns the 8-bit PCI configuration register specified by Address.
68 This function must guarantee that all PCI read and write operations are
71 If Address > 0x0FFFFFFF, then ASSERT().
72 If the register specified by Address >= 0x100, then ASSERT().
74 @param Address Address that encodes the PCI Bus, Device, Function and
77 @return The read value from the PCI configuration register.
87 Writes an 8-bit PCI configuration register.
89 Writes the 8-bit PCI configuration register specified by Address with the
90 value specified by Value. Value is returned. This function must guarantee
91 that all PCI read and write operations are serialized.
93 If Address > 0x0FFFFFFF, then ASSERT().
94 If the register specified by Address >= 0x100, then ASSERT().
96 @param Address Address that encodes the PCI Bus, Device, Function and
98 @param Value The value to write.
100 @return The value written to the PCI configuration register.
111 Performs a bitwise OR of an 8-bit PCI configuration register with
114 Reads the 8-bit PCI configuration register specified by Address, performs a
115 bitwise OR between the read result and the value specified by
116 OrData, and writes the result to the 8-bit PCI configuration register
117 specified by Address. The value written to the PCI configuration register is
118 returned. This function must guarantee that all PCI read and write operations
121 If Address > 0x0FFFFFFF, then ASSERT().
122 If the register specified by Address >= 0x100, then ASSERT().
124 @param Address Address that encodes the PCI Bus, Device, Function and
126 @param OrData The value to OR with the PCI configuration register.
128 @return The value written back to the PCI configuration register.
139 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
142 Reads the 8-bit PCI configuration register specified by Address, performs a
143 bitwise AND between the read result and the value specified by AndData, and
144 writes the result to the 8-bit PCI configuration register specified by
145 Address. The value written to the PCI configuration register is returned.
146 This function must guarantee that all PCI read and write operations are
149 If Address > 0x0FFFFFFF, then ASSERT().
150 If the register specified by Address >= 0x100, then ASSERT().
152 @param Address Address that encodes the PCI Bus, Device, Function and
154 @param AndData The value to AND with the PCI configuration register.
156 @return The value written back to the PCI configuration register.
167 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
168 value, followed a bitwise OR with another 8-bit value.
170 Reads the 8-bit PCI configuration register specified by Address, performs a
171 bitwise AND between the read result and the value specified by AndData,
172 performs a bitwise OR between the result of the AND operation and
173 the value specified by OrData, and writes the result to the 8-bit PCI
174 configuration register specified by Address. The value written to the PCI
175 configuration register is returned. This function must guarantee that all PCI
176 read and write operations are serialized.
178 If Address > 0x0FFFFFFF, then ASSERT().
179 If the register specified by Address >= 0x100, then ASSERT().
181 @param Address Address that encodes the PCI Bus, Device, Function and
183 @param AndData The value to AND with the PCI configuration register.
184 @param OrData The value to OR with the result of the AND operation.
186 @return The value written back to the PCI configuration register.
198 Reads a bit field of a PCI configuration register.
200 Reads the bit field in an 8-bit PCI configuration register. The bit field is
201 specified by the StartBit and the EndBit. The value of the bit field is
204 If Address > 0x0FFFFFFF, then ASSERT().
205 If the register specified by Address >= 0x100, then ASSERT().
206 If StartBit is greater than 7, then ASSERT().
207 If EndBit is greater than 7, then ASSERT().
208 If EndBit is less than StartBit, then ASSERT().
210 @param Address PCI configuration register to read.
211 @param StartBit The ordinal of the least significant bit in the bit field.
213 @param EndBit The ordinal of the most significant bit in the bit field.
216 @return The value of the bit field read from the PCI configuration register.
221 PciCf8BitFieldRead8 (
228 Writes a bit field to a PCI configuration register.
230 Writes Value to the bit field of the PCI configuration register. The bit
231 field is specified by the StartBit and the EndBit. All other bits in the
232 destination PCI configuration register are preserved. The new value of the
233 8-bit register is returned.
235 If Address > 0x0FFFFFFF, then ASSERT().
236 If the register specified by Address >= 0x100, then ASSERT().
237 If StartBit is greater than 7, then ASSERT().
238 If EndBit is greater than 7, then ASSERT().
239 If EndBit is less than StartBit, then ASSERT().
240 If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
242 @param Address PCI configuration register to write.
243 @param StartBit The ordinal of the least significant bit in the bit field.
245 @param EndBit The ordinal of the most significant bit in the bit field.
247 @param Value New value of the bit field.
249 @return The value written back to the PCI configuration register.
254 PciCf8BitFieldWrite8 (
262 Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
263 writes the result back to the bit field in the 8-bit port.
265 Reads the 8-bit PCI configuration register specified by Address, performs a
266 bitwise OR between the read result and the value specified by
267 OrData, and writes the result to the 8-bit PCI configuration register
268 specified by Address. The value written to the PCI configuration register is
269 returned. This function must guarantee that all PCI read and write operations
270 are serialized. Extra left bits in OrData are stripped.
272 If Address > 0x0FFFFFFF, then ASSERT().
273 If the register specified by Address >= 0x100, then ASSERT().
274 If StartBit is greater than 7, then ASSERT().
275 If EndBit is greater than 7, then ASSERT().
276 If EndBit is less than StartBit, then ASSERT().
277 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
279 @param Address PCI configuration register to write.
280 @param StartBit The ordinal of the least significant bit in the bit field.
282 @param EndBit The ordinal of the most significant bit in the bit field.
284 @param OrData The value to OR with the PCI configuration register.
286 @return The value written back to the PCI configuration register.
299 Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
300 AND, and writes the result back to the bit field in the 8-bit register.
302 Reads the 8-bit PCI configuration register specified by Address, performs a
303 bitwise AND between the read result and the value specified by AndData, and
304 writes the result to the 8-bit PCI configuration register specified by
305 Address. The value written to the PCI configuration register is returned.
306 This function must guarantee that all PCI read and write operations are
307 serialized. Extra left bits in AndData are stripped.
309 If Address > 0x0FFFFFFF, then ASSERT().
310 If the register specified by Address >= 0x100, then ASSERT().
311 If StartBit is greater than 7, then ASSERT().
312 If EndBit is greater than 7, then ASSERT().
313 If EndBit is less than StartBit, then ASSERT().
314 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
316 @param Address PCI configuration register to write.
317 @param StartBit The ordinal of the least significant bit in the bit field.
319 @param EndBit The ordinal of the most significant bit in the bit field.
321 @param AndData The value to AND with the PCI configuration register.
323 @return The value written back to the PCI configuration register.
336 Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
337 bitwise OR, and writes the result back to the bit field in the
340 Reads the 8-bit PCI configuration register specified by Address, performs a
341 bitwise AND followed by a bitwise OR between the read result and
342 the value specified by AndData, and writes the result to the 8-bit PCI
343 configuration register specified by Address. The value written to the PCI
344 configuration register is returned. This function must guarantee that all PCI
345 read and write operations are serialized. Extra left bits in both AndData and
348 If Address > 0x0FFFFFFF, then ASSERT().
349 If the register specified by Address >= 0x100, then ASSERT().
350 If StartBit is greater than 7, then ASSERT().
351 If EndBit is greater than 7, then ASSERT().
352 If EndBit is less than StartBit, then ASSERT().
353 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
354 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
356 @param Address PCI configuration register to write.
357 @param StartBit The ordinal of the least significant bit in the bit field.
359 @param EndBit The ordinal of the most significant bit in the bit field.
361 @param AndData The value to AND with the PCI configuration register.
362 @param OrData The value to OR with the result of the AND operation.
364 @return The value written back to the PCI configuration register.
369 PciCf8BitFieldAndThenOr8 (
378 Reads a 16-bit PCI configuration register.
380 Reads and returns the 16-bit PCI configuration register specified by Address.
381 This function must guarantee that all PCI read and write operations are
384 If Address > 0x0FFFFFFF, then ASSERT().
385 If Address is not aligned on a 16-bit boundary, then ASSERT().
386 If the register specified by Address >= 0x100, then ASSERT().
388 @param Address Address that encodes the PCI Bus, Device, Function and
391 @return The read value from the PCI configuration register.
401 Writes a 16-bit PCI configuration register.
403 Writes the 16-bit PCI configuration register specified by Address with the
404 value specified by Value. Value is returned. This function must guarantee
405 that all PCI read and write operations are serialized.
407 If Address > 0x0FFFFFFF, then ASSERT().
408 If Address is not aligned on a 16-bit boundary, then ASSERT().
409 If the register specified by Address >= 0x100, then ASSERT().
411 @param Address Address that encodes the PCI Bus, Device, Function and
413 @param Value The value to write.
415 @return The value written to the PCI configuration register.
426 Performs a bitwise OR of a 16-bit PCI configuration register with
429 Reads the 16-bit PCI configuration register specified by Address, performs a
430 bitwise OR between the read result and the value specified by
431 OrData, and writes the result to the 16-bit PCI configuration register
432 specified by Address. The value written to the PCI configuration register is
433 returned. This function must guarantee that all PCI read and write operations
436 If Address > 0x0FFFFFFF, then ASSERT().
437 If Address is not aligned on a 16-bit boundary, then ASSERT().
438 If the register specified by Address >= 0x100, then ASSERT().
440 @param Address Address that encodes the PCI Bus, Device, Function and
442 @param OrData The value to OR with the PCI configuration register.
444 @return The value written back to the PCI configuration register.
455 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
458 Reads the 16-bit PCI configuration register specified by Address, performs a
459 bitwise AND between the read result and the value specified by AndData, and
460 writes the result to the 16-bit PCI configuration register specified by
461 Address. The value written to the PCI configuration register is returned.
462 This function must guarantee that all PCI read and write operations are
465 If Address > 0x0FFFFFFF, then ASSERT().
466 If Address is not aligned on a 16-bit boundary, then ASSERT().
467 If the register specified by Address >= 0x100, then ASSERT().
469 @param Address Address that encodes the PCI Bus, Device, Function and
471 @param AndData The value to AND with the PCI configuration register.
473 @return The value written back to the PCI configuration register.
484 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
485 value, followed a bitwise OR with another 16-bit value.
487 Reads the 16-bit PCI configuration register specified by Address, performs a
488 bitwise AND between the read result and the value specified by AndData,
489 performs a bitwise OR between the result of the AND operation and
490 the value specified by OrData, and writes the result to the 16-bit PCI
491 configuration register specified by Address. The value written to the PCI
492 configuration register is returned. This function must guarantee that all PCI
493 read and write operations are serialized.
495 If Address > 0x0FFFFFFF, then ASSERT().
496 If Address is not aligned on a 16-bit boundary, then ASSERT().
497 If the register specified by Address >= 0x100, then ASSERT().
499 @param Address Address that encodes the PCI Bus, Device, Function and
501 @param AndData The value to AND with the PCI configuration register.
502 @param OrData The value to OR with the result of the AND operation.
504 @return The value written back to the PCI configuration register.
516 Reads a bit field of a PCI configuration register.
518 Reads the bit field in a 16-bit PCI configuration register. The bit field is
519 specified by the StartBit and the EndBit. The value of the bit field is
522 If Address > 0x0FFFFFFF, then ASSERT().
523 If Address is not aligned on a 16-bit boundary, then ASSERT().
524 If the register specified by Address >= 0x100, then ASSERT().
525 If StartBit is greater than 15, then ASSERT().
526 If EndBit is greater than 15, then ASSERT().
527 If EndBit is less than StartBit, then ASSERT().
529 @param Address PCI configuration register to read.
530 @param StartBit The ordinal of the least significant bit in the bit field.
532 @param EndBit The ordinal of the most significant bit in the bit field.
535 @return The value of the bit field read from the PCI configuration register.
540 PciCf8BitFieldRead16 (
547 Writes a bit field to a PCI configuration register.
549 Writes Value to the bit field of the PCI configuration register. The bit
550 field is specified by the StartBit and the EndBit. All other bits in the
551 destination PCI configuration register are preserved. The new value of the
552 16-bit register is returned.
554 If Address > 0x0FFFFFFF, then ASSERT().
555 If Address is not aligned on a 16-bit boundary, then ASSERT().
556 If the register specified by Address >= 0x100, then ASSERT().
557 If StartBit is greater than 15, then ASSERT().
558 If EndBit is greater than 15, then ASSERT().
559 If EndBit is less than StartBit, then ASSERT().
560 If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
562 @param Address PCI configuration register to write.
563 @param StartBit The ordinal of the least significant bit in the bit field.
565 @param EndBit The ordinal of the most significant bit in the bit field.
567 @param Value New value of the bit field.
569 @return The value written back to the PCI configuration register.
574 PciCf8BitFieldWrite16 (
582 Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
583 writes the result back to the bit field in the 16-bit port.
585 Reads the 16-bit PCI configuration register specified by Address, performs a
586 bitwise OR between the read result and the value specified by
587 OrData, and writes the result to the 16-bit PCI configuration register
588 specified by Address. The value written to the PCI configuration register is
589 returned. This function must guarantee that all PCI read and write operations
590 are serialized. Extra left bits in OrData are stripped.
592 If Address > 0x0FFFFFFF, then ASSERT().
593 If Address is not aligned on a 16-bit boundary, then ASSERT().
594 If the register specified by Address >= 0x100, then ASSERT().
595 If StartBit is greater than 15, then ASSERT().
596 If EndBit is greater than 15, then ASSERT().
597 If EndBit is less than StartBit, then ASSERT().
598 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
600 @param Address PCI configuration register to write.
601 @param StartBit The ordinal of the least significant bit in the bit field.
603 @param EndBit The ordinal of the most significant bit in the bit field.
605 @param OrData The value to OR with the PCI configuration register.
607 @return The value written back to the PCI configuration register.
620 Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
621 AND, and writes the result back to the bit field in the 16-bit register.
623 Reads the 16-bit PCI configuration register specified by Address, performs a
624 bitwise AND between the read result and the value specified by AndData, and
625 writes the result to the 16-bit PCI configuration register specified by
626 Address. The value written to the PCI configuration register is returned.
627 This function must guarantee that all PCI read and write operations are
628 serialized. Extra left bits in AndData are stripped.
630 If Address > 0x0FFFFFFF, then ASSERT().
631 If Address is not aligned on a 16-bit boundary, then ASSERT().
632 If the register specified by Address >= 0x100, then ASSERT().
633 If StartBit is greater than 15, then ASSERT().
634 If EndBit is greater than 15, then ASSERT().
635 If EndBit is less than StartBit, then ASSERT().
636 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
638 @param Address PCI configuration register to write.
639 @param StartBit The ordinal of the least significant bit in the bit field.
641 @param EndBit The ordinal of the most significant bit in the bit field.
643 @param AndData The value to AND with the PCI configuration register.
645 @return The value written back to the PCI configuration register.
650 PciCf8BitFieldAnd16 (
658 Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
659 bitwise OR, and writes the result back to the bit field in the
662 Reads the 16-bit PCI configuration register specified by Address, performs a
663 bitwise AND followed by a bitwise OR between the read result and
664 the value specified by AndData, and writes the result to the 16-bit PCI
665 configuration register specified by Address. The value written to the PCI
666 configuration register is returned. This function must guarantee that all PCI
667 read and write operations are serialized. Extra left bits in both AndData and
670 If Address > 0x0FFFFFFF, then ASSERT().
671 If Address is not aligned on a 16-bit boundary, then ASSERT().
672 If the register specified by Address >= 0x100, then ASSERT().
673 If StartBit is greater than 15, then ASSERT().
674 If EndBit is greater than 15, then ASSERT().
675 If EndBit is less than StartBit, then ASSERT().
676 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
677 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
679 @param Address PCI configuration register to write.
680 @param StartBit The ordinal of the least significant bit in the bit field.
682 @param EndBit The ordinal of the most significant bit in the bit field.
684 @param AndData The value to AND with the PCI configuration register.
685 @param OrData The value to OR with the result of the AND operation.
687 @return The value written back to the PCI configuration register.
692 PciCf8BitFieldAndThenOr16 (
701 Reads a 32-bit PCI configuration register.
703 Reads and returns the 32-bit PCI configuration register specified by Address.
704 This function must guarantee that all PCI read and write operations are
707 If Address > 0x0FFFFFFF, then ASSERT().
708 If Address is not aligned on a 32-bit boundary, then ASSERT().
709 If the register specified by Address >= 0x100, then ASSERT().
711 @param Address Address that encodes the PCI Bus, Device, Function and
714 @return The read value from the PCI configuration register.
724 Writes a 32-bit PCI configuration register.
726 Writes the 32-bit PCI configuration register specified by Address with the
727 value specified by Value. Value is returned. This function must guarantee
728 that all PCI read and write operations are serialized.
730 If Address > 0x0FFFFFFF, then ASSERT().
731 If Address is not aligned on a 32-bit boundary, then ASSERT().
732 If the register specified by Address >= 0x100, then ASSERT().
734 @param Address Address that encodes the PCI Bus, Device, Function and
736 @param Value The value to write.
738 @return The value written to the PCI configuration register.
749 Performs a bitwise OR of a 32-bit PCI configuration register with
752 Reads the 32-bit PCI configuration register specified by Address, performs a
753 bitwise OR between the read result and the value specified by
754 OrData, and writes the result to the 32-bit PCI configuration register
755 specified by Address. The value written to the PCI configuration register is
756 returned. This function must guarantee that all PCI read and write operations
759 If Address > 0x0FFFFFFF, then ASSERT().
760 If Address is not aligned on a 32-bit boundary, then ASSERT().
761 If the register specified by Address >= 0x100, then ASSERT().
763 @param Address Address that encodes the PCI Bus, Device, Function and
765 @param OrData The value to OR with the PCI configuration register.
767 @return The value written back to the PCI configuration register.
778 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
781 Reads the 32-bit PCI configuration register specified by Address, performs a
782 bitwise AND between the read result and the value specified by AndData, and
783 writes the result to the 32-bit PCI configuration register specified by
784 Address. The value written to the PCI configuration register is returned.
785 This function must guarantee that all PCI read and write operations are
788 If Address > 0x0FFFFFFF, then ASSERT().
789 If Address is not aligned on a 32-bit boundary, then ASSERT().
790 If the register specified by Address >= 0x100, then ASSERT().
792 @param Address Address that encodes the PCI Bus, Device, Function and
794 @param AndData The value to AND with the PCI configuration register.
796 @return The value written back to the PCI configuration register.
807 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
808 value, followed a bitwise OR with another 32-bit value.
810 Reads the 32-bit PCI configuration register specified by Address, performs a
811 bitwise AND between the read result and the value specified by AndData,
812 performs a bitwise OR between the result of the AND operation and
813 the value specified by OrData, and writes the result to the 32-bit PCI
814 configuration register specified by Address. The value written to the PCI
815 configuration register is returned. This function must guarantee that all PCI
816 read and write operations are serialized.
818 If Address > 0x0FFFFFFF, then ASSERT().
819 If Address is not aligned on a 32-bit boundary, then ASSERT().
820 If the register specified by Address >= 0x100, then ASSERT().
822 @param Address Address that encodes the PCI Bus, Device, Function and
824 @param AndData The value to AND with the PCI configuration register.
825 @param OrData The value to OR with the result of the AND operation.
827 @return The value written back to the PCI configuration register.
839 Reads a bit field of a PCI configuration register.
841 Reads the bit field in a 32-bit PCI configuration register. The bit field is
842 specified by the StartBit and the EndBit. The value of the bit field is
845 If Address > 0x0FFFFFFF, then ASSERT().
846 If Address is not aligned on a 32-bit boundary, then ASSERT().
847 If the register specified by Address >= 0x100, then ASSERT().
848 If StartBit is greater than 31, then ASSERT().
849 If EndBit is greater than 31, then ASSERT().
850 If EndBit is less than StartBit, then ASSERT().
852 @param Address PCI configuration register to read.
853 @param StartBit The ordinal of the least significant bit in the bit field.
855 @param EndBit The ordinal of the most significant bit in the bit field.
858 @return The value of the bit field read from the PCI configuration register.
863 PciCf8BitFieldRead32 (
870 Writes a bit field to a PCI configuration register.
872 Writes Value to the bit field of the PCI configuration register. The bit
873 field is specified by the StartBit and the EndBit. All other bits in the
874 destination PCI configuration register are preserved. The new value of the
875 32-bit register is returned.
877 If Address > 0x0FFFFFFF, then ASSERT().
878 If Address is not aligned on a 32-bit boundary, then ASSERT().
879 If the register specified by Address >= 0x100, then ASSERT().
880 If StartBit is greater than 31, then ASSERT().
881 If EndBit is greater than 31, then ASSERT().
882 If EndBit is less than StartBit, then ASSERT().
883 If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
885 @param Address PCI configuration register to write.
886 @param StartBit The ordinal of the least significant bit in the bit field.
888 @param EndBit The ordinal of the most significant bit in the bit field.
890 @param Value New value of the bit field.
892 @return The value written back to the PCI configuration register.
897 PciCf8BitFieldWrite32 (
905 Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
906 writes the result back to the bit field in the 32-bit port.
908 Reads the 32-bit PCI configuration register specified by Address, performs a
909 bitwise OR between the read result and the value specified by
910 OrData, and writes the result to the 32-bit PCI configuration register
911 specified by Address. The value written to the PCI configuration register is
912 returned. This function must guarantee that all PCI read and write operations
913 are serialized. Extra left bits in OrData are stripped.
915 If Address > 0x0FFFFFFF, then ASSERT().
916 If Address is not aligned on a 32-bit boundary, then ASSERT().
917 If the register specified by Address >= 0x100, then ASSERT().
918 If StartBit is greater than 31, then ASSERT().
919 If EndBit is greater than 31, then ASSERT().
920 If EndBit is less than StartBit, then ASSERT().
921 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
923 @param Address PCI configuration register to write.
924 @param StartBit The ordinal of the least significant bit in the bit field.
926 @param EndBit The ordinal of the most significant bit in the bit field.
928 @param OrData The value to OR with the PCI configuration register.
930 @return The value written back to the PCI configuration register.
943 Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
944 AND, and writes the result back to the bit field in the 32-bit register.
946 Reads the 32-bit PCI configuration register specified by Address, performs a
947 bitwise AND between the read result and the value specified by AndData, and
948 writes the result to the 32-bit PCI configuration register specified by
949 Address. The value written to the PCI configuration register is returned.
950 This function must guarantee that all PCI read and write operations are
951 serialized. Extra left bits in AndData are stripped.
953 If Address > 0x0FFFFFFF, then ASSERT().
954 If Address is not aligned on a 32-bit boundary, then ASSERT().
955 If the register specified by Address >= 0x100, then ASSERT().
956 If StartBit is greater than 31, then ASSERT().
957 If EndBit is greater than 31, then ASSERT().
958 If EndBit is less than StartBit, then ASSERT().
959 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
961 @param Address PCI configuration register to write.
962 @param StartBit The ordinal of the least significant bit in the bit field.
964 @param EndBit The ordinal of the most significant bit in the bit field.
966 @param AndData The value to AND with the PCI configuration register.
968 @return The value written back to the PCI configuration register.
973 PciCf8BitFieldAnd32 (
981 Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
982 bitwise OR, and writes the result back to the bit field in the
985 Reads the 32-bit PCI configuration register specified by Address, performs a
986 bitwise AND followed by a bitwise OR between the read result and
987 the value specified by AndData, and writes the result to the 32-bit PCI
988 configuration register specified by Address. The value written to the PCI
989 configuration register is returned. This function must guarantee that all PCI
990 read and write operations are serialized. Extra left bits in both AndData and
993 If Address > 0x0FFFFFFF, then ASSERT().
994 If Address is not aligned on a 32-bit boundary, then ASSERT().
995 If the register specified by Address >= 0x100, then ASSERT().
996 If StartBit is greater than 31, then ASSERT().
997 If EndBit is greater than 31, then ASSERT().
998 If EndBit is less than StartBit, then ASSERT().
999 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
1000 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
1002 @param Address PCI configuration register to write.
1003 @param StartBit The ordinal of the least significant bit in the bit field.
1005 @param EndBit The ordinal of the most significant bit in the bit field.
1007 @param AndData The value to AND with the PCI configuration register.
1008 @param OrData The value to OR with the result of the AND operation.
1010 @return The value written back to the PCI configuration register.
1015 PciCf8BitFieldAndThenOr32 (
1024 Reads a range of PCI configuration registers into a caller supplied buffer.
1026 Reads the range of PCI configuration registers specified by StartAddress and
1027 Size into the buffer specified by Buffer. This function only allows the PCI
1028 configuration registers from a single PCI function to be read. Size is
1029 returned. When possible 32-bit PCI configuration read cycles are used to read
1030 from StartAddress to StartAddress + Size. Due to alignment restrictions, 8-bit
1031 and 16-bit PCI configuration read cycles may be used at the beginning and the
1034 If StartAddress > 0x0FFFFFFF, then ASSERT().
1035 If the register specified by StartAddress >= 0x100, then ASSERT().
1036 If ((StartAddress & 0xFFF) + Size) > 0x100, then ASSERT().
1037 If Size > 0 and Buffer is NULL, then ASSERT().
1039 @param StartAddress Starting address that encodes the PCI Bus, Device,
1040 Function and Register.
1041 @param Size Size in bytes of the transfer.
1042 @param Buffer Pointer to a buffer receiving the data read.
1044 @return Size read from StartAddress.
1050 IN UINTN StartAddress
,
1056 Copies the data in a caller supplied buffer to a specified range of PCI
1057 configuration space.
1059 Writes the range of PCI configuration registers specified by StartAddress and
1060 Size from the buffer specified by Buffer. This function only allows the PCI
1061 configuration registers from a single PCI function to be written. Size is
1062 returned. When possible 32-bit PCI configuration write cycles are used to
1063 write from StartAddress to StartAddress + Size. Due to alignment restrictions,
1064 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
1065 and the end of the range.
1067 If StartAddress > 0x0FFFFFFF, then ASSERT().
1068 If the register specified by StartAddress >= 0x100, then ASSERT().
1069 If ((StartAddress & 0xFFF) + Size) > 0x100, then ASSERT().
1070 If Size > 0 and Buffer is NULL, then ASSERT().
1072 @param StartAddress Starting address that encodes the PCI Bus, Device,
1073 Function and Register.
1074 @param Size Size in bytes of the transfer.
1075 @param Buffer Pointer to a buffer containing the data to write.
1077 @return Size written to StartAddress.
1083 IN UINTN StartAddress
,