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2 Provides services to access PCI Configuration Space on a platform with multiple PCI segments.
4 The PCI Segment Library function provide services to read, write, and modify the PCI configuration
5 registers on PCI root bridges on any supported PCI segment. These library services take a single
6 address parameter that encodes the PCI Segment, PCI Bus, PCI Device, PCI Function, and PCI Register.
7 The layout of this address parameter is as follows:
9 PCI Register: Bits 0..11
10 PCI Function Bits 12..14
11 PCI Device Bits 15..19
13 Reserved Bits 28..31. Must be 0.
14 PCI Segment Bits 32..47
15 Reserved Bits 48..63. Must be 0.
17 | Reserved (MBZ) | Segment | Reserved (MBZ) | Bus | Device | Function | Register |
18 63 48 47 32 31 28 27 20 19 15 14 12 11 0
20 These functions perform PCI configuration cycles using the default PCI configuration access
21 method. This may use I/O ports 0xCF8 and 0xCFC to perform PCI configuration accesses, or it
22 may use MMIO registers relative to the PcdPciExpressBaseAddress, or it may use some alternate
23 access method. Modules will typically use the PCI Segment Library for its PCI configuration
24 accesses when PCI Segments other than Segment #0 must be accessed.
26 Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>
27 This program and the accompanying materials
28 are licensed and made available under the terms and conditions of the BSD License
29 which accompanies this distribution. The full text of the license may be found at
30 http://opensource.org/licenses/bsd-license.php
32 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
33 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
37 #ifndef __PCI_SEGMENT_LIB__
38 #define __PCI_SEGMENT_LIB__
42 Macro that converts PCI Segment, PCI Bus, PCI Device, PCI Function,
43 and PCI Register to an address that can be passed to the PCI Segment Library functions.
45 Computes an address that is compatible with the PCI Segment Library functions.
46 The unused upper bits of Segment, Bus, Device, Function,
47 and Register are stripped prior to the generation of the address.
49 @param Segment PCI Segment number. Range 0..65535.
50 @param Bus PCI Bus number. Range 0..255.
51 @param Device PCI Device number. Range 0..31.
52 @param Function PCI Function number. Range 0..7.
53 @param Register PCI Register number. Range 0..255 for PCI. Range 0..4095 for PCI Express.
55 @return The address that is compatible with the PCI Segment Library functions.
58 #define PCI_SEGMENT_LIB_ADDRESS(Segment,Bus,Device,Function,Register) \
60 ( ((Register) & 0xfff) | \
61 (((Function) & 0x07) << 12) | \
62 (((Device) & 0x1f) << 15) | \
63 (((Bus) & 0xff) << 20) | \
64 (LShiftU64 ((Segment) & 0xffff, 32)) \
66 ( ((Register) & 0xfff) | \
67 (((Function) & 0x07) << 12) | \
68 (((Device) & 0x1f) << 15) | \
69 (((Bus) & 0xff) << 20) \
74 Register a PCI device so PCI configuration registers may be accessed after
75 SetVirtualAddressMap().
77 If any reserved bits in Address are set, then ASSERT().
79 @param Address Address that encodes the PCI Bus, Device, Function and
82 @retval RETURN_SUCCESS The PCI device was registered for runtime access.
83 @retval RETURN_UNSUPPORTED An attempt was made to call this function
84 after ExitBootServices().
85 @retval RETURN_UNSUPPORTED The resources required to access the PCI device
86 at runtime could not be mapped.
87 @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to
88 complete the registration.
93 PciSegmentRegisterForRuntimeAccess (
98 Reads an 8-bit PCI configuration register.
100 Reads and returns the 8-bit PCI configuration register specified by Address.
101 This function must guarantee that all PCI read and write operations are serialized.
103 If any reserved bits in Address are set, then ASSERT().
105 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
107 @return The 8-bit PCI configuration register specified by Address.
117 Writes an 8-bit PCI configuration register.
119 Writes the 8-bit PCI configuration register specified by Address with the value specified by Value.
120 Value is returned. This function must guarantee that all PCI read and write operations are serialized.
122 If any reserved bits in Address are set, then ASSERT().
124 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
125 @param Value The value to write.
127 @return The value written to the PCI configuration register.
138 Performs a bitwise OR of an 8-bit PCI configuration register with an 8-bit value.
140 Reads the 8-bit PCI configuration register specified by Address,
141 performs a bitwise OR between the read result and the value specified by OrData,
142 and writes the result to the 8-bit PCI configuration register specified by Address.
143 The value written to the PCI configuration register is returned.
144 This function must guarantee that all PCI read and write operations are serialized.
146 If any reserved bits in Address are set, then ASSERT().
148 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
149 @param OrData The value to OR with the PCI configuration register.
151 @return The value written to the PCI configuration register.
162 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value.
164 Reads the 8-bit PCI configuration register specified by Address,
165 performs a bitwise AND between the read result and the value specified by AndData,
166 and writes the result to the 8-bit PCI configuration register specified by Address.
167 The value written to the PCI configuration register is returned.
168 This function must guarantee that all PCI read and write operations are serialized.
169 If any reserved bits in Address are set, then ASSERT().
171 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
172 @param AndData The value to AND with the PCI configuration register.
174 @return The value written to the PCI configuration register.
185 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value,
186 followed a bitwise OR with another 8-bit value.
188 Reads the 8-bit PCI configuration register specified by Address,
189 performs a bitwise AND between the read result and the value specified by AndData,
190 performs a bitwise OR between the result of the AND operation and the value specified by OrData,
191 and writes the result to the 8-bit PCI configuration register specified by Address.
192 The value written to the PCI configuration register is returned.
193 This function must guarantee that all PCI read and write operations are serialized.
195 If any reserved bits in Address are set, then ASSERT().
197 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
198 @param AndData The value to AND with the PCI configuration register.
199 @param OrData The value to OR with the PCI configuration register.
201 @return The value written to the PCI configuration register.
206 PciSegmentAndThenOr8 (
213 Reads a bit field of a PCI configuration register.
215 Reads the bit field in an 8-bit PCI configuration register. The bit field is
216 specified by the StartBit and the EndBit. The value of the bit field is
219 If any reserved bits in Address are set, then ASSERT().
220 If StartBit is greater than 7, then ASSERT().
221 If EndBit is greater than 7, then ASSERT().
222 If EndBit is less than StartBit, then ASSERT().
224 @param Address PCI configuration register to read.
225 @param StartBit The ordinal of the least significant bit in the bit field.
227 @param EndBit The ordinal of the most significant bit in the bit field.
230 @return The value of the bit field read from the PCI configuration register.
235 PciSegmentBitFieldRead8 (
242 Writes a bit field to a PCI configuration register.
244 Writes Value to the bit field of the PCI configuration register. The bit
245 field is specified by the StartBit and the EndBit. All other bits in the
246 destination PCI configuration register are preserved. The new value of the
247 8-bit register is returned.
249 If any reserved bits in Address are set, then ASSERT().
250 If StartBit is greater than 7, then ASSERT().
251 If EndBit is greater than 7, then ASSERT().
252 If EndBit is less than StartBit, then ASSERT().
253 If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
255 @param Address PCI configuration register to write.
256 @param StartBit The ordinal of the least significant bit in the bit field.
258 @param EndBit The ordinal of the most significant bit in the bit field.
260 @param Value New value of the bit field.
262 @return The value written back to the PCI configuration register.
267 PciSegmentBitFieldWrite8 (
275 Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
276 writes the result back to the bit field in the 8-bit port.
278 Reads the 8-bit PCI configuration register specified by Address, performs a
279 bitwise OR between the read result and the value specified by
280 OrData, and writes the result to the 8-bit PCI configuration register
281 specified by Address. The value written to the PCI configuration register is
282 returned. This function must guarantee that all PCI read and write operations
283 are serialized. Extra left bits in OrData are stripped.
285 If any reserved bits in Address are set, then ASSERT().
286 If StartBit is greater than 7, then ASSERT().
287 If EndBit is greater than 7, then ASSERT().
288 If EndBit is less than StartBit, then ASSERT().
289 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
291 @param Address PCI configuration register to write.
292 @param StartBit The ordinal of the least significant bit in the bit field.
294 @param EndBit The ordinal of the most significant bit in the bit field.
296 @param OrData The value to OR with the PCI configuration register.
298 @return The value written back to the PCI configuration register.
303 PciSegmentBitFieldOr8 (
311 Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
312 AND, and writes the result back to the bit field in the 8-bit register.
314 Reads the 8-bit PCI configuration register specified by Address, performs a
315 bitwise AND between the read result and the value specified by AndData, and
316 writes the result to the 8-bit PCI configuration register specified by
317 Address. The value written to the PCI configuration register is returned.
318 This function must guarantee that all PCI read and write operations are
319 serialized. Extra left bits in AndData are stripped.
321 If any reserved bits in Address are set, then ASSERT().
322 If StartBit is greater than 7, then ASSERT().
323 If EndBit is greater than 7, then ASSERT().
324 If EndBit is less than StartBit, then ASSERT().
325 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
327 @param Address PCI configuration register to write.
328 @param StartBit The ordinal of the least significant bit in the bit field.
330 @param EndBit The ordinal of the most significant bit in the bit field.
332 @param AndData The value to AND with the PCI configuration register.
334 @return The value written back to the PCI configuration register.
339 PciSegmentBitFieldAnd8 (
347 Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
348 bitwise OR, and writes the result back to the bit field in the 8-bit port.
350 Reads the 8-bit PCI configuration register specified by Address, performs a
351 bitwise AND followed by a bitwise OR between the read result and
352 the value specified by AndData, and writes the result to the 8-bit PCI
353 configuration register specified by Address. The value written to the PCI
354 configuration register is returned. This function must guarantee that all PCI
355 read and write operations are serialized. Extra left bits in both AndData and
358 If any reserved bits in Address are set, then ASSERT().
359 If StartBit is greater than 7, then ASSERT().
360 If EndBit is greater than 7, then ASSERT().
361 If EndBit is less than StartBit, then ASSERT().
362 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
363 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
365 @param Address PCI configuration register to write.
366 @param StartBit The ordinal of the least significant bit in the bit field.
368 @param EndBit The ordinal of the most significant bit in the bit field.
370 @param AndData The value to AND with the PCI configuration register.
371 @param OrData The value to OR with the result of the AND operation.
373 @return The value written back to the PCI configuration register.
378 PciSegmentBitFieldAndThenOr8 (
387 Reads a 16-bit PCI configuration register.
389 Reads and returns the 16-bit PCI configuration register specified by Address.
390 This function must guarantee that all PCI read and write operations are serialized.
392 If any reserved bits in Address are set, then ASSERT().
393 If Address is not aligned on a 16-bit boundary, then ASSERT().
395 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
397 @return The 16-bit PCI configuration register specified by Address.
407 Writes a 16-bit PCI configuration register.
409 Writes the 16-bit PCI configuration register specified by Address with the value specified by Value.
410 Value is returned. This function must guarantee that all PCI read and write operations are serialized.
412 If any reserved bits in Address are set, then ASSERT().
413 If Address is not aligned on a 16-bit boundary, then ASSERT().
415 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
416 @param Value The value to write.
418 @return The parameter of Value.
429 Performs a bitwise OR of a 16-bit PCI configuration register with
432 Reads the 16-bit PCI configuration register specified by Address, performs a
433 bitwise OR between the read result and the value specified by OrData, and
434 writes the result to the 16-bit PCI configuration register specified by Address.
435 The value written to the PCI configuration register is returned. This function
436 must guarantee that all PCI read and write operations are serialized.
438 If any reserved bits in Address are set, then ASSERT().
439 If Address is not aligned on a 16-bit boundary, then ASSERT().
441 @param Address Address that encodes the PCI Segment, Bus, Device, Function and
443 @param OrData The value to OR with the PCI configuration register.
445 @return The value written back to the PCI configuration register.
456 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value.
458 Reads the 16-bit PCI configuration register specified by Address,
459 performs a bitwise AND between the read result and the value specified by AndData,
460 and writes the result to the 16-bit PCI configuration register specified by Address.
461 The value written to the PCI configuration register is returned.
462 This function must guarantee that all PCI read and write operations are serialized.
464 If any reserved bits in Address are set, then ASSERT().
465 If Address is not aligned on a 16-bit boundary, then ASSERT().
467 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
468 @param AndData The value to AND with the PCI configuration register.
470 @return The value written to the PCI configuration register.
481 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value,
482 followed a bitwise OR with another 16-bit value.
484 Reads the 16-bit PCI configuration register specified by Address,
485 performs a bitwise AND between the read result and the value specified by AndData,
486 performs a bitwise OR between the result of the AND operation and the value specified by OrData,
487 and writes the result to the 16-bit PCI configuration register specified by Address.
488 The value written to the PCI configuration register is returned.
489 This function must guarantee that all PCI read and write operations are serialized.
491 If any reserved bits in Address are set, then ASSERT().
492 If Address is not aligned on a 16-bit boundary, then ASSERT().
494 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
495 @param AndData The value to AND with the PCI configuration register.
496 @param OrData The value to OR with the PCI configuration register.
498 @return The value written to the PCI configuration register.
503 PciSegmentAndThenOr16 (
510 Reads a bit field of a PCI configuration register.
512 Reads the bit field in a 16-bit PCI configuration register. The bit field is
513 specified by the StartBit and the EndBit. The value of the bit field is
516 If any reserved bits in Address are set, then ASSERT().
517 If Address is not aligned on a 16-bit boundary, then ASSERT().
518 If StartBit is greater than 15, then ASSERT().
519 If EndBit is greater than 15, then ASSERT().
520 If EndBit is less than StartBit, then ASSERT().
522 @param Address PCI configuration register to read.
523 @param StartBit The ordinal of the least significant bit in the bit field.
525 @param EndBit The ordinal of the most significant bit in the bit field.
528 @return The value of the bit field read from the PCI configuration register.
533 PciSegmentBitFieldRead16 (
540 Writes a bit field to a PCI configuration register.
542 Writes Value to the bit field of the PCI configuration register. The bit
543 field is specified by the StartBit and the EndBit. All other bits in the
544 destination PCI configuration register are preserved. The new value of the
545 16-bit register is returned.
547 If any reserved bits in Address are set, then ASSERT().
548 If Address is not aligned on a 16-bit boundary, then ASSERT().
549 If StartBit is greater than 15, then ASSERT().
550 If EndBit is greater than 15, then ASSERT().
551 If EndBit is less than StartBit, then ASSERT().
552 If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
554 @param Address PCI configuration register to write.
555 @param StartBit The ordinal of the least significant bit in the bit field.
557 @param EndBit The ordinal of the most significant bit in the bit field.
559 @param Value New value of the bit field.
561 @return The value written back to the PCI configuration register.
566 PciSegmentBitFieldWrite16 (
574 Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, writes
575 the result back to the bit field in the 16-bit port.
577 Reads the 16-bit PCI configuration register specified by Address, performs a
578 bitwise OR between the read result and the value specified by
579 OrData, and writes the result to the 16-bit PCI configuration register
580 specified by Address. The value written to the PCI configuration register is
581 returned. This function must guarantee that all PCI read and write operations
582 are serialized. Extra left bits in OrData are stripped.
584 If any reserved bits in Address are set, then ASSERT().
585 If Address is not aligned on a 16-bit boundary, then ASSERT().
586 If StartBit is greater than 15, then ASSERT().
587 If EndBit is greater than 15, then ASSERT().
588 If EndBit is less than StartBit, then ASSERT().
589 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
591 @param Address PCI configuration register to write.
592 @param StartBit The ordinal of the least significant bit in the bit field.
594 @param EndBit The ordinal of the most significant bit in the bit field.
596 @param OrData The value to OR with the PCI configuration register.
598 @return The value written back to the PCI configuration register.
603 PciSegmentBitFieldOr16 (
611 Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
612 AND, writes the result back to the bit field in the 16-bit register.
614 Reads the 16-bit PCI configuration register specified by Address, performs a
615 bitwise AND between the read result and the value specified by AndData, and
616 writes the result to the 16-bit PCI configuration register specified by
617 Address. The value written to the PCI configuration register is returned.
618 This function must guarantee that all PCI read and write operations are
619 serialized. Extra left bits in AndData are stripped.
621 If any reserved bits in Address are set, then ASSERT().
622 If Address is not aligned on a 16-bit boundary, then ASSERT().
623 If StartBit is greater than 15, then ASSERT().
624 If EndBit is greater than 15, then ASSERT().
625 If EndBit is less than StartBit, then ASSERT().
626 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
628 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
629 @param StartBit The ordinal of the least significant bit in the bit field.
631 @param EndBit The ordinal of the most significant bit in the bit field.
633 @param AndData The value to AND with the PCI configuration register.
635 @return The value written back to the PCI configuration register.
640 PciSegmentBitFieldAnd16 (
648 Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
649 bitwise OR, and writes the result back to the bit field in the
652 Reads the 16-bit PCI configuration register specified by Address, performs a
653 bitwise AND followed by a bitwise OR between the read result and
654 the value specified by AndData, and writes the result to the 16-bit PCI
655 configuration register specified by Address. The value written to the PCI
656 configuration register is returned. This function must guarantee that all PCI
657 read and write operations are serialized. Extra left bits in both AndData and
660 If any reserved bits in Address are set, then ASSERT().
661 If StartBit is greater than 15, then ASSERT().
662 If EndBit is greater than 15, then ASSERT().
663 If EndBit is less than StartBit, then ASSERT().
664 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
665 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
667 @param Address PCI configuration register to write.
668 @param StartBit The ordinal of the least significant bit in the bit field.
670 @param EndBit The ordinal of the most significant bit in the bit field.
672 @param AndData The value to AND with the PCI configuration register.
673 @param OrData The value to OR with the result of the AND operation.
675 @return The value written back to the PCI configuration register.
680 PciSegmentBitFieldAndThenOr16 (
689 Reads a 32-bit PCI configuration register.
691 Reads and returns the 32-bit PCI configuration register specified by Address.
692 This function must guarantee that all PCI read and write operations are serialized.
694 If any reserved bits in Address are set, then ASSERT().
695 If Address is not aligned on a 32-bit boundary, then ASSERT().
697 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
699 @return The 32-bit PCI configuration register specified by Address.
709 Writes a 32-bit PCI configuration register.
711 Writes the 32-bit PCI configuration register specified by Address with the value specified by Value.
712 Value is returned. This function must guarantee that all PCI read and write operations are serialized.
714 If any reserved bits in Address are set, then ASSERT().
715 If Address is not aligned on a 32-bit boundary, then ASSERT().
717 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
718 @param Value The value to write.
720 @return The parameter of Value.
731 Performs a bitwise OR of a 32-bit PCI configuration register with a 32-bit value.
733 Reads the 32-bit PCI configuration register specified by Address,
734 performs a bitwise OR between the read result and the value specified by OrData,
735 and writes the result to the 32-bit PCI configuration register specified by Address.
736 The value written to the PCI configuration register is returned.
737 This function must guarantee that all PCI read and write operations are serialized.
739 If any reserved bits in Address are set, then ASSERT().
740 If Address is not aligned on a 32-bit boundary, then ASSERT().
742 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
743 @param OrData The value to OR with the PCI configuration register.
745 @return The value written to the PCI configuration register.
756 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value.
758 Reads the 32-bit PCI configuration register specified by Address,
759 performs a bitwise AND between the read result and the value specified by AndData,
760 and writes the result to the 32-bit PCI configuration register specified by Address.
761 The value written to the PCI configuration register is returned.
762 This function must guarantee that all PCI read and write operations are serialized.
764 If any reserved bits in Address are set, then ASSERT().
765 If Address is not aligned on a 32-bit boundary, then ASSERT().
767 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
768 @param AndData The value to AND with the PCI configuration register.
770 @return The value written to the PCI configuration register.
781 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value,
782 followed a bitwise OR with another 32-bit value.
784 Reads the 32-bit PCI configuration register specified by Address,
785 performs a bitwise AND between the read result and the value specified by AndData,
786 performs a bitwise OR between the result of the AND operation and the value specified by OrData,
787 and writes the result to the 32-bit PCI configuration register specified by Address.
788 The value written to the PCI configuration register is returned.
789 This function must guarantee that all PCI read and write operations are serialized.
791 If any reserved bits in Address are set, then ASSERT().
792 If Address is not aligned on a 32-bit boundary, then ASSERT().
794 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
795 @param AndData The value to AND with the PCI configuration register.
796 @param OrData The value to OR with the PCI configuration register.
798 @return The value written to the PCI configuration register.
803 PciSegmentAndThenOr32 (
810 Reads a bit field of a PCI configuration register.
812 Reads the bit field in a 32-bit PCI configuration register. The bit field is
813 specified by the StartBit and the EndBit. The value of the bit field is
816 If any reserved bits in Address are set, then ASSERT().
817 If Address is not aligned on a 32-bit boundary, then ASSERT().
818 If StartBit is greater than 31, then ASSERT().
819 If EndBit is greater than 31, then ASSERT().
820 If EndBit is less than StartBit, then ASSERT().
822 @param Address PCI configuration register to read.
823 @param StartBit The ordinal of the least significant bit in the bit field.
825 @param EndBit The ordinal of the most significant bit in the bit field.
828 @return The value of the bit field read from the PCI configuration register.
833 PciSegmentBitFieldRead32 (
840 Writes a bit field to a PCI configuration register.
842 Writes Value to the bit field of the PCI configuration register. The bit
843 field is specified by the StartBit and the EndBit. All other bits in the
844 destination PCI configuration register are preserved. The new value of the
845 32-bit register is returned.
847 If any reserved bits in Address are set, then ASSERT().
848 If Address is not aligned on a 32-bit boundary, then ASSERT().
849 If StartBit is greater than 31, then ASSERT().
850 If EndBit is greater than 31, then ASSERT().
851 If EndBit is less than StartBit, then ASSERT().
852 If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
854 @param Address PCI configuration register to write.
855 @param StartBit The ordinal of the least significant bit in the bit field.
857 @param EndBit The ordinal of the most significant bit in the bit field.
859 @param Value New value of the bit field.
861 @return The value written back to the PCI configuration register.
866 PciSegmentBitFieldWrite32 (
874 Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
875 writes the result back to the bit field in the 32-bit port.
877 Reads the 32-bit PCI configuration register specified by Address, performs a
878 bitwise OR between the read result and the value specified by
879 OrData, and writes the result to the 32-bit PCI configuration register
880 specified by Address. The value written to the PCI configuration register is
881 returned. This function must guarantee that all PCI read and write operations
882 are serialized. Extra left bits in OrData are stripped.
884 If any reserved bits in Address are set, then ASSERT().
885 If StartBit is greater than 31, then ASSERT().
886 If EndBit is greater than 31, then ASSERT().
887 If EndBit is less than StartBit, then ASSERT().
888 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
890 @param Address PCI configuration register to write.
891 @param StartBit The ordinal of the least significant bit in the bit field.
893 @param EndBit The ordinal of the most significant bit in the bit field.
895 @param OrData The value to OR with the PCI configuration register.
897 @return The value written back to the PCI configuration register.
902 PciSegmentBitFieldOr32 (
910 Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
911 AND, and writes the result back to the bit field in the 32-bit register.
914 Reads the 32-bit PCI configuration register specified by Address, performs a bitwise
915 AND between the read result and the value specified by AndData, and writes the result
916 to the 32-bit PCI configuration register specified by Address. The value written to
917 the PCI configuration register is returned. This function must guarantee that all PCI
918 read and write operations are serialized. Extra left bits in AndData are stripped.
919 If any reserved bits in Address are set, then ASSERT().
920 If Address is not aligned on a 32-bit boundary, then ASSERT().
921 If StartBit is greater than 31, then ASSERT().
922 If EndBit is greater than 31, then ASSERT().
923 If EndBit is less than StartBit, then ASSERT().
924 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
926 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
927 @param StartBit The ordinal of the least significant bit in the bit field.
929 @param EndBit The ordinal of the most significant bit in the bit field.
931 @param AndData The value to AND with the PCI configuration register.
933 @return The value written back to the PCI configuration register.
938 PciSegmentBitFieldAnd32 (
946 Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
947 bitwise OR, and writes the result back to the bit field in the
950 Reads the 32-bit PCI configuration register specified by Address, performs a
951 bitwise AND followed by a bitwise OR between the read result and
952 the value specified by AndData, and writes the result to the 32-bit PCI
953 configuration register specified by Address. The value written to the PCI
954 configuration register is returned. This function must guarantee that all PCI
955 read and write operations are serialized. Extra left bits in both AndData and
958 If any reserved bits in Address are set, then ASSERT().
959 If StartBit is greater than 31, then ASSERT().
960 If EndBit is greater than 31, then ASSERT().
961 If EndBit is less than StartBit, then ASSERT().
962 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
963 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
965 @param Address PCI configuration register to write.
966 @param StartBit The ordinal of the least significant bit in the bit field.
968 @param EndBit The ordinal of the most significant bit in the bit field.
970 @param AndData The value to AND with the PCI configuration register.
971 @param OrData The value to OR with the result of the AND operation.
973 @return The value written back to the PCI configuration register.
978 PciSegmentBitFieldAndThenOr32 (
987 Reads a range of PCI configuration registers into a caller supplied buffer.
989 Reads the range of PCI configuration registers specified by StartAddress and
990 Size into the buffer specified by Buffer. This function only allows the PCI
991 configuration registers from a single PCI function to be read. Size is
992 returned. When possible 32-bit PCI configuration read cycles are used to read
993 from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
994 and 16-bit PCI configuration read cycles may be used at the beginning and the
997 If any reserved bits in StartAddress are set, then ASSERT().
998 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
999 If Size > 0 and Buffer is NULL, then ASSERT().
1001 @param StartAddress Starting address that encodes the PCI Segment, Bus, Device,
1002 Function and Register.
1003 @param Size Size in bytes of the transfer.
1004 @param Buffer Pointer to a buffer receiving the data read.
1011 PciSegmentReadBuffer (
1012 IN UINT64 StartAddress
,
1018 Copies the data in a caller supplied buffer to a specified range of PCI
1019 configuration space.
1021 Writes the range of PCI configuration registers specified by StartAddress and
1022 Size from the buffer specified by Buffer. This function only allows the PCI
1023 configuration registers from a single PCI function to be written. Size is
1024 returned. When possible 32-bit PCI configuration write cycles are used to
1025 write from StartAdress to StartAddress + Size. Due to alignment restrictions,
1026 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
1027 and the end of the range.
1029 If any reserved bits in StartAddress are set, then ASSERT().
1030 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1031 If Size > 0 and Buffer is NULL, then ASSERT().
1033 @param StartAddress Starting address that encodes the PCI Segment, Bus, Device,
1034 Function and Register.
1035 @param Size Size in bytes of the transfer.
1036 @param Buffer Pointer to a buffer containing the data to write.
1038 @return The parameter of Size.
1043 PciSegmentWriteBuffer (
1044 IN UINT64 StartAddress
,