MdePkg/Include/Library/PciSegmentLib.h

   1 /** @file
   2   Provides services to access PCI Configuration Space on a platform with multiple PCI segments.
   3
   4   The PCI Segment Library function provide services to read, write, and modify the PCI configuration
   5   registers on PCI root bridges on any supported PCI segment.  These library services take a single
   6   address parameter that encodes the PCI Segment, PCI Bus, PCI Device, PCI Function, and PCI Register.
   7   The layout of this address parameter is as follows:
   8
   9             PCI Register: Bits 0..11
  10             PCI Function  Bits 12..14
  11             PCI Device  Bits 15..19
  12             PCI Bus Bits 20..27
  13             Reserved  Bits 28..31.  Must be 0.
  14             PCI Segment Bits 32..47
  15             Reserved  Bits 48..63.  Must be 0.
  16
  17   | Reserved (MBZ) | Segment | Reserved (MBZ) |     Bus     | Device | Function | Register |
  18   63             48  47    32  31           28 27         20 19    15 14      12 11         0
  19
  20   These functions perform PCI configuration cycles using the default PCI configuration access
  21   method.  This may use I/O ports 0xCF8 and 0xCFC to perform PCI configuration accesses, or it
  22   may use MMIO registers relative to the PcdPciExpressBaseAddress, or it may use some alternate
  23   access method.  Modules will typically use the PCI Segment Library for its PCI configuration
  24   accesses when PCI Segments other than Segment #0 must be accessed.
  25
  26 Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
  27 SPDX-License-Identifier: BSD-2-Clause-Patent
  28
  29 **/
  30
  31 #ifndef __PCI_SEGMENT_LIB__
  32 #define __PCI_SEGMENT_LIB__
  33
  34 /**
  35   Macro that converts PCI Segment, PCI Bus, PCI Device, PCI Function,
  36   and PCI Register to an address that can be passed to the PCI Segment Library functions.
  37
  38   Computes an address that is compatible with the PCI Segment Library functions.
  39   The unused upper bits of Segment, Bus, Device, Function,
  40   and Register are stripped prior to the generation of the address.
  41
  42   @param  Segment   PCI Segment number.  Range 0..65535.
  43   @param  Bus       PCI Bus number.  Range 0..255.
  44   @param  Device    PCI Device number.  Range 0..31.
  45   @param  Function  PCI Function number.  Range 0..7.
  46   @param  Register  PCI Register number.  Range 0..255 for PCI.  Range 0..4095 for PCI Express.
  47
  48   @return The address that is compatible with the PCI Segment Library functions.
  49
  50 **/
  51 #define PCI_SEGMENT_LIB_ADDRESS(Segment, Bus, Device, Function, Register) \
  52   ((Segment != 0) ? \
  53     ( ((Register) & 0xfff)                 | \
  54       (((Function) & 0x07) << 12)          | \
  55       (((Device) & 0x1f) << 15)            | \
  56       (((Bus) & 0xff) << 20)               | \
  57       (LShiftU64 ((Segment) & 0xffff, 32))   \
  58     ) :                                      \
  59     ( ((Register) & 0xfff)                 | \
  60       (((Function) & 0x07) << 12)          | \
  61       (((Device) & 0x1f) << 15)            | \
  62       (((Bus) & 0xff) << 20)                 \
  63     )                                        \
  64   )
  65
  66 /**
  67   Register a PCI device so PCI configuration registers may be accessed after
  68   SetVirtualAddressMap().
  69
  70   If any reserved bits in Address are set, then ASSERT().
  71
  72   @param  Address Address that encodes the PCI Bus, Device, Function and
  73                   Register.
  74
  75   @retval RETURN_SUCCESS           The PCI device was registered for runtime access.
  76   @retval RETURN_UNSUPPORTED       An attempt was made to call this function
  77                                    after ExitBootServices().
  78   @retval RETURN_UNSUPPORTED       The resources required to access the PCI device
  79                                    at runtime could not be mapped.
  80   @retval RETURN_OUT_OF_RESOURCES  There are not enough resources available to
  81                                    complete the registration.
  82
  83 **/
  84 RETURN_STATUS
  85 EFIAPI
  86 PciSegmentRegisterForRuntimeAccess (
  87   IN UINTN  Address
  88   );
  89
  90 /**
  91   Reads an 8-bit PCI configuration register.
  92
  93   Reads and returns the 8-bit PCI configuration register specified by Address.
  94   This function must guarantee that all PCI read and write operations are serialized.
  95
  96   If any reserved bits in Address are set, then ASSERT().
  97
  98   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
  99
 100   @return The 8-bit PCI configuration register specified by Address.
 101
 102 **/
 103 UINT8
 104 EFIAPI
 105 PciSegmentRead8 (
 106   IN UINT64  Address
 107   );
 108
 109 /**
 110   Writes an 8-bit PCI configuration register.
 111
 112   Writes the 8-bit PCI configuration register specified by Address with the value specified by Value.
 113   Value is returned.  This function must guarantee that all PCI read and write operations are serialized.
 114
 115   If any reserved bits in Address are set, then ASSERT().
 116
 117   @param  Address     Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 118   @param  Value       The value to write.
 119
 120   @return The value written to the PCI configuration register.
 121
 122 **/
 123 UINT8
 124 EFIAPI
 125 PciSegmentWrite8 (
 126   IN UINT64  Address,
 127   IN UINT8   Value
 128   );
 129
 130 /**
 131   Performs a bitwise OR of an 8-bit PCI configuration register with an 8-bit value.
 132
 133   Reads the 8-bit PCI configuration register specified by Address,
 134   performs a bitwise OR between the read result and the value specified by OrData,
 135   and writes the result to the 8-bit PCI configuration register specified by Address.
 136   The value written to the PCI configuration register is returned.
 137   This function must guarantee that all PCI read and write operations are serialized.
 138
 139   If any reserved bits in Address are set, then ASSERT().
 140
 141   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 142   @param  OrData    The value to OR with the PCI configuration register.
 143
 144   @return The value written to the PCI configuration register.
 145
 146 **/
 147 UINT8
 148 EFIAPI
 149 PciSegmentOr8 (
 150   IN UINT64  Address,
 151   IN UINT8   OrData
 152   );
 153
 154 /**
 155   Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value.
 156
 157   Reads the 8-bit PCI configuration register specified by Address,
 158   performs a bitwise AND between the read result and the value specified by AndData,
 159   and writes the result to the 8-bit PCI configuration register specified by Address.
 160   The value written to the PCI configuration register is returned.
 161   This function must guarantee that all PCI read and write operations are serialized.
 162   If any reserved bits in Address are set, then ASSERT().
 163
 164   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 165   @param  AndData   The value to AND with the PCI configuration register.
 166
 167   @return The value written to the PCI configuration register.
 168
 169 **/
 170 UINT8
 171 EFIAPI
 172 PciSegmentAnd8 (
 173   IN UINT64  Address,
 174   IN UINT8   AndData
 175   );
 176
 177 /**
 178   Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value,
 179   followed a  bitwise OR with another 8-bit value.
 180
 181   Reads the 8-bit PCI configuration register specified by Address,
 182   performs a bitwise AND between the read result and the value specified by AndData,
 183   performs a bitwise OR between the result of the AND operation and the value specified by OrData,
 184   and writes the result to the 8-bit PCI configuration register specified by Address.
 185   The value written to the PCI configuration register is returned.
 186   This function must guarantee that all PCI read and write operations are serialized.
 187
 188   If any reserved bits in Address are set, then ASSERT().
 189
 190   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 191   @param  AndData   The value to AND with the PCI configuration register.
 192   @param  OrData    The value to OR with the PCI configuration register.
 193
 194   @return The value written to the PCI configuration register.
 195
 196 **/
 197 UINT8
 198 EFIAPI
 199 PciSegmentAndThenOr8 (
 200   IN UINT64  Address,
 201   IN UINT8   AndData,
 202   IN UINT8   OrData
 203   );
 204
 205 /**
 206   Reads a bit field of a PCI configuration register.
 207
 208   Reads the bit field in an 8-bit PCI configuration register. The bit field is
 209   specified by the StartBit and the EndBit. The value of the bit field is
 210   returned.
 211
 212   If any reserved bits in Address are set, then ASSERT().
 213   If StartBit is greater than 7, then ASSERT().
 214   If EndBit is greater than 7, then ASSERT().
 215   If EndBit is less than StartBit, then ASSERT().
 216
 217   @param  Address   PCI configuration register to read.
 218   @param  StartBit  The ordinal of the least significant bit in the bit field.
 219                     Range 0..7.
 220   @param  EndBit    The ordinal of the most significant bit in the bit field.
 221                     Range 0..7.
 222
 223   @return The value of the bit field read from the PCI configuration register.
 224
 225 **/
 226 UINT8
 227 EFIAPI
 228 PciSegmentBitFieldRead8 (
 229   IN UINT64  Address,
 230   IN UINTN   StartBit,
 231   IN UINTN   EndBit
 232   );
 233
 234 /**
 235   Writes a bit field to a PCI configuration register.
 236
 237   Writes Value to the bit field of the PCI configuration register. The bit
 238   field is specified by the StartBit and the EndBit. All other bits in the
 239   destination PCI configuration register are preserved. The new value of the
 240   8-bit register is returned.
 241
 242   If any reserved bits in Address are set, then ASSERT().
 243   If StartBit is greater than 7, then ASSERT().
 244   If EndBit is greater than 7, then ASSERT().
 245   If EndBit is less than StartBit, then ASSERT().
 246   If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
 247
 248   @param  Address   PCI configuration register to write.
 249   @param  StartBit  The ordinal of the least significant bit in the bit field.
 250                     Range 0..7.
 251   @param  EndBit    The ordinal of the most significant bit in the bit field.
 252                     Range 0..7.
 253   @param  Value     New value of the bit field.
 254
 255   @return The value written back to the PCI configuration register.
 256
 257 **/
 258 UINT8
 259 EFIAPI
 260 PciSegmentBitFieldWrite8 (
 261   IN UINT64  Address,
 262   IN UINTN   StartBit,
 263   IN UINTN   EndBit,
 264   IN UINT8   Value
 265   );
 266
 267 /**
 268   Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
 269   writes the result back to the bit field in the 8-bit port.
 270
 271   Reads the 8-bit PCI configuration register specified by Address, performs a
 272   bitwise OR between the read result and the value specified by
 273   OrData, and writes the result to the 8-bit PCI configuration register
 274   specified by Address. The value written to the PCI configuration register is
 275   returned. This function must guarantee that all PCI read and write operations
 276   are serialized. Extra left bits in OrData are stripped.
 277
 278   If any reserved bits in Address are set, then ASSERT().
 279   If StartBit is greater than 7, then ASSERT().
 280   If EndBit is greater than 7, then ASSERT().
 281   If EndBit is less than StartBit, then ASSERT().
 282   If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
 283
 284   @param  Address   PCI configuration register to write.
 285   @param  StartBit  The ordinal of the least significant bit in the bit field.
 286                     Range 0..7.
 287   @param  EndBit    The ordinal of the most significant bit in the bit field.
 288                     Range 0..7.
 289   @param  OrData    The value to OR with the PCI configuration register.
 290
 291   @return The value written back to the PCI configuration register.
 292
 293 **/
 294 UINT8
 295 EFIAPI
 296 PciSegmentBitFieldOr8 (
 297   IN UINT64  Address,
 298   IN UINTN   StartBit,
 299   IN UINTN   EndBit,
 300   IN UINT8   OrData
 301   );
 302
 303 /**
 304   Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
 305   AND, and writes the result back to the bit field in the 8-bit register.
 306
 307   Reads the 8-bit PCI configuration register specified by Address, performs a
 308   bitwise AND between the read result and the value specified by AndData, and
 309   writes the result to the 8-bit PCI configuration register specified by
 310   Address. The value written to the PCI configuration register is returned.
 311   This function must guarantee that all PCI read and write operations are
 312   serialized. Extra left bits in AndData are stripped.
 313
 314   If any reserved bits in Address are set, then ASSERT().
 315   If StartBit is greater than 7, then ASSERT().
 316   If EndBit is greater than 7, then ASSERT().
 317   If EndBit is less than StartBit, then ASSERT().
 318   If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
 319
 320   @param  Address   PCI configuration register to write.
 321   @param  StartBit  The ordinal of the least significant bit in the bit field.
 322                     Range 0..7.
 323   @param  EndBit    The ordinal of the most significant bit in the bit field.
 324                     Range 0..7.
 325   @param  AndData   The value to AND with the PCI configuration register.
 326
 327   @return The value written back to the PCI configuration register.
 328
 329 **/
 330 UINT8
 331 EFIAPI
 332 PciSegmentBitFieldAnd8 (
 333   IN UINT64  Address,
 334   IN UINTN   StartBit,
 335   IN UINTN   EndBit,
 336   IN UINT8   AndData
 337   );
 338
 339 /**
 340   Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
 341   bitwise OR, and writes the result back to the bit field in the 8-bit port.
 342
 343   Reads the 8-bit PCI configuration register specified by Address, performs a
 344   bitwise AND followed by a bitwise OR between the read result and
 345   the value specified by AndData, and writes the result to the 8-bit PCI
 346   configuration register specified by Address. The value written to the PCI
 347   configuration register is returned. This function must guarantee that all PCI
 348   read and write operations are serialized. Extra left bits in both AndData and
 349   OrData are stripped.
 350
 351   If any reserved bits in Address are set, then ASSERT().
 352   If StartBit is greater than 7, then ASSERT().
 353   If EndBit is greater than 7, then ASSERT().
 354   If EndBit is less than StartBit, then ASSERT().
 355   If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
 356   If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
 357
 358   @param  Address   PCI configuration register to write.
 359   @param  StartBit  The ordinal of the least significant bit in the bit field.
 360                     Range 0..7.
 361   @param  EndBit    The ordinal of the most significant bit in the bit field.
 362                     Range 0..7.
 363   @param  AndData   The value to AND with the PCI configuration register.
 364   @param  OrData    The value to OR with the result of the AND operation.
 365
 366   @return The value written back to the PCI configuration register.
 367
 368 **/
 369 UINT8
 370 EFIAPI
 371 PciSegmentBitFieldAndThenOr8 (
 372   IN UINT64  Address,
 373   IN UINTN   StartBit,
 374   IN UINTN   EndBit,
 375   IN UINT8   AndData,
 376   IN UINT8   OrData
 377   );
 378
 379 /**
 380   Reads a 16-bit PCI configuration register.
 381
 382   Reads and returns the 16-bit PCI configuration register specified by Address.
 383   This function must guarantee that all PCI read and write operations are serialized.
 384
 385   If any reserved bits in Address are set, then ASSERT().
 386   If Address is not aligned on a 16-bit boundary, then ASSERT().
 387
 388   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 389
 390   @return The 16-bit PCI configuration register specified by Address.
 391
 392 **/
 393 UINT16
 394 EFIAPI
 395 PciSegmentRead16 (
 396   IN UINT64  Address
 397   );
 398
 399 /**
 400   Writes a 16-bit PCI configuration register.
 401
 402   Writes the 16-bit PCI configuration register specified by Address with the value specified by Value.
 403   Value is returned.  This function must guarantee that all PCI read and write operations are serialized.
 404
 405   If any reserved bits in Address are set, then ASSERT().
 406   If Address is not aligned on a 16-bit boundary, then ASSERT().
 407
 408   @param  Address     Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 409   @param  Value       The value to write.
 410
 411   @return The parameter of Value.
 412
 413 **/
 414 UINT16
 415 EFIAPI
 416 PciSegmentWrite16 (
 417   IN UINT64  Address,
 418   IN UINT16  Value
 419   );
 420
 421 /**
 422   Performs a bitwise OR of a 16-bit PCI configuration register with
 423   a 16-bit value.
 424
 425   Reads the 16-bit PCI configuration register specified by Address, performs a
 426   bitwise OR between the read result and the value specified by OrData, and
 427   writes the result to the 16-bit PCI configuration register specified by Address.
 428   The value written to the PCI configuration register is returned. This function
 429   must guarantee that all PCI read and write operations are serialized.
 430
 431   If any reserved bits in Address are set, then ASSERT().
 432   If Address is not aligned on a 16-bit boundary, then ASSERT().
 433
 434   @param  Address Address that encodes the PCI Segment, Bus, Device, Function and
 435                   Register.
 436   @param  OrData  The value to OR with the PCI configuration register.
 437
 438   @return The value written back to the PCI configuration register.
 439
 440 **/
 441 UINT16
 442 EFIAPI
 443 PciSegmentOr16 (
 444   IN UINT64  Address,
 445   IN UINT16  OrData
 446   );
 447
 448 /**
 449   Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value.
 450
 451   Reads the 16-bit PCI configuration register specified by Address,
 452   performs a bitwise AND between the read result and the value specified by AndData,
 453   and writes the result to the 16-bit PCI configuration register specified by Address.
 454   The value written to the PCI configuration register is returned.
 455   This function must guarantee that all PCI read and write operations are serialized.
 456
 457   If any reserved bits in Address are set, then ASSERT().
 458   If Address is not aligned on a 16-bit boundary, then ASSERT().
 459
 460   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 461   @param  AndData   The value to AND with the PCI configuration register.
 462
 463   @return The value written to the PCI configuration register.
 464
 465 **/
 466 UINT16
 467 EFIAPI
 468 PciSegmentAnd16 (
 469   IN UINT64  Address,
 470   IN UINT16  AndData
 471   );
 472
 473 /**
 474   Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value,
 475   followed a  bitwise OR with another 16-bit value.
 476
 477   Reads the 16-bit PCI configuration register specified by Address,
 478   performs a bitwise AND between the read result and the value specified by AndData,
 479   performs a bitwise OR between the result of the AND operation and the value specified by OrData,
 480   and writes the result to the 16-bit PCI configuration register specified by Address.
 481   The value written to the PCI configuration register is returned.
 482   This function must guarantee that all PCI read and write operations are serialized.
 483
 484   If any reserved bits in Address are set, then ASSERT().
 485   If Address is not aligned on a 16-bit boundary, then ASSERT().
 486
 487   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 488   @param  AndData   The value to AND with the PCI configuration register.
 489   @param  OrData    The value to OR with the PCI configuration register.
 490
 491   @return The value written to the PCI configuration register.
 492
 493 **/
 494 UINT16
 495 EFIAPI
 496 PciSegmentAndThenOr16 (
 497   IN UINT64  Address,
 498   IN UINT16  AndData,
 499   IN UINT16  OrData
 500   );
 501
 502 /**
 503   Reads a bit field of a PCI configuration register.
 504
 505   Reads the bit field in a 16-bit PCI configuration register. The bit field is
 506   specified by the StartBit and the EndBit. The value of the bit field is
 507   returned.
 508
 509   If any reserved bits in Address are set, then ASSERT().
 510   If Address is not aligned on a 16-bit boundary, then ASSERT().
 511   If StartBit is greater than 15, then ASSERT().
 512   If EndBit is greater than 15, then ASSERT().
 513   If EndBit is less than StartBit, then ASSERT().
 514
 515   @param  Address   PCI configuration register to read.
 516   @param  StartBit  The ordinal of the least significant bit in the bit field.
 517                     Range 0..15.
 518   @param  EndBit    The ordinal of the most significant bit in the bit field.
 519                     Range 0..15.
 520
 521   @return The value of the bit field read from the PCI configuration register.
 522
 523 **/
 524 UINT16
 525 EFIAPI
 526 PciSegmentBitFieldRead16 (
 527   IN UINT64  Address,
 528   IN UINTN   StartBit,
 529   IN UINTN   EndBit
 530   );
 531
 532 /**
 533   Writes a bit field to a PCI configuration register.
 534
 535   Writes Value to the bit field of the PCI configuration register. The bit
 536   field is specified by the StartBit and the EndBit. All other bits in the
 537   destination PCI configuration register are preserved. The new value of the
 538   16-bit register is returned.
 539
 540   If any reserved bits in Address are set, then ASSERT().
 541   If Address is not aligned on a 16-bit boundary, then ASSERT().
 542   If StartBit is greater than 15, then ASSERT().
 543   If EndBit is greater than 15, then ASSERT().
 544   If EndBit is less than StartBit, then ASSERT().
 545   If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
 546
 547   @param  Address   PCI configuration register to write.
 548   @param  StartBit  The ordinal of the least significant bit in the bit field.
 549                     Range 0..15.
 550   @param  EndBit    The ordinal of the most significant bit in the bit field.
 551                     Range 0..15.
 552   @param  Value     New value of the bit field.
 553
 554   @return The value written back to the PCI configuration register.
 555
 556 **/
 557 UINT16
 558 EFIAPI
 559 PciSegmentBitFieldWrite16 (
 560   IN UINT64  Address,
 561   IN UINTN   StartBit,
 562   IN UINTN   EndBit,
 563   IN UINT16  Value
 564   );
 565
 566 /**
 567   Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, writes
 568   the result back to the bit field in the 16-bit port.
 569
 570   Reads the 16-bit PCI configuration register specified by Address, performs a
 571   bitwise OR between the read result and the value specified by
 572   OrData, and writes the result to the 16-bit PCI configuration register
 573   specified by Address. The value written to the PCI configuration register is
 574   returned. This function must guarantee that all PCI read and write operations
 575   are serialized. Extra left bits in OrData are stripped.
 576
 577   If any reserved bits in Address are set, then ASSERT().
 578   If Address is not aligned on a 16-bit boundary, then ASSERT().
 579   If StartBit is greater than 15, then ASSERT().
 580   If EndBit is greater than 15, then ASSERT().
 581   If EndBit is less than StartBit, then ASSERT().
 582   If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
 583
 584   @param  Address   PCI configuration register to write.
 585   @param  StartBit  The ordinal of the least significant bit in the bit field.
 586                     Range 0..15.
 587   @param  EndBit    The ordinal of the most significant bit in the bit field.
 588                     Range 0..15.
 589   @param  OrData    The value to OR with the PCI configuration register.
 590
 591   @return The value written back to the PCI configuration register.
 592
 593 **/
 594 UINT16
 595 EFIAPI
 596 PciSegmentBitFieldOr16 (
 597   IN UINT64  Address,
 598   IN UINTN   StartBit,
 599   IN UINTN   EndBit,
 600   IN UINT16  OrData
 601   );
 602
 603 /**
 604   Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
 605   AND, writes the result back to the bit field in the 16-bit register.
 606
 607   Reads the 16-bit PCI configuration register specified by Address, performs a
 608   bitwise AND between the read result and the value specified by AndData, and
 609   writes the result to the 16-bit PCI configuration register specified by
 610   Address. The value written to the PCI configuration register is returned.
 611   This function must guarantee that all PCI read and write operations are
 612   serialized. Extra left bits in AndData are stripped.
 613
 614   If any reserved bits in Address are set, then ASSERT().
 615   If Address is not aligned on a 16-bit boundary, then ASSERT().
 616   If StartBit is greater than 15, then ASSERT().
 617   If EndBit is greater than 15, then ASSERT().
 618   If EndBit is less than StartBit, then ASSERT().
 619   If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
 620
 621   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 622   @param  StartBit  The ordinal of the least significant bit in the bit field.
 623                     Range 0..15.
 624   @param  EndBit    The ordinal of the most significant bit in the bit field.
 625                     Range 0..15.
 626   @param  AndData   The value to AND with the PCI configuration register.
 627
 628   @return The value written back to the PCI configuration register.
 629
 630 **/
 631 UINT16
 632 EFIAPI
 633 PciSegmentBitFieldAnd16 (
 634   IN UINT64  Address,
 635   IN UINTN   StartBit,
 636   IN UINTN   EndBit,
 637   IN UINT16  AndData
 638   );
 639
 640 /**
 641   Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
 642   bitwise OR, and writes the result back to the bit field in the
 643   16-bit port.
 644
 645   Reads the 16-bit PCI configuration register specified by Address, performs a
 646   bitwise AND followed by a bitwise OR between the read result and
 647   the value specified by AndData, and writes the result to the 16-bit PCI
 648   configuration register specified by Address. The value written to the PCI
 649   configuration register is returned. This function must guarantee that all PCI
 650   read and write operations are serialized. Extra left bits in both AndData and
 651   OrData are stripped.
 652
 653   If any reserved bits in Address are set, then ASSERT().
 654   If StartBit is greater than 15, then ASSERT().
 655   If EndBit is greater than 15, then ASSERT().
 656   If EndBit is less than StartBit, then ASSERT().
 657   If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
 658   If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
 659
 660   @param  Address   PCI configuration register to write.
 661   @param  StartBit  The ordinal of the least significant bit in the bit field.
 662                     Range 0..15.
 663   @param  EndBit    The ordinal of the most significant bit in the bit field.
 664                     Range 0..15.
 665   @param  AndData   The value to AND with the PCI configuration register.
 666   @param  OrData    The value to OR with the result of the AND operation.
 667
 668   @return The value written back to the PCI configuration register.
 669
 670 **/
 671 UINT16
 672 EFIAPI
 673 PciSegmentBitFieldAndThenOr16 (
 674   IN UINT64  Address,
 675   IN UINTN   StartBit,
 676   IN UINTN   EndBit,
 677   IN UINT16  AndData,
 678   IN UINT16  OrData
 679   );
 680
 681 /**
 682   Reads a 32-bit PCI configuration register.
 683
 684   Reads and returns the 32-bit PCI configuration register specified by Address.
 685   This function must guarantee that all PCI read and write operations are serialized.
 686
 687   If any reserved bits in Address are set, then ASSERT().
 688   If Address is not aligned on a 32-bit boundary, then ASSERT().
 689
 690   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 691
 692   @return The 32-bit PCI configuration register specified by Address.
 693
 694 **/
 695 UINT32
 696 EFIAPI
 697 PciSegmentRead32 (
 698   IN UINT64  Address
 699   );
 700
 701 /**
 702   Writes a 32-bit PCI configuration register.
 703
 704   Writes the 32-bit PCI configuration register specified by Address with the value specified by Value.
 705   Value is returned.  This function must guarantee that all PCI read and write operations are serialized.
 706
 707   If any reserved bits in Address are set, then ASSERT().
 708   If Address is not aligned on a 32-bit boundary, then ASSERT().
 709
 710   @param  Address     Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 711   @param  Value       The value to write.
 712
 713   @return The parameter of Value.
 714
 715 **/
 716 UINT32
 717 EFIAPI
 718 PciSegmentWrite32 (
 719   IN UINT64  Address,
 720   IN UINT32  Value
 721   );
 722
 723 /**
 724   Performs a bitwise OR of a 32-bit PCI configuration register with a 32-bit value.
 725
 726   Reads the 32-bit PCI configuration register specified by Address,
 727   performs a bitwise OR between the read result and the value specified by OrData,
 728   and writes the result to the 32-bit PCI configuration register specified by Address.
 729   The value written to the PCI configuration register is returned.
 730   This function must guarantee that all PCI read and write operations are serialized.
 731
 732   If any reserved bits in Address are set, then ASSERT().
 733   If Address is not aligned on a 32-bit boundary, then ASSERT().
 734
 735   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 736   @param  OrData    The value to OR with the PCI configuration register.
 737
 738   @return The value written to the PCI configuration register.
 739
 740 **/
 741 UINT32
 742 EFIAPI
 743 PciSegmentOr32 (
 744   IN UINT64  Address,
 745   IN UINT32  OrData
 746   );
 747
 748 /**
 749   Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value.
 750
 751   Reads the 32-bit PCI configuration register specified by Address,
 752   performs a bitwise AND between the read result and the value specified by AndData,
 753   and writes the result to the 32-bit PCI configuration register specified by Address.
 754   The value written to the PCI configuration register is returned.
 755   This function must guarantee that all PCI read and write operations are serialized.
 756
 757   If any reserved bits in Address are set, then ASSERT().
 758   If Address is not aligned on a 32-bit boundary, then ASSERT().
 759
 760   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 761   @param  AndData   The value to AND with the PCI configuration register.
 762
 763   @return The value written to the PCI configuration register.
 764
 765 **/
 766 UINT32
 767 EFIAPI
 768 PciSegmentAnd32 (
 769   IN UINT64  Address,
 770   IN UINT32  AndData
 771   );
 772
 773 /**
 774   Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value,
 775   followed a  bitwise OR with another 32-bit value.
 776
 777   Reads the 32-bit PCI configuration register specified by Address,
 778   performs a bitwise AND between the read result and the value specified by AndData,
 779   performs a bitwise OR between the result of the AND operation and the value specified by OrData,
 780   and writes the result to the 32-bit PCI configuration register specified by Address.
 781   The value written to the PCI configuration register is returned.
 782   This function must guarantee that all PCI read and write operations are serialized.
 783
 784   If any reserved bits in Address are set, then ASSERT().
 785   If Address is not aligned on a 32-bit boundary, then ASSERT().
 786
 787   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 788   @param  AndData   The value to AND with the PCI configuration register.
 789   @param  OrData    The value to OR with the PCI configuration register.
 790
 791   @return The value written to the PCI configuration register.
 792
 793 **/
 794 UINT32
 795 EFIAPI
 796 PciSegmentAndThenOr32 (
 797   IN UINT64  Address,
 798   IN UINT32  AndData,
 799   IN UINT32  OrData
 800   );
 801
 802 /**
 803   Reads a bit field of a PCI configuration register.
 804
 805   Reads the bit field in a 32-bit PCI configuration register. The bit field is
 806   specified by the StartBit and the EndBit. The value of the bit field is
 807   returned.
 808
 809   If any reserved bits in Address are set, then ASSERT().
 810   If Address is not aligned on a 32-bit boundary, then ASSERT().
 811   If StartBit is greater than 31, then ASSERT().
 812   If EndBit is greater than 31, then ASSERT().
 813   If EndBit is less than StartBit, then ASSERT().
 814
 815   @param  Address   PCI configuration register to read.
 816   @param  StartBit  The ordinal of the least significant bit in the bit field.
 817                     Range 0..31.
 818   @param  EndBit    The ordinal of the most significant bit in the bit field.
 819                     Range 0..31.
 820
 821   @return The value of the bit field read from the PCI configuration register.
 822
 823 **/
 824 UINT32
 825 EFIAPI
 826 PciSegmentBitFieldRead32 (
 827   IN UINT64  Address,
 828   IN UINTN   StartBit,
 829   IN UINTN   EndBit
 830   );
 831
 832 /**
 833   Writes a bit field to a PCI configuration register.
 834
 835   Writes Value to the bit field of the PCI configuration register. The bit
 836   field is specified by the StartBit and the EndBit. All other bits in the
 837   destination PCI configuration register are preserved. The new value of the
 838   32-bit register is returned.
 839
 840   If any reserved bits in Address are set, then ASSERT().
 841   If Address is not aligned on a 32-bit boundary, then ASSERT().
 842   If StartBit is greater than 31, then ASSERT().
 843   If EndBit is greater than 31, then ASSERT().
 844   If EndBit is less than StartBit, then ASSERT().
 845   If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
 846
 847   @param  Address   PCI configuration register to write.
 848   @param  StartBit  The ordinal of the least significant bit in the bit field.
 849                     Range 0..31.
 850   @param  EndBit    The ordinal of the most significant bit in the bit field.
 851                     Range 0..31.
 852   @param  Value     New value of the bit field.
 853
 854   @return The value written back to the PCI configuration register.
 855
 856 **/
 857 UINT32
 858 EFIAPI
 859 PciSegmentBitFieldWrite32 (
 860   IN UINT64  Address,
 861   IN UINTN   StartBit,
 862   IN UINTN   EndBit,
 863   IN UINT32  Value
 864   );
 865
 866 /**
 867   Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
 868   writes the result back to the bit field in the 32-bit port.
 869
 870   Reads the 32-bit PCI configuration register specified by Address, performs a
 871   bitwise OR between the read result and the value specified by
 872   OrData, and writes the result to the 32-bit PCI configuration register
 873   specified by Address. The value written to the PCI configuration register is
 874   returned. This function must guarantee that all PCI read and write operations
 875   are serialized. Extra left bits in OrData are stripped.
 876
 877   If any reserved bits in Address are set, then ASSERT().
 878   If StartBit is greater than 31, then ASSERT().
 879   If EndBit is greater than 31, then ASSERT().
 880   If EndBit is less than StartBit, then ASSERT().
 881   If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
 882
 883   @param  Address   PCI configuration register to write.
 884   @param  StartBit  The ordinal of the least significant bit in the bit field.
 885                     Range 0..31.
 886   @param  EndBit    The ordinal of the most significant bit in the bit field.
 887                     Range 0..31.
 888   @param  OrData    The value to OR with the PCI configuration register.
 889
 890   @return The value written back to the PCI configuration register.
 891
 892 **/
 893 UINT32
 894 EFIAPI
 895 PciSegmentBitFieldOr32 (
 896   IN UINT64  Address,
 897   IN UINTN   StartBit,
 898   IN UINTN   EndBit,
 899   IN UINT32  OrData
 900   );
 901
 902 /**
 903   Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
 904   AND, and writes the result back to the bit field in the 32-bit register.
 905
 906
 907   Reads the 32-bit PCI configuration register specified by Address, performs a bitwise
 908   AND between the read result and the value specified by AndData, and writes the result
 909   to the 32-bit PCI configuration register specified by Address. The value written to
 910   the PCI configuration register is returned.  This function must guarantee that all PCI
 911   read and write operations are serialized.  Extra left bits in AndData are stripped.
 912   If any reserved bits in Address are set, then ASSERT().
 913   If Address is not aligned on a 32-bit boundary, then ASSERT().
 914   If StartBit is greater than 31, then ASSERT().
 915   If EndBit is greater than 31, then ASSERT().
 916   If EndBit is less than StartBit, then ASSERT().
 917   If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
 918
 919   @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.
 920   @param  StartBit  The ordinal of the least significant bit in the bit field.
 921                     Range 0..31.
 922   @param  EndBit    The ordinal of the most significant bit in the bit field.
 923                     Range 0..31.
 924   @param  AndData   The value to AND with the PCI configuration register.
 925
 926   @return The value written back to the PCI configuration register.
 927
 928 **/
 929 UINT32
 930 EFIAPI
 931 PciSegmentBitFieldAnd32 (
 932   IN UINT64  Address,
 933   IN UINTN   StartBit,
 934   IN UINTN   EndBit,
 935   IN UINT32  AndData
 936   );
 937
 938 /**
 939   Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
 940   bitwise OR, and writes the result back to the bit field in the
 941   32-bit port.
 942
 943   Reads the 32-bit PCI configuration register specified by Address, performs a
 944   bitwise AND followed by a bitwise OR between the read result and
 945   the value specified by AndData, and writes the result to the 32-bit PCI
 946   configuration register specified by Address. The value written to the PCI
 947   configuration register is returned. This function must guarantee that all PCI
 948   read and write operations are serialized. Extra left bits in both AndData and
 949   OrData are stripped.
 950
 951   If any reserved bits in Address are set, then ASSERT().
 952   If StartBit is greater than 31, then ASSERT().
 953   If EndBit is greater than 31, then ASSERT().
 954   If EndBit is less than StartBit, then ASSERT().
 955   If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
 956   If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
 957
 958   @param  Address   PCI configuration register to write.
 959   @param  StartBit  The ordinal of the least significant bit in the bit field.
 960                     Range 0..31.
 961   @param  EndBit    The ordinal of the most significant bit in the bit field.
 962                     Range 0..31.
 963   @param  AndData   The value to AND with the PCI configuration register.
 964   @param  OrData    The value to OR with the result of the AND operation.
 965
 966   @return The value written back to the PCI configuration register.
 967
 968 **/
 969 UINT32
 970 EFIAPI
 971 PciSegmentBitFieldAndThenOr32 (
 972   IN UINT64  Address,
 973   IN UINTN   StartBit,
 974   IN UINTN   EndBit,
 975   IN UINT32  AndData,
 976   IN UINT32  OrData
 977   );
 978
 979 /**
 980   Reads a range of PCI configuration registers into a caller supplied buffer.
 981
 982   Reads the range of PCI configuration registers specified by StartAddress and
 983   Size into the buffer specified by Buffer. This function only allows the PCI
 984   configuration registers from a single PCI function to be read. Size is
 985   returned. When possible 32-bit PCI configuration read cycles are used to read
 986   from StartAddress to StartAddress + Size. Due to alignment restrictions, 8-bit
 987   and 16-bit PCI configuration read cycles may be used at the beginning and the
 988   end of the range.
 989
 990   If any reserved bits in StartAddress are set, then ASSERT().
 991   If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
 992   If Size > 0 and Buffer is NULL, then ASSERT().
 993
 994   @param  StartAddress  Starting address that encodes the PCI Segment, Bus, Device,
 995                         Function and Register.
 996   @param  Size          Size in bytes of the transfer.
 997   @param  Buffer        Pointer to a buffer receiving the data read.
 998
 999   @return Size
1000
1001 **/
1002 UINTN
1003 EFIAPI
1004 PciSegmentReadBuffer (
1005   IN  UINT64  StartAddress,
1006   IN  UINTN   Size,
1007   OUT VOID    *Buffer
1008   );
1009
1010 /**
1011   Copies the data in a caller supplied buffer to a specified range of PCI
1012   configuration space.
1013
1014   Writes the range of PCI configuration registers specified by StartAddress and
1015   Size from the buffer specified by Buffer. This function only allows the PCI
1016   configuration registers from a single PCI function to be written. Size is
1017   returned. When possible 32-bit PCI configuration write cycles are used to
1018   write from StartAddress to StartAddress + Size. Due to alignment restrictions,
1019   8-bit and 16-bit PCI configuration write cycles may be used at the beginning
1020   and the end of the range.
1021
1022   If any reserved bits in StartAddress are set, then ASSERT().
1023   If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1024   If Size > 0 and Buffer is NULL, then ASSERT().
1025
1026   @param  StartAddress  Starting address that encodes the PCI Segment, Bus, Device,
1027                         Function and Register.
1028   @param  Size          Size in bytes of the transfer.
1029   @param  Buffer        Pointer to a buffer containing the data to write.
1030
1031   @return The parameter of Size.
1032
1033 **/
1034 UINTN
1035 EFIAPI
1036 PciSegmentWriteBuffer (
1037   IN UINT64  StartAddress,
1038   IN UINTN   Size,
1039   IN VOID    *Buffer
1040   );
1041
1042 #endif