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2 Provides services to access PCI Configuration Space on a platform with multiple PCI segments.
4 The PCI Segment Library function provide services to read, write, and modify the PCI configuration
5 registers on PCI root bridges on any supported PCI segment. These library services take a single
6 address parameter that encodes the PCI Segment, PCI Bus, PCI Device, PCI Function, and PCI Register.
7 The layout of this address parameter is as follows:
9 PCI Register: Bits 0..11
10 PCI Function Bits 12..14
11 PCI Device Bits 15..19
13 Reserved Bits 28..31. Must be 0.
14 PCI Segment Bits 32..47
15 Reserved Bits 48..63. Must be 0.
17 | Reserved (MBZ) | Segment | Reserved (MBZ) | Bus | Device | Function | Register |
18 63 48 47 32 31 28 27 20 19 15 14 12 11 0
20 These functions perform PCI configuration cycles using the default PCI configuration access
21 method. This may use I/O ports 0xCF8 and 0xCFC to perform PCI configuration accesses, or it
22 may use MMIO registers relative to the PcdPciExpressBaseAddress, or it may use some alternate
23 access method. Modules will typically use the PCI Segment Library for its PCI configuration
24 accesses when PCI Segments other than Segment #0 must be accessed.
26 Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
27 SPDX-License-Identifier: BSD-2-Clause-Patent
31 #ifndef __PCI_SEGMENT_LIB__
32 #define __PCI_SEGMENT_LIB__
36 Macro that converts PCI Segment, PCI Bus, PCI Device, PCI Function,
37 and PCI Register to an address that can be passed to the PCI Segment Library functions.
39 Computes an address that is compatible with the PCI Segment Library functions.
40 The unused upper bits of Segment, Bus, Device, Function,
41 and Register are stripped prior to the generation of the address.
43 @param Segment PCI Segment number. Range 0..65535.
44 @param Bus PCI Bus number. Range 0..255.
45 @param Device PCI Device number. Range 0..31.
46 @param Function PCI Function number. Range 0..7.
47 @param Register PCI Register number. Range 0..255 for PCI. Range 0..4095 for PCI Express.
49 @return The address that is compatible with the PCI Segment Library functions.
52 #define PCI_SEGMENT_LIB_ADDRESS(Segment,Bus,Device,Function,Register) \
54 ( ((Register) & 0xfff) | \
55 (((Function) & 0x07) << 12) | \
56 (((Device) & 0x1f) << 15) | \
57 (((Bus) & 0xff) << 20) | \
58 (LShiftU64 ((Segment) & 0xffff, 32)) \
60 ( ((Register) & 0xfff) | \
61 (((Function) & 0x07) << 12) | \
62 (((Device) & 0x1f) << 15) | \
63 (((Bus) & 0xff) << 20) \
68 Register a PCI device so PCI configuration registers may be accessed after
69 SetVirtualAddressMap().
71 If any reserved bits in Address are set, then ASSERT().
73 @param Address Address that encodes the PCI Bus, Device, Function and
76 @retval RETURN_SUCCESS The PCI device was registered for runtime access.
77 @retval RETURN_UNSUPPORTED An attempt was made to call this function
78 after ExitBootServices().
79 @retval RETURN_UNSUPPORTED The resources required to access the PCI device
80 at runtime could not be mapped.
81 @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to
82 complete the registration.
87 PciSegmentRegisterForRuntimeAccess (
92 Reads an 8-bit PCI configuration register.
94 Reads and returns the 8-bit PCI configuration register specified by Address.
95 This function must guarantee that all PCI read and write operations are serialized.
97 If any reserved bits in Address are set, then ASSERT().
99 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
101 @return The 8-bit PCI configuration register specified by Address.
111 Writes an 8-bit PCI configuration register.
113 Writes the 8-bit PCI configuration register specified by Address with the value specified by Value.
114 Value is returned. This function must guarantee that all PCI read and write operations are serialized.
116 If any reserved bits in Address are set, then ASSERT().
118 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
119 @param Value The value to write.
121 @return The value written to the PCI configuration register.
132 Performs a bitwise OR of an 8-bit PCI configuration register with an 8-bit value.
134 Reads the 8-bit PCI configuration register specified by Address,
135 performs a bitwise OR between the read result and the value specified by OrData,
136 and writes the result to the 8-bit PCI configuration register specified by Address.
137 The value written to the PCI configuration register is returned.
138 This function must guarantee that all PCI read and write operations are serialized.
140 If any reserved bits in Address are set, then ASSERT().
142 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
143 @param OrData The value to OR with the PCI configuration register.
145 @return The value written to the PCI configuration register.
156 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value.
158 Reads the 8-bit PCI configuration register specified by Address,
159 performs a bitwise AND between the read result and the value specified by AndData,
160 and writes the result to the 8-bit PCI configuration register specified by Address.
161 The value written to the PCI configuration register is returned.
162 This function must guarantee that all PCI read and write operations are serialized.
163 If any reserved bits in Address are set, then ASSERT().
165 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
166 @param AndData The value to AND with the PCI configuration register.
168 @return The value written to the PCI configuration register.
179 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value,
180 followed a bitwise OR with another 8-bit value.
182 Reads the 8-bit PCI configuration register specified by Address,
183 performs a bitwise AND between the read result and the value specified by AndData,
184 performs a bitwise OR between the result of the AND operation and the value specified by OrData,
185 and writes the result to the 8-bit PCI configuration register specified by Address.
186 The value written to the PCI configuration register is returned.
187 This function must guarantee that all PCI read and write operations are serialized.
189 If any reserved bits in Address are set, then ASSERT().
191 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
192 @param AndData The value to AND with the PCI configuration register.
193 @param OrData The value to OR with the PCI configuration register.
195 @return The value written to the PCI configuration register.
200 PciSegmentAndThenOr8 (
207 Reads a bit field of a PCI configuration register.
209 Reads the bit field in an 8-bit PCI configuration register. The bit field is
210 specified by the StartBit and the EndBit. The value of the bit field is
213 If any reserved bits in Address are set, then ASSERT().
214 If StartBit is greater than 7, then ASSERT().
215 If EndBit is greater than 7, then ASSERT().
216 If EndBit is less than StartBit, then ASSERT().
218 @param Address PCI configuration register to read.
219 @param StartBit The ordinal of the least significant bit in the bit field.
221 @param EndBit The ordinal of the most significant bit in the bit field.
224 @return The value of the bit field read from the PCI configuration register.
229 PciSegmentBitFieldRead8 (
236 Writes a bit field to a PCI configuration register.
238 Writes Value to the bit field of the PCI configuration register. The bit
239 field is specified by the StartBit and the EndBit. All other bits in the
240 destination PCI configuration register are preserved. The new value of the
241 8-bit register is returned.
243 If any reserved bits in Address are set, then ASSERT().
244 If StartBit is greater than 7, then ASSERT().
245 If EndBit is greater than 7, then ASSERT().
246 If EndBit is less than StartBit, then ASSERT().
247 If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
249 @param Address PCI configuration register to write.
250 @param StartBit The ordinal of the least significant bit in the bit field.
252 @param EndBit The ordinal of the most significant bit in the bit field.
254 @param Value New value of the bit field.
256 @return The value written back to the PCI configuration register.
261 PciSegmentBitFieldWrite8 (
269 Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
270 writes the result back to the bit field in the 8-bit port.
272 Reads the 8-bit PCI configuration register specified by Address, performs a
273 bitwise OR between the read result and the value specified by
274 OrData, and writes the result to the 8-bit PCI configuration register
275 specified by Address. The value written to the PCI configuration register is
276 returned. This function must guarantee that all PCI read and write operations
277 are serialized. Extra left bits in OrData are stripped.
279 If any reserved bits in Address are set, then ASSERT().
280 If StartBit is greater than 7, then ASSERT().
281 If EndBit is greater than 7, then ASSERT().
282 If EndBit is less than StartBit, then ASSERT().
283 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
285 @param Address PCI configuration register to write.
286 @param StartBit The ordinal of the least significant bit in the bit field.
288 @param EndBit The ordinal of the most significant bit in the bit field.
290 @param OrData The value to OR with the PCI configuration register.
292 @return The value written back to the PCI configuration register.
297 PciSegmentBitFieldOr8 (
305 Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
306 AND, and writes the result back to the bit field in the 8-bit register.
308 Reads the 8-bit PCI configuration register specified by Address, performs a
309 bitwise AND between the read result and the value specified by AndData, and
310 writes the result to the 8-bit PCI configuration register specified by
311 Address. The value written to the PCI configuration register is returned.
312 This function must guarantee that all PCI read and write operations are
313 serialized. Extra left bits in AndData are stripped.
315 If any reserved bits in Address are set, then ASSERT().
316 If StartBit is greater than 7, then ASSERT().
317 If EndBit is greater than 7, then ASSERT().
318 If EndBit is less than StartBit, then ASSERT().
319 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
321 @param Address PCI configuration register to write.
322 @param StartBit The ordinal of the least significant bit in the bit field.
324 @param EndBit The ordinal of the most significant bit in the bit field.
326 @param AndData The value to AND with the PCI configuration register.
328 @return The value written back to the PCI configuration register.
333 PciSegmentBitFieldAnd8 (
341 Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
342 bitwise OR, and writes the result back to the bit field in the 8-bit port.
344 Reads the 8-bit PCI configuration register specified by Address, performs a
345 bitwise AND followed by a bitwise OR between the read result and
346 the value specified by AndData, and writes the result to the 8-bit PCI
347 configuration register specified by Address. The value written to the PCI
348 configuration register is returned. This function must guarantee that all PCI
349 read and write operations are serialized. Extra left bits in both AndData and
352 If any reserved bits in Address are set, then ASSERT().
353 If StartBit is greater than 7, then ASSERT().
354 If EndBit is greater than 7, then ASSERT().
355 If EndBit is less than StartBit, then ASSERT().
356 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
357 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
359 @param Address PCI configuration register to write.
360 @param StartBit The ordinal of the least significant bit in the bit field.
362 @param EndBit The ordinal of the most significant bit in the bit field.
364 @param AndData The value to AND with the PCI configuration register.
365 @param OrData The value to OR with the result of the AND operation.
367 @return The value written back to the PCI configuration register.
372 PciSegmentBitFieldAndThenOr8 (
381 Reads a 16-bit PCI configuration register.
383 Reads and returns the 16-bit PCI configuration register specified by Address.
384 This function must guarantee that all PCI read and write operations are serialized.
386 If any reserved bits in Address are set, then ASSERT().
387 If Address is not aligned on a 16-bit boundary, then ASSERT().
389 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
391 @return The 16-bit PCI configuration register specified by Address.
401 Writes a 16-bit PCI configuration register.
403 Writes the 16-bit PCI configuration register specified by Address with the value specified by Value.
404 Value is returned. This function must guarantee that all PCI read and write operations are serialized.
406 If any reserved bits in Address are set, then ASSERT().
407 If Address is not aligned on a 16-bit boundary, then ASSERT().
409 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
410 @param Value The value to write.
412 @return The parameter of Value.
423 Performs a bitwise OR of a 16-bit PCI configuration register with
426 Reads the 16-bit PCI configuration register specified by Address, performs a
427 bitwise OR between the read result and the value specified by OrData, and
428 writes the result to the 16-bit PCI configuration register specified by Address.
429 The value written to the PCI configuration register is returned. This function
430 must guarantee that all PCI read and write operations are serialized.
432 If any reserved bits in Address are set, then ASSERT().
433 If Address is not aligned on a 16-bit boundary, then ASSERT().
435 @param Address Address that encodes the PCI Segment, Bus, Device, Function and
437 @param OrData The value to OR with the PCI configuration register.
439 @return The value written back to the PCI configuration register.
450 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value.
452 Reads the 16-bit PCI configuration register specified by Address,
453 performs a bitwise AND between the read result and the value specified by AndData,
454 and writes the result to the 16-bit PCI configuration register specified by Address.
455 The value written to the PCI configuration register is returned.
456 This function must guarantee that all PCI read and write operations are serialized.
458 If any reserved bits in Address are set, then ASSERT().
459 If Address is not aligned on a 16-bit boundary, then ASSERT().
461 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
462 @param AndData The value to AND with the PCI configuration register.
464 @return The value written to the PCI configuration register.
475 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value,
476 followed a bitwise OR with another 16-bit value.
478 Reads the 16-bit PCI configuration register specified by Address,
479 performs a bitwise AND between the read result and the value specified by AndData,
480 performs a bitwise OR between the result of the AND operation and the value specified by OrData,
481 and writes the result to the 16-bit PCI configuration register specified by Address.
482 The value written to the PCI configuration register is returned.
483 This function must guarantee that all PCI read and write operations are serialized.
485 If any reserved bits in Address are set, then ASSERT().
486 If Address is not aligned on a 16-bit boundary, then ASSERT().
488 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
489 @param AndData The value to AND with the PCI configuration register.
490 @param OrData The value to OR with the PCI configuration register.
492 @return The value written to the PCI configuration register.
497 PciSegmentAndThenOr16 (
504 Reads a bit field of a PCI configuration register.
506 Reads the bit field in a 16-bit PCI configuration register. The bit field is
507 specified by the StartBit and the EndBit. The value of the bit field is
510 If any reserved bits in Address are set, then ASSERT().
511 If Address is not aligned on a 16-bit boundary, then ASSERT().
512 If StartBit is greater than 15, then ASSERT().
513 If EndBit is greater than 15, then ASSERT().
514 If EndBit is less than StartBit, then ASSERT().
516 @param Address PCI configuration register to read.
517 @param StartBit The ordinal of the least significant bit in the bit field.
519 @param EndBit The ordinal of the most significant bit in the bit field.
522 @return The value of the bit field read from the PCI configuration register.
527 PciSegmentBitFieldRead16 (
534 Writes a bit field to a PCI configuration register.
536 Writes Value to the bit field of the PCI configuration register. The bit
537 field is specified by the StartBit and the EndBit. All other bits in the
538 destination PCI configuration register are preserved. The new value of the
539 16-bit register is returned.
541 If any reserved bits in Address are set, then ASSERT().
542 If Address is not aligned on a 16-bit boundary, then ASSERT().
543 If StartBit is greater than 15, then ASSERT().
544 If EndBit is greater than 15, then ASSERT().
545 If EndBit is less than StartBit, then ASSERT().
546 If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
548 @param Address PCI configuration register to write.
549 @param StartBit The ordinal of the least significant bit in the bit field.
551 @param EndBit The ordinal of the most significant bit in the bit field.
553 @param Value New value of the bit field.
555 @return The value written back to the PCI configuration register.
560 PciSegmentBitFieldWrite16 (
568 Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, writes
569 the result back to the bit field in the 16-bit port.
571 Reads the 16-bit PCI configuration register specified by Address, performs a
572 bitwise OR between the read result and the value specified by
573 OrData, and writes the result to the 16-bit PCI configuration register
574 specified by Address. The value written to the PCI configuration register is
575 returned. This function must guarantee that all PCI read and write operations
576 are serialized. Extra left bits in OrData are stripped.
578 If any reserved bits in Address are set, then ASSERT().
579 If Address is not aligned on a 16-bit boundary, then ASSERT().
580 If StartBit is greater than 15, then ASSERT().
581 If EndBit is greater than 15, then ASSERT().
582 If EndBit is less than StartBit, then ASSERT().
583 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
585 @param Address PCI configuration register to write.
586 @param StartBit The ordinal of the least significant bit in the bit field.
588 @param EndBit The ordinal of the most significant bit in the bit field.
590 @param OrData The value to OR with the PCI configuration register.
592 @return The value written back to the PCI configuration register.
597 PciSegmentBitFieldOr16 (
605 Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
606 AND, writes the result back to the bit field in the 16-bit register.
608 Reads the 16-bit PCI configuration register specified by Address, performs a
609 bitwise AND between the read result and the value specified by AndData, and
610 writes the result to the 16-bit PCI configuration register specified by
611 Address. The value written to the PCI configuration register is returned.
612 This function must guarantee that all PCI read and write operations are
613 serialized. Extra left bits in AndData are stripped.
615 If any reserved bits in Address are set, then ASSERT().
616 If Address is not aligned on a 16-bit boundary, then ASSERT().
617 If StartBit is greater than 15, then ASSERT().
618 If EndBit is greater than 15, then ASSERT().
619 If EndBit is less than StartBit, then ASSERT().
620 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
622 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
623 @param StartBit The ordinal of the least significant bit in the bit field.
625 @param EndBit The ordinal of the most significant bit in the bit field.
627 @param AndData The value to AND with the PCI configuration register.
629 @return The value written back to the PCI configuration register.
634 PciSegmentBitFieldAnd16 (
642 Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
643 bitwise OR, and writes the result back to the bit field in the
646 Reads the 16-bit PCI configuration register specified by Address, performs a
647 bitwise AND followed by a bitwise OR between the read result and
648 the value specified by AndData, and writes the result to the 16-bit PCI
649 configuration register specified by Address. The value written to the PCI
650 configuration register is returned. This function must guarantee that all PCI
651 read and write operations are serialized. Extra left bits in both AndData and
654 If any reserved bits in Address are set, then ASSERT().
655 If StartBit is greater than 15, then ASSERT().
656 If EndBit is greater than 15, then ASSERT().
657 If EndBit is less than StartBit, then ASSERT().
658 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
659 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
661 @param Address PCI configuration register to write.
662 @param StartBit The ordinal of the least significant bit in the bit field.
664 @param EndBit The ordinal of the most significant bit in the bit field.
666 @param AndData The value to AND with the PCI configuration register.
667 @param OrData The value to OR with the result of the AND operation.
669 @return The value written back to the PCI configuration register.
674 PciSegmentBitFieldAndThenOr16 (
683 Reads a 32-bit PCI configuration register.
685 Reads and returns the 32-bit PCI configuration register specified by Address.
686 This function must guarantee that all PCI read and write operations are serialized.
688 If any reserved bits in Address are set, then ASSERT().
689 If Address is not aligned on a 32-bit boundary, then ASSERT().
691 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
693 @return The 32-bit PCI configuration register specified by Address.
703 Writes a 32-bit PCI configuration register.
705 Writes the 32-bit PCI configuration register specified by Address with the value specified by Value.
706 Value is returned. This function must guarantee that all PCI read and write operations are serialized.
708 If any reserved bits in Address are set, then ASSERT().
709 If Address is not aligned on a 32-bit boundary, then ASSERT().
711 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
712 @param Value The value to write.
714 @return The parameter of Value.
725 Performs a bitwise OR of a 32-bit PCI configuration register with a 32-bit value.
727 Reads the 32-bit PCI configuration register specified by Address,
728 performs a bitwise OR between the read result and the value specified by OrData,
729 and writes the result to the 32-bit PCI configuration register specified by Address.
730 The value written to the PCI configuration register is returned.
731 This function must guarantee that all PCI read and write operations are serialized.
733 If any reserved bits in Address are set, then ASSERT().
734 If Address is not aligned on a 32-bit boundary, then ASSERT().
736 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
737 @param OrData The value to OR with the PCI configuration register.
739 @return The value written to the PCI configuration register.
750 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value.
752 Reads the 32-bit PCI configuration register specified by Address,
753 performs a bitwise AND between the read result and the value specified by AndData,
754 and writes the result to the 32-bit PCI configuration register specified by Address.
755 The value written to the PCI configuration register is returned.
756 This function must guarantee that all PCI read and write operations are serialized.
758 If any reserved bits in Address are set, then ASSERT().
759 If Address is not aligned on a 32-bit boundary, then ASSERT().
761 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
762 @param AndData The value to AND with the PCI configuration register.
764 @return The value written to the PCI configuration register.
775 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value,
776 followed a bitwise OR with another 32-bit value.
778 Reads the 32-bit PCI configuration register specified by Address,
779 performs a bitwise AND between the read result and the value specified by AndData,
780 performs a bitwise OR between the result of the AND operation and the value specified by OrData,
781 and writes the result to the 32-bit PCI configuration register specified by Address.
782 The value written to the PCI configuration register is returned.
783 This function must guarantee that all PCI read and write operations are serialized.
785 If any reserved bits in Address are set, then ASSERT().
786 If Address is not aligned on a 32-bit boundary, then ASSERT().
788 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
789 @param AndData The value to AND with the PCI configuration register.
790 @param OrData The value to OR with the PCI configuration register.
792 @return The value written to the PCI configuration register.
797 PciSegmentAndThenOr32 (
804 Reads a bit field of a PCI configuration register.
806 Reads the bit field in a 32-bit PCI configuration register. The bit field is
807 specified by the StartBit and the EndBit. The value of the bit field is
810 If any reserved bits in Address are set, then ASSERT().
811 If Address is not aligned on a 32-bit boundary, then ASSERT().
812 If StartBit is greater than 31, then ASSERT().
813 If EndBit is greater than 31, then ASSERT().
814 If EndBit is less than StartBit, then ASSERT().
816 @param Address PCI configuration register to read.
817 @param StartBit The ordinal of the least significant bit in the bit field.
819 @param EndBit The ordinal of the most significant bit in the bit field.
822 @return The value of the bit field read from the PCI configuration register.
827 PciSegmentBitFieldRead32 (
834 Writes a bit field to a PCI configuration register.
836 Writes Value to the bit field of the PCI configuration register. The bit
837 field is specified by the StartBit and the EndBit. All other bits in the
838 destination PCI configuration register are preserved. The new value of the
839 32-bit register is returned.
841 If any reserved bits in Address are set, then ASSERT().
842 If Address is not aligned on a 32-bit boundary, then ASSERT().
843 If StartBit is greater than 31, then ASSERT().
844 If EndBit is greater than 31, then ASSERT().
845 If EndBit is less than StartBit, then ASSERT().
846 If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
848 @param Address PCI configuration register to write.
849 @param StartBit The ordinal of the least significant bit in the bit field.
851 @param EndBit The ordinal of the most significant bit in the bit field.
853 @param Value New value of the bit field.
855 @return The value written back to the PCI configuration register.
860 PciSegmentBitFieldWrite32 (
868 Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
869 writes the result back to the bit field in the 32-bit port.
871 Reads the 32-bit PCI configuration register specified by Address, performs a
872 bitwise OR between the read result and the value specified by
873 OrData, and writes the result to the 32-bit PCI configuration register
874 specified by Address. The value written to the PCI configuration register is
875 returned. This function must guarantee that all PCI read and write operations
876 are serialized. Extra left bits in OrData are stripped.
878 If any reserved bits in Address are set, then ASSERT().
879 If StartBit is greater than 31, then ASSERT().
880 If EndBit is greater than 31, then ASSERT().
881 If EndBit is less than StartBit, then ASSERT().
882 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
884 @param Address PCI configuration register to write.
885 @param StartBit The ordinal of the least significant bit in the bit field.
887 @param EndBit The ordinal of the most significant bit in the bit field.
889 @param OrData The value to OR with the PCI configuration register.
891 @return The value written back to the PCI configuration register.
896 PciSegmentBitFieldOr32 (
904 Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
905 AND, and writes the result back to the bit field in the 32-bit register.
908 Reads the 32-bit PCI configuration register specified by Address, performs a bitwise
909 AND between the read result and the value specified by AndData, and writes the result
910 to the 32-bit PCI configuration register specified by Address. The value written to
911 the PCI configuration register is returned. This function must guarantee that all PCI
912 read and write operations are serialized. Extra left bits in AndData are stripped.
913 If any reserved bits in Address are set, then ASSERT().
914 If Address is not aligned on a 32-bit boundary, then ASSERT().
915 If StartBit is greater than 31, then ASSERT().
916 If EndBit is greater than 31, then ASSERT().
917 If EndBit is less than StartBit, then ASSERT().
918 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
920 @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.
921 @param StartBit The ordinal of the least significant bit in the bit field.
923 @param EndBit The ordinal of the most significant bit in the bit field.
925 @param AndData The value to AND with the PCI configuration register.
927 @return The value written back to the PCI configuration register.
932 PciSegmentBitFieldAnd32 (
940 Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
941 bitwise OR, and writes the result back to the bit field in the
944 Reads the 32-bit PCI configuration register specified by Address, performs a
945 bitwise AND followed by a bitwise OR between the read result and
946 the value specified by AndData, and writes the result to the 32-bit PCI
947 configuration register specified by Address. The value written to the PCI
948 configuration register is returned. This function must guarantee that all PCI
949 read and write operations are serialized. Extra left bits in both AndData and
952 If any reserved bits in Address are set, then ASSERT().
953 If StartBit is greater than 31, then ASSERT().
954 If EndBit is greater than 31, then ASSERT().
955 If EndBit is less than StartBit, then ASSERT().
956 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
957 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
959 @param Address PCI configuration register to write.
960 @param StartBit The ordinal of the least significant bit in the bit field.
962 @param EndBit The ordinal of the most significant bit in the bit field.
964 @param AndData The value to AND with the PCI configuration register.
965 @param OrData The value to OR with the result of the AND operation.
967 @return The value written back to the PCI configuration register.
972 PciSegmentBitFieldAndThenOr32 (
981 Reads a range of PCI configuration registers into a caller supplied buffer.
983 Reads the range of PCI configuration registers specified by StartAddress and
984 Size into the buffer specified by Buffer. This function only allows the PCI
985 configuration registers from a single PCI function to be read. Size is
986 returned. When possible 32-bit PCI configuration read cycles are used to read
987 from StartAddress to StartAddress + Size. Due to alignment restrictions, 8-bit
988 and 16-bit PCI configuration read cycles may be used at the beginning and the
991 If any reserved bits in StartAddress are set, then ASSERT().
992 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
993 If Size > 0 and Buffer is NULL, then ASSERT().
995 @param StartAddress Starting address that encodes the PCI Segment, Bus, Device,
996 Function and Register.
997 @param Size Size in bytes of the transfer.
998 @param Buffer Pointer to a buffer receiving the data read.
1005 PciSegmentReadBuffer (
1006 IN UINT64 StartAddress
,
1012 Copies the data in a caller supplied buffer to a specified range of PCI
1013 configuration space.
1015 Writes the range of PCI configuration registers specified by StartAddress and
1016 Size from the buffer specified by Buffer. This function only allows the PCI
1017 configuration registers from a single PCI function to be written. Size is
1018 returned. When possible 32-bit PCI configuration write cycles are used to
1019 write from StartAddress to StartAddress + Size. Due to alignment restrictions,
1020 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
1021 and the end of the range.
1023 If any reserved bits in StartAddress are set, then ASSERT().
1024 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1025 If Size > 0 and Buffer is NULL, then ASSERT().
1027 @param StartAddress Starting address that encodes the PCI Segment, Bus, Device,
1028 Function and Register.
1029 @param Size Size in bytes of the transfer.
1030 @param Buffer Pointer to a buffer containing the data to write.
1032 @return The parameter of Size.
1037 PciSegmentWriteBuffer (
1038 IN UINT64 StartAddress
,