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git.proxmox.com Git - mirror_edk2.git/blob - MdePkg/Library/BaseCacheMaintenanceLib/ArmCache.c
2 Cache Maintenance Functions. These functions vary by ARM architecture so the MdePkg
3 versions are null functions used to make sure things will compile.
5 Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
6 Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
7 SPDX-License-Identifier: BSD-2-Clause-Patent
12 // Include common header file for this module.
15 #include <Library/DebugLib.h>
18 Invalidates the entire instruction cache in cache coherency domain of the
21 Invalidates the entire instruction cache in cache coherency domain of the
27 InvalidateInstructionCache (
35 Invalidates a range of instruction cache lines in the cache coherency domain
38 Invalidates the instruction cache lines specified by Address and Length. If
39 Address is not aligned on a cache line boundary, then entire instruction
40 cache line containing Address is invalidated. If Address + Length is not
41 aligned on a cache line boundary, then the entire instruction cache line
42 containing Address + Length -1 is invalidated. This function may choose to
43 invalidate the entire instruction cache if that is more efficient than
44 invalidating the specified range. If Length is 0, then no instruction cache
45 lines are invalidated. Address is returned.
47 If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
49 @param Address The base address of the instruction cache lines to
50 invalidate. If the CPU is in a physical addressing mode, then
51 Address is a physical address. If the CPU is in a virtual
52 addressing mode, then Address is a virtual address.
54 @param Length The number of bytes to invalidate from the instruction cache.
61 InvalidateInstructionCacheRange (
66 ASSERT (Length
<= MAX_ADDRESS
- (UINTN
)Address
+ 1);
72 Writes back and invalidates the entire data cache in cache coherency domain
75 Writes Back and Invalidates the entire data cache in cache coherency domain
76 of the calling CPU. This function guarantees that all dirty cache lines are
77 written back to system memory, and also invalidates all the data cache lines
78 in the cache coherency domain of the calling CPU.
83 WriteBackInvalidateDataCache (
91 Writes back and invalidates a range of data cache lines in the cache
92 coherency domain of the calling CPU.
94 Writes back and invalidates the data cache lines specified by Address and
95 Length. If Address is not aligned on a cache line boundary, then entire data
96 cache line containing Address is written back and invalidated. If Address +
97 Length is not aligned on a cache line boundary, then the entire data cache
98 line containing Address + Length -1 is written back and invalidated. This
99 function may choose to write back and invalidate the entire data cache if
100 that is more efficient than writing back and invalidating the specified
101 range. If Length is 0, then no data cache lines are written back and
102 invalidated. Address is returned.
104 If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
106 @param Address The base address of the data cache lines to write back and
107 invalidate. If the CPU is in a physical addressing mode, then
108 Address is a physical address. If the CPU is in a virtual
109 addressing mode, then Address is a virtual address.
110 @param Length The number of bytes to write back and invalidate from the
118 WriteBackInvalidateDataCacheRange (
123 ASSERT (Length
<= MAX_ADDRESS
- (UINTN
)Address
+ 1);
129 Writes back the entire data cache in cache coherency domain of the calling
132 Writes back the entire data cache in cache coherency domain of the calling
133 CPU. This function guarantees that all dirty cache lines are written back to
134 system memory. This function may also invalidate all the data cache lines in
135 the cache coherency domain of the calling CPU.
148 Writes back a range of data cache lines in the cache coherency domain of the
151 Writes back the data cache lines specified by Address and Length. If Address
152 is not aligned on a cache line boundary, then entire data cache line
153 containing Address is written back. If Address + Length is not aligned on a
154 cache line boundary, then the entire data cache line containing Address +
155 Length -1 is written back. This function may choose to write back the entire
156 data cache if that is more efficient than writing back the specified range.
157 If Length is 0, then no data cache lines are written back. This function may
158 also invalidate all the data cache lines in the specified range of the cache
159 coherency domain of the calling CPU. Address is returned.
161 If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
163 @param Address The base address of the data cache lines to write back. If
164 the CPU is in a physical addressing mode, then Address is a
165 physical address. If the CPU is in a virtual addressing
166 mode, then Address is a virtual address.
167 @param Length The number of bytes to write back from the data cache.
174 WriteBackDataCacheRange (
179 ASSERT (Length
<= MAX_ADDRESS
- (UINTN
)Address
+ 1);
185 Invalidates the entire data cache in cache coherency domain of the calling
188 Invalidates the entire data cache in cache coherency domain of the calling
189 CPU. This function must be used with care because dirty cache lines are not
190 written back to system memory. It is typically used for cache diagnostics. If
191 the CPU does not support invalidation of the entire data cache, then a write
192 back and invalidate operation should be performed on the entire data cache.
197 InvalidateDataCache (
205 Invalidates a range of data cache lines in the cache coherency domain of the
208 Invalidates the data cache lines specified by Address and Length. If Address
209 is not aligned on a cache line boundary, then entire data cache line
210 containing Address is invalidated. If Address + Length is not aligned on a
211 cache line boundary, then the entire data cache line containing Address +
212 Length -1 is invalidated. This function must never invalidate any cache lines
213 outside the specified range. If Length is 0, then no data cache lines are
214 invalidated. Address is returned. This function must be used with care
215 because dirty cache lines are not written back to system memory. It is
216 typically used for cache diagnostics. If the CPU does not support
217 invalidation of a data cache range, then a write back and invalidate
218 operation should be performed on the data cache range.
220 If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
222 @param Address The base address of the data cache lines to invalidate. If
223 the CPU is in a physical addressing mode, then Address is a
224 physical address. If the CPU is in a virtual addressing mode,
225 then Address is a virtual address.
226 @param Length The number of bytes to invalidate from the data cache.
233 InvalidateDataCacheRange (
238 ASSERT (Length
<= MAX_ADDRESS
- (UINTN
)Address
+ 1);