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git.proxmox.com Git - mirror_edk2.git/blob - MdePkg/Library/BaseCacheMaintenanceLib/EbcCache.c
2 Cache Maintenance Functions.
4 Copyright (c) 2006, Intel Corporation<BR>
5 All rights reserved. This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
16 // Include common header file for this module.
19 #include <Library/DebugLib.h>
22 Invalidates the entire instruction cache in cache coherency domain of the
25 Invalidates the entire instruction cache in cache coherency domain of the
31 InvalidateInstructionCache (
38 Invalidates a range of instruction cache lines in the cache coherency domain
41 Invalidates the instruction cache lines specified by Address and Length. If
42 Address is not aligned on a cache line boundary, then entire instruction
43 cache line containing Address is invalidated. If Address + Length is not
44 aligned on a cache line boundary, then the entire instruction cache line
45 containing Address + Length -1 is invalidated. This function may choose to
46 invalidate the entire instruction cache if that is more efficient than
47 invalidating the specified range. If Length is 0, the no instruction cache
48 lines are invalidated. Address is returned.
50 If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
52 @param Address The base address of the instruction cache lines to
53 invalidate. If the CPU is in a physical addressing mode, then
54 Address is a physical address. If the CPU is in a virtual
55 addressing mode, then Address is a virtual address.
57 @param Length The number of bytes to invalidate from the instruction cache.
64 InvalidateInstructionCacheRange (
69 ASSERT (Length
<= MAX_ADDRESS
- (UINTN
)Address
+ 1);
74 Writes Back and Invalidates the entire data cache in cache coherency domain
77 Writes Back and Invalidates the entire data cache in cache coherency domain
78 of the calling CPU. This function guarantees that all dirty cache lines are
79 written back to system memory, and also invalidates all the data cache lines
80 in the cache coherency domain of the calling CPU.
85 WriteBackInvalidateDataCache (
92 Writes Back and Invalidates a range of data cache lines in the cache
93 coherency domain of the calling CPU.
95 Writes Back and Invalidate the data cache lines specified by Address and
96 Length. If Address is not aligned on a cache line boundary, then entire data
97 cache line containing Address is written back and invalidated. If Address +
98 Length is not aligned on a cache line boundary, then the entire data cache
99 line containing Address + Length -1 is written back and invalidated. This
100 function may choose to write back and invalidate the entire data cache if
101 that is more efficient than writing back and invalidating the specified
102 range. If Length is 0, the no data cache lines are written back and
103 invalidated. Address is returned.
105 If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
107 @param Address The base address of the data cache lines to write back and
108 invalidate. If the CPU is in a physical addressing mode, then
109 Address is a physical address. If the CPU is in a virtual
110 addressing mode, then Address is a virtual address.
111 @param Length The number of bytes to write back and invalidate from the
119 WriteBackInvalidateDataCacheRange (
124 ASSERT (Length
<= MAX_ADDRESS
- (UINTN
)Address
+ 1);
129 Writes Back the entire data cache in cache coherency domain of the calling
132 Writes Back the entire data cache in cache coherency domain of the calling
133 CPU. This function guarantees that all dirty cache lines are written back to
134 system memory. This function may also invalidate all the data cache lines in
135 the cache coherency domain of the calling CPU.
147 Writes Back a range of data cache lines in the cache coherency domain of the
150 Writes Back the data cache lines specified by Address and Length. If Address
151 is not aligned on a cache line boundary, then entire data cache line
152 containing Address is written back. If Address + Length is not aligned on a
153 cache line boundary, then the entire data cache line containing Address +
154 Length -1 is written back. This function may choose to write back the entire
155 data cache if that is more efficient than writing back the specified range.
156 If Length is 0, the no data cache lines are written back. This function may
157 also invalidate all the data cache lines in the specified range of the cache
158 coherency domain of the calling CPU. Address is returned.
160 If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
162 @param Address The base address of the data cache lines to write back. If
163 the CPU is in a physical addressing mode, then Address is a
164 physical address. If the CPU is in a virtual addressing
165 mode, then Address is a virtual address.
166 @param Length The number of bytes to write back from the data cache.
173 WriteBackDataCacheRange (
178 ASSERT (Length
<= MAX_ADDRESS
- (UINTN
)Address
+ 1);
183 Invalidates the entire data cache in cache coherency domain of the calling
186 Invalidates the entire data cache in cache coherency domain of the calling
187 CPU. This function must be used with care because dirty cache lines are not
188 written back to system memory. It is typically used for cache diagnostics. If
189 the CPU does not support invalidation of the entire data cache, then a write
190 back and invalidate operation should be performed on the entire data cache.
195 InvalidateDataCache (
202 Invalidates a range of data cache lines in the cache coherency domain of the
205 Invalidates the data cache lines specified by Address and Length. If Address
206 is not aligned on a cache line boundary, then entire data cache line
207 containing Address is invalidated. If Address + Length is not aligned on a
208 cache line boundary, then the entire data cache line containing Address +
209 Length -1 is invalidated. This function must never invalidate any cache lines
210 outside the specified range. If Length is 0, the no data cache lines are
211 invalidated. Address is returned. This function must be used with care
212 because dirty cache lines are not written back to system memory. It is
213 typically used for cache diagnostics. If the CPU does not support
214 invalidation of a data cache range, then a write back and invalidate
215 operation should be performed on the data cache range.
217 If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
219 @param Address The base address of the data cache lines to invalidate. If
220 the CPU is in a physical addressing mode, then Address is a
221 physical address. If the CPU is in a virtual addressing mode,
222 then Address is a virtual address.
223 @param Length The number of bytes to invalidate from the data cache.
230 InvalidateDataCacheRange (
235 ASSERT (Length
<= MAX_ADDRESS
- (UINTN
)Address
+ 1);