MdePkg/Library/BaseCacheMaintenanceLib/EbcCache.c

   1 /** @file
   2   Cache Maintenance Functions.
   3
   4   Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
   5   SPDX-License-Identifier: BSD-2-Clause-Patent
   6
   7 **/
   8
   9 #include <Base.h>
  10 #include <Library/DebugLib.h>
  11
  12 /**
  13   Invalidates the entire instruction cache in cache coherency domain of the
  14   calling CPU.
  15
  16 **/
  17 VOID
  18 EFIAPI
  19 InvalidateInstructionCache (
  20   VOID
  21   )
  22 {
  23 }
  24
  25 /**
  26   Invalidates a range of instruction cache lines in the cache coherency domain
  27   of the calling CPU.
  28
  29   Invalidates the instruction cache lines specified by Address and Length. If
  30   Address is not aligned on a cache line boundary, then entire instruction
  31   cache line containing Address is invalidated. If Address + Length is not
  32   aligned on a cache line boundary, then the entire instruction cache line
  33   containing Address + Length -1 is invalidated. This function may choose to
  34   invalidate the entire instruction cache if that is more efficient than
  35   invalidating the specified range. If Length is 0, then no instruction cache
  36   lines are invalidated. Address is returned.
  37
  38   If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
  39
  40   @param  Address The base address of the instruction cache lines to
  41                   invalidate. If the CPU is in a physical addressing mode, then
  42                   Address is a physical address. If the CPU is in a virtual
  43                   addressing mode, then Address is a virtual address.
  44
  45   @param  Length  The number of bytes to invalidate from the instruction cache.
  46
  47   @return Address.
  48
  49 **/
  50 VOID *
  51 EFIAPI
  52 InvalidateInstructionCacheRange (
  53   IN      VOID   *Address,
  54   IN      UINTN  Length
  55   )
  56 {
  57   ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
  58   return Address;
  59 }
  60
  61 /**
  62   Writes back and invalidates the entire data cache in cache coherency domain
  63   of the calling CPU.
  64
  65   Writes back and invalidates the entire data cache in cache coherency domain
  66   of the calling CPU. This function guarantees that all dirty cache lines are
  67   written back to system memory, and also invalidates all the data cache lines
  68   in the cache coherency domain of the calling CPU.
  69
  70 **/
  71 VOID
  72 EFIAPI
  73 WriteBackInvalidateDataCache (
  74   VOID
  75   )
  76 {
  77 }
  78
  79 /**
  80   Writes back and invalidates a range of data cache lines in the cache
  81   coherency domain of the calling CPU.
  82
  83   Writes Back and Invalidate the data cache lines specified by Address and
  84   Length. If Address is not aligned on a cache line boundary, then entire data
  85   cache line containing Address is written back and invalidated. If Address +
  86   Length is not aligned on a cache line boundary, then the entire data cache
  87   line containing Address + Length -1 is written back and invalidated. This
  88   function may choose to write back and invalidate the entire data cache if
  89   that is more efficient than writing back and invalidating the specified
  90   range. If Length is 0, then no data cache lines are written back and
  91   invalidated. Address is returned.
  92
  93   If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
  94
  95   @param  Address The base address of the data cache lines to write back and
  96                   invalidate. If the CPU is in a physical addressing mode, then
  97                   Address is a physical address. If the CPU is in a virtual
  98                   addressing mode, then Address is a virtual address.
  99   @param  Length  The number of bytes to write back and invalidate from the
 100                   data cache.
 101
 102   @return Address of cache invalidation.
 103
 104 **/
 105 VOID *
 106 EFIAPI
 107 WriteBackInvalidateDataCacheRange (
 108   IN      VOID   *Address,
 109   IN      UINTN  Length
 110   )
 111 {
 112   ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
 113   return Address;
 114 }
 115
 116 /**
 117   Writes back the entire data cache in cache coherency domain of the calling
 118   CPU.
 119
 120   Writes back the entire data cache in cache coherency domain of the calling
 121   CPU. This function guarantees that all dirty cache lines are written back to
 122   system memory. This function may also invalidate all the data cache lines in
 123   the cache coherency domain of the calling CPU.
 124
 125 **/
 126 VOID
 127 EFIAPI
 128 WriteBackDataCache (
 129   VOID
 130   )
 131 {
 132 }
 133
 134 /**
 135   Writes back a range of data cache lines in the cache coherency domain of the
 136   calling CPU.
 137
 138   Writes back the data cache lines specified by Address and Length. If Address
 139   is not aligned on a cache line boundary, then entire data cache line
 140   containing Address is written back. If Address + Length is not aligned on a
 141   cache line boundary, then the entire data cache line containing Address +
 142   Length -1 is written back. This function may choose to write back the entire
 143   data cache if that is more efficient than writing back the specified range.
 144   If Length is 0, then no data cache lines are written back. This function may
 145   also invalidate all the data cache lines in the specified range of the cache
 146   coherency domain of the calling CPU. Address is returned.
 147
 148   If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
 149
 150   @param  Address The base address of the data cache lines to write back. If
 151                   the CPU is in a physical addressing mode, then Address is a
 152                   physical address. If the CPU is in a virtual addressing
 153                   mode, then Address is a virtual address.
 154   @param  Length  The number of bytes to write back from the data cache.
 155
 156   @return Address of cache written in main memory.
 157
 158 **/
 159 VOID *
 160 EFIAPI
 161 WriteBackDataCacheRange (
 162   IN      VOID   *Address,
 163   IN      UINTN  Length
 164   )
 165 {
 166   ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
 167   return Address;
 168 }
 169
 170 /**
 171   Invalidates the entire data cache in cache coherency domain of the calling
 172   CPU.
 173
 174   Invalidates the entire data cache in cache coherency domain of the calling
 175   CPU. This function must be used with care because dirty cache lines are not
 176   written back to system memory. It is typically used for cache diagnostics. If
 177   the CPU does not support invalidation of the entire data cache, then a write
 178   back and invalidate operation should be performed on the entire data cache.
 179
 180 **/
 181 VOID
 182 EFIAPI
 183 InvalidateDataCache (
 184   VOID
 185   )
 186 {
 187 }
 188
 189 /**
 190   Invalidates a range of data cache lines in the cache coherency domain of the
 191   calling CPU.
 192
 193   Invalidates the data cache lines specified by Address and Length. If Address
 194   is not aligned on a cache line boundary, then entire data cache line
 195   containing Address is invalidated. If Address + Length is not aligned on a
 196   cache line boundary, then the entire data cache line containing Address +
 197   Length -1 is invalidated. This function must never invalidate any cache lines
 198   outside the specified range. If Length is 0, then no data cache lines are
 199   invalidated. Address is returned. This function must be used with care
 200   because dirty cache lines are not written back to system memory. It is
 201   typically used for cache diagnostics. If the CPU does not support
 202   invalidation of a data cache range, then a write back and invalidate
 203   operation should be performed on the data cache range.
 204
 205   If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
 206
 207   @param  Address The base address of the data cache lines to invalidate. If
 208                   the CPU is in a physical addressing mode, then Address is a
 209                   physical address. If the CPU is in a virtual addressing mode,
 210                   then Address is a virtual address.
 211   @param  Length  The number of bytes to invalidate from the data cache.
 212
 213   @return Address.
 214
 215 **/
 216 VOID *
 217 EFIAPI
 218 InvalidateDataCacheRange (
 219   IN      VOID   *Address,
 220   IN      UINTN  Length
 221   )
 222 {
 223   ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
 224   return Address;
 225 }