2 IA32/X64 specific Unit Test Host functions.
4 Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
5 SPDX-License-Identifier: BSD-2-Clause-Patent
9 #include "UnitTestHost.h"
12 /// Defines for mUnitTestHostBaseLibSegment indexes
14 #define UNIT_TEST_HOST_BASE_LIB_SEGMENT_CS 0
15 #define UNIT_TEST_HOST_BASE_LIB_SEGMENT_DS 1
16 #define UNIT_TEST_HOST_BASE_LIB_SEGMENT_ES 2
17 #define UNIT_TEST_HOST_BASE_LIB_SEGMENT_FS 3
18 #define UNIT_TEST_HOST_BASE_LIB_SEGMENT_GS 4
19 #define UNIT_TEST_HOST_BASE_LIB_SEGMENT_SS 5
20 #define UNIT_TEST_HOST_BASE_LIB_SEGMENT_TR 6
21 #define UNIT_TEST_HOST_BASE_LIB_SEGMENT_LDTR 7
24 /// Module global variables for simple system emulation of MSRs, CRx, DRx,
25 /// GDTR, IDTR, and Segment Selectors.
27 STATIC UINT64 mUnitTestHostBaseLibMsr
[2][0x1000];
28 STATIC UINTN mUnitTestHostBaseLibCr
[5];
29 STATIC UINTN mUnitTestHostBaseLibDr
[8];
30 STATIC UINT16 mUnitTestHostBaseLibSegment
[8];
31 STATIC IA32_DESCRIPTOR mUnitTestHostBaseLibGdtr
;
32 STATIC IA32_DESCRIPTOR mUnitTestHostBaseLibIdtr
;
35 Retrieves CPUID information.
37 Executes the CPUID instruction with EAX set to the value specified by Index.
38 This function always returns Index.
39 If Eax is not NULL, then the value of EAX after CPUID is returned in Eax.
40 If Ebx is not NULL, then the value of EBX after CPUID is returned in Ebx.
41 If Ecx is not NULL, then the value of ECX after CPUID is returned in Ecx.
42 If Edx is not NULL, then the value of EDX after CPUID is returned in Edx.
43 This function is only available on IA-32 and x64.
45 @param Index The 32-bit value to load into EAX prior to invoking the CPUID
47 @param Eax The pointer to the 32-bit EAX value returned by the CPUID
48 instruction. This is an optional parameter that may be NULL.
49 @param Ebx The pointer to the 32-bit EBX value returned by the CPUID
50 instruction. This is an optional parameter that may be NULL.
51 @param Ecx The pointer to the 32-bit ECX value returned by the CPUID
52 instruction. This is an optional parameter that may be NULL.
53 @param Edx The pointer to the 32-bit EDX value returned by the CPUID
54 instruction. This is an optional parameter that may be NULL.
61 UnitTestHostBaseLibAsmCpuid (
63 OUT UINT32
*Eax OPTIONAL
,
64 OUT UINT32
*Ebx OPTIONAL
,
65 OUT UINT32
*Ecx OPTIONAL
,
66 OUT UINT32
*Edx OPTIONAL
89 Retrieves CPUID information using an extended leaf identifier.
91 Executes the CPUID instruction with EAX set to the value specified by Index
92 and ECX set to the value specified by SubIndex. This function always returns
93 Index. This function is only available on IA-32 and x64.
95 If Eax is not NULL, then the value of EAX after CPUID is returned in Eax.
96 If Ebx is not NULL, then the value of EBX after CPUID is returned in Ebx.
97 If Ecx is not NULL, then the value of ECX after CPUID is returned in Ecx.
98 If Edx is not NULL, then the value of EDX after CPUID is returned in Edx.
100 @param Index The 32-bit value to load into EAX prior to invoking the
102 @param SubIndex The 32-bit value to load into ECX prior to invoking the
104 @param Eax The pointer to the 32-bit EAX value returned by the CPUID
105 instruction. This is an optional parameter that may be
107 @param Ebx The pointer to the 32-bit EBX value returned by the CPUID
108 instruction. This is an optional parameter that may be
110 @param Ecx The pointer to the 32-bit ECX value returned by the CPUID
111 instruction. This is an optional parameter that may be
113 @param Edx The pointer to the 32-bit EDX value returned by the CPUID
114 instruction. This is an optional parameter that may be
122 UnitTestHostBaseLibAsmCpuidEx (
125 OUT UINT32
*Eax OPTIONAL
,
126 OUT UINT32
*Ebx OPTIONAL
,
127 OUT UINT32
*Ecx OPTIONAL
,
128 OUT UINT32
*Edx OPTIONAL
151 Set CD bit and clear NW bit of CR0 followed by a WBINVD.
153 Disables the caches by setting the CD bit of CR0 to 1, clearing the NW bit of CR0 to 0,
154 and executing a WBINVD instruction. This function is only available on IA-32 and x64.
159 UnitTestHostBaseLibAsmDisableCache (
166 Perform a WBINVD and clear both the CD and NW bits of CR0.
168 Enables the caches by executing a WBINVD instruction and then clear both the CD and NW
169 bits of CR0 to 0. This function is only available on IA-32 and x64.
174 UnitTestHostBaseLibAsmEnableCache (
181 Returns a 64-bit Machine Specific Register(MSR).
183 Reads and returns the 64-bit MSR specified by Index. No parameter checking is
184 performed on Index, and some Index values may cause CPU exceptions. The
185 caller must either guarantee that Index is valid, or the caller must set up
186 exception handlers to catch the exceptions. This function is only available
189 @param Index The 32-bit MSR index to read.
191 @return The value of the MSR identified by Index.
196 UnitTestHostBaseLibAsmReadMsr64 (
200 if (Index
< 0x1000) {
201 return mUnitTestHostBaseLibMsr
[0][Index
];
204 if ((Index
>= 0xC0000000) && (Index
< 0xC0001000)) {
205 return mUnitTestHostBaseLibMsr
[1][Index
];
212 Writes a 64-bit value to a Machine Specific Register(MSR), and returns the
215 Writes the 64-bit value specified by Value to the MSR specified by Index. The
216 64-bit value written to the MSR is returned. No parameter checking is
217 performed on Index or Value, and some of these may cause CPU exceptions. The
218 caller must either guarantee that Index and Value are valid, or the caller
219 must establish proper exception handlers. This function is only available on
222 @param Index The 32-bit MSR index to write.
223 @param Value The 64-bit value to write to the MSR.
230 UnitTestHostBaseLibAsmWriteMsr64 (
235 if (Index
< 0x1000) {
236 mUnitTestHostBaseLibMsr
[0][Index
] = Value
;
239 if ((Index
>= 0xC0000000) && (Index
< 0xC0001000)) {
240 mUnitTestHostBaseLibMsr
[1][Index
- 0xC00000000] = Value
;
247 Reads the current value of the Control Register 0 (CR0).
249 Reads and returns the current value of CR0. This function is only available
250 on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
253 @return The value of the Control Register 0 (CR0).
258 UnitTestHostBaseLibAsmReadCr0 (
262 return mUnitTestHostBaseLibCr
[0];
266 Reads the current value of the Control Register 2 (CR2).
268 Reads and returns the current value of CR2. This function is only available
269 on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
272 @return The value of the Control Register 2 (CR2).
277 UnitTestHostBaseLibAsmReadCr2 (
281 return mUnitTestHostBaseLibCr
[2];
285 Reads the current value of the Control Register 3 (CR3).
287 Reads and returns the current value of CR3. This function is only available
288 on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
291 @return The value of the Control Register 3 (CR3).
296 UnitTestHostBaseLibAsmReadCr3 (
300 return mUnitTestHostBaseLibCr
[3];
304 Reads the current value of the Control Register 4 (CR4).
306 Reads and returns the current value of CR4. This function is only available
307 on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
310 @return The value of the Control Register 4 (CR4).
315 UnitTestHostBaseLibAsmReadCr4 (
319 return mUnitTestHostBaseLibCr
[4];
323 Writes a value to Control Register 0 (CR0).
325 Writes and returns a new value to CR0. This function is only available on
326 IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
328 @param Cr0 The value to write to CR0.
330 @return The value written to CR0.
335 UnitTestHostBaseLibAsmWriteCr0 (
339 mUnitTestHostBaseLibCr
[0] = Cr0
;
344 Writes a value to Control Register 2 (CR2).
346 Writes and returns a new value to CR2. This function is only available on
347 IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
349 @param Cr2 The value to write to CR2.
351 @return The value written to CR2.
356 UnitTestHostBaseLibAsmWriteCr2 (
360 mUnitTestHostBaseLibCr
[2] = Cr2
;
365 Writes a value to Control Register 3 (CR3).
367 Writes and returns a new value to CR3. This function is only available on
368 IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
370 @param Cr3 The value to write to CR3.
372 @return The value written to CR3.
377 UnitTestHostBaseLibAsmWriteCr3 (
381 mUnitTestHostBaseLibCr
[3] = Cr3
;
386 Writes a value to Control Register 4 (CR4).
388 Writes and returns a new value to CR4. This function is only available on
389 IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
391 @param Cr4 The value to write to CR4.
393 @return The value written to CR4.
398 UnitTestHostBaseLibAsmWriteCr4 (
402 mUnitTestHostBaseLibCr
[4] = Cr4
;
407 Reads the current value of Debug Register 0 (DR0).
409 Reads and returns the current value of DR0. This function is only available
410 on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
413 @return The value of Debug Register 0 (DR0).
418 UnitTestHostBaseLibAsmReadDr0 (
422 return mUnitTestHostBaseLibDr
[0];
426 Reads the current value of Debug Register 1 (DR1).
428 Reads and returns the current value of DR1. This function is only available
429 on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
432 @return The value of Debug Register 1 (DR1).
437 UnitTestHostBaseLibAsmReadDr1 (
441 return mUnitTestHostBaseLibDr
[1];
445 Reads the current value of Debug Register 2 (DR2).
447 Reads and returns the current value of DR2. This function is only available
448 on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
451 @return The value of Debug Register 2 (DR2).
456 UnitTestHostBaseLibAsmReadDr2 (
460 return mUnitTestHostBaseLibDr
[2];
464 Reads the current value of Debug Register 3 (DR3).
466 Reads and returns the current value of DR3. This function is only available
467 on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
470 @return The value of Debug Register 3 (DR3).
475 UnitTestHostBaseLibAsmReadDr3 (
479 return mUnitTestHostBaseLibDr
[3];
483 Reads the current value of Debug Register 4 (DR4).
485 Reads and returns the current value of DR4. This function is only available
486 on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
489 @return The value of Debug Register 4 (DR4).
494 UnitTestHostBaseLibAsmReadDr4 (
498 return mUnitTestHostBaseLibDr
[4];
502 Reads the current value of Debug Register 5 (DR5).
504 Reads and returns the current value of DR5. This function is only available
505 on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
508 @return The value of Debug Register 5 (DR5).
513 UnitTestHostBaseLibAsmReadDr5 (
517 return mUnitTestHostBaseLibDr
[5];
521 Reads the current value of Debug Register 6 (DR6).
523 Reads and returns the current value of DR6. This function is only available
524 on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
527 @return The value of Debug Register 6 (DR6).
532 UnitTestHostBaseLibAsmReadDr6 (
536 return mUnitTestHostBaseLibDr
[6];
540 Reads the current value of Debug Register 7 (DR7).
542 Reads and returns the current value of DR7. This function is only available
543 on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
546 @return The value of Debug Register 7 (DR7).
551 UnitTestHostBaseLibAsmReadDr7 (
555 return mUnitTestHostBaseLibDr
[7];
559 Writes a value to Debug Register 0 (DR0).
561 Writes and returns a new value to DR0. This function is only available on
562 IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
564 @param Dr0 The value to write to Dr0.
566 @return The value written to Debug Register 0 (DR0).
571 UnitTestHostBaseLibAsmWriteDr0 (
575 mUnitTestHostBaseLibDr
[0] = Dr0
;
580 Writes a value to Debug Register 1 (DR1).
582 Writes and returns a new value to DR1. This function is only available on
583 IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
585 @param Dr1 The value to write to Dr1.
587 @return The value written to Debug Register 1 (DR1).
592 UnitTestHostBaseLibAsmWriteDr1 (
596 mUnitTestHostBaseLibDr
[1] = Dr1
;
601 Writes a value to Debug Register 2 (DR2).
603 Writes and returns a new value to DR2. This function is only available on
604 IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
606 @param Dr2 The value to write to Dr2.
608 @return The value written to Debug Register 2 (DR2).
613 UnitTestHostBaseLibAsmWriteDr2 (
617 mUnitTestHostBaseLibDr
[2] = Dr2
;
622 Writes a value to Debug Register 3 (DR3).
624 Writes and returns a new value to DR3. This function is only available on
625 IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
627 @param Dr3 The value to write to Dr3.
629 @return The value written to Debug Register 3 (DR3).
634 UnitTestHostBaseLibAsmWriteDr3 (
638 mUnitTestHostBaseLibDr
[3] = Dr3
;
643 Writes a value to Debug Register 4 (DR4).
645 Writes and returns a new value to DR4. This function is only available on
646 IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
648 @param Dr4 The value to write to Dr4.
650 @return The value written to Debug Register 4 (DR4).
655 UnitTestHostBaseLibAsmWriteDr4 (
659 mUnitTestHostBaseLibDr
[4] = Dr4
;
664 Writes a value to Debug Register 5 (DR5).
666 Writes and returns a new value to DR5. This function is only available on
667 IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
669 @param Dr5 The value to write to Dr5.
671 @return The value written to Debug Register 5 (DR5).
676 UnitTestHostBaseLibAsmWriteDr5 (
680 mUnitTestHostBaseLibDr
[5] = Dr5
;
685 Writes a value to Debug Register 6 (DR6).
687 Writes and returns a new value to DR6. This function is only available on
688 IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
690 @param Dr6 The value to write to Dr6.
692 @return The value written to Debug Register 6 (DR6).
697 UnitTestHostBaseLibAsmWriteDr6 (
701 mUnitTestHostBaseLibDr
[6] = Dr6
;
706 Writes a value to Debug Register 7 (DR7).
708 Writes and returns a new value to DR7. This function is only available on
709 IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
711 @param Dr7 The value to write to Dr7.
713 @return The value written to Debug Register 7 (DR7).
718 UnitTestHostBaseLibAsmWriteDr7 (
722 mUnitTestHostBaseLibDr
[7] = Dr7
;
727 Reads the current value of Code Segment Register (CS).
729 Reads and returns the current value of CS. This function is only available on
732 @return The current value of CS.
737 UnitTestHostBaseLibAsmReadCs (
741 return mUnitTestHostBaseLibSegment
[UNIT_TEST_HOST_BASE_LIB_SEGMENT_CS
];
745 Reads the current value of Data Segment Register (DS).
747 Reads and returns the current value of DS. This function is only available on
750 @return The current value of DS.
755 UnitTestHostBaseLibAsmReadDs (
759 return mUnitTestHostBaseLibSegment
[UNIT_TEST_HOST_BASE_LIB_SEGMENT_DS
];
763 Reads the current value of Extra Segment Register (ES).
765 Reads and returns the current value of ES. This function is only available on
768 @return The current value of ES.
773 UnitTestHostBaseLibAsmReadEs (
777 return mUnitTestHostBaseLibSegment
[UNIT_TEST_HOST_BASE_LIB_SEGMENT_ES
];
781 Reads the current value of FS Data Segment Register (FS).
783 Reads and returns the current value of FS. This function is only available on
786 @return The current value of FS.
791 UnitTestHostBaseLibAsmReadFs (
795 return mUnitTestHostBaseLibSegment
[UNIT_TEST_HOST_BASE_LIB_SEGMENT_FS
];
799 Reads the current value of GS Data Segment Register (GS).
801 Reads and returns the current value of GS. This function is only available on
804 @return The current value of GS.
809 UnitTestHostBaseLibAsmReadGs (
813 return mUnitTestHostBaseLibSegment
[UNIT_TEST_HOST_BASE_LIB_SEGMENT_GS
];
817 Reads the current value of Stack Segment Register (SS).
819 Reads and returns the current value of SS. This function is only available on
822 @return The current value of SS.
827 UnitTestHostBaseLibAsmReadSs (
831 return mUnitTestHostBaseLibSegment
[UNIT_TEST_HOST_BASE_LIB_SEGMENT_SS
];
835 Reads the current value of Task Register (TR).
837 Reads and returns the current value of TR. This function is only available on
840 @return The current value of TR.
845 UnitTestHostBaseLibAsmReadTr (
849 return mUnitTestHostBaseLibSegment
[UNIT_TEST_HOST_BASE_LIB_SEGMENT_TR
];
853 Reads the current Global Descriptor Table Register(GDTR) descriptor.
855 Reads and returns the current GDTR descriptor and returns it in Gdtr. This
856 function is only available on IA-32 and x64.
858 If Gdtr is NULL, then ASSERT().
860 @param Gdtr The pointer to a GDTR descriptor.
865 UnitTestHostBaseLibAsmReadGdtr (
866 OUT IA32_DESCRIPTOR
*Gdtr
869 Gdtr
= &mUnitTestHostBaseLibGdtr
;
873 Writes the current Global Descriptor Table Register (GDTR) descriptor.
875 Writes and the current GDTR descriptor specified by Gdtr. This function is
876 only available on IA-32 and x64.
878 If Gdtr is NULL, then ASSERT().
880 @param Gdtr The pointer to a GDTR descriptor.
885 UnitTestHostBaseLibAsmWriteGdtr (
886 IN CONST IA32_DESCRIPTOR
*Gdtr
889 CopyMem (&mUnitTestHostBaseLibGdtr
, Gdtr
, sizeof (IA32_DESCRIPTOR
));
893 Reads the current Interrupt Descriptor Table Register(IDTR) descriptor.
895 Reads and returns the current IDTR descriptor and returns it in Idtr. This
896 function is only available on IA-32 and x64.
898 If Idtr is NULL, then ASSERT().
900 @param Idtr The pointer to a IDTR descriptor.
905 UnitTestHostBaseLibAsmReadIdtr (
906 OUT IA32_DESCRIPTOR
*Idtr
909 Idtr
= &mUnitTestHostBaseLibIdtr
;
913 Writes the current Interrupt Descriptor Table Register(IDTR) descriptor.
915 Writes the current IDTR descriptor and returns it in Idtr. This function is
916 only available on IA-32 and x64.
918 If Idtr is NULL, then ASSERT().
920 @param Idtr The pointer to a IDTR descriptor.
925 UnitTestHostBaseLibAsmWriteIdtr (
926 IN CONST IA32_DESCRIPTOR
*Idtr
929 CopyMem (&mUnitTestHostBaseLibIdtr
, Idtr
, sizeof (IA32_DESCRIPTOR
));
933 Reads the current Local Descriptor Table Register(LDTR) selector.
935 Reads and returns the current 16-bit LDTR descriptor value. This function is
936 only available on IA-32 and x64.
938 @return The current selector of LDT.
943 UnitTestHostBaseLibAsmReadLdtr (
947 return mUnitTestHostBaseLibSegment
[UNIT_TEST_HOST_BASE_LIB_SEGMENT_LDTR
];
951 Writes the current Local Descriptor Table Register (LDTR) selector.
953 Writes and the current LDTR descriptor specified by Ldtr. This function is
954 only available on IA-32 and x64.
956 @param Ldtr 16-bit LDTR selector value.
961 UnitTestHostBaseLibAsmWriteLdtr (
965 mUnitTestHostBaseLibSegment
[UNIT_TEST_HOST_BASE_LIB_SEGMENT_LDTR
] = Ldtr
;
969 Reads the current value of a Performance Counter (PMC).
971 Reads and returns the current value of performance counter specified by
972 Index. This function is only available on IA-32 and x64.
974 @param Index The 32-bit Performance Counter index to read.
976 @return The value of the PMC specified by Index.
981 UnitTestHostBaseLibAsmReadPmc (
989 Sets up a monitor buffer that is used by AsmMwait().
991 Executes a MONITOR instruction with the register state specified by Eax, Ecx
992 and Edx. Returns Eax. This function is only available on IA-32 and x64.
994 @param Eax The value to load into EAX or RAX before executing the MONITOR
996 @param Ecx The value to load into ECX or RCX before executing the MONITOR
998 @param Edx The value to load into EDX or RDX before executing the MONITOR
1006 UnitTestHostBaseLibAsmMonitor (
1016 Executes an MWAIT instruction.
1018 Executes an MWAIT instruction with the register state specified by Eax and
1019 Ecx. Returns Eax. This function is only available on IA-32 and x64.
1021 @param Eax The value to load into EAX or RAX before executing the MONITOR
1023 @param Ecx The value to load into ECX or RCX before executing the MONITOR
1031 UnitTestHostBaseLibAsmMwait (
1040 Executes a WBINVD instruction.
1042 Executes a WBINVD instruction. This function is only available on IA-32 and
1048 UnitTestHostBaseLibAsmWbinvd (
1055 Executes a INVD instruction.
1057 Executes a INVD instruction. This function is only available on IA-32 and
1063 UnitTestHostBaseLibAsmInvd (
1070 Flushes a cache line from all the instruction and data caches within the
1071 coherency domain of the CPU.
1073 Flushed the cache line specified by LinearAddress, and returns LinearAddress.
1074 This function is only available on IA-32 and x64.
1076 @param LinearAddress The address of the cache line to flush. If the CPU is
1077 in a physical addressing mode, then LinearAddress is a
1078 physical address. If the CPU is in a virtual
1079 addressing mode, then LinearAddress is a virtual
1082 @return LinearAddress.
1086 UnitTestHostBaseLibAsmFlushCacheLine (
1087 IN VOID
*LinearAddress
1090 return LinearAddress
;
1094 Enables the 32-bit paging mode on the CPU.
1096 Enables the 32-bit paging mode on the CPU. CR0, CR3, CR4, and the page tables
1097 must be properly initialized prior to calling this service. This function
1098 assumes the current execution mode is 32-bit protected mode. This function is
1099 only available on IA-32. After the 32-bit paging mode is enabled, control is
1100 transferred to the function specified by EntryPoint using the new stack
1101 specified by NewStack and passing in the parameters specified by Context1 and
1102 Context2. Context1 and Context2 are optional and may be NULL. The function
1103 EntryPoint must never return.
1105 If the current execution mode is not 32-bit protected mode, then ASSERT().
1106 If EntryPoint is NULL, then ASSERT().
1107 If NewStack is NULL, then ASSERT().
1109 There are a number of constraints that must be followed before calling this
1111 1) Interrupts must be disabled.
1112 2) The caller must be in 32-bit protected mode with flat descriptors. This
1113 means all descriptors must have a base of 0 and a limit of 4GB.
1114 3) CR0 and CR4 must be compatible with 32-bit protected mode with flat
1116 4) CR3 must point to valid page tables that will be used once the transition
1117 is complete, and those page tables must guarantee that the pages for this
1118 function and the stack are identity mapped.
1120 @param EntryPoint A pointer to function to call with the new stack after
1122 @param Context1 A pointer to the context to pass into the EntryPoint
1123 function as the first parameter after paging is enabled.
1124 @param Context2 A pointer to the context to pass into the EntryPoint
1125 function as the second parameter after paging is enabled.
1126 @param NewStack A pointer to the new stack to use for the EntryPoint
1127 function after paging is enabled.
1132 UnitTestHostBaseLibAsmEnablePaging32 (
1133 IN SWITCH_STACK_ENTRY_POINT EntryPoint
,
1134 IN VOID
*Context1 OPTIONAL
,
1135 IN VOID
*Context2 OPTIONAL
,
1139 EntryPoint (Context1
, Context2
);
1143 Disables the 32-bit paging mode on the CPU.
1145 Disables the 32-bit paging mode on the CPU and returns to 32-bit protected
1146 mode. This function assumes the current execution mode is 32-paged protected
1147 mode. This function is only available on IA-32. After the 32-bit paging mode
1148 is disabled, control is transferred to the function specified by EntryPoint
1149 using the new stack specified by NewStack and passing in the parameters
1150 specified by Context1 and Context2. Context1 and Context2 are optional and
1151 may be NULL. The function EntryPoint must never return.
1153 If the current execution mode is not 32-bit paged mode, then ASSERT().
1154 If EntryPoint is NULL, then ASSERT().
1155 If NewStack is NULL, then ASSERT().
1157 There are a number of constraints that must be followed before calling this
1159 1) Interrupts must be disabled.
1160 2) The caller must be in 32-bit paged mode.
1161 3) CR0, CR3, and CR4 must be compatible with 32-bit paged mode.
1162 4) CR3 must point to valid page tables that guarantee that the pages for
1163 this function and the stack are identity mapped.
1165 @param EntryPoint A pointer to function to call with the new stack after
1167 @param Context1 A pointer to the context to pass into the EntryPoint
1168 function as the first parameter after paging is disabled.
1169 @param Context2 A pointer to the context to pass into the EntryPoint
1170 function as the second parameter after paging is
1172 @param NewStack A pointer to the new stack to use for the EntryPoint
1173 function after paging is disabled.
1178 UnitTestHostBaseLibAsmDisablePaging32 (
1179 IN SWITCH_STACK_ENTRY_POINT EntryPoint
,
1180 IN VOID
*Context1 OPTIONAL
,
1181 IN VOID
*Context2 OPTIONAL
,
1185 EntryPoint (Context1
, Context2
);
1189 Enables the 64-bit paging mode on the CPU.
1191 Enables the 64-bit paging mode on the CPU. CR0, CR3, CR4, and the page tables
1192 must be properly initialized prior to calling this service. This function
1193 assumes the current execution mode is 32-bit protected mode with flat
1194 descriptors. This function is only available on IA-32. After the 64-bit
1195 paging mode is enabled, control is transferred to the function specified by
1196 EntryPoint using the new stack specified by NewStack and passing in the
1197 parameters specified by Context1 and Context2. Context1 and Context2 are
1198 optional and may be 0. The function EntryPoint must never return.
1200 If the current execution mode is not 32-bit protected mode with flat
1201 descriptors, then ASSERT().
1202 If EntryPoint is 0, then ASSERT().
1203 If NewStack is 0, then ASSERT().
1205 @param Cs The 16-bit selector to load in the CS before EntryPoint
1206 is called. The descriptor in the GDT that this selector
1207 references must be setup for long mode.
1208 @param EntryPoint The 64-bit virtual address of the function to call with
1209 the new stack after paging is enabled.
1210 @param Context1 The 64-bit virtual address of the context to pass into
1211 the EntryPoint function as the first parameter after
1213 @param Context2 The 64-bit virtual address of the context to pass into
1214 the EntryPoint function as the second parameter after
1216 @param NewStack The 64-bit virtual address of the new stack to use for
1217 the EntryPoint function after paging is enabled.
1222 UnitTestHostBaseLibAsmEnablePaging64 (
1224 IN UINT64 EntryPoint
,
1225 IN UINT64 Context1 OPTIONAL
,
1226 IN UINT64 Context2 OPTIONAL
,
1230 SWITCH_STACK_ENTRY_POINT NewEntryPoint
;
1232 NewEntryPoint
= (SWITCH_STACK_ENTRY_POINT
)(UINTN
)(EntryPoint
);
1233 NewEntryPoint ((VOID
*)(UINTN
)Context1
, (VOID
*)(UINTN
)Context2
);
1237 Disables the 64-bit paging mode on the CPU.
1239 Disables the 64-bit paging mode on the CPU and returns to 32-bit protected
1240 mode. This function assumes the current execution mode is 64-paging mode.
1241 This function is only available on x64. After the 64-bit paging mode is
1242 disabled, control is transferred to the function specified by EntryPoint
1243 using the new stack specified by NewStack and passing in the parameters
1244 specified by Context1 and Context2. Context1 and Context2 are optional and
1245 may be 0. The function EntryPoint must never return.
1247 If the current execution mode is not 64-bit paged mode, then ASSERT().
1248 If EntryPoint is 0, then ASSERT().
1249 If NewStack is 0, then ASSERT().
1251 @param Cs The 16-bit selector to load in the CS before EntryPoint
1252 is called. The descriptor in the GDT that this selector
1253 references must be setup for 32-bit protected mode.
1254 @param EntryPoint The 64-bit virtual address of the function to call with
1255 the new stack after paging is disabled.
1256 @param Context1 The 64-bit virtual address of the context to pass into
1257 the EntryPoint function as the first parameter after
1259 @param Context2 The 64-bit virtual address of the context to pass into
1260 the EntryPoint function as the second parameter after
1262 @param NewStack The 64-bit virtual address of the new stack to use for
1263 the EntryPoint function after paging is disabled.
1268 UnitTestHostBaseLibAsmDisablePaging64 (
1270 IN UINT32 EntryPoint
,
1271 IN UINT32 Context1 OPTIONAL
,
1272 IN UINT32 Context2 OPTIONAL
,
1276 SWITCH_STACK_ENTRY_POINT NewEntryPoint
;
1278 NewEntryPoint
= (SWITCH_STACK_ENTRY_POINT
)(UINTN
)(EntryPoint
);
1279 NewEntryPoint ((VOID
*)(UINTN
)Context1
, (VOID
*)(UINTN
)Context2
);
1283 Retrieves the properties for 16-bit thunk functions.
1285 Computes the size of the buffer and stack below 1MB required to use the
1286 AsmPrepareThunk16(), AsmThunk16() and AsmPrepareAndThunk16() functions. This
1287 buffer size is returned in RealModeBufferSize, and the stack size is returned
1288 in ExtraStackSize. If parameters are passed to the 16-bit real mode code,
1289 then the actual minimum stack size is ExtraStackSize plus the maximum number
1290 of bytes that need to be passed to the 16-bit real mode code.
1292 If RealModeBufferSize is NULL, then ASSERT().
1293 If ExtraStackSize is NULL, then ASSERT().
1295 @param RealModeBufferSize A pointer to the size of the buffer below 1MB
1296 required to use the 16-bit thunk functions.
1297 @param ExtraStackSize A pointer to the extra size of stack below 1MB
1298 that the 16-bit thunk functions require for
1299 temporary storage in the transition to and from
1305 UnitTestHostBaseLibAsmGetThunk16Properties (
1306 OUT UINT32
*RealModeBufferSize
,
1307 OUT UINT32
*ExtraStackSize
1310 *RealModeBufferSize
= 0;
1311 *ExtraStackSize
= 0;
1315 Prepares all structures a code required to use AsmThunk16().
1317 Prepares all structures and code required to use AsmThunk16().
1319 This interface is limited to be used in either physical mode or virtual modes with paging enabled where the
1320 virtual to physical mappings for ThunkContext.RealModeBuffer is mapped 1:1.
1322 If ThunkContext is NULL, then ASSERT().
1324 @param ThunkContext A pointer to the context structure that describes the
1325 16-bit real mode code to call.
1330 UnitTestHostBaseLibAsmPrepareThunk16 (
1331 IN OUT THUNK_CONTEXT
*ThunkContext
1337 Transfers control to a 16-bit real mode entry point and returns the results.
1339 Transfers control to a 16-bit real mode entry point and returns the results.
1340 AsmPrepareThunk16() must be called with ThunkContext before this function is used.
1341 This function must be called with interrupts disabled.
1343 The register state from the RealModeState field of ThunkContext is restored just prior
1344 to calling the 16-bit real mode entry point. This includes the EFLAGS field of RealModeState,
1345 which is used to set the interrupt state when a 16-bit real mode entry point is called.
1346 Control is transferred to the 16-bit real mode entry point specified by the CS and Eip fields of RealModeState.
1347 The stack is initialized to the SS and ESP fields of RealModeState. Any parameters passed to
1348 the 16-bit real mode code must be populated by the caller at SS:ESP prior to calling this function.
1349 The 16-bit real mode entry point is invoked with a 16-bit CALL FAR instruction,
1350 so when accessing stack contents, the 16-bit real mode code must account for the 16-bit segment
1351 and 16-bit offset of the return address that were pushed onto the stack. The 16-bit real mode entry
1352 point must exit with a RETF instruction. The register state is captured into RealModeState immediately
1353 after the RETF instruction is executed.
1355 If EFLAGS specifies interrupts enabled, or any of the 16-bit real mode code enables interrupts,
1356 or any of the 16-bit real mode code makes a SW interrupt, then the caller is responsible for making sure
1357 the IDT at address 0 is initialized to handle any HW or SW interrupts that may occur while in 16-bit real mode.
1359 If EFLAGS specifies interrupts enabled, or any of the 16-bit real mode code enables interrupts,
1360 then the caller is responsible for making sure the 8259 PIC is in a state compatible with 16-bit real mode.
1361 This includes the base vectors, the interrupt masks, and the edge/level trigger mode.
1363 If THUNK_ATTRIBUTE_BIG_REAL_MODE is set in the ThunkAttributes field of ThunkContext, then the user code
1364 is invoked in big real mode. Otherwise, the user code is invoked in 16-bit real mode with 64KB segment limits.
1366 If neither THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 nor THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL are set in
1367 ThunkAttributes, then it is assumed that the user code did not enable the A20 mask, and no attempt is made to
1368 disable the A20 mask.
1370 If THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 is set and THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL is clear in
1371 ThunkAttributes, then attempt to use the INT 15 service to disable the A20 mask. If this INT 15 call fails,
1372 then attempt to disable the A20 mask by directly accessing the 8042 keyboard controller I/O ports.
1374 If THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 is clear and THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL is set in
1375 ThunkAttributes, then attempt to disable the A20 mask by directly accessing the 8042 keyboard controller I/O ports.
1377 If ThunkContext is NULL, then ASSERT().
1378 If AsmPrepareThunk16() was not previously called with ThunkContext, then ASSERT().
1379 If both THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 and THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL are set in
1380 ThunkAttributes, then ASSERT().
1382 This interface is limited to be used in either physical mode or virtual modes with paging enabled where the
1383 virtual to physical mappings for ThunkContext.RealModeBuffer are mapped 1:1.
1385 @param ThunkContext A pointer to the context structure that describes the
1386 16-bit real mode code to call.
1391 UnitTestHostBaseLibAsmThunk16 (
1392 IN OUT THUNK_CONTEXT
*ThunkContext
1398 Prepares all structures and code for a 16-bit real mode thunk, transfers
1399 control to a 16-bit real mode entry point, and returns the results.
1401 Prepares all structures and code for a 16-bit real mode thunk, transfers
1402 control to a 16-bit real mode entry point, and returns the results. If the
1403 caller only need to perform a single 16-bit real mode thunk, then this
1404 service should be used. If the caller intends to make more than one 16-bit
1405 real mode thunk, then it is more efficient if AsmPrepareThunk16() is called
1406 once and AsmThunk16() can be called for each 16-bit real mode thunk.
1408 This interface is limited to be used in either physical mode or virtual modes with paging enabled where the
1409 virtual to physical mappings for ThunkContext.RealModeBuffer is mapped 1:1.
1411 See AsmPrepareThunk16() and AsmThunk16() for the detailed description and ASSERT() conditions.
1413 @param ThunkContext A pointer to the context structure that describes the
1414 16-bit real mode code to call.
1419 UnitTestHostBaseLibAsmPrepareAndThunk16 (
1420 IN OUT THUNK_CONTEXT
*ThunkContext
1426 Load given selector into TR register.
1428 @param[in] Selector Task segment selector
1432 UnitTestHostBaseLibAsmWriteTr (
1436 mUnitTestHostBaseLibSegment
[UNIT_TEST_HOST_BASE_LIB_SEGMENT_TR
] = Selector
;
1440 Performs a serializing operation on all load-from-memory instructions that
1441 were issued prior the AsmLfence function.
1443 Executes a LFENCE instruction. This function is only available on IA-32 and x64.
1448 UnitTestHostBaseLibAsmLfence (
1455 Patch the immediate operand of an IA32 or X64 instruction such that the byte,
1456 word, dword or qword operand is encoded at the end of the instruction's
1457 binary representation.
1459 This function should be used to update object code that was compiled with
1460 NASM from assembly source code. Example:
1464 mov eax, strict dword 0 ; the imm32 zero operand will be patched
1470 X86_ASSEMBLY_PATCH_LABEL gPatchCr3;
1471 PatchInstructionX86 (gPatchCr3, AsmReadCr3 (), 4);
1473 @param[out] InstructionEnd Pointer right past the instruction to patch. The
1474 immediate operand to patch is expected to
1475 comprise the trailing bytes of the instruction.
1476 If InstructionEnd is closer to address 0 than
1477 ValueSize permits, then ASSERT().
1479 @param[in] PatchValue The constant to write to the immediate operand.
1480 The caller is responsible for ensuring that
1481 PatchValue can be represented in the byte, word,
1482 dword or qword operand (as indicated through
1483 ValueSize); otherwise ASSERT().
1485 @param[in] ValueSize The size of the operand in bytes; must be 1, 2,
1486 4, or 8. ASSERT() otherwise.
1490 UnitTestHostBaseLibPatchInstructionX86 (
1491 OUT X86_ASSEMBLY_PATCH_LABEL
*InstructionEnd
,
1492 IN UINT64 PatchValue
,
1499 Retrieves CPUID information.
1501 Executes the CPUID instruction with EAX set to the value specified by Index.
1502 This function always returns Index.
1503 If Eax is not NULL, then the value of EAX after CPUID is returned in Eax.
1504 If Ebx is not NULL, then the value of EBX after CPUID is returned in Ebx.
1505 If Ecx is not NULL, then the value of ECX after CPUID is returned in Ecx.
1506 If Edx is not NULL, then the value of EDX after CPUID is returned in Edx.
1507 This function is only available on IA-32 and x64.
1509 @param Index The 32-bit value to load into EAX prior to invoking the CPUID
1511 @param Eax The pointer to the 32-bit EAX value returned by the CPUID
1512 instruction. This is an optional parameter that may be NULL.
1513 @param Ebx The pointer to the 32-bit EBX value returned by the CPUID
1514 instruction. This is an optional parameter that may be NULL.
1515 @param Ecx The pointer to the 32-bit ECX value returned by the CPUID
1516 instruction. This is an optional parameter that may be NULL.
1517 @param Edx The pointer to the 32-bit EDX value returned by the CPUID
1518 instruction. This is an optional parameter that may be NULL.
1527 OUT UINT32
*Eax OPTIONAL
,
1528 OUT UINT32
*Ebx OPTIONAL
,
1529 OUT UINT32
*Ecx OPTIONAL
,
1530 OUT UINT32
*Edx OPTIONAL
1533 return gUnitTestHostBaseLib
.X86
->AsmCpuid (Index
, Eax
, Ebx
, Ecx
, Edx
);
1537 Retrieves CPUID information using an extended leaf identifier.
1539 Executes the CPUID instruction with EAX set to the value specified by Index
1540 and ECX set to the value specified by SubIndex. This function always returns
1541 Index. This function is only available on IA-32 and x64.
1543 If Eax is not NULL, then the value of EAX after CPUID is returned in Eax.
1544 If Ebx is not NULL, then the value of EBX after CPUID is returned in Ebx.
1545 If Ecx is not NULL, then the value of ECX after CPUID is returned in Ecx.
1546 If Edx is not NULL, then the value of EDX after CPUID is returned in Edx.
1548 @param Index The 32-bit value to load into EAX prior to invoking the
1550 @param SubIndex The 32-bit value to load into ECX prior to invoking the
1552 @param Eax The pointer to the 32-bit EAX value returned by the CPUID
1553 instruction. This is an optional parameter that may be
1555 @param Ebx The pointer to the 32-bit EBX value returned by the CPUID
1556 instruction. This is an optional parameter that may be
1558 @param Ecx The pointer to the 32-bit ECX value returned by the CPUID
1559 instruction. This is an optional parameter that may be
1561 @param Edx The pointer to the 32-bit EDX value returned by the CPUID
1562 instruction. This is an optional parameter that may be
1573 OUT UINT32
*Eax OPTIONAL
,
1574 OUT UINT32
*Ebx OPTIONAL
,
1575 OUT UINT32
*Ecx OPTIONAL
,
1576 OUT UINT32
*Edx OPTIONAL
1579 return gUnitTestHostBaseLib
.X86
->AsmCpuidEx (Index
, SubIndex
, Eax
, Ebx
, Ecx
, Edx
);
1583 Set CD bit and clear NW bit of CR0 followed by a WBINVD.
1585 Disables the caches by setting the CD bit of CR0 to 1, clearing the NW bit of CR0 to 0,
1586 and executing a WBINVD instruction. This function is only available on IA-32 and x64.
1595 gUnitTestHostBaseLib
.X86
->AsmDisableCache ();
1599 Perform a WBINVD and clear both the CD and NW bits of CR0.
1601 Enables the caches by executing a WBINVD instruction and then clear both the CD and NW
1602 bits of CR0 to 0. This function is only available on IA-32 and x64.
1611 gUnitTestHostBaseLib
.X86
->AsmEnableCache ();
1615 Returns a 64-bit Machine Specific Register(MSR).
1617 Reads and returns the 64-bit MSR specified by Index. No parameter checking is
1618 performed on Index, and some Index values may cause CPU exceptions. The
1619 caller must either guarantee that Index is valid, or the caller must set up
1620 exception handlers to catch the exceptions. This function is only available
1623 @param Index The 32-bit MSR index to read.
1625 @return The value of the MSR identified by Index.
1634 return gUnitTestHostBaseLib
.X86
->AsmReadMsr64 (Index
);
1638 Writes a 64-bit value to a Machine Specific Register(MSR), and returns the
1641 Writes the 64-bit value specified by Value to the MSR specified by Index. The
1642 64-bit value written to the MSR is returned. No parameter checking is
1643 performed on Index or Value, and some of these may cause CPU exceptions. The
1644 caller must either guarantee that Index and Value are valid, or the caller
1645 must establish proper exception handlers. This function is only available on
1648 @param Index The 32-bit MSR index to write.
1649 @param Value The 64-bit value to write to the MSR.
1661 return gUnitTestHostBaseLib
.X86
->AsmWriteMsr64 (Index
, Value
);
1665 Reads the current value of the Control Register 0 (CR0).
1667 Reads and returns the current value of CR0. This function is only available
1668 on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
1671 @return The value of the Control Register 0 (CR0).
1680 return gUnitTestHostBaseLib
.X86
->AsmReadCr0 ();
1684 Reads the current value of the Control Register 2 (CR2).
1686 Reads and returns the current value of CR2. This function is only available
1687 on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
1690 @return The value of the Control Register 2 (CR2).
1699 return gUnitTestHostBaseLib
.X86
->AsmReadCr2 ();
1703 Reads the current value of the Control Register 3 (CR3).
1705 Reads and returns the current value of CR3. This function is only available
1706 on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
1709 @return The value of the Control Register 3 (CR3).
1718 return gUnitTestHostBaseLib
.X86
->AsmReadCr3 ();
1722 Reads the current value of the Control Register 4 (CR4).
1724 Reads and returns the current value of CR4. This function is only available
1725 on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
1728 @return The value of the Control Register 4 (CR4).
1737 return gUnitTestHostBaseLib
.X86
->AsmReadCr4 ();
1741 Writes a value to Control Register 0 (CR0).
1743 Writes and returns a new value to CR0. This function is only available on
1744 IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
1746 @param Cr0 The value to write to CR0.
1748 @return The value written to CR0.
1757 return gUnitTestHostBaseLib
.X86
->AsmWriteCr0 (Cr0
);
1761 Writes a value to Control Register 2 (CR2).
1763 Writes and returns a new value to CR2. This function is only available on
1764 IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
1766 @param Cr2 The value to write to CR2.
1768 @return The value written to CR2.
1777 return gUnitTestHostBaseLib
.X86
->AsmWriteCr2 (Cr2
);
1781 Writes a value to Control Register 3 (CR3).
1783 Writes and returns a new value to CR3. This function is only available on
1784 IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
1786 @param Cr3 The value to write to CR3.
1788 @return The value written to CR3.
1797 return gUnitTestHostBaseLib
.X86
->AsmWriteCr3 (Cr3
);
1801 Writes a value to Control Register 4 (CR4).
1803 Writes and returns a new value to CR4. This function is only available on
1804 IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
1806 @param Cr4 The value to write to CR4.
1808 @return The value written to CR4.
1817 return gUnitTestHostBaseLib
.X86
->AsmWriteCr4 (Cr4
);
1821 Reads the current value of Debug Register 0 (DR0).
1823 Reads and returns the current value of DR0. This function is only available
1824 on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
1827 @return The value of Debug Register 0 (DR0).
1836 return gUnitTestHostBaseLib
.X86
->AsmReadDr0 ();
1840 Reads the current value of Debug Register 1 (DR1).
1842 Reads and returns the current value of DR1. This function is only available
1843 on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
1846 @return The value of Debug Register 1 (DR1).
1855 return gUnitTestHostBaseLib
.X86
->AsmReadDr1 ();
1859 Reads the current value of Debug Register 2 (DR2).
1861 Reads and returns the current value of DR2. This function is only available
1862 on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
1865 @return The value of Debug Register 2 (DR2).
1874 return gUnitTestHostBaseLib
.X86
->AsmReadDr2 ();
1878 Reads the current value of Debug Register 3 (DR3).
1880 Reads and returns the current value of DR3. This function is only available
1881 on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
1884 @return The value of Debug Register 3 (DR3).
1893 return gUnitTestHostBaseLib
.X86
->AsmReadDr3 ();
1897 Reads the current value of Debug Register 4 (DR4).
1899 Reads and returns the current value of DR4. This function is only available
1900 on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
1903 @return The value of Debug Register 4 (DR4).
1912 return gUnitTestHostBaseLib
.X86
->AsmReadDr4 ();
1916 Reads the current value of Debug Register 5 (DR5).
1918 Reads and returns the current value of DR5. This function is only available
1919 on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
1922 @return The value of Debug Register 5 (DR5).
1931 return gUnitTestHostBaseLib
.X86
->AsmReadDr5 ();
1935 Reads the current value of Debug Register 6 (DR6).
1937 Reads and returns the current value of DR6. This function is only available
1938 on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
1941 @return The value of Debug Register 6 (DR6).
1950 return gUnitTestHostBaseLib
.X86
->AsmReadDr6 ();
1954 Reads the current value of Debug Register 7 (DR7).
1956 Reads and returns the current value of DR7. This function is only available
1957 on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on
1960 @return The value of Debug Register 7 (DR7).
1969 return gUnitTestHostBaseLib
.X86
->AsmReadDr7 ();
1973 Writes a value to Debug Register 0 (DR0).
1975 Writes and returns a new value to DR0. This function is only available on
1976 IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
1978 @param Dr0 The value to write to Dr0.
1980 @return The value written to Debug Register 0 (DR0).
1989 return gUnitTestHostBaseLib
.X86
->AsmWriteDr0 (Dr0
);
1993 Writes a value to Debug Register 1 (DR1).
1995 Writes and returns a new value to DR1. This function is only available on
1996 IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
1998 @param Dr1 The value to write to Dr1.
2000 @return The value written to Debug Register 1 (DR1).
2009 return gUnitTestHostBaseLib
.X86
->AsmWriteDr1 (Dr1
);
2013 Writes a value to Debug Register 2 (DR2).
2015 Writes and returns a new value to DR2. This function is only available on
2016 IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
2018 @param Dr2 The value to write to Dr2.
2020 @return The value written to Debug Register 2 (DR2).
2029 return gUnitTestHostBaseLib
.X86
->AsmWriteDr2 (Dr2
);
2033 Writes a value to Debug Register 3 (DR3).
2035 Writes and returns a new value to DR3. This function is only available on
2036 IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
2038 @param Dr3 The value to write to Dr3.
2040 @return The value written to Debug Register 3 (DR3).
2049 return gUnitTestHostBaseLib
.X86
->AsmWriteDr3 (Dr3
);
2053 Writes a value to Debug Register 4 (DR4).
2055 Writes and returns a new value to DR4. This function is only available on
2056 IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
2058 @param Dr4 The value to write to Dr4.
2060 @return The value written to Debug Register 4 (DR4).
2069 return gUnitTestHostBaseLib
.X86
->AsmWriteDr4 (Dr4
);
2073 Writes a value to Debug Register 5 (DR5).
2075 Writes and returns a new value to DR5. This function is only available on
2076 IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
2078 @param Dr5 The value to write to Dr5.
2080 @return The value written to Debug Register 5 (DR5).
2089 return gUnitTestHostBaseLib
.X86
->AsmWriteDr5 (Dr5
);
2093 Writes a value to Debug Register 6 (DR6).
2095 Writes and returns a new value to DR6. This function is only available on
2096 IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
2098 @param Dr6 The value to write to Dr6.
2100 @return The value written to Debug Register 6 (DR6).
2109 return gUnitTestHostBaseLib
.X86
->AsmWriteDr6 (Dr6
);
2113 Writes a value to Debug Register 7 (DR7).
2115 Writes and returns a new value to DR7. This function is only available on
2116 IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.
2118 @param Dr7 The value to write to Dr7.
2120 @return The value written to Debug Register 7 (DR7).
2129 return gUnitTestHostBaseLib
.X86
->AsmWriteDr7 (Dr7
);
2133 Reads the current value of Code Segment Register (CS).
2135 Reads and returns the current value of CS. This function is only available on
2138 @return The current value of CS.
2147 return gUnitTestHostBaseLib
.X86
->AsmReadCs ();
2151 Reads the current value of Data Segment Register (DS).
2153 Reads and returns the current value of DS. This function is only available on
2156 @return The current value of DS.
2165 return gUnitTestHostBaseLib
.X86
->AsmReadDs ();
2169 Reads the current value of Extra Segment Register (ES).
2171 Reads and returns the current value of ES. This function is only available on
2174 @return The current value of ES.
2183 return gUnitTestHostBaseLib
.X86
->AsmReadEs ();
2187 Reads the current value of FS Data Segment Register (FS).
2189 Reads and returns the current value of FS. This function is only available on
2192 @return The current value of FS.
2201 return gUnitTestHostBaseLib
.X86
->AsmReadFs ();
2205 Reads the current value of GS Data Segment Register (GS).
2207 Reads and returns the current value of GS. This function is only available on
2210 @return The current value of GS.
2219 return gUnitTestHostBaseLib
.X86
->AsmReadGs ();
2223 Reads the current value of Stack Segment Register (SS).
2225 Reads and returns the current value of SS. This function is only available on
2228 @return The current value of SS.
2237 return gUnitTestHostBaseLib
.X86
->AsmReadSs ();
2241 Reads the current value of Task Register (TR).
2243 Reads and returns the current value of TR. This function is only available on
2246 @return The current value of TR.
2255 return gUnitTestHostBaseLib
.X86
->AsmReadTr ();
2259 Reads the current Global Descriptor Table Register(GDTR) descriptor.
2261 Reads and returns the current GDTR descriptor and returns it in Gdtr. This
2262 function is only available on IA-32 and x64.
2264 If Gdtr is NULL, then ASSERT().
2266 @param Gdtr The pointer to a GDTR descriptor.
2272 OUT IA32_DESCRIPTOR
*Gdtr
2275 gUnitTestHostBaseLib
.X86
->AsmReadGdtr (Gdtr
);
2279 Writes the current Global Descriptor Table Register (GDTR) descriptor.
2281 Writes and the current GDTR descriptor specified by Gdtr. This function is
2282 only available on IA-32 and x64.
2284 If Gdtr is NULL, then ASSERT().
2286 @param Gdtr The pointer to a GDTR descriptor.
2292 IN CONST IA32_DESCRIPTOR
*Gdtr
2295 gUnitTestHostBaseLib
.X86
->AsmWriteGdtr (Gdtr
);
2299 Reads the current Interrupt Descriptor Table Register(IDTR) descriptor.
2301 Reads and returns the current IDTR descriptor and returns it in Idtr. This
2302 function is only available on IA-32 and x64.
2304 If Idtr is NULL, then ASSERT().
2306 @param Idtr The pointer to a IDTR descriptor.
2312 OUT IA32_DESCRIPTOR
*Idtr
2315 gUnitTestHostBaseLib
.X86
->AsmReadIdtr (Idtr
);
2319 Writes the current Interrupt Descriptor Table Register(IDTR) descriptor.
2321 Writes the current IDTR descriptor and returns it in Idtr. This function is
2322 only available on IA-32 and x64.
2324 If Idtr is NULL, then ASSERT().
2326 @param Idtr The pointer to a IDTR descriptor.
2332 IN CONST IA32_DESCRIPTOR
*Idtr
2335 gUnitTestHostBaseLib
.X86
->AsmWriteIdtr (Idtr
);
2339 Reads the current Local Descriptor Table Register(LDTR) selector.
2341 Reads and returns the current 16-bit LDTR descriptor value. This function is
2342 only available on IA-32 and x64.
2344 @return The current selector of LDT.
2353 return gUnitTestHostBaseLib
.X86
->AsmReadLdtr ();
2357 Writes the current Local Descriptor Table Register (LDTR) selector.
2359 Writes and the current LDTR descriptor specified by Ldtr. This function is
2360 only available on IA-32 and x64.
2362 @param Ldtr 16-bit LDTR selector value.
2371 gUnitTestHostBaseLib
.X86
->AsmWriteLdtr (Ldtr
);
2375 Reads the current value of a Performance Counter (PMC).
2377 Reads and returns the current value of performance counter specified by
2378 Index. This function is only available on IA-32 and x64.
2380 @param Index The 32-bit Performance Counter index to read.
2382 @return The value of the PMC specified by Index.
2391 return gUnitTestHostBaseLib
.X86
->AsmReadPmc (Index
);
2395 Sets up a monitor buffer that is used by AsmMwait().
2397 Executes a MONITOR instruction with the register state specified by Eax, Ecx
2398 and Edx. Returns Eax. This function is only available on IA-32 and x64.
2400 @param Eax The value to load into EAX or RAX before executing the MONITOR
2402 @param Ecx The value to load into ECX or RCX before executing the MONITOR
2404 @param Edx The value to load into EDX or RDX before executing the MONITOR
2418 return gUnitTestHostBaseLib
.X86
->AsmMonitor (Eax
, Ecx
, Edx
);
2422 Executes an MWAIT instruction.
2424 Executes an MWAIT instruction with the register state specified by Eax and
2425 Ecx. Returns Eax. This function is only available on IA-32 and x64.
2427 @param Eax The value to load into EAX or RAX before executing the MONITOR
2429 @param Ecx The value to load into ECX or RCX before executing the MONITOR
2442 return gUnitTestHostBaseLib
.X86
->AsmMwait (Eax
, Ecx
);
2446 Executes a WBINVD instruction.
2448 Executes a WBINVD instruction. This function is only available on IA-32 and
2458 gUnitTestHostBaseLib
.X86
->AsmWbinvd ();
2462 Executes a INVD instruction.
2464 Executes a INVD instruction. This function is only available on IA-32 and
2474 gUnitTestHostBaseLib
.X86
->AsmInvd ();
2478 Flushes a cache line from all the instruction and data caches within the
2479 coherency domain of the CPU.
2481 Flushed the cache line specified by LinearAddress, and returns LinearAddress.
2482 This function is only available on IA-32 and x64.
2484 @param LinearAddress The address of the cache line to flush. If the CPU is
2485 in a physical addressing mode, then LinearAddress is a
2486 physical address. If the CPU is in a virtual
2487 addressing mode, then LinearAddress is a virtual
2490 @return LinearAddress.
2495 IN VOID
*LinearAddress
2498 return gUnitTestHostBaseLib
.X86
->AsmFlushCacheLine (LinearAddress
);
2502 Enables the 32-bit paging mode on the CPU.
2504 Enables the 32-bit paging mode on the CPU. CR0, CR3, CR4, and the page tables
2505 must be properly initialized prior to calling this service. This function
2506 assumes the current execution mode is 32-bit protected mode. This function is
2507 only available on IA-32. After the 32-bit paging mode is enabled, control is
2508 transferred to the function specified by EntryPoint using the new stack
2509 specified by NewStack and passing in the parameters specified by Context1 and
2510 Context2. Context1 and Context2 are optional and may be NULL. The function
2511 EntryPoint must never return.
2513 If the current execution mode is not 32-bit protected mode, then ASSERT().
2514 If EntryPoint is NULL, then ASSERT().
2515 If NewStack is NULL, then ASSERT().
2517 There are a number of constraints that must be followed before calling this
2519 1) Interrupts must be disabled.
2520 2) The caller must be in 32-bit protected mode with flat descriptors. This
2521 means all descriptors must have a base of 0 and a limit of 4GB.
2522 3) CR0 and CR4 must be compatible with 32-bit protected mode with flat
2524 4) CR3 must point to valid page tables that will be used once the transition
2525 is complete, and those page tables must guarantee that the pages for this
2526 function and the stack are identity mapped.
2528 @param EntryPoint A pointer to function to call with the new stack after
2530 @param Context1 A pointer to the context to pass into the EntryPoint
2531 function as the first parameter after paging is enabled.
2532 @param Context2 A pointer to the context to pass into the EntryPoint
2533 function as the second parameter after paging is enabled.
2534 @param NewStack A pointer to the new stack to use for the EntryPoint
2535 function after paging is enabled.
2541 IN SWITCH_STACK_ENTRY_POINT EntryPoint
,
2542 IN VOID
*Context1 OPTIONAL
,
2543 IN VOID
*Context2 OPTIONAL
,
2547 gUnitTestHostBaseLib
.X86
->AsmEnablePaging32 (EntryPoint
, Context1
, Context2
, NewStack
);
2551 Disables the 32-bit paging mode on the CPU.
2553 Disables the 32-bit paging mode on the CPU and returns to 32-bit protected
2554 mode. This function assumes the current execution mode is 32-paged protected
2555 mode. This function is only available on IA-32. After the 32-bit paging mode
2556 is disabled, control is transferred to the function specified by EntryPoint
2557 using the new stack specified by NewStack and passing in the parameters
2558 specified by Context1 and Context2. Context1 and Context2 are optional and
2559 may be NULL. The function EntryPoint must never return.
2561 If the current execution mode is not 32-bit paged mode, then ASSERT().
2562 If EntryPoint is NULL, then ASSERT().
2563 If NewStack is NULL, then ASSERT().
2565 There are a number of constraints that must be followed before calling this
2567 1) Interrupts must be disabled.
2568 2) The caller must be in 32-bit paged mode.
2569 3) CR0, CR3, and CR4 must be compatible with 32-bit paged mode.
2570 4) CR3 must point to valid page tables that guarantee that the pages for
2571 this function and the stack are identity mapped.
2573 @param EntryPoint A pointer to function to call with the new stack after
2575 @param Context1 A pointer to the context to pass into the EntryPoint
2576 function as the first parameter after paging is disabled.
2577 @param Context2 A pointer to the context to pass into the EntryPoint
2578 function as the second parameter after paging is
2580 @param NewStack A pointer to the new stack to use for the EntryPoint
2581 function after paging is disabled.
2586 AsmDisablePaging32 (
2587 IN SWITCH_STACK_ENTRY_POINT EntryPoint
,
2588 IN VOID
*Context1 OPTIONAL
,
2589 IN VOID
*Context2 OPTIONAL
,
2593 gUnitTestHostBaseLib
.X86
->AsmDisablePaging32 (EntryPoint
, Context1
, Context2
, NewStack
);
2597 Enables the 64-bit paging mode on the CPU.
2599 Enables the 64-bit paging mode on the CPU. CR0, CR3, CR4, and the page tables
2600 must be properly initialized prior to calling this service. This function
2601 assumes the current execution mode is 32-bit protected mode with flat
2602 descriptors. This function is only available on IA-32. After the 64-bit
2603 paging mode is enabled, control is transferred to the function specified by
2604 EntryPoint using the new stack specified by NewStack and passing in the
2605 parameters specified by Context1 and Context2. Context1 and Context2 are
2606 optional and may be 0. The function EntryPoint must never return.
2608 If the current execution mode is not 32-bit protected mode with flat
2609 descriptors, then ASSERT().
2610 If EntryPoint is 0, then ASSERT().
2611 If NewStack is 0, then ASSERT().
2613 @param Cs The 16-bit selector to load in the CS before EntryPoint
2614 is called. The descriptor in the GDT that this selector
2615 references must be setup for long mode.
2616 @param EntryPoint The 64-bit virtual address of the function to call with
2617 the new stack after paging is enabled.
2618 @param Context1 The 64-bit virtual address of the context to pass into
2619 the EntryPoint function as the first parameter after
2621 @param Context2 The 64-bit virtual address of the context to pass into
2622 the EntryPoint function as the second parameter after
2624 @param NewStack The 64-bit virtual address of the new stack to use for
2625 the EntryPoint function after paging is enabled.
2632 IN UINT64 EntryPoint
,
2633 IN UINT64 Context1 OPTIONAL
,
2634 IN UINT64 Context2 OPTIONAL
,
2638 gUnitTestHostBaseLib
.X86
->AsmEnablePaging64 (Cs
, EntryPoint
, Context1
, Context2
, NewStack
);
2642 Disables the 64-bit paging mode on the CPU.
2644 Disables the 64-bit paging mode on the CPU and returns to 32-bit protected
2645 mode. This function assumes the current execution mode is 64-paging mode.
2646 This function is only available on x64. After the 64-bit paging mode is
2647 disabled, control is transferred to the function specified by EntryPoint
2648 using the new stack specified by NewStack and passing in the parameters
2649 specified by Context1 and Context2. Context1 and Context2 are optional and
2650 may be 0. The function EntryPoint must never return.
2652 If the current execution mode is not 64-bit paged mode, then ASSERT().
2653 If EntryPoint is 0, then ASSERT().
2654 If NewStack is 0, then ASSERT().
2656 @param Cs The 16-bit selector to load in the CS before EntryPoint
2657 is called. The descriptor in the GDT that this selector
2658 references must be setup for 32-bit protected mode.
2659 @param EntryPoint The 64-bit virtual address of the function to call with
2660 the new stack after paging is disabled.
2661 @param Context1 The 64-bit virtual address of the context to pass into
2662 the EntryPoint function as the first parameter after
2664 @param Context2 The 64-bit virtual address of the context to pass into
2665 the EntryPoint function as the second parameter after
2667 @param NewStack The 64-bit virtual address of the new stack to use for
2668 the EntryPoint function after paging is disabled.
2673 AsmDisablePaging64 (
2675 IN UINT32 EntryPoint
,
2676 IN UINT32 Context1 OPTIONAL
,
2677 IN UINT32 Context2 OPTIONAL
,
2681 gUnitTestHostBaseLib
.X86
->AsmDisablePaging64 (Cs
, EntryPoint
, Context1
, Context2
, NewStack
);
2685 Retrieves the properties for 16-bit thunk functions.
2687 Computes the size of the buffer and stack below 1MB required to use the
2688 AsmPrepareThunk16(), AsmThunk16() and AsmPrepareAndThunk16() functions. This
2689 buffer size is returned in RealModeBufferSize, and the stack size is returned
2690 in ExtraStackSize. If parameters are passed to the 16-bit real mode code,
2691 then the actual minimum stack size is ExtraStackSize plus the maximum number
2692 of bytes that need to be passed to the 16-bit real mode code.
2694 If RealModeBufferSize is NULL, then ASSERT().
2695 If ExtraStackSize is NULL, then ASSERT().
2697 @param RealModeBufferSize A pointer to the size of the buffer below 1MB
2698 required to use the 16-bit thunk functions.
2699 @param ExtraStackSize A pointer to the extra size of stack below 1MB
2700 that the 16-bit thunk functions require for
2701 temporary storage in the transition to and from
2707 AsmGetThunk16Properties (
2708 OUT UINT32
*RealModeBufferSize
,
2709 OUT UINT32
*ExtraStackSize
2712 gUnitTestHostBaseLib
.X86
->AsmGetThunk16Properties (RealModeBufferSize
, ExtraStackSize
);
2716 Prepares all structures a code required to use AsmThunk16().
2718 Prepares all structures and code required to use AsmThunk16().
2720 This interface is limited to be used in either physical mode or virtual modes with paging enabled where the
2721 virtual to physical mappings for ThunkContext.RealModeBuffer is mapped 1:1.
2723 If ThunkContext is NULL, then ASSERT().
2725 @param ThunkContext A pointer to the context structure that describes the
2726 16-bit real mode code to call.
2732 IN OUT THUNK_CONTEXT
*ThunkContext
2735 gUnitTestHostBaseLib
.X86
->AsmPrepareThunk16 (ThunkContext
);
2739 Transfers control to a 16-bit real mode entry point and returns the results.
2741 Transfers control to a 16-bit real mode entry point and returns the results.
2742 AsmPrepareThunk16() must be called with ThunkContext before this function is used.
2743 This function must be called with interrupts disabled.
2745 The register state from the RealModeState field of ThunkContext is restored just prior
2746 to calling the 16-bit real mode entry point. This includes the EFLAGS field of RealModeState,
2747 which is used to set the interrupt state when a 16-bit real mode entry point is called.
2748 Control is transferred to the 16-bit real mode entry point specified by the CS and Eip fields of RealModeState.
2749 The stack is initialized to the SS and ESP fields of RealModeState. Any parameters passed to
2750 the 16-bit real mode code must be populated by the caller at SS:ESP prior to calling this function.
2751 The 16-bit real mode entry point is invoked with a 16-bit CALL FAR instruction,
2752 so when accessing stack contents, the 16-bit real mode code must account for the 16-bit segment
2753 and 16-bit offset of the return address that were pushed onto the stack. The 16-bit real mode entry
2754 point must exit with a RETF instruction. The register state is captured into RealModeState immediately
2755 after the RETF instruction is executed.
2757 If EFLAGS specifies interrupts enabled, or any of the 16-bit real mode code enables interrupts,
2758 or any of the 16-bit real mode code makes a SW interrupt, then the caller is responsible for making sure
2759 the IDT at address 0 is initialized to handle any HW or SW interrupts that may occur while in 16-bit real mode.
2761 If EFLAGS specifies interrupts enabled, or any of the 16-bit real mode code enables interrupts,
2762 then the caller is responsible for making sure the 8259 PIC is in a state compatible with 16-bit real mode.
2763 This includes the base vectors, the interrupt masks, and the edge/level trigger mode.
2765 If THUNK_ATTRIBUTE_BIG_REAL_MODE is set in the ThunkAttributes field of ThunkContext, then the user code
2766 is invoked in big real mode. Otherwise, the user code is invoked in 16-bit real mode with 64KB segment limits.
2768 If neither THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 nor THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL are set in
2769 ThunkAttributes, then it is assumed that the user code did not enable the A20 mask, and no attempt is made to
2770 disable the A20 mask.
2772 If THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 is set and THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL is clear in
2773 ThunkAttributes, then attempt to use the INT 15 service to disable the A20 mask. If this INT 15 call fails,
2774 then attempt to disable the A20 mask by directly accessing the 8042 keyboard controller I/O ports.
2776 If THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 is clear and THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL is set in
2777 ThunkAttributes, then attempt to disable the A20 mask by directly accessing the 8042 keyboard controller I/O ports.
2779 If ThunkContext is NULL, then ASSERT().
2780 If AsmPrepareThunk16() was not previously called with ThunkContext, then ASSERT().
2781 If both THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 and THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL are set in
2782 ThunkAttributes, then ASSERT().
2784 This interface is limited to be used in either physical mode or virtual modes with paging enabled where the
2785 virtual to physical mappings for ThunkContext.RealModeBuffer are mapped 1:1.
2787 @param ThunkContext A pointer to the context structure that describes the
2788 16-bit real mode code to call.
2794 IN OUT THUNK_CONTEXT
*ThunkContext
2797 gUnitTestHostBaseLib
.X86
->AsmThunk16 (ThunkContext
);
2801 Prepares all structures and code for a 16-bit real mode thunk, transfers
2802 control to a 16-bit real mode entry point, and returns the results.
2804 Prepares all structures and code for a 16-bit real mode thunk, transfers
2805 control to a 16-bit real mode entry point, and returns the results. If the
2806 caller only need to perform a single 16-bit real mode thunk, then this
2807 service should be used. If the caller intends to make more than one 16-bit
2808 real mode thunk, then it is more efficient if AsmPrepareThunk16() is called
2809 once and AsmThunk16() can be called for each 16-bit real mode thunk.
2811 This interface is limited to be used in either physical mode or virtual modes with paging enabled where the
2812 virtual to physical mappings for ThunkContext.RealModeBuffer is mapped 1:1.
2814 See AsmPrepareThunk16() and AsmThunk16() for the detailed description and ASSERT() conditions.
2816 @param ThunkContext A pointer to the context structure that describes the
2817 16-bit real mode code to call.
2822 AsmPrepareAndThunk16 (
2823 IN OUT THUNK_CONTEXT
*ThunkContext
2826 gUnitTestHostBaseLib
.X86
->AsmPrepareAndThunk16 (ThunkContext
);
2830 Load given selector into TR register.
2832 @param[in] Selector Task segment selector
2840 gUnitTestHostBaseLib
.X86
->AsmWriteTr (Selector
);
2844 Performs a serializing operation on all load-from-memory instructions that
2845 were issued prior the AsmLfence function.
2847 Executes a LFENCE instruction. This function is only available on IA-32 and x64.
2856 gUnitTestHostBaseLib
.X86
->AsmLfence ();
2860 Patch the immediate operand of an IA32 or X64 instruction such that the byte,
2861 word, dword or qword operand is encoded at the end of the instruction's
2862 binary representation.
2864 This function should be used to update object code that was compiled with
2865 NASM from assembly source code. Example:
2869 mov eax, strict dword 0 ; the imm32 zero operand will be patched
2875 X86_ASSEMBLY_PATCH_LABEL gPatchCr3;
2876 PatchInstructionX86 (gPatchCr3, AsmReadCr3 (), 4);
2878 @param[out] InstructionEnd Pointer right past the instruction to patch. The
2879 immediate operand to patch is expected to
2880 comprise the trailing bytes of the instruction.
2881 If InstructionEnd is closer to address 0 than
2882 ValueSize permits, then ASSERT().
2884 @param[in] PatchValue The constant to write to the immediate operand.
2885 The caller is responsible for ensuring that
2886 PatchValue can be represented in the byte, word,
2887 dword or qword operand (as indicated through
2888 ValueSize); otherwise ASSERT().
2890 @param[in] ValueSize The size of the operand in bytes; must be 1, 2,
2891 4, or 8. ASSERT() otherwise.
2895 PatchInstructionX86 (
2896 OUT X86_ASSEMBLY_PATCH_LABEL
*InstructionEnd
,
2897 IN UINT64 PatchValue
,
2901 gUnitTestHostBaseLib
.X86
->PatchInstructionX86 (InstructionEnd
, PatchValue
, ValueSize
);
2907 STATIC UNIT_TEST_HOST_BASE_LIB_COMMON mUnitTestHostBaseLibCommon
= {
2908 UnitTestHostBaseLibEnableInterrupts
,
2909 UnitTestHostBaseLibDisableInterrupts
,
2910 UnitTestHostBaseLibEnableDisableInterrupts
,
2911 UnitTestHostBaseLibGetInterruptState
,
2915 /// IA32/X64 services
2917 STATIC UNIT_TEST_HOST_BASE_LIB_X86 mUnitTestHostBaseLibX86
= {
2918 UnitTestHostBaseLibAsmCpuid
,
2919 UnitTestHostBaseLibAsmCpuidEx
,
2920 UnitTestHostBaseLibAsmDisableCache
,
2921 UnitTestHostBaseLibAsmEnableCache
,
2922 UnitTestHostBaseLibAsmReadMsr64
,
2923 UnitTestHostBaseLibAsmWriteMsr64
,
2924 UnitTestHostBaseLibAsmReadCr0
,
2925 UnitTestHostBaseLibAsmReadCr2
,
2926 UnitTestHostBaseLibAsmReadCr3
,
2927 UnitTestHostBaseLibAsmReadCr4
,
2928 UnitTestHostBaseLibAsmWriteCr0
,
2929 UnitTestHostBaseLibAsmWriteCr2
,
2930 UnitTestHostBaseLibAsmWriteCr3
,
2931 UnitTestHostBaseLibAsmWriteCr4
,
2932 UnitTestHostBaseLibAsmReadDr0
,
2933 UnitTestHostBaseLibAsmReadDr1
,
2934 UnitTestHostBaseLibAsmReadDr2
,
2935 UnitTestHostBaseLibAsmReadDr3
,
2936 UnitTestHostBaseLibAsmReadDr4
,
2937 UnitTestHostBaseLibAsmReadDr5
,
2938 UnitTestHostBaseLibAsmReadDr6
,
2939 UnitTestHostBaseLibAsmReadDr7
,
2940 UnitTestHostBaseLibAsmWriteDr0
,
2941 UnitTestHostBaseLibAsmWriteDr1
,
2942 UnitTestHostBaseLibAsmWriteDr2
,
2943 UnitTestHostBaseLibAsmWriteDr3
,
2944 UnitTestHostBaseLibAsmWriteDr4
,
2945 UnitTestHostBaseLibAsmWriteDr5
,
2946 UnitTestHostBaseLibAsmWriteDr6
,
2947 UnitTestHostBaseLibAsmWriteDr7
,
2948 UnitTestHostBaseLibAsmReadCs
,
2949 UnitTestHostBaseLibAsmReadDs
,
2950 UnitTestHostBaseLibAsmReadEs
,
2951 UnitTestHostBaseLibAsmReadFs
,
2952 UnitTestHostBaseLibAsmReadGs
,
2953 UnitTestHostBaseLibAsmReadSs
,
2954 UnitTestHostBaseLibAsmReadTr
,
2955 UnitTestHostBaseLibAsmReadGdtr
,
2956 UnitTestHostBaseLibAsmWriteGdtr
,
2957 UnitTestHostBaseLibAsmReadIdtr
,
2958 UnitTestHostBaseLibAsmWriteIdtr
,
2959 UnitTestHostBaseLibAsmReadLdtr
,
2960 UnitTestHostBaseLibAsmWriteLdtr
,
2961 UnitTestHostBaseLibAsmReadPmc
,
2962 UnitTestHostBaseLibAsmMonitor
,
2963 UnitTestHostBaseLibAsmMwait
,
2964 UnitTestHostBaseLibAsmWbinvd
,
2965 UnitTestHostBaseLibAsmInvd
,
2966 UnitTestHostBaseLibAsmFlushCacheLine
,
2967 UnitTestHostBaseLibAsmEnablePaging32
,
2968 UnitTestHostBaseLibAsmDisablePaging32
,
2969 UnitTestHostBaseLibAsmEnablePaging64
,
2970 UnitTestHostBaseLibAsmDisablePaging64
,
2971 UnitTestHostBaseLibAsmGetThunk16Properties
,
2972 UnitTestHostBaseLibAsmPrepareThunk16
,
2973 UnitTestHostBaseLibAsmThunk16
,
2974 UnitTestHostBaseLibAsmPrepareAndThunk16
,
2975 UnitTestHostBaseLibAsmWriteTr
,
2976 UnitTestHostBaseLibAsmLfence
,
2977 UnitTestHostBaseLibPatchInstructionX86
2981 /// Structure of hook functions for BaseLib functions that can not be used from
2982 /// a host application. A simple emulation of these function is provided by
2983 /// default. A specific unit test can provide its own implementation for any
2984 /// of these functions.
2986 UNIT_TEST_HOST_BASE_LIB gUnitTestHostBaseLib
= {
2987 &mUnitTestHostBaseLibCommon
,
2988 &mUnitTestHostBaseLibX86