;------------------------------------------------------------------------------\r
;\r
-; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>\r
; SPDX-License-Identifier: BSD-2-Clause-Patent\r
;\r
; Module Name:\r
mov cr0, eax ; enable paging\r
retf ; topmost 2 dwords hold the address\r
.0:\r
- DB 0x67, 0x48 ; 32-bit address size, 64-bit operand size\r
- mov ebx, [esp] ; mov rbx, [esp]\r
- DB 0x67, 0x48\r
- mov ecx, [esp + 8] ; mov rcx, [esp + 8]\r
- DB 0x67, 0x48\r
- mov edx, [esp + 0x10] ; mov rdx, [esp + 10h]\r
- DB 0x67, 0x48\r
- mov esp, [esp + 0x18] ; mov rsp, [esp + 18h]\r
- DB 0x48\r
- add esp, -0x20 ; add rsp, -20h\r
- call ebx ; call rbx\r
+BITS 64\r
+ mov rbx, [esp]\r
+ mov rcx, [esp + 8]\r
+ mov rdx, [esp + 0x10]\r
+ mov rsp, [esp + 0x18]\r
+ add rsp, -0x20\r
+ call rbx\r
hlt ; no one should get here\r
\r
;------------------------------------------------------------------------------\r
;\r
-; Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>\r
; SPDX-License-Identifier: BSD-2-Clause-Patent\r
;\r
; Module Name:\r
\r
mov edx, [esp + 4] ; edx = JumpBuffer\r
mov edx, [edx + 24] ; edx = target SSP\r
- READSSP_EAX\r
+ rdsspd eax\r
sub edx, eax ; edx = delta\r
mov eax, edx ; eax = delta\r
\r
shr eax, 2 ; eax = delta/sizeof(UINT32)\r
- INCSSP_EAX\r
+ incsspd eax\r
\r
CetDone:\r
\r
;------------------------------------------------------------------------------\r
;\r
-; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>\r
; SPDX-License-Identifier: BSD-2-Clause-Patent\r
;\r
; Module Name:\r
mov eax, [esp + 4]\r
mov ecx, [esp + 8]\r
mov edx, [esp + 12]\r
- DB 0xf, 1, 0xc8 ; monitor\r
+ monitor\r
ret\r
\r
;------------------------------------------------------------------------------\r
;\r
-; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>\r
; SPDX-License-Identifier: BSD-2-Clause-Patent\r
;\r
; Module Name:\r
ASM_PFX(AsmMwait):\r
mov eax, [esp + 4]\r
mov ecx, [esp + 8]\r
- DB 0xf, 1, 0xc9 ; mwait\r
+ mwait\r
ret\r
\r
;------------------------------------------------------------------------------\r
;\r
-; Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2015 - 2022, Intel Corporation. All rights reserved.<BR>\r
; SPDX-License-Identifier: BSD-2-Clause-Patent\r
;\r
; Module Name:\r
;------------------------------------------------------------------------------\r
global ASM_PFX(InternalX86RdRand16)\r
ASM_PFX(InternalX86RdRand16):\r
- ; rdrand ax ; generate a 16 bit RN into ax\r
+ rdrand eax ; generate a 16 bit RN into ax\r
; CF=1 if RN generated ok, otherwise CF=0\r
- db 0xf, 0xc7, 0xf0 ; rdrand r16: "0f c7 /6 ModRM:r/m(w)"\r
jc rn16_ok ; jmp if CF=1\r
xor eax, eax ; reg=0 if CF=0\r
ret ; return with failure status\r
;------------------------------------------------------------------------------\r
global ASM_PFX(InternalX86RdRand32)\r
ASM_PFX(InternalX86RdRand32):\r
- ; rdrand eax ; generate a 32 bit RN into eax\r
+ rdrand eax ; generate a 32 bit RN into eax\r
; CF=1 if RN generated ok, otherwise CF=0\r
- db 0xf, 0xc7, 0xf0 ; rdrand r32: "0f c7 /6 ModRM:r/m(w)"\r
jc rn32_ok ; jmp if CF=1\r
xor eax, eax ; reg=0 if CF=0\r
ret ; return with failure status\r
;------------------------------------------------------------------------------\r
global ASM_PFX(InternalX86RdRand64)\r
ASM_PFX(InternalX86RdRand64):\r
- ; rdrand eax ; generate a 32 bit RN into eax\r
+ rdrand eax ; generate a 32 bit RN into eax\r
; CF=1 if RN generated ok, otherwise CF=0\r
- db 0xf, 0xc7, 0xf0 ; rdrand r32: "0f c7 /6 ModRM:r/m(w)"\r
jnc rn64_ret ; jmp if CF=0\r
mov edx, dword [esp + 4]\r
mov [edx], eax\r
\r
- db 0xf, 0xc7, 0xf0 ; generate another 32 bit RN\r
+ rdrand eax ; generate another 32 bit RN\r
jnc rn64_ret ; jmp if CF=0\r
mov [edx + 4], eax\r
\r
;------------------------------------------------------------------------------\r
;\r
-; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>\r
; SPDX-License-Identifier: BSD-2-Clause-Patent\r
;\r
; Module Name:\r
; this register will cause a #UD exception.\r
;\r
; MS assembler doesn't support this instruction since no one would use it\r
- ; under normal circustances. Here opcode is used.\r
+ ; under normal circustances.\r
;\r
- DB 0xf, 0x21, 0xe0\r
+ mov eax, dr4\r
ret\r
\r
;------------------------------------------------------------------------------\r
;\r
-; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>\r
; SPDX-License-Identifier: BSD-2-Clause-Patent\r
;\r
; Module Name:\r
; this register will cause a #UD exception.\r
;\r
; MS assembler doesn't support this instruction since no one would use it\r
- ; under normal circustances. Here opcode is used.\r
+ ; under normal circustances.\r
;\r
- DB 0xf, 0x21, 0xe8\r
+ mov eax, dr5\r
ret\r
\r
;------------------------------------------------------------------------------\r
;\r
-; Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>\r
; SPDX-License-Identifier: BSD-2-Clause-Patent\r
;\r
; Module Name:\r
jnc CetDone\r
\r
mov eax, 1\r
- INCSSP_EAX ; to read original SSP\r
- READSSP_EAX\r
+ incsspd eax ; to read original SSP\r
+ rdsspd eax\r
mov [edx + 0x24], eax ; save SSP\r
\r
CetDone:\r
;------------------------------------------------------------------------------\r
;\r
-; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>\r
; SPDX-License-Identifier: BSD-2-Clause-Patent\r
;\r
; Module Name:\r
; this register will cause a #UD exception.\r
;\r
; MS assembler doesn't support this instruction since no one would use it\r
- ; under normal circustances. Here opcode is used.\r
+ ; under normal circustances.\r
;\r
- DB 0xf, 0x23, 0xe0\r
+ mov dr4, eax\r
ret\r
\r
;------------------------------------------------------------------------------\r
;\r
-; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>\r
; SPDX-License-Identifier: BSD-2-Clause-Patent\r
;\r
; Module Name:\r
; this register will cause a #UD exception.\r
;\r
; MS assembler doesn't support this instruction since no one would use it\r
- ; under normal circustances. Here opcode is used.\r
+ ; under normal circustances.\r
;\r
- DB 0xf, 0x23, 0xe8\r
+ mov dr5, eax\r
ret\r
\r
;------------------------------------------------------------------------------\r
;\r
-; Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>\r
; SPDX-License-Identifier: BSD-2-Clause-Patent\r
;\r
; Module Name:\r
sub eax, 4 ; eax <- One slot below transition code on the stack\r
push rcx ; push Cs to stack\r
push r10 ; push address of tansition code on stack\r
- DB 0x48 ; prefix to composite "retq" with next "retf"\r
- retf ; Use far return to load CS register from stack\r
+ retfq\r
\r
; Start of transition code\r
.0:\r
;------------------------------------------------------------------------------\r
;\r
-; Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>\r
; SPDX-License-Identifier: BSD-2-Clause-Patent\r
;\r
; Module Name:\r
push rdx ; save rdx\r
\r
mov rdx, [rcx + 0xF8] ; rdx = target SSP\r
- READSSP_RAX\r
+ rdsspq rax\r
sub rdx, rax ; rdx = delta\r
mov rax, rdx ; rax = delta\r
\r
shr rax, 3 ; rax = delta/sizeof(UINT64)\r
- INCSSP_RAX\r
+ incsspq rax\r
\r
pop rdx ; restore rdx\r
CetDone:\r
;------------------------------------------------------------------------------\r
;\r
-; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>\r
; SPDX-License-Identifier: BSD-2-Clause-Patent\r
;\r
; Module Name:\r
mov eax, ecx\r
mov ecx, edx\r
mov edx, r8d\r
- DB 0xf, 1, 0xc8 ; monitor\r
+ monitor\r
ret\r
\r
;------------------------------------------------------------------------------\r
;\r
-; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>\r
; SPDX-License-Identifier: BSD-2-Clause-Patent\r
;\r
; Module Name:\r
ASM_PFX(AsmMwait):\r
mov eax, ecx\r
mov ecx, edx\r
- DB 0xf, 1, 0xc9 ; mwait\r
+ mwait\r
ret\r
\r
;------------------------------------------------------------------------------\r
;\r
-; Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2015 - 2022, Intel Corporation. All rights reserved.<BR>\r
; SPDX-License-Identifier: BSD-2-Clause-Patent\r
;\r
; Module Name:\r
;------------------------------------------------------------------------------\r
global ASM_PFX(InternalX86RdRand16)\r
ASM_PFX(InternalX86RdRand16):\r
- ; rdrand ax ; generate a 16 bit RN into eax,\r
+ rdrand eax ; generate a 16 bit RN into eax,\r
; CF=1 if RN generated ok, otherwise CF=0\r
- db 0xf, 0xc7, 0xf0 ; rdrand r16: "0f c7 /6 ModRM:r/m(w)"\r
jc rn16_ok ; jmp if CF=1\r
xor rax, rax ; reg=0 if CF=0\r
ret ; return with failure status\r
;------------------------------------------------------------------------------\r
global ASM_PFX(InternalX86RdRand32)\r
ASM_PFX(InternalX86RdRand32):\r
- ; rdrand eax ; generate a 32 bit RN into eax,\r
+ rdrand eax ; generate a 32 bit RN into eax,\r
; CF=1 if RN generated ok, otherwise CF=0\r
- db 0xf, 0xc7, 0xf0 ; rdrand r32: "0f c7 /6 ModRM:r/m(w)"\r
jc rn32_ok ; jmp if CF=1\r
xor rax, rax ; reg=0 if CF=0\r
ret ; return with failure status\r
;------------------------------------------------------------------------------\r
global ASM_PFX(InternalX86RdRand64)\r
ASM_PFX(InternalX86RdRand64):\r
- ; rdrand rax ; generate a 64 bit RN into rax,\r
+ rdrand rax ; generate a 64 bit RN into rax,\r
; CF=1 if RN generated ok, otherwise CF=0\r
- db 0x48, 0xf, 0xc7, 0xf0 ; rdrand r64: "REX.W + 0f c7 /6 ModRM:r/m(w)"\r
jc rn64_ok ; jmp if CF=1\r
xor rax, rax ; reg=0 if CF=0\r
ret ; return with failure status\r
;------------------------------------------------------------------------------\r
;\r
-; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>\r
; SPDX-License-Identifier: BSD-2-Clause-Patent\r
;\r
; Module Name:\r
; There's no obvious reason to access this register, since it's aliased to\r
; DR7 when DE=0 or an exception generated when DE=1\r
;\r
- DB 0xf, 0x21, 0xe0\r
+ mov rax, dr4\r
ret\r
\r
;------------------------------------------------------------------------------\r
;\r
-; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>\r
; SPDX-License-Identifier: BSD-2-Clause-Patent\r
;\r
; Module Name:\r
; There's no obvious reason to access this register, since it's aliased to\r
; DR7 when DE=0 or an exception generated when DE=1\r
;\r
- DB 0xf, 0x21, 0xe8\r
+ mov rax, dr5\r
ret\r
\r
;------------------------------------------------------------------------------\r
;\r
-; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>\r
; SPDX-License-Identifier: BSD-2-Clause-Patent\r
;\r
; Module Name:\r
;------------------------------------------------------------------------------\r
global ASM_PFX(AsmReadMm0)\r
ASM_PFX(AsmReadMm0):\r
- ;\r
- ; 64-bit MASM doesn't support MMX instructions, so use opcode here\r
- ;\r
- DB 0x48, 0xf, 0x7e, 0xc0\r
+ movq rax, mm0\r
ret\r
\r
;------------------------------------------------------------------------------\r
;\r
-; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>\r
; SPDX-License-Identifier: BSD-2-Clause-Patent\r
;\r
; Module Name:\r
;------------------------------------------------------------------------------\r
global ASM_PFX(AsmReadMm1)\r
ASM_PFX(AsmReadMm1):\r
- ;\r
- ; 64-bit MASM doesn't support MMX instructions, so use opcode here\r
- ;\r
- DB 0x48, 0xf, 0x7e, 0xc8\r
+ movq rax, mm1\r
ret\r
\r
;------------------------------------------------------------------------------\r
;\r
-; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>\r
; SPDX-License-Identifier: BSD-2-Clause-Patent\r
;\r
; Module Name:\r
;------------------------------------------------------------------------------\r
global ASM_PFX(AsmReadMm2)\r
ASM_PFX(AsmReadMm2):\r
- ;\r
- ; 64-bit MASM doesn't support MMX instructions, so use opcode here\r
- ;\r
- DB 0x48, 0xf, 0x7e, 0xd0\r
+ movq rax, mm2\r
ret\r
\r
;------------------------------------------------------------------------------\r
;\r
-; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>\r
; SPDX-License-Identifier: BSD-2-Clause-Patent\r
;\r
; Module Name:\r
;------------------------------------------------------------------------------\r
global ASM_PFX(AsmReadMm3)\r
ASM_PFX(AsmReadMm3):\r
- ;\r
- ; 64-bit MASM doesn't support MMX instructions, so use opcode here\r
- ;\r
- DB 0x48, 0xf, 0x7e, 0xd8\r
+ movq rax, mm3\r
ret\r
\r
;------------------------------------------------------------------------------\r
;\r
-; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>\r
; SPDX-License-Identifier: BSD-2-Clause-Patent\r
;\r
; Module Name:\r
;------------------------------------------------------------------------------\r
global ASM_PFX(AsmReadMm4)\r
ASM_PFX(AsmReadMm4):\r
- ;\r
- ; 64-bit MASM doesn't support MMX instructions, so use opcode here\r
- ;\r
- DB 0x48, 0xf, 0x7e, 0xe0\r
+ movq rax, mm4\r
ret\r
\r
;------------------------------------------------------------------------------\r
;\r
-; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>\r
; SPDX-License-Identifier: BSD-2-Clause-Patent\r
;\r
; Module Name:\r
;------------------------------------------------------------------------------\r
global ASM_PFX(AsmReadMm5)\r
ASM_PFX(AsmReadMm5):\r
- ;\r
- ; 64-bit MASM doesn't support MMX instructions, so use opcode here\r
- ;\r
- DB 0x48, 0xf, 0x7e, 0xe8\r
+ movq rax, mm5\r
ret\r
\r
;------------------------------------------------------------------------------\r
;\r
-; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>\r
; SPDX-License-Identifier: BSD-2-Clause-Patent\r
;\r
; Module Name:\r
;------------------------------------------------------------------------------\r
global ASM_PFX(AsmReadMm6)\r
ASM_PFX(AsmReadMm6):\r
- ;\r
- ; 64-bit MASM doesn't support MMX instructions, so use opcode here\r
- ;\r
- DB 0x48, 0xf, 0x7e, 0xf0\r
+ movq rax, mm6\r
ret\r
\r
;------------------------------------------------------------------------------\r
;\r
-; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>\r
; SPDX-License-Identifier: BSD-2-Clause-Patent\r
;\r
; Module Name:\r
;------------------------------------------------------------------------------\r
global ASM_PFX(AsmReadMm7)\r
ASM_PFX(AsmReadMm7):\r
- ;\r
- ; 64-bit MASM doesn't support MMX instructions, so use opcode here\r
- ;\r
- DB 0x48, 0xf, 0x7e, 0xf8\r
+ movq rax, mm7\r
ret\r
\r
;------------------------------------------------------------------------------\r
;\r
-; Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>\r
; SPDX-License-Identifier: BSD-2-Clause-Patent\r
;\r
; Module Name:\r
jnc CetDone\r
\r
mov rax, 1\r
- INCSSP_RAX ; to read original SSP\r
- READSSP_RAX\r
+ incsspq rax ; to read original SSP\r
+ rdsspq rax\r
mov [rcx + 0xF8], rax ; save SSP\r
\r
CetDone:\r
;------------------------------------------------------------------------------\r
;\r
-; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>\r
; SPDX-License-Identifier: BSD-2-Clause-Patent\r
;\r
; Module Name:\r
; There's no obvious reason to access this register, since it's aliased to\r
; DR6 when DE=0 or an exception generated when DE=1\r
;\r
- DB 0xf, 0x23, 0xe1\r
+ mov dr4, rcx\r
mov rax, rcx\r
ret\r
\r
;------------------------------------------------------------------------------\r
;\r
-; Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>\r
; SPDX-License-Identifier: BSD-2-Clause-Patent\r
;\r
; Module Name:\r
; There's no obvious reason to access this register, since it's aliased to\r
; DR7 when DE=0 or an exception generated when DE=1\r
;\r
- DB 0xf, 0x23, 0xe9\r
+ mov dr5, rcx\r
mov rax, rcx\r
ret\r
\r
;------------------------------------------------------------------------------\r
;\r
-; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>\r
; SPDX-License-Identifier: BSD-2-Clause-Patent\r
;\r
; Module Name:\r
;------------------------------------------------------------------------------\r
global ASM_PFX(AsmWriteMm0)\r
ASM_PFX(AsmWriteMm0):\r
- ;\r
- ; 64-bit MASM doesn't support MMX instructions, so use opcode here\r
- ;\r
- DB 0x48, 0xf, 0x6e, 0xc1\r
+ movq mm0, rcx\r
ret\r
\r
;------------------------------------------------------------------------------\r
;\r
-; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>\r
; SPDX-License-Identifier: BSD-2-Clause-Patent\r
;\r
; Module Name:\r
;------------------------------------------------------------------------------\r
global ASM_PFX(AsmWriteMm1)\r
ASM_PFX(AsmWriteMm1):\r
- ;\r
- ; 64-bit MASM doesn't support MMX instructions, so use opcode here\r
- ;\r
- DB 0x48, 0xf, 0x6e, 0xc9\r
+ movq mm1, rcx\r
ret\r
\r
;------------------------------------------------------------------------------\r
;\r
-; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>\r
; SPDX-License-Identifier: BSD-2-Clause-Patent\r
;\r
; Module Name:\r
;------------------------------------------------------------------------------\r
global ASM_PFX(AsmWriteMm2)\r
ASM_PFX(AsmWriteMm2):\r
- ;\r
- ; 64-bit MASM doesn't support MMX instructions, so use opcode here\r
- ;\r
- DB 0x48, 0xf, 0x6e, 0xd1\r
+ movq mm2, rcx\r
ret\r
\r
;------------------------------------------------------------------------------\r
;\r
-; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>\r
; SPDX-License-Identifier: BSD-2-Clause-Patent\r
;\r
; Module Name:\r
;------------------------------------------------------------------------------\r
global ASM_PFX(AsmWriteMm3)\r
ASM_PFX(AsmWriteMm3):\r
- ;\r
- ; 64-bit MASM doesn't support MMX instructions, so use opcode here\r
- ;\r
- DB 0x48, 0xf, 0x6e, 0xd9\r
+ movq mm3, rcx\r
ret\r
\r
;------------------------------------------------------------------------------\r
;\r
-; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>\r
; SPDX-License-Identifier: BSD-2-Clause-Patent\r
;\r
; Module Name:\r
;------------------------------------------------------------------------------\r
global ASM_PFX(AsmWriteMm4)\r
ASM_PFX(AsmWriteMm4):\r
- ;\r
- ; 64-bit MASM doesn't support MMX instructions, so use opcode here\r
- ;\r
- DB 0x48, 0xf, 0x6e, 0xe1\r
+ movq mm4, rcx\r
ret\r
\r
;------------------------------------------------------------------------------\r
;\r
-; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>\r
; SPDX-License-Identifier: BSD-2-Clause-Patent\r
;\r
; Module Name:\r
;------------------------------------------------------------------------------\r
global ASM_PFX(AsmWriteMm5)\r
ASM_PFX(AsmWriteMm5):\r
- ;\r
- ; 64-bit MASM doesn't support MMX instructions, so use opcode here\r
- ;\r
- DB 0x48, 0xf, 0x6e, 0xe9\r
+ movq mm5, rcx\r
ret\r
\r
;------------------------------------------------------------------------------\r
;\r
-; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>\r
; SPDX-License-Identifier: BSD-2-Clause-Patent\r
;\r
; Module Name:\r
;------------------------------------------------------------------------------\r
global ASM_PFX(AsmWriteMm6)\r
ASM_PFX(AsmWriteMm6):\r
- ;\r
- ; 64-bit MASM doesn't support MMX instructions, so use opcode here\r
- ;\r
- DB 0x48, 0xf, 0x6e, 0xf1\r
+ movq mm6, rcx\r
ret\r
\r
;------------------------------------------------------------------------------\r
;\r
-; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>\r
; SPDX-License-Identifier: BSD-2-Clause-Patent\r
;\r
; Module Name:\r
;------------------------------------------------------------------------------\r
global ASM_PFX(AsmWriteMm7)\r
ASM_PFX(AsmWriteMm7):\r
- ;\r
- ; 64-bit MASM doesn't support MMX instructions, so use opcode here\r
- ;\r
- DB 0x48, 0xf, 0x6e, 0xf9\r
+ movq mm7, rcx\r
ret\r
\r
;------------------------------------------------------------------------------\r
;\r
-; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>\r
; SPDX-License-Identifier: BSD-2-Clause-Patent\r
;\r
; Module Name:\r
and r8, 7\r
shr rcx, 3 ; rcx <- # of Qwords to copy\r
jz @CopyBytes\r
- DB 0x49, 0xf, 0x7e, 0xc2 ; movd r10, mm0 (Save mm0 in r10)\r
+ movq r10, mm0\r
.1:\r
- DB 0xf, 0x6f, 0x6 ; movd mm0, [rsi]\r
- DB 0xf, 0xe7, 0x7 ; movntq [rdi], mm0\r
+ movq mm0, [rsi]\r
+ movntq [rdi], mm0\r
add rsi, 8\r
add rdi, 8\r
loop .1\r
mfence\r
- DB 0x49, 0xf, 0x6e, 0xc2 ; movd mm0, r10 (Restore mm0)\r
+ movq mm0, r10\r
jmp @CopyBytes\r
@CopyBackward:\r
mov rsi, r9 ; rsi <- End of Source\r
;------------------------------------------------------------------------------\r
;\r
-; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>\r
; SPDX-License-Identifier: BSD-2-Clause-Patent\r
;\r
; Module Name:\r
push rdi\r
mov rax, r8\r
mov ah, al\r
- DB 0x48, 0xf, 0x6e, 0xc0 ; movd mm0, rax\r
+ movq mm0, rax\r
mov r8, rcx\r
mov rdi, r8 ; rdi <- Buffer\r
mov rcx, rdx\r
and edx, 7\r
shr rcx, 3\r
jz @SetBytes\r
- DB 0xf, 0x70, 0xC0, 0x0 ; pshufw mm0, mm0, 0h\r
+ pshufw mm0, mm0, 0\r
.0:\r
- DB 0xf, 0xe7, 0x7 ; movntq [rdi], mm0\r
+ movntq [rdi], mm0\r
add rdi, 8\r
loop .0\r
mfence\r
;------------------------------------------------------------------------------\r
;\r
-; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>\r
; SPDX-License-Identifier: BSD-2-Clause-Patent\r
;\r
; Module Name:\r
ASM_PFX(InternalMemSetMem16):\r
push rdi\r
mov rax, r8\r
- DB 0x48, 0xf, 0x6e, 0xc0 ; movd mm0, rax\r
+ movq mm0, rax\r
mov r8, rcx\r
mov rdi, r8\r
mov rcx, rdx\r
and edx, 3\r
shr rcx, 2\r
jz @SetWords\r
- DB 0xf, 0x70, 0xC0, 0x0 ; pshufw mm0, mm0, 0h\r
+ pshufw mm0, mm0, 0\r
.0:\r
- DB 0xf, 0xe7, 0x7 ; movntq [rdi], mm0\r
+ movntq [rdi], mm0\r
add rdi, 8\r
loop .0\r
mfence\r
;------------------------------------------------------------------------------\r
;\r
-; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>\r
; SPDX-License-Identifier: BSD-2-Clause-Patent\r
;\r
; Module Name:\r
;------------------------------------------------------------------------------\r
global ASM_PFX(InternalMemSetMem32)\r
ASM_PFX(InternalMemSetMem32):\r
- DB 0x49, 0xf, 0x6e, 0xc0 ; movd mm0, r8 (Value)\r
+ movq mm0, r8\r
mov rax, rcx ; rax <- Buffer\r
xchg rcx, rdx ; rcx <- Count rdx <- Buffer\r
shr rcx, 1 ; rcx <- # of qwords to set\r
jz @SetDwords\r
- DB 0xf, 0x70, 0xC0, 0x44 ; pshufw mm0, mm0, 44h\r
+ pshufw mm0, mm0, 44h\r
.0:\r
- DB 0xf, 0xe7, 0x2 ; movntq [rdx], mm0\r
+ movntq [rdx], mm0\r
lea rdx, [rdx + 8] ; use "lea" to avoid flag changes\r
loop .0\r
mfence\r
@SetDwords:\r
jnc .1\r
- DB 0xf, 0x7e, 0x2 ; movd [rdx], mm0\r
+ movd [rdx], mm0\r
.1:\r
ret\r
\r
;------------------------------------------------------------------------------\r
;\r
-; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>\r
; SPDX-License-Identifier: BSD-2-Clause-Patent\r
;\r
; Module Name:\r
;------------------------------------------------------------------------------\r
global ASM_PFX(InternalMemSetMem64)\r
ASM_PFX(InternalMemSetMem64):\r
- DB 0x49, 0xf, 0x6e, 0xc0 ; movd mm0, r8 (Value)\r
+ movq mm0, r8\r
mov rax, rcx ; rax <- Buffer\r
xchg rcx, rdx ; rcx <- Count\r
.0:\r
- DB 0xf, 0xe7, 0x2 ; movntq [rdx], mm0\r
+ movntq [rdx], mm0\r
add rdx, 8\r
loop .0\r
mfence\r
;------------------------------------------------------------------------------\r
;\r
-; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>\r
; SPDX-License-Identifier: BSD-2-Clause-Patent\r
;\r
; Module Name:\r
and edx, 7\r
shr rcx, 3\r
jz @ZeroBytes\r
- DB 0xf, 0xef, 0xc0 ; pxor mm0, mm0\r
+ pxor mm0, mm0\r
.0:\r
- DB 0xf, 0xe7, 7 ; movntq [rdi], mm0\r
+ movntq [rdi], mm0\r
add rdi, 8\r
loop .0\r
- DB 0xf, 0xae, 0xf0 ; mfence\r
+ mfence\r
@ZeroBytes:\r
xor eax, eax\r
mov ecx, edx\r