2 PCI Library using PCI Root Bridge I/O Protocol.
4 Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>
5 SPDX-License-Identifier: BSD-2-Clause-Patent
9 #include <Protocol/PciRootBridgeIo.h>
11 #include <Library/PciLib.h>
12 #include <Library/BaseLib.h>
13 #include <Library/UefiBootServicesTableLib.h>
14 #include <Library/DebugLib.h>
17 Assert the validity of a PCI address. A valid PCI address should contain 1's
18 only in the low 28 bits.
20 @param A The address to validate.
21 @param M Additional bits to assert to be zero.
24 #define ASSERT_INVALID_PCI_ADDRESS(A,M) \
25 ASSERT (((A) & (~0xfffffff | (M))) == 0)
28 Translate PCI Lib address into format of PCI Root Bridge I/O Protocol.
30 @param A The address that encodes the PCI Bus, Device, Function and
34 #define PCI_TO_PCI_ROOT_BRIDGE_IO_ADDRESS(A) \
35 ((((A) << 4) & 0xff000000) | (((A) >> 4) & 0x00000700) | (((A) << 1) & 0x001f0000) | (LShiftU64((A) & 0xfff, 32)))
38 // Global varible to cache pointer to PCI Root Bridge I/O protocol.
40 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*mPciRootBridgeIo
= NULL
;
43 The constructor function caches the pointer to PCI Root Bridge I/O protocol.
45 The constructor function locates PCI Root Bridge I/O protocol from protocol database.
46 It will ASSERT() if that operation fails and it will always return EFI_SUCCESS.
48 @param ImageHandle The firmware allocated handle for the EFI image.
49 @param SystemTable A pointer to the EFI System Table.
51 @retval EFI_SUCCESS The constructor always returns EFI_SUCCESS.
57 IN EFI_HANDLE ImageHandle
,
58 IN EFI_SYSTEM_TABLE
*SystemTable
63 Status
= gBS
->LocateProtocol (&gEfiPciRootBridgeIoProtocolGuid
, NULL
, (VOID
**) &mPciRootBridgeIo
);
64 ASSERT_EFI_ERROR (Status
);
65 ASSERT (mPciRootBridgeIo
!= NULL
);
71 Internal worker function to read a PCI configuration register.
73 This function wraps EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.Pci.Read() service.
74 It reads and returns the PCI configuration register specified by Address,
75 the width of data is specified by Width.
77 @param Address The address that encodes the PCI Bus, Device, Function and
79 @param Width The width of data to read
81 @return The value read from the PCI configuration register.
85 DxePciLibPciRootBridgeIoReadWorker (
87 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
92 mPciRootBridgeIo
->Pci
.Read (
95 PCI_TO_PCI_ROOT_BRIDGE_IO_ADDRESS (Address
),
104 Internal worker function to writes a PCI configuration register.
106 This function wraps EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.Pci.Write() service.
107 It writes the PCI configuration register specified by Address with the
108 value specified by Data. The width of data is specified by Width.
111 @param Address The address that encodes the PCI Bus, Device, Function and
113 @param Width The width of data to write
114 @param Data The value to write.
116 @return The value written to the PCI configuration register.
120 DxePciLibPciRootBridgeIoWriteWorker (
122 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width
,
126 mPciRootBridgeIo
->Pci
.Write (
129 PCI_TO_PCI_ROOT_BRIDGE_IO_ADDRESS (Address
),
137 Registers a PCI device so PCI configuration registers may be accessed after
138 SetVirtualAddressMap().
140 Registers the PCI device specified by Address so all the PCI configuration registers
141 associated with that PCI device may be accessed after SetVirtualAddressMap() is called.
143 If Address > 0x0FFFFFFF, then ASSERT().
145 @param Address The address that encodes the PCI Bus, Device, Function and
148 @retval RETURN_SUCCESS The PCI device was registered for runtime access.
149 @retval RETURN_UNSUPPORTED An attempt was made to call this function
150 after ExitBootServices().
151 @retval RETURN_UNSUPPORTED The resources required to access the PCI device
152 at runtime could not be mapped.
153 @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to
154 complete the registration.
159 PciRegisterForRuntimeAccess (
163 ASSERT_INVALID_PCI_ADDRESS (Address
, 0);
164 return RETURN_UNSUPPORTED
;
168 Reads an 8-bit PCI configuration register.
170 Reads and returns the 8-bit PCI configuration register specified by Address.
171 This function must guarantee that all PCI read and write operations are
174 If Address > 0x0FFFFFFF, then ASSERT().
176 @param Address The address that encodes the PCI Bus, Device, Function and
179 @return The read value from the PCI configuration register.
188 ASSERT_INVALID_PCI_ADDRESS (Address
, 0);
190 return (UINT8
) DxePciLibPciRootBridgeIoReadWorker (Address
, EfiPciWidthUint8
);
194 Writes an 8-bit PCI configuration register.
196 Writes the 8-bit PCI configuration register specified by Address with the
197 value specified by Value. Value is returned. This function must guarantee
198 that all PCI read and write operations are serialized.
200 If Address > 0x0FFFFFFF, then ASSERT().
202 @param Address The address that encodes the PCI Bus, Device, Function and
204 @param Value The value to write.
206 @return The value written to the PCI configuration register.
216 ASSERT_INVALID_PCI_ADDRESS (Address
, 0);
218 return (UINT8
) DxePciLibPciRootBridgeIoWriteWorker (Address
, EfiPciWidthUint8
, Value
);
222 Performs a bitwise OR of an 8-bit PCI configuration register with
225 Reads the 8-bit PCI configuration register specified by Address, performs a
226 bitwise OR between the read result and the value specified by
227 OrData, and writes the result to the 8-bit PCI configuration register
228 specified by Address. The value written to the PCI configuration register is
229 returned. This function must guarantee that all PCI read and write operations
232 If Address > 0x0FFFFFFF, then ASSERT().
234 @param Address The address that encodes the PCI Bus, Device, Function and
236 @param OrData The value to OR with the PCI configuration register.
238 @return The value written back to the PCI configuration register.
248 return PciWrite8 (Address
, (UINT8
) (PciRead8 (Address
) | OrData
));
252 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
255 Reads the 8-bit PCI configuration register specified by Address, performs a
256 bitwise AND between the read result and the value specified by AndData, and
257 writes the result to the 8-bit PCI configuration register specified by
258 Address. The value written to the PCI configuration register is returned.
259 This function must guarantee that all PCI read and write operations are
262 If Address > 0x0FFFFFFF, then ASSERT().
264 @param Address The address that encodes the PCI Bus, Device, Function and
266 @param AndData The value to AND with the PCI configuration register.
268 @return The value written back to the PCI configuration register.
278 return PciWrite8 (Address
, (UINT8
) (PciRead8 (Address
) & AndData
));
282 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
283 value, followed a bitwise OR with another 8-bit value.
285 Reads the 8-bit PCI configuration register specified by Address, performs a
286 bitwise AND between the read result and the value specified by AndData,
287 performs a bitwise OR between the result of the AND operation and
288 the value specified by OrData, and writes the result to the 8-bit PCI
289 configuration register specified by Address. The value written to the PCI
290 configuration register is returned. This function must guarantee that all PCI
291 read and write operations are serialized.
293 If Address > 0x0FFFFFFF, then ASSERT().
295 @param Address The address that encodes the PCI Bus, Device, Function and
297 @param AndData The value to AND with the PCI configuration register.
298 @param OrData The value to OR with the result of the AND operation.
300 @return The value written back to the PCI configuration register.
311 return PciWrite8 (Address
, (UINT8
) ((PciRead8 (Address
) & AndData
) | OrData
));
315 Reads a bit field of a PCI configuration register.
317 Reads the bit field in an 8-bit PCI configuration register. The bit field is
318 specified by the StartBit and the EndBit. The value of the bit field is
321 If Address > 0x0FFFFFFF, then ASSERT().
322 If StartBit is greater than 7, then ASSERT().
323 If EndBit is greater than 7, then ASSERT().
324 If EndBit is less than StartBit, then ASSERT().
326 @param Address The PCI configuration register to read.
327 @param StartBit The ordinal of the least significant bit in the bit field.
329 @param EndBit The ordinal of the most significant bit in the bit field.
332 @return The value of the bit field read from the PCI configuration register.
343 return BitFieldRead8 (PciRead8 (Address
), StartBit
, EndBit
);
347 Writes a bit field to a PCI configuration register.
349 Writes Value to the bit field of the PCI configuration register. The bit
350 field is specified by the StartBit and the EndBit. All other bits in the
351 destination PCI configuration register are preserved. The new value of the
352 8-bit register is returned.
354 If Address > 0x0FFFFFFF, then ASSERT().
355 If StartBit is greater than 7, then ASSERT().
356 If EndBit is greater than 7, then ASSERT().
357 If EndBit is less than StartBit, then ASSERT().
358 If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
360 @param Address The PCI configuration register to write.
361 @param StartBit The ordinal of the least significant bit in the bit field.
363 @param EndBit The ordinal of the most significant bit in the bit field.
365 @param Value The new value of the bit field.
367 @return The value written back to the PCI configuration register.
381 BitFieldWrite8 (PciRead8 (Address
), StartBit
, EndBit
, Value
)
386 Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
387 writes the result back to the bit field in the 8-bit port.
389 Reads the 8-bit PCI configuration register specified by Address, performs a
390 bitwise OR between the read result and the value specified by
391 OrData, and writes the result to the 8-bit PCI configuration register
392 specified by Address. The value written to the PCI configuration register is
393 returned. This function must guarantee that all PCI read and write operations
394 are serialized. Extra left bits in OrData are stripped.
396 If Address > 0x0FFFFFFF, then ASSERT().
397 If StartBit is greater than 7, then ASSERT().
398 If EndBit is greater than 7, then ASSERT().
399 If EndBit is less than StartBit, then ASSERT().
400 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
402 @param Address The PCI configuration register to write.
403 @param StartBit The ordinal of the least significant bit in the bit field.
405 @param EndBit The ordinal of the most significant bit in the bit field.
407 @param OrData The value to OR with the PCI configuration register.
409 @return The value written back to the PCI configuration register.
423 BitFieldOr8 (PciRead8 (Address
), StartBit
, EndBit
, OrData
)
428 Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
429 AND, and writes the result back to the bit field in the 8-bit register.
431 Reads the 8-bit PCI configuration register specified by Address, performs a
432 bitwise AND between the read result and the value specified by AndData, and
433 writes the result to the 8-bit PCI configuration register specified by
434 Address. The value written to the PCI configuration register is returned.
435 This function must guarantee that all PCI read and write operations are
436 serialized. Extra left bits in AndData are stripped.
438 If Address > 0x0FFFFFFF, then ASSERT().
439 If StartBit is greater than 7, then ASSERT().
440 If EndBit is greater than 7, then ASSERT().
441 If EndBit is less than StartBit, then ASSERT().
442 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
444 @param Address The PCI configuration register to write.
445 @param StartBit The ordinal of the least significant bit in the bit field.
447 @param EndBit The ordinal of the most significant bit in the bit field.
449 @param AndData The value to AND with the PCI configuration register.
451 @return The value written back to the PCI configuration register.
465 BitFieldAnd8 (PciRead8 (Address
), StartBit
, EndBit
, AndData
)
470 Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
471 bitwise OR, and writes the result back to the bit field in the
474 Reads the 8-bit PCI configuration register specified by Address, performs a
475 bitwise AND followed by a bitwise OR between the read result and
476 the value specified by AndData, and writes the result to the 8-bit PCI
477 configuration register specified by Address. The value written to the PCI
478 configuration register is returned. This function must guarantee that all PCI
479 read and write operations are serialized. Extra left bits in both AndData and
482 If Address > 0x0FFFFFFF, then ASSERT().
483 If StartBit is greater than 7, then ASSERT().
484 If EndBit is greater than 7, then ASSERT().
485 If EndBit is less than StartBit, then ASSERT().
486 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
487 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
489 @param Address The PCI configuration register to write.
490 @param StartBit The ordinal of the least significant bit in the bit field.
492 @param EndBit The ordinal of the most significant bit in the bit field.
494 @param AndData The value to AND with the PCI configuration register.
495 @param OrData The value to OR with the result of the AND operation.
497 @return The value written back to the PCI configuration register.
502 PciBitFieldAndThenOr8 (
512 BitFieldAndThenOr8 (PciRead8 (Address
), StartBit
, EndBit
, AndData
, OrData
)
517 Reads a 16-bit PCI configuration register.
519 Reads and returns the 16-bit PCI configuration register specified by Address.
520 This function must guarantee that all PCI read and write operations are
523 If Address > 0x0FFFFFFF, then ASSERT().
524 If Address is not aligned on a 16-bit boundary, then ASSERT().
526 @param Address The address that encodes the PCI Bus, Device, Function and
529 @return The read value from the PCI configuration register.
538 ASSERT_INVALID_PCI_ADDRESS (Address
, 1);
540 return (UINT16
) DxePciLibPciRootBridgeIoReadWorker (Address
, EfiPciWidthUint16
);
544 Writes a 16-bit PCI configuration register.
546 Writes the 16-bit PCI configuration register specified by Address with the
547 value specified by Value. Value is returned. This function must guarantee
548 that all PCI read and write operations are serialized.
550 If Address > 0x0FFFFFFF, then ASSERT().
551 If Address is not aligned on a 16-bit boundary, then ASSERT().
553 @param Address The address that encodes the PCI Bus, Device, Function and
555 @param Value The value to write.
557 @return The value written to the PCI configuration register.
567 ASSERT_INVALID_PCI_ADDRESS (Address
, 1);
569 return (UINT16
) DxePciLibPciRootBridgeIoWriteWorker (Address
, EfiPciWidthUint16
, Value
);
573 Performs a bitwise OR of a 16-bit PCI configuration register with
576 Reads the 16-bit PCI configuration register specified by Address, performs a
577 bitwise OR between the read result and the value specified by
578 OrData, and writes the result to the 16-bit PCI configuration register
579 specified by Address. The value written to the PCI configuration register is
580 returned. This function must guarantee that all PCI read and write operations
583 If Address > 0x0FFFFFFF, then ASSERT().
584 If Address is not aligned on a 16-bit boundary, then ASSERT().
586 @param Address The address that encodes the PCI Bus, Device, Function and
588 @param OrData The value to OR with the PCI configuration register.
590 @return The value written back to the PCI configuration register.
600 return PciWrite16 (Address
, (UINT16
) (PciRead16 (Address
) | OrData
));
604 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
607 Reads the 16-bit PCI configuration register specified by Address, performs a
608 bitwise AND between the read result and the value specified by AndData, and
609 writes the result to the 16-bit PCI configuration register specified by
610 Address. The value written to the PCI configuration register is returned.
611 This function must guarantee that all PCI read and write operations are
614 If Address > 0x0FFFFFFF, then ASSERT().
615 If Address is not aligned on a 16-bit boundary, then ASSERT().
617 @param Address The address that encodes the PCI Bus, Device, Function and
619 @param AndData The value to AND with the PCI configuration register.
621 @return The value written back to the PCI configuration register.
631 return PciWrite16 (Address
, (UINT16
) (PciRead16 (Address
) & AndData
));
635 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
636 value, followed a bitwise OR with another 16-bit value.
638 Reads the 16-bit PCI configuration register specified by Address, performs a
639 bitwise AND between the read result and the value specified by AndData,
640 performs a bitwise OR between the result of the AND operation and
641 the value specified by OrData, and writes the result to the 16-bit PCI
642 configuration register specified by Address. The value written to the PCI
643 configuration register is returned. This function must guarantee that all PCI
644 read and write operations are serialized.
646 If Address > 0x0FFFFFFF, then ASSERT().
647 If Address is not aligned on a 16-bit boundary, then ASSERT().
649 @param Address The address that encodes the PCI Bus, Device, Function and
651 @param AndData The value to AND with the PCI configuration register.
652 @param OrData The value to OR with the result of the AND operation.
654 @return The value written back to the PCI configuration register.
665 return PciWrite16 (Address
, (UINT16
) ((PciRead16 (Address
) & AndData
) | OrData
));
669 Reads a bit field of a PCI configuration register.
671 Reads the bit field in a 16-bit PCI configuration register. The bit field is
672 specified by the StartBit and the EndBit. The value of the bit field is
675 If Address > 0x0FFFFFFF, then ASSERT().
676 If Address is not aligned on a 16-bit boundary, then ASSERT().
677 If StartBit is greater than 15, then ASSERT().
678 If EndBit is greater than 15, then ASSERT().
679 If EndBit is less than StartBit, then ASSERT().
681 @param Address The PCI configuration register to read.
682 @param StartBit The ordinal of the least significant bit in the bit field.
684 @param EndBit The ordinal of the most significant bit in the bit field.
687 @return The value of the bit field read from the PCI configuration register.
698 return BitFieldRead16 (PciRead16 (Address
), StartBit
, EndBit
);
702 Writes a bit field to a PCI configuration register.
704 Writes Value to the bit field of the PCI configuration register. The bit
705 field is specified by the StartBit and the EndBit. All other bits in the
706 destination PCI configuration register are preserved. The new value of the
707 16-bit register is returned.
709 If Address > 0x0FFFFFFF, then ASSERT().
710 If Address is not aligned on a 16-bit boundary, then ASSERT().
711 If StartBit is greater than 15, then ASSERT().
712 If EndBit is greater than 15, then ASSERT().
713 If EndBit is less than StartBit, then ASSERT().
714 If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
716 @param Address The PCI configuration register to write.
717 @param StartBit The ordinal of the least significant bit in the bit field.
719 @param EndBit The ordinal of the most significant bit in the bit field.
721 @param Value The new value of the bit field.
723 @return The value written back to the PCI configuration register.
737 BitFieldWrite16 (PciRead16 (Address
), StartBit
, EndBit
, Value
)
742 Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
743 writes the result back to the bit field in the 16-bit port.
745 Reads the 16-bit PCI configuration register specified by Address, performs a
746 bitwise OR between the read result and the value specified by
747 OrData, and writes the result to the 16-bit PCI configuration register
748 specified by Address. The value written to the PCI configuration register is
749 returned. This function must guarantee that all PCI read and write operations
750 are serialized. Extra left bits in OrData are stripped.
752 If Address > 0x0FFFFFFF, then ASSERT().
753 If Address is not aligned on a 16-bit boundary, then ASSERT().
754 If StartBit is greater than 15, then ASSERT().
755 If EndBit is greater than 15, then ASSERT().
756 If EndBit is less than StartBit, then ASSERT().
757 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
759 @param Address The PCI configuration register to write.
760 @param StartBit The ordinal of the least significant bit in the bit field.
762 @param EndBit The ordinal of the most significant bit in the bit field.
764 @param OrData The value to OR with the PCI configuration register.
766 @return The value written back to the PCI configuration register.
780 BitFieldOr16 (PciRead16 (Address
), StartBit
, EndBit
, OrData
)
785 Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
786 AND, and writes the result back to the bit field in the 16-bit register.
788 Reads the 16-bit PCI configuration register specified by Address, performs a
789 bitwise AND between the read result and the value specified by AndData, and
790 writes the result to the 16-bit PCI configuration register specified by
791 Address. The value written to the PCI configuration register is returned.
792 This function must guarantee that all PCI read and write operations are
793 serialized. Extra left bits in AndData are stripped.
795 If Address > 0x0FFFFFFF, then ASSERT().
796 If Address is not aligned on a 16-bit boundary, then ASSERT().
797 If StartBit is greater than 15, then ASSERT().
798 If EndBit is greater than 15, then ASSERT().
799 If EndBit is less than StartBit, then ASSERT().
800 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
802 @param Address The PCI configuration register to write.
803 @param StartBit The ordinal of the least significant bit in the bit field.
805 @param EndBit The ordinal of the most significant bit in the bit field.
807 @param AndData The value to AND with the PCI configuration register.
809 @return The value written back to the PCI configuration register.
823 BitFieldAnd16 (PciRead16 (Address
), StartBit
, EndBit
, AndData
)
828 Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
829 bitwise OR, and writes the result back to the bit field in the
832 Reads the 16-bit PCI configuration register specified by Address, performs a
833 bitwise AND followed by a bitwise OR between the read result and
834 the value specified by AndData, and writes the result to the 16-bit PCI
835 configuration register specified by Address. The value written to the PCI
836 configuration register is returned. This function must guarantee that all PCI
837 read and write operations are serialized. Extra left bits in both AndData and
840 If Address > 0x0FFFFFFF, then ASSERT().
841 If Address is not aligned on a 16-bit boundary, then ASSERT().
842 If StartBit is greater than 15, then ASSERT().
843 If EndBit is greater than 15, then ASSERT().
844 If EndBit is less than StartBit, then ASSERT().
845 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
846 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
848 @param Address The PCI configuration register to write.
849 @param StartBit The ordinal of the least significant bit in the bit field.
851 @param EndBit The ordinal of the most significant bit in the bit field.
853 @param AndData The value to AND with the PCI configuration register.
854 @param OrData The value to OR with the result of the AND operation.
856 @return The value written back to the PCI configuration register.
861 PciBitFieldAndThenOr16 (
871 BitFieldAndThenOr16 (PciRead16 (Address
), StartBit
, EndBit
, AndData
, OrData
)
876 Reads a 32-bit PCI configuration register.
878 Reads and returns the 32-bit PCI configuration register specified by Address.
879 This function must guarantee that all PCI read and write operations are
882 If Address > 0x0FFFFFFF, then ASSERT().
883 If Address is not aligned on a 32-bit boundary, then ASSERT().
885 @param Address The address that encodes the PCI Bus, Device, Function and
888 @return The read value from the PCI configuration register.
897 ASSERT_INVALID_PCI_ADDRESS (Address
, 3);
899 return DxePciLibPciRootBridgeIoReadWorker (Address
, EfiPciWidthUint32
);
903 Writes a 32-bit PCI configuration register.
905 Writes the 32-bit PCI configuration register specified by Address with the
906 value specified by Value. Value is returned. This function must guarantee
907 that all PCI read and write operations are serialized.
909 If Address > 0x0FFFFFFF, then ASSERT().
910 If Address is not aligned on a 32-bit boundary, then ASSERT().
912 @param Address The address that encodes the PCI Bus, Device, Function and
914 @param Value The value to write.
916 @return The value written to the PCI configuration register.
926 ASSERT_INVALID_PCI_ADDRESS (Address
, 3);
928 return DxePciLibPciRootBridgeIoWriteWorker (Address
, EfiPciWidthUint32
, Value
);
932 Performs a bitwise OR of a 32-bit PCI configuration register with
935 Reads the 32-bit PCI configuration register specified by Address, performs a
936 bitwise OR between the read result and the value specified by
937 OrData, and writes the result to the 32-bit PCI configuration register
938 specified by Address. The value written to the PCI configuration register is
939 returned. This function must guarantee that all PCI read and write operations
942 If Address > 0x0FFFFFFF, then ASSERT().
943 If Address is not aligned on a 32-bit boundary, then ASSERT().
945 @param Address The address that encodes the PCI Bus, Device, Function and
947 @param OrData The value to OR with the PCI configuration register.
949 @return The value written back to the PCI configuration register.
959 return PciWrite32 (Address
, PciRead32 (Address
) | OrData
);
963 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
966 Reads the 32-bit PCI configuration register specified by Address, performs a
967 bitwise AND between the read result and the value specified by AndData, and
968 writes the result to the 32-bit PCI configuration register specified by
969 Address. The value written to the PCI configuration register is returned.
970 This function must guarantee that all PCI read and write operations are
973 If Address > 0x0FFFFFFF, then ASSERT().
974 If Address is not aligned on a 32-bit boundary, then ASSERT().
976 @param Address The address that encodes the PCI Bus, Device, Function and
978 @param AndData The value to AND with the PCI configuration register.
980 @return The value written back to the PCI configuration register.
990 return PciWrite32 (Address
, PciRead32 (Address
) & AndData
);
994 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
995 value, followed a bitwise OR with another 32-bit value.
997 Reads the 32-bit PCI configuration register specified by Address, performs a
998 bitwise AND between the read result and the value specified by AndData,
999 performs a bitwise OR between the result of the AND operation and
1000 the value specified by OrData, and writes the result to the 32-bit PCI
1001 configuration register specified by Address. The value written to the PCI
1002 configuration register is returned. This function must guarantee that all PCI
1003 read and write operations are serialized.
1005 If Address > 0x0FFFFFFF, then ASSERT().
1006 If Address is not aligned on a 32-bit boundary, then ASSERT().
1008 @param Address The address that encodes the PCI Bus, Device, Function and
1010 @param AndData The value to AND with the PCI configuration register.
1011 @param OrData The value to OR with the result of the AND operation.
1013 @return The value written back to the PCI configuration register.
1024 return PciWrite32 (Address
, (PciRead32 (Address
) & AndData
) | OrData
);
1028 Reads a bit field of a PCI configuration register.
1030 Reads the bit field in a 32-bit PCI configuration register. The bit field is
1031 specified by the StartBit and the EndBit. The value of the bit field is
1034 If Address > 0x0FFFFFFF, then ASSERT().
1035 If Address is not aligned on a 32-bit boundary, then ASSERT().
1036 If StartBit is greater than 31, then ASSERT().
1037 If EndBit is greater than 31, then ASSERT().
1038 If EndBit is less than StartBit, then ASSERT().
1040 @param Address The PCI configuration register to read.
1041 @param StartBit The ordinal of the least significant bit in the bit field.
1043 @param EndBit The ordinal of the most significant bit in the bit field.
1046 @return The value of the bit field read from the PCI configuration register.
1057 return BitFieldRead32 (PciRead32 (Address
), StartBit
, EndBit
);
1061 Writes a bit field to a PCI configuration register.
1063 Writes Value to the bit field of the PCI configuration register. The bit
1064 field is specified by the StartBit and the EndBit. All other bits in the
1065 destination PCI configuration register are preserved. The new value of the
1066 32-bit register is returned.
1068 If Address > 0x0FFFFFFF, then ASSERT().
1069 If Address is not aligned on a 32-bit boundary, then ASSERT().
1070 If StartBit is greater than 31, then ASSERT().
1071 If EndBit is greater than 31, then ASSERT().
1072 If EndBit is less than StartBit, then ASSERT().
1073 If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
1075 @param Address The PCI configuration register to write.
1076 @param StartBit The ordinal of the least significant bit in the bit field.
1078 @param EndBit The ordinal of the most significant bit in the bit field.
1080 @param Value The new value of the bit field.
1082 @return The value written back to the PCI configuration register.
1087 PciBitFieldWrite32 (
1096 BitFieldWrite32 (PciRead32 (Address
), StartBit
, EndBit
, Value
)
1101 Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
1102 writes the result back to the bit field in the 32-bit port.
1104 Reads the 32-bit PCI configuration register specified by Address, performs a
1105 bitwise OR between the read result and the value specified by
1106 OrData, and writes the result to the 32-bit PCI configuration register
1107 specified by Address. The value written to the PCI configuration register is
1108 returned. This function must guarantee that all PCI read and write operations
1109 are serialized. Extra left bits in OrData are stripped.
1111 If Address > 0x0FFFFFFF, then ASSERT().
1112 If Address is not aligned on a 32-bit boundary, then ASSERT().
1113 If StartBit is greater than 31, then ASSERT().
1114 If EndBit is greater than 31, then ASSERT().
1115 If EndBit is less than StartBit, then ASSERT().
1116 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
1118 @param Address The PCI configuration register to write.
1119 @param StartBit The ordinal of the least significant bit in the bit field.
1121 @param EndBit The ordinal of the most significant bit in the bit field.
1123 @param OrData The value to OR with the PCI configuration register.
1125 @return The value written back to the PCI configuration register.
1139 BitFieldOr32 (PciRead32 (Address
), StartBit
, EndBit
, OrData
)
1144 Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
1145 AND, and writes the result back to the bit field in the 32-bit register.
1147 Reads the 32-bit PCI configuration register specified by Address, performs a
1148 bitwise AND between the read result and the value specified by AndData, and
1149 writes the result to the 32-bit PCI configuration register specified by
1150 Address. The value written to the PCI configuration register is returned.
1151 This function must guarantee that all PCI read and write operations are
1152 serialized. Extra left bits in AndData are stripped.
1154 If Address > 0x0FFFFFFF, then ASSERT().
1155 If Address is not aligned on a 32-bit boundary, then ASSERT().
1156 If StartBit is greater than 31, then ASSERT().
1157 If EndBit is greater than 31, then ASSERT().
1158 If EndBit is less than StartBit, then ASSERT().
1159 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
1161 @param Address The PCI configuration register to write.
1162 @param StartBit The ordinal of the least significant bit in the bit field.
1164 @param EndBit The ordinal of the most significant bit in the bit field.
1166 @param AndData The value to AND with the PCI configuration register.
1168 @return The value written back to the PCI configuration register.
1182 BitFieldAnd32 (PciRead32 (Address
), StartBit
, EndBit
, AndData
)
1187 Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
1188 bitwise OR, and writes the result back to the bit field in the
1191 Reads the 32-bit PCI configuration register specified by Address, performs a
1192 bitwise AND followed by a bitwise OR between the read result and
1193 the value specified by AndData, and writes the result to the 32-bit PCI
1194 configuration register specified by Address. The value written to the PCI
1195 configuration register is returned. This function must guarantee that all PCI
1196 read and write operations are serialized. Extra left bits in both AndData and
1197 OrData are stripped.
1199 If Address > 0x0FFFFFFF, then ASSERT().
1200 If Address is not aligned on a 32-bit boundary, then ASSERT().
1201 If StartBit is greater than 31, then ASSERT().
1202 If EndBit is greater than 31, then ASSERT().
1203 If EndBit is less than StartBit, then ASSERT().
1204 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
1205 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
1207 @param Address The PCI configuration register to write.
1208 @param StartBit The ordinal of the least significant bit in the bit field.
1210 @param EndBit The ordinal of the most significant bit in the bit field.
1212 @param AndData The value to AND with the PCI configuration register.
1213 @param OrData The value to OR with the result of the AND operation.
1215 @return The value written back to the PCI configuration register.
1220 PciBitFieldAndThenOr32 (
1230 BitFieldAndThenOr32 (PciRead32 (Address
), StartBit
, EndBit
, AndData
, OrData
)
1235 Reads a range of PCI configuration registers into a caller supplied buffer.
1237 Reads the range of PCI configuration registers specified by StartAddress and
1238 Size into the buffer specified by Buffer. This function only allows the PCI
1239 configuration registers from a single PCI function to be read. Size is
1240 returned. When possible 32-bit PCI configuration read cycles are used to read
1241 from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
1242 and 16-bit PCI configuration read cycles may be used at the beginning and the
1245 If StartAddress > 0x0FFFFFFF, then ASSERT().
1246 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1247 If Size > 0 and Buffer is NULL, then ASSERT().
1249 @param StartAddress The starting address that encodes the PCI Bus, Device,
1250 Function and Register.
1251 @param Size The size in bytes of the transfer.
1252 @param Buffer The pointer to a buffer receiving the data read.
1260 IN UINTN StartAddress
,
1267 ASSERT_INVALID_PCI_ADDRESS (StartAddress
, 0);
1268 ASSERT (((StartAddress
& 0xFFF) + Size
) <= 0x1000);
1274 ASSERT (Buffer
!= NULL
);
1277 // Save Size for return
1281 if ((StartAddress
& BIT0
) != 0) {
1283 // Read a byte if StartAddress is byte aligned
1285 *(volatile UINT8
*)Buffer
= PciRead8 (StartAddress
);
1286 StartAddress
+= sizeof (UINT8
);
1287 Size
-= sizeof (UINT8
);
1288 Buffer
= (UINT8
*)Buffer
+ 1;
1291 if (Size
>= sizeof (UINT16
) && (StartAddress
& BIT1
) != 0) {
1293 // Read a word if StartAddress is word aligned
1295 WriteUnaligned16 (Buffer
, PciRead16 (StartAddress
));
1296 StartAddress
+= sizeof (UINT16
);
1297 Size
-= sizeof (UINT16
);
1298 Buffer
= (UINT16
*)Buffer
+ 1;
1301 while (Size
>= sizeof (UINT32
)) {
1303 // Read as many double words as possible
1305 WriteUnaligned32 (Buffer
, PciRead32 (StartAddress
));
1306 StartAddress
+= sizeof (UINT32
);
1307 Size
-= sizeof (UINT32
);
1308 Buffer
= (UINT32
*)Buffer
+ 1;
1311 if (Size
>= sizeof (UINT16
)) {
1313 // Read the last remaining word if exist
1315 WriteUnaligned16 (Buffer
, PciRead16 (StartAddress
));
1316 StartAddress
+= sizeof (UINT16
);
1317 Size
-= sizeof (UINT16
);
1318 Buffer
= (UINT16
*)Buffer
+ 1;
1321 if (Size
>= sizeof (UINT8
)) {
1323 // Read the last remaining byte if exist
1325 *(volatile UINT8
*)Buffer
= PciRead8 (StartAddress
);
1332 Copies the data in a caller supplied buffer to a specified range of PCI
1333 configuration space.
1335 Writes the range of PCI configuration registers specified by StartAddress and
1336 Size from the buffer specified by Buffer. This function only allows the PCI
1337 configuration registers from a single PCI function to be written. Size is
1338 returned. When possible 32-bit PCI configuration write cycles are used to
1339 write from StartAdress to StartAddress + Size. Due to alignment restrictions,
1340 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
1341 and the end of the range.
1343 If StartAddress > 0x0FFFFFFF, then ASSERT().
1344 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1345 If Size > 0 and Buffer is NULL, then ASSERT().
1347 @param StartAddress The starting address that encodes the PCI Bus, Device,
1348 Function and Register.
1349 @param Size The size in bytes of the transfer.
1350 @param Buffer The pointer to a buffer containing the data to write.
1352 @return Size written to StartAddress.
1358 IN UINTN StartAddress
,
1365 ASSERT_INVALID_PCI_ADDRESS (StartAddress
, 0);
1366 ASSERT (((StartAddress
& 0xFFF) + Size
) <= 0x1000);
1372 ASSERT (Buffer
!= NULL
);
1375 // Save Size for return
1379 if ((StartAddress
& BIT0
) != 0) {
1381 // Write a byte if StartAddress is byte aligned
1383 PciWrite8 (StartAddress
, *(UINT8
*)Buffer
);
1384 StartAddress
+= sizeof (UINT8
);
1385 Size
-= sizeof (UINT8
);
1386 Buffer
= (UINT8
*)Buffer
+ 1;
1389 if (Size
>= sizeof (UINT16
) && (StartAddress
& BIT1
) != 0) {
1391 // Write a word if StartAddress is word aligned
1393 PciWrite16 (StartAddress
, ReadUnaligned16 (Buffer
));
1394 StartAddress
+= sizeof (UINT16
);
1395 Size
-= sizeof (UINT16
);
1396 Buffer
= (UINT16
*)Buffer
+ 1;
1399 while (Size
>= sizeof (UINT32
)) {
1401 // Write as many double words as possible
1403 PciWrite32 (StartAddress
, ReadUnaligned32 (Buffer
));
1404 StartAddress
+= sizeof (UINT32
);
1405 Size
-= sizeof (UINT32
);
1406 Buffer
= (UINT32
*)Buffer
+ 1;
1409 if (Size
>= sizeof (UINT16
)) {
1411 // Write the last remaining word if exist
1413 PciWrite16 (StartAddress
, ReadUnaligned16 (Buffer
));
1414 StartAddress
+= sizeof (UINT16
);
1415 Size
-= sizeof (UINT16
);
1416 Buffer
= (UINT16
*)Buffer
+ 1;
1419 if (Size
>= sizeof (UINT8
)) {
1421 // Write the last remaining byte if exist
1423 PciWrite8 (StartAddress
, *(UINT8
*)Buffer
);