2 Main SAL API's defined in SAL 3.0 specification.
4 Copyright (c) 2006, Intel Corporation
5 All rights reserved. This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
22 // Table 2-2 of Intel Itanium Processor Family System Abstraction Layer Specification December 2003
24 #define EFI_SAL_FIT_FIT_HEADER_TYPE 0x00
25 #define EFI_SAL_FIT_PAL_B_TYPE 0x01
27 // type from 0x02 to 0x0E is reserved.
29 #define EFI_SAL_FIT_PAL_A_TYPE 0x0F
31 // OEM-defined type range is from 0x10 to 0x7E. Here we defined the PEI_CORE type as 0x10
33 #define EFI_SAL_FIT_PEI_CORE_TYPE 0x10
34 #define EFI_SAL_FIT_UNUSED_TYPE 0x7F
39 typedef UINTN EFI_SAL_STATUS
;
41 #define EFI_SAL_SUCCESS ((EFI_SAL_STATUS) 0)
42 #define EFI_SAL_MORE_RECORDS ((EFI_SAL_STATUS) 3)
43 #define EFI_SAL_NOT_IMPLEMENTED ((EFI_SAL_STATUS) - 1)
44 #define EFI_SAL_INVALID_ARGUMENT ((EFI_SAL_STATUS) - 2)
45 #define EFI_SAL_ERROR ((EFI_SAL_STATUS) - 3)
46 #define EFI_SAL_VIRTUAL_ADDRESS_ERROR ((EFI_SAL_STATUS) - 4)
47 #define EFI_SAL_NO_INFORMATION ((EFI_SAL_STATUS) - 5)
48 #define EFI_SAL_NOT_ENOUGH_SCRATCH ((EFI_SAL_STATUS) - 9)
51 // Return values from SAL
54 EFI_SAL_STATUS Status
; // register r8
61 // Delivery Mode of IPF CPU.
64 EFI_DELIVERY_MODE_INT
,
65 EFI_DELIVERY_MODE_MPreserved1
,
66 EFI_DELIVERY_MODE_PMI
,
67 EFI_DELIVERY_MODE_MPreserved2
,
68 EFI_DELIVERY_MODE_NMI
,
69 EFI_DELIVERY_MODE_INIT
,
70 EFI_DELIVERY_MODE_MPreserved3
,
71 EFI_DELIVERY_MODE_ExtINT
74 typedef SAL_RETURN_REGS (EFIAPI
*SAL_PROC
)
87 // SAL Procedure FunctionId definition
89 #define EFI_SAL_SET_VECTORS 0x01000000
90 #define EFI_SAL_GET_STATE_INFO 0x01000001
91 #define EFI_SAL_GET_STATE_INFO_SIZE 0x01000002
92 #define EFI_SAL_CLEAR_STATE_INFO 0x01000003
93 #define EFI_SAL_MC_RENDEZ 0x01000004
94 #define EFI_SAL_MC_SET_PARAMS 0x01000005
95 #define EFI_SAL_REGISTER_PHYSICAL_ADDR 0x01000006
96 #define EFI_SAL_CACHE_FLUSH 0x01000008
97 #define EFI_SAL_CACHE_INIT 0x01000009
98 #define EFI_SAL_PCI_CONFIG_READ 0x01000010
99 #define EFI_SAL_PCI_CONFIG_WRITE 0x01000011
100 #define EFI_SAL_FREQ_BASE 0x01000012
101 #define EFI_SAL_UPDATE_PAL 0x01000020
103 #define EFI_SAL_FUNCTION_ID_MASK 0x0000ffff
104 #define EFI_SAL_MAX_SAL_FUNCTION_ID 0x00000021
107 // SAL Procedure parameter definitions
108 // Not much point in using typedefs or enums because all params
109 // are UINT64 and the entry point is common
111 // EFI_SAL_SET_VECTORS
113 #define EFI_SAL_SET_MCA_VECTOR 0x0
114 #define EFI_SAL_SET_INIT_VECTOR 0x1
115 #define EFI_SAL_SET_BOOT_RENDEZ_VECTOR 0x2
119 UINT64 ChecksumValid
: 1;
120 UINT64 Reserved1
: 7;
121 UINT64 ByteChecksum
: 8;
122 UINT64 Reserved2
: 16;
123 } SAL_SET_VECTORS_CS_N
;
126 // EFI_SAL_GET_STATE_INFO, EFI_SAL_GET_STATE_INFO_SIZE,
127 // EFI_SAL_CLEAR_STATE_INFO
129 #define EFI_SAL_MCA_STATE_INFO 0x0
130 #define EFI_SAL_INIT_STATE_INFO 0x1
131 #define EFI_SAL_CMC_STATE_INFO 0x2
132 #define EFI_SAL_CP_STATE_INFO 0x3
135 // EFI_SAL_MC_SET_PARAMS
137 #define EFI_SAL_MC_SET_RENDEZ_PARAM 0x1
138 #define EFI_SAL_MC_SET_WAKEUP_PARAM 0x2
139 #define EFI_SAL_MC_SET_CPE_PARAM 0x3
141 #define EFI_SAL_MC_SET_INTR_PARAM 0x1
142 #define EFI_SAL_MC_SET_MEM_PARAM 0x2
145 // EFI_SAL_REGISTER_PAL_PHYSICAL_ADDR
147 #define EFI_SAL_REGISTER_PAL_ADDR 0x0
150 // EFI_SAL_CACHE_FLUSH
152 #define EFI_SAL_FLUSH_I_CACHE 0x01
153 #define EFI_SAL_FLUSH_D_CACHE 0x02
154 #define EFI_SAL_FLUSH_BOTH_CACHE 0x03
155 #define EFI_SAL_FLUSH_MAKE_COHERENT 0x04
158 // EFI_SAL_PCI_CONFIG_READ, EFI_SAL_PCI_CONFIG_WRITE
160 #define EFI_SAL_PCI_CONFIG_ONE_BYTE 0x1
161 #define EFI_SAL_PCI_CONFIG_TWO_BYTES 0x2
162 #define EFI_SAL_PCI_CONFIG_FOUR_BYTES 0x4
170 UINT64 Reserved
: 32;
176 #define EFI_SAL_CPU_INPUT_FREQ_BASE 0x0
177 #define EFI_SAL_PLATFORM_IT_FREQ_BASE 0x1
178 #define EFI_SAL_PLATFORM_RTC_FREQ_BASE 0x2
181 // EFI_SAL_UPDATE_PAL
183 #define EFI_SAL_UPDATE_BAD_PAL_VERSION ((UINT64) -1)
184 #define EFI_SAL_UPDATE_PAL_AUTH_FAIL ((UINT64) -2)
185 #define EFI_SAL_UPDATE_PAL_BAD_TYPE ((UINT64) -3)
186 #define EFI_SAL_UPDATE_PAL_READONLY ((UINT64) -4)
187 #define EFI_SAL_UPDATE_PAL_WRITE_FAIL ((UINT64) -10)
188 #define EFI_SAL_UPDATE_PAL_ERASE_FAIL ((UINT64) -11)
189 #define EFI_SAL_UPDATE_PAL_READ_FAIL ((UINT64) -12)
190 #define EFI_SAL_UPDATE_PAL_CANT_FIT ((UINT64) -13)
199 } SAL_UPDATE_PAL_DATA_BLOCK
;
201 typedef struct _SAL_UPDATE_PAL_INFO_BLOCK
{
202 struct _SAL_UPDATE_PAL_INFO_BLOCK
*Next
;
203 struct SAL_UPDATE_PAL_DATA_BLOCK
*DataBlock
;
206 } SAL_UPDATE_PAL_INFO_BLOCK
;
209 // SAL System Table Definitions
224 } SAL_SYSTEM_TABLE_HEADER
;
227 #define EFI_SAL_ST_HEADER_SIGNATURE "SST_"
228 #define EFI_SAL_REVISION 0x0300
232 #define EFI_SAL_ST_ENTRY_POINT 0
233 #define EFI_SAL_ST_MEMORY_DESCRIPTOR 1
234 #define EFI_SAL_ST_PLATFORM_FEATURES 2
235 #define EFI_SAL_ST_TR_USAGE 3
236 #define EFI_SAL_ST_PTC 4
237 #define EFI_SAL_ST_AP_WAKEUP 5
241 UINT8 Type
; // Type == 0
245 UINT64 SalGlobalDataPointer
;
247 } SAL_ST_ENTRY_POINT_DESCRIPTOR
;
250 // Not needed for Itanium-based OS boot
253 UINT8 Type
; // Type == 1
254 UINT8 NeedVirtualRegistration
;
255 UINT8 MemoryAttributes
;
256 UINT8 PageAccessRights
;
257 UINT8 SupportedAttributes
;
261 UINT64 PhysicalMemoryAddress
;
265 } SAL_ST_MEMORY_DESCRIPTOR_ENTRY
;
271 #define SAL_MDT_ATTRIB_WB 0x00
273 // #define SAL_MDT_ATTRIB_UC 0x02
275 #define SAL_MDT_ATTRIB_UC 0x04
276 #define SAL_MDT_ATTRIB_UCE 0x05
277 #define SAL_MDT_ATTRIB_WC 0x06
280 // Supported memory Attributes
282 #define SAL_MDT_SUPPORT_WB 0x1
283 #define SAL_MDT_SUPPORT_UC 0x2
284 #define SAL_MDT_SUPPORT_UCE 0x4
285 #define SAL_MDT_SUPPORT_WC 0x8
288 // Virtual address registration
290 #define SAL_MDT_NO_VA 0x00
291 #define SAL_MDT_NEED_VA 0x01
295 #define SAL_REGULAR_MEMORY 0x0000
296 #define SAL_MMIO_MAPPING 0x0001
297 #define SAL_SAPIC_IPI_BLOCK 0x0002
298 #define SAL_IO_PORT_MAPPING 0x0003
299 #define SAL_FIRMWARE_MEMORY 0x0004
300 #define SAL_BLACK_HOLE 0x000A
304 #define SAL_MDT_USAGE_UNSPECIFIED 0x00
305 #define SAL_PAL_CODE 0x01
306 #define SAL_BOOTSERVICE_CODE 0x02
307 #define SAL_BOOTSERVICE_DATA 0x03
308 #define SAL_RUNTIMESERVICE_CODE 0x04
309 #define SAL_RUNTIMESERVICE_DATA 0x05
310 #define SAL_IA32_OPTIONROM 0x06
311 #define SAL_IA32_SYSTEMROM 0x07
312 #define SAL_PMI_CODE 0x0a
313 #define SAL_PMI_DATA 0x0b
317 UINT8 Type
; // Type == 2
318 UINT8 PlatformFeatures
;
320 } SAL_ST_PLATFORM_FEATURES
;
323 #define SAL_PLAT_FEAT_BUS_LOCK 0x01
324 #define SAL_PLAT_FEAT_PLAT_IPI_HINT 0x02
325 #define SAL_PLAT_FEAT_PROC_IPI_HINT 0x04
329 UINT8 Type
; // Type == 3
333 UINT64 VirtualAddress
;
334 UINT64 EncodedPageSize
;
336 } SAL_ST_TR_DECRIPTOR
;
339 #define EFI_SAL_ST_TR_USAGE_INSTRUCTION 00
340 #define EFI_SAL_ST_TR_USAGE_DATA 01
344 UINT64 NumberOfProcessors
;
345 UINT64 LocalIDRegister
;
346 } SAL_COHERENCE_DOMAIN_INFO
;
351 UINT8 Type
; // Type == 4
353 UINT32 NumberOfDomains
;
354 SAL_COHERENCE_DOMAIN_INFO
*DomainInformation
;
355 } SAL_ST_CACHE_COHERENCE_DECRIPTOR
;
360 UINT8 Type
; // Type == 5
363 UINT64 ExternalInterruptVector
;
364 } SAL_ST_AP_WAKEUP_DECRIPTOR
;
369 #define EFI_SAL_FIT_ENTRY_PTR (0x100000000 - 32) // 4GB - 24
370 #define EFI_SAL_FIT_PALA_ENTRY (0x100000000 - 48) // 4GB - 32
371 #define EFI_SAL_FIT_PALB_TYPE 01
379 UINT8 CheckSumValid
: 1;
384 // SAL Common Record Header
406 UINT8 ValidationBits
;
408 SAL_TIME_STAMP TimeStamp
;
409 UINT8 OemPlatformId
[16];
415 UINT8 ErrorRecoveryInfo
;
417 UINT32 SectionLength
;
421 // SAL Processor Record
423 #define SAL_PROCESSOR_ERROR_RECORD_INFO \
425 0xe429faf1, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
428 #define CHECK_INFO_VALID_BIT_MASK 0x1
429 #define REQUESTOR_ID_VALID_BIT_MASK 0x2
430 #define RESPONDER_ID_VALID_BIT_MASK 0x4
431 #define TARGER_ID_VALID_BIT_MASK 0x8
432 #define PRECISE_IP_VALID_BIT_MASK 0x10
435 UINT64 InfoValid
: 1;
437 UINT64 RespValid
: 1;
438 UINT64 TargetValid
: 1;
440 UINT64 Reserved
: 59;
458 #define MIN_STATE_VALID_BIT_MASK 0x1
459 #define BR_VALID_BIT_MASK 0x2
460 #define CR_VALID_BIT_MASK 0x4
461 #define AR_VALID_BIT_MASK 0x8
462 #define RR_VALID_BIT_MASK 0x10
463 #define FR_VALID_BIT_MASK 0x20
466 UINT64 ValidFieldBits
;
467 UINT8 MinStateInfo
[1024];
475 #define PROC_ERROR_MAP_VALID_BIT_MASK 0x1
476 #define PROC_STATE_PARAMETER_VALID_BIT_MASK 0x2
477 #define PROC_CR_LID_VALID_BIT_MASK 0x4
478 #define PROC_STATIC_STRUCT_VALID_BIT_MASK 0x8
479 #define CPU_INFO_VALID_BIT_MASK 0x1000000
482 SAL_SEC_HEADER SectionHeader
;
483 UINT64 ValidationBits
;
485 UINT64 ProcStateParameter
;
487 MOD_ERROR_INFO CacheError
[15];
488 MOD_ERROR_INFO TlbError
[15];
489 MOD_ERROR_INFO BusError
[15];
490 MOD_ERROR_INFO RegFileCheck
[15];
491 MOD_ERROR_INFO MsCheck
[15];
493 PSI_STATIC_STRUCT PsiValidData
;
494 } SAL_PROCESSOR_ERROR_RECORD
;
497 // Sal Platform memory Error Record
499 #define SAL_MEMORY_ERROR_RECORD_INFO \
501 0xe429faf2, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
504 #define MEMORY_ERROR_STATUS_VALID_BIT_MASK 0x1
505 #define MEMORY_PHYSICAL_ADDRESS_VALID_BIT_MASK 0x2
506 #define MEMORY_ADDR_BIT_MASK 0x4
507 #define MEMORY_NODE_VALID_BIT_MASK 0x8
508 #define MEMORY_CARD_VALID_BIT_MASK 0x10
509 #define MEMORY_MODULE_VALID_BIT_MASK 0x20
510 #define MEMORY_BANK_VALID_BIT_MASK 0x40
511 #define MEMORY_DEVICE_VALID_BIT_MASK 0x80
512 #define MEMORY_ROW_VALID_BIT_MASK 0x100
513 #define MEMORY_COLUMN_VALID_BIT_MASK 0x200
514 #define MEMORY_BIT_POSITION_VALID_BIT_MASK 0x400
515 #define MEMORY_PLATFORM_REQUESTOR_ID_VALID_BIT_MASK 0x800
516 #define MEMORY_PLATFORM_RESPONDER_ID_VALID_BIT_MASK 0x1000
517 #define MEMORY_PLATFORM_TARGET_VALID_BIT_MASK 0x2000
518 #define MEMORY_PLATFORM_BUS_SPECIFIC_DATA_VALID_BIT_MASK 0x4000
519 #define MEMORY_PLATFORM_OEM_ID_VALID_BIT_MASK 0x8000
520 #define MEMORY_PLATFORM_OEM_DATA_STRUCT_VALID_BIT_MASK 0x10000
523 SAL_SEC_HEADER SectionHeader
;
524 UINT64 ValidationBits
;
525 UINT64 MemErrorStatus
;
526 UINT64 MemPhysicalAddress
;
527 UINT64 MemPhysicalAddressMask
;
535 UINT16 MemBitPosition
;
536 UINT64 ModRequestorId
;
537 UINT64 ModResponderId
;
539 UINT64 BusSpecificData
;
540 UINT8 MemPlatformOemId
[16];
541 } SAL_MEMORY_ERROR_RECORD
;
546 #define SAL_PCI_BUS_ERROR_RECORD_INFO \
548 0xe429faf4, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
551 #define PCI_BUS_ERROR_STATUS_VALID_BIT_MASK 0x1
552 #define PCI_BUS_ERROR_TYPE_VALID_BIT_MASK 0x2
553 #define PCI_BUS_ID_VALID_BIT_MASK 0x4
554 #define PCI_BUS_ADDRESS_VALID_BIT_MASK 0x8
555 #define PCI_BUS_DATA_VALID_BIT_MASK 0x10
556 #define PCI_BUS_CMD_VALID_BIT_MASK 0x20
557 #define PCI_BUS_REQUESTOR_ID_VALID_BIT_MASK 0x40
558 #define PCI_BUS_RESPONDER_ID_VALID_BIT_MASK 0x80
559 #define PCI_BUS_TARGET_VALID_BIT_MASK 0x100
560 #define PCI_BUS_OEM_ID_VALID_BIT_MASK 0x200
561 #define PCI_BUS_OEM_DATA_STRUCT_VALID_BIT_MASK 0x400
569 SAL_SEC_HEADER SectionHeader
;
570 UINT64 ValidationBits
;
571 UINT64 PciBusErrorStatus
;
572 UINT16 PciBusErrorType
;
575 UINT64 PciBusAddress
;
577 UINT64 PciBusCommand
;
578 UINT64 PciBusRequestorId
;
579 UINT64 PciBusResponderId
;
580 UINT64 PciBusTargetId
;
581 UINT8 PciBusOemId
[16];
582 } SAL_PCI_BUS_ERROR_RECORD
;
585 // PCI Component Errors
587 #define SAL_PCI_COMP_ERROR_RECORD_INFO \
589 0xe429faf6, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
592 #define PCI_COMP_ERROR_STATUS_VALID_BIT_MASK 0x1
593 #define PCI_COMP_INFO_VALID_BIT_MASK 0x2
594 #define PCI_COMP_MEM_NUM_VALID_BIT_MASK 0x4
595 #define PCI_COMP_IO_NUM_VALID_BIT_MASK 0x8
596 #define PCI_COMP_REG_DATA_PAIR_VALID_BIT_MASK 0x10
597 #define PCI_COMP_OEM_DATA_STRUCT_VALID_BIT_MASK 0x20
603 UINT8 FunctionNumber
;
611 SAL_SEC_HEADER SectionHeader
;
612 UINT64 ValidationBits
;
613 UINT64 PciComponentErrorStatus
;
614 PCI_COMP_INFO PciComponentInfo
;
615 UINT32 PciComponentMemNum
;
616 UINT32 PciComponentIoNum
;
617 UINT8 PciBusOemId
[16];
618 } SAL_PCI_COMPONENT_ERROR_RECORD
;
621 // Sal Device Errors Info.
623 #define SAL_DEVICE_ERROR_RECORD_INFO \
625 0xe429faf3, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
628 #define SEL_RECORD_ID_VALID_BIT_MASK 0x1;
629 #define SEL_RECORD_TYPE_VALID_BIT_MASK 0x2;
630 #define SEL_GENERATOR_ID_VALID_BIT_MASK 0x4;
631 #define SEL_EVM_REV_VALID_BIT_MASK 0x8;
632 #define SEL_SENSOR_TYPE_VALID_BIT_MASK 0x10;
633 #define SEL_SENSOR_NUM_VALID_BIT_MASK 0x20;
634 #define SEL_EVENT_DIR_TYPE_VALID_BIT_MASK 0x40;
635 #define SEL_EVENT_DATA1_VALID_BIT_MASK 0x80;
636 #define SEL_EVENT_DATA2_VALID_BIT_MASK 0x100;
637 #define SEL_EVENT_DATA3_VALID_BIT_MASK 0x200;
640 SAL_SEC_HEADER SectionHeader
;
641 UINT64 ValidationBits
;
653 } SAL_DEVICE_ERROR_RECORD
;
656 // Sal SMBIOS Device Errors Info.
658 #define SAL_SMBIOS_ERROR_RECORD_INFO \
660 0xe429faf5, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
663 #define SMBIOS_EVENT_TYPE_VALID_BIT_MASK 0x1
664 #define SMBIOS_LENGTH_VALID_BIT_MASK 0x2
665 #define SMBIOS_TIME_STAMP_VALID_BIT_MASK 0x4
666 #define SMBIOS_DATA_VALID_BIT_MASK 0x8
669 SAL_SEC_HEADER SectionHeader
;
670 UINT64 ValidationBits
;
671 UINT8 SmbiosEventType
;
673 UINT8 SmbiosBcdTimeStamp
[6];
674 } SAL_SMBIOS_DEVICE_ERROR_RECORD
;
677 // Sal Platform Specific Errors Info.
679 #define SAL_PLATFORM_ERROR_RECORD_INFO \
681 0xe429faf7, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \
684 #define PLATFORM_ERROR_STATUS_VALID_BIT_MASK 0x1
685 #define PLATFORM_REQUESTOR_ID_VALID_BIT_MASK 0x2
686 #define PLATFORM_RESPONDER_ID_VALID_BIT_MASK 0x4
687 #define PLATFORM_TARGET_VALID_BIT_MASK 0x8
688 #define PLATFORM_SPECIFIC_DATA_VALID_BIT_MASK 0x10
689 #define PLATFORM_OEM_ID_VALID_BIT_MASK 0x20
690 #define PLATFORM_OEM_DATA_STRUCT_VALID_BIT_MASK 0x40
691 #define PLATFORM_OEM_DEVICE_PATH_VALID_BIT_MASK 0x80
694 SAL_SEC_HEADER SectionHeader
;
695 UINT64 ValidationBits
;
696 UINT64 PlatformErrorStatus
;
697 UINT64 PlatformRequestorId
;
698 UINT64 PlatformResponderId
;
699 UINT64 PlatformTargetId
;
700 UINT64 PlatformBusSpecificData
;
701 UINT8 OemComponentId
[16];
702 } SAL_PLATFORM_SPECIFIC_ERROR_RECORD
;
705 // Union of all the possible Sal Record Types
708 SAL_RECORD_HEADER
*RecordHeader
;
709 SAL_PROCESSOR_ERROR_RECORD
*SalProcessorRecord
;
710 SAL_PCI_BUS_ERROR_RECORD
*SalPciBusRecord
;
711 SAL_PCI_COMPONENT_ERROR_RECORD
*SalPciComponentRecord
;
712 SAL_DEVICE_ERROR_RECORD
*ImpiRecord
;
713 SAL_SMBIOS_DEVICE_ERROR_RECORD
*SmbiosRecord
;
714 SAL_PLATFORM_SPECIFIC_ERROR_RECORD
*PlatformRecord
;
715 SAL_MEMORY_ERROR_RECORD
*MemoryRecord
;
717 } SAL_ERROR_RECORDS_POINTERS
;