2 Abstractions for simple OMAP DMA channel.
5 Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
7 This program and the accompanying materials
8 are licensed and made available under the terms and conditions of the BSD License
9 which accompanies this distribution. The full text of the license may be found at
10 http://opensource.org/licenses/bsd-license.php
12 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
13 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 #include <Library/DebugLib.h>
19 #include <Library/OmapDmaLib.h>
20 #include <Library/IoLib.h>
21 #include <Library/BaseMemoryLib.h>
22 #include <Omap3530/Omap3530.h>
26 Configure OMAP DMA Channel
28 @param Channel DMA Channel to configure
29 @param Dma4 Pointer to structure used to initialize DMA registers for the Channel
31 @retval EFI_SUCCESS The range was mapped for the returned NumberOfBytes.
32 @retval EFI_INVALID_PARAMETER Channel is not valid
33 @retval EFI_DEVICE_ERROR The system hardware could not map the requested information.
46 if (Channel
> DMA4_MAX_CHANNEL
) {
47 return EFI_INVALID_PARAMETER
;
50 /* 1) Configure the transfer parameters in the logical DMA registers */
51 /*-------------------------------------------------------------------*/
53 /* a) Set the data type CSDP[1:0], the Read/Write Port access type
54 CSDP[8:7]/[15:14], the Source/dest endianism CSDP[21]/CSDP[19],
55 write mode CSDP[17:16], source/dest packed or nonpacked CSDP[6]/CSDP[13] */
58 RegVal
= MmioRead32 (DMA4_CSDP (Channel
));
61 RegVal
= ((RegVal
& ~ 0x3) | DMA4
->DataType
);
62 RegVal
= ((RegVal
& ~(0x3 << 7)) | (DMA4
->ReadPortAccessType
<< 7));
63 RegVal
= ((RegVal
& ~(0x3 << 14)) | (DMA4
->WritePortAccessType
<< 14));
64 RegVal
= ((RegVal
& ~(0x1 << 21)) | (DMA4
->SourceEndiansim
<< 21));
65 RegVal
= ((RegVal
& ~(0x1 << 19)) | (DMA4
->DestinationEndianism
<< 19));
66 RegVal
= ((RegVal
& ~(0x3 << 16)) | (DMA4
->WriteMode
<< 16));
67 RegVal
= ((RegVal
& ~(0x1 << 6)) | (DMA4
->SourcePacked
<< 6));
68 RegVal
= ((RegVal
& ~(0x1 << 13)) | (DMA4
->DestinationPacked
<< 13));
70 MmioWrite32 (DMA4_CSDP (Channel
), RegVal
);
72 /* b) Set the number of element per frame CEN[23:0]*/
73 MmioWrite32 (DMA4_CEN (Channel
), DMA4
->NumberOfElementPerFrame
);
75 /* c) Set the number of frame per block CFN[15:0]*/
76 MmioWrite32 (DMA4_CFN (Channel
), DMA4
->NumberOfFramePerTransferBlock
);
78 /* d) Set the Source/dest start address index CSSA[31:0]/CDSA[31:0]*/
79 MmioWrite32 (DMA4_CSSA (Channel
), DMA4
->SourceStartAddress
);
80 MmioWrite32 (DMA4_CDSA (Channel
), DMA4
->DestinationStartAddress
);
82 /* e) Set the Read Port addressing mode CCR[13:12], the Write Port addressing mode CCR[15:14],
83 read/write priority CCR[6]/CCR[26]
84 I changed LCH CCR[20:19]=00 and CCR[4:0]=00000 to
85 LCH CCR[20:19]= DMA4->WriteRequestNumber and CCR[4:0]=DMA4->ReadRequestNumber
89 RegVal
= MmioRead32 (DMA4_CCR (Channel
));
92 RegVal
= ((RegVal
& ~0x1f) | DMA4
->ReadRequestNumber
);
93 RegVal
= ((RegVal
& ~(BIT20
| BIT19
)) | DMA4
->WriteRequestNumber
<< 19);
94 RegVal
= ((RegVal
& ~(0x3 << 12)) | (DMA4
->ReadPortAccessMode
<< 12));
95 RegVal
= ((RegVal
& ~(0x3 << 14)) | (DMA4
->WritePortAccessMode
<< 14));
96 RegVal
= ((RegVal
& ~(0x1 << 6)) | (DMA4
->ReadPriority
<< 6));
97 RegVal
= ((RegVal
& ~(0x1 << 26)) | (DMA4
->WritePriority
<< 26));
100 MmioWrite32 (DMA4_CCR (Channel
), RegVal
);
102 /* f)- Set the source element index CSEI[15:0]*/
103 MmioWrite32 (DMA4_CSEI (Channel
), DMA4
->SourceElementIndex
);
105 /* - Set the source frame index CSFI[15:0]*/
106 MmioWrite32 (DMA4_CSFI (Channel
), DMA4
->SourceFrameIndex
);
109 /* - Set the destination element index CDEI[15:0]*/
110 MmioWrite32 (DMA4_CDEI (Channel
), DMA4
->DestinationElementIndex
);
112 /* - Set the destination frame index CDFI[31:0]*/
113 MmioWrite32 (DMA4_CDFI (Channel
), DMA4
->DestinationFrameIndex
);
115 MmioWrite32 (DMA4_CDFI (Channel
), DMA4
->DestinationFrameIndex
);
117 // Enable all the status bits since we are polling
118 MmioWrite32 (DMA4_CICR (Channel
), DMA4_CICR_ENABLE_ALL
);
119 MmioWrite32 (DMA4_CSR (Channel
), DMA4_CSR_RESET
);
121 /* 2) Start the DMA transfer by Setting the enable bit CCR[7]=1 */
122 /*--------------------------------------------------------------*/
124 MmioOr32 (DMA4_CCR(Channel
), DMA4_CCR_ENABLE
); //Launch transfer
130 Turn of DMA channel configured by EnableDma().
132 @param Channel DMA Channel to configure
133 @param SuccesMask Bits in DMA4_CSR register indicate EFI_SUCCESS
134 @param ErrorMask Bits in DMA4_CSR register indicate EFI_DEVICE_ERROR
136 @retval EFI_SUCCESS DMA hardware disabled
137 @retval EFI_INVALID_PARAMETER Channel is not valid
138 @retval EFI_DEVICE_ERROR The system hardware could not map the requested information.
145 IN UINT32 SuccessMask
,
149 EFI_STATUS Status
= EFI_SUCCESS
;
153 if (Channel
> DMA4_MAX_CHANNEL
) {
154 return EFI_INVALID_PARAMETER
;
158 Reg
= MmioRead32 (DMA4_CSR(Channel
));
159 if ((Reg
& ErrorMask
) != 0) {
160 Status
= EFI_DEVICE_ERROR
;
161 DEBUG ((EFI_D_ERROR
, "DMA Error (%d) %x\n", Channel
, Reg
));
164 } while ((Reg
& SuccessMask
) != SuccessMask
);
167 // Disable all status bits and clear them
168 MmioWrite32 (DMA4_CICR (Channel
), 0);
169 MmioWrite32 (DMA4_CSR (Channel
), DMA4_CSR_RESET
);
171 MmioAnd32 (DMA4_CCR(0), ~(DMA4_CCR_ENABLE
| DMA4_CCR_RD_ACTIVE
| DMA4_CCR_WR_ACTIVE
));