2 Memory Detection for Virtual Machines.
4 Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
5 This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
20 // The package level header files this module uses
22 #include <IndustryStandard/E820.h>
23 #include <IndustryStandard/Q35MchIch9.h>
27 // The Library classes this module consumes
29 #include <Library/BaseLib.h>
30 #include <Library/BaseMemoryLib.h>
31 #include <Library/DebugLib.h>
32 #include <Library/HobLib.h>
33 #include <Library/IoLib.h>
34 #include <Library/PcdLib.h>
35 #include <Library/PciLib.h>
36 #include <Library/PeimEntryPoint.h>
37 #include <Library/ResourcePublicationLib.h>
38 #include <Library/MtrrLib.h>
39 #include <Library/QemuFwCfgLib.h>
44 UINT8 mPhysMemAddressWidth
;
46 STATIC UINT32 mS3AcpiReservedMemoryBase
;
47 STATIC UINT32 mS3AcpiReservedMemorySize
;
49 STATIC UINT16 mQ35TsegMbytes
;
52 Q35TsegMbytesInitialization (
56 UINT16 ExtendedTsegMbytes
;
57 RETURN_STATUS PcdStatus
;
59 if (mHostBridgeDevId
!= INTEL_Q35_MCH_DEVICE_ID
) {
62 "%a: no TSEG (SMRAM) on host bridge DID=0x%04x; "
63 "only DID=0x%04x (Q35) is supported\n",
66 INTEL_Q35_MCH_DEVICE_ID
73 // Check if QEMU offers an extended TSEG.
75 // This can be seen from writing MCH_EXT_TSEG_MB_QUERY to the MCH_EXT_TSEG_MB
76 // register, and reading back the register.
78 // On a QEMU machine type that does not offer an extended TSEG, the initial
79 // write overwrites whatever value a malicious guest OS may have placed in
80 // the (unimplemented) register, before entering S3 or rebooting.
81 // Subsequently, the read returns MCH_EXT_TSEG_MB_QUERY unchanged.
83 // On a QEMU machine type that offers an extended TSEG, the initial write
84 // triggers an update to the register. Subsequently, the value read back
85 // (which is guaranteed to differ from MCH_EXT_TSEG_MB_QUERY) tells us the
86 // number of megabytes.
88 PciWrite16 (DRAMC_REGISTER_Q35 (MCH_EXT_TSEG_MB
), MCH_EXT_TSEG_MB_QUERY
);
89 ExtendedTsegMbytes
= PciRead16 (DRAMC_REGISTER_Q35 (MCH_EXT_TSEG_MB
));
90 if (ExtendedTsegMbytes
== MCH_EXT_TSEG_MB_QUERY
) {
91 mQ35TsegMbytes
= PcdGet16 (PcdQ35TsegMbytes
);
97 "%a: QEMU offers an extended TSEG (%d MB)\n",
101 PcdStatus
= PcdSet16S (PcdQ35TsegMbytes
, ExtendedTsegMbytes
);
102 ASSERT_RETURN_ERROR (PcdStatus
);
103 mQ35TsegMbytes
= ExtendedTsegMbytes
;
108 Iterate over the RAM entries in QEMU's fw_cfg E820 RAM map that start outside
109 of the 32-bit address range.
111 Find the highest exclusive >=4GB RAM address, or produce memory resource
112 descriptor HOBs for RAM entries that start at or above 4GB.
114 @param[out] MaxAddress If MaxAddress is NULL, then ScanOrAdd64BitE820Ram()
115 produces memory resource descriptor HOBs for RAM
116 entries that start at or above 4GB.
118 Otherwise, MaxAddress holds the highest exclusive
119 >=4GB RAM address on output. If QEMU's fw_cfg E820
120 RAM map contains no RAM entry that starts outside of
121 the 32-bit address range, then MaxAddress is exactly
124 @retval EFI_SUCCESS The fw_cfg E820 RAM map was found and processed.
126 @retval EFI_PROTOCOL_ERROR The RAM map was found, but its size wasn't a
127 whole multiple of sizeof(EFI_E820_ENTRY64). No
128 RAM entry was processed.
130 @return Error codes from QemuFwCfgFindFile(). No RAM
135 ScanOrAdd64BitE820Ram (
136 OUT UINT64
*MaxAddress OPTIONAL
140 FIRMWARE_CONFIG_ITEM FwCfgItem
;
142 EFI_E820_ENTRY64 E820Entry
;
145 Status
= QemuFwCfgFindFile ("etc/e820", &FwCfgItem
, &FwCfgSize
);
146 if (EFI_ERROR (Status
)) {
149 if (FwCfgSize
% sizeof E820Entry
!= 0) {
150 return EFI_PROTOCOL_ERROR
;
153 if (MaxAddress
!= NULL
) {
154 *MaxAddress
= BASE_4GB
;
157 QemuFwCfgSelectItem (FwCfgItem
);
158 for (Processed
= 0; Processed
< FwCfgSize
; Processed
+= sizeof E820Entry
) {
159 QemuFwCfgReadBytes (sizeof E820Entry
, &E820Entry
);
162 "%a: Base=0x%Lx Length=0x%Lx Type=%u\n",
168 if (E820Entry
.Type
== EfiAcpiAddressRangeMemory
&&
169 E820Entry
.BaseAddr
>= BASE_4GB
) {
170 if (MaxAddress
== NULL
) {
175 // Round up the start address, and round down the end address.
177 Base
= ALIGN_VALUE (E820Entry
.BaseAddr
, (UINT64
)EFI_PAGE_SIZE
);
178 End
= (E820Entry
.BaseAddr
+ E820Entry
.Length
) &
179 ~(UINT64
)EFI_PAGE_MASK
;
181 AddMemoryRangeHob (Base
, End
);
184 "%a: AddMemoryRangeHob [0x%Lx, 0x%Lx)\n",
193 Candidate
= E820Entry
.BaseAddr
+ E820Entry
.Length
;
194 if (Candidate
> *MaxAddress
) {
195 *MaxAddress
= Candidate
;
198 "%a: MaxAddress=0x%Lx\n",
211 GetSystemMemorySizeBelow4gb (
219 // CMOS 0x34/0x35 specifies the system memory above 16 MB.
220 // * CMOS(0x35) is the high byte
221 // * CMOS(0x34) is the low byte
222 // * The size is specified in 64kb chunks
223 // * Since this is memory above 16MB, the 16MB must be added
224 // into the calculation to get the total memory size.
227 Cmos0x34
= (UINT8
) CmosRead8 (0x34);
228 Cmos0x35
= (UINT8
) CmosRead8 (0x35);
230 return (UINT32
) (((UINTN
)((Cmos0x35
<< 8) + Cmos0x34
) << 16) + SIZE_16MB
);
236 GetSystemMemorySizeAbove4gb (
243 // CMOS 0x5b-0x5d specifies the system memory above 4GB MB.
244 // * CMOS(0x5d) is the most significant size byte
245 // * CMOS(0x5c) is the middle size byte
246 // * CMOS(0x5b) is the least significant size byte
247 // * The size is specified in 64kb chunks
251 for (CmosIndex
= 0x5d; CmosIndex
>= 0x5b; CmosIndex
--) {
252 Size
= (UINT32
) (Size
<< 8) + (UINT32
) CmosRead8 (CmosIndex
);
255 return LShiftU64 (Size
, 16);
260 Return the highest address that DXE could possibly use, plus one.
268 UINT64 FirstNonAddress
;
269 UINT64 Pci64Base
, Pci64Size
;
270 CHAR8 MbString
[7 + 1];
272 FIRMWARE_CONFIG_ITEM FwCfgItem
;
274 UINT64 HotPlugMemoryEnd
;
275 RETURN_STATUS PcdStatus
;
278 // set FirstNonAddress to suppress incorrect compiler/analyzer warnings
283 // If QEMU presents an E820 map, then get the highest exclusive >=4GB RAM
284 // address from it. This can express an address >= 4GB+1TB.
286 // Otherwise, get the flat size of the memory above 4GB from the CMOS (which
287 // can only express a size smaller than 1TB), and add it to 4GB.
289 Status
= ScanOrAdd64BitE820Ram (&FirstNonAddress
);
290 if (EFI_ERROR (Status
)) {
291 FirstNonAddress
= BASE_4GB
+ GetSystemMemorySizeAbove4gb ();
295 // If DXE is 32-bit, then we're done; PciBusDxe will degrade 64-bit MMIO
296 // resources to 32-bit anyway. See DegradeResource() in
297 // "PciResourceSupport.c".
300 if (!FeaturePcdGet (PcdDxeIplSwitchToLongMode
)) {
301 return FirstNonAddress
;
306 // Otherwise, in order to calculate the highest address plus one, we must
307 // consider the 64-bit PCI host aperture too. Fetch the default size.
309 Pci64Size
= PcdGet64 (PcdPciMmio64Size
);
312 // See if the user specified the number of megabytes for the 64-bit PCI host
313 // aperture. The number of non-NUL characters in MbString allows for
314 // 9,999,999 MB, which is approximately 10 TB.
316 // As signaled by the "X-" prefix, this knob is experimental, and might go
319 Status
= QemuFwCfgFindFile ("opt/ovmf/X-PciMmio64Mb", &FwCfgItem
,
321 if (!EFI_ERROR (Status
)) {
322 if (FwCfgSize
>= sizeof MbString
) {
324 "%a: ignoring malformed 64-bit PCI host aperture size from fw_cfg\n",
327 QemuFwCfgSelectItem (FwCfgItem
);
328 QemuFwCfgReadBytes (FwCfgSize
, MbString
);
329 MbString
[FwCfgSize
] = '\0';
330 Pci64Size
= LShiftU64 (AsciiStrDecimalToUint64 (MbString
), 20);
334 if (Pci64Size
== 0) {
335 if (mBootMode
!= BOOT_ON_S3_RESUME
) {
336 DEBUG ((EFI_D_INFO
, "%a: disabling 64-bit PCI host aperture\n",
338 PcdStatus
= PcdSet64S (PcdPciMmio64Size
, 0);
339 ASSERT_RETURN_ERROR (PcdStatus
);
343 // There's nothing more to do; the amount of memory above 4GB fully
344 // determines the highest address plus one. The memory hotplug area (see
345 // below) plays no role for the firmware in this case.
347 return FirstNonAddress
;
351 // The "etc/reserved-memory-end" fw_cfg file, when present, contains an
352 // absolute, exclusive end address for the memory hotplug area. This area
353 // starts right at the end of the memory above 4GB. The 64-bit PCI host
354 // aperture must be placed above it.
356 Status
= QemuFwCfgFindFile ("etc/reserved-memory-end", &FwCfgItem
,
358 if (!EFI_ERROR (Status
) && FwCfgSize
== sizeof HotPlugMemoryEnd
) {
359 QemuFwCfgSelectItem (FwCfgItem
);
360 QemuFwCfgReadBytes (FwCfgSize
, &HotPlugMemoryEnd
);
361 DEBUG ((DEBUG_VERBOSE
, "%a: HotPlugMemoryEnd=0x%Lx\n", __FUNCTION__
,
364 ASSERT (HotPlugMemoryEnd
>= FirstNonAddress
);
365 FirstNonAddress
= HotPlugMemoryEnd
;
369 // SeaBIOS aligns both boundaries of the 64-bit PCI host aperture to 1GB, so
370 // that the host can map it with 1GB hugepages. Follow suit.
372 Pci64Base
= ALIGN_VALUE (FirstNonAddress
, (UINT64
)SIZE_1GB
);
373 Pci64Size
= ALIGN_VALUE (Pci64Size
, (UINT64
)SIZE_1GB
);
376 // The 64-bit PCI host aperture should also be "naturally" aligned. The
377 // alignment is determined by rounding the size of the aperture down to the
378 // next smaller or equal power of two. That is, align the aperture by the
379 // largest BAR size that can fit into it.
381 Pci64Base
= ALIGN_VALUE (Pci64Base
, GetPowerOfTwo64 (Pci64Size
));
383 if (mBootMode
!= BOOT_ON_S3_RESUME
) {
385 // The core PciHostBridgeDxe driver will automatically add this range to
386 // the GCD memory space map through our PciHostBridgeLib instance; here we
387 // only need to set the PCDs.
389 PcdStatus
= PcdSet64S (PcdPciMmio64Base
, Pci64Base
);
390 ASSERT_RETURN_ERROR (PcdStatus
);
391 PcdStatus
= PcdSet64S (PcdPciMmio64Size
, Pci64Size
);
392 ASSERT_RETURN_ERROR (PcdStatus
);
394 DEBUG ((EFI_D_INFO
, "%a: Pci64Base=0x%Lx Pci64Size=0x%Lx\n",
395 __FUNCTION__
, Pci64Base
, Pci64Size
));
399 // The useful address space ends with the 64-bit PCI host aperture.
401 FirstNonAddress
= Pci64Base
+ Pci64Size
;
402 return FirstNonAddress
;
407 Initialize the mPhysMemAddressWidth variable, based on guest RAM size.
410 AddressWidthInitialization (
414 UINT64 FirstNonAddress
;
417 // As guest-physical memory size grows, the permanent PEI RAM requirements
418 // are dominated by the identity-mapping page tables built by the DXE IPL.
419 // The DXL IPL keys off of the physical address bits advertized in the CPU
420 // HOB. To conserve memory, we calculate the minimum address width here.
422 FirstNonAddress
= GetFirstNonAddress ();
423 mPhysMemAddressWidth
= (UINT8
)HighBitSet64 (FirstNonAddress
);
426 // If FirstNonAddress is not an integral power of two, then we need an
429 if ((FirstNonAddress
& (FirstNonAddress
- 1)) != 0) {
430 ++mPhysMemAddressWidth
;
434 // The minimum address width is 36 (covers up to and excluding 64 GB, which
435 // is the maximum for Ia32 + PAE). The theoretical architecture maximum for
436 // X64 long mode is 52 bits, but the DXE IPL clamps that down to 48 bits. We
437 // can simply assert that here, since 48 bits are good enough for 256 TB.
439 if (mPhysMemAddressWidth
<= 36) {
440 mPhysMemAddressWidth
= 36;
442 ASSERT (mPhysMemAddressWidth
<= 48);
447 Calculate the cap for the permanent PEI memory.
455 BOOLEAN Page1GSupport
;
463 // If DXE is 32-bit, then just return the traditional 64 MB cap.
466 if (!FeaturePcdGet (PcdDxeIplSwitchToLongMode
)) {
472 // Dependent on physical address width, PEI memory allocations can be
473 // dominated by the page tables built for 64-bit DXE. So we key the cap off
474 // of those. The code below is based on CreateIdentityMappingPageTables() in
475 // "MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c".
477 Page1GSupport
= FALSE
;
478 if (PcdGetBool (PcdUse1GPageTable
)) {
479 AsmCpuid (0x80000000, &RegEax
, NULL
, NULL
, NULL
);
480 if (RegEax
>= 0x80000001) {
481 AsmCpuid (0x80000001, NULL
, NULL
, NULL
, &RegEdx
);
482 if ((RegEdx
& BIT26
) != 0) {
483 Page1GSupport
= TRUE
;
488 if (mPhysMemAddressWidth
<= 39) {
490 PdpEntries
= 1 << (mPhysMemAddressWidth
- 30);
491 ASSERT (PdpEntries
<= 0x200);
493 Pml4Entries
= 1 << (mPhysMemAddressWidth
- 39);
494 ASSERT (Pml4Entries
<= 0x200);
498 TotalPages
= Page1GSupport
? Pml4Entries
+ 1 :
499 (PdpEntries
+ 1) * Pml4Entries
+ 1;
500 ASSERT (TotalPages
<= 0x40201);
503 // Add 64 MB for miscellaneous allocations. Note that for
504 // mPhysMemAddressWidth values close to 36, the cap will actually be
505 // dominated by this increment.
507 return (UINT32
)(EFI_PAGES_TO_SIZE (TotalPages
) + SIZE_64MB
);
512 Publish PEI core memory
514 @return EFI_SUCCESS The PEIM initialized successfully.
523 EFI_PHYSICAL_ADDRESS MemoryBase
;
525 UINT32 LowerMemorySize
;
528 LowerMemorySize
= GetSystemMemorySizeBelow4gb ();
529 if (FeaturePcdGet (PcdSmmSmramRequire
)) {
531 // TSEG is chipped from the end of low RAM
533 LowerMemorySize
-= mQ35TsegMbytes
* SIZE_1MB
;
537 // If S3 is supported, then the S3 permanent PEI memory is placed next,
538 // downwards. Its size is primarily dictated by CpuMpPei. The formula below
539 // is an approximation.
542 mS3AcpiReservedMemorySize
= SIZE_512KB
+
544 PcdGet32 (PcdCpuApStackSize
);
545 mS3AcpiReservedMemoryBase
= LowerMemorySize
- mS3AcpiReservedMemorySize
;
546 LowerMemorySize
= mS3AcpiReservedMemoryBase
;
549 if (mBootMode
== BOOT_ON_S3_RESUME
) {
550 MemoryBase
= mS3AcpiReservedMemoryBase
;
551 MemorySize
= mS3AcpiReservedMemorySize
;
553 PeiMemoryCap
= GetPeiMemoryCap ();
554 DEBUG ((EFI_D_INFO
, "%a: mPhysMemAddressWidth=%d PeiMemoryCap=%u KB\n",
555 __FUNCTION__
, mPhysMemAddressWidth
, PeiMemoryCap
>> 10));
558 // Determine the range of memory to use during PEI
560 // Technically we could lay the permanent PEI RAM over SEC's temporary
561 // decompression and scratch buffer even if "secure S3" is needed, since
562 // their lifetimes don't overlap. However, PeiFvInitialization() will cover
563 // RAM up to PcdOvmfDecompressionScratchEnd with an EfiACPIMemoryNVS memory
564 // allocation HOB, and other allocations served from the permanent PEI RAM
565 // shouldn't overlap with that HOB.
567 MemoryBase
= mS3Supported
&& FeaturePcdGet (PcdSmmSmramRequire
) ?
568 PcdGet32 (PcdOvmfDecompressionScratchEnd
) :
569 PcdGet32 (PcdOvmfDxeMemFvBase
) + PcdGet32 (PcdOvmfDxeMemFvSize
);
570 MemorySize
= LowerMemorySize
- MemoryBase
;
571 if (MemorySize
> PeiMemoryCap
) {
572 MemoryBase
= LowerMemorySize
- PeiMemoryCap
;
573 MemorySize
= PeiMemoryCap
;
578 // Publish this memory to the PEI Core
580 Status
= PublishSystemMemory(MemoryBase
, MemorySize
);
581 ASSERT_EFI_ERROR (Status
);
588 Peform Memory Detection for QEMU / KVM
597 UINT64 LowerMemorySize
;
598 UINT64 UpperMemorySize
;
599 MTRR_SETTINGS MtrrSettings
;
602 DEBUG ((EFI_D_INFO
, "%a called\n", __FUNCTION__
));
605 // Determine total memory size available
607 LowerMemorySize
= GetSystemMemorySizeBelow4gb ();
608 UpperMemorySize
= GetSystemMemorySizeAbove4gb ();
610 if (mBootMode
== BOOT_ON_S3_RESUME
) {
612 // Create the following memory HOB as an exception on the S3 boot path.
614 // Normally we'd create memory HOBs only on the normal boot path. However,
615 // CpuMpPei specifically needs such a low-memory HOB on the S3 path as
616 // well, for "borrowing" a subset of it temporarily, for the AP startup
619 // CpuMpPei saves the original contents of the borrowed area in permanent
620 // PEI RAM, in a backup buffer allocated with the normal PEI services.
621 // CpuMpPei restores the original contents ("returns" the borrowed area) at
622 // End-of-PEI. End-of-PEI in turn is emitted by S3Resume2Pei before
623 // transferring control to the OS's wakeup vector in the FACS.
625 // We expect any other PEIMs that "borrow" memory similarly to CpuMpPei to
626 // restore the original contents. Furthermore, we expect all such PEIMs
627 // (CpuMpPei included) to claim the borrowed areas by producing memory
628 // allocation HOBs, and to honor preexistent memory allocation HOBs when
629 // looking for an area to borrow.
631 AddMemoryRangeHob (0, BASE_512KB
+ BASE_128KB
);
634 // Create memory HOBs
636 AddMemoryRangeHob (0, BASE_512KB
+ BASE_128KB
);
638 if (FeaturePcdGet (PcdSmmSmramRequire
)) {
641 TsegSize
= mQ35TsegMbytes
* SIZE_1MB
;
642 AddMemoryRangeHob (BASE_1MB
, LowerMemorySize
- TsegSize
);
643 AddReservedMemoryBaseSizeHob (LowerMemorySize
- TsegSize
, TsegSize
,
646 AddMemoryRangeHob (BASE_1MB
, LowerMemorySize
);
650 // If QEMU presents an E820 map, then create memory HOBs for the >=4GB RAM
651 // entries. Otherwise, create a single memory HOB with the flat >=4GB
652 // memory size read from the CMOS.
654 Status
= ScanOrAdd64BitE820Ram (NULL
);
655 if (EFI_ERROR (Status
) && UpperMemorySize
!= 0) {
656 AddMemoryBaseSizeHob (BASE_4GB
, UpperMemorySize
);
661 // We'd like to keep the following ranges uncached:
663 // - [LowerMemorySize, 4 GB)
665 // Everything else should be WB. Unfortunately, programming the inverse (ie.
666 // keeping the default UC, and configuring the complement set of the above as
667 // WB) is not reliable in general, because the end of the upper RAM can have
668 // practically any alignment, and we may not have enough variable MTRRs to
671 if (IsMtrrSupported ()) {
672 MtrrGetAllMtrrs (&MtrrSettings
);
675 // MTRRs disabled, fixed MTRRs disabled, default type is uncached
677 ASSERT ((MtrrSettings
.MtrrDefType
& BIT11
) == 0);
678 ASSERT ((MtrrSettings
.MtrrDefType
& BIT10
) == 0);
679 ASSERT ((MtrrSettings
.MtrrDefType
& 0xFF) == 0);
682 // flip default type to writeback
684 SetMem (&MtrrSettings
.Fixed
, sizeof MtrrSettings
.Fixed
, 0x06);
685 ZeroMem (&MtrrSettings
.Variables
, sizeof MtrrSettings
.Variables
);
686 MtrrSettings
.MtrrDefType
|= BIT11
| BIT10
| 6;
687 MtrrSetAllMtrrs (&MtrrSettings
);
690 // Set memory range from 640KB to 1MB to uncacheable
692 Status
= MtrrSetMemoryAttribute (BASE_512KB
+ BASE_128KB
,
693 BASE_1MB
- (BASE_512KB
+ BASE_128KB
), CacheUncacheable
);
694 ASSERT_EFI_ERROR (Status
);
697 // Set memory range from the "top of lower RAM" (RAM below 4GB) to 4GB as
700 Status
= MtrrSetMemoryAttribute (LowerMemorySize
,
701 SIZE_4GB
- LowerMemorySize
, CacheUncacheable
);
702 ASSERT_EFI_ERROR (Status
);
707 Publish system RAM and reserve memory regions
711 InitializeRamRegions (
716 QemuInitializeRam ();
718 XenPublishRamRegions ();
721 if (mS3Supported
&& mBootMode
!= BOOT_ON_S3_RESUME
) {
723 // This is the memory range that will be used for PEI on S3 resume
725 BuildMemoryAllocationHob (
726 mS3AcpiReservedMemoryBase
,
727 mS3AcpiReservedMemorySize
,
732 // Cover the initial RAM area used as stack and temporary PEI heap.
734 // This is reserved as ACPI NVS so it can be used on S3 resume.
736 BuildMemoryAllocationHob (
737 PcdGet32 (PcdOvmfSecPeiTempRamBase
),
738 PcdGet32 (PcdOvmfSecPeiTempRamSize
),
743 // SEC stores its table of GUIDed section handlers here.
745 BuildMemoryAllocationHob (
746 PcdGet64 (PcdGuidedExtractHandlerTableAddress
),
747 PcdGet32 (PcdGuidedExtractHandlerTableSize
),
753 // Reserve the initial page tables built by the reset vector code.
755 // Since this memory range will be used by the Reset Vector on S3
756 // resume, it must be reserved as ACPI NVS.
758 BuildMemoryAllocationHob (
759 (EFI_PHYSICAL_ADDRESS
)(UINTN
) PcdGet32 (PcdOvmfSecPageTablesBase
),
760 (UINT64
)(UINTN
) PcdGet32 (PcdOvmfSecPageTablesSize
),
766 if (mBootMode
!= BOOT_ON_S3_RESUME
) {
767 if (!FeaturePcdGet (PcdSmmSmramRequire
)) {
769 // Reserve the lock box storage area
771 // Since this memory range will be used on S3 resume, it must be
772 // reserved as ACPI NVS.
774 // If S3 is unsupported, then various drivers might still write to the
775 // LockBox area. We ought to prevent DXE from serving allocation requests
776 // such that they would overlap the LockBox storage.
779 (VOID
*)(UINTN
) PcdGet32 (PcdOvmfLockBoxStorageBase
),
780 (UINTN
) PcdGet32 (PcdOvmfLockBoxStorageSize
)
782 BuildMemoryAllocationHob (
783 (EFI_PHYSICAL_ADDRESS
)(UINTN
) PcdGet32 (PcdOvmfLockBoxStorageBase
),
784 (UINT64
)(UINTN
) PcdGet32 (PcdOvmfLockBoxStorageSize
),
785 mS3Supported
? EfiACPIMemoryNVS
: EfiBootServicesData
789 if (FeaturePcdGet (PcdSmmSmramRequire
)) {
793 // Make sure the TSEG area that we reported as a reserved memory resource
794 // cannot be used for reserved memory allocations.
796 TsegSize
= mQ35TsegMbytes
* SIZE_1MB
;
797 BuildMemoryAllocationHob (
798 GetSystemMemorySizeBelow4gb() - TsegSize
,
800 EfiReservedMemoryType