4 Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
5 Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>
7 This program and the accompanying materials
8 are licensed and made available under the terms and conditions of the BSD License
9 which accompanies this distribution. The full text of the license may be found at
10 http://opensource.org/licenses/bsd-license.php
12 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
13 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 // The package level header files this module uses
23 // The Library classes this module consumes
25 #include <Library/DebugLib.h>
26 #include <Library/HobLib.h>
27 #include <Library/IoLib.h>
28 #include <Library/MemoryAllocationLib.h>
29 #include <Library/PcdLib.h>
30 #include <Library/PciLib.h>
31 #include <Library/PeimEntryPoint.h>
32 #include <Library/PeiServicesLib.h>
33 #include <Library/QemuFwCfgLib.h>
34 #include <Library/ResourcePublicationLib.h>
35 #include <Guid/MemoryTypeInformation.h>
36 #include <Ppi/MasterBootMode.h>
37 #include <IndustryStandard/Pci22.h>
38 #include <OvmfPlatforms.h>
43 EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation
[] = {
44 { EfiACPIMemoryNVS
, 0x004 },
45 { EfiACPIReclaimMemory
, 0x008 },
46 { EfiReservedMemoryType
, 0x004 },
47 { EfiRuntimeServicesData
, 0x024 },
48 { EfiRuntimeServicesCode
, 0x030 },
49 { EfiBootServicesCode
, 0x180 },
50 { EfiBootServicesData
, 0xF00 },
51 { EfiMaxMemoryType
, 0x000 }
55 EFI_PEI_PPI_DESCRIPTOR mPpiBootMode
[] = {
57 EFI_PEI_PPI_DESCRIPTOR_PPI
| EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST
,
58 &gEfiPeiMasterBootModePpiGuid
,
64 UINT16 mHostBridgeDevId
;
66 EFI_BOOT_MODE mBootMode
= BOOT_WITH_FULL_CONFIGURATION
;
68 BOOLEAN mS3Supported
= FALSE
;
72 AddIoMemoryBaseSizeHob (
73 EFI_PHYSICAL_ADDRESS MemoryBase
,
77 BuildResourceDescriptorHob (
78 EFI_RESOURCE_MEMORY_MAPPED_IO
,
79 EFI_RESOURCE_ATTRIBUTE_PRESENT
|
80 EFI_RESOURCE_ATTRIBUTE_INITIALIZED
|
81 EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE
|
82 EFI_RESOURCE_ATTRIBUTE_TESTED
,
89 AddReservedMemoryBaseSizeHob (
90 EFI_PHYSICAL_ADDRESS MemoryBase
,
95 BuildResourceDescriptorHob (
96 EFI_RESOURCE_MEMORY_RESERVED
,
97 EFI_RESOURCE_ATTRIBUTE_PRESENT
|
98 EFI_RESOURCE_ATTRIBUTE_INITIALIZED
|
99 EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE
|
101 EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE
|
102 EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE
|
103 EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE
:
106 EFI_RESOURCE_ATTRIBUTE_TESTED
,
113 AddIoMemoryRangeHob (
114 EFI_PHYSICAL_ADDRESS MemoryBase
,
115 EFI_PHYSICAL_ADDRESS MemoryLimit
118 AddIoMemoryBaseSizeHob (MemoryBase
, (UINT64
)(MemoryLimit
- MemoryBase
));
123 AddMemoryBaseSizeHob (
124 EFI_PHYSICAL_ADDRESS MemoryBase
,
128 BuildResourceDescriptorHob (
129 EFI_RESOURCE_SYSTEM_MEMORY
,
130 EFI_RESOURCE_ATTRIBUTE_PRESENT
|
131 EFI_RESOURCE_ATTRIBUTE_INITIALIZED
|
132 EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE
|
133 EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE
|
134 EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE
|
135 EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE
|
136 EFI_RESOURCE_ATTRIBUTE_TESTED
,
145 EFI_PHYSICAL_ADDRESS MemoryBase
,
146 EFI_PHYSICAL_ADDRESS MemoryLimit
149 AddMemoryBaseSizeHob (MemoryBase
, (UINT64
)(MemoryLimit
- MemoryBase
));
154 AddUntestedMemoryBaseSizeHob (
155 EFI_PHYSICAL_ADDRESS MemoryBase
,
159 BuildResourceDescriptorHob (
160 EFI_RESOURCE_SYSTEM_MEMORY
,
161 EFI_RESOURCE_ATTRIBUTE_PRESENT
|
162 EFI_RESOURCE_ATTRIBUTE_INITIALIZED
|
163 EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE
|
164 EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE
|
165 EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE
|
166 EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE
,
174 AddUntestedMemoryRangeHob (
175 EFI_PHYSICAL_ADDRESS MemoryBase
,
176 EFI_PHYSICAL_ADDRESS MemoryLimit
179 AddUntestedMemoryBaseSizeHob (MemoryBase
, (UINT64
)(MemoryLimit
- MemoryBase
));
183 MemMapInitialization (
188 // Create Memory Type Information HOB
191 &gEfiMemoryTypeInformationGuid
,
192 mDefaultMemoryTypeInformation
,
193 sizeof(mDefaultMemoryTypeInformation
)
197 // Add PCI IO Port space available for PCI resource allocations.
199 BuildResourceDescriptorHob (
201 EFI_RESOURCE_ATTRIBUTE_PRESENT
|
202 EFI_RESOURCE_ATTRIBUTE_INITIALIZED
,
208 // Video memory + Legacy BIOS region
210 AddIoMemoryRangeHob (0x0A0000, BASE_1MB
);
216 TopOfLowRam
= GetSystemMemorySizeBelow4gb ();
217 if (mHostBridgeDevId
== INTEL_Q35_MCH_DEVICE_ID
) {
219 // A 3GB base will always fall into Q35's 32-bit PCI host aperture,
220 // regardless of the Q35 MMCONFIG BAR. Correspondingly, QEMU never lets
221 // the RAM below 4 GB exceed it.
223 PciBase
= BASE_2GB
+ BASE_1GB
;
224 ASSERT (TopOfLowRam
<= PciBase
);
226 PciBase
= (TopOfLowRam
< BASE_2GB
) ? BASE_2GB
: TopOfLowRam
;
230 // address purpose size
231 // ------------ -------- -------------------------
232 // max(top, 2g) PCI MMIO 0xFC000000 - max(top, 2g)
233 // 0xFC000000 gap 44 MB
234 // 0xFEC00000 IO-APIC 4 KB
235 // 0xFEC01000 gap 1020 KB
236 // 0xFED00000 HPET 1 KB
237 // 0xFED00400 gap 111 KB
238 // 0xFED1C000 gap (PIIX4) / RCRB (ICH9) 16 KB
239 // 0xFED20000 gap 896 KB
240 // 0xFEE00000 LAPIC 1 MB
242 AddIoMemoryRangeHob (PciBase
, 0xFC000000);
243 AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB
);
244 AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB
);
245 if (mHostBridgeDevId
== INTEL_Q35_MCH_DEVICE_ID
) {
246 AddIoMemoryBaseSizeHob (ICH9_ROOT_COMPLEX_BASE
, SIZE_16KB
);
248 AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress
), SIZE_1MB
);
253 GetNamedFwCfgBoolean (
254 IN CHAR8
*FwCfgFileName
,
259 FIRMWARE_CONFIG_ITEM FwCfgItem
;
263 Status
= QemuFwCfgFindFile (FwCfgFileName
, &FwCfgItem
, &FwCfgSize
);
264 if (EFI_ERROR (Status
)) {
267 if (FwCfgSize
> sizeof Value
) {
268 return EFI_BAD_BUFFER_SIZE
;
270 QemuFwCfgSelectItem (FwCfgItem
);
271 QemuFwCfgReadBytes (FwCfgSize
, Value
);
273 if ((FwCfgSize
== 1) ||
274 (FwCfgSize
== 2 && Value
[1] == '\n') ||
275 (FwCfgSize
== 3 && Value
[1] == '\r' && Value
[2] == '\n')) {
293 return EFI_PROTOCOL_ERROR
;
296 #define UPDATE_BOOLEAN_PCD_FROM_FW_CFG(TokenName) \
300 if (!EFI_ERROR (GetNamedFwCfgBoolean ( \
301 "opt/ovmf/" #TokenName, &Setting))) { \
302 PcdSetBool (TokenName, Setting); \
307 NoexecDxeInitialization (
311 UPDATE_BOOLEAN_PCD_FROM_FW_CFG (PcdPropertiesTableEnable
);
312 UPDATE_BOOLEAN_PCD_FROM_FW_CFG (PcdSetNxForStack
);
331 // Build the CPU HOB with guest RAM size dependent address width and 16-bits
332 // of IO space. (Side note: unlike other HOBs, the CPU HOB is needed during
333 // S3 resume as well, so we build it unconditionally.)
335 BuildCpuHob (mPhysMemAddressWidth
, 16);
338 // Determine platform type and save Host Bridge DID to PCD
340 switch (mHostBridgeDevId
) {
341 case INTEL_82441_DEVICE_ID
:
342 PmCmd
= POWER_MGMT_REGISTER_PIIX4 (PCI_COMMAND_OFFSET
);
343 Pmba
= POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA
);
344 AcpiCtlReg
= POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC
);
345 AcpiEnBit
= PIIX4_PMREGMISC_PMIOSE
;
347 case INTEL_Q35_MCH_DEVICE_ID
:
348 PmCmd
= POWER_MGMT_REGISTER_Q35 (PCI_COMMAND_OFFSET
);
349 Pmba
= POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE
);
350 AcpiCtlReg
= POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL
);
351 AcpiEnBit
= ICH9_ACPI_CNTL_ACPI_EN
;
354 DEBUG ((EFI_D_ERROR
, "%a: Unknown Host Bridge Device ID: 0x%04x\n",
355 __FUNCTION__
, mHostBridgeDevId
));
359 PcdSet16 (PcdOvmfHostBridgePciDevId
, mHostBridgeDevId
);
362 // If the appropriate IOspace enable bit is set, assume the ACPI PMBA
363 // has been configured (e.g., by Xen) and skip the setup here.
364 // This matches the logic in AcpiTimerLibConstructor ().
366 if ((PciRead8 (AcpiCtlReg
) & AcpiEnBit
) == 0) {
368 // The PEI phase should be exited with fully accessibe ACPI PM IO space:
371 PciAndThenOr32 (Pmba
, (UINT32
) ~0xFFC0, PcdGet16 (PcdAcpiPmBaseAddress
));
374 // 2. set PCICMD/IOSE
376 PciOr8 (PmCmd
, EFI_PCI_COMMAND_IO_SPACE
);
379 // 3. set ACPI PM IO enable bit (PMREGMISC:PMIOSE or ACPI_CNTL:ACPI_EN)
381 PciOr8 (AcpiCtlReg
, AcpiEnBit
);
384 if (mHostBridgeDevId
== INTEL_Q35_MCH_DEVICE_ID
) {
386 // Set Root Complex Register Block BAR
389 POWER_MGMT_REGISTER_Q35 (ICH9_RCBA
),
390 ICH9_ROOT_COMPLEX_BASE
| ICH9_RCBA_EN
397 BootModeInitialization (
403 if (CmosRead8 (0xF) == 0xFE) {
404 mBootMode
= BOOT_ON_S3_RESUME
;
406 CmosWrite8 (0xF, 0x00);
408 Status
= PeiServicesSetBootMode (mBootMode
);
409 ASSERT_EFI_ERROR (Status
);
411 Status
= PeiServicesInstallPpi (mPpiBootMode
);
412 ASSERT_EFI_ERROR (Status
);
417 ReserveEmuVariableNvStore (
420 EFI_PHYSICAL_ADDRESS VariableStore
;
423 // Allocate storage for NV variables early on so it will be
424 // at a consistent address. Since VM memory is preserved
425 // across reboots, this allows the NV variable storage to survive
429 (EFI_PHYSICAL_ADDRESS
)(UINTN
)
430 AllocateAlignedRuntimePages (
431 EFI_SIZE_TO_PAGES (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize
)),
432 PcdGet32 (PcdFlashNvStorageFtwSpareSize
)
435 "Reserved variable store memory: 0x%lX; size: %dkb\n",
437 (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize
)) / 1024
439 PcdSet64 (PcdEmuVariableNvStoreReserved
, VariableStore
);
450 DEBUG ((EFI_D_INFO
, "CMOS:\n"));
452 for (Loop
= 0; Loop
< 0x80; Loop
++) {
453 if ((Loop
% 0x10) == 0) {
454 DEBUG ((EFI_D_INFO
, "%02x:", Loop
));
456 DEBUG ((EFI_D_INFO
, " %02x", CmosRead8 (Loop
)));
457 if ((Loop
% 0x10) == 0xf) {
458 DEBUG ((EFI_D_INFO
, "\n"));
465 Perform Platform PEI initialization.
467 @param FileHandle Handle of the file being invoked.
468 @param PeiServices Describes the list of possible PEI Services.
470 @return EFI_SUCCESS The PEIM initialized successfully.
476 IN EFI_PEI_FILE_HANDLE FileHandle
,
477 IN CONST EFI_PEI_SERVICES
**PeiServices
480 DEBUG ((EFI_D_ERROR
, "Platform PEIM Loaded\n"));
486 if (QemuFwCfgS3Enabled ()) {
487 DEBUG ((EFI_D_INFO
, "S3 support was detected on QEMU\n"));
491 BootModeInitialization ();
492 AddressWidthInitialization ();
496 InitializeRamRegions ();
499 DEBUG ((EFI_D_INFO
, "Xen was detected\n"));
504 // Query Host Bridge DID
506 mHostBridgeDevId
= PciRead16 (OVMF_HOSTBRIDGE_DID
);
508 if (mBootMode
!= BOOT_ON_S3_RESUME
) {
509 ReserveEmuVariableNvStore ();
510 PeiFvInitialization ();
511 MemMapInitialization ();
512 NoexecDxeInitialization ();
515 MiscInitialization ();