#include <PiSmm.h>\r
#include <Library/SmmCpuFeaturesLib.h>\r
#include <Library/BaseLib.h>\r
-#include <Library/MtrrLib.h>\r
#include <Library/PcdLib.h>\r
#include <Library/MemoryAllocationLib.h>\r
#include <Library/DebugLib.h>\r
-#include <Register/Cpuid.h>\r
#include <Register/SmramSaveStateMap.h>\r
\r
-//\r
-// Machine Specific Registers (MSRs)\r
-//\r
-#define SMM_FEATURES_LIB_IA32_MTRR_CAP 0x0FE\r
-#define SMM_FEATURES_LIB_IA32_FEATURE_CONTROL 0x03A\r
-#define SMM_FEATURES_LIB_IA32_SMRR_PHYSBASE 0x1F2\r
-#define SMM_FEATURES_LIB_IA32_SMRR_PHYSMASK 0x1F3\r
-#define SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSBASE 0x0A0\r
-#define SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSMASK 0x0A1\r
-#define EFI_MSR_SMRR_MASK 0xFFFFF000\r
-#define EFI_MSR_SMRR_PHYS_MASK_VALID BIT11\r
-#define SMM_FEATURES_LIB_SMM_FEATURE_CONTROL 0x4E0\r
-\r
-//\r
-// MSRs required for configuration of SMM Code Access Check\r
-//\r
-#define SMM_FEATURES_LIB_IA32_MCA_CAP 0x17D\r
-#define SMM_CODE_ACCESS_CHK_BIT BIT58\r
-\r
-//\r
-// Set default value to assume SMRR is not supported\r
-//\r
-BOOLEAN mSmrrSupported = FALSE;\r
-\r
-//\r
-// Set default value to assume MSR_SMM_FEATURE_CONTROL is not supported\r
-//\r
-BOOLEAN mSmmFeatureControlSupported = FALSE;\r
-\r
-//\r
-// Set default value to assume IA-32 Architectural MSRs are used\r
-//\r
-UINT32 mSmrrPhysBaseMsr = SMM_FEATURES_LIB_IA32_SMRR_PHYSBASE;\r
-UINT32 mSmrrPhysMaskMsr = SMM_FEATURES_LIB_IA32_SMRR_PHYSMASK;\r
-\r
-//\r
-// Set default value to assume MTRRs need to be configured on each SMI\r
-//\r
-BOOLEAN mNeedConfigureMtrrs = TRUE;\r
-\r
-//\r
-// Array for state of SMRR enable on all CPUs\r
-//\r
-BOOLEAN *mSmrrEnabled;\r
-\r
/**\r
The constructor function\r
\r
IN EFI_SYSTEM_TABLE *SystemTable\r
)\r
{\r
- UINT32 RegEax;\r
- UINT32 RegEdx;\r
- UINTN FamilyId;\r
- UINTN ModelId;\r
-\r
- //\r
- // Retrieve CPU Family and Model\r
- //\r
- AsmCpuid (CPUID_VERSION_INFO, &RegEax, NULL, NULL, &RegEdx);\r
- FamilyId = (RegEax >> 8) & 0xf;\r
- ModelId = (RegEax >> 4) & 0xf;\r
- if (FamilyId == 0x06 || FamilyId == 0x0f) {\r
- ModelId = ModelId | ((RegEax >> 12) & 0xf0);\r
- }\r
-\r
- //\r
- // Check CPUID(CPUID_VERSION_INFO).EDX[12] for MTRR capability\r
- //\r
- if ((RegEdx & BIT12) != 0) {\r
- //\r
- // Check MTRR_CAP MSR bit 11 for SMRR support\r
- //\r
- if ((AsmReadMsr64 (SMM_FEATURES_LIB_IA32_MTRR_CAP) & BIT11) != 0) {\r
- mSmrrSupported = TRUE;\r
- }\r
- }\r
-\r
- //\r
- // Intel(R) 64 and IA-32 Architectures Software Developer's Manual\r
- // Volume 3C, Section 35.3 MSRs in the Intel(R) Atom(TM) Processor Family\r
- //\r
- // If CPU Family/Model is 06_1CH, 06_26H, 06_27H, 06_35H or 06_36H, then\r
- // SMRR Physical Base and SMM Physical Mask MSRs are not available.\r
- //\r
- if (FamilyId == 0x06) {\r
- if (ModelId == 0x1C || ModelId == 0x26 || ModelId == 0x27 || ModelId == 0x35 || ModelId == 0x36) {\r
- mSmrrSupported = FALSE;\r
- }\r
- }\r
-\r
- //\r
- // Intel(R) 64 and IA-32 Architectures Software Developer's Manual\r
- // Volume 3C, Section 35.2 MSRs in the Intel(R) Core(TM) 2 Processor Family\r
- //\r
- // If CPU Family/Model is 06_0F or 06_17, then use Intel(R) Core(TM) 2\r
- // Processor Family MSRs\r
- //\r
- if (FamilyId == 0x06) {\r
- if (ModelId == 0x17 || ModelId == 0x0f) {\r
- mSmrrPhysBaseMsr = SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSBASE;\r
- mSmrrPhysMaskMsr = SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSMASK;\r
- }\r
- }\r
-\r
- //\r
- // Intel(R) 64 and IA-32 Architectures Software Developer's Manual\r
- // Volume 3C, Section 34.4.2 SMRAM Caching\r
- // An IA-32 processor does not automatically write back and invalidate its\r
- // caches before entering SMM or before exiting SMM. Because of this behavior,\r
- // care must be taken in the placement of the SMRAM in system memory and in\r
- // the caching of the SMRAM to prevent cache incoherence when switching back\r
- // and forth between SMM and protected mode operation.\r
- //\r
- // An IA-32 processor is a processor that does not support the Intel 64\r
- // Architecture. Support for the Intel 64 Architecture can be detected from\r
- // CPUID(CPUID_EXTENDED_CPU_SIG).EDX[29]\r
- //\r
- // If an IA-32 processor is detected, then set mNeedConfigureMtrrs to TRUE,\r
- // so caches are flushed on SMI entry and SMI exit, the interrupted code\r
- // MTRRs are saved/restored, and MTRRs for SMM are loaded.\r
- //\r
- AsmCpuid (CPUID_EXTENDED_FUNCTION, &RegEax, NULL, NULL, NULL);\r
- if (RegEax >= CPUID_EXTENDED_CPU_SIG) {\r
- AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, NULL, &RegEdx);\r
- if ((RegEdx & BIT29) != 0) {\r
- mNeedConfigureMtrrs = FALSE;\r
- }\r
- }\r
-\r
//\r
- // Allocate array for state of SMRR enable on all CPUs\r
+ // No need to program SMRRs on our virtual platform.\r
//\r
- mSmrrEnabled = (BOOLEAN *)AllocatePool (sizeof (BOOLEAN) * PcdGet32 (PcdCpuMaxLogicalProcessorNumber));\r
- ASSERT (mSmrrEnabled != NULL);\r
-\r
return EFI_SUCCESS;\r
}\r
\r
)\r
{\r
SMRAM_SAVE_STATE_MAP *CpuState;\r
- UINT64 FeatureControl;\r
- UINT32 RegEax;\r
- UINT32 RegEdx;\r
- UINTN FamilyId;\r
- UINTN ModelId;\r
\r
//\r
// Configure SMBASE.\r
CpuState->x86.SMBASE = (UINT32)CpuHotPlugData->SmBase[CpuIndex];\r
\r
//\r
- // Intel(R) 64 and IA-32 Architectures Software Developer's Manual\r
- // Volume 3C, Section 35.2 MSRs in the Intel(R) Core(TM) 2 Processor Family\r
- //\r
- // If Intel(R) Core(TM) Core(TM) 2 Processor Family MSRs are being used, then\r
- // make sure SMRR Enable(BIT3) of MSR_FEATURE_CONTROL MSR(0x3A) is set before\r
- // accessing SMRR base/mask MSRs. If Lock(BIT0) of MSR_FEATURE_CONTROL MSR(0x3A)\r
- // is set, then the MSR is locked and can not be modified.\r
- //\r
- if (mSmrrSupported && mSmrrPhysBaseMsr == SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSBASE) {\r
- FeatureControl = AsmReadMsr64 (SMM_FEATURES_LIB_IA32_FEATURE_CONTROL);\r
- if ((FeatureControl & BIT3) == 0) {\r
- if ((FeatureControl & BIT0) == 0) {\r
- AsmWriteMsr64 (SMM_FEATURES_LIB_IA32_FEATURE_CONTROL, FeatureControl | BIT3);\r
- } else {\r
- mSmrrSupported = FALSE;\r
- }\r
- }\r
- }\r
-\r
- //\r
- // If SMRR is supported, then program SMRR base/mask MSRs.\r
- // The EFI_MSR_SMRR_PHYS_MASK_VALID bit is not set until the first normal SMI.\r
- // The code that initializes SMM environment is running in normal mode\r
- // from SMRAM region. If SMRR is enabled here, then the SMRAM region\r
- // is protected and the normal mode code execution will fail.\r
- //\r
- if (mSmrrSupported) {\r
- AsmWriteMsr64 (mSmrrPhysBaseMsr, CpuHotPlugData->SmrrBase | MTRR_CACHE_WRITE_BACK);\r
- AsmWriteMsr64 (mSmrrPhysMaskMsr, (~(CpuHotPlugData->SmrrSize - 1) & EFI_MSR_SMRR_MASK));\r
- mSmrrEnabled[CpuIndex] = FALSE;\r
- }\r
-\r
- //\r
- // Retrieve CPU Family and Model\r
- //\r
- AsmCpuid (CPUID_VERSION_INFO, &RegEax, NULL, NULL, &RegEdx);\r
- FamilyId = (RegEax >> 8) & 0xf;\r
- ModelId = (RegEax >> 4) & 0xf;\r
- if (FamilyId == 0x06 || FamilyId == 0x0f) {\r
- ModelId = ModelId | ((RegEax >> 12) & 0xf0);\r
- }\r
-\r
- //\r
- // Intel(R) 64 and IA-32 Architectures Software Developer's Manual\r
- // Volume 3C, Section 35.10.1 MSRs in 4th Generation Intel(R) Core(TM)\r
- // Processor Family.\r
- //\r
- // If CPU Family/Model is 06_3C, 06_45, or 06_46 then use 4th Generation\r
- // Intel(R) Core(TM) Processor Family MSRs.\r
+ // No need to program SMRRs on our virtual platform.\r
//\r
- if (FamilyId == 0x06) {\r
- if (ModelId == 0x3C || ModelId == 0x45 || ModelId == 0x46) {\r
- //\r
- // Check to see if the CPU supports the SMM Code Access Check feature\r
- // Do not access this MSR unless the CPU supports the SmmRegFeatureControl\r
- //\r
- if ((AsmReadMsr64 (SMM_FEATURES_LIB_IA32_MCA_CAP) & SMM_CODE_ACCESS_CHK_BIT) != 0) {\r
- mSmmFeatureControlSupported = TRUE;\r
- }\r
- }\r
- }\r
}\r
\r
/**\r
VOID\r
)\r
{\r
- return mNeedConfigureMtrrs;\r
+ return FALSE;\r
}\r
\r
/**\r
VOID\r
)\r
{\r
- if (mSmrrSupported && mNeedConfigureMtrrs) {\r
- AsmWriteMsr64 (mSmrrPhysMaskMsr, AsmReadMsr64(mSmrrPhysMaskMsr) & ~EFI_MSR_SMRR_PHYS_MASK_VALID);\r
- }\r
+ //\r
+ // No SMRR support, nothing to do\r
+ //\r
}\r
\r
/**\r
VOID\r
)\r
{\r
- if (mSmrrSupported && mNeedConfigureMtrrs) {\r
- AsmWriteMsr64 (mSmrrPhysMaskMsr, AsmReadMsr64(mSmrrPhysMaskMsr) | EFI_MSR_SMRR_PHYS_MASK_VALID);\r
- }\r
+ //\r
+ // No SMRR support, nothing to do\r
+ //\r
}\r
\r
/**\r
)\r
{\r
//\r
- // If SMRR is supported and this is the first normal SMI, then enable SMRR\r
+ // No SMRR support, nothing to do\r
//\r
- if (mSmrrSupported && !mSmrrEnabled[CpuIndex]) {\r
- AsmWriteMsr64 (mSmrrPhysMaskMsr, AsmReadMsr64 (mSmrrPhysMaskMsr) | EFI_MSR_SMRR_PHYS_MASK_VALID);\r
- mSmrrEnabled[CpuIndex] = TRUE;\r
- }\r
}\r
\r
/**\r
IN SMM_REG_NAME RegName\r
)\r
{\r
- if (mSmmFeatureControlSupported && RegName == SmmRegFeatureControl) {\r
- return TRUE;\r
- }\r
+ ASSERT (RegName == SmmRegFeatureControl);\r
return FALSE;\r
}\r
\r
IN SMM_REG_NAME RegName\r
)\r
{\r
- if (mSmmFeatureControlSupported && RegName == SmmRegFeatureControl) {\r
- return AsmReadMsr64 (SMM_FEATURES_LIB_SMM_FEATURE_CONTROL);\r
- }\r
+ //\r
+ // This is called for SmmRegSmmDelayed, SmmRegSmmBlocked, SmmRegSmmEnable.\r
+ // The last of these should actually be SmmRegSmmDisable, so we can just\r
+ // return FALSE.\r
+ //\r
return 0;\r
}\r
\r
IN UINT64 Value\r
)\r
{\r
- if (mSmmFeatureControlSupported && RegName == SmmRegFeatureControl) {\r
- AsmWriteMsr64 (SMM_FEATURES_LIB_SMM_FEATURE_CONTROL, Value);\r
- }\r
+ ASSERT (FALSE);\r
}\r
\r
/**\r
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