1 ;------------------------------------------------------------------------------
3 ; Sets the CR3 register for 64-bit paging
5 ; Copyright (c) 2008 - 2013, Intel Corporation. All rights reserved.<BR>
6 ; Copyright (c) 2017 - 2020, Advanced Micro Devices, Inc. All rights reserved.<BR>
7 ; SPDX-License-Identifier: BSD-2-Clause-Patent
9 ;------------------------------------------------------------------------------
13 %define PAGE_PRESENT 0x01
14 %define PAGE_READ_WRITE 0x02
15 %define PAGE_USER_SUPERVISOR 0x04
16 %define PAGE_WRITE_THROUGH 0x08
17 %define PAGE_CACHE_DISABLE 0x010
18 %define PAGE_ACCESSED 0x020
19 %define PAGE_DIRTY 0x040
20 %define PAGE_PAT 0x080
21 %define PAGE_GLOBAL 0x0100
22 %define PAGE_2M_MBO 0x080
23 %define PAGE_2M_PAT 0x01000
25 %define PAGE_4K_PDE_ATTR (PAGE_ACCESSED + \
30 %define PAGE_2M_PDE_ATTR (PAGE_2M_MBO + \
36 %define PAGE_PDP_ATTR (PAGE_ACCESSED + \
41 ; Modified: EAX, EBX, ECX, EDX
43 SetCr3ForPageTables64:
45 OneTimeCall CheckSevFeatures
50 ; If SEV is enabled, C-bit is always above 31
57 ; For OVMF, build some initial page tables at
58 ; PcdOvmfSecPageTablesBase - (PcdOvmfSecPageTablesBase + 0x6000).
60 ; This range should match with PcdOvmfSecPageTablesSize which is
61 ; declared in the FDF files.
63 ; At the end of PEI, the pages tables will be rebuilt into a
64 ; more permanent location by DxeIpl.
67 mov ecx, 6 * 0x1000 / 4
69 clearPageTablesMemoryLoop:
70 mov dword[ecx * 4 + PT_ADDR (0) - 4], eax
71 loop clearPageTablesMemoryLoop
74 ; Top level Page Directory Pointers (1 * 512GB entry)
76 mov dword[PT_ADDR (0)], PT_ADDR (0x1000) + PAGE_PDP_ATTR
77 mov dword[PT_ADDR (4)], edx
80 ; Next level Page Directory Pointers (4 * 1GB entries => 4GB)
82 mov dword[PT_ADDR (0x1000)], PT_ADDR (0x2000) + PAGE_PDP_ATTR
83 mov dword[PT_ADDR (0x1004)], edx
84 mov dword[PT_ADDR (0x1008)], PT_ADDR (0x3000) + PAGE_PDP_ATTR
85 mov dword[PT_ADDR (0x100C)], edx
86 mov dword[PT_ADDR (0x1010)], PT_ADDR (0x4000) + PAGE_PDP_ATTR
87 mov dword[PT_ADDR (0x1014)], edx
88 mov dword[PT_ADDR (0x1018)], PT_ADDR (0x5000) + PAGE_PDP_ATTR
89 mov dword[PT_ADDR (0x101C)], edx
92 ; Page Table Entries (2048 * 2MB entries => 4GB)
99 add eax, PAGE_2M_PDE_ATTR
100 mov [ecx * 8 + PT_ADDR (0x2000 - 8)], eax
101 mov [(ecx * 8 + PT_ADDR (0x2000 - 8)) + 4], edx
102 loop pageTableEntriesLoop
104 OneTimeCall IsSevEsEnabled
109 ; The initial GHCB will live at GHCB_BASE and needs to be un-encrypted.
110 ; This requires the 2MB page for this range be broken down into 512 4KB
111 ; pages. All will be marked encrypted, except for the GHCB.
113 mov ecx, (GHCB_BASE >> 21)
114 mov eax, GHCB_PT_ADDR + PAGE_PDP_ATTR
115 mov [ecx * 8 + PT_ADDR (0x2000)], eax
118 ; Page Table Entries (512 * 4KB entries => 2MB)
121 pageTableEntries4kLoop:
125 add eax, GHCB_BASE & 0xFFE0_0000
126 add eax, PAGE_4K_PDE_ATTR
127 mov [ecx * 8 + GHCB_PT_ADDR - 8], eax
128 mov [(ecx * 8 + GHCB_PT_ADDR - 8) + 4], edx
129 loop pageTableEntries4kLoop
132 ; Clear the encryption bit from the GHCB entry
134 mov ecx, (GHCB_BASE & 0x1F_FFFF) >> 12
135 mov [ecx * 8 + GHCB_PT_ADDR + 4], strict dword 0
137 mov ecx, GHCB_SIZE / 4
140 mov dword[ecx * 4 + GHCB_BASE - 4], eax
141 loop clearGhcbMemoryLoop
145 ; Set CR3 now that the paging structures are available
150 OneTimeCallRet SetCr3ForPageTables64