2 Public include file for I/O APIC library.
4 I/O APIC library assumes I/O APIC is enabled. It does not
5 handles cases where I/O APIC is disabled.
7 Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.<BR>
8 SPDX-License-Identifier: BSD-2-Clause-Patent
12 #ifndef __IO_APIC_LIB_H__
13 #define __IO_APIC_LIB_H__
16 Read a 32-bit I/O APIC register.
18 If Index is >= 0x100, then ASSERT().
20 @param Index Specifies the I/O APIC register to read.
22 @return The 32-bit value read from the I/O APIC register specified by Index.
31 Write a 32-bit I/O APIC register.
33 If Index is >= 0x100, then ASSERT().
35 @param Index Specifies the I/O APIC register to write.
36 @param Value Specifies the value to write to the I/O APIC register specified by Index.
38 @return The 32-bit value written to I/O APIC register specified by Index.
48 Set the interrupt mask of an I/O APIC interrupt.
50 If Irq is larger than the maximum number I/O APIC redirection entries, then ASSERT().
52 @param Irq Specifies the I/O APIC interrupt to enable or disable.
53 @param Enable If TRUE, then enable the I/O APIC interrupt specified by Irq.
54 If FALSE, then disable the I/O APIC interrupt specified by Irq.
58 IoApicEnableInterrupt (
64 Configures an I/O APIC interrupt.
66 Configure an I/O APIC Redirection Table Entry to deliver an interrupt in physical
67 mode to the Local APIC of the currently executing CPU. The default state of the
68 entry is for the interrupt to be disabled (masked). IoApicEnableInterrupts() must
69 be used to enable(unmask) the I/O APIC Interrupt.
71 If Irq is larger than the maximum number I/O APIC redirection entries, then ASSERT().
72 If Vector >= 0x100, then ASSERT().
73 If DeliveryMode is not supported, then ASSERT().
75 @param Irq Specifies the I/O APIC interrupt to initialize.
76 @param Vector The 8-bit interrupt vector associated with the I/O APIC
77 Interrupt. Must be in the range 0x10..0xFE.
78 @param DeliveryMode A 3-bit value that specifies how the recept of the I/O APIC
79 interrupt is handled. The only supported values are:
80 0: IO_APIC_DELIVERY_MODE_FIXED
81 1: IO_APIC_DELIVERY_MODE_LOWEST_PRIORITY
82 2: IO_APIC_DELIVERY_MODE_SMI
83 4: IO_APIC_DELIVERY_MODE_NMI
84 5: IO_APIC_DELIVERY_MODE_INIT
85 7: IO_APIC_DELIVERY_MODE_EXTINT
86 @param LevelTriggered TRUE specifies a level triggered interrupt.
87 FALSE specifies an edge triggered interrupt.
88 @param AssertionLevel TRUE specified an active high interrupt.
89 FALSE specifies an active low interrupt.
93 IoApicConfigureInterrupt (
96 IN UINTN DeliveryMode
,
97 IN BOOLEAN LevelTriggered
,
98 IN BOOLEAN AssertionLevel