2 I/O APIC Register Definitions from 82093AA I/O Advanced Programmable Interrupt
3 Controller (IOAPIC), 1996.
5 Copyright (c) 2011, Intel Corporation. All rights reserved.<BR>
6 This program and the accompanying materials
7 are licensed and made available under the terms and conditions of the BSD License
8 which accompanies this distribution. The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
20 /// I/O APIC Register Offsets
22 #define IOAPIC_INDEX_OFFSET 0x00
23 #define IOAPIC_DATA_OFFSET 0x10
26 /// I/O APIC Indirect Register Indexes
28 #define IO_APIC_IDENTIFICATION_REGISTER_INDEX 0x00
29 #define IO_APIC_VERSION_REGISTER_INDEX 0x01
30 #define IO_APIC_REDIRECTION_TABLE_ENTRY_INDEX 0x10
33 /// I/O APIC Interrupt Deliver Modes
35 #define IO_APIC_DELIVERY_MODE_FIXED 0
36 #define IO_APIC_DELIVERY_MODE_LOWEST_PRIORITY 1
37 #define IO_APIC_DELIVERY_MODE_SMI 2
38 #define IO_APIC_DELIVERY_MODE_NMI 4
39 #define IO_APIC_DELIVERY_MODE_INIT 5
40 #define IO_APIC_DELIVERY_MODE_EXTINT 7
47 UINT32 Identification
:4;
51 } IO_APIC_IDENTIFICATION_REGISTER
;
57 UINT32 MaximumRedirectionEntry
:8;
61 } IO_APIC_VERSION_REGISTER
;
66 UINT32 DeliveryMode
: 3;
67 UINT32 DestinationMode
: 1;
68 UINT32 DeliveryStatus
: 1;
71 UINT32 TriggerMode
: 1;
75 UINT32 DestinationID
: 8;
82 } IO_APIC_REDIRECTION_TABLE_ENTRY
;