2 System On Chip Unit (SOCUnit) routines.
4 Copyright (c) 2013-2015 Intel Corporation.
6 SPDX-License-Identifier: BSD-2-Clause-Patent
10 #include "CommonHeader.h"
12 /** Early initialisation of the SOC Unit
14 @retval EFI_SUCCESS Operation success.
19 SocUnitEarlyInitialisation (
26 // Set the mixer load resistance
28 NewValue
= QNCPortIORead (QUARK_SC_PCIE_AFE_SB_PORT_ID
, QUARK_PCIE_AFE_PCIE_RXPICTRL0_L0
);
29 NewValue
&= OCFGPIMIXLOAD_1_0_MASK
;
30 QNCPortIOWrite (QUARK_SC_PCIE_AFE_SB_PORT_ID
, QUARK_PCIE_AFE_PCIE_RXPICTRL0_L0
, NewValue
);
32 NewValue
= QNCPortIORead (QUARK_SC_PCIE_AFE_SB_PORT_ID
, QUARK_PCIE_AFE_PCIE_RXPICTRL0_L1
);
33 NewValue
&= OCFGPIMIXLOAD_1_0_MASK
;
34 QNCPortIOWrite (QUARK_SC_PCIE_AFE_SB_PORT_ID
, QUARK_PCIE_AFE_PCIE_RXPICTRL0_L1
, NewValue
);
39 /** Tasks to release PCI controller from reset pre wait for PLL Lock.
41 @retval EFI_SUCCESS Operation success.
46 SocUnitReleasePcieControllerPreWaitPllLock (
47 IN CONST EFI_PLATFORM_TYPE PlatformType
53 // Assert PERST# and validate time assertion time.
55 PlatformPERSTAssert (PlatformType
);
56 ASSERT (PCIEXP_PERST_MIN_ASSERT_US
<= (PCIEXP_DELAY_US_POST_CMNRESET_RESET
+ PCIEXP_DELAY_US_WAIT_PLL_LOCK
+ PCIEXP_DELAY_US_POST_SBI_RESET
));
59 // PHY Common lane reset.
61 NewValue
= QNCAltPortRead (QUARK_SCSS_SOC_UNIT_SB_PORT_ID
, QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG
);
62 NewValue
|= SOCCLKEN_CONFIG_PHY_I_CMNRESET_L
;
63 QNCAltPortWrite (QUARK_SCSS_SOC_UNIT_SB_PORT_ID
, QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG
, NewValue
);
66 // Wait post common lane reset.
68 MicroSecondDelay (PCIEXP_DELAY_US_POST_CMNRESET_RESET
);
71 // PHY Sideband interface reset.
72 // Controller main reset
74 NewValue
= QNCAltPortRead (QUARK_SCSS_SOC_UNIT_SB_PORT_ID
, QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG
);
75 NewValue
|= (SOCCLKEN_CONFIG_SBI_RST_100_CORE_B
| SOCCLKEN_CONFIG_PHY_I_SIDE_RST_L
);
76 QNCAltPortWrite (QUARK_SCSS_SOC_UNIT_SB_PORT_ID
, QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG
, NewValue
);
81 /** Tasks to release PCI controller from reset after PLL has locked
83 @retval EFI_SUCCESS Operation success.
88 SocUnitReleasePcieControllerPostPllLock (
89 IN CONST EFI_PLATFORM_TYPE PlatformType
95 // Controller sideband interface reset.
97 NewValue
= QNCAltPortRead (QUARK_SCSS_SOC_UNIT_SB_PORT_ID
, QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG
);
98 NewValue
|= SOCCLKEN_CONFIG_SBI_BB_RST_B
;
99 QNCAltPortWrite (QUARK_SCSS_SOC_UNIT_SB_PORT_ID
, QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG
, NewValue
);
102 // Wait post sideband interface reset.
104 MicroSecondDelay (PCIEXP_DELAY_US_POST_SBI_RESET
);
109 PlatformPERSTDeAssert (PlatformType
);
112 // Wait post de assert PERST#.
114 MicroSecondDelay (PCIEXP_DELAY_US_POST_PERST_DEASSERT
);
117 // Controller primary interface reset.
119 NewValue
= QNCAltPortRead (QUARK_SCSS_SOC_UNIT_SB_PORT_ID
, QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG
);
120 NewValue
|= SOCCLKEN_CONFIG_BB_RST_B
;
121 QNCAltPortWrite (QUARK_SCSS_SOC_UNIT_SB_PORT_ID
, QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG
, NewValue
);