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QuarkPlatformPkg: Add new package for Galileo boards
[mirror_edk2.git] / QuarkPlatformPkg / Platform / Pei / PlatformInit / PlatformEarlyInit.c
1 /** @file
2 This PEIM initialize platform for MRC, following action is performed,
3 1. Initizluize GMCH
4 2. Detect boot mode
5 3. Detect video adapter to determine whether we need pre allocated memory
6 4. Calls MRC to initialize memory and install a PPI notify to do post memory initialization.
7 This file contains the main entrypoint of the PEIM.
8
9 Copyright (c) 2013 Intel Corporation.
10
11 This program and the accompanying materials
12 are licensed and made available under the terms and conditions of the BSD License
13 which accompanies this distribution. The full text of the license may be found at
14 http://opensource.org/licenses/bsd-license.php
15
16 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
17 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18
19 **/
20
21
22 #include "CommonHeader.h"
23 #include "PlatformEarlyInit.h"
24 #include "PeiFvSecurity.h"
25
26 EFI_STATUS
27 EFIAPI
28 EndOfPeiSignalPpiNotifyCallback (
29 IN EFI_PEI_SERVICES **PeiServices,
30 IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
31 IN VOID *Ppi
32 );
33
34 //
35 // Function prototypes to routines implemented in other source modules
36 // within this component.
37 //
38
39 EFI_STATUS
40 EFIAPI
41 PlatformErratasPostMrc (
42 VOID
43 );
44
45 //
46 // The global indicator, the FvFileLoader callback will modify it to TRUE after loading PEIM into memory
47 //
48 BOOLEAN ImageInMemory = FALSE;
49
50 BOARD_LEGACY_GPIO_CONFIG mBoardLegacyGpioConfigTable[] = { PLATFORM_LEGACY_GPIO_TABLE_DEFINITION };
51 UINTN mBoardLegacyGpioConfigTableLen = (sizeof(mBoardLegacyGpioConfigTable) / sizeof(BOARD_LEGACY_GPIO_CONFIG));
52 BOARD_GPIO_CONTROLLER_CONFIG mBoardGpioControllerConfigTable[] = { PLATFORM_GPIO_CONTROLLER_CONFIG_DEFINITION };
53 UINTN mBoardGpioControllerConfigTableLen = (sizeof(mBoardGpioControllerConfigTable) / sizeof(BOARD_GPIO_CONTROLLER_CONFIG));
54 UINT8 ChipsetDefaultMac [6] = {0xff,0xff,0xff,0xff,0xff,0xff};
55
56 EFI_PEI_PPI_DESCRIPTOR mPpiBootMode[1] = {
57 {
58 (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
59 &gEfiPeiMasterBootModePpiGuid,
60 NULL
61 }
62 };
63
64 EFI_PEI_NOTIFY_DESCRIPTOR mMemoryDiscoveredNotifyList[1] = {
65 {
66 (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
67 &gEfiPeiMemoryDiscoveredPpiGuid,
68 MemoryDiscoveredPpiNotifyCallback
69 }
70 };
71
72 EFI_PEI_NOTIFY_DESCRIPTOR mEndOfPeiSignalPpiNotifyList[1] = {
73 {
74 (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
75 &gEfiEndOfPeiSignalPpiGuid,
76 EndOfPeiSignalPpiNotifyCallback
77 }
78 };
79
80 EFI_PEI_STALL_PPI mStallPpi = {
81 PEI_STALL_RESOLUTION,
82 Stall
83 };
84
85 EFI_PEI_PPI_DESCRIPTOR mPpiStall[1] = {
86 {
87 (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
88 &gEfiPeiStallPpiGuid,
89 &mStallPpi
90 }
91 };
92
93 /**
94 Set Mac address on chipset ethernet device.
95
96 @param Bus PCI Bus number of chipset ethernet device.
97 @param Device Device number of chipset ethernet device.
98 @param Func PCI Function number of chipset ethernet device.
99 @param MacAddr MAC Address to set.
100
101 **/
102 VOID
103 EFIAPI
104 SetLanControllerMacAddr (
105 IN CONST UINT8 Bus,
106 IN CONST UINT8 Device,
107 IN CONST UINT8 Func,
108 IN CONST UINT8 *MacAddr,
109 IN CONST UINT32 Bar0
110 )
111 {
112 UINT32 Data32;
113 UINT16 PciVid;
114 UINT16 PciDid;
115 UINT32 Addr;
116 UINT32 MacVer;
117 volatile UINT8 *Wrote;
118 UINT32 DevPcieAddr;
119 UINT16 SaveCmdReg;
120 UINT32 SaveBarReg;
121
122 DevPcieAddr = PCI_LIB_ADDRESS (
123 Bus,
124 Device,
125 Func,
126 0
127 );
128
129 //
130 // Do nothing if not a supported device.
131 //
132 PciVid = PciRead16 (DevPcieAddr + PCI_VENDOR_ID_OFFSET);
133 PciDid = PciRead16 (DevPcieAddr + PCI_DEVICE_ID_OFFSET);
134 if((PciVid != V_IOH_MAC_VENDOR_ID) || (PciDid != V_IOH_MAC_DEVICE_ID)) {
135 return;
136 }
137
138 //
139 // Save current settings for PCI CMD/BAR registers
140 //
141 SaveCmdReg = PciRead16 (DevPcieAddr + PCI_COMMAND_OFFSET);
142 SaveBarReg = PciRead32 (DevPcieAddr + R_IOH_MAC_MEMBAR);
143
144 //
145 // Use predefined tempory memory resource
146 //
147 PciWrite32 ( DevPcieAddr + R_IOH_MAC_MEMBAR, Bar0);
148 PciWrite8 ( DevPcieAddr + PCI_COMMAND_OFFSET, EFI_PCI_COMMAND_MEMORY_SPACE);
149
150 Addr = Bar0 + R_IOH_MAC_GMAC_REG_8;
151 MacVer = *((volatile UINT32 *) (UINTN)(Addr));
152
153 DEBUG ((EFI_D_INFO, "Ioh MAC [B:%d, D:%d, F:%d] VER:%04x ADDR:",
154 (UINTN) Bus,
155 (UINTN) Device,
156 (UINTN) Func,
157 (UINTN) MacVer
158 ));
159
160 //
161 // Set MAC Address0 Low Register (GMAC_REG_17) ADDRLO bits.
162 //
163 Addr = Bar0 + R_IOH_MAC_GMAC_REG_17;
164 Data32 = *((UINT32 *) (UINTN)(&MacAddr[0]));
165 *((volatile UINT32 *) (UINTN)(Addr)) = Data32;
166 Wrote = (volatile UINT8 *) (UINTN)(Addr);
167 DEBUG ((EFI_D_INFO, "%02x-%02x-%02x-%02x-",
168 (UINTN) Wrote[0],
169 (UINTN) Wrote[1],
170 (UINTN) Wrote[2],
171 (UINTN) Wrote[3]
172 ));
173
174 //
175 // Set MAC Address0 High Register (GMAC_REG_16) ADDRHI bits
176 // and Address Enable (AE) bit.
177 //
178 Addr = Bar0 + R_IOH_MAC_GMAC_REG_16;
179 Data32 =
180 ((UINT32) MacAddr[4]) |
181 (((UINT32)MacAddr[5]) << 8) |
182 B_IOH_MAC_AE;
183 *((volatile UINT32 *) (UINTN)(Addr)) = Data32;
184 Wrote = (volatile UINT8 *) (UINTN)(Addr);
185
186 DEBUG ((EFI_D_INFO, "%02x-%02x\n", (UINTN) Wrote[0], (UINTN) Wrote[1]));
187
188 //
189 // Restore settings for PCI CMD/BAR registers
190 //
191 PciWrite32 ((DevPcieAddr + R_IOH_MAC_MEMBAR), SaveBarReg);
192 PciWrite16 (DevPcieAddr + PCI_COMMAND_OFFSET, SaveCmdReg);
193 }
194
195 /**
196 This is the entrypoint of PEIM
197
198 @param FileHandle Handle of the file being invoked.
199 @param PeiServices Describes the list of possible PEI Services.
200
201 @retval EFI_SUCCESS if it completed successfully.
202 **/
203 EFI_STATUS
204 EFIAPI
205 PeiInitPlatform (
206 IN EFI_PEI_FILE_HANDLE FileHandle,
207 IN CONST EFI_PEI_SERVICES **PeiServices
208 )
209 {
210 EFI_STATUS Status;
211 EFI_BOOT_MODE BootMode;
212 EFI_PEI_STALL_PPI *StallPpi;
213 EFI_PEI_PPI_DESCRIPTOR *StallPeiPpiDescriptor;
214 EFI_FV_FILE_INFO FileInfo;
215 EFI_PLATFORM_TYPE PlatformType;
216
217 PlatformType = (EFI_PLATFORM_TYPE)PcdGet16 (PcdPlatformType);
218
219 //
220 // Initialize Firmware Volume security.
221 // This must be done before any firmware volume accesses (excl. BFV)
222 //
223 Status = PeiInitializeFvSecurity();
224 ASSERT_EFI_ERROR (Status);
225
226 //
227 // Do any early platform specific initialization.
228 //
229 EarlyPlatformInit ();
230
231 //
232 // This is a second path on entry, in recovery boot path the Stall PPI need to be memory-based
233 // to improve recovery performance.
234 //
235 Status = PeiServicesFfsGetFileInfo (FileHandle, &FileInfo);
236 ASSERT_EFI_ERROR (Status);
237 //
238 // The follow conditional check only works for memory-mapped FFS,
239 // so we ASSERT that the file is really a MM FFS.
240 //
241 ASSERT (FileInfo.Buffer != NULL);
242 if (!(((UINTN) FileInfo.Buffer <= (UINTN) PeiInitPlatform) &&
243 ((UINTN) PeiInitPlatform <= (UINTN) FileInfo.Buffer + FileInfo.BufferSize))) {
244 //
245 // Now that module in memory, update the
246 // PPI that describes the Stall to other modules
247 //
248 Status = PeiServicesLocatePpi (
249 &gEfiPeiStallPpiGuid,
250 0,
251 &StallPeiPpiDescriptor,
252 (VOID **) &StallPpi
253 );
254
255 if (!EFI_ERROR (Status)) {
256
257 Status = PeiServicesReInstallPpi (
258 StallPeiPpiDescriptor,
259 &mPpiStall[0]
260 );
261 } else {
262
263 Status = PeiServicesInstallPpi (&mPpiStall[0]);
264 }
265 return Status;
266 }
267
268 //
269 // Initialize System Phys
270 //
271
272 // Program USB Phy
273 InitializeUSBPhy();
274
275 //
276 // Do platform specific logic to create a boot mode
277 //
278 Status = UpdateBootMode ((EFI_PEI_SERVICES**)PeiServices, &BootMode);
279 ASSERT_EFI_ERROR (Status);
280
281 //
282 // Signal possible dependent modules that there has been a
283 // final boot mode determination
284 //
285 if (!EFI_ERROR(Status)) {
286 Status = PeiServicesInstallPpi (&mPpiBootMode[0]);
287 ASSERT_EFI_ERROR (Status);
288 }
289
290 if (BootMode != BOOT_ON_S3_RESUME) {
291 QNCClearSmiAndWake ();
292 }
293
294 DEBUG ((EFI_D_INFO, "MRC Entry\n"));
295 MemoryInit ((EFI_PEI_SERVICES**)PeiServices);
296
297 //
298 // Do Early PCIe init.
299 //
300 DEBUG ((EFI_D_INFO, "Early PCIe controller initialization\n"));
301 PlatformPciExpressEarlyInit (PlatformType);
302
303
304 DEBUG ((EFI_D_INFO, "Platform Erratas After MRC\n"));
305 PlatformErratasPostMrc ();
306
307 //
308 // Now that all of the pre-permanent memory activities have
309 // been taken care of, post a call-back for the permanent-memory
310 // resident services, such as HOB construction.
311 // PEI Core will switch stack after this PEIM exit. After that the MTRR
312 // can be set.
313 //
314 Status = PeiServicesNotifyPpi (&mMemoryDiscoveredNotifyList[0]);
315 ASSERT_EFI_ERROR (Status);
316 /*
317
318 if (BootMode != BOOT_ON_S3_RESUME) {
319 Status = PeiServicesNotifyPpi (mEndOfPeiSignalPpiNotifyList);
320 ASSERT_EFI_ERROR (Status);
321 }
322 */
323 if (BootMode == BOOT_IN_RECOVERY_MODE) {
324 PeiServicesRegisterForShadow (FileHandle);
325 }
326
327 return Status;
328 }
329
330 EFI_STATUS
331 EFIAPI
332 EndOfPeiSignalPpiNotifyCallback (
333 IN EFI_PEI_SERVICES **PeiServices,
334 IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
335 IN VOID *Ppi
336 )
337 {
338 EFI_STATUS Status;
339
340 DEBUG ((EFI_D_INFO, "End of PEI Signal Callback\n"));
341
342 //
343 // Restore the flash region to be UC
344 // for both normal boot as we build a Resource Hob to
345 // describe this region as UC to DXE core.
346 //
347 WriteBackInvalidateDataCacheRange (
348 (VOID *) (UINTN) PcdGet32 (PcdFlashAreaBaseAddress),
349 PcdGet32 (PcdFlashAreaSize)
350 );
351
352 Status = MtrrSetMemoryAttribute (PcdGet32 (PcdFlashAreaBaseAddress), PcdGet32 (PcdFlashAreaSize), CacheUncacheable);
353 ASSERT_EFI_ERROR (Status);
354
355 return EFI_SUCCESS;
356 }
357
358 /**
359 This function will initialize USB Phy registers associated with QuarkSouthCluster.
360
361 @param VOID No Argument
362
363 @retval EFI_SUCCESS All registers have been initialized
364 **/
365 VOID
366 EFIAPI
367 InitializeUSBPhy (
368 VOID
369 )
370 {
371 UINT32 RegData32;
372
373 /** In order to configure the PHY to use clk120 (ickusbcoreclk) as PLL reference clock
374 * and Port2 as a USB device port, the following sequence must be followed
375 *
376 **/
377
378 // Sideband register write to USB AFE (Phy)
379 RegData32 = QNCAltPortRead (QUARK_SC_USB_AFE_SB_PORT_ID, USB2_GLOBAL_PORT);
380 RegData32 &= ~(BIT1);
381 //
382 // Sighting #4930631 PDNRESCFG [8:7] of USB2_GLOBAL_PORT = 11b.
383 // For port 0 & 1 as host and port 2 as device.
384 //
385 RegData32 |= (BIT8 | BIT7);
386 QNCAltPortWrite (QUARK_SC_USB_AFE_SB_PORT_ID, USB2_GLOBAL_PORT, RegData32);
387
388 //
389 // Sighting #4930653 Required BIOS change on Disconnect vref to change to 600mV.
390 //
391 RegData32 = QNCAltPortRead (QUARK_SC_USB_AFE_SB_PORT_ID, USB2_COMPBG);
392 RegData32 &= ~(BIT10 | BIT9 | BIT8 | BIT7);
393 RegData32 |= (BIT10 | BIT7);
394 QNCAltPortWrite (QUARK_SC_USB_AFE_SB_PORT_ID, USB2_COMPBG, RegData32);
395
396 // Sideband register write to USB AFE (Phy)
397 // (pllbypass) to bypass/Disable PLL before switch
398 RegData32 = QNCAltPortRead (QUARK_SC_USB_AFE_SB_PORT_ID, USB2_PLL2);
399 RegData32 |= BIT29;
400 QNCAltPortWrite (QUARK_SC_USB_AFE_SB_PORT_ID, USB2_PLL2, RegData32);
401
402 // Sideband register write to USB AFE (Phy)
403 // (coreclksel) to select 120MHz (ickusbcoreclk) clk source.
404 // (Default 0 to select 96MHz (ickusbclk96_npad/ppad))
405 RegData32 = QNCAltPortRead (QUARK_SC_USB_AFE_SB_PORT_ID, USB2_PLL1);
406 RegData32 |= BIT1;
407 QNCAltPortWrite (QUARK_SC_USB_AFE_SB_PORT_ID, USB2_PLL1, RegData32);
408
409 // Sideband register write to USB AFE (Phy)
410 // (divide by 8) to achieve internal 480MHz clock
411 // for 120MHz input refclk. (Default: 4'b1000 (divide by 10) for 96MHz)
412 RegData32 = QNCAltPortRead (QUARK_SC_USB_AFE_SB_PORT_ID, USB2_PLL1);
413 RegData32 &= ~(BIT5 | BIT4 | BIT3);
414 RegData32 |= BIT6;
415 QNCAltPortWrite (QUARK_SC_USB_AFE_SB_PORT_ID, USB2_PLL1, RegData32);
416
417 // Sideband register write to USB AFE (Phy)
418 // Clear (pllbypass)
419 RegData32 = QNCAltPortRead (QUARK_SC_USB_AFE_SB_PORT_ID, USB2_PLL2);
420 RegData32 &= ~BIT29;
421 QNCAltPortWrite (QUARK_SC_USB_AFE_SB_PORT_ID, USB2_PLL2, RegData32);
422
423 // Sideband register write to USB AFE (Phy)
424 // Set (startlock) to force the PLL FSM to restart the lock
425 // sequence due to input clock/freq switch.
426 RegData32 = QNCAltPortRead (QUARK_SC_USB_AFE_SB_PORT_ID, USB2_PLL2);
427 RegData32 |= BIT24;
428 QNCAltPortWrite (QUARK_SC_USB_AFE_SB_PORT_ID, USB2_PLL2, RegData32);
429
430 // At this point the PLL FSM and COMP FSM will complete
431
432 }
433
434 /**
435 This function provides early platform Thermal sensor initialisation.
436 **/
437 VOID
438 EFIAPI
439 EarlyPlatformThermalSensorInit (
440 VOID
441 )
442 {
443 DEBUG ((EFI_D_INFO, "Early Platform Thermal Sensor Init\n"));
444
445 //
446 // Set Thermal sensor mode.
447 //
448 QNCThermalSensorSetRatiometricMode ();
449
450 //
451 // Enable RMU Thermal sensor with a Catastrophic Trip point.
452 //
453 QNCThermalSensorEnableWithCatastrophicTrip (PLATFORM_CATASTROPHIC_TRIP_CELSIUS);
454
455 //
456 // Lock all RMU Thermal sensor control & trip point registers.
457 //
458 QNCThermalSensorLockAllRegisters ();
459 }
460
461 /**
462 Print early platform info messages includeing the Stage1 module that's
463 running, MFH item list and platform data item list.
464 **/
465 VOID
466 EFIAPI
467 EarlyPlatformInfoMessages (
468 VOID
469 )
470 {
471 DEBUG_CODE_BEGIN ();
472 QUARK_EDKII_STAGE1_HEADER *Edk2ImageHeader;
473
474 //
475 // Find which 'Stage1' image we are running and print the details
476 //
477 Edk2ImageHeader = (QUARK_EDKII_STAGE1_HEADER *) PcdGet32 (PcdEsramStage1Base);
478 DEBUG ((EFI_D_INFO, "\n************************************************************\n"));
479
480 switch ((UINT8)Edk2ImageHeader->ImageIndex & QUARK_STAGE1_IMAGE_TYPE_MASK) {
481 case QUARK_STAGE1_BOOT_IMAGE_TYPE:
482 DEBUG ((EFI_D_INFO, "**** Quark EDKII Stage 1 Boot Image %d ****\n", ((UINT8)Edk2ImageHeader->ImageIndex & ~(QUARK_STAGE1_IMAGE_TYPE_MASK))));
483 break;
484
485 case QUARK_STAGE1_RECOVERY_IMAGE_TYPE:
486 DEBUG ((EFI_D_INFO, "**** Quark EDKII Stage 1 Recovery Image %d ****\n", ((UINT8)Edk2ImageHeader->ImageIndex & ~(QUARK_STAGE1_IMAGE_TYPE_MASK))));
487 break;
488
489 default:
490 DEBUG ((EFI_D_INFO, "**** Quark EDKII Unknown Stage 1 Image !!!! ****\n"));
491 break;
492 }
493 DEBUG (
494 (EFI_D_INFO,
495 "**** Quark EDKII Stage 2 Image 0x%08X:0x%08X ****\n" ,
496 (UINTN) PcdGet32 (PcdFlashFvMainBase),
497 (UINTN) PcdGet32 (PcdFlashFvMainSize)
498 ));
499
500 DEBUG (
501 (EFI_D_INFO,
502 "**** Quark EDKII Payload Image 0x%08X:0x%08X ****\n" ,
503 (UINTN) PcdGet32 (PcdFlashFvPayloadBase),
504 (UINTN) PcdGet32 (PcdFlashFvPayloadSize)
505 ));
506
507 DEBUG ((EFI_D_INFO, "************************************************************\n\n"));
508
509 DEBUG_CODE_END ();
510 }
511
512 /**
513 Check if system reset due to error condition.
514
515 @param ClearErrorBits If TRUE clear error flags and value bits.
516
517 @retval TRUE if system reset due to error condition.
518 @retval FALSE if NO reset error conditions.
519 **/
520 BOOLEAN
521 CheckForResetDueToErrors (
522 IN BOOLEAN ClearErrorBits
523 )
524 {
525 UINT32 RegValue;
526 BOOLEAN ResetDueToError;
527
528 ResetDueToError = FALSE;
529
530 //
531 // Check if RMU reset system due to access violations.
532 // RMU updates a SOC Unit register before reseting the system.
533 //
534 RegValue = QNCAltPortRead (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_CFG_STICKY_RW);
535 if ((RegValue & B_CFG_STICKY_RW_VIOLATION) != 0) {
536 ResetDueToError = TRUE;
537
538 DEBUG (
539 (EFI_D_ERROR,
540 "\nReset due to access violation: %s %s %s %s\n",
541 ((RegValue & B_CFG_STICKY_RW_IMR_VIOLATION) != 0) ? L"'IMR'" : L".",
542 ((RegValue & B_CFG_STICKY_RW_DECC_VIOLATION) != 0) ? L"'DECC'" : L".",
543 ((RegValue & B_CFG_STICKY_RW_SMM_VIOLATION) != 0) ? L"'SMM'" : L".",
544 ((RegValue & B_CFG_STICKY_RW_HMB_VIOLATION) != 0) ? L"'HMB'" : L"."
545 ));
546
547 //
548 // Clear error bits.
549 //
550 if (ClearErrorBits) {
551 RegValue &= ~(B_CFG_STICKY_RW_VIOLATION);
552 QNCAltPortWrite (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_CFG_STICKY_RW, RegValue);
553 }
554 }
555
556 return ResetDueToError;
557 }
558
559 /**
560 This function provides early platform initialization.
561
562 @param PlatformInfo Pointer to platform Info structure.
563
564 **/
565 VOID
566 EFIAPI
567 EarlyPlatformInit (
568 VOID
569 )
570 {
571 EFI_PLATFORM_TYPE PlatformType;
572
573 PlatformType = (EFI_PLATFORM_TYPE) PcdGet16 (PcdPlatformType);
574
575 DEBUG ((EFI_D_INFO, "EarlyPlatformInit for PlatType=0x%02x\n", (UINTN) PlatformType));
576
577 //
578 // Check if system reset due to error condition.
579 //
580 if (CheckForResetDueToErrors (TRUE)) {
581 if(FeaturePcdGet (WaitIfResetDueToError)) {
582 DEBUG ((EFI_D_ERROR, "Press any key to continue.\n"));
583 PlatformDebugPortGetChar8 ();
584 }
585 }
586
587 //
588 // Display platform info messages.
589 //
590 EarlyPlatformInfoMessages ();
591
592 //
593 // Early Legacy Gpio Init.
594 //
595 EarlyPlatformLegacyGpioInit (PlatformType);
596
597 //
598 // Early platform Legacy GPIO manipulation depending on GPIOs
599 // setup by EarlyPlatformLegacyGpioInit.
600 //
601 EarlyPlatformLegacyGpioManipulation (PlatformType);
602
603 //
604 // Early platform specific GPIO Controller init & manipulation.
605 // Combined for sharing of temp. memory bar.
606 //
607 EarlyPlatformGpioCtrlerInitAndManipulation (PlatformType);
608
609 //
610 // Early Thermal Sensor Init.
611 //
612 EarlyPlatformThermalSensorInit ();
613
614 //
615 // Early Lan Ethernet Mac Init.
616 //
617 EarlyPlatformMacInit (
618 PcdGetPtr (PcdIohEthernetMac0),
619 PcdGetPtr (PcdIohEthernetMac1)
620 );
621 }
622
623 /**
624 This function provides early platform Legacy GPIO initialisation.
625
626 @param PlatformType Platform type for GPIO init.
627
628 **/
629 VOID
630 EFIAPI
631 EarlyPlatformLegacyGpioInit (
632 IN CONST EFI_PLATFORM_TYPE PlatformType
633 )
634 {
635 BOARD_LEGACY_GPIO_CONFIG *LegacyGpioConfig;
636 UINT32 NewValue;
637 UINT32 GpioBaseAddress;
638
639 //
640 // Assert if platform type outside table range.
641 //
642 ASSERT ((UINTN) PlatformType < mBoardLegacyGpioConfigTableLen);
643 LegacyGpioConfig = &mBoardLegacyGpioConfigTable[(UINTN) PlatformType];
644
645 GpioBaseAddress = (UINT32)PcdGet16 (PcdGbaIoBaseAddress);
646
647 NewValue = 0x0;
648 //
649 // Program QNC GPIO Registers.
650 //
651 NewValue = (IoRead32 (GpioBaseAddress + R_QNC_GPIO_CGEN_CORE_WELL) & 0xFFFFFFFC) | LegacyGpioConfig->CoreWellEnable;
652 IoWrite32 (GpioBaseAddress + R_QNC_GPIO_CGEN_CORE_WELL, NewValue );
653 NewValue = (IoRead32 (GpioBaseAddress + R_QNC_GPIO_CGIO_CORE_WELL) & 0xFFFFFFFC) | LegacyGpioConfig->CoreWellIoSelect;
654 IoWrite32 (GpioBaseAddress + R_QNC_GPIO_CGIO_CORE_WELL, NewValue);
655 NewValue = (IoRead32 (GpioBaseAddress + R_QNC_GPIO_CGLVL_CORE_WELL) & 0xFFFFFFFC) | LegacyGpioConfig->CoreWellLvlForInputOrOutput;
656 IoWrite32 (GpioBaseAddress + R_QNC_GPIO_CGLVL_CORE_WELL, NewValue);
657 NewValue = (IoRead32 (GpioBaseAddress + R_QNC_GPIO_CGTPE_CORE_WELL) & 0xFFFFFFFC) | LegacyGpioConfig->CoreWellTriggerPositiveEdge;
658 IoWrite32 (GpioBaseAddress + R_QNC_GPIO_CGTPE_CORE_WELL, NewValue );
659 NewValue = (IoRead32 (GpioBaseAddress + R_QNC_GPIO_CGTNE_CORE_WELL) & 0xFFFFFFFC) | LegacyGpioConfig->CoreWellTriggerNegativeEdge;
660 IoWrite32 (GpioBaseAddress + R_QNC_GPIO_CGTNE_CORE_WELL, NewValue);
661 NewValue = (IoRead32 (GpioBaseAddress + R_QNC_GPIO_CGGPE_CORE_WELL) & 0xFFFFFFFC) | LegacyGpioConfig->CoreWellGPEEnable;
662 IoWrite32 (GpioBaseAddress + R_QNC_GPIO_CGGPE_CORE_WELL, NewValue);
663 NewValue = (IoRead32 (GpioBaseAddress + R_QNC_GPIO_CGSMI_CORE_WELL) & 0xFFFFFFFC) | LegacyGpioConfig->CoreWellSMIEnable;
664 IoWrite32 (GpioBaseAddress + R_QNC_GPIO_CGSMI_CORE_WELL, NewValue );
665 NewValue = (IoRead32 (GpioBaseAddress + R_QNC_GPIO_CGTS_CORE_WELL) & 0xFFFFFFFC) | LegacyGpioConfig->CoreWellTriggerStatus;
666 IoWrite32 (GpioBaseAddress + R_QNC_GPIO_CGTS_CORE_WELL, NewValue);
667 NewValue = (IoRead32 (GpioBaseAddress + R_QNC_GPIO_CNMIEN_CORE_WELL) & 0xFFFFFFFC) | LegacyGpioConfig->CoreWellNMIEnable;
668 IoWrite32 (GpioBaseAddress + R_QNC_GPIO_CNMIEN_CORE_WELL, NewValue);
669
670 NewValue = (IoRead32 (GpioBaseAddress + R_QNC_GPIO_RGEN_RESUME_WELL) & 0xFFFFFFC0) | LegacyGpioConfig->ResumeWellEnable;
671 IoWrite32 (GpioBaseAddress + R_QNC_GPIO_RGEN_RESUME_WELL, NewValue );
672 NewValue = (IoRead32 (GpioBaseAddress + R_QNC_GPIO_RGIO_RESUME_WELL) & 0xFFFFFFC0) | LegacyGpioConfig->ResumeWellIoSelect;
673 IoWrite32 (GpioBaseAddress + R_QNC_GPIO_RGIO_RESUME_WELL, NewValue) ;
674 NewValue = (IoRead32 (GpioBaseAddress + R_QNC_GPIO_RGLVL_RESUME_WELL) & 0xFFFFFFC0) | LegacyGpioConfig->ResumeWellLvlForInputOrOutput;
675 IoWrite32 (GpioBaseAddress + R_QNC_GPIO_RGLVL_RESUME_WELL, NewValue);
676 NewValue = (IoRead32 (GpioBaseAddress + R_QNC_GPIO_RGTPE_RESUME_WELL) & 0xFFFFFFC0) | LegacyGpioConfig->ResumeWellTriggerPositiveEdge;
677 IoWrite32 (GpioBaseAddress + R_QNC_GPIO_RGTPE_RESUME_WELL, NewValue );
678 NewValue = (IoRead32 (GpioBaseAddress + R_QNC_GPIO_RGTNE_RESUME_WELL) & 0xFFFFFFC0) | LegacyGpioConfig->ResumeWellTriggerNegativeEdge;
679 IoWrite32 (GpioBaseAddress + R_QNC_GPIO_RGTNE_RESUME_WELL, NewValue) ;
680 NewValue = (IoRead32 (GpioBaseAddress + R_QNC_GPIO_RGGPE_RESUME_WELL) & 0xFFFFFFC0) | LegacyGpioConfig->ResumeWellGPEEnable;
681 IoWrite32 (GpioBaseAddress + R_QNC_GPIO_RGGPE_RESUME_WELL, NewValue);
682 NewValue = (IoRead32 (GpioBaseAddress + R_QNC_GPIO_RGSMI_RESUME_WELL) & 0xFFFFFFC0) | LegacyGpioConfig->ResumeWellSMIEnable;
683 IoWrite32 (GpioBaseAddress + R_QNC_GPIO_RGSMI_RESUME_WELL, NewValue );
684 NewValue = (IoRead32 (GpioBaseAddress + R_QNC_GPIO_RGTS_RESUME_WELL) & 0xFFFFFFC0) | LegacyGpioConfig->ResumeWellTriggerStatus;
685 IoWrite32 (GpioBaseAddress + R_QNC_GPIO_RGTS_RESUME_WELL, NewValue) ;
686 NewValue = (IoRead32 (GpioBaseAddress + R_QNC_GPIO_RNMIEN_RESUME_WELL) & 0xFFFFFFC0) | LegacyGpioConfig->ResumeWellNMIEnable;
687 IoWrite32 (GpioBaseAddress + R_QNC_GPIO_RNMIEN_RESUME_WELL, NewValue);
688 }
689
690 /**
691 Performs any early platform specific Legacy GPIO manipulation.
692
693 @param PlatformType Platform type GPIO manipulation.
694
695 **/
696 VOID
697 EFIAPI
698 EarlyPlatformLegacyGpioManipulation (
699 IN CONST EFI_PLATFORM_TYPE PlatformType
700 )
701 {
702 if (PlatformType == CrossHill) {
703
704 //
705 // Pull TPM reset low for 80us (equivalent to cold reset, Table 39
706 // Infineon SLB9645 Databook), then pull TPM reset high and wait for
707 // 150ms to give time for TPM to stabilise (Section 4.7.1 Infineon
708 // SLB9645 Databook states TPM is ready to receive command after 30ms
709 // but section 4.7 states some TPM commands may take longer to execute
710 // upto 150ms after test).
711 //
712
713 PlatformLegacyGpioSetLevel (
714 R_QNC_GPIO_RGLVL_RESUME_WELL,
715 PLATFORM_RESUMEWELL_TPM_RST_GPIO,
716 FALSE
717 );
718 MicroSecondDelay (80);
719
720 PlatformLegacyGpioSetLevel (
721 R_QNC_GPIO_RGLVL_RESUME_WELL,
722 PLATFORM_RESUMEWELL_TPM_RST_GPIO,
723 TRUE
724 );
725 MicroSecondDelay (150000);
726 }
727
728 }
729
730 /**
731 Performs any early platform specific GPIO Controller init & manipulation.
732
733 @param PlatformType Platform type for GPIO init & manipulation.
734
735 **/
736 VOID
737 EFIAPI
738 EarlyPlatformGpioCtrlerInitAndManipulation (
739 IN CONST EFI_PLATFORM_TYPE PlatformType
740 )
741 {
742 UINT32 IohGpioBase;
743 UINT32 Data32;
744 UINT32 Addr;
745 BOARD_GPIO_CONTROLLER_CONFIG *GpioConfig;
746 UINT32 DevPcieAddr;
747 UINT16 SaveCmdReg;
748 UINT32 SaveBarReg;
749 UINT16 PciVid;
750 UINT16 PciDid;
751
752 ASSERT ((UINTN) PlatformType < mBoardGpioControllerConfigTableLen);
753 GpioConfig = &mBoardGpioControllerConfigTable[(UINTN) PlatformType];
754
755 IohGpioBase = (UINT32) PcdGet64 (PcdIohGpioMmioBase);
756
757 DevPcieAddr = PCI_LIB_ADDRESS (
758 PcdGet8 (PcdIohGpioBusNumber),
759 PcdGet8 (PcdIohGpioDevNumber),
760 PcdGet8 (PcdIohGpioFunctionNumber),
761 0
762 );
763
764 //
765 // Do nothing if not a supported device.
766 //
767 PciVid = PciRead16 (DevPcieAddr + PCI_VENDOR_ID_OFFSET);
768 PciDid = PciRead16 (DevPcieAddr + PCI_DEVICE_ID_OFFSET);
769 if((PciVid != V_IOH_I2C_GPIO_VENDOR_ID) || (PciDid != V_IOH_I2C_GPIO_DEVICE_ID)) {
770 return;
771 }
772
773 //
774 // Save current settings for PCI CMD/BAR registers.
775 //
776 SaveCmdReg = PciRead16 (DevPcieAddr + PCI_COMMAND_OFFSET);
777 SaveBarReg = PciRead32 (DevPcieAddr + PcdGet8 (PcdIohGpioBarRegister));
778
779 //
780 // Use predefined tempory memory resource.
781 //
782 PciWrite32 ( DevPcieAddr + PcdGet8 (PcdIohGpioBarRegister), IohGpioBase);
783 PciWrite8 ( DevPcieAddr + PCI_COMMAND_OFFSET, EFI_PCI_COMMAND_MEMORY_SPACE);
784
785 //
786 // Gpio Controller Init Tasks.
787 //
788
789 //
790 // IEN- Interrupt Enable Register
791 //
792 Addr = IohGpioBase + GPIO_INTEN;
793 Data32 = *((volatile UINT32 *) (UINTN)(Addr)) & 0xFFFFFF00; // Keep reserved bits [31:8]
794 Data32 |= (GpioConfig->IntEn & 0x000FFFFF);
795 *((volatile UINT32 *) (UINTN)(Addr)) = Data32;
796
797 //
798 // ISTATUS- Interrupt Status Register
799 //
800 Addr = IohGpioBase + GPIO_INTSTATUS;
801 Data32 = *((volatile UINT32 *) (UINTN)(Addr)) & 0xFFFFFF00; // Keep reserved bits [31:8]
802 *((volatile UINT32 *) (UINTN)(Addr)) = Data32;
803
804 //
805 // GPIO SWPORTA Direction Register - GPIO_SWPORTA_DR
806 //
807 Addr = IohGpioBase + GPIO_SWPORTA_DR;
808 Data32 = *((volatile UINT32 *) (UINTN)(Addr)) & 0xFFFFFF00; // Keep reserved bits [31:8]
809 Data32 |= (GpioConfig->PortADR & 0x000FFFFF);
810 *((volatile UINT32 *) (UINTN)(Addr)) = Data32;
811
812 //
813 // GPIO SWPORTA Data Direction Register - GPIO_SWPORTA_DDR - default input
814 //
815 Addr = IohGpioBase + GPIO_SWPORTA_DDR;
816 Data32 = *((volatile UINT32 *) (UINTN)(Addr)) & 0xFFFFFF00; // Keep reserved bits [31:8]
817 Data32 |= (GpioConfig->PortADir & 0x000FFFFF);
818 *((volatile UINT32 *) (UINTN)(Addr)) = Data32;
819
820 //
821 // Interrupt Mask Register - GPIO_INTMASK - default interrupts unmasked
822 //
823 Addr = IohGpioBase + GPIO_INTMASK;
824 Data32 = *((volatile UINT32 *) (UINTN)(Addr)) & 0xFFFFFF00; // Keep reserved bits [31:8]
825 Data32 |= (GpioConfig->IntMask & 0x000FFFFF);
826 *((volatile UINT32 *) (UINTN)(Addr)) = Data32;
827
828 //
829 // Interrupt Level Type Register - GPIO_INTTYPE_LEVEL - default is level sensitive
830 //
831 Addr = IohGpioBase + GPIO_INTTYPE_LEVEL;
832 Data32 = *((volatile UINT32 *) (UINTN)(Addr)) & 0xFFFFFF00; // Keep reserved bits [31:8]
833 Data32 |= (GpioConfig->IntType & 0x000FFFFF);
834 *((volatile UINT32 *) (UINTN)(Addr)) = Data32;
835
836 //
837 // Interrupt Polarity Type Register - GPIO_INT_POLARITY - default is active low
838 //
839 Addr = IohGpioBase + GPIO_INT_POLARITY;
840 Data32 = *((volatile UINT32 *) (UINTN)(Addr)) & 0xFFFFFF00; // Keep reserved bits [31:8]
841 Data32 |= (GpioConfig->IntPolarity & 0x000FFFFF);
842 *((volatile UINT32 *) (UINTN)(Addr)) = Data32;
843
844 //
845 // Interrupt Debounce Type Register - GPIO_DEBOUNCE - default no debounce
846 //
847 Addr = IohGpioBase + GPIO_DEBOUNCE;
848 Data32 = *((volatile UINT32 *) (UINTN)(Addr)) & 0xFFFFFF00; // Keep reserved bits [31:8]
849 Data32 |= (GpioConfig->Debounce & 0x000FFFFF);
850 *((volatile UINT32 *) (UINTN)(Addr)) = Data32;
851
852 //
853 // Interrupt Clock Synchronisation Register - GPIO_LS_SYNC - default no sync with pclk_intr(APB bus clk)
854 //
855 Addr = IohGpioBase + GPIO_LS_SYNC;
856 Data32 = *((volatile UINT32 *) (UINTN)(Addr)) & 0xFFFFFF00; // Keep reserved bits [31:8]
857 Data32 |= (GpioConfig->LsSync & 0x000FFFFF);
858 *((volatile UINT32 *) (UINTN)(Addr)) = Data32;
859
860 //
861 // Gpio Controller Manipulation Tasks.
862 //
863
864 if (PlatformType == (EFI_PLATFORM_TYPE) Galileo) {
865 //
866 // Reset Cypress Expander on Galileo Platform
867 //
868 Addr = IohGpioBase + GPIO_SWPORTA_DR;
869 Data32 = *((volatile UINT32 *) (UINTN)(Addr));
870 Data32 |= BIT4; // Cypress Reset line controlled by GPIO<4>
871 *((volatile UINT32 *) (UINTN)(Addr)) = Data32;
872
873 Data32 = *((volatile UINT32 *) (UINTN)(Addr));
874 Data32 &= ~BIT4; // Cypress Reset line controlled by GPIO<4>
875 *((volatile UINT32 *) (UINTN)(Addr)) = Data32;
876
877 }
878
879 //
880 // Restore settings for PCI CMD/BAR registers
881 //
882 PciWrite32 ((DevPcieAddr + PcdGet8 (PcdIohGpioBarRegister)), SaveBarReg);
883 PciWrite16 (DevPcieAddr + PCI_COMMAND_OFFSET, SaveCmdReg);
884 }
885
886 /**
887 Performs any early platform init of SoC Ethernet Mac devices.
888
889 @param IohMac0Address Mac address to program into Mac0 device.
890 @param IohMac1Address Mac address to program into Mac1 device.
891
892 **/
893 VOID
894 EFIAPI
895 EarlyPlatformMacInit (
896 IN CONST UINT8 *IohMac0Address,
897 IN CONST UINT8 *IohMac1Address
898 )
899 {
900 BOOLEAN SetMacAddr;
901
902 //
903 // Set chipset MAC0 address if configured.
904 //
905 SetMacAddr =
906 (CompareMem (ChipsetDefaultMac, IohMac0Address, sizeof (ChipsetDefaultMac))) != 0;
907 if (SetMacAddr) {
908 if ((*(IohMac0Address) & BIT0) != 0) {
909 DEBUG ((EFI_D_ERROR, "HALT: Multicast Mac Address configured for Ioh MAC [B:%d, D:%d, F:%d]\n",
910 (UINTN) IOH_MAC0_BUS_NUMBER,
911 (UINTN) IOH_MAC0_DEVICE_NUMBER,
912 (UINTN) IOH_MAC0_FUNCTION_NUMBER
913 ));
914 ASSERT (FALSE);
915 } else {
916 SetLanControllerMacAddr (
917 IOH_MAC0_BUS_NUMBER,
918 IOH_MAC0_DEVICE_NUMBER,
919 IOH_MAC0_FUNCTION_NUMBER,
920 IohMac0Address,
921 (UINT32) PcdGet64(PcdIohMac0MmioBase)
922 );
923 }
924 } else {
925 DEBUG ((EFI_D_WARN, "WARNING: Ioh MAC [B:%d, D:%d, F:%d] NO HW ADDR CONFIGURED!!!\n",
926 (UINTN) IOH_MAC0_BUS_NUMBER,
927 (UINTN) IOH_MAC0_DEVICE_NUMBER,
928 (UINTN) IOH_MAC0_FUNCTION_NUMBER
929 ));
930 }
931
932 //
933 // Set chipset MAC1 address if configured.
934 //
935 SetMacAddr =
936 (CompareMem (ChipsetDefaultMac, IohMac1Address, sizeof (ChipsetDefaultMac))) != 0;
937 if (SetMacAddr) {
938 if ((*(IohMac1Address) & BIT0) != 0) {
939 DEBUG ((EFI_D_ERROR, "HALT: Multicast Mac Address configured for Ioh MAC [B:%d, D:%d, F:%d]\n",
940 (UINTN) IOH_MAC1_BUS_NUMBER,
941 (UINTN) IOH_MAC1_DEVICE_NUMBER,
942 (UINTN) IOH_MAC1_FUNCTION_NUMBER
943 ));
944 ASSERT (FALSE);
945 } else {
946 SetLanControllerMacAddr (
947 IOH_MAC1_BUS_NUMBER,
948 IOH_MAC1_DEVICE_NUMBER,
949 IOH_MAC1_FUNCTION_NUMBER,
950 IohMac1Address,
951 (UINT32) PcdGet64(PcdIohMac1MmioBase)
952 );
953 }
954 } else {
955 DEBUG ((EFI_D_WARN, "WARNING: Ioh MAC [B:%d, D:%d, F:%d] NO HW ADDR CONFIGURED!!!\n",
956 (UINTN) IOH_MAC1_BUS_NUMBER,
957 (UINTN) IOH_MAC1_DEVICE_NUMBER,
958 (UINTN) IOH_MAC1_FUNCTION_NUMBER
959 ));
960 }
961 }
962
EFI Development Kit II mirror for PVE