2 Platform Erratas performed by early init PEIM driver.
4 Copyright (c) 2013 Intel Corporation.
6 This program and the accompanying materials
7 are licensed and made available under the terms and conditions of the BSD License
8 which accompanies this distribution. The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
16 #include "CommonHeader.h"
17 #include "PlatformEarlyInit.h"
24 // Platform EHCI Packet Buffer OUT/IN Thresholds, values in number of DWORDs.
26 #define EHCI_OUT_THRESHOLD_VALUE (0x7f)
27 #define EHCI_IN_THRESHOLD_VALUE (0x7f)
30 // Platform init USB device interrupt masks.
32 #define V_IOH_USBDEVICE_D_INTR_MSK_UDC_REG (0x0000007f)
33 #define V_IOH_USBDEVICE_EP_INTR_MSK_UDC_REG (B_IOH_USBDEVICE_EP_INTR_MSK_UDC_REG_OUT_EP_MASK | B_IOH_USBDEVICE_EP_INTR_MSK_UDC_REG_IN_EP_MASK)
36 // Global variables defined within this source module.
39 UINTN IohEhciPciReg
[IOH_MAX_EHCI_USB_CONTROLLERS
] = {
40 PCI_LIB_ADDRESS (IOH_USB_BUS_NUMBER
, IOH_USB_EHCI_DEVICE_NUMBER
, IOH_EHCI_FUNCTION_NUMBER
, 0),
43 UINTN IohUsbDevicePciReg
[IOH_MAX_USBDEVICE_USB_CONTROLLERS
] = {
44 PCI_LIB_ADDRESS (IOH_USB_BUS_NUMBER
, IOH_USBDEVICE_DEVICE_NUMBER
, IOH_USBDEVICE_FUNCTION_NUMBER
, 0),
48 // Routines local to this source module.
51 /** Perform USB erratas after MRC init.
55 PlatformUsbErratasPostMrc (
64 TempBar0Addr
= PcdGet32(PcdPeiQNCUsbControllerMemoryBaseAddress
);
67 // Apply EHCI controller erratas.
69 for (Index
= 0; Index
< IOH_MAX_EHCI_USB_CONTROLLERS
; Index
++, TempBar0Addr
+= IOH_USB_CONTROLLER_MMIO_RANGE
) {
71 if ((PciRead16 (IohEhciPciReg
[Index
] + R_IOH_USB_VENDOR_ID
)) != V_IOH_USB_VENDOR_ID
) {
72 continue; // Device not enabled, skip.
76 // Save current settings for PCI CMD/BAR0 registers
78 SaveCmdReg
= PciRead16 (IohEhciPciReg
[Index
] + R_IOH_USB_COMMAND
);
79 SaveBar0Reg
= PciRead32 (IohEhciPciReg
[Index
] + R_IOH_USB_MEMBAR
);
82 // Temp. assign base address register, Enable Memory Space.
84 PciWrite32 ((IohEhciPciReg
[Index
] + R_IOH_USB_MEMBAR
), TempBar0Addr
);
85 PciWrite16 (IohEhciPciReg
[Index
] + R_IOH_USB_COMMAND
, SaveCmdReg
| B_IOH_USB_COMMAND_MSE
);
89 // Set packet buffer OUT/IN thresholds.
92 TempBar0Addr
+ R_IOH_EHCI_INSNREG01
,
93 (UINT32
) (~(B_IOH_EHCI_INSNREG01_OUT_THRESHOLD_MASK
| B_IOH_EHCI_INSNREG01_IN_THRESHOLD_MASK
)),
94 (UINT32
) ((EHCI_OUT_THRESHOLD_VALUE
<< B_IOH_EHCI_INSNREG01_OUT_THRESHOLD_BP
) | (EHCI_IN_THRESHOLD_VALUE
<< B_IOH_EHCI_INSNREG01_IN_THRESHOLD_BP
))
98 // Restore settings for PCI CMD/BAR0 registers
100 PciWrite32 ((IohEhciPciReg
[Index
] + R_IOH_USB_MEMBAR
), SaveBar0Reg
);
101 PciWrite16 (IohEhciPciReg
[Index
] + R_IOH_USB_COMMAND
, SaveCmdReg
);
105 // Apply USB device controller erratas.
107 for (Index
= 0; Index
< IOH_MAX_USBDEVICE_USB_CONTROLLERS
; Index
++, TempBar0Addr
+= IOH_USB_CONTROLLER_MMIO_RANGE
) {
109 if ((PciRead16 (IohUsbDevicePciReg
[Index
] + R_IOH_USB_VENDOR_ID
)) != V_IOH_USB_VENDOR_ID
) {
110 continue; // Device not enabled, skip.
114 // Save current settings for PCI CMD/BAR0 registers
116 SaveCmdReg
= PciRead16 (IohUsbDevicePciReg
[Index
] + R_IOH_USB_COMMAND
);
117 SaveBar0Reg
= PciRead32 (IohUsbDevicePciReg
[Index
] + R_IOH_USB_MEMBAR
);
120 // Temp. assign base address register, Enable Memory Space.
122 PciWrite32 ((IohUsbDevicePciReg
[Index
] + R_IOH_USB_MEMBAR
), TempBar0Addr
);
123 PciWrite16 (IohUsbDevicePciReg
[Index
] + R_IOH_USB_COMMAND
, SaveCmdReg
| B_IOH_USB_COMMAND_MSE
);
126 // Erratas for USB Device interrupt registers.
130 // 1st Mask interrupts.
133 TempBar0Addr
+ R_IOH_USBDEVICE_D_INTR_MSK_UDC_REG
,
134 V_IOH_USBDEVICE_D_INTR_MSK_UDC_REG
137 // 2nd RW/1C of equivalent status bits.
140 TempBar0Addr
+ R_IOH_USBDEVICE_D_INTR_UDC_REG
,
141 V_IOH_USBDEVICE_D_INTR_MSK_UDC_REG
145 // 1st Mask end point interrupts.
148 TempBar0Addr
+ R_IOH_USBDEVICE_EP_INTR_MSK_UDC_REG
,
149 V_IOH_USBDEVICE_EP_INTR_MSK_UDC_REG
152 // 2nd RW/1C of equivalent end point status bits.
155 TempBar0Addr
+ R_IOH_USBDEVICE_EP_INTR_UDC_REG
,
156 V_IOH_USBDEVICE_EP_INTR_MSK_UDC_REG
160 // Restore settings for PCI CMD/BAR0 registers
162 PciWrite32 ((IohUsbDevicePciReg
[Index
] + R_IOH_USB_MEMBAR
), SaveBar0Reg
);
163 PciWrite16 (IohUsbDevicePciReg
[Index
] + R_IOH_USB_COMMAND
, SaveCmdReg
);
168 // Routines exported by this source module.
171 /** Perform Platform Erratas after MRC.
173 @retval EFI_SUCCESS Operation success.
178 PlatformErratasPostMrc (
182 PlatformUsbErratasPostMrc ();