]>
git.proxmox.com Git - mirror_edk2.git/blob - QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/io.h
2 Declaration of IO handling routines.
4 Copyright (c) 2013-2015 Intel Corporation.
6 SPDX-License-Identifier: BSD-2-Clause-Patent
12 #include "core_types.h"
14 #include "general_definitions.h"
15 #include "gen5_iosf_sb_definitions.h"
17 // Instruction not present on Quark
20 #define DEAD_LOOP() for(;;);
23 // Define each of the IOSF_SB ports used by MRC
27 // Has to be 0 because of emulation static data
29 // Space_t EmuSpace[ SPACE_COUNT] = {0};
33 // Pseudo side-band ports for access abstraction
34 // See Wr32/Rd32 functions
39 // Real side-band ports
40 // See Wr32/Rd32 functions
42 #define HOST_BRIDGE 0x003
43 #define MEMORY_MANAGER 0x005
48 // End of IOSF_SB ports
52 #define EC_BASE 0xE0000000
54 #define PCIADDR(bus,dev,fn,reg) ( \
61 // Various offsets used in the building sideband commands.
62 #define SB_OPCODE_OFFSET 24
63 #define SB_PORT_OFFSET 16
64 #define SB_REG_OFFEST 8
67 #define SB_REG_READ_OPCODE 0x10
68 #define SB_REG_WRITE_OPCODE 0x11
70 #define SB_FUSE_REG_READ_OPCODE 0x06
71 #define SB_FUSE_REG_WRITE_OPCODE 0x07
73 #define SB_DDRIO_REG_READ_OPCODE 0x06
74 #define SB_DDRIO_REG_WRITE_OPCODE 0x07
76 #define SB_DRAM_CMND_OPCODE 0x68
77 #define SB_WAKE_CMND_OPCODE 0xCA
78 #define SB_SUSPEND_CMND_OPCODE 0xCC
80 // Register addresses for sideband command and data.
81 #define SB_PACKET_REG 0x00D0
82 #define SB_DATA_REG 0x00D4
83 #define SB_HADR_REG 0x00D8
85 // We always flag all 4 bytes in the register reads/writes as required.
86 #define SB_ALL_BYTES_ENABLED 0xF0
88 #define SB_COMMAND(Opcode, Port, Reg) \
89 ((Opcode << SB_OPCODE_OFFSET) | \
90 (Port << SB_PORT_OFFSET) | \
91 (Reg << SB_REG_OFFEST) | \
95 #define isbM32m WrMask32