2 Main file for Pci shell Debug1 function.
4 Copyright (c) 2005 - 2021, Intel Corporation. All rights reserved.<BR>
5 (C) Copyright 2013-2015 Hewlett-Packard Development Company, L.P.<BR>
6 (C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>
7 SPDX-License-Identifier: BSD-2-Clause-Patent
11 #include "UefiShellDebug1CommandsLib.h"
12 #include <Protocol/PciRootBridgeIo.h>
13 #include <Library/ShellLib.h>
14 #include <IndustryStandard/Pci.h>
15 #include <IndustryStandard/Acpi.h>
19 // Printable strings for Pci class code
22 CHAR16
*BaseClass
; // Pointer to the PCI base class string
23 CHAR16
*SubClass
; // Pointer to the PCI sub class string
24 CHAR16
*PIFClass
; // Pointer to the PCI programming interface string
28 // a structure holding a single entry, which also points to its lower level
31 typedef struct PCI_CLASS_ENTRY_TAG
{
32 UINT8 Code
; // Class, subclass or I/F code
33 CHAR16
*DescText
; // Description string
34 struct PCI_CLASS_ENTRY_TAG
*LowerLevelClass
; // Subclass or I/F if any
38 // Declarations of entries which contain printable strings for class codes
39 // in PCI configuration space
41 PCI_CLASS_ENTRY PCIBlankEntry
[];
42 PCI_CLASS_ENTRY PCISubClass_00
[];
43 PCI_CLASS_ENTRY PCISubClass_01
[];
44 PCI_CLASS_ENTRY PCISubClass_02
[];
45 PCI_CLASS_ENTRY PCISubClass_03
[];
46 PCI_CLASS_ENTRY PCISubClass_04
[];
47 PCI_CLASS_ENTRY PCISubClass_05
[];
48 PCI_CLASS_ENTRY PCISubClass_06
[];
49 PCI_CLASS_ENTRY PCISubClass_07
[];
50 PCI_CLASS_ENTRY PCISubClass_08
[];
51 PCI_CLASS_ENTRY PCISubClass_09
[];
52 PCI_CLASS_ENTRY PCISubClass_0a
[];
53 PCI_CLASS_ENTRY PCISubClass_0b
[];
54 PCI_CLASS_ENTRY PCISubClass_0c
[];
55 PCI_CLASS_ENTRY PCISubClass_0d
[];
56 PCI_CLASS_ENTRY PCISubClass_0e
[];
57 PCI_CLASS_ENTRY PCISubClass_0f
[];
58 PCI_CLASS_ENTRY PCISubClass_10
[];
59 PCI_CLASS_ENTRY PCISubClass_11
[];
60 PCI_CLASS_ENTRY PCISubClass_12
[];
61 PCI_CLASS_ENTRY PCISubClass_13
[];
62 PCI_CLASS_ENTRY PCIPIFClass_0100
[];
63 PCI_CLASS_ENTRY PCIPIFClass_0101
[];
64 PCI_CLASS_ENTRY PCIPIFClass_0105
[];
65 PCI_CLASS_ENTRY PCIPIFClass_0106
[];
66 PCI_CLASS_ENTRY PCIPIFClass_0107
[];
67 PCI_CLASS_ENTRY PCIPIFClass_0108
[];
68 PCI_CLASS_ENTRY PCIPIFClass_0109
[];
69 PCI_CLASS_ENTRY PCIPIFClass_0300
[];
70 PCI_CLASS_ENTRY PCIPIFClass_0604
[];
71 PCI_CLASS_ENTRY PCIPIFClass_0609
[];
72 PCI_CLASS_ENTRY PCIPIFClass_060b
[];
73 PCI_CLASS_ENTRY PCIPIFClass_0700
[];
74 PCI_CLASS_ENTRY PCIPIFClass_0701
[];
75 PCI_CLASS_ENTRY PCIPIFClass_0703
[];
76 PCI_CLASS_ENTRY PCIPIFClass_0800
[];
77 PCI_CLASS_ENTRY PCIPIFClass_0801
[];
78 PCI_CLASS_ENTRY PCIPIFClass_0802
[];
79 PCI_CLASS_ENTRY PCIPIFClass_0803
[];
80 PCI_CLASS_ENTRY PCIPIFClass_0904
[];
81 PCI_CLASS_ENTRY PCIPIFClass_0c00
[];
82 PCI_CLASS_ENTRY PCIPIFClass_0c03
[];
83 PCI_CLASS_ENTRY PCIPIFClass_0c07
[];
84 PCI_CLASS_ENTRY PCIPIFClass_0d01
[];
85 PCI_CLASS_ENTRY PCIPIFClass_0e00
[];
88 // Base class strings entries
90 PCI_CLASS_ENTRY gClassStringList
[] = {
98 L
"Mass Storage Controller",
103 L
"Network Controller",
108 L
"Display Controller",
113 L
"Multimedia Device",
118 L
"Memory Controller",
128 L
"Simple Communications Controllers",
133 L
"Base System Peripherals",
153 L
"Serial Bus Controllers",
158 L
"Wireless Controllers",
163 L
"Intelligent IO Controllers",
168 L
"Satellite Communications Controllers",
173 L
"Encryption/Decryption Controllers",
178 L
"Data Acquisition & Signal Processing Controllers",
183 L
"Processing Accelerators",
188 L
"Non-Essential Instrumentation",
193 L
"Device does not fit in any defined classes",
199 /* null string ends the list */NULL
204 // Subclass strings entries
206 PCI_CLASS_ENTRY PCIBlankEntry
[] = {
215 /* null string ends the list */NULL
219 PCI_CLASS_ENTRY PCISubClass_00
[] = {
222 L
"All devices other than VGA",
227 L
"VGA-compatible devices",
233 /* null string ends the list */NULL
237 PCI_CLASS_ENTRY PCISubClass_01
[] = {
250 L
"Floppy disk controller",
265 L
"ATA controller with ADMA interface",
270 L
"Serial ATA controller",
275 L
"Serial Attached SCSI (SAS) controller ",
280 L
"Non-volatile memory subsystem",
285 L
"Universal Flash Storage (UFS) controller ",
290 L
"Other mass storage controller",
296 /* null string ends the list */NULL
300 PCI_CLASS_ENTRY PCISubClass_02
[] = {
303 L
"Ethernet controller",
308 L
"Token ring controller",
328 L
"WorldFip controller",
333 L
"PICMG 2.14 Multi Computing",
338 L
"InfiniBand controller",
343 L
"Other network controller",
349 /* null string ends the list */NULL
353 PCI_CLASS_ENTRY PCISubClass_03
[] = {
356 L
"VGA/8514 controller",
371 L
"Other display controller",
377 /* null string ends the list */PCIBlankEntry
381 PCI_CLASS_ENTRY PCISubClass_04
[] = {
394 L
"Computer Telephony device",
399 L
"Mixed mode device",
404 L
"Other multimedia device",
410 /* null string ends the list */NULL
414 PCI_CLASS_ENTRY PCISubClass_05
[] = {
417 L
"RAM memory controller",
422 L
"Flash memory controller",
427 L
"Other memory controller",
433 /* null string ends the list */NULL
437 PCI_CLASS_ENTRY PCISubClass_06
[] = {
455 L
"PCI/Micro Channel bridge",
465 L
"PCI/PCMCIA bridge",
485 L
"Semi-transparent PCI-to-PCI bridge",
490 L
"InfiniBand-to-PCI host bridge",
495 L
"Advanced Switching to PCI host bridge",
500 L
"Other bridge type",
506 /* null string ends the list */NULL
510 PCI_CLASS_ENTRY PCISubClass_07
[] = {
513 L
"Serial controller",
523 L
"Multiport serial controller",
533 L
"GPIB (IEEE 488.1/2) controller",
543 L
"Other communication device",
549 /* null string ends the list */NULL
553 PCI_CLASS_ENTRY PCISubClass_08
[] = {
576 L
"Generic PCI Hot-Plug controller",
581 L
"SD Host controller",
591 L
"Root Complex Event Collector",
596 L
"Other system peripheral",
602 /* null string ends the list */NULL
606 PCI_CLASS_ENTRY PCISubClass_09
[] = {
609 L
"Keyboard controller",
624 L
"Scanner controller",
629 L
"Gameport controller",
634 L
"Other input controller",
640 /* null string ends the list */NULL
644 PCI_CLASS_ENTRY PCISubClass_0a
[] = {
647 L
"Generic docking station",
652 L
"Other type of docking station",
658 /* null string ends the list */NULL
662 PCI_CLASS_ENTRY PCISubClass_0b
[] = {
706 /* null string ends the list */NULL
710 PCI_CLASS_ENTRY PCISubClass_0c
[] = {
738 L
"System Management Bus",
753 L
"SERCOS Interface Standard (IEC 61491)",
769 /* null string ends the list */NULL
773 PCI_CLASS_ENTRY PCISubClass_0d
[] = {
776 L
"iRDA compatible controller",
801 L
"Ethernet (802.11a - 5 GHz)",
806 L
"Ethernet (802.11b - 2.4 GHz)",
811 L
"Other type of wireless controller",
817 /* null string ends the list */NULL
821 PCI_CLASS_ENTRY PCISubClass_0e
[] = {
830 /* null string ends the list */NULL
834 PCI_CLASS_ENTRY PCISubClass_0f
[] = {
857 L
"Other satellite communication controller",
863 /* null string ends the list */NULL
867 PCI_CLASS_ENTRY PCISubClass_10
[] = {
870 L
"Network & computing Encrypt/Decrypt",
875 L
"Entertainment Encrypt/Decrypt",
880 L
"Other Encrypt/Decrypt",
886 /* null string ends the list */NULL
890 PCI_CLASS_ENTRY PCISubClass_11
[] = {
898 L
"Performance Counters",
903 L
"Communications synchronization plus time and frequency test/measurement ",
913 L
"Other DAQ & SP controllers",
919 /* null string ends the list */NULL
923 PCI_CLASS_ENTRY PCISubClass_12
[] = {
926 L
"Processing Accelerator",
932 /* null string ends the list */NULL
936 PCI_CLASS_ENTRY PCISubClass_13
[] = {
939 L
"Non-Essential Instrumentation Function",
945 /* null string ends the list */NULL
950 // Programming Interface entries
952 PCI_CLASS_ENTRY PCIPIFClass_0100
[] = {
960 L
"SCSI storage device SOP using PQI",
965 L
"SCSI controller SOP using PQI",
970 L
"SCSI storage device and controller SOP using PQI",
975 L
"SCSI storage device SOP using NVMe",
981 /* null string ends the list */NULL
985 PCI_CLASS_ENTRY PCIPIFClass_0101
[] = {
1013 L
"OM-primary, OM-secondary",
1018 L
"PI-primary, OM-secondary",
1023 L
"OM/PI-primary, OM-secondary",
1033 L
"OM-primary, PI-secondary",
1038 L
"PI-primary, PI-secondary",
1043 L
"OM/PI-primary, PI-secondary",
1053 L
"OM-primary, OM/PI-secondary",
1058 L
"PI-primary, OM/PI-secondary",
1063 L
"OM/PI-primary, OM/PI-secondary",
1073 L
"Master, OM-primary",
1078 L
"Master, PI-primary",
1083 L
"Master, OM/PI-primary",
1088 L
"Master, OM-secondary",
1093 L
"Master, OM-primary, OM-secondary",
1098 L
"Master, PI-primary, OM-secondary",
1103 L
"Master, OM/PI-primary, OM-secondary",
1108 L
"Master, OM-secondary",
1113 L
"Master, OM-primary, PI-secondary",
1118 L
"Master, PI-primary, PI-secondary",
1123 L
"Master, OM/PI-primary, PI-secondary",
1128 L
"Master, OM-secondary",
1133 L
"Master, OM-primary, OM/PI-secondary",
1138 L
"Master, PI-primary, OM/PI-secondary",
1143 L
"Master, OM/PI-primary, OM/PI-secondary",
1149 /* null string ends the list */NULL
1153 PCI_CLASS_ENTRY PCIPIFClass_0105
[] = {
1161 L
"Continuous operation",
1167 /* null string ends the list */NULL
1171 PCI_CLASS_ENTRY PCIPIFClass_0106
[] = {
1184 L
"Serial Storage Bus",
1190 /* null string ends the list */NULL
1194 PCI_CLASS_ENTRY PCIPIFClass_0107
[] = {
1208 /* null string ends the list */NULL
1212 PCI_CLASS_ENTRY PCIPIFClass_0108
[] = {
1231 /* null string ends the list */NULL
1235 PCI_CLASS_ENTRY PCIPIFClass_0109
[] = {
1249 /* null string ends the list */NULL
1253 PCI_CLASS_ENTRY PCIPIFClass_0300
[] = {
1267 /* null string ends the list */NULL
1271 PCI_CLASS_ENTRY PCIPIFClass_0604
[] = {
1279 L
"Subtractive decode",
1285 /* null string ends the list */NULL
1289 PCI_CLASS_ENTRY PCIPIFClass_0609
[] = {
1292 L
"Primary PCI bus side facing the system host processor",
1297 L
"Secondary PCI bus side facing the system host processor",
1303 /* null string ends the list */NULL
1307 PCI_CLASS_ENTRY PCIPIFClass_060b
[] = {
1315 L
"ASI-SIG Defined Portal",
1321 /* null string ends the list */NULL
1325 PCI_CLASS_ENTRY PCIPIFClass_0700
[] = {
1328 L
"Generic XT-compatible",
1333 L
"16450-compatible",
1338 L
"16550-compatible",
1343 L
"16650-compatible",
1348 L
"16750-compatible",
1353 L
"16850-compatible",
1358 L
"16950-compatible",
1364 /* null string ends the list */NULL
1368 PCI_CLASS_ENTRY PCIPIFClass_0701
[] = {
1381 L
"ECP 1.X-compliant",
1391 L
"IEEE 1284 target (not a controller)",
1397 /* null string ends the list */NULL
1401 PCI_CLASS_ENTRY PCIPIFClass_0703
[] = {
1409 L
"Hayes-compatible 16450",
1414 L
"Hayes-compatible 16550",
1419 L
"Hayes-compatible 16650",
1424 L
"Hayes-compatible 16750",
1430 /* null string ends the list */NULL
1434 PCI_CLASS_ENTRY PCIPIFClass_0800
[] = {
1457 L
"IO(x) APIC interrupt controller",
1463 /* null string ends the list */NULL
1467 PCI_CLASS_ENTRY PCIPIFClass_0801
[] = {
1486 /* null string ends the list */NULL
1490 PCI_CLASS_ENTRY PCIPIFClass_0802
[] = {
1509 /* null string ends the list */NULL
1513 PCI_CLASS_ENTRY PCIPIFClass_0803
[] = {
1532 /* null string ends the list */NULL
1536 PCI_CLASS_ENTRY PCIPIFClass_0904
[] = {
1550 /* null string ends the list */NULL
1554 PCI_CLASS_ENTRY PCIPIFClass_0c00
[] = {
1562 L
"Using 1394 OpenHCI spec",
1568 /* null string ends the list */NULL
1572 PCI_CLASS_ENTRY PCIPIFClass_0c03
[] = {
1595 L
"No specific programming interface",
1600 L
"(Not Host Controller)",
1606 /* null string ends the list */NULL
1610 PCI_CLASS_ENTRY PCIPIFClass_0c07
[] = {
1618 L
"Keyboard Controller Style",
1629 /* null string ends the list */NULL
1633 PCI_CLASS_ENTRY PCIPIFClass_0d01
[] = {
1636 L
"Consumer IR controller",
1641 L
"UWB Radio controller",
1647 /* null string ends the list */NULL
1651 PCI_CLASS_ENTRY PCIPIFClass_0e00
[] = {
1654 L
"Message FIFO at offset 40h",
1665 /* null string ends the list */NULL
1671 Generates printable Unicode strings that represent PCI device class,
1672 subclass and programmed I/F based on a value passed to the function.
1674 @param[in] ClassCode Value representing the PCI "Class Code" register read from a
1675 PCI device. The encodings are:
1676 bits 23:16 - Base Class Code
1677 bits 15:8 - Sub-Class Code
1678 bits 7:0 - Programming Interface
1679 @param[in, out] ClassStrings Pointer of PCI_CLASS_STRINGS structure, which contains
1680 printable class strings corresponding to ClassCode. The
1681 caller must not modify the strings that are pointed by
1682 the fields in ClassStrings.
1685 PciGetClassStrings (
1686 IN UINT32 ClassCode
,
1687 IN OUT PCI_CLASS_STRINGS
*ClassStrings
1692 PCI_CLASS_ENTRY
*CurrentClass
;
1695 // Assume no strings found
1697 ClassStrings
->BaseClass
= L
"UNDEFINED";
1698 ClassStrings
->SubClass
= L
"UNDEFINED";
1699 ClassStrings
->PIFClass
= L
"UNDEFINED";
1701 CurrentClass
= gClassStringList
;
1702 Code
= (UINT8
) (ClassCode
>> 16);
1706 // Go through all entries of the base class, until the entry with a matching
1707 // base class code is found. If reaches an entry with a null description
1708 // text, the last entry is met, which means no text for the base class was
1709 // found, so no more action is needed.
1711 while (Code
!= CurrentClass
[Index
].Code
) {
1712 if (NULL
== CurrentClass
[Index
].DescText
) {
1719 // A base class was found. Assign description, and check if this class has
1720 // sub-class defined. If sub-class defined, no more action is needed,
1721 // otherwise, continue to find description for the sub-class code.
1723 ClassStrings
->BaseClass
= CurrentClass
[Index
].DescText
;
1724 if (NULL
== CurrentClass
[Index
].LowerLevelClass
) {
1728 // find Subclass entry
1730 CurrentClass
= CurrentClass
[Index
].LowerLevelClass
;
1731 Code
= (UINT8
) (ClassCode
>> 8);
1735 // Go through all entries of the sub-class, until the entry with a matching
1736 // sub-class code is found. If reaches an entry with a null description
1737 // text, the last entry is met, which means no text for the sub-class was
1738 // found, so no more action is needed.
1740 while (Code
!= CurrentClass
[Index
].Code
) {
1741 if (NULL
== CurrentClass
[Index
].DescText
) {
1748 // A class was found for the sub-class code. Assign description, and check if
1749 // this sub-class has programming interface defined. If no, no more action is
1750 // needed, otherwise, continue to find description for the programming
1753 ClassStrings
->SubClass
= CurrentClass
[Index
].DescText
;
1754 if (NULL
== CurrentClass
[Index
].LowerLevelClass
) {
1758 // Find programming interface entry
1760 CurrentClass
= CurrentClass
[Index
].LowerLevelClass
;
1761 Code
= (UINT8
) ClassCode
;
1765 // Go through all entries of the I/F entries, until the entry with a
1766 // matching I/F code is found. If reaches an entry with a null description
1767 // text, the last entry is met, which means no text was found, so no more
1768 // action is needed.
1770 while (Code
!= CurrentClass
[Index
].Code
) {
1771 if (NULL
== CurrentClass
[Index
].DescText
) {
1778 // A class was found for the I/F code. Assign description, done!
1780 ClassStrings
->PIFClass
= CurrentClass
[Index
].DescText
;
1785 Print strings that represent PCI device class, subclass and programmed I/F.
1787 @param[in] ClassCodePtr Points to the memory which stores register Class Code in PCI
1788 configuration space.
1789 @param[in] IncludePIF If the printed string should include the programming I/F part
1793 IN UINT8
*ClassCodePtr
,
1794 IN BOOLEAN IncludePIF
1798 PCI_CLASS_STRINGS ClassStrings
;
1801 ClassCode
|= (UINT32
)ClassCodePtr
[0];
1802 ClassCode
|= (UINT32
)(ClassCodePtr
[1] << 8);
1803 ClassCode
|= (UINT32
)(ClassCodePtr
[2] << 16);
1806 // Get name from class code
1808 PciGetClassStrings (ClassCode
, &ClassStrings
);
1812 // Print base class, sub class, and programming inferface name
1814 ShellPrintEx (-1, -1, L
"%s - %s - %s",
1815 ClassStrings
.BaseClass
,
1816 ClassStrings
.SubClass
,
1817 ClassStrings
.PIFClass
1822 // Only print base class and sub class name
1824 ShellPrintEx (-1, -1, L
"%s - %s",
1825 ClassStrings
.BaseClass
,
1826 ClassStrings
.SubClass
1832 This function finds out the protocol which is in charge of the given
1833 segment, and its bus range covers the current bus number. It lookes
1834 each instances of RootBridgeIoProtocol handle, until the one meets the
1837 @param[in] HandleBuf Buffer which holds all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.
1838 @param[in] HandleCount Count of all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.
1839 @param[in] Segment Segment number of device we are dealing with.
1840 @param[in] Bus Bus number of device we are dealing with.
1841 @param[out] IoDev Handle used to access configuration space of PCI device.
1843 @retval EFI_SUCCESS The command completed successfully.
1844 @retval EFI_INVALID_PARAMETER Invalid parameter.
1848 PciFindProtocolInterface (
1849 IN EFI_HANDLE
*HandleBuf
,
1850 IN UINTN HandleCount
,
1853 OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
**IoDev
1857 This function gets the protocol interface from the given handle, and
1858 obtains its address space descriptors.
1860 @param[in] Handle The PCI_ROOT_BRIDIGE_IO_PROTOCOL handle.
1861 @param[out] IoDev Handle used to access configuration space of PCI device.
1862 @param[out] Descriptors Points to the address space descriptors.
1864 @retval EFI_SUCCESS The command completed successfully
1867 PciGetProtocolAndResource (
1868 IN EFI_HANDLE Handle
,
1869 OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
**IoDev
,
1870 OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
**Descriptors
1874 This function get the next bus range of given address space descriptors.
1875 It also moves the pointer backward a node, to get prepared to be called
1878 @param[in, out] Descriptors Points to current position of a serial of address space
1880 @param[out] MinBus The lower range of bus number.
1881 @param[out] MaxBus The upper range of bus number.
1882 @param[out] IsEnd Meet end of the serial of descriptors.
1884 @retval EFI_SUCCESS The command completed successfully.
1887 PciGetNextBusRange (
1888 IN OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
**Descriptors
,
1895 Explain the data in PCI configuration space. The part which is common for
1896 PCI device and bridge is interpreted in this function. It calls other
1897 functions to interpret data unique for device or bridge.
1899 @param[in] ConfigSpace Data in PCI configuration space.
1900 @param[in] Address Address used to access configuration space of this PCI device.
1901 @param[in] IoDev Handle used to access configuration space of PCI device.
1905 IN PCI_CONFIG_SPACE
*ConfigSpace
,
1907 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
1911 Explain the device specific part of data in PCI configuration space.
1913 @param[in] Device Data in PCI configuration space.
1914 @param[in] Address Address used to access configuration space of this PCI device.
1915 @param[in] IoDev Handle used to access configuration space of PCI device.
1917 @retval EFI_SUCCESS The command completed successfully.
1920 PciExplainDeviceData (
1921 IN PCI_DEVICE_HEADER_TYPE_REGION
*Device
,
1923 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
1927 Explain the bridge specific part of data in PCI configuration space.
1929 @param[in] Bridge Bridge specific data region in PCI configuration space.
1930 @param[in] Address Address used to access configuration space of this PCI device.
1931 @param[in] IoDev Handle used to access configuration space of PCI device.
1933 @retval EFI_SUCCESS The command completed successfully.
1936 PciExplainBridgeData (
1937 IN PCI_BRIDGE_CONTROL_REGISTER
*Bridge
,
1939 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
1943 Explain the Base Address Register(Bar) in PCI configuration space.
1945 @param[in] Bar Points to the Base Address Register intended to interpret.
1946 @param[in] Command Points to the register Command.
1947 @param[in] Address Address used to access configuration space of this PCI device.
1948 @param[in] IoDev Handle used to access configuration space of PCI device.
1949 @param[in, out] Index The Index.
1951 @retval EFI_SUCCESS The command completed successfully.
1958 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
,
1963 Explain the cardbus specific part of data in PCI configuration space.
1965 @param[in] CardBus CardBus specific region of PCI configuration space.
1966 @param[in] Address Address used to access configuration space of this PCI device.
1967 @param[in] IoDev Handle used to access configuration space of PCI device.
1969 @retval EFI_SUCCESS The command completed successfully.
1972 PciExplainCardBusData (
1973 IN PCI_CARDBUS_CONTROL_REGISTER
*CardBus
,
1975 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
1979 Explain each meaningful bit of register Status. The definition of Status is
1980 slightly different depending on the PCI header type.
1982 @param[in] Status Points to the content of register Status.
1983 @param[in] MainStatus Indicates if this register is main status(not secondary
1985 @param[in] HeaderType Header type of this PCI device.
1987 @retval EFI_SUCCESS The command completed successfully.
1992 IN BOOLEAN MainStatus
,
1993 IN PCI_HEADER_TYPE HeaderType
1997 Explain each meaningful bit of register Command.
1999 @param[in] Command Points to the content of register Command.
2001 @retval EFI_SUCCESS The command completed successfully.
2009 Explain each meaningful bit of register Bridge Control.
2011 @param[in] BridgeControl Points to the content of register Bridge Control.
2012 @param[in] HeaderType The headertype.
2014 @retval EFI_SUCCESS The command completed successfully.
2017 PciExplainBridgeControl (
2018 IN UINT16
*BridgeControl
,
2019 IN PCI_HEADER_TYPE HeaderType
2023 Locate capability register block per capability ID.
2025 @param[in] ConfigSpace Data in PCI configuration space.
2026 @param[in] CapabilityId The capability ID.
2028 @return The offset of the register block per capability ID.
2031 LocatePciCapability (
2032 IN PCI_CONFIG_SPACE
*ConfigSpace
,
2033 IN UINT8 CapabilityId
2037 Display Pcie device structure.
2039 @param[in] PciExpressCap PCI Express capability buffer.
2040 @param[in] ExtendedConfigSpace PCI Express extended configuration space.
2041 @param[in] ExtendedConfigSize PCI Express extended configuration size.
2042 @param[in] ExtendedCapability PCI Express extended capability ID to explain.
2045 PciExplainPciExpress (
2046 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
,
2047 IN UINT8
*ExtendedConfigSpace
,
2048 IN UINTN ExtendedConfigSize
,
2049 IN CONST UINT16 ExtendedCapability
2053 Print out information of the capability information.
2055 @param[in] PciExpressCap The pointer to the structure about the device.
2057 @retval EFI_SUCCESS The operation was successful.
2061 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
2065 Print out information of the device capability information.
2067 @param[in] PciExpressCap The pointer to the structure about the device.
2069 @retval EFI_SUCCESS The operation was successful.
2072 ExplainPcieDeviceCap (
2073 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
2077 Print out information of the device control information.
2079 @param[in] PciExpressCap The pointer to the structure about the device.
2081 @retval EFI_SUCCESS The operation was successful.
2084 ExplainPcieDeviceControl (
2085 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
2089 Print out information of the device status information.
2091 @param[in] PciExpressCap The pointer to the structure about the device.
2093 @retval EFI_SUCCESS The operation was successful.
2096 ExplainPcieDeviceStatus (
2097 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
2101 Print out information of the device link information.
2103 @param[in] PciExpressCap The pointer to the structure about the device.
2105 @retval EFI_SUCCESS The operation was successful.
2108 ExplainPcieLinkCap (
2109 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
2113 Print out information of the device link control information.
2115 @param[in] PciExpressCap The pointer to the structure about the device.
2117 @retval EFI_SUCCESS The operation was successful.
2120 ExplainPcieLinkControl (
2121 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
2125 Print out information of the device link status information.
2127 @param[in] PciExpressCap The pointer to the structure about the device.
2129 @retval EFI_SUCCESS The operation was successful.
2132 ExplainPcieLinkStatus (
2133 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
2137 Print out information of the device slot information.
2139 @param[in] PciExpressCap The pointer to the structure about the device.
2141 @retval EFI_SUCCESS The operation was successful.
2144 ExplainPcieSlotCap (
2145 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
2149 Print out information of the device slot control information.
2151 @param[in] PciExpressCap The pointer to the structure about the device.
2153 @retval EFI_SUCCESS The operation was successful.
2156 ExplainPcieSlotControl (
2157 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
2161 Print out information of the device slot status information.
2163 @param[in] PciExpressCap The pointer to the structure about the device.
2165 @retval EFI_SUCCESS The operation was successful.
2168 ExplainPcieSlotStatus (
2169 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
2173 Print out information of the device root information.
2175 @param[in] PciExpressCap The pointer to the structure about the device.
2177 @retval EFI_SUCCESS The operation was successful.
2180 ExplainPcieRootControl (
2181 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
2185 Print out information of the device root capability information.
2187 @param[in] PciExpressCap The pointer to the structure about the device.
2189 @retval EFI_SUCCESS The operation was successful.
2192 ExplainPcieRootCap (
2193 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
2197 Print out information of the device root status information.
2199 @param[in] PciExpressCap The pointer to the structure about the device.
2201 @retval EFI_SUCCESS The operation was successful.
2204 ExplainPcieRootStatus (
2205 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
2208 typedef EFI_STATUS (*PCIE_EXPLAIN_FUNCTION
) (IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
);
2214 } PCIE_CAPREG_FIELD_WIDTH
;
2217 PcieExplainTypeCommon
,
2218 PcieExplainTypeDevice
,
2219 PcieExplainTypeLink
,
2220 PcieExplainTypeSlot
,
2221 PcieExplainTypeRoot
,
2223 } PCIE_EXPLAIN_TYPE
;
2229 PCIE_CAPREG_FIELD_WIDTH Width
;
2230 PCIE_EXPLAIN_FUNCTION Func
;
2231 PCIE_EXPLAIN_TYPE Type
;
2232 } PCIE_EXPLAIN_STRUCT
;
2234 PCIE_EXPLAIN_STRUCT PcieExplainList
[] = {
2236 STRING_TOKEN (STR_PCIEX_CAPABILITY_CAPID
),
2240 PcieExplainTypeCommon
2243 STRING_TOKEN (STR_PCIEX_NEXTCAP_PTR
),
2247 PcieExplainTypeCommon
2250 STRING_TOKEN (STR_PCIEX_CAP_REGISTER
),
2254 PcieExplainTypeCommon
2257 STRING_TOKEN (STR_PCIEX_DEVICE_CAP
),
2260 ExplainPcieDeviceCap
,
2261 PcieExplainTypeDevice
2264 STRING_TOKEN (STR_PCIEX_DEVICE_CONTROL
),
2267 ExplainPcieDeviceControl
,
2268 PcieExplainTypeDevice
2271 STRING_TOKEN (STR_PCIEX_DEVICE_STATUS
),
2274 ExplainPcieDeviceStatus
,
2275 PcieExplainTypeDevice
2278 STRING_TOKEN (STR_PCIEX_LINK_CAPABILITIES
),
2285 STRING_TOKEN (STR_PCIEX_LINK_CONTROL
),
2288 ExplainPcieLinkControl
,
2292 STRING_TOKEN (STR_PCIEX_LINK_STATUS
),
2295 ExplainPcieLinkStatus
,
2299 STRING_TOKEN (STR_PCIEX_SLOT_CAPABILITIES
),
2306 STRING_TOKEN (STR_PCIEX_SLOT_CONTROL
),
2309 ExplainPcieSlotControl
,
2313 STRING_TOKEN (STR_PCIEX_SLOT_STATUS
),
2316 ExplainPcieSlotStatus
,
2320 STRING_TOKEN (STR_PCIEX_ROOT_CONTROL
),
2323 ExplainPcieRootControl
,
2327 STRING_TOKEN (STR_PCIEX_RSVDP
),
2334 STRING_TOKEN (STR_PCIEX_ROOT_STATUS
),
2337 ExplainPcieRootStatus
,
2343 (PCIE_CAPREG_FIELD_WIDTH
)0,
2352 PCI_CONFIG_SPACE
*mConfigSpace
= NULL
;
2353 STATIC CONST SHELL_PARAM_ITEM ParamList
[] = {
2356 {L
"-ec", TypeValue
},
2360 CHAR16
*DevicePortTypeTable
[] = {
2361 L
"PCI Express Endpoint",
2362 L
"Legacy PCI Express Endpoint",
2365 L
"Root Port of PCI Express Root Complex",
2366 L
"Upstream Port of PCI Express Switch",
2367 L
"Downstream Port of PCI Express Switch",
2368 L
"PCI Express to PCI/PCI-X Bridge",
2369 L
"PCI/PCI-X to PCI Express Bridge",
2370 L
"Root Complex Integrated Endpoint",
2371 L
"Root Complex Event Collector"
2374 CHAR16
*L0sLatencyStrTable
[] = {
2376 L
"64ns to less than 128ns",
2377 L
"128ns to less than 256ns",
2378 L
"256ns to less than 512ns",
2379 L
"512ns to less than 1us",
2380 L
"1us to less than 2us",
2385 CHAR16
*L1LatencyStrTable
[] = {
2387 L
"1us to less than 2us",
2388 L
"2us to less than 4us",
2389 L
"4us to less than 8us",
2390 L
"8us to less than 16us",
2391 L
"16us to less than 32us",
2396 CHAR16
*ASPMCtrlStrTable
[] = {
2398 L
"L0s Entry Enabled",
2399 L
"L1 Entry Enabled",
2400 L
"L0s and L1 Entry Enabled"
2403 CHAR16
*SlotPwrLmtScaleTable
[] = {
2410 CHAR16
*IndicatorTable
[] = {
2419 Function for 'pci' command.
2421 @param[in] ImageHandle Handle to the Image (NULL if Internal).
2422 @param[in] SystemTable Pointer to the System Table (NULL if Internal).
2426 ShellCommandRunPci (
2427 IN EFI_HANDLE ImageHandle
,
2428 IN EFI_SYSTEM_TABLE
*SystemTable
2436 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
;
2438 PCI_DEVICE_INDEPENDENT_REGION PciHeader
;
2439 PCI_CONFIG_SPACE ConfigSpace
;
2443 BOOLEAN ExplainData
;
2447 UINTN HandleBufSize
;
2448 EFI_HANDLE
*HandleBuf
;
2450 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
*Descriptors
;
2454 LIST_ENTRY
*Package
;
2455 CHAR16
*ProblemParam
;
2456 SHELL_STATUS ShellStatus
;
2459 UINT16 ExtendedCapability
;
2460 UINT8 PcieCapabilityPtr
;
2461 UINT8
*ExtendedConfigSpace
;
2462 UINTN ExtendedConfigSize
;
2464 ShellStatus
= SHELL_SUCCESS
;
2465 Status
= EFI_SUCCESS
;
2472 // initialize the shell lib (we must be in non-auto-init...)
2474 Status
= ShellInitialize();
2475 ASSERT_EFI_ERROR(Status
);
2477 Status
= CommandInit();
2478 ASSERT_EFI_ERROR(Status
);
2481 // parse the command line
2483 Status
= ShellCommandLineParse (ParamList
, &Package
, &ProblemParam
, TRUE
);
2484 if (EFI_ERROR(Status
)) {
2485 if (Status
== EFI_VOLUME_CORRUPTED
&& ProblemParam
!= NULL
) {
2486 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_GEN_PROBLEM
), gShellDebug1HiiHandle
, L
"pci", ProblemParam
);
2487 FreePool(ProblemParam
);
2488 ShellStatus
= SHELL_INVALID_PARAMETER
;
2494 if (ShellCommandLineGetCount(Package
) == 2) {
2495 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_GEN_TOO_FEW
), gShellDebug1HiiHandle
, L
"pci");
2496 ShellStatus
= SHELL_INVALID_PARAMETER
;
2500 if (ShellCommandLineGetCount(Package
) > 4) {
2501 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_GEN_TOO_MANY
), gShellDebug1HiiHandle
, L
"pci");
2502 ShellStatus
= SHELL_INVALID_PARAMETER
;
2505 if (ShellCommandLineGetFlag(Package
, L
"-ec") && ShellCommandLineGetValue(Package
, L
"-ec") == NULL
) {
2506 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_GEN_NO_VALUE
), gShellDebug1HiiHandle
, L
"pci", L
"-ec");
2507 ShellStatus
= SHELL_INVALID_PARAMETER
;
2510 if (ShellCommandLineGetFlag(Package
, L
"-s") && ShellCommandLineGetValue(Package
, L
"-s") == NULL
) {
2511 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_GEN_NO_VALUE
), gShellDebug1HiiHandle
, L
"pci", L
"-s");
2512 ShellStatus
= SHELL_INVALID_PARAMETER
;
2516 // Get all instances of PciRootBridgeIo. Allocate space for 1 EFI_HANDLE and
2517 // call LibLocateHandle(), if EFI_BUFFER_TOO_SMALL is returned, allocate enough
2518 // space for handles and call it again.
2520 HandleBufSize
= sizeof (EFI_HANDLE
);
2521 HandleBuf
= (EFI_HANDLE
*) AllocateZeroPool (HandleBufSize
);
2522 if (HandleBuf
== NULL
) {
2523 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_GEN_OUT_MEM
), gShellDebug1HiiHandle
, L
"pci");
2524 ShellStatus
= SHELL_OUT_OF_RESOURCES
;
2528 Status
= gBS
->LocateHandle (
2530 &gEfiPciRootBridgeIoProtocolGuid
,
2536 if (Status
== EFI_BUFFER_TOO_SMALL
) {
2537 HandleBuf
= ReallocatePool (sizeof (EFI_HANDLE
), HandleBufSize
, HandleBuf
);
2538 if (HandleBuf
== NULL
) {
2539 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_GEN_OUT_MEM
), gShellDebug1HiiHandle
, L
"pci");
2540 ShellStatus
= SHELL_OUT_OF_RESOURCES
;
2544 Status
= gBS
->LocateHandle (
2546 &gEfiPciRootBridgeIoProtocolGuid
,
2553 if (EFI_ERROR (Status
)) {
2554 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_GEN_PCIRBIO_NF
), gShellDebug1HiiHandle
, L
"pci");
2555 ShellStatus
= SHELL_NOT_FOUND
;
2559 HandleCount
= HandleBufSize
/ sizeof (EFI_HANDLE
);
2561 // Argument Count == 1(no other argument): enumerate all pci functions
2563 if (ShellCommandLineGetCount(Package
) == 1) {
2564 gST
->ConOut
->QueryMode (
2566 gST
->ConOut
->Mode
->Mode
,
2573 if ((ScreenSize
& 1) == 1) {
2580 // For each handle, which decides a segment and a bus number range,
2581 // enumerate all devices on it.
2583 for (Index
= 0; Index
< HandleCount
; Index
++) {
2584 Status
= PciGetProtocolAndResource (
2589 if (EFI_ERROR (Status
)) {
2590 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_PCI_HANDLE_CFG_ERR
), gShellDebug1HiiHandle
, L
"pci");
2591 ShellStatus
= SHELL_NOT_FOUND
;
2595 // No document say it's impossible for a RootBridgeIo protocol handle
2596 // to have more than one address space descriptors, so find out every
2597 // bus range and for each of them do device enumeration.
2600 Status
= PciGetNextBusRange (&Descriptors
, &MinBus
, &MaxBus
, &IsEnd
);
2602 if (EFI_ERROR (Status
)) {
2603 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_PCI_BUS_RANGE_ERR
), gShellDebug1HiiHandle
, L
"pci");
2604 ShellStatus
= SHELL_NOT_FOUND
;
2612 for (Bus
= MinBus
; Bus
<= MaxBus
; Bus
++) {
2614 // For each devices, enumerate all functions it contains
2616 for (Device
= 0; Device
<= PCI_MAX_DEVICE
; Device
++) {
2618 // For each function, read its configuration space and print summary
2620 for (Func
= 0; Func
<= PCI_MAX_FUNC
; Func
++) {
2621 if (ShellGetExecutionBreakFlag ()) {
2622 ShellStatus
= SHELL_ABORTED
;
2625 Address
= EFI_PCI_ADDRESS (Bus
, Device
, Func
, 0);
2635 // If VendorId = 0xffff, there does not exist a device at this
2636 // location. For each device, if there is any function on it,
2637 // there must be 1 function at Function 0. So if Func = 0, there
2638 // will be no more functions in the same device, so we can break
2639 // loop to deal with the next device.
2641 if (PciHeader
.VendorId
== 0xffff && Func
== 0) {
2645 if (PciHeader
.VendorId
!= 0xffff) {
2648 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_PCI_TITLE
), gShellDebug1HiiHandle
);
2656 sizeof (PciHeader
) / sizeof (UINT32
),
2661 -1, -1, NULL
, STRING_TOKEN (STR_PCI_LINE_P1
), gShellDebug1HiiHandle
,
2662 IoDev
->SegmentNumber
,
2668 PciPrintClassCode (PciHeader
.ClassCode
, FALSE
);
2670 -1, -1, NULL
, STRING_TOKEN (STR_PCI_LINE_P2
), gShellDebug1HiiHandle
,
2673 PciHeader
.ClassCode
[0]
2677 if (ScreenCount
>= ScreenSize
&& ScreenSize
!= 0) {
2679 // If ScreenSize == 0 we have the console redirected so don't
2685 // If this is not a multi-function device, we can leave the loop
2686 // to deal with the next device.
2688 if (Func
== 0 && ((PciHeader
.HeaderType
& HEADER_TYPE_MULTI_FUNCTION
) == 0x00)) {
2696 // If Descriptor is NULL, Configuration() returns EFI_UNSUPPRORED,
2697 // we assume the bus range is 0~PCI_MAX_BUS. After enumerated all
2698 // devices on all bus, we can leave loop.
2700 if (Descriptors
== NULL
) {
2706 Status
= EFI_SUCCESS
;
2710 ExplainData
= FALSE
;
2715 ExtendedCapability
= 0xFFFF;
2716 if (ShellCommandLineGetFlag(Package
, L
"-i")) {
2720 Temp
= ShellCommandLineGetValue(Package
, L
"-s");
2723 // Input converted to hexadecimal number.
2725 if (!EFI_ERROR (ShellConvertStringToUint64 (Temp
, &RetVal
, TRUE
, TRUE
))) {
2726 Segment
= (UINT16
) RetVal
;
2728 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_GEN_PARAM_INV_HEX
), gShellDebug1HiiHandle
, L
"pci", Temp
);
2729 ShellStatus
= SHELL_INVALID_PARAMETER
;
2735 // The first Argument(except "-i") is assumed to be Bus number, second
2736 // to be Device number, and third to be Func number.
2738 Temp
= ShellCommandLineGetRawValue(Package
, 1);
2741 // Input converted to hexadecimal number.
2743 if (!EFI_ERROR (ShellConvertStringToUint64 (Temp
, &RetVal
, TRUE
, TRUE
))) {
2744 Bus
= (UINT16
) RetVal
;
2746 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_GEN_PARAM_INV_HEX
), gShellDebug1HiiHandle
, L
"pci", Temp
);
2747 ShellStatus
= SHELL_INVALID_PARAMETER
;
2751 if (Bus
> PCI_MAX_BUS
) {
2752 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_GEN_PARAM_INV
), gShellDebug1HiiHandle
, L
"pci", Temp
);
2753 ShellStatus
= SHELL_INVALID_PARAMETER
;
2757 Temp
= ShellCommandLineGetRawValue(Package
, 2);
2760 // Input converted to hexadecimal number.
2762 if (!EFI_ERROR (ShellConvertStringToUint64 (Temp
, &RetVal
, TRUE
, TRUE
))) {
2763 Device
= (UINT16
) RetVal
;
2765 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_GEN_PARAM_INV_HEX
), gShellDebug1HiiHandle
, L
"pci", Temp
);
2766 ShellStatus
= SHELL_INVALID_PARAMETER
;
2770 if (Device
> PCI_MAX_DEVICE
){
2771 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_GEN_PARAM_INV
), gShellDebug1HiiHandle
, L
"pci", Temp
);
2772 ShellStatus
= SHELL_INVALID_PARAMETER
;
2777 Temp
= ShellCommandLineGetRawValue(Package
, 3);
2780 // Input converted to hexadecimal number.
2782 if (!EFI_ERROR (ShellConvertStringToUint64 (Temp
, &RetVal
, TRUE
, TRUE
))) {
2783 Func
= (UINT16
) RetVal
;
2785 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_GEN_PARAM_INV_HEX
), gShellDebug1HiiHandle
, L
"pci", Temp
);
2786 ShellStatus
= SHELL_INVALID_PARAMETER
;
2790 if (Func
> PCI_MAX_FUNC
){
2791 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_GEN_PARAM_INV
), gShellDebug1HiiHandle
, L
"pci", Temp
);
2792 ShellStatus
= SHELL_INVALID_PARAMETER
;
2797 Temp
= ShellCommandLineGetValue (Package
, L
"-ec");
2800 // Input converted to hexadecimal number.
2802 if (!EFI_ERROR (ShellConvertStringToUint64 (Temp
, &RetVal
, TRUE
, TRUE
))) {
2803 ExtendedCapability
= (UINT16
) RetVal
;
2805 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_GEN_PARAM_INV_HEX
), gShellDebug1HiiHandle
, L
"pci", Temp
);
2806 ShellStatus
= SHELL_INVALID_PARAMETER
;
2812 // Find the protocol interface who's in charge of current segment, and its
2813 // bus range covers the current bus
2815 Status
= PciFindProtocolInterface (
2823 if (EFI_ERROR (Status
)) {
2825 -1, -1, NULL
, STRING_TOKEN (STR_PCI_NO_FIND
), gShellDebug1HiiHandle
, L
"pci",
2829 ShellStatus
= SHELL_NOT_FOUND
;
2833 Address
= EFI_PCI_ADDRESS (Bus
, Device
, Func
, 0);
2834 Status
= IoDev
->Pci
.Read (
2838 sizeof (ConfigSpace
),
2842 if (EFI_ERROR (Status
)) {
2843 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_PCI_NO_CFG
), gShellDebug1HiiHandle
, L
"pci");
2844 ShellStatus
= SHELL_ACCESS_DENIED
;
2848 mConfigSpace
= &ConfigSpace
;
2853 STRING_TOKEN (STR_PCI_INFO
),
2854 gShellDebug1HiiHandle
,
2866 // Dump standard header of configuration space
2868 SizeOfHeader
= sizeof (ConfigSpace
.Common
) + sizeof (ConfigSpace
.NonCommon
);
2870 DumpHex (2, 0, SizeOfHeader
, &ConfigSpace
);
2871 ShellPrintEx(-1,-1, L
"\r\n");
2874 // Dump device dependent Part of configuration space
2879 sizeof (ConfigSpace
) - SizeOfHeader
,
2883 ExtendedConfigSpace
= NULL
;
2884 ExtendedConfigSize
= 0;
2885 PcieCapabilityPtr
= LocatePciCapability (&ConfigSpace
, EFI_PCI_CAPABILITY_ID_PCIEXP
);
2886 if (PcieCapabilityPtr
!= 0) {
2887 ExtendedConfigSize
= 0x1000 - EFI_PCIE_CAPABILITY_BASE_OFFSET
;
2888 ExtendedConfigSpace
= AllocatePool (ExtendedConfigSize
);
2889 if (ExtendedConfigSpace
!= NULL
) {
2890 Status
= IoDev
->Pci
.Read (
2893 EFI_PCI_ADDRESS (Bus
, Device
, Func
, EFI_PCIE_CAPABILITY_BASE_OFFSET
),
2894 ExtendedConfigSize
/ sizeof (UINT32
),
2897 if (EFI_ERROR (Status
)) {
2898 SHELL_FREE_NON_NULL (ExtendedConfigSpace
);
2903 if ((ExtendedConfigSpace
!= NULL
) && !ShellGetExecutionBreakFlag ()) {
2905 // Print the PciEx extend space in raw bytes ( 0xFF-0xFFF)
2907 ShellPrintEx (-1, -1, L
"\r\n%HStart dumping PCIex extended configuration space (0x100 - 0xFFF).%N\r\n\r\n");
2911 EFI_PCIE_CAPABILITY_BASE_OFFSET
,
2918 // If "-i" appears in command line, interpret data in configuration space
2921 PciExplainPci (&ConfigSpace
, Address
, IoDev
);
2922 if ((ExtendedConfigSpace
!= NULL
) && !ShellGetExecutionBreakFlag ()) {
2923 PciExplainPciExpress (
2924 (PCI_CAPABILITY_PCIEXP
*) ((UINT8
*) &ConfigSpace
+ PcieCapabilityPtr
),
2925 ExtendedConfigSpace
,
2933 if (HandleBuf
!= NULL
) {
2934 FreePool (HandleBuf
);
2936 if (Package
!= NULL
) {
2937 ShellCommandLineFreeVarList (Package
);
2939 mConfigSpace
= NULL
;
2944 This function finds out the protocol which is in charge of the given
2945 segment, and its bus range covers the current bus number. It lookes
2946 each instances of RootBridgeIoProtocol handle, until the one meets the
2949 @param[in] HandleBuf Buffer which holds all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.
2950 @param[in] HandleCount Count of all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.
2951 @param[in] Segment Segment number of device we are dealing with.
2952 @param[in] Bus Bus number of device we are dealing with.
2953 @param[out] IoDev Handle used to access configuration space of PCI device.
2955 @retval EFI_SUCCESS The command completed successfully.
2956 @retval EFI_INVALID_PARAMETER Invalid parameter.
2960 PciFindProtocolInterface (
2961 IN EFI_HANDLE
*HandleBuf
,
2962 IN UINTN HandleCount
,
2965 OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
**IoDev
2970 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
*Descriptors
;
2976 // Go through all handles, until the one meets the criteria is found
2978 for (Index
= 0; Index
< HandleCount
; Index
++) {
2979 Status
= PciGetProtocolAndResource (HandleBuf
[Index
], IoDev
, &Descriptors
);
2980 if (EFI_ERROR (Status
)) {
2984 // When Descriptors == NULL, the Configuration() is not implemented,
2985 // so we only check the Segment number
2987 if (Descriptors
== NULL
&& Segment
== (*IoDev
)->SegmentNumber
) {
2991 if ((*IoDev
)->SegmentNumber
!= Segment
) {
2996 Status
= PciGetNextBusRange (&Descriptors
, &MinBus
, &MaxBus
, &IsEnd
);
2997 if (EFI_ERROR (Status
)) {
3005 if (MinBus
<= Bus
&& MaxBus
>= Bus
) {
3011 return EFI_NOT_FOUND
;
3015 This function gets the protocol interface from the given handle, and
3016 obtains its address space descriptors.
3018 @param[in] Handle The PCI_ROOT_BRIDIGE_IO_PROTOCOL handle.
3019 @param[out] IoDev Handle used to access configuration space of PCI device.
3020 @param[out] Descriptors Points to the address space descriptors.
3022 @retval EFI_SUCCESS The command completed successfully
3025 PciGetProtocolAndResource (
3026 IN EFI_HANDLE Handle
,
3027 OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
**IoDev
,
3028 OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
**Descriptors
3034 // Get inferface from protocol
3036 Status
= gBS
->HandleProtocol (
3038 &gEfiPciRootBridgeIoProtocolGuid
,
3042 if (EFI_ERROR (Status
)) {
3046 // Call Configuration() to get address space descriptors
3048 Status
= (*IoDev
)->Configuration (*IoDev
, (VOID
**)Descriptors
);
3049 if (Status
== EFI_UNSUPPORTED
) {
3050 *Descriptors
= NULL
;
3059 This function get the next bus range of given address space descriptors.
3060 It also moves the pointer backward a node, to get prepared to be called
3063 @param[in, out] Descriptors Points to current position of a serial of address space
3065 @param[out] MinBus The lower range of bus number.
3066 @param[out] MaxBus The upper range of bus number.
3067 @param[out] IsEnd Meet end of the serial of descriptors.
3069 @retval EFI_SUCCESS The command completed successfully.
3072 PciGetNextBusRange (
3073 IN OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
**Descriptors
,
3082 // When *Descriptors is NULL, Configuration() is not implemented, so assume
3083 // range is 0~PCI_MAX_BUS
3085 if ((*Descriptors
) == NULL
) {
3087 *MaxBus
= PCI_MAX_BUS
;
3091 // *Descriptors points to one or more address space descriptors, which
3092 // ends with a end tagged descriptor. Examine each of the descriptors,
3093 // if a bus typed one is found and its bus range covers bus, this handle
3094 // is the handle we are looking for.
3097 while ((*Descriptors
)->Desc
!= ACPI_END_TAG_DESCRIPTOR
) {
3098 if ((*Descriptors
)->ResType
== ACPI_ADDRESS_SPACE_TYPE_BUS
) {
3099 *MinBus
= (UINT16
) (*Descriptors
)->AddrRangeMin
;
3100 *MaxBus
= (UINT16
) (*Descriptors
)->AddrRangeMax
;
3102 return (EFI_SUCCESS
);
3108 if ((*Descriptors
)->Desc
== ACPI_END_TAG_DESCRIPTOR
) {
3116 Explain the data in PCI configuration space. The part which is common for
3117 PCI device and bridge is interpreted in this function. It calls other
3118 functions to interpret data unique for device or bridge.
3120 @param[in] ConfigSpace Data in PCI configuration space.
3121 @param[in] Address Address used to access configuration space of this PCI device.
3122 @param[in] IoDev Handle used to access configuration space of PCI device.
3126 IN PCI_CONFIG_SPACE
*ConfigSpace
,
3128 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
3131 PCI_DEVICE_INDEPENDENT_REGION
*Common
;
3132 PCI_HEADER_TYPE HeaderType
;
3134 Common
= &(ConfigSpace
->Common
);
3136 ShellPrintEx (-1, -1, L
"\r\n");
3139 // Print Vendor Id and Device Id
3141 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_PCI_LINE_VID_DID
), gShellDebug1HiiHandle
,
3142 INDEX_OF (&(Common
->VendorId
)),
3144 INDEX_OF (&(Common
->DeviceId
)),
3149 // Print register Command
3151 PciExplainCommand (&(Common
->Command
));
3154 // Print register Status
3156 PciExplainStatus (&(Common
->Status
), TRUE
, PciUndefined
);
3159 // Print register Revision ID
3161 ShellPrintEx(-1, -1, L
"\r\n");
3162 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_PCI_LINE_RID
), gShellDebug1HiiHandle
,
3163 INDEX_OF (&(Common
->RevisionID
)),
3168 // Print register BIST
3170 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_PCI_LINE_BIST
), gShellDebug1HiiHandle
, INDEX_OF (&(Common
->BIST
)));
3171 if ((Common
->BIST
& BIT7
) != 0) {
3172 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_PCI_LINE_CAP
), gShellDebug1HiiHandle
, 0x0f & Common
->BIST
);
3174 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_PCI_LINE_CAP_NO
), gShellDebug1HiiHandle
);
3177 // Print register Cache Line Size
3179 ShellPrintHiiEx(-1, -1, NULL
,
3180 STRING_TOKEN (STR_PCI2_CACHE_LINE_SIZE
),
3181 gShellDebug1HiiHandle
,
3182 INDEX_OF (&(Common
->CacheLineSize
)),
3183 Common
->CacheLineSize
3187 // Print register Latency Timer
3189 ShellPrintHiiEx(-1, -1, NULL
,
3190 STRING_TOKEN (STR_PCI2_LATENCY_TIMER
),
3191 gShellDebug1HiiHandle
,
3192 INDEX_OF (&(Common
->LatencyTimer
)),
3193 Common
->LatencyTimer
3197 // Print register Header Type
3199 ShellPrintHiiEx(-1, -1, NULL
,
3200 STRING_TOKEN (STR_PCI2_HEADER_TYPE
),
3201 gShellDebug1HiiHandle
,
3202 INDEX_OF (&(Common
->HeaderType
)),
3206 if ((Common
->HeaderType
& BIT7
) != 0) {
3207 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_MULTI_FUNCTION
), gShellDebug1HiiHandle
);
3210 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_SINGLE_FUNCTION
), gShellDebug1HiiHandle
);
3213 HeaderType
= (PCI_HEADER_TYPE
)(UINT8
) (Common
->HeaderType
& 0x7f);
3214 switch (HeaderType
) {
3216 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_PCI_DEVICE
), gShellDebug1HiiHandle
);
3220 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_P2P_BRIDGE
), gShellDebug1HiiHandle
);
3223 case PciCardBusBridge
:
3224 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_CARDBUS_BRIDGE
), gShellDebug1HiiHandle
);
3228 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_RESERVED
), gShellDebug1HiiHandle
);
3229 HeaderType
= PciUndefined
;
3233 // Print register Class Code
3235 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_CLASS
), gShellDebug1HiiHandle
);
3236 PciPrintClassCode ((UINT8
*) Common
->ClassCode
, TRUE
);
3237 ShellPrintEx (-1, -1, L
"\r\n");
3241 Explain the device specific part of data in PCI configuration space.
3243 @param[in] Device Data in PCI configuration space.
3244 @param[in] Address Address used to access configuration space of this PCI device.
3245 @param[in] IoDev Handle used to access configuration space of PCI device.
3247 @retval EFI_SUCCESS The command completed successfully.
3250 PciExplainDeviceData (
3251 IN PCI_DEVICE_HEADER_TYPE_REGION
*Device
,
3253 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
3262 // Print Base Address Registers(Bar). When Bar = 0, this Bar does not
3263 // exist. If these no Bar for this function, print "none", otherwise
3264 // list detail information about this Bar.
3266 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_BASE_ADDR
), gShellDebug1HiiHandle
, INDEX_OF (Device
->Bar
));
3269 BarCount
= sizeof (Device
->Bar
) / sizeof (Device
->Bar
[0]);
3270 for (Index
= 0; Index
< BarCount
; Index
++) {
3271 if (Device
->Bar
[Index
] == 0) {
3277 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_START_TYPE
), gShellDebug1HiiHandle
);
3278 ShellPrintEx (-1, -1, L
" --------------------------------------------------------------------------");
3281 Status
= PciExplainBar (
3282 &(Device
->Bar
[Index
]),
3283 &(mConfigSpace
->Common
.Command
),
3289 if (EFI_ERROR (Status
)) {
3295 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_NONE
), gShellDebug1HiiHandle
);
3298 ShellPrintEx (-1, -1, L
"\r\n --------------------------------------------------------------------------");
3302 // Print register Expansion ROM Base Address
3304 if ((Device
->ExpansionRomBar
& BIT0
) == 0) {
3305 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_EXPANSION_ROM_DISABLED
), gShellDebug1HiiHandle
, INDEX_OF (&(Device
->ExpansionRomBar
)));
3308 ShellPrintHiiEx(-1, -1, NULL
,
3309 STRING_TOKEN (STR_PCI2_EXPANSION_ROM_BASE
),
3310 gShellDebug1HiiHandle
,
3311 INDEX_OF (&(Device
->ExpansionRomBar
)),
3312 Device
->ExpansionRomBar
3316 // Print register Cardbus CIS ptr
3318 ShellPrintHiiEx(-1, -1, NULL
,
3319 STRING_TOKEN (STR_PCI2_CARDBUS_CIS
),
3320 gShellDebug1HiiHandle
,
3321 INDEX_OF (&(Device
->CISPtr
)),
3326 // Print register Sub-vendor ID and subsystem ID
3328 ShellPrintHiiEx(-1, -1, NULL
,
3329 STRING_TOKEN (STR_PCI2_SUB_VENDOR_ID
),
3330 gShellDebug1HiiHandle
,
3331 INDEX_OF (&(Device
->SubsystemVendorID
)),
3332 Device
->SubsystemVendorID
3335 ShellPrintHiiEx(-1, -1, NULL
,
3336 STRING_TOKEN (STR_PCI2_SUBSYSTEM_ID
),
3337 gShellDebug1HiiHandle
,
3338 INDEX_OF (&(Device
->SubsystemID
)),
3343 // Print register Capabilities Ptr
3345 ShellPrintHiiEx(-1, -1, NULL
,
3346 STRING_TOKEN (STR_PCI2_CAPABILITIES_PTR
),
3347 gShellDebug1HiiHandle
,
3348 INDEX_OF (&(Device
->CapabilityPtr
)),
3349 Device
->CapabilityPtr
3353 // Print register Interrupt Line and interrupt pin
3355 ShellPrintHiiEx(-1, -1, NULL
,
3356 STRING_TOKEN (STR_PCI2_INTERRUPT_LINE
),
3357 gShellDebug1HiiHandle
,
3358 INDEX_OF (&(Device
->InterruptLine
)),
3359 Device
->InterruptLine
3362 ShellPrintHiiEx(-1, -1, NULL
,
3363 STRING_TOKEN (STR_PCI2_INTERRUPT_PIN
),
3364 gShellDebug1HiiHandle
,
3365 INDEX_OF (&(Device
->InterruptPin
)),
3366 Device
->InterruptPin
3370 // Print register Min_Gnt and Max_Lat
3372 ShellPrintHiiEx(-1, -1, NULL
,
3373 STRING_TOKEN (STR_PCI2_MIN_GNT
),
3374 gShellDebug1HiiHandle
,
3375 INDEX_OF (&(Device
->MinGnt
)),
3379 ShellPrintHiiEx(-1, -1, NULL
,
3380 STRING_TOKEN (STR_PCI2_MAX_LAT
),
3381 gShellDebug1HiiHandle
,
3382 INDEX_OF (&(Device
->MaxLat
)),
3390 Explain the bridge specific part of data in PCI configuration space.
3392 @param[in] Bridge Bridge specific data region in PCI configuration space.
3393 @param[in] Address Address used to access configuration space of this PCI device.
3394 @param[in] IoDev Handle used to access configuration space of PCI device.
3396 @retval EFI_SUCCESS The command completed successfully.
3399 PciExplainBridgeData (
3400 IN PCI_BRIDGE_CONTROL_REGISTER
*Bridge
,
3402 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
3412 // Print Base Address Registers. When Bar = 0, this Bar does not
3413 // exist. If these no Bar for this function, print "none", otherwise
3414 // list detail information about this Bar.
3416 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_BASE_ADDRESS
), gShellDebug1HiiHandle
, INDEX_OF (&(Bridge
->Bar
)));
3419 BarCount
= sizeof (Bridge
->Bar
) / sizeof (Bridge
->Bar
[0]);
3421 for (Index
= 0; Index
< BarCount
; Index
++) {
3422 if (Bridge
->Bar
[Index
] == 0) {
3428 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_START_TYPE_2
), gShellDebug1HiiHandle
);
3429 ShellPrintEx (-1, -1, L
" --------------------------------------------------------------------------");
3432 Status
= PciExplainBar (
3433 &(Bridge
->Bar
[Index
]),
3434 &(mConfigSpace
->Common
.Command
),
3440 if (EFI_ERROR (Status
)) {
3446 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_NONE
), gShellDebug1HiiHandle
);
3448 ShellPrintEx (-1, -1, L
"\r\n --------------------------------------------------------------------------");
3452 // Expansion register ROM Base Address
3454 if ((Bridge
->ExpansionRomBAR
& BIT0
) == 0) {
3455 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_NO_EXPANSION_ROM
), gShellDebug1HiiHandle
, INDEX_OF (&(Bridge
->ExpansionRomBAR
)));
3458 ShellPrintHiiEx(-1, -1, NULL
,
3459 STRING_TOKEN (STR_PCI2_EXPANSION_ROM_BASE_2
),
3460 gShellDebug1HiiHandle
,
3461 INDEX_OF (&(Bridge
->ExpansionRomBAR
)),
3462 Bridge
->ExpansionRomBAR
3466 // Print Bus Numbers(Primary, Secondary, and Subordinate
3468 ShellPrintHiiEx(-1, -1, NULL
,
3469 STRING_TOKEN (STR_PCI2_BUS_NUMBERS
),
3470 gShellDebug1HiiHandle
,
3471 INDEX_OF (&(Bridge
->PrimaryBus
)),
3472 INDEX_OF (&(Bridge
->SecondaryBus
)),
3473 INDEX_OF (&(Bridge
->SubordinateBus
))
3476 ShellPrintEx (-1, -1, L
" ------------------------------------------------------\r\n");
3478 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_BRIDGE
), gShellDebug1HiiHandle
, Bridge
->PrimaryBus
);
3479 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_BRIDGE
), gShellDebug1HiiHandle
, Bridge
->SecondaryBus
);
3480 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_BRIDGE
), gShellDebug1HiiHandle
, Bridge
->SubordinateBus
);
3483 // Print register Secondary Latency Timer
3485 ShellPrintHiiEx(-1, -1, NULL
,
3486 STRING_TOKEN (STR_PCI2_SECONDARY_TIMER
),
3487 gShellDebug1HiiHandle
,
3488 INDEX_OF (&(Bridge
->SecondaryLatencyTimer
)),
3489 Bridge
->SecondaryLatencyTimer
3493 // Print register Secondary Status
3495 PciExplainStatus (&(Bridge
->SecondaryStatus
), FALSE
, PciP2pBridge
);
3498 // Print I/O and memory ranges this bridge forwards. There are 3 resource
3499 // types: I/O, memory, and pre-fetchable memory. For each resource type,
3500 // base and limit address are listed.
3502 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_RESOURCE_TYPE
), gShellDebug1HiiHandle
);
3503 ShellPrintEx (-1, -1, L
"----------------------------------------------------------------------\r\n");
3508 IoAddress32
= (Bridge
->IoBaseUpper16
<< 16 | Bridge
->IoBase
<< 8);
3509 IoAddress32
&= 0xfffff000;
3510 ShellPrintHiiEx(-1, -1, NULL
,
3511 STRING_TOKEN (STR_PCI2_TWO_VARS
),
3512 gShellDebug1HiiHandle
,
3513 INDEX_OF (&(Bridge
->IoBase
)),
3517 IoAddress32
= (Bridge
->IoLimitUpper16
<< 16 | Bridge
->IoLimit
<< 8);
3518 IoAddress32
|= 0x00000fff;
3519 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_ONE_VAR
), gShellDebug1HiiHandle
, IoAddress32
);
3522 // Memory Base & Limit
3524 ShellPrintHiiEx(-1, -1, NULL
,
3525 STRING_TOKEN (STR_PCI2_MEMORY
),
3526 gShellDebug1HiiHandle
,
3527 INDEX_OF (&(Bridge
->MemoryBase
)),
3528 (Bridge
->MemoryBase
<< 16) & 0xfff00000
3531 ShellPrintHiiEx(-1, -1, NULL
,
3532 STRING_TOKEN (STR_PCI2_ONE_VAR
),
3533 gShellDebug1HiiHandle
,
3534 (Bridge
->MemoryLimit
<< 16) | 0x000fffff
3538 // Pre-fetch-able Memory Base & Limit
3540 ShellPrintHiiEx(-1, -1, NULL
,
3541 STRING_TOKEN (STR_PCI2_PREFETCHABLE
),
3542 gShellDebug1HiiHandle
,
3543 INDEX_OF (&(Bridge
->PrefetchableMemoryBase
)),
3544 Bridge
->PrefetchableBaseUpper32
,
3545 (Bridge
->PrefetchableMemoryBase
<< 16) & 0xfff00000
3548 ShellPrintHiiEx(-1, -1, NULL
,
3549 STRING_TOKEN (STR_PCI2_TWO_VARS_2
),
3550 gShellDebug1HiiHandle
,
3551 Bridge
->PrefetchableLimitUpper32
,
3552 (Bridge
->PrefetchableMemoryLimit
<< 16) | 0x000fffff
3556 // Print register Capabilities Pointer
3558 ShellPrintHiiEx(-1, -1, NULL
,
3559 STRING_TOKEN (STR_PCI2_CAPABILITIES_PTR_2
),
3560 gShellDebug1HiiHandle
,
3561 INDEX_OF (&(Bridge
->CapabilityPtr
)),
3562 Bridge
->CapabilityPtr
3566 // Print register Bridge Control
3568 PciExplainBridgeControl (&(Bridge
->BridgeControl
), PciP2pBridge
);
3571 // Print register Interrupt Line & PIN
3573 ShellPrintHiiEx(-1, -1, NULL
,
3574 STRING_TOKEN (STR_PCI2_INTERRUPT_LINE_2
),
3575 gShellDebug1HiiHandle
,
3576 INDEX_OF (&(Bridge
->InterruptLine
)),
3577 Bridge
->InterruptLine
3580 ShellPrintHiiEx(-1, -1, NULL
,
3581 STRING_TOKEN (STR_PCI2_INTERRUPT_PIN
),
3582 gShellDebug1HiiHandle
,
3583 INDEX_OF (&(Bridge
->InterruptPin
)),
3584 Bridge
->InterruptPin
3591 Explain the Base Address Register(Bar) in PCI configuration space.
3593 @param[in] Bar Points to the Base Address Register intended to interpret.
3594 @param[in] Command Points to the register Command.
3595 @param[in] Address Address used to access configuration space of this PCI device.
3596 @param[in] IoDev Handle used to access configuration space of PCI device.
3597 @param[in, out] Index The Index.
3599 @retval EFI_SUCCESS The command completed successfully.
3606 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
,
3627 // According the bar type, list detail about this bar, for example: 32 or
3628 // 64 bits; pre-fetchable or not.
3630 if ((*Bar
& BIT0
) == 0) {
3632 // This bar is of memory type
3636 if ((*Bar
& BIT1
) == 0 && (*Bar
& BIT2
) == 0) {
3637 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_BAR
), gShellDebug1HiiHandle
, *Bar
& 0xfffffff0);
3638 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_MEM
), gShellDebug1HiiHandle
);
3639 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_32_BITS
), gShellDebug1HiiHandle
);
3641 } else if ((*Bar
& BIT1
) == 0 && (*Bar
& BIT2
) != 0) {
3643 CopyMem (&Bar64
, Bar
, sizeof (UINT64
));
3644 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_ONE_VAR_2
), gShellDebug1HiiHandle
, (UINT32
) RShiftU64 ((Bar64
& 0xfffffffffffffff0ULL
), 32));
3645 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_ONE_VAR_3
), gShellDebug1HiiHandle
, (UINT32
) (Bar64
& 0xfffffffffffffff0ULL
));
3646 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_MEM
), gShellDebug1HiiHandle
);
3647 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_64_BITS
), gShellDebug1HiiHandle
);
3655 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_BAR
), gShellDebug1HiiHandle
, *Bar
& 0xfffffff0);
3656 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_MEM_2
), gShellDebug1HiiHandle
);
3659 if ((*Bar
& BIT3
) == 0) {
3660 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_NO
), gShellDebug1HiiHandle
);
3663 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_YES
), gShellDebug1HiiHandle
);
3668 // This bar is of io type
3671 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_ONE_VAR_4
), gShellDebug1HiiHandle
, *Bar
& 0xfffffffc);
3672 ShellPrintEx (-1, -1, L
"I/O ");
3676 // Get BAR length(or the amount of resource this bar demands for). To get
3677 // Bar length, first we should temporarily disable I/O and memory access
3678 // of this function(by set bits in the register Command), then write all
3679 // "1"s to this bar. The bar value read back is the amount of resource
3680 // this bar demands for.
3683 // Disable io & mem access
3685 OldCommand
= *Command
;
3686 NewCommand
= (UINT16
) (OldCommand
& 0xfffc);
3687 RegAddress
= Address
| INDEX_OF (Command
);
3688 IoDev
->Pci
.Write (IoDev
, EfiPciWidthUint16
, RegAddress
, 1, &NewCommand
);
3690 RegAddress
= Address
| INDEX_OF (Bar
);
3693 // Read after write the BAR to get the size
3697 NewBar32
= 0xffffffff;
3699 IoDev
->Pci
.Write (IoDev
, EfiPciWidthUint32
, RegAddress
, 1, &NewBar32
);
3700 IoDev
->Pci
.Read (IoDev
, EfiPciWidthUint32
, RegAddress
, 1, &NewBar32
);
3701 IoDev
->Pci
.Write (IoDev
, EfiPciWidthUint32
, RegAddress
, 1, &OldBar32
);
3704 NewBar32
= NewBar32
& 0xfffffff0;
3705 NewBar32
= (~NewBar32
) + 1;
3708 NewBar32
= NewBar32
& 0xfffffffc;
3709 NewBar32
= (~NewBar32
) + 1;
3710 NewBar32
= NewBar32
& 0x0000ffff;
3715 CopyMem (&OldBar64
, Bar
, sizeof (UINT64
));
3716 NewBar64
= 0xffffffffffffffffULL
;
3718 IoDev
->Pci
.Write (IoDev
, EfiPciWidthUint32
, RegAddress
, 2, &NewBar64
);
3719 IoDev
->Pci
.Read (IoDev
, EfiPciWidthUint32
, RegAddress
, 2, &NewBar64
);
3720 IoDev
->Pci
.Write (IoDev
, EfiPciWidthUint32
, RegAddress
, 2, &OldBar64
);
3723 NewBar64
= NewBar64
& 0xfffffffffffffff0ULL
;
3724 NewBar64
= (~NewBar64
) + 1;
3727 NewBar64
= NewBar64
& 0xfffffffffffffffcULL
;
3728 NewBar64
= (~NewBar64
) + 1;
3729 NewBar64
= NewBar64
& 0x000000000000ffff;
3733 // Enable io & mem access
3735 RegAddress
= Address
| INDEX_OF (Command
);
3736 IoDev
->Pci
.Write (IoDev
, EfiPciWidthUint16
, RegAddress
, 1, &OldCommand
);
3740 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_NEWBAR_32
), gShellDebug1HiiHandle
, NewBar32
);
3741 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_NEWBAR_32_2
), gShellDebug1HiiHandle
, NewBar32
+ (*Bar
& 0xfffffff0) - 1);
3744 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_RSHIFT
), gShellDebug1HiiHandle
, (UINT32
) RShiftU64 (NewBar64
, 32));
3745 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_RSHIFT
), gShellDebug1HiiHandle
, (UINT32
) NewBar64
);
3746 ShellPrintEx (-1, -1, L
" ");
3747 ShellPrintHiiEx(-1, -1, NULL
,
3748 STRING_TOKEN (STR_PCI2_RSHIFT
),
3749 gShellDebug1HiiHandle
,
3750 (UINT32
) RShiftU64 ((NewBar64
+ (Bar64
& 0xfffffffffffffff0ULL
) - 1), 32)
3752 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_RSHIFT
), gShellDebug1HiiHandle
, (UINT32
) (NewBar64
+ (Bar64
& 0xfffffffffffffff0ULL
) - 1));
3756 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_NEWBAR_32_3
), gShellDebug1HiiHandle
, NewBar32
);
3757 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_NEWBAR_32_4
), gShellDebug1HiiHandle
, NewBar32
+ (*Bar
& 0xfffffffc) - 1);
3764 Explain the cardbus specific part of data in PCI configuration space.
3766 @param[in] CardBus CardBus specific region of PCI configuration space.
3767 @param[in] Address Address used to access configuration space of this PCI device.
3768 @param[in] IoDev Handle used to access configuration space of PCI device.
3770 @retval EFI_SUCCESS The command completed successfully.
3773 PciExplainCardBusData (
3774 IN PCI_CARDBUS_CONTROL_REGISTER
*CardBus
,
3776 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
3780 PCI_CARDBUS_DATA
*CardBusData
;
3782 ShellPrintHiiEx(-1, -1, NULL
,
3783 STRING_TOKEN (STR_PCI2_CARDBUS_SOCKET
),
3784 gShellDebug1HiiHandle
,
3785 INDEX_OF (&(CardBus
->CardBusSocketReg
)),
3786 CardBus
->CardBusSocketReg
3790 // Print Secondary Status
3792 PciExplainStatus (&(CardBus
->SecondaryStatus
), FALSE
, PciCardBusBridge
);
3795 // Print Bus Numbers(Primary bus number, CardBus bus number, and
3796 // Subordinate bus number
3798 ShellPrintHiiEx(-1, -1, NULL
,
3799 STRING_TOKEN (STR_PCI2_BUS_NUMBERS_2
),
3800 gShellDebug1HiiHandle
,
3801 INDEX_OF (&(CardBus
->PciBusNumber
)),
3802 INDEX_OF (&(CardBus
->CardBusBusNumber
)),
3803 INDEX_OF (&(CardBus
->SubordinateBusNumber
))
3806 ShellPrintEx (-1, -1, L
" ------------------------------------------------------\r\n");
3808 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_CARDBUS
), gShellDebug1HiiHandle
, CardBus
->PciBusNumber
);
3809 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_CARDBUS_2
), gShellDebug1HiiHandle
, CardBus
->CardBusBusNumber
);
3810 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_CARDBUS_3
), gShellDebug1HiiHandle
, CardBus
->SubordinateBusNumber
);
3813 // Print CardBus Latency Timer
3815 ShellPrintHiiEx(-1, -1, NULL
,
3816 STRING_TOKEN (STR_PCI2_CARDBUS_LATENCY
),
3817 gShellDebug1HiiHandle
,
3818 INDEX_OF (&(CardBus
->CardBusLatencyTimer
)),
3819 CardBus
->CardBusLatencyTimer
3823 // Print Memory/Io ranges this cardbus bridge forwards
3825 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_RESOURCE_TYPE_2
), gShellDebug1HiiHandle
);
3826 ShellPrintEx (-1, -1, L
"----------------------------------------------------------------------\r\n");
3828 ShellPrintHiiEx(-1, -1, NULL
,
3829 STRING_TOKEN (STR_PCI2_MEM_3
),
3830 gShellDebug1HiiHandle
,
3831 INDEX_OF (&(CardBus
->MemoryBase0
)),
3832 CardBus
->BridgeControl
& BIT8
? L
" Prefetchable" : L
"Non-Prefetchable",
3833 CardBus
->MemoryBase0
& 0xfffff000,
3834 CardBus
->MemoryLimit0
| 0x00000fff
3837 ShellPrintHiiEx(-1, -1, NULL
,
3838 STRING_TOKEN (STR_PCI2_MEM_3
),
3839 gShellDebug1HiiHandle
,
3840 INDEX_OF (&(CardBus
->MemoryBase1
)),
3841 CardBus
->BridgeControl
& BIT9
? L
" Prefetchable" : L
"Non-Prefetchable",
3842 CardBus
->MemoryBase1
& 0xfffff000,
3843 CardBus
->MemoryLimit1
| 0x00000fff
3846 Io32Bit
= (BOOLEAN
) (CardBus
->IoBase0
& BIT0
);
3847 ShellPrintHiiEx(-1, -1, NULL
,
3848 STRING_TOKEN (STR_PCI2_IO_2
),
3849 gShellDebug1HiiHandle
,
3850 INDEX_OF (&(CardBus
->IoBase0
)),
3851 Io32Bit
? L
" 32 bit" : L
" 16 bit",
3852 CardBus
->IoBase0
& (Io32Bit
? 0xfffffffc : 0x0000fffc),
3853 (CardBus
->IoLimit0
& (Io32Bit
? 0xffffffff : 0x0000ffff)) | 0x00000003
3856 Io32Bit
= (BOOLEAN
) (CardBus
->IoBase1
& BIT0
);
3857 ShellPrintHiiEx(-1, -1, NULL
,
3858 STRING_TOKEN (STR_PCI2_IO_2
),
3859 gShellDebug1HiiHandle
,
3860 INDEX_OF (&(CardBus
->IoBase1
)),
3861 Io32Bit
? L
" 32 bit" : L
" 16 bit",
3862 CardBus
->IoBase1
& (Io32Bit
? 0xfffffffc : 0x0000fffc),
3863 (CardBus
->IoLimit1
& (Io32Bit
? 0xffffffff : 0x0000ffff)) | 0x00000003
3867 // Print register Interrupt Line & PIN
3869 ShellPrintHiiEx(-1, -1, NULL
,
3870 STRING_TOKEN (STR_PCI2_INTERRUPT_LINE_3
),
3871 gShellDebug1HiiHandle
,
3872 INDEX_OF (&(CardBus
->InterruptLine
)),
3873 CardBus
->InterruptLine
,
3874 INDEX_OF (&(CardBus
->InterruptPin
)),
3875 CardBus
->InterruptPin
3879 // Print register Bridge Control
3881 PciExplainBridgeControl (&(CardBus
->BridgeControl
), PciCardBusBridge
);
3884 // Print some registers in data region of PCI configuration space for cardbus
3885 // bridge. Fields include: Sub VendorId, Subsystem ID, and Legacy Mode Base
3888 CardBusData
= (PCI_CARDBUS_DATA
*) ((UINT8
*) CardBus
+ sizeof (PCI_CARDBUS_CONTROL_REGISTER
));
3890 ShellPrintHiiEx(-1, -1, NULL
,
3891 STRING_TOKEN (STR_PCI2_SUB_VENDOR_ID_2
),
3892 gShellDebug1HiiHandle
,
3893 INDEX_OF (&(CardBusData
->SubVendorId
)),
3894 CardBusData
->SubVendorId
,
3895 INDEX_OF (&(CardBusData
->SubSystemId
)),
3896 CardBusData
->SubSystemId
3899 ShellPrintHiiEx(-1, -1, NULL
,
3900 STRING_TOKEN (STR_PCI2_OPTIONAL
),
3901 gShellDebug1HiiHandle
,
3902 INDEX_OF (&(CardBusData
->LegacyBase
)),
3903 CardBusData
->LegacyBase
3910 Explain each meaningful bit of register Status. The definition of Status is
3911 slightly different depending on the PCI header type.
3913 @param[in] Status Points to the content of register Status.
3914 @param[in] MainStatus Indicates if this register is main status(not secondary
3916 @param[in] HeaderType Header type of this PCI device.
3918 @retval EFI_SUCCESS The command completed successfully.
3923 IN BOOLEAN MainStatus
,
3924 IN PCI_HEADER_TYPE HeaderType
3928 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_STATUS
), gShellDebug1HiiHandle
, INDEX_OF (Status
), *Status
);
3931 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_SECONDARY_STATUS
), gShellDebug1HiiHandle
, INDEX_OF (Status
), *Status
);
3934 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_NEW_CAPABILITIES
), gShellDebug1HiiHandle
, (*Status
& BIT4
) != 0);
3937 // Bit 5 is meaningless for CardBus Bridge
3939 if (HeaderType
== PciCardBusBridge
) {
3940 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_66_CAPABLE
), gShellDebug1HiiHandle
, (*Status
& BIT5
) != 0);
3943 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_66_CAPABLE_2
), gShellDebug1HiiHandle
, (*Status
& BIT5
) != 0);
3946 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_FAST_BACK
), gShellDebug1HiiHandle
, (*Status
& BIT7
) != 0);
3948 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_MASTER_DATA
), gShellDebug1HiiHandle
, (*Status
& BIT8
) != 0);
3950 // Bit 9 and bit 10 together decides the DEVSEL timing
3952 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_DEVSEL_TIMING
), gShellDebug1HiiHandle
);
3953 if ((*Status
& BIT9
) == 0 && (*Status
& BIT10
) == 0) {
3954 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_FAST
), gShellDebug1HiiHandle
);
3956 } else if ((*Status
& BIT9
) != 0 && (*Status
& BIT10
) == 0) {
3957 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_MEDIUM
), gShellDebug1HiiHandle
);
3959 } else if ((*Status
& BIT9
) == 0 && (*Status
& BIT10
) != 0) {
3960 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_SLOW
), gShellDebug1HiiHandle
);
3963 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_RESERVED_2
), gShellDebug1HiiHandle
);
3966 ShellPrintHiiEx(-1, -1, NULL
,
3967 STRING_TOKEN (STR_PCI2_SIGNALED_TARGET
),
3968 gShellDebug1HiiHandle
,
3969 (*Status
& BIT11
) != 0
3972 ShellPrintHiiEx(-1, -1, NULL
,
3973 STRING_TOKEN (STR_PCI2_RECEIVED_TARGET
),
3974 gShellDebug1HiiHandle
,
3975 (*Status
& BIT12
) != 0
3978 ShellPrintHiiEx(-1, -1, NULL
,
3979 STRING_TOKEN (STR_PCI2_RECEIVED_MASTER
),
3980 gShellDebug1HiiHandle
,
3981 (*Status
& BIT13
) != 0
3985 ShellPrintHiiEx(-1, -1, NULL
,
3986 STRING_TOKEN (STR_PCI2_SIGNALED_ERROR
),
3987 gShellDebug1HiiHandle
,
3988 (*Status
& BIT14
) != 0
3992 ShellPrintHiiEx(-1, -1, NULL
,
3993 STRING_TOKEN (STR_PCI2_RECEIVED_ERROR
),
3994 gShellDebug1HiiHandle
,
3995 (*Status
& BIT14
) != 0
3999 ShellPrintHiiEx(-1, -1, NULL
,
4000 STRING_TOKEN (STR_PCI2_DETECTED_ERROR
),
4001 gShellDebug1HiiHandle
,
4002 (*Status
& BIT15
) != 0
4009 Explain each meaningful bit of register Command.
4011 @param[in] Command Points to the content of register Command.
4013 @retval EFI_SUCCESS The command completed successfully.
4021 // Print the binary value of register Command
4023 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_COMMAND
), gShellDebug1HiiHandle
, INDEX_OF (Command
), *Command
);
4026 // Explain register Command bit by bit
4028 ShellPrintHiiEx(-1, -1, NULL
,
4029 STRING_TOKEN (STR_PCI2_SPACE_ACCESS_DENIED
),
4030 gShellDebug1HiiHandle
,
4031 (*Command
& BIT0
) != 0
4034 ShellPrintHiiEx(-1, -1, NULL
,
4035 STRING_TOKEN (STR_PCI2_MEMORY_SPACE
),
4036 gShellDebug1HiiHandle
,
4037 (*Command
& BIT1
) != 0
4040 ShellPrintHiiEx(-1, -1, NULL
,
4041 STRING_TOKEN (STR_PCI2_BEHAVE_BUS_MASTER
),
4042 gShellDebug1HiiHandle
,
4043 (*Command
& BIT2
) != 0
4046 ShellPrintHiiEx(-1, -1, NULL
,
4047 STRING_TOKEN (STR_PCI2_MONITOR_SPECIAL_CYCLE
),
4048 gShellDebug1HiiHandle
,
4049 (*Command
& BIT3
) != 0
4052 ShellPrintHiiEx(-1, -1, NULL
,
4053 STRING_TOKEN (STR_PCI2_MEM_WRITE_INVALIDATE
),
4054 gShellDebug1HiiHandle
,
4055 (*Command
& BIT4
) != 0
4058 ShellPrintHiiEx(-1, -1, NULL
,
4059 STRING_TOKEN (STR_PCI2_PALETTE_SNOOPING
),
4060 gShellDebug1HiiHandle
,
4061 (*Command
& BIT5
) != 0
4064 ShellPrintHiiEx(-1, -1, NULL
,
4065 STRING_TOKEN (STR_PCI2_ASSERT_PERR
),
4066 gShellDebug1HiiHandle
,
4067 (*Command
& BIT6
) != 0
4070 ShellPrintHiiEx(-1, -1, NULL
,
4071 STRING_TOKEN (STR_PCI2_DO_ADDR_STEPPING
),
4072 gShellDebug1HiiHandle
,
4073 (*Command
& BIT7
) != 0
4076 ShellPrintHiiEx(-1, -1, NULL
,
4077 STRING_TOKEN (STR_PCI2_SERR_DRIVER
),
4078 gShellDebug1HiiHandle
,
4079 (*Command
& BIT8
) != 0
4082 ShellPrintHiiEx(-1, -1, NULL
,
4083 STRING_TOKEN (STR_PCI2_FAST_BACK_2
),
4084 gShellDebug1HiiHandle
,
4085 (*Command
& BIT9
) != 0
4092 Explain each meaningful bit of register Bridge Control.
4094 @param[in] BridgeControl Points to the content of register Bridge Control.
4095 @param[in] HeaderType The headertype.
4097 @retval EFI_SUCCESS The command completed successfully.
4100 PciExplainBridgeControl (
4101 IN UINT16
*BridgeControl
,
4102 IN PCI_HEADER_TYPE HeaderType
4105 ShellPrintHiiEx(-1, -1, NULL
,
4106 STRING_TOKEN (STR_PCI2_BRIDGE_CONTROL
),
4107 gShellDebug1HiiHandle
,
4108 INDEX_OF (BridgeControl
),
4112 ShellPrintHiiEx(-1, -1, NULL
,
4113 STRING_TOKEN (STR_PCI2_PARITY_ERROR
),
4114 gShellDebug1HiiHandle
,
4115 (*BridgeControl
& BIT0
) != 0
4117 ShellPrintHiiEx(-1, -1, NULL
,
4118 STRING_TOKEN (STR_PCI2_SERR_ENABLE
),
4119 gShellDebug1HiiHandle
,
4120 (*BridgeControl
& BIT1
) != 0
4122 ShellPrintHiiEx(-1, -1, NULL
,
4123 STRING_TOKEN (STR_PCI2_ISA_ENABLE
),
4124 gShellDebug1HiiHandle
,
4125 (*BridgeControl
& BIT2
) != 0
4127 ShellPrintHiiEx(-1, -1, NULL
,
4128 STRING_TOKEN (STR_PCI2_VGA_ENABLE
),
4129 gShellDebug1HiiHandle
,
4130 (*BridgeControl
& BIT3
) != 0
4132 ShellPrintHiiEx(-1, -1, NULL
,
4133 STRING_TOKEN (STR_PCI2_MASTER_ABORT
),
4134 gShellDebug1HiiHandle
,
4135 (*BridgeControl
& BIT5
) != 0
4139 // Register Bridge Control has some slight differences between P2P bridge
4140 // and Cardbus bridge from bit 6 to bit 11.
4142 if (HeaderType
== PciP2pBridge
) {
4143 ShellPrintHiiEx(-1, -1, NULL
,
4144 STRING_TOKEN (STR_PCI2_SECONDARY_BUS_RESET
),
4145 gShellDebug1HiiHandle
,
4146 (*BridgeControl
& BIT6
) != 0
4148 ShellPrintHiiEx(-1, -1, NULL
,
4149 STRING_TOKEN (STR_PCI2_FAST_ENABLE
),
4150 gShellDebug1HiiHandle
,
4151 (*BridgeControl
& BIT7
) != 0
4153 ShellPrintHiiEx(-1, -1, NULL
,
4154 STRING_TOKEN (STR_PCI2_PRIMARY_DISCARD_TIMER
),
4155 gShellDebug1HiiHandle
,
4156 (*BridgeControl
& BIT8
)!=0 ? L
"2^10" : L
"2^15"
4158 ShellPrintHiiEx(-1, -1, NULL
,
4159 STRING_TOKEN (STR_PCI2_SECONDARY_DISCARD_TIMER
),
4160 gShellDebug1HiiHandle
,
4161 (*BridgeControl
& BIT9
)!=0 ? L
"2^10" : L
"2^15"
4163 ShellPrintHiiEx(-1, -1, NULL
,
4164 STRING_TOKEN (STR_PCI2_DISCARD_TIMER_STATUS
),
4165 gShellDebug1HiiHandle
,
4166 (*BridgeControl
& BIT10
) != 0
4168 ShellPrintHiiEx(-1, -1, NULL
,
4169 STRING_TOKEN (STR_PCI2_DISCARD_TIMER_SERR
),
4170 gShellDebug1HiiHandle
,
4171 (*BridgeControl
& BIT11
) != 0
4175 ShellPrintHiiEx(-1, -1, NULL
,
4176 STRING_TOKEN (STR_PCI2_CARDBUS_RESET
),
4177 gShellDebug1HiiHandle
,
4178 (*BridgeControl
& BIT6
) != 0
4180 ShellPrintHiiEx(-1, -1, NULL
,
4181 STRING_TOKEN (STR_PCI2_IREQ_ENABLE
),
4182 gShellDebug1HiiHandle
,
4183 (*BridgeControl
& BIT7
) != 0
4185 ShellPrintHiiEx(-1, -1, NULL
,
4186 STRING_TOKEN (STR_PCI2_WRITE_POSTING_ENABLE
),
4187 gShellDebug1HiiHandle
,
4188 (*BridgeControl
& BIT10
) != 0
4196 Locate capability register block per capability ID.
4198 @param[in] ConfigSpace Data in PCI configuration space.
4199 @param[in] CapabilityId The capability ID.
4201 @return The offset of the register block per capability ID,
4202 or 0 if the register block cannot be found.
4205 LocatePciCapability (
4206 IN PCI_CONFIG_SPACE
*ConfigSpace
,
4207 IN UINT8 CapabilityId
4210 UINT8 CapabilityPtr
;
4211 EFI_PCI_CAPABILITY_HDR
*CapabilityEntry
;
4214 // To check the cpability of this device supports
4216 if ((ConfigSpace
->Common
.Status
& EFI_PCI_STATUS_CAPABILITY
) == 0) {
4220 switch ((PCI_HEADER_TYPE
)(ConfigSpace
->Common
.HeaderType
& 0x7f)) {
4222 CapabilityPtr
= ConfigSpace
->NonCommon
.Device
.CapabilityPtr
;
4225 CapabilityPtr
= ConfigSpace
->NonCommon
.Bridge
.CapabilityPtr
;
4227 case PciCardBusBridge
:
4228 CapabilityPtr
= ConfigSpace
->NonCommon
.CardBus
.Cap_Ptr
;
4234 while ((CapabilityPtr
>= 0x40) && ((CapabilityPtr
& 0x03) == 0x00)) {
4235 CapabilityEntry
= (EFI_PCI_CAPABILITY_HDR
*) ((UINT8
*) ConfigSpace
+ CapabilityPtr
);
4236 if (CapabilityEntry
->CapabilityID
== CapabilityId
) {
4237 return CapabilityPtr
;
4241 // Certain PCI device may incorrectly have capability pointing to itself,
4242 // break to avoid dead loop.
4244 if (CapabilityPtr
== CapabilityEntry
->NextItemPtr
) {
4248 CapabilityPtr
= CapabilityEntry
->NextItemPtr
;
4255 Print out information of the capability information.
4257 @param[in] PciExpressCap The pointer to the structure about the device.
4259 @retval EFI_SUCCESS The operation was successful.
4263 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
4266 CHAR16
*DevicePortType
;
4268 ShellPrintEx (-1, -1,
4269 L
" Capability Version(3:0): %E0x%04x%N\r\n",
4270 PciExpressCap
->Capability
.Bits
.Version
4272 if (PciExpressCap
->Capability
.Bits
.DevicePortType
< ARRAY_SIZE (DevicePortTypeTable
)) {
4273 DevicePortType
= DevicePortTypeTable
[PciExpressCap
->Capability
.Bits
.DevicePortType
];
4275 DevicePortType
= L
"Unknown Type";
4277 ShellPrintEx (-1, -1,
4278 L
" Device/PortType(7:4): %E%s%N\r\n",
4282 // 'Slot Implemented' is only valid for:
4283 // a) Root Port of PCI Express Root Complex, or
4284 // b) Downstream Port of PCI Express Switch
4286 if (PciExpressCap
->Capability
.Bits
.DevicePortType
== PCIE_DEVICE_PORT_TYPE_ROOT_PORT
||
4287 PciExpressCap
->Capability
.Bits
.DevicePortType
== PCIE_DEVICE_PORT_TYPE_DOWNSTREAM_PORT
) {
4288 ShellPrintEx (-1, -1,
4289 L
" Slot Implemented(8): %E%d%N\r\n",
4290 PciExpressCap
->Capability
.Bits
.SlotImplemented
4293 ShellPrintEx (-1, -1,
4294 L
" Interrupt Message Number(13:9): %E0x%05x%N\r\n",
4295 PciExpressCap
->Capability
.Bits
.InterruptMessageNumber
4301 Print out information of the device capability information.
4303 @param[in] PciExpressCap The pointer to the structure about the device.
4305 @retval EFI_SUCCESS The operation was successful.
4308 ExplainPcieDeviceCap (
4309 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
4312 UINT8 DevicePortType
;
4316 DevicePortType
= (UINT8
)PciExpressCap
->Capability
.Bits
.DevicePortType
;
4317 ShellPrintEx (-1, -1, L
" Max_Payload_Size Supported(2:0): ");
4318 if (PciExpressCap
->DeviceCapability
.Bits
.MaxPayloadSize
< 6) {
4319 ShellPrintEx (-1, -1, L
"%E%d bytes%N\r\n", 1 << (PciExpressCap
->DeviceCapability
.Bits
.MaxPayloadSize
+ 7));
4321 ShellPrintEx (-1, -1, L
"%EUnknown%N\r\n");
4323 ShellPrintEx (-1, -1,
4324 L
" Phantom Functions Supported(4:3): %E%d%N\r\n",
4325 PciExpressCap
->DeviceCapability
.Bits
.PhantomFunctions
4327 ShellPrintEx (-1, -1,
4328 L
" Extended Tag Field Supported(5): %E%d-bit Tag field supported%N\r\n",
4329 PciExpressCap
->DeviceCapability
.Bits
.ExtendedTagField
? 8 : 5
4332 // Endpoint L0s and L1 Acceptable Latency is only valid for Endpoint
4334 if (IS_PCIE_ENDPOINT (DevicePortType
)) {
4335 L0sLatency
= (UINT8
)PciExpressCap
->DeviceCapability
.Bits
.EndpointL0sAcceptableLatency
;
4336 L1Latency
= (UINT8
)PciExpressCap
->DeviceCapability
.Bits
.EndpointL1AcceptableLatency
;
4337 ShellPrintEx (-1, -1, L
" Endpoint L0s Acceptable Latency(8:6): ");
4338 if (L0sLatency
< 4) {
4339 ShellPrintEx (-1, -1, L
"%EMaximum of %d ns%N\r\n", 1 << (L0sLatency
+ 6));
4341 if (L0sLatency
< 7) {
4342 ShellPrintEx (-1, -1, L
"%EMaximum of %d us%N\r\n", 1 << (L0sLatency
- 3));
4344 ShellPrintEx (-1, -1, L
"%ENo limit%N\r\n");
4347 ShellPrintEx (-1, -1, L
" Endpoint L1 Acceptable Latency(11:9): ");
4348 if (L1Latency
< 7) {
4349 ShellPrintEx (-1, -1, L
"%EMaximum of %d us%N\r\n", 1 << (L1Latency
+ 1));
4351 ShellPrintEx (-1, -1, L
"%ENo limit%N\r\n");
4354 ShellPrintEx (-1, -1,
4355 L
" Role-based Error Reporting(15): %E%d%N\r\n",
4356 PciExpressCap
->DeviceCapability
.Bits
.RoleBasedErrorReporting
4359 // Only valid for Upstream Port:
4360 // a) Captured Slot Power Limit Value
4361 // b) Captured Slot Power Scale
4363 if (DevicePortType
== PCIE_DEVICE_PORT_TYPE_UPSTREAM_PORT
) {
4364 ShellPrintEx (-1, -1,
4365 L
" Captured Slot Power Limit Value(25:18): %E0x%02x%N\r\n",
4366 PciExpressCap
->DeviceCapability
.Bits
.CapturedSlotPowerLimitValue
4368 ShellPrintEx (-1, -1,
4369 L
" Captured Slot Power Limit Scale(27:26): %E%s%N\r\n",
4370 SlotPwrLmtScaleTable
[PciExpressCap
->DeviceCapability
.Bits
.CapturedSlotPowerLimitScale
]
4374 // Function Level Reset Capability is only valid for Endpoint
4376 if (IS_PCIE_ENDPOINT (DevicePortType
)) {
4377 ShellPrintEx (-1, -1,
4378 L
" Function Level Reset Capability(28): %E%d%N\r\n",
4379 PciExpressCap
->DeviceCapability
.Bits
.FunctionLevelReset
4386 Print out information of the device control information.
4388 @param[in] PciExpressCap The pointer to the structure about the device.
4390 @retval EFI_SUCCESS The operation was successful.
4393 ExplainPcieDeviceControl (
4394 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
4397 ShellPrintEx (-1, -1,
4398 L
" Correctable Error Reporting Enable(0): %E%d%N\r\n",
4399 PciExpressCap
->DeviceControl
.Bits
.CorrectableError
4401 ShellPrintEx (-1, -1,
4402 L
" Non-Fatal Error Reporting Enable(1): %E%d%N\r\n",
4403 PciExpressCap
->DeviceControl
.Bits
.NonFatalError
4405 ShellPrintEx (-1, -1,
4406 L
" Fatal Error Reporting Enable(2): %E%d%N\r\n",
4407 PciExpressCap
->DeviceControl
.Bits
.FatalError
4409 ShellPrintEx (-1, -1,
4410 L
" Unsupported Request Reporting Enable(3): %E%d%N\r\n",
4411 PciExpressCap
->DeviceControl
.Bits
.UnsupportedRequest
4413 ShellPrintEx (-1, -1,
4414 L
" Enable Relaxed Ordering(4): %E%d%N\r\n",
4415 PciExpressCap
->DeviceControl
.Bits
.RelaxedOrdering
4417 ShellPrintEx (-1, -1, L
" Max_Payload_Size(7:5): ");
4418 if (PciExpressCap
->DeviceControl
.Bits
.MaxPayloadSize
< 6) {
4419 ShellPrintEx (-1, -1, L
"%E%d bytes%N\r\n", 1 << (PciExpressCap
->DeviceControl
.Bits
.MaxPayloadSize
+ 7));
4421 ShellPrintEx (-1, -1, L
"%EUnknown%N\r\n");
4423 ShellPrintEx (-1, -1,
4424 L
" Extended Tag Field Enable(8): %E%d%N\r\n",
4425 PciExpressCap
->DeviceControl
.Bits
.ExtendedTagField
4427 ShellPrintEx (-1, -1,
4428 L
" Phantom Functions Enable(9): %E%d%N\r\n",
4429 PciExpressCap
->DeviceControl
.Bits
.PhantomFunctions
4431 ShellPrintEx (-1, -1,
4432 L
" Auxiliary (AUX) Power PM Enable(10): %E%d%N\r\n",
4433 PciExpressCap
->DeviceControl
.Bits
.AuxPower
4435 ShellPrintEx (-1, -1,
4436 L
" Enable No Snoop(11): %E%d%N\r\n",
4437 PciExpressCap
->DeviceControl
.Bits
.NoSnoop
4439 ShellPrintEx (-1, -1, L
" Max_Read_Request_Size(14:12): ");
4440 if (PciExpressCap
->DeviceControl
.Bits
.MaxReadRequestSize
< 6) {
4441 ShellPrintEx (-1, -1, L
"%E%d bytes%N\r\n", 1 << (PciExpressCap
->DeviceControl
.Bits
.MaxReadRequestSize
+ 7));
4443 ShellPrintEx (-1, -1, L
"%EUnknown%N\r\n");
4446 // Read operation is only valid for PCI Express to PCI/PCI-X Bridges
4448 if (PciExpressCap
->Capability
.Bits
.DevicePortType
== PCIE_DEVICE_PORT_TYPE_PCIE_TO_PCI_BRIDGE
) {
4449 ShellPrintEx (-1, -1,
4450 L
" Bridge Configuration Retry Enable(15): %E%d%N\r\n",
4451 PciExpressCap
->DeviceControl
.Bits
.BridgeConfigurationRetryOrFunctionLevelReset
4458 Print out information of the device status information.
4460 @param[in] PciExpressCap The pointer to the structure about the device.
4462 @retval EFI_SUCCESS The operation was successful.
4465 ExplainPcieDeviceStatus (
4466 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
4469 ShellPrintEx (-1, -1,
4470 L
" Correctable Error Detected(0): %E%d%N\r\n",
4471 PciExpressCap
->DeviceStatus
.Bits
.CorrectableError
4473 ShellPrintEx (-1, -1,
4474 L
" Non-Fatal Error Detected(1): %E%d%N\r\n",
4475 PciExpressCap
->DeviceStatus
.Bits
.NonFatalError
4477 ShellPrintEx (-1, -1,
4478 L
" Fatal Error Detected(2): %E%d%N\r\n",
4479 PciExpressCap
->DeviceStatus
.Bits
.FatalError
4481 ShellPrintEx (-1, -1,
4482 L
" Unsupported Request Detected(3): %E%d%N\r\n",
4483 PciExpressCap
->DeviceStatus
.Bits
.UnsupportedRequest
4485 ShellPrintEx (-1, -1,
4486 L
" AUX Power Detected(4): %E%d%N\r\n",
4487 PciExpressCap
->DeviceStatus
.Bits
.AuxPower
4489 ShellPrintEx (-1, -1,
4490 L
" Transactions Pending(5): %E%d%N\r\n",
4491 PciExpressCap
->DeviceStatus
.Bits
.TransactionsPending
4497 Print out information of the device link information.
4499 @param[in] PciExpressCap The pointer to the structure about the device.
4501 @retval EFI_SUCCESS The operation was successful.
4504 ExplainPcieLinkCap (
4505 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
4508 CHAR16
*MaxLinkSpeed
;
4511 switch (PciExpressCap
->LinkCapability
.Bits
.MaxLinkSpeed
) {
4513 MaxLinkSpeed
= L
"2.5 GT/s";
4516 MaxLinkSpeed
= L
"5.0 GT/s";
4519 MaxLinkSpeed
= L
"8.0 GT/s";
4522 MaxLinkSpeed
= L
"16.0 GT/s";
4525 MaxLinkSpeed
= L
"32.0 GT/s";
4528 MaxLinkSpeed
= L
"Reserved";
4531 ShellPrintEx (-1, -1,
4532 L
" Maximum Link Speed(3:0): %E%s%N\r\n",
4535 ShellPrintEx (-1, -1,
4536 L
" Maximum Link Width(9:4): %Ex%d%N\r\n",
4537 PciExpressCap
->LinkCapability
.Bits
.MaxLinkWidth
4539 switch (PciExpressCap
->LinkCapability
.Bits
.Aspm
) {
4550 AspmValue
= L
"L0s and L1";
4553 AspmValue
= L
"Reserved";
4556 ShellPrintEx (-1, -1,
4557 L
" Active State Power Management Support(11:10): %E%s Supported%N\r\n",
4560 ShellPrintEx (-1, -1,
4561 L
" L0s Exit Latency(14:12): %E%s%N\r\n",
4562 L0sLatencyStrTable
[PciExpressCap
->LinkCapability
.Bits
.L0sExitLatency
]
4564 ShellPrintEx (-1, -1,
4565 L
" L1 Exit Latency(17:15): %E%s%N\r\n",
4566 L1LatencyStrTable
[PciExpressCap
->LinkCapability
.Bits
.L1ExitLatency
]
4568 ShellPrintEx (-1, -1,
4569 L
" Clock Power Management(18): %E%d%N\r\n",
4570 PciExpressCap
->LinkCapability
.Bits
.ClockPowerManagement
4572 ShellPrintEx (-1, -1,
4573 L
" Surprise Down Error Reporting Capable(19): %E%d%N\r\n",
4574 PciExpressCap
->LinkCapability
.Bits
.SurpriseDownError
4576 ShellPrintEx (-1, -1,
4577 L
" Data Link Layer Link Active Reporting Capable(20): %E%d%N\r\n",
4578 PciExpressCap
->LinkCapability
.Bits
.DataLinkLayerLinkActive
4580 ShellPrintEx (-1, -1,
4581 L
" Link Bandwidth Notification Capability(21): %E%d%N\r\n",
4582 PciExpressCap
->LinkCapability
.Bits
.LinkBandwidthNotification
4584 ShellPrintEx (-1, -1,
4585 L
" Port Number(31:24): %E0x%02x%N\r\n",
4586 PciExpressCap
->LinkCapability
.Bits
.PortNumber
4592 Print out information of the device link control information.
4594 @param[in] PciExpressCap The pointer to the structure about the device.
4596 @retval EFI_SUCCESS The operation was successful.
4599 ExplainPcieLinkControl (
4600 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
4603 UINT8 DevicePortType
;
4605 DevicePortType
= (UINT8
)PciExpressCap
->Capability
.Bits
.DevicePortType
;
4606 ShellPrintEx (-1, -1,
4607 L
" Active State Power Management Control(1:0): %E%s%N\r\n",
4608 ASPMCtrlStrTable
[PciExpressCap
->LinkControl
.Bits
.AspmControl
]
4611 // RCB is not applicable to switches
4613 if (!IS_PCIE_SWITCH(DevicePortType
)) {
4614 ShellPrintEx (-1, -1,
4615 L
" Read Completion Boundary (RCB)(3): %E%d byte%N\r\n",
4616 1 << (PciExpressCap
->LinkControl
.Bits
.ReadCompletionBoundary
+ 6)
4620 // Link Disable is reserved on
4622 // b) PCI Express to PCI/PCI-X bridges
4623 // c) Upstream Ports of Switches
4625 if (!IS_PCIE_ENDPOINT (DevicePortType
) &&
4626 DevicePortType
!= PCIE_DEVICE_PORT_TYPE_UPSTREAM_PORT
&&
4627 DevicePortType
!= PCIE_DEVICE_PORT_TYPE_PCIE_TO_PCI_BRIDGE
) {
4628 ShellPrintEx (-1, -1,
4629 L
" Link Disable(4): %E%d%N\r\n",
4630 PciExpressCap
->LinkControl
.Bits
.LinkDisable
4633 ShellPrintEx (-1, -1,
4634 L
" Common Clock Configuration(6): %E%d%N\r\n",
4635 PciExpressCap
->LinkControl
.Bits
.CommonClockConfiguration
4637 ShellPrintEx (-1, -1,
4638 L
" Extended Synch(7): %E%d%N\r\n",
4639 PciExpressCap
->LinkControl
.Bits
.ExtendedSynch
4641 ShellPrintEx (-1, -1,
4642 L
" Enable Clock Power Management(8): %E%d%N\r\n",
4643 PciExpressCap
->LinkControl
.Bits
.ClockPowerManagement
4645 ShellPrintEx (-1, -1,
4646 L
" Hardware Autonomous Width Disable(9): %E%d%N\r\n",
4647 PciExpressCap
->LinkControl
.Bits
.HardwareAutonomousWidthDisable
4649 ShellPrintEx (-1, -1,
4650 L
" Link Bandwidth Management Interrupt Enable(10): %E%d%N\r\n",
4651 PciExpressCap
->LinkControl
.Bits
.LinkBandwidthManagementInterrupt
4653 ShellPrintEx (-1, -1,
4654 L
" Link Autonomous Bandwidth Interrupt Enable(11): %E%d%N\r\n",
4655 PciExpressCap
->LinkControl
.Bits
.LinkAutonomousBandwidthInterrupt
4661 Print out information of the device link status information.
4663 @param[in] PciExpressCap The pointer to the structure about the device.
4665 @retval EFI_SUCCESS The operation was successful.
4668 ExplainPcieLinkStatus (
4669 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
4672 CHAR16
*CurLinkSpeed
;
4674 switch (PciExpressCap
->LinkStatus
.Bits
.CurrentLinkSpeed
) {
4676 CurLinkSpeed
= L
"2.5 GT/s";
4679 CurLinkSpeed
= L
"5.0 GT/s";
4682 CurLinkSpeed
= L
"8.0 GT/s";
4685 CurLinkSpeed
= L
"16.0 GT/s";
4688 CurLinkSpeed
= L
"32.0 GT/s";
4691 CurLinkSpeed
= L
"Reserved";
4694 ShellPrintEx (-1, -1,
4695 L
" Current Link Speed(3:0): %E%s%N\r\n",
4698 ShellPrintEx (-1, -1,
4699 L
" Negotiated Link Width(9:4): %Ex%d%N\r\n",
4700 PciExpressCap
->LinkStatus
.Bits
.NegotiatedLinkWidth
4702 ShellPrintEx (-1, -1,
4703 L
" Link Training(11): %E%d%N\r\n",
4704 PciExpressCap
->LinkStatus
.Bits
.LinkTraining
4706 ShellPrintEx (-1, -1,
4707 L
" Slot Clock Configuration(12): %E%d%N\r\n",
4708 PciExpressCap
->LinkStatus
.Bits
.SlotClockConfiguration
4710 ShellPrintEx (-1, -1,
4711 L
" Data Link Layer Link Active(13): %E%d%N\r\n",
4712 PciExpressCap
->LinkStatus
.Bits
.DataLinkLayerLinkActive
4714 ShellPrintEx (-1, -1,
4715 L
" Link Bandwidth Management Status(14): %E%d%N\r\n",
4716 PciExpressCap
->LinkStatus
.Bits
.LinkBandwidthManagement
4718 ShellPrintEx (-1, -1,
4719 L
" Link Autonomous Bandwidth Status(15): %E%d%N\r\n",
4720 PciExpressCap
->LinkStatus
.Bits
.LinkAutonomousBandwidth
4726 Print out information of the device slot information.
4728 @param[in] PciExpressCap The pointer to the structure about the device.
4730 @retval EFI_SUCCESS The operation was successful.
4733 ExplainPcieSlotCap (
4734 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
4737 ShellPrintEx (-1, -1,
4738 L
" Attention Button Present(0): %E%d%N\r\n",
4739 PciExpressCap
->SlotCapability
.Bits
.AttentionButton
4741 ShellPrintEx (-1, -1,
4742 L
" Power Controller Present(1): %E%d%N\r\n",
4743 PciExpressCap
->SlotCapability
.Bits
.PowerController
4745 ShellPrintEx (-1, -1,
4746 L
" MRL Sensor Present(2): %E%d%N\r\n",
4747 PciExpressCap
->SlotCapability
.Bits
.MrlSensor
4749 ShellPrintEx (-1, -1,
4750 L
" Attention Indicator Present(3): %E%d%N\r\n",
4751 PciExpressCap
->SlotCapability
.Bits
.AttentionIndicator
4753 ShellPrintEx (-1, -1,
4754 L
" Power Indicator Present(4): %E%d%N\r\n",
4755 PciExpressCap
->SlotCapability
.Bits
.PowerIndicator
4757 ShellPrintEx (-1, -1,
4758 L
" Hot-Plug Surprise(5): %E%d%N\r\n",
4759 PciExpressCap
->SlotCapability
.Bits
.HotPlugSurprise
4761 ShellPrintEx (-1, -1,
4762 L
" Hot-Plug Capable(6): %E%d%N\r\n",
4763 PciExpressCap
->SlotCapability
.Bits
.HotPlugCapable
4765 ShellPrintEx (-1, -1,
4766 L
" Slot Power Limit Value(14:7): %E0x%02x%N\r\n",
4767 PciExpressCap
->SlotCapability
.Bits
.SlotPowerLimitValue
4769 ShellPrintEx (-1, -1,
4770 L
" Slot Power Limit Scale(16:15): %E%s%N\r\n",
4771 SlotPwrLmtScaleTable
[PciExpressCap
->SlotCapability
.Bits
.SlotPowerLimitScale
]
4773 ShellPrintEx (-1, -1,
4774 L
" Electromechanical Interlock Present(17): %E%d%N\r\n",
4775 PciExpressCap
->SlotCapability
.Bits
.ElectromechanicalInterlock
4777 ShellPrintEx (-1, -1,
4778 L
" No Command Completed Support(18): %E%d%N\r\n",
4779 PciExpressCap
->SlotCapability
.Bits
.NoCommandCompleted
4781 ShellPrintEx (-1, -1,
4782 L
" Physical Slot Number(31:19): %E%d%N\r\n",
4783 PciExpressCap
->SlotCapability
.Bits
.PhysicalSlotNumber
4790 Print out information of the device slot control information.
4792 @param[in] PciExpressCap The pointer to the structure about the device.
4794 @retval EFI_SUCCESS The operation was successful.
4797 ExplainPcieSlotControl (
4798 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
4801 ShellPrintEx (-1, -1,
4802 L
" Attention Button Pressed Enable(0): %E%d%N\r\n",
4803 PciExpressCap
->SlotControl
.Bits
.AttentionButtonPressed
4805 ShellPrintEx (-1, -1,
4806 L
" Power Fault Detected Enable(1): %E%d%N\r\n",
4807 PciExpressCap
->SlotControl
.Bits
.PowerFaultDetected
4809 ShellPrintEx (-1, -1,
4810 L
" MRL Sensor Changed Enable(2): %E%d%N\r\n",
4811 PciExpressCap
->SlotControl
.Bits
.MrlSensorChanged
4813 ShellPrintEx (-1, -1,
4814 L
" Presence Detect Changed Enable(3): %E%d%N\r\n",
4815 PciExpressCap
->SlotControl
.Bits
.PresenceDetectChanged
4817 ShellPrintEx (-1, -1,
4818 L
" Command Completed Interrupt Enable(4): %E%d%N\r\n",
4819 PciExpressCap
->SlotControl
.Bits
.CommandCompletedInterrupt
4821 ShellPrintEx (-1, -1,
4822 L
" Hot-Plug Interrupt Enable(5): %E%d%N\r\n",
4823 PciExpressCap
->SlotControl
.Bits
.HotPlugInterrupt
4825 ShellPrintEx (-1, -1,
4826 L
" Attention Indicator Control(7:6): %E%s%N\r\n",
4828 PciExpressCap
->SlotControl
.Bits
.AttentionIndicator
]
4830 ShellPrintEx (-1, -1,
4831 L
" Power Indicator Control(9:8): %E%s%N\r\n",
4832 IndicatorTable
[PciExpressCap
->SlotControl
.Bits
.PowerIndicator
]
4834 ShellPrintEx (-1, -1, L
" Power Controller Control(10): %EPower ");
4836 PciExpressCap
->SlotControl
.Bits
.PowerController
) {
4837 ShellPrintEx (-1, -1, L
"Off%N\r\n");
4839 ShellPrintEx (-1, -1, L
"On%N\r\n");
4841 ShellPrintEx (-1, -1,
4842 L
" Electromechanical Interlock Control(11): %E%d%N\r\n",
4843 PciExpressCap
->SlotControl
.Bits
.ElectromechanicalInterlock
4845 ShellPrintEx (-1, -1,
4846 L
" Data Link Layer State Changed Enable(12): %E%d%N\r\n",
4847 PciExpressCap
->SlotControl
.Bits
.DataLinkLayerStateChanged
4853 Print out information of the device slot status information.
4855 @param[in] PciExpressCap The pointer to the structure about the device.
4857 @retval EFI_SUCCESS The operation was successful.
4860 ExplainPcieSlotStatus (
4861 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
4864 ShellPrintEx (-1, -1,
4865 L
" Attention Button Pressed(0): %E%d%N\r\n",
4866 PciExpressCap
->SlotStatus
.Bits
.AttentionButtonPressed
4868 ShellPrintEx (-1, -1,
4869 L
" Power Fault Detected(1): %E%d%N\r\n",
4870 PciExpressCap
->SlotStatus
.Bits
.PowerFaultDetected
4872 ShellPrintEx (-1, -1,
4873 L
" MRL Sensor Changed(2): %E%d%N\r\n",
4874 PciExpressCap
->SlotStatus
.Bits
.MrlSensorChanged
4876 ShellPrintEx (-1, -1,
4877 L
" Presence Detect Changed(3): %E%d%N\r\n",
4878 PciExpressCap
->SlotStatus
.Bits
.PresenceDetectChanged
4880 ShellPrintEx (-1, -1,
4881 L
" Command Completed(4): %E%d%N\r\n",
4882 PciExpressCap
->SlotStatus
.Bits
.CommandCompleted
4884 ShellPrintEx (-1, -1, L
" MRL Sensor State(5): %EMRL ");
4886 PciExpressCap
->SlotStatus
.Bits
.MrlSensor
) {
4887 ShellPrintEx (-1, -1, L
" Opened%N\r\n");
4889 ShellPrintEx (-1, -1, L
" Closed%N\r\n");
4891 ShellPrintEx (-1, -1, L
" Presence Detect State(6): ");
4893 PciExpressCap
->SlotStatus
.Bits
.PresenceDetect
) {
4894 ShellPrintEx (-1, -1, L
"%ECard Present in slot%N\r\n");
4896 ShellPrintEx (-1, -1, L
"%ESlot Empty%N\r\n");
4898 ShellPrintEx (-1, -1, L
" Electromechanical Interlock Status(7): %EElectromechanical Interlock ");
4900 PciExpressCap
->SlotStatus
.Bits
.ElectromechanicalInterlock
) {
4901 ShellPrintEx (-1, -1, L
"Engaged%N\r\n");
4903 ShellPrintEx (-1, -1, L
"Disengaged%N\r\n");
4905 ShellPrintEx (-1, -1,
4906 L
" Data Link Layer State Changed(8): %E%d%N\r\n",
4907 PciExpressCap
->SlotStatus
.Bits
.DataLinkLayerStateChanged
4913 Print out information of the device root information.
4915 @param[in] PciExpressCap The pointer to the structure about the device.
4917 @retval EFI_SUCCESS The operation was successful.
4920 ExplainPcieRootControl (
4921 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
4924 ShellPrintEx (-1, -1,
4925 L
" System Error on Correctable Error Enable(0): %E%d%N\r\n",
4926 PciExpressCap
->RootControl
.Bits
.SystemErrorOnCorrectableError
4928 ShellPrintEx (-1, -1,
4929 L
" System Error on Non-Fatal Error Enable(1): %E%d%N\r\n",
4930 PciExpressCap
->RootControl
.Bits
.SystemErrorOnNonFatalError
4932 ShellPrintEx (-1, -1,
4933 L
" System Error on Fatal Error Enable(2): %E%d%N\r\n",
4934 PciExpressCap
->RootControl
.Bits
.SystemErrorOnFatalError
4936 ShellPrintEx (-1, -1,
4937 L
" PME Interrupt Enable(3): %E%d%N\r\n",
4938 PciExpressCap
->RootControl
.Bits
.PmeInterrupt
4940 ShellPrintEx (-1, -1,
4941 L
" CRS Software Visibility Enable(4): %E%d%N\r\n",
4942 PciExpressCap
->RootControl
.Bits
.CrsSoftwareVisibility
4949 Print out information of the device root capability information.
4951 @param[in] PciExpressCap The pointer to the structure about the device.
4953 @retval EFI_SUCCESS The operation was successful.
4956 ExplainPcieRootCap (
4957 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
4960 ShellPrintEx (-1, -1,
4961 L
" CRS Software Visibility(0): %E%d%N\r\n",
4962 PciExpressCap
->RootCapability
.Bits
.CrsSoftwareVisibility
4969 Print out information of the device root status information.
4971 @param[in] PciExpressCap The pointer to the structure about the device.
4973 @retval EFI_SUCCESS The operation was successful.
4976 ExplainPcieRootStatus (
4977 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
4980 ShellPrintEx (-1, -1,
4981 L
" PME Requester ID(15:0): %E0x%04x%N\r\n",
4982 PciExpressCap
->RootStatus
.Bits
.PmeRequesterId
4984 ShellPrintEx (-1, -1,
4985 L
" PME Status(16): %E%d%N\r\n",
4986 PciExpressCap
->RootStatus
.Bits
.PmeStatus
4988 ShellPrintEx (-1, -1,
4989 L
" PME Pending(17): %E%d%N\r\n",
4990 PciExpressCap
->RootStatus
.Bits
.PmePending
4996 Function to interpret and print out the link control structure
4998 @param[in] HeaderAddress The Address of this capability header.
4999 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5002 PrintInterpretedExtendedCompatibilityLinkControl (
5003 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5004 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
5007 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_INTERNAL_LINK_CONTROL
*Header
;
5008 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_INTERNAL_LINK_CONTROL
*)HeaderAddress
;
5012 STRING_TOKEN (STR_PCI_EXT_CAP_LINK_CONTROL
),
5013 gShellDebug1HiiHandle
,
5014 Header
->RootComplexLinkCapabilities
,
5015 Header
->RootComplexLinkControl
,
5016 Header
->RootComplexLinkStatus
5020 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5021 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_INTERNAL_LINK_CONTROL
),
5022 (VOID
*) (HeaderAddress
)
5024 return (EFI_SUCCESS
);
5028 Function to interpret and print out the power budgeting structure
5030 @param[in] HeaderAddress The Address of this capability header.
5031 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5034 PrintInterpretedExtendedCompatibilityPowerBudgeting (
5035 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5036 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
5039 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_POWER_BUDGETING
*Header
;
5040 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_POWER_BUDGETING
*)HeaderAddress
;
5044 STRING_TOKEN (STR_PCI_EXT_CAP_POWER
),
5045 gShellDebug1HiiHandle
,
5048 Header
->PowerBudgetCapability
5052 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5053 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_POWER_BUDGETING
),
5054 (VOID
*) (HeaderAddress
)
5056 return (EFI_SUCCESS
);
5060 Function to interpret and print out the ACS structure
5062 @param[in] HeaderAddress The Address of this capability header.
5063 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5066 PrintInterpretedExtendedCompatibilityAcs (
5067 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5068 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
5071 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_ACS_EXTENDED
*Header
;
5075 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_ACS_EXTENDED
*)HeaderAddress
;
5080 STRING_TOKEN (STR_PCI_EXT_CAP_ACS
),
5081 gShellDebug1HiiHandle
,
5082 Header
->AcsCapability
,
5085 if (PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_GET_EGRES_CONTROL(Header
)) {
5086 VectorSize
= PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_GET_EGRES_VECTOR_SIZE(Header
);
5087 if (VectorSize
== 0) {
5090 for (LoopCounter
= 0 ; LoopCounter
* 8 < VectorSize
; LoopCounter
++) {
5093 STRING_TOKEN (STR_PCI_EXT_CAP_ACS2
),
5094 gShellDebug1HiiHandle
,
5096 Header
->EgressControlVectorArray
[LoopCounter
]
5102 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5103 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_ACS_EXTENDED
) + (VectorSize
/ 8) - 1,
5104 (VOID
*) (HeaderAddress
)
5106 return (EFI_SUCCESS
);
5110 Function to interpret and print out the latency tolerance reporting structure
5112 @param[in] HeaderAddress The Address of this capability header.
5113 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5116 PrintInterpretedExtendedCompatibilityLatencyToleranceReporting (
5117 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5118 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
5121 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_LATENCE_TOLERANCE_REPORTING
*Header
;
5122 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_LATENCE_TOLERANCE_REPORTING
*)HeaderAddress
;
5126 STRING_TOKEN (STR_PCI_EXT_CAP_LAT
),
5127 gShellDebug1HiiHandle
,
5128 Header
->MaxSnoopLatency
,
5129 Header
->MaxNoSnoopLatency
5133 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5134 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_LATENCE_TOLERANCE_REPORTING
),
5135 (VOID
*) (HeaderAddress
)
5137 return (EFI_SUCCESS
);
5141 Function to interpret and print out the serial number structure
5143 @param[in] HeaderAddress The Address of this capability header.
5144 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5147 PrintInterpretedExtendedCompatibilitySerialNumber (
5148 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5149 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
5152 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_SERIAL_NUMBER
*Header
;
5153 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_SERIAL_NUMBER
*)HeaderAddress
;
5157 STRING_TOKEN (STR_PCI_EXT_CAP_SN
),
5158 gShellDebug1HiiHandle
,
5159 Header
->SerialNumber
5163 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5164 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_SERIAL_NUMBER
),
5165 (VOID
*) (HeaderAddress
)
5167 return (EFI_SUCCESS
);
5171 Function to interpret and print out the RCRB structure
5173 @param[in] HeaderAddress The Address of this capability header.
5174 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5177 PrintInterpretedExtendedCompatibilityRcrb (
5178 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5179 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
5182 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_RCRB_HEADER
*Header
;
5183 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_RCRB_HEADER
*)HeaderAddress
;
5187 STRING_TOKEN (STR_PCI_EXT_CAP_RCRB
),
5188 gShellDebug1HiiHandle
,
5191 Header
->RcrbCapabilities
,
5196 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5197 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_RCRB_HEADER
),
5198 (VOID
*) (HeaderAddress
)
5200 return (EFI_SUCCESS
);
5204 Function to interpret and print out the vendor specific structure
5206 @param[in] HeaderAddress The Address of this capability header.
5207 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5210 PrintInterpretedExtendedCompatibilityVendorSpecific (
5211 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5212 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
5215 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_VENDOR_SPECIFIC
*Header
;
5216 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_VENDOR_SPECIFIC
*)HeaderAddress
;
5220 STRING_TOKEN (STR_PCI_EXT_CAP_VEN
),
5221 gShellDebug1HiiHandle
,
5222 Header
->VendorSpecificHeader
5226 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5227 PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_GET_SIZE(Header
),
5228 (VOID
*) (HeaderAddress
)
5230 return (EFI_SUCCESS
);
5234 Function to interpret and print out the Event Collector Endpoint Association structure
5236 @param[in] HeaderAddress The Address of this capability header.
5237 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5240 PrintInterpretedExtendedCompatibilityECEA (
5241 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5242 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
5245 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION
*Header
;
5246 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION
*)HeaderAddress
;
5250 STRING_TOKEN (STR_PCI_EXT_CAP_ECEA
),
5251 gShellDebug1HiiHandle
,
5252 Header
->AssociationBitmap
5256 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5257 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION
),
5258 (VOID
*) (HeaderAddress
)
5260 return (EFI_SUCCESS
);
5264 Function to interpret and print out the ARI structure
5266 @param[in] HeaderAddress The Address of this capability header.
5267 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5270 PrintInterpretedExtendedCompatibilityAri (
5271 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5272 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
5275 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_ARI_CAPABILITY
*Header
;
5276 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_ARI_CAPABILITY
*)HeaderAddress
;
5280 STRING_TOKEN (STR_PCI_EXT_CAP_ARI
),
5281 gShellDebug1HiiHandle
,
5282 Header
->AriCapability
,
5287 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5288 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_ARI_CAPABILITY
),
5289 (VOID
*) (HeaderAddress
)
5291 return (EFI_SUCCESS
);
5295 Function to interpret and print out the DPA structure
5297 @param[in] HeaderAddress The Address of this capability header.
5298 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5301 PrintInterpretedExtendedCompatibilityDynamicPowerAllocation (
5302 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5303 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
5306 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_DYNAMIC_POWER_ALLOCATION
*Header
;
5308 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_DYNAMIC_POWER_ALLOCATION
*)HeaderAddress
;
5312 STRING_TOKEN (STR_PCI_EXT_CAP_DPA
),
5313 gShellDebug1HiiHandle
,
5314 Header
->DpaCapability
,
5315 Header
->DpaLatencyIndicator
,
5319 for (LinkCount
= 0 ; LinkCount
< PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_GET_SUBSTATE_MAX(Header
) + 1 ; LinkCount
++) {
5322 STRING_TOKEN (STR_PCI_EXT_CAP_DPA2
),
5323 gShellDebug1HiiHandle
,
5325 Header
->DpaPowerAllocationArray
[LinkCount
]
5330 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5331 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_DYNAMIC_POWER_ALLOCATION
) - 1 + PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_GET_SUBSTATE_MAX(Header
),
5332 (VOID
*) (HeaderAddress
)
5334 return (EFI_SUCCESS
);
5338 Function to interpret and print out the link declaration structure
5340 @param[in] HeaderAddress The Address of this capability header.
5341 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5344 PrintInterpretedExtendedCompatibilityLinkDeclaration (
5345 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5346 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
5349 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_LINK_DECLARATION
*Header
;
5351 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_LINK_DECLARATION
*)HeaderAddress
;
5355 STRING_TOKEN (STR_PCI_EXT_CAP_LINK_DECLAR
),
5356 gShellDebug1HiiHandle
,
5357 Header
->ElementSelfDescription
5360 for (LinkCount
= 0 ; LinkCount
< PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_GET_LINK_COUNT(Header
) ; LinkCount
++) {
5363 STRING_TOKEN (STR_PCI_EXT_CAP_LINK_DECLAR2
),
5364 gShellDebug1HiiHandle
,
5366 Header
->LinkEntry
[LinkCount
]
5371 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5372 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_LINK_DECLARATION
) + (PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_GET_LINK_COUNT(Header
)-1)*sizeof(UINT32
),
5373 (VOID
*) (HeaderAddress
)
5375 return (EFI_SUCCESS
);
5379 Function to interpret and print out the Advanced Error Reporting structure
5381 @param[in] HeaderAddress The Address of this capability header.
5382 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5385 PrintInterpretedExtendedCompatibilityAer (
5386 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5387 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
5390 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_ADVANCED_ERROR_REPORTING
*Header
;
5391 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_ADVANCED_ERROR_REPORTING
*)HeaderAddress
;
5395 STRING_TOKEN (STR_PCI_EXT_CAP_AER
),
5396 gShellDebug1HiiHandle
,
5397 Header
->UncorrectableErrorStatus
,
5398 Header
->UncorrectableErrorMask
,
5399 Header
->UncorrectableErrorSeverity
,
5400 Header
->CorrectableErrorStatus
,
5401 Header
->CorrectableErrorMask
,
5402 Header
->AdvancedErrorCapabilitiesAndControl
,
5403 Header
->HeaderLog
[0],
5404 Header
->HeaderLog
[1],
5405 Header
->HeaderLog
[2],
5406 Header
->HeaderLog
[3],
5407 Header
->RootErrorCommand
,
5408 Header
->RootErrorStatus
,
5409 Header
->ErrorSourceIdentification
,
5410 Header
->CorrectableErrorSourceIdentification
,
5411 Header
->TlpPrefixLog
[0],
5412 Header
->TlpPrefixLog
[1],
5413 Header
->TlpPrefixLog
[2],
5414 Header
->TlpPrefixLog
[3]
5418 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5419 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_ADVANCED_ERROR_REPORTING
),
5420 (VOID
*) (HeaderAddress
)
5422 return (EFI_SUCCESS
);
5426 Function to interpret and print out the multicast structure
5428 @param[in] HeaderAddress The Address of this capability header.
5429 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5430 @param[in] PciExpressCapPtr The address of the PCIe capabilities structure.
5433 PrintInterpretedExtendedCompatibilityMulticast (
5434 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5435 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
,
5436 IN CONST PCI_CAPABILITY_PCIEXP
*PciExpressCapPtr
5439 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTICAST
*Header
;
5440 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTICAST
*)HeaderAddress
;
5444 STRING_TOKEN (STR_PCI_EXT_CAP_MULTICAST
),
5445 gShellDebug1HiiHandle
,
5446 Header
->MultiCastCapability
,
5447 Header
->MulticastControl
,
5448 Header
->McBaseAddress
,
5449 Header
->McReceiveAddress
,
5451 Header
->McBlockUntranslated
,
5452 Header
->McOverlayBar
5457 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5458 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTICAST
),
5459 (VOID
*) (HeaderAddress
)
5462 return (EFI_SUCCESS
);
5466 Function to interpret and print out the virtual channel and multi virtual channel structure
5468 @param[in] HeaderAddress The Address of this capability header.
5469 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5472 PrintInterpretedExtendedCompatibilityVirtualChannel (
5473 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5474 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
5477 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY
*Header
;
5478 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_VC
*CapabilityItem
;
5480 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY
*)HeaderAddress
;
5484 STRING_TOKEN (STR_PCI_EXT_CAP_VC_BASE
),
5485 gShellDebug1HiiHandle
,
5486 Header
->ExtendedVcCount
,
5487 Header
->PortVcCapability1
,
5488 Header
->PortVcCapability2
,
5489 Header
->VcArbTableOffset
,
5490 Header
->PortVcControl
,
5491 Header
->PortVcStatus
5493 for (ItemCount
= 0 ; ItemCount
< Header
->ExtendedVcCount
; ItemCount
++) {
5494 CapabilityItem
= &Header
->Capability
[ItemCount
];
5497 STRING_TOKEN (STR_PCI_EXT_CAP_VC_ITEM
),
5498 gShellDebug1HiiHandle
,
5500 CapabilityItem
->VcResourceCapability
,
5501 CapabilityItem
->PortArbTableOffset
,
5502 CapabilityItem
->VcResourceControl
,
5503 CapabilityItem
->VcResourceStatus
5509 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5510 sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY
)
5511 + Header
->ExtendedVcCount
* sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_VC
),
5512 (VOID
*) (HeaderAddress
)
5515 return (EFI_SUCCESS
);
5519 Function to interpret and print out the resizeable bar structure
5521 @param[in] HeaderAddress The Address of this capability header.
5522 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5525 PrintInterpretedExtendedCompatibilityResizeableBar (
5526 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5527 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
5530 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR
*Header
;
5532 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR
*)HeaderAddress
;
5534 for (ItemCount
= 0 ; ItemCount
< (UINT32
)GET_NUMBER_RESIZABLE_BARS(Header
) ; ItemCount
++) {
5537 STRING_TOKEN (STR_PCI_EXT_CAP_RESIZE_BAR
),
5538 gShellDebug1HiiHandle
,
5540 Header
->Capability
[ItemCount
].ResizableBarCapability
.Uint32
,
5541 Header
->Capability
[ItemCount
].ResizableBarControl
.Uint32
5547 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5548 (UINT32
)GET_NUMBER_RESIZABLE_BARS(Header
) * sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY
),
5549 (VOID
*) (HeaderAddress
)
5552 return (EFI_SUCCESS
);
5556 Function to interpret and print out the TPH structure
5558 @param[in] HeaderAddress The Address of this capability header.
5559 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5562 PrintInterpretedExtendedCompatibilityTph (
5563 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5564 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
5567 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH
*Header
;
5568 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH
*)HeaderAddress
;
5572 STRING_TOKEN (STR_PCI_EXT_CAP_TPH
),
5573 gShellDebug1HiiHandle
,
5574 Header
->TphRequesterCapability
,
5575 Header
->TphRequesterControl
5579 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)Header
->TphStTable
- (UINT8
*)HeadersBaseAddress
),
5580 GET_TPH_TABLE_SIZE(Header
),
5581 (VOID
*)Header
->TphStTable
5586 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5587 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH
) + GET_TPH_TABLE_SIZE(Header
) - sizeof(UINT16
),
5588 (VOID
*) (HeaderAddress
)
5591 return (EFI_SUCCESS
);
5595 Function to interpret and print out the secondary PCIe capability structure
5597 @param[in] HeaderAddress The Address of this capability header.
5598 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5599 @param[in] PciExpressCapPtr The address of the PCIe capabilities structure.
5602 PrintInterpretedExtendedCompatibilitySecondary (
5603 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5604 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
,
5605 IN CONST PCI_CAPABILITY_PCIEXP
*PciExpressCap
5608 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_SECONDARY_PCIE
*Header
;
5609 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_SECONDARY_PCIE
*)HeaderAddress
;
5613 STRING_TOKEN (STR_PCI_EXT_CAP_SECONDARY
),
5614 gShellDebug1HiiHandle
,
5615 Header
->LinkControl3
.Uint32
,
5616 Header
->LaneErrorStatus
5620 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)Header
->EqualizationControl
- (UINT8
*)HeadersBaseAddress
),
5621 PciExpressCap
->LinkCapability
.Bits
.MaxLinkWidth
* sizeof (PCI_EXPRESS_REG_LANE_EQUALIZATION_CONTROL
),
5622 (VOID
*)Header
->EqualizationControl
5627 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5628 sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_SECONDARY_PCIE
) - sizeof (Header
->EqualizationControl
)
5629 + PciExpressCap
->LinkCapability
.Bits
.MaxLinkWidth
* sizeof (PCI_EXPRESS_REG_LANE_EQUALIZATION_CONTROL
),
5630 (VOID
*) (HeaderAddress
)
5633 return (EFI_SUCCESS
);
5637 Display Pcie extended capability details
5639 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5640 @param[in] HeaderAddress The address of this capability header.
5641 @param[in] PciExpressCapPtr The address of the PCIe capabilities structure.
5644 PrintPciExtendedCapabilityDetails(
5645 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
,
5646 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5647 IN CONST PCI_CAPABILITY_PCIEXP
*PciExpressCapPtr
5650 switch (HeaderAddress
->CapabilityId
){
5651 case PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_ID
:
5652 return PrintInterpretedExtendedCompatibilityAer(HeaderAddress
, HeadersBaseAddress
);
5653 case PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_CONTROL_ID
:
5654 return PrintInterpretedExtendedCompatibilityLinkControl(HeaderAddress
, HeadersBaseAddress
);
5655 case PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_ID
:
5656 return PrintInterpretedExtendedCompatibilityLinkDeclaration(HeaderAddress
, HeadersBaseAddress
);
5657 case PCI_EXPRESS_EXTENDED_CAPABILITY_SERIAL_NUMBER_ID
:
5658 return PrintInterpretedExtendedCompatibilitySerialNumber(HeaderAddress
, HeadersBaseAddress
);
5659 case PCI_EXPRESS_EXTENDED_CAPABILITY_POWER_BUDGETING_ID
:
5660 return PrintInterpretedExtendedCompatibilityPowerBudgeting(HeaderAddress
, HeadersBaseAddress
);
5661 case PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_ID
:
5662 return PrintInterpretedExtendedCompatibilityAcs(HeaderAddress
, HeadersBaseAddress
);
5663 case PCI_EXPRESS_EXTENDED_CAPABILITY_LATENCE_TOLERANCE_REPORTING_ID
:
5664 return PrintInterpretedExtendedCompatibilityLatencyToleranceReporting(HeaderAddress
, HeadersBaseAddress
);
5665 case PCI_EXPRESS_EXTENDED_CAPABILITY_ARI_CAPABILITY_ID
:
5666 return PrintInterpretedExtendedCompatibilityAri(HeaderAddress
, HeadersBaseAddress
);
5667 case PCI_EXPRESS_EXTENDED_CAPABILITY_RCRB_HEADER_ID
:
5668 return PrintInterpretedExtendedCompatibilityRcrb(HeaderAddress
, HeadersBaseAddress
);
5669 case PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_ID
:
5670 return PrintInterpretedExtendedCompatibilityVendorSpecific(HeaderAddress
, HeadersBaseAddress
);
5671 case PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_ID
:
5672 return PrintInterpretedExtendedCompatibilityDynamicPowerAllocation(HeaderAddress
, HeadersBaseAddress
);
5673 case PCI_EXPRESS_EXTENDED_CAPABILITY_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION_ID
:
5674 return PrintInterpretedExtendedCompatibilityECEA(HeaderAddress
, HeadersBaseAddress
);
5675 case PCI_EXPRESS_EXTENDED_CAPABILITY_VIRTUAL_CHANNEL_ID
:
5676 case PCI_EXPRESS_EXTENDED_CAPABILITY_MULTI_FUNCTION_VIRTUAL_CHANNEL_ID
:
5677 return PrintInterpretedExtendedCompatibilityVirtualChannel(HeaderAddress
, HeadersBaseAddress
);
5678 case PCI_EXPRESS_EXTENDED_CAPABILITY_MULTICAST_ID
:
5680 // should only be present if PCIE_CAP_DEVICEPORT_TYPE(PciExpressCapPtr->PcieCapReg) == 0100b, 0101b, or 0110b
5682 return PrintInterpretedExtendedCompatibilityMulticast(HeaderAddress
, HeadersBaseAddress
, PciExpressCapPtr
);
5683 case PCI_EXPRESS_EXTENDED_CAPABILITY_RESIZABLE_BAR_ID
:
5684 return PrintInterpretedExtendedCompatibilityResizeableBar(HeaderAddress
, HeadersBaseAddress
);
5685 case PCI_EXPRESS_EXTENDED_CAPABILITY_TPH_ID
:
5686 return PrintInterpretedExtendedCompatibilityTph(HeaderAddress
, HeadersBaseAddress
);
5687 case PCI_EXPRESS_EXTENDED_CAPABILITY_SECONDARY_PCIE_ID
:
5688 return PrintInterpretedExtendedCompatibilitySecondary(HeaderAddress
, HeadersBaseAddress
, PciExpressCapPtr
);
5690 ShellPrintEx (-1, -1,
5691 L
"Unknown PCIe extended capability ID (%04xh). No interpretation available.\r\n",
5692 HeaderAddress
->CapabilityId
5700 Display Pcie device structure.
5702 @param[in] PciExpressCap PCI Express capability buffer.
5703 @param[in] ExtendedConfigSpace PCI Express extended configuration space.
5704 @param[in] ExtendedConfigSize PCI Express extended configuration size.
5705 @param[in] ExtendedCapability PCI Express extended capability ID to explain.
5708 PciExplainPciExpress (
5709 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
,
5710 IN UINT8
*ExtendedConfigSpace
,
5711 IN UINTN ExtendedConfigSize
,
5712 IN CONST UINT16 ExtendedCapability
5715 UINT8 DevicePortType
;
5719 PCI_EXP_EXT_HDR
*ExtHdr
;
5721 DevicePortType
= (UINT8
)PciExpressCap
->Capability
.Bits
.DevicePortType
;
5723 ShellPrintEx (-1, -1, L
"\r\nPci Express device capability structure:\r\n");
5725 for (Index
= 0; PcieExplainList
[Index
].Type
< PcieExplainTypeMax
; Index
++) {
5726 if (ShellGetExecutionBreakFlag()) {
5729 RegAddr
= (UINT8
*) PciExpressCap
+ PcieExplainList
[Index
].Offset
;
5730 switch (PcieExplainList
[Index
].Width
) {
5731 case FieldWidthUINT8
:
5732 RegValue
= *(UINT8
*) RegAddr
;
5734 case FieldWidthUINT16
:
5735 RegValue
= *(UINT16
*) RegAddr
;
5737 case FieldWidthUINT32
:
5738 RegValue
= *(UINT32
*) RegAddr
;
5744 ShellPrintHiiEx(-1, -1, NULL
,
5745 PcieExplainList
[Index
].Token
,
5746 gShellDebug1HiiHandle
,
5747 PcieExplainList
[Index
].Offset
,
5750 if (PcieExplainList
[Index
].Func
== NULL
) {
5753 switch (PcieExplainList
[Index
].Type
) {
5754 case PcieExplainTypeLink
:
5756 // Link registers should not be used by
5757 // a) Root Complex Integrated Endpoint
5758 // b) Root Complex Event Collector
5760 if (DevicePortType
== PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX_INTEGRATED_ENDPOINT
||
5761 DevicePortType
== PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX_EVENT_COLLECTOR
) {
5765 case PcieExplainTypeSlot
:
5767 // Slot registers are only valid for
5768 // a) Root Port of PCI Express Root Complex
5769 // b) Downstream Port of PCI Express Switch
5770 // and when SlotImplemented bit is set in PCIE cap register.
5772 if ((DevicePortType
!= PCIE_DEVICE_PORT_TYPE_ROOT_PORT
&&
5773 DevicePortType
!= PCIE_DEVICE_PORT_TYPE_DOWNSTREAM_PORT
) ||
5774 !PciExpressCap
->Capability
.Bits
.SlotImplemented
) {
5778 case PcieExplainTypeRoot
:
5780 // Root registers are only valid for
5781 // Root Port of PCI Express Root Complex
5783 if (DevicePortType
!= PCIE_DEVICE_PORT_TYPE_ROOT_PORT
) {
5790 PcieExplainList
[Index
].Func (PciExpressCap
);
5793 ExtHdr
= (PCI_EXP_EXT_HDR
*)ExtendedConfigSpace
;
5794 while (ExtHdr
->CapabilityId
!= 0 && ExtHdr
->CapabilityVersion
!= 0 && ExtHdr
->CapabilityId
!= 0xFFFF) {
5796 // Process this item
5798 if (ExtendedCapability
== 0xFFFF || ExtendedCapability
== ExtHdr
->CapabilityId
) {
5802 PrintPciExtendedCapabilityDetails((PCI_EXP_EXT_HDR
*)ExtendedConfigSpace
, ExtHdr
, PciExpressCap
);
5806 // Advance to the next item if it exists
5808 if (ExtHdr
->NextCapabilityOffset
!= 0 &&
5809 (ExtHdr
->NextCapabilityOffset
<= (UINT32
) (ExtendedConfigSize
+ EFI_PCIE_CAPABILITY_BASE_OFFSET
- sizeof (PCI_EXP_EXT_HDR
)))) {
5810 ExtHdr
= (PCI_EXP_EXT_HDR
*)(ExtendedConfigSpace
+ ExtHdr
->NextCapabilityOffset
- EFI_PCIE_CAPABILITY_BASE_OFFSET
);