2 Main file for Pci shell Debug1 function.
4 Copyright (c) 2005 - 2016, Intel Corporation. All rights reserved.<BR>
5 (C) Copyright 2013-2015 Hewlett-Packard Development Company, L.P.<BR>
6 (C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>
7 This program and the accompanying materials
8 are licensed and made available under the terms and conditions of the BSD License
9 which accompanies this distribution. The full text of the license may be found at
10 http://opensource.org/licenses/bsd-license.php
12 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
13 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
17 #include "UefiShellDebug1CommandsLib.h"
18 #include <Protocol/PciRootBridgeIo.h>
19 #include <Library/ShellLib.h>
20 #include <IndustryStandard/Pci.h>
21 #include <IndustryStandard/Acpi.h>
25 // Printable strings for Pci class code
28 CHAR16
*BaseClass
; // Pointer to the PCI base class string
29 CHAR16
*SubClass
; // Pointer to the PCI sub class string
30 CHAR16
*PIFClass
; // Pointer to the PCI programming interface string
34 // a structure holding a single entry, which also points to its lower level
37 typedef struct PCI_CLASS_ENTRY_TAG
{
38 UINT8 Code
; // Class, subclass or I/F code
39 CHAR16
*DescText
; // Description string
40 struct PCI_CLASS_ENTRY_TAG
*LowerLevelClass
; // Subclass or I/F if any
44 // Declarations of entries which contain printable strings for class codes
45 // in PCI configuration space
47 PCI_CLASS_ENTRY PCIBlankEntry
[];
48 PCI_CLASS_ENTRY PCISubClass_00
[];
49 PCI_CLASS_ENTRY PCISubClass_01
[];
50 PCI_CLASS_ENTRY PCISubClass_02
[];
51 PCI_CLASS_ENTRY PCISubClass_03
[];
52 PCI_CLASS_ENTRY PCISubClass_04
[];
53 PCI_CLASS_ENTRY PCISubClass_05
[];
54 PCI_CLASS_ENTRY PCISubClass_06
[];
55 PCI_CLASS_ENTRY PCISubClass_07
[];
56 PCI_CLASS_ENTRY PCISubClass_08
[];
57 PCI_CLASS_ENTRY PCISubClass_09
[];
58 PCI_CLASS_ENTRY PCISubClass_0a
[];
59 PCI_CLASS_ENTRY PCISubClass_0b
[];
60 PCI_CLASS_ENTRY PCISubClass_0c
[];
61 PCI_CLASS_ENTRY PCISubClass_0d
[];
62 PCI_CLASS_ENTRY PCISubClass_0e
[];
63 PCI_CLASS_ENTRY PCISubClass_0f
[];
64 PCI_CLASS_ENTRY PCISubClass_10
[];
65 PCI_CLASS_ENTRY PCISubClass_11
[];
66 PCI_CLASS_ENTRY PCISubClass_12
[];
67 PCI_CLASS_ENTRY PCISubClass_13
[];
68 PCI_CLASS_ENTRY PCIPIFClass_0100
[];
69 PCI_CLASS_ENTRY PCIPIFClass_0101
[];
70 PCI_CLASS_ENTRY PCIPIFClass_0105
[];
71 PCI_CLASS_ENTRY PCIPIFClass_0106
[];
72 PCI_CLASS_ENTRY PCIPIFClass_0107
[];
73 PCI_CLASS_ENTRY PCIPIFClass_0108
[];
74 PCI_CLASS_ENTRY PCIPIFClass_0109
[];
75 PCI_CLASS_ENTRY PCIPIFClass_0300
[];
76 PCI_CLASS_ENTRY PCIPIFClass_0604
[];
77 PCI_CLASS_ENTRY PCIPIFClass_0609
[];
78 PCI_CLASS_ENTRY PCIPIFClass_060b
[];
79 PCI_CLASS_ENTRY PCIPIFClass_0700
[];
80 PCI_CLASS_ENTRY PCIPIFClass_0701
[];
81 PCI_CLASS_ENTRY PCIPIFClass_0703
[];
82 PCI_CLASS_ENTRY PCIPIFClass_0800
[];
83 PCI_CLASS_ENTRY PCIPIFClass_0801
[];
84 PCI_CLASS_ENTRY PCIPIFClass_0802
[];
85 PCI_CLASS_ENTRY PCIPIFClass_0803
[];
86 PCI_CLASS_ENTRY PCIPIFClass_0904
[];
87 PCI_CLASS_ENTRY PCIPIFClass_0c00
[];
88 PCI_CLASS_ENTRY PCIPIFClass_0c03
[];
89 PCI_CLASS_ENTRY PCIPIFClass_0c07
[];
90 PCI_CLASS_ENTRY PCIPIFClass_0d01
[];
91 PCI_CLASS_ENTRY PCIPIFClass_0e00
[];
94 // Base class strings entries
96 PCI_CLASS_ENTRY gClassStringList
[] = {
104 L
"Mass Storage Controller",
109 L
"Network Controller",
114 L
"Display Controller",
119 L
"Multimedia Device",
124 L
"Memory Controller",
134 L
"Simple Communications Controllers",
139 L
"Base System Peripherals",
159 L
"Serial Bus Controllers",
164 L
"Wireless Controllers",
169 L
"Intelligent IO Controllers",
174 L
"Satellite Communications Controllers",
179 L
"Encryption/Decryption Controllers",
184 L
"Data Acquisition & Signal Processing Controllers",
189 L
"Processing Accelerators",
194 L
"Non-Essential Instrumentation",
199 L
"Device does not fit in any defined classes",
205 /* null string ends the list */NULL
210 // Subclass strings entries
212 PCI_CLASS_ENTRY PCIBlankEntry
[] = {
221 /* null string ends the list */NULL
225 PCI_CLASS_ENTRY PCISubClass_00
[] = {
228 L
"All devices other than VGA",
233 L
"VGA-compatible devices",
239 /* null string ends the list */NULL
243 PCI_CLASS_ENTRY PCISubClass_01
[] = {
256 L
"Floppy disk controller",
271 L
"ATA controller with ADMA interface",
276 L
"Serial ATA controller",
281 L
"Serial Attached SCSI (SAS) controller ",
286 L
"Non-volatile memory subsystem",
291 L
"Universal Flash Storage (UFS) controller ",
296 L
"Other mass storage controller",
302 /* null string ends the list */NULL
306 PCI_CLASS_ENTRY PCISubClass_02
[] = {
309 L
"Ethernet controller",
314 L
"Token ring controller",
334 L
"WorldFip controller",
339 L
"PICMG 2.14 Multi Computing",
344 L
"InfiniBand controller",
349 L
"Other network controller",
355 /* null string ends the list */NULL
359 PCI_CLASS_ENTRY PCISubClass_03
[] = {
362 L
"VGA/8514 controller",
377 L
"Other display controller",
383 /* null string ends the list */PCIBlankEntry
387 PCI_CLASS_ENTRY PCISubClass_04
[] = {
400 L
"Computer Telephony device",
405 L
"Mixed mode device",
410 L
"Other multimedia device",
416 /* null string ends the list */NULL
420 PCI_CLASS_ENTRY PCISubClass_05
[] = {
423 L
"RAM memory controller",
428 L
"Flash memory controller",
433 L
"Other memory controller",
439 /* null string ends the list */NULL
443 PCI_CLASS_ENTRY PCISubClass_06
[] = {
461 L
"PCI/Micro Channel bridge",
471 L
"PCI/PCMCIA bridge",
491 L
"Semi-transparent PCI-to-PCI bridge",
496 L
"InfiniBand-to-PCI host bridge",
501 L
"Advanced Switching to PCI host bridge",
506 L
"Other bridge type",
512 /* null string ends the list */NULL
516 PCI_CLASS_ENTRY PCISubClass_07
[] = {
519 L
"Serial controller",
529 L
"Multiport serial controller",
539 L
"GPIB (IEEE 488.1/2) controller",
549 L
"Other communication device",
555 /* null string ends the list */NULL
559 PCI_CLASS_ENTRY PCISubClass_08
[] = {
582 L
"Generic PCI Hot-Plug controller",
587 L
"SD Host controller",
597 L
"Root Complex Event Collector",
602 L
"Other system peripheral",
608 /* null string ends the list */NULL
612 PCI_CLASS_ENTRY PCISubClass_09
[] = {
615 L
"Keyboard controller",
630 L
"Scanner controller",
635 L
"Gameport controller",
640 L
"Other input controller",
646 /* null string ends the list */NULL
650 PCI_CLASS_ENTRY PCISubClass_0a
[] = {
653 L
"Generic docking station",
658 L
"Other type of docking station",
664 /* null string ends the list */NULL
668 PCI_CLASS_ENTRY PCISubClass_0b
[] = {
712 /* null string ends the list */NULL
716 PCI_CLASS_ENTRY PCISubClass_0c
[] = {
744 L
"System Management Bus",
759 L
"SERCOS Interface Standard (IEC 61491)",
775 /* null string ends the list */NULL
779 PCI_CLASS_ENTRY PCISubClass_0d
[] = {
782 L
"iRDA compatible controller",
807 L
"Ethernet (802.11a - 5 GHz)",
812 L
"Ethernet (802.11b - 2.4 GHz)",
817 L
"Other type of wireless controller",
823 /* null string ends the list */NULL
827 PCI_CLASS_ENTRY PCISubClass_0e
[] = {
836 /* null string ends the list */NULL
840 PCI_CLASS_ENTRY PCISubClass_0f
[] = {
863 L
"Other satellite communication controller",
869 /* null string ends the list */NULL
873 PCI_CLASS_ENTRY PCISubClass_10
[] = {
876 L
"Network & computing Encrypt/Decrypt",
881 L
"Entertainment Encrypt/Decrypt",
886 L
"Other Encrypt/Decrypt",
892 /* null string ends the list */NULL
896 PCI_CLASS_ENTRY PCISubClass_11
[] = {
904 L
"Performance Counters",
909 L
"Communications synchronization plus time and frequency test/measurement ",
919 L
"Other DAQ & SP controllers",
925 /* null string ends the list */NULL
929 PCI_CLASS_ENTRY PCISubClass_12
[] = {
932 L
"Processing Accelerator",
938 /* null string ends the list */NULL
942 PCI_CLASS_ENTRY PCISubClass_13
[] = {
945 L
"Non-Essential Instrumentation Function",
951 /* null string ends the list */NULL
956 // Programming Interface entries
958 PCI_CLASS_ENTRY PCIPIFClass_0100
[] = {
966 L
"SCSI storage device SOP using PQI",
971 L
"SCSI controller SOP using PQI",
976 L
"SCSI storage device and controller SOP using PQI",
981 L
"SCSI storage device SOP using NVMe",
987 /* null string ends the list */NULL
991 PCI_CLASS_ENTRY PCIPIFClass_0101
[] = {
1019 L
"OM-primary, OM-secondary",
1024 L
"PI-primary, OM-secondary",
1029 L
"OM/PI-primary, OM-secondary",
1039 L
"OM-primary, PI-secondary",
1044 L
"PI-primary, PI-secondary",
1049 L
"OM/PI-primary, PI-secondary",
1059 L
"OM-primary, OM/PI-secondary",
1064 L
"PI-primary, OM/PI-secondary",
1069 L
"OM/PI-primary, OM/PI-secondary",
1079 L
"Master, OM-primary",
1084 L
"Master, PI-primary",
1089 L
"Master, OM/PI-primary",
1094 L
"Master, OM-secondary",
1099 L
"Master, OM-primary, OM-secondary",
1104 L
"Master, PI-primary, OM-secondary",
1109 L
"Master, OM/PI-primary, OM-secondary",
1114 L
"Master, OM-secondary",
1119 L
"Master, OM-primary, PI-secondary",
1124 L
"Master, PI-primary, PI-secondary",
1129 L
"Master, OM/PI-primary, PI-secondary",
1134 L
"Master, OM-secondary",
1139 L
"Master, OM-primary, OM/PI-secondary",
1144 L
"Master, PI-primary, OM/PI-secondary",
1149 L
"Master, OM/PI-primary, OM/PI-secondary",
1155 /* null string ends the list */NULL
1159 PCI_CLASS_ENTRY PCIPIFClass_0105
[] = {
1167 L
"Continuous operation",
1173 /* null string ends the list */NULL
1177 PCI_CLASS_ENTRY PCIPIFClass_0106
[] = {
1190 L
"Serial Storage Bus",
1196 /* null string ends the list */NULL
1200 PCI_CLASS_ENTRY PCIPIFClass_0107
[] = {
1214 /* null string ends the list */NULL
1218 PCI_CLASS_ENTRY PCIPIFClass_0108
[] = {
1237 /* null string ends the list */NULL
1241 PCI_CLASS_ENTRY PCIPIFClass_0109
[] = {
1255 /* null string ends the list */NULL
1259 PCI_CLASS_ENTRY PCIPIFClass_0300
[] = {
1273 /* null string ends the list */NULL
1277 PCI_CLASS_ENTRY PCIPIFClass_0604
[] = {
1285 L
"Subtractive decode",
1291 /* null string ends the list */NULL
1295 PCI_CLASS_ENTRY PCIPIFClass_0609
[] = {
1298 L
"Primary PCI bus side facing the system host processor",
1303 L
"Secondary PCI bus side facing the system host processor",
1309 /* null string ends the list */NULL
1313 PCI_CLASS_ENTRY PCIPIFClass_060b
[] = {
1321 L
"ASI-SIG Defined Portal",
1327 /* null string ends the list */NULL
1331 PCI_CLASS_ENTRY PCIPIFClass_0700
[] = {
1334 L
"Generic XT-compatible",
1339 L
"16450-compatible",
1344 L
"16550-compatible",
1349 L
"16650-compatible",
1354 L
"16750-compatible",
1359 L
"16850-compatible",
1364 L
"16950-compatible",
1370 /* null string ends the list */NULL
1374 PCI_CLASS_ENTRY PCIPIFClass_0701
[] = {
1387 L
"ECP 1.X-compliant",
1397 L
"IEEE 1284 target (not a controller)",
1403 /* null string ends the list */NULL
1407 PCI_CLASS_ENTRY PCIPIFClass_0703
[] = {
1415 L
"Hayes-compatible 16450",
1420 L
"Hayes-compatible 16550",
1425 L
"Hayes-compatible 16650",
1430 L
"Hayes-compatible 16750",
1436 /* null string ends the list */NULL
1440 PCI_CLASS_ENTRY PCIPIFClass_0800
[] = {
1463 L
"IO(x) APIC interrupt controller",
1469 /* null string ends the list */NULL
1473 PCI_CLASS_ENTRY PCIPIFClass_0801
[] = {
1492 /* null string ends the list */NULL
1496 PCI_CLASS_ENTRY PCIPIFClass_0802
[] = {
1515 /* null string ends the list */NULL
1519 PCI_CLASS_ENTRY PCIPIFClass_0803
[] = {
1538 /* null string ends the list */NULL
1542 PCI_CLASS_ENTRY PCIPIFClass_0904
[] = {
1556 /* null string ends the list */NULL
1560 PCI_CLASS_ENTRY PCIPIFClass_0c00
[] = {
1568 L
"Using 1394 OpenHCI spec",
1574 /* null string ends the list */NULL
1578 PCI_CLASS_ENTRY PCIPIFClass_0c03
[] = {
1601 L
"No specific programming interface",
1606 L
"(Not Host Controller)",
1612 /* null string ends the list */NULL
1616 PCI_CLASS_ENTRY PCIPIFClass_0c07
[] = {
1624 L
"Keyboard Controller Style",
1635 /* null string ends the list */NULL
1639 PCI_CLASS_ENTRY PCIPIFClass_0d01
[] = {
1642 L
"Consumer IR controller",
1647 L
"UWB Radio controller",
1653 /* null string ends the list */NULL
1657 PCI_CLASS_ENTRY PCIPIFClass_0e00
[] = {
1660 L
"Message FIFO at offset 40h",
1671 /* null string ends the list */NULL
1677 Generates printable Unicode strings that represent PCI device class,
1678 subclass and programmed I/F based on a value passed to the function.
1680 @param[in] ClassCode Value representing the PCI "Class Code" register read from a
1681 PCI device. The encodings are:
1682 bits 23:16 - Base Class Code
1683 bits 15:8 - Sub-Class Code
1684 bits 7:0 - Programming Interface
1685 @param[in, out] ClassStrings Pointer of PCI_CLASS_STRINGS structure, which contains
1686 printable class strings corresponding to ClassCode. The
1687 caller must not modify the strings that are pointed by
1688 the fields in ClassStrings.
1691 PciGetClassStrings (
1692 IN UINT32 ClassCode
,
1693 IN OUT PCI_CLASS_STRINGS
*ClassStrings
1698 PCI_CLASS_ENTRY
*CurrentClass
;
1701 // Assume no strings found
1703 ClassStrings
->BaseClass
= L
"UNDEFINED";
1704 ClassStrings
->SubClass
= L
"UNDEFINED";
1705 ClassStrings
->PIFClass
= L
"UNDEFINED";
1707 CurrentClass
= gClassStringList
;
1708 Code
= (UINT8
) (ClassCode
>> 16);
1712 // Go through all entries of the base class, until the entry with a matching
1713 // base class code is found. If reaches an entry with a null description
1714 // text, the last entry is met, which means no text for the base class was
1715 // found, so no more action is needed.
1717 while (Code
!= CurrentClass
[Index
].Code
) {
1718 if (NULL
== CurrentClass
[Index
].DescText
) {
1725 // A base class was found. Assign description, and check if this class has
1726 // sub-class defined. If sub-class defined, no more action is needed,
1727 // otherwise, continue to find description for the sub-class code.
1729 ClassStrings
->BaseClass
= CurrentClass
[Index
].DescText
;
1730 if (NULL
== CurrentClass
[Index
].LowerLevelClass
) {
1734 // find Subclass entry
1736 CurrentClass
= CurrentClass
[Index
].LowerLevelClass
;
1737 Code
= (UINT8
) (ClassCode
>> 8);
1741 // Go through all entries of the sub-class, until the entry with a matching
1742 // sub-class code is found. If reaches an entry with a null description
1743 // text, the last entry is met, which means no text for the sub-class was
1744 // found, so no more action is needed.
1746 while (Code
!= CurrentClass
[Index
].Code
) {
1747 if (NULL
== CurrentClass
[Index
].DescText
) {
1754 // A class was found for the sub-class code. Assign description, and check if
1755 // this sub-class has programming interface defined. If no, no more action is
1756 // needed, otherwise, continue to find description for the programming
1759 ClassStrings
->SubClass
= CurrentClass
[Index
].DescText
;
1760 if (NULL
== CurrentClass
[Index
].LowerLevelClass
) {
1764 // Find programming interface entry
1766 CurrentClass
= CurrentClass
[Index
].LowerLevelClass
;
1767 Code
= (UINT8
) ClassCode
;
1771 // Go through all entries of the I/F entries, until the entry with a
1772 // matching I/F code is found. If reaches an entry with a null description
1773 // text, the last entry is met, which means no text was found, so no more
1774 // action is needed.
1776 while (Code
!= CurrentClass
[Index
].Code
) {
1777 if (NULL
== CurrentClass
[Index
].DescText
) {
1784 // A class was found for the I/F code. Assign description, done!
1786 ClassStrings
->PIFClass
= CurrentClass
[Index
].DescText
;
1791 Print strings that represent PCI device class, subclass and programmed I/F.
1793 @param[in] ClassCodePtr Points to the memory which stores register Class Code in PCI
1794 configuration space.
1795 @param[in] IncludePIF If the printed string should include the programming I/F part
1799 IN UINT8
*ClassCodePtr
,
1800 IN BOOLEAN IncludePIF
1804 PCI_CLASS_STRINGS ClassStrings
;
1807 ClassCode
|= (UINT32
)ClassCodePtr
[0];
1808 ClassCode
|= (UINT32
)(ClassCodePtr
[1] << 8);
1809 ClassCode
|= (UINT32
)(ClassCodePtr
[2] << 16);
1812 // Get name from class code
1814 PciGetClassStrings (ClassCode
, &ClassStrings
);
1818 // Print base class, sub class, and programming inferface name
1820 ShellPrintEx (-1, -1, L
"%s - %s - %s",
1821 ClassStrings
.BaseClass
,
1822 ClassStrings
.SubClass
,
1823 ClassStrings
.PIFClass
1828 // Only print base class and sub class name
1830 ShellPrintEx (-1, -1, L
"%s - %s",
1831 ClassStrings
.BaseClass
,
1832 ClassStrings
.SubClass
1838 This function finds out the protocol which is in charge of the given
1839 segment, and its bus range covers the current bus number. It lookes
1840 each instances of RootBridgeIoProtocol handle, until the one meets the
1843 @param[in] HandleBuf Buffer which holds all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.
1844 @param[in] HandleCount Count of all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.
1845 @param[in] Segment Segment number of device we are dealing with.
1846 @param[in] Bus Bus number of device we are dealing with.
1847 @param[out] IoDev Handle used to access configuration space of PCI device.
1849 @retval EFI_SUCCESS The command completed successfully.
1850 @retval EFI_INVALID_PARAMETER Invalid parameter.
1854 PciFindProtocolInterface (
1855 IN EFI_HANDLE
*HandleBuf
,
1856 IN UINTN HandleCount
,
1859 OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
**IoDev
1863 This function gets the protocol interface from the given handle, and
1864 obtains its address space descriptors.
1866 @param[in] Handle The PCI_ROOT_BRIDIGE_IO_PROTOCOL handle.
1867 @param[out] IoDev Handle used to access configuration space of PCI device.
1868 @param[out] Descriptors Points to the address space descriptors.
1870 @retval EFI_SUCCESS The command completed successfully
1873 PciGetProtocolAndResource (
1874 IN EFI_HANDLE Handle
,
1875 OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
**IoDev
,
1876 OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
**Descriptors
1880 This function get the next bus range of given address space descriptors.
1881 It also moves the pointer backward a node, to get prepared to be called
1884 @param[in, out] Descriptors Points to current position of a serial of address space
1886 @param[out] MinBus The lower range of bus number.
1887 @param[out] MaxBus The upper range of bus number.
1888 @param[out] IsEnd Meet end of the serial of descriptors.
1890 @retval EFI_SUCCESS The command completed successfully.
1893 PciGetNextBusRange (
1894 IN OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
**Descriptors
,
1901 Explain the data in PCI configuration space. The part which is common for
1902 PCI device and bridge is interpreted in this function. It calls other
1903 functions to interpret data unique for device or bridge.
1905 @param[in] ConfigSpace Data in PCI configuration space.
1906 @param[in] Address Address used to access configuration space of this PCI device.
1907 @param[in] IoDev Handle used to access configuration space of PCI device.
1908 @param[in] EnhancedDump The print format for the dump data.
1910 @retval EFI_SUCCESS The command completed successfully.
1914 IN PCI_CONFIG_SPACE
*ConfigSpace
,
1916 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
,
1917 IN CONST UINT16 EnhancedDump
1921 Explain the device specific part of data in PCI configuration space.
1923 @param[in] Device Data in PCI configuration space.
1924 @param[in] Address Address used to access configuration space of this PCI device.
1925 @param[in] IoDev Handle used to access configuration space of PCI device.
1927 @retval EFI_SUCCESS The command completed successfully.
1930 PciExplainDeviceData (
1931 IN PCI_DEVICE_HEADER
*Device
,
1933 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
1937 Explain the bridge specific part of data in PCI configuration space.
1939 @param[in] Bridge Bridge specific data region in PCI configuration space.
1940 @param[in] Address Address used to access configuration space of this PCI device.
1941 @param[in] IoDev Handle used to access configuration space of PCI device.
1943 @retval EFI_SUCCESS The command completed successfully.
1946 PciExplainBridgeData (
1947 IN PCI_BRIDGE_HEADER
*Bridge
,
1949 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
1953 Explain the Base Address Register(Bar) in PCI configuration space.
1955 @param[in] Bar Points to the Base Address Register intended to interpret.
1956 @param[in] Command Points to the register Command.
1957 @param[in] Address Address used to access configuration space of this PCI device.
1958 @param[in] IoDev Handle used to access configuration space of PCI device.
1959 @param[in, out] Index The Index.
1961 @retval EFI_SUCCESS The command completed successfully.
1968 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
,
1973 Explain the cardbus specific part of data in PCI configuration space.
1975 @param[in] CardBus CardBus specific region of PCI configuration space.
1976 @param[in] Address Address used to access configuration space of this PCI device.
1977 @param[in] IoDev Handle used to access configuration space of PCI device.
1979 @retval EFI_SUCCESS The command completed successfully.
1982 PciExplainCardBusData (
1983 IN PCI_CARDBUS_HEADER
*CardBus
,
1985 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
1989 Explain each meaningful bit of register Status. The definition of Status is
1990 slightly different depending on the PCI header type.
1992 @param[in] Status Points to the content of register Status.
1993 @param[in] MainStatus Indicates if this register is main status(not secondary
1995 @param[in] HeaderType Header type of this PCI device.
1997 @retval EFI_SUCCESS The command completed successfully.
2002 IN BOOLEAN MainStatus
,
2003 IN PCI_HEADER_TYPE HeaderType
2007 Explain each meaningful bit of register Command.
2009 @param[in] Command Points to the content of register Command.
2011 @retval EFI_SUCCESS The command completed successfully.
2019 Explain each meaningful bit of register Bridge Control.
2021 @param[in] BridgeControl Points to the content of register Bridge Control.
2022 @param[in] HeaderType The headertype.
2024 @retval EFI_SUCCESS The command completed successfully.
2027 PciExplainBridgeControl (
2028 IN UINT16
*BridgeControl
,
2029 IN PCI_HEADER_TYPE HeaderType
2033 Print each capability structure.
2035 @param[in] IoDev The pointer to the deivce.
2036 @param[in] Address The address to start at.
2037 @param[in] CapPtr The offset from the address.
2038 @param[in] EnhancedDump The print format for the dump data.
2040 @retval EFI_SUCCESS The operation was successful.
2043 PciExplainCapabilityStruct (
2044 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
,
2047 IN CONST UINT16 EnhancedDump
2051 Display Pcie device structure.
2053 @param[in] IoDev The pointer to the root pci protocol.
2054 @param[in] Address The Address to start at.
2055 @param[in] CapabilityPtr The offset from the address to start.
2056 @param[in] EnhancedDump The print format for the dump data.
2058 @retval EFI_SUCCESS The command completed successfully.
2059 @retval @retval EFI_SUCCESS Pci express extend space IO is not suppoted.
2062 PciExplainPciExpress (
2063 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
,
2065 IN UINT8 CapabilityPtr
,
2066 IN CONST UINT16 EnhancedDump
2070 Print out information of the capability information.
2072 @param[in] PciExpressCap The pointer to the structure about the device.
2074 @retval EFI_SUCCESS The operation was successful.
2078 IN PCIE_CAP_STRUCTURE
*PciExpressCap
2082 Print out information of the device capability information.
2084 @param[in] PciExpressCap The pointer to the structure about the device.
2086 @retval EFI_SUCCESS The operation was successful.
2089 ExplainPcieDeviceCap (
2090 IN PCIE_CAP_STRUCTURE
*PciExpressCap
2094 Print out information of the device control information.
2096 @param[in] PciExpressCap The pointer to the structure about the device.
2098 @retval EFI_SUCCESS The operation was successful.
2101 ExplainPcieDeviceControl (
2102 IN PCIE_CAP_STRUCTURE
*PciExpressCap
2106 Print out information of the device status information.
2108 @param[in] PciExpressCap The pointer to the structure about the device.
2110 @retval EFI_SUCCESS The operation was successful.
2113 ExplainPcieDeviceStatus (
2114 IN PCIE_CAP_STRUCTURE
*PciExpressCap
2118 Print out information of the device link information.
2120 @param[in] PciExpressCap The pointer to the structure about the device.
2122 @retval EFI_SUCCESS The operation was successful.
2125 ExplainPcieLinkCap (
2126 IN PCIE_CAP_STRUCTURE
*PciExpressCap
2130 Print out information of the device link control information.
2132 @param[in] PciExpressCap The pointer to the structure about the device.
2134 @retval EFI_SUCCESS The operation was successful.
2137 ExplainPcieLinkControl (
2138 IN PCIE_CAP_STRUCTURE
*PciExpressCap
2142 Print out information of the device link status information.
2144 @param[in] PciExpressCap The pointer to the structure about the device.
2146 @retval EFI_SUCCESS The operation was successful.
2149 ExplainPcieLinkStatus (
2150 IN PCIE_CAP_STRUCTURE
*PciExpressCap
2154 Print out information of the device slot information.
2156 @param[in] PciExpressCap The pointer to the structure about the device.
2158 @retval EFI_SUCCESS The operation was successful.
2161 ExplainPcieSlotCap (
2162 IN PCIE_CAP_STRUCTURE
*PciExpressCap
2166 Print out information of the device slot control information.
2168 @param[in] PciExpressCap The pointer to the structure about the device.
2170 @retval EFI_SUCCESS The operation was successful.
2173 ExplainPcieSlotControl (
2174 IN PCIE_CAP_STRUCTURE
*PciExpressCap
2178 Print out information of the device slot status information.
2180 @param[in] PciExpressCap The pointer to the structure about the device.
2182 @retval EFI_SUCCESS The operation was successful.
2185 ExplainPcieSlotStatus (
2186 IN PCIE_CAP_STRUCTURE
*PciExpressCap
2190 Print out information of the device root information.
2192 @param[in] PciExpressCap The pointer to the structure about the device.
2194 @retval EFI_SUCCESS The operation was successful.
2197 ExplainPcieRootControl (
2198 IN PCIE_CAP_STRUCTURE
*PciExpressCap
2202 Print out information of the device root capability information.
2204 @param[in] PciExpressCap The pointer to the structure about the device.
2206 @retval EFI_SUCCESS The operation was successful.
2209 ExplainPcieRootCap (
2210 IN PCIE_CAP_STRUCTURE
*PciExpressCap
2214 Print out information of the device root status information.
2216 @param[in] PciExpressCap The pointer to the structure about the device.
2218 @retval EFI_SUCCESS The operation was successful.
2221 ExplainPcieRootStatus (
2222 IN PCIE_CAP_STRUCTURE
*PciExpressCap
2225 typedef EFI_STATUS (*PCIE_EXPLAIN_FUNCTION
) (IN PCIE_CAP_STRUCTURE
*PciExpressCap
);
2231 } PCIE_CAPREG_FIELD_WIDTH
;
2234 PcieExplainTypeCommon
,
2235 PcieExplainTypeDevice
,
2236 PcieExplainTypeLink
,
2237 PcieExplainTypeSlot
,
2238 PcieExplainTypeRoot
,
2240 } PCIE_EXPLAIN_TYPE
;
2246 PCIE_CAPREG_FIELD_WIDTH Width
;
2247 PCIE_EXPLAIN_FUNCTION Func
;
2248 PCIE_EXPLAIN_TYPE Type
;
2249 } PCIE_EXPLAIN_STRUCT
;
2251 PCIE_EXPLAIN_STRUCT PcieExplainList
[] = {
2253 STRING_TOKEN (STR_PCIEX_CAPABILITY_CAPID
),
2257 PcieExplainTypeCommon
2260 STRING_TOKEN (STR_PCIEX_NEXTCAP_PTR
),
2264 PcieExplainTypeCommon
2267 STRING_TOKEN (STR_PCIEX_CAP_REGISTER
),
2271 PcieExplainTypeCommon
2274 STRING_TOKEN (STR_PCIEX_DEVICE_CAP
),
2277 ExplainPcieDeviceCap
,
2278 PcieExplainTypeDevice
2281 STRING_TOKEN (STR_PCIEX_DEVICE_CONTROL
),
2284 ExplainPcieDeviceControl
,
2285 PcieExplainTypeDevice
2288 STRING_TOKEN (STR_PCIEX_DEVICE_STATUS
),
2291 ExplainPcieDeviceStatus
,
2292 PcieExplainTypeDevice
2295 STRING_TOKEN (STR_PCIEX_LINK_CAPABILITIES
),
2302 STRING_TOKEN (STR_PCIEX_LINK_CONTROL
),
2305 ExplainPcieLinkControl
,
2309 STRING_TOKEN (STR_PCIEX_LINK_STATUS
),
2312 ExplainPcieLinkStatus
,
2316 STRING_TOKEN (STR_PCIEX_SLOT_CAPABILITIES
),
2323 STRING_TOKEN (STR_PCIEX_SLOT_CONTROL
),
2326 ExplainPcieSlotControl
,
2330 STRING_TOKEN (STR_PCIEX_SLOT_STATUS
),
2333 ExplainPcieSlotStatus
,
2337 STRING_TOKEN (STR_PCIEX_ROOT_CONTROL
),
2340 ExplainPcieRootControl
,
2344 STRING_TOKEN (STR_PCIEX_RSVDP
),
2351 STRING_TOKEN (STR_PCIEX_ROOT_STATUS
),
2354 ExplainPcieRootStatus
,
2360 (PCIE_CAPREG_FIELD_WIDTH
)0,
2369 PCI_CONFIG_SPACE
*mConfigSpace
= NULL
;
2370 STATIC CONST SHELL_PARAM_ITEM ParamList
[] = {
2377 CHAR16
*DevicePortTypeTable
[] = {
2378 L
"PCI Express Endpoint",
2379 L
"Legacy PCI Express Endpoint",
2382 L
"Root Port of PCI Express Root Complex",
2383 L
"Upstream Port of PCI Express Switch",
2384 L
"Downstream Port of PCI Express Switch",
2385 L
"PCI Express to PCI/PCI-X Bridge",
2386 L
"PCI/PCI-X to PCI Express Bridge",
2387 L
"Root Complex Integrated Endpoint",
2388 L
"Root Complex Event Collector"
2391 CHAR16
*L0sLatencyStrTable
[] = {
2393 L
"64ns to less than 128ns",
2394 L
"128ns to less than 256ns",
2395 L
"256ns to less than 512ns",
2396 L
"512ns to less than 1us",
2397 L
"1us to less than 2us",
2402 CHAR16
*L1LatencyStrTable
[] = {
2404 L
"1us to less than 2us",
2405 L
"2us to less than 4us",
2406 L
"4us to less than 8us",
2407 L
"8us to less than 16us",
2408 L
"16us to less than 32us",
2413 CHAR16
*ASPMCtrlStrTable
[] = {
2415 L
"L0s Entry Enabled",
2416 L
"L1 Entry Enabled",
2417 L
"L0s and L1 Entry Enabled"
2420 CHAR16
*SlotPwrLmtScaleTable
[] = {
2427 CHAR16
*IndicatorTable
[] = {
2436 Function for 'pci' command.
2438 @param[in] ImageHandle Handle to the Image (NULL if Internal).
2439 @param[in] SystemTable Pointer to the System Table (NULL if Internal).
2443 ShellCommandRunPci (
2444 IN EFI_HANDLE ImageHandle
,
2445 IN EFI_SYSTEM_TABLE
*SystemTable
2453 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
;
2455 PCI_COMMON_HEADER PciHeader
;
2456 PCI_CONFIG_SPACE ConfigSpace
;
2460 BOOLEAN ExplainData
;
2464 UINTN HandleBufSize
;
2465 EFI_HANDLE
*HandleBuf
;
2467 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
*Descriptors
;
2471 LIST_ENTRY
*Package
;
2472 CHAR16
*ProblemParam
;
2473 SHELL_STATUS ShellStatus
;
2476 UINT16 EnhancedDump
;
2478 ShellStatus
= SHELL_SUCCESS
;
2479 Status
= EFI_SUCCESS
;
2486 // initialize the shell lib (we must be in non-auto-init...)
2488 Status
= ShellInitialize();
2489 ASSERT_EFI_ERROR(Status
);
2491 Status
= CommandInit();
2492 ASSERT_EFI_ERROR(Status
);
2495 // parse the command line
2497 Status
= ShellCommandLineParse (ParamList
, &Package
, &ProblemParam
, TRUE
);
2498 if (EFI_ERROR(Status
)) {
2499 if (Status
== EFI_VOLUME_CORRUPTED
&& ProblemParam
!= NULL
) {
2500 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_GEN_PROBLEM
), gShellDebug1HiiHandle
, L
"pci", ProblemParam
);
2501 FreePool(ProblemParam
);
2502 ShellStatus
= SHELL_INVALID_PARAMETER
;
2508 if (ShellCommandLineGetCount(Package
) == 2) {
2509 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_GEN_TOO_FEW
), gShellDebug1HiiHandle
, L
"pci");
2510 ShellStatus
= SHELL_INVALID_PARAMETER
;
2514 if (ShellCommandLineGetCount(Package
) > 4) {
2515 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_GEN_TOO_MANY
), gShellDebug1HiiHandle
, L
"pci");
2516 ShellStatus
= SHELL_INVALID_PARAMETER
;
2519 if (ShellCommandLineGetFlag(Package
, L
"-s") && ShellCommandLineGetValue(Package
, L
"-s") == NULL
) {
2520 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_GEN_NO_VALUE
), gShellDebug1HiiHandle
, L
"pci", L
"-s");
2521 ShellStatus
= SHELL_INVALID_PARAMETER
;
2525 // Get all instances of PciRootBridgeIo. Allocate space for 1 EFI_HANDLE and
2526 // call LibLocateHandle(), if EFI_BUFFER_TOO_SMALL is returned, allocate enough
2527 // space for handles and call it again.
2529 HandleBufSize
= sizeof (EFI_HANDLE
);
2530 HandleBuf
= (EFI_HANDLE
*) AllocateZeroPool (HandleBufSize
);
2531 if (HandleBuf
== NULL
) {
2532 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_GEN_OUT_MEM
), gShellDebug1HiiHandle
, L
"pci");
2533 ShellStatus
= SHELL_OUT_OF_RESOURCES
;
2537 Status
= gBS
->LocateHandle (
2539 &gEfiPciRootBridgeIoProtocolGuid
,
2545 if (Status
== EFI_BUFFER_TOO_SMALL
) {
2546 HandleBuf
= ReallocatePool (sizeof (EFI_HANDLE
), HandleBufSize
, HandleBuf
);
2547 if (HandleBuf
== NULL
) {
2548 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_GEN_OUT_MEM
), gShellDebug1HiiHandle
, L
"pci");
2549 ShellStatus
= SHELL_OUT_OF_RESOURCES
;
2553 Status
= gBS
->LocateHandle (
2555 &gEfiPciRootBridgeIoProtocolGuid
,
2562 if (EFI_ERROR (Status
)) {
2563 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_GEN_PCIRBIO_NF
), gShellDebug1HiiHandle
, L
"pci");
2564 ShellStatus
= SHELL_NOT_FOUND
;
2568 HandleCount
= HandleBufSize
/ sizeof (EFI_HANDLE
);
2570 // Argument Count == 1(no other argument): enumerate all pci functions
2572 if (ShellCommandLineGetCount(Package
) == 1) {
2573 gST
->ConOut
->QueryMode (
2575 gST
->ConOut
->Mode
->Mode
,
2582 if ((ScreenSize
& 1) == 1) {
2589 // For each handle, which decides a segment and a bus number range,
2590 // enumerate all devices on it.
2592 for (Index
= 0; Index
< HandleCount
; Index
++) {
2593 Status
= PciGetProtocolAndResource (
2598 if (EFI_ERROR (Status
)) {
2599 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_PCI_HANDLE_CFG_ERR
), gShellDebug1HiiHandle
, L
"pci");
2600 ShellStatus
= SHELL_NOT_FOUND
;
2604 // No document say it's impossible for a RootBridgeIo protocol handle
2605 // to have more than one address space descriptors, so find out every
2606 // bus range and for each of them do device enumeration.
2609 Status
= PciGetNextBusRange (&Descriptors
, &MinBus
, &MaxBus
, &IsEnd
);
2611 if (EFI_ERROR (Status
)) {
2612 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_PCI_BUS_RANGE_ERR
), gShellDebug1HiiHandle
, L
"pci");
2613 ShellStatus
= SHELL_NOT_FOUND
;
2621 for (Bus
= MinBus
; Bus
<= MaxBus
; Bus
++) {
2623 // For each devices, enumerate all functions it contains
2625 for (Device
= 0; Device
<= PCI_MAX_DEVICE
; Device
++) {
2627 // For each function, read its configuration space and print summary
2629 for (Func
= 0; Func
<= PCI_MAX_FUNC
; Func
++) {
2630 if (ShellGetExecutionBreakFlag ()) {
2631 ShellStatus
= SHELL_ABORTED
;
2634 Address
= CALC_EFI_PCI_ADDRESS (Bus
, Device
, Func
, 0);
2644 // If VendorId = 0xffff, there does not exist a device at this
2645 // location. For each device, if there is any function on it,
2646 // there must be 1 function at Function 0. So if Func = 0, there
2647 // will be no more functions in the same device, so we can break
2648 // loop to deal with the next device.
2650 if (PciHeader
.VendorId
== 0xffff && Func
== 0) {
2654 if (PciHeader
.VendorId
!= 0xffff) {
2657 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_PCI_TITLE
), gShellDebug1HiiHandle
);
2665 sizeof (PciHeader
) / sizeof (UINT32
),
2670 -1, -1, NULL
, STRING_TOKEN (STR_PCI_LINE_P1
), gShellDebug1HiiHandle
,
2671 IoDev
->SegmentNumber
,
2677 PciPrintClassCode (PciHeader
.ClassCode
, FALSE
);
2679 -1, -1, NULL
, STRING_TOKEN (STR_PCI_LINE_P2
), gShellDebug1HiiHandle
,
2682 PciHeader
.ClassCode
[0]
2686 if (ScreenCount
>= ScreenSize
&& ScreenSize
!= 0) {
2688 // If ScreenSize == 0 we have the console redirected so don't
2694 // If this is not a multi-function device, we can leave the loop
2695 // to deal with the next device.
2697 if (Func
== 0 && ((PciHeader
.HeaderType
& HEADER_TYPE_MULTI_FUNCTION
) == 0x00)) {
2705 // If Descriptor is NULL, Configuration() returns EFI_UNSUPPRORED,
2706 // we assume the bus range is 0~PCI_MAX_BUS. After enumerated all
2707 // devices on all bus, we can leave loop.
2709 if (Descriptors
== NULL
) {
2715 Status
= EFI_SUCCESS
;
2719 ExplainData
= FALSE
;
2724 if (ShellCommandLineGetFlag(Package
, L
"-i")) {
2728 Temp
= ShellCommandLineGetValue(Package
, L
"-s");
2731 // Input converted to hexadecimal number.
2733 if (!EFI_ERROR (ShellConvertStringToUint64 (Temp
, &RetVal
, TRUE
, TRUE
))) {
2734 Segment
= (UINT16
) RetVal
;
2736 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_GEN_PARAM_INV_HEX
), gShellDebug1HiiHandle
, L
"pci", Temp
);
2737 ShellStatus
= SHELL_INVALID_PARAMETER
;
2743 // The first Argument(except "-i") is assumed to be Bus number, second
2744 // to be Device number, and third to be Func number.
2746 Temp
= ShellCommandLineGetRawValue(Package
, 1);
2749 // Input converted to hexadecimal number.
2751 if (!EFI_ERROR (ShellConvertStringToUint64 (Temp
, &RetVal
, TRUE
, TRUE
))) {
2752 Bus
= (UINT16
) RetVal
;
2754 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_GEN_PARAM_INV_HEX
), gShellDebug1HiiHandle
, L
"pci", Temp
);
2755 ShellStatus
= SHELL_INVALID_PARAMETER
;
2759 if (Bus
> MAX_BUS_NUMBER
) {
2760 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_GEN_PARAM_INV
), gShellDebug1HiiHandle
, L
"pci", Temp
);
2761 ShellStatus
= SHELL_INVALID_PARAMETER
;
2765 Temp
= ShellCommandLineGetRawValue(Package
, 2);
2768 // Input converted to hexadecimal number.
2770 if (!EFI_ERROR (ShellConvertStringToUint64 (Temp
, &RetVal
, TRUE
, TRUE
))) {
2771 Device
= (UINT16
) RetVal
;
2773 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_GEN_PARAM_INV_HEX
), gShellDebug1HiiHandle
, L
"pci", Temp
);
2774 ShellStatus
= SHELL_INVALID_PARAMETER
;
2778 if (Device
> MAX_DEVICE_NUMBER
){
2779 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_GEN_PARAM_INV
), gShellDebug1HiiHandle
, L
"pci", Temp
);
2780 ShellStatus
= SHELL_INVALID_PARAMETER
;
2785 Temp
= ShellCommandLineGetRawValue(Package
, 3);
2788 // Input converted to hexadecimal number.
2790 if (!EFI_ERROR (ShellConvertStringToUint64 (Temp
, &RetVal
, TRUE
, TRUE
))) {
2791 Func
= (UINT16
) RetVal
;
2793 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_GEN_PARAM_INV_HEX
), gShellDebug1HiiHandle
, L
"pci", Temp
);
2794 ShellStatus
= SHELL_INVALID_PARAMETER
;
2798 if (Func
> MAX_FUNCTION_NUMBER
){
2799 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_GEN_PARAM_INV
), gShellDebug1HiiHandle
, L
"pci", Temp
);
2800 ShellStatus
= SHELL_INVALID_PARAMETER
;
2806 // Find the protocol interface who's in charge of current segment, and its
2807 // bus range covers the current bus
2809 Status
= PciFindProtocolInterface (
2817 if (EFI_ERROR (Status
)) {
2819 -1, -1, NULL
, STRING_TOKEN (STR_PCI_NO_FIND
), gShellDebug1HiiHandle
, L
"pci",
2823 ShellStatus
= SHELL_NOT_FOUND
;
2827 Address
= CALC_EFI_PCI_ADDRESS (Bus
, Device
, Func
, 0);
2828 Status
= IoDev
->Pci
.Read (
2832 sizeof (ConfigSpace
),
2836 if (EFI_ERROR (Status
)) {
2837 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_PCI_NO_CFG
), gShellDebug1HiiHandle
, L
"pci");
2838 ShellStatus
= SHELL_ACCESS_DENIED
;
2842 mConfigSpace
= &ConfigSpace
;
2847 STRING_TOKEN (STR_PCI_INFO
),
2848 gShellDebug1HiiHandle
,
2860 // Dump standard header of configuration space
2862 SizeOfHeader
= sizeof (ConfigSpace
.Common
) + sizeof (ConfigSpace
.NonCommon
);
2864 DumpHex (2, 0, SizeOfHeader
, &ConfigSpace
);
2865 ShellPrintEx(-1,-1, L
"\r\n");
2868 // Dump device dependent Part of configuration space
2873 sizeof (ConfigSpace
) - SizeOfHeader
,
2878 // If "-i" appears in command line, interpret data in configuration space
2882 if (ShellCommandLineGetFlag(Package
, L
"-_e")) {
2883 EnhancedDump
= 0xFFFF;
2884 Temp
= ShellCommandLineGetValue(Package
, L
"-_e");
2886 EnhancedDump
= (UINT16
) ShellHexStrToUintn (Temp
);
2889 Status
= PciExplainData (&ConfigSpace
, Address
, IoDev
, EnhancedDump
);
2893 if (HandleBuf
!= NULL
) {
2894 FreePool (HandleBuf
);
2896 if (Package
!= NULL
) {
2897 ShellCommandLineFreeVarList (Package
);
2899 mConfigSpace
= NULL
;
2904 This function finds out the protocol which is in charge of the given
2905 segment, and its bus range covers the current bus number. It lookes
2906 each instances of RootBridgeIoProtocol handle, until the one meets the
2909 @param[in] HandleBuf Buffer which holds all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.
2910 @param[in] HandleCount Count of all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.
2911 @param[in] Segment Segment number of device we are dealing with.
2912 @param[in] Bus Bus number of device we are dealing with.
2913 @param[out] IoDev Handle used to access configuration space of PCI device.
2915 @retval EFI_SUCCESS The command completed successfully.
2916 @retval EFI_INVALID_PARAMETER Invalid parameter.
2920 PciFindProtocolInterface (
2921 IN EFI_HANDLE
*HandleBuf
,
2922 IN UINTN HandleCount
,
2925 OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
**IoDev
2930 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
*Descriptors
;
2936 // Go through all handles, until the one meets the criteria is found
2938 for (Index
= 0; Index
< HandleCount
; Index
++) {
2939 Status
= PciGetProtocolAndResource (HandleBuf
[Index
], IoDev
, &Descriptors
);
2940 if (EFI_ERROR (Status
)) {
2944 // When Descriptors == NULL, the Configuration() is not implemented,
2945 // so we only check the Segment number
2947 if (Descriptors
== NULL
&& Segment
== (*IoDev
)->SegmentNumber
) {
2951 if ((*IoDev
)->SegmentNumber
!= Segment
) {
2956 Status
= PciGetNextBusRange (&Descriptors
, &MinBus
, &MaxBus
, &IsEnd
);
2957 if (EFI_ERROR (Status
)) {
2965 if (MinBus
<= Bus
&& MaxBus
>= Bus
) {
2971 return EFI_NOT_FOUND
;
2975 This function gets the protocol interface from the given handle, and
2976 obtains its address space descriptors.
2978 @param[in] Handle The PCI_ROOT_BRIDIGE_IO_PROTOCOL handle.
2979 @param[out] IoDev Handle used to access configuration space of PCI device.
2980 @param[out] Descriptors Points to the address space descriptors.
2982 @retval EFI_SUCCESS The command completed successfully
2985 PciGetProtocolAndResource (
2986 IN EFI_HANDLE Handle
,
2987 OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
**IoDev
,
2988 OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
**Descriptors
2994 // Get inferface from protocol
2996 Status
= gBS
->HandleProtocol (
2998 &gEfiPciRootBridgeIoProtocolGuid
,
3002 if (EFI_ERROR (Status
)) {
3006 // Call Configuration() to get address space descriptors
3008 Status
= (*IoDev
)->Configuration (*IoDev
, (VOID
**)Descriptors
);
3009 if (Status
== EFI_UNSUPPORTED
) {
3010 *Descriptors
= NULL
;
3019 This function get the next bus range of given address space descriptors.
3020 It also moves the pointer backward a node, to get prepared to be called
3023 @param[in, out] Descriptors Points to current position of a serial of address space
3025 @param[out] MinBus The lower range of bus number.
3026 @param[out] MaxBus The upper range of bus number.
3027 @param[out] IsEnd Meet end of the serial of descriptors.
3029 @retval EFI_SUCCESS The command completed successfully.
3032 PciGetNextBusRange (
3033 IN OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
**Descriptors
,
3042 // When *Descriptors is NULL, Configuration() is not implemented, so assume
3043 // range is 0~PCI_MAX_BUS
3045 if ((*Descriptors
) == NULL
) {
3047 *MaxBus
= PCI_MAX_BUS
;
3051 // *Descriptors points to one or more address space descriptors, which
3052 // ends with a end tagged descriptor. Examine each of the descriptors,
3053 // if a bus typed one is found and its bus range covers bus, this handle
3054 // is the handle we are looking for.
3057 while ((*Descriptors
)->Desc
!= ACPI_END_TAG_DESCRIPTOR
) {
3058 if ((*Descriptors
)->ResType
== ACPI_ADDRESS_SPACE_TYPE_BUS
) {
3059 *MinBus
= (UINT16
) (*Descriptors
)->AddrRangeMin
;
3060 *MaxBus
= (UINT16
) (*Descriptors
)->AddrRangeMax
;
3062 return (EFI_SUCCESS
);
3068 if ((*Descriptors
)->Desc
== ACPI_END_TAG_DESCRIPTOR
) {
3076 Explain the data in PCI configuration space. The part which is common for
3077 PCI device and bridge is interpreted in this function. It calls other
3078 functions to interpret data unique for device or bridge.
3080 @param[in] ConfigSpace Data in PCI configuration space.
3081 @param[in] Address Address used to access configuration space of this PCI device.
3082 @param[in] IoDev Handle used to access configuration space of PCI device.
3083 @param[in] EnhancedDump The print format for the dump data.
3085 @retval EFI_SUCCESS The command completed successfully.
3089 IN PCI_CONFIG_SPACE
*ConfigSpace
,
3091 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
,
3092 IN CONST UINT16 EnhancedDump
3095 PCI_COMMON_HEADER
*Common
;
3096 PCI_HEADER_TYPE HeaderType
;
3100 Common
= &(ConfigSpace
->Common
);
3102 ShellPrintEx (-1, -1, L
"\r\n");
3105 // Print Vendor Id and Device Id
3107 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_PCI_LINE_VID_DID
), gShellDebug1HiiHandle
,
3108 INDEX_OF (&(Common
->VendorId
)),
3110 INDEX_OF (&(Common
->DeviceId
)),
3115 // Print register Command
3117 PciExplainCommand (&(Common
->Command
));
3120 // Print register Status
3122 PciExplainStatus (&(Common
->Status
), TRUE
, PciUndefined
);
3125 // Print register Revision ID
3127 ShellPrintEx(-1, -1, L
"\r\n");
3128 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_PCI_LINE_RID
), gShellDebug1HiiHandle
,
3129 INDEX_OF (&(Common
->RevisionId
)),
3134 // Print register BIST
3136 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_PCI_LINE_BIST
), gShellDebug1HiiHandle
, INDEX_OF (&(Common
->Bist
)));
3137 if ((Common
->Bist
& PCI_BIT_7
) != 0) {
3138 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_PCI_LINE_CAP
), gShellDebug1HiiHandle
, 0x0f & Common
->Bist
);
3140 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_PCI_LINE_CAP_NO
), gShellDebug1HiiHandle
);
3143 // Print register Cache Line Size
3145 ShellPrintHiiEx(-1, -1, NULL
,
3146 STRING_TOKEN (STR_PCI2_CACHE_LINE_SIZE
),
3147 gShellDebug1HiiHandle
,
3148 INDEX_OF (&(Common
->CacheLineSize
)),
3149 Common
->CacheLineSize
3153 // Print register Latency Timer
3155 ShellPrintHiiEx(-1, -1, NULL
,
3156 STRING_TOKEN (STR_PCI2_LATENCY_TIMER
),
3157 gShellDebug1HiiHandle
,
3158 INDEX_OF (&(Common
->PrimaryLatencyTimer
)),
3159 Common
->PrimaryLatencyTimer
3163 // Print register Header Type
3165 ShellPrintHiiEx(-1, -1, NULL
,
3166 STRING_TOKEN (STR_PCI2_HEADER_TYPE
),
3167 gShellDebug1HiiHandle
,
3168 INDEX_OF (&(Common
->HeaderType
)),
3172 if ((Common
->HeaderType
& PCI_BIT_7
) != 0) {
3173 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_MULTI_FUNCTION
), gShellDebug1HiiHandle
);
3176 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_SINGLE_FUNCTION
), gShellDebug1HiiHandle
);
3179 HeaderType
= (PCI_HEADER_TYPE
)(UINT8
) (Common
->HeaderType
& 0x7f);
3180 switch (HeaderType
) {
3182 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_PCI_DEVICE
), gShellDebug1HiiHandle
);
3186 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_P2P_BRIDGE
), gShellDebug1HiiHandle
);
3189 case PciCardBusBridge
:
3190 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_CARDBUS_BRIDGE
), gShellDebug1HiiHandle
);
3194 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_RESERVED
), gShellDebug1HiiHandle
);
3195 HeaderType
= PciUndefined
;
3199 // Print register Class Code
3201 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_CLASS
), gShellDebug1HiiHandle
);
3202 PciPrintClassCode ((UINT8
*) Common
->ClassCode
, TRUE
);
3203 ShellPrintEx (-1, -1, L
"\r\n");
3205 if (ShellGetExecutionBreakFlag()) {
3210 // Interpret remaining part of PCI configuration header depending on
3214 Status
= EFI_SUCCESS
;
3215 switch (HeaderType
) {
3217 Status
= PciExplainDeviceData (
3218 &(ConfigSpace
->NonCommon
.Device
),
3222 CapPtr
= ConfigSpace
->NonCommon
.Device
.CapabilitiesPtr
;
3226 Status
= PciExplainBridgeData (
3227 &(ConfigSpace
->NonCommon
.Bridge
),
3231 CapPtr
= ConfigSpace
->NonCommon
.Bridge
.CapabilitiesPtr
;
3234 case PciCardBusBridge
:
3235 Status
= PciExplainCardBusData (
3236 &(ConfigSpace
->NonCommon
.CardBus
),
3240 CapPtr
= ConfigSpace
->NonCommon
.CardBus
.CapabilitiesPtr
;
3247 // If Status bit4 is 1, dump or explain capability structure
3249 if ((Common
->Status
) & EFI_PCI_STATUS_CAPABILITY
) {
3250 PciExplainCapabilityStruct (IoDev
, Address
, CapPtr
, EnhancedDump
);
3257 Explain the device specific part of data in PCI configuration space.
3259 @param[in] Device Data in PCI configuration space.
3260 @param[in] Address Address used to access configuration space of this PCI device.
3261 @param[in] IoDev Handle used to access configuration space of PCI device.
3263 @retval EFI_SUCCESS The command completed successfully.
3266 PciExplainDeviceData (
3267 IN PCI_DEVICE_HEADER
*Device
,
3269 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
3278 // Print Base Address Registers(Bar). When Bar = 0, this Bar does not
3279 // exist. If these no Bar for this function, print "none", otherwise
3280 // list detail information about this Bar.
3282 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_BASE_ADDR
), gShellDebug1HiiHandle
, INDEX_OF (Device
->Bar
));
3285 BarCount
= sizeof (Device
->Bar
) / sizeof (Device
->Bar
[0]);
3286 for (Index
= 0; Index
< BarCount
; Index
++) {
3287 if (Device
->Bar
[Index
] == 0) {
3293 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_START_TYPE
), gShellDebug1HiiHandle
);
3294 ShellPrintEx (-1, -1, L
" --------------------------------------------------------------------------");
3297 Status
= PciExplainBar (
3298 &(Device
->Bar
[Index
]),
3299 &(mConfigSpace
->Common
.Command
),
3305 if (EFI_ERROR (Status
)) {
3311 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_NONE
), gShellDebug1HiiHandle
);
3314 ShellPrintEx (-1, -1, L
"\r\n --------------------------------------------------------------------------");
3318 // Print register Expansion ROM Base Address
3320 if ((Device
->ROMBar
& PCI_BIT_0
) == 0) {
3321 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_EXPANSION_ROM_DISABLED
), gShellDebug1HiiHandle
, INDEX_OF (&(Device
->ROMBar
)));
3324 ShellPrintHiiEx(-1, -1, NULL
,
3325 STRING_TOKEN (STR_PCI2_EXPANSION_ROM_BASE
),
3326 gShellDebug1HiiHandle
,
3327 INDEX_OF (&(Device
->ROMBar
)),
3332 // Print register Cardbus CIS ptr
3334 ShellPrintHiiEx(-1, -1, NULL
,
3335 STRING_TOKEN (STR_PCI2_CARDBUS_CIS
),
3336 gShellDebug1HiiHandle
,
3337 INDEX_OF (&(Device
->CardBusCISPtr
)),
3338 Device
->CardBusCISPtr
3342 // Print register Sub-vendor ID and subsystem ID
3344 ShellPrintHiiEx(-1, -1, NULL
,
3345 STRING_TOKEN (STR_PCI2_SUB_VENDOR_ID
),
3346 gShellDebug1HiiHandle
,
3347 INDEX_OF (&(Device
->SubVendorId
)),
3351 ShellPrintHiiEx(-1, -1, NULL
,
3352 STRING_TOKEN (STR_PCI2_SUBSYSTEM_ID
),
3353 gShellDebug1HiiHandle
,
3354 INDEX_OF (&(Device
->SubSystemId
)),
3359 // Print register Capabilities Ptr
3361 ShellPrintHiiEx(-1, -1, NULL
,
3362 STRING_TOKEN (STR_PCI2_CAPABILITIES_PTR
),
3363 gShellDebug1HiiHandle
,
3364 INDEX_OF (&(Device
->CapabilitiesPtr
)),
3365 Device
->CapabilitiesPtr
3369 // Print register Interrupt Line and interrupt pin
3371 ShellPrintHiiEx(-1, -1, NULL
,
3372 STRING_TOKEN (STR_PCI2_INTERRUPT_LINE
),
3373 gShellDebug1HiiHandle
,
3374 INDEX_OF (&(Device
->InterruptLine
)),
3375 Device
->InterruptLine
3378 ShellPrintHiiEx(-1, -1, NULL
,
3379 STRING_TOKEN (STR_PCI2_INTERRUPT_PIN
),
3380 gShellDebug1HiiHandle
,
3381 INDEX_OF (&(Device
->InterruptPin
)),
3382 Device
->InterruptPin
3386 // Print register Min_Gnt and Max_Lat
3388 ShellPrintHiiEx(-1, -1, NULL
,
3389 STRING_TOKEN (STR_PCI2_MIN_GNT
),
3390 gShellDebug1HiiHandle
,
3391 INDEX_OF (&(Device
->MinGnt
)),
3395 ShellPrintHiiEx(-1, -1, NULL
,
3396 STRING_TOKEN (STR_PCI2_MAX_LAT
),
3397 gShellDebug1HiiHandle
,
3398 INDEX_OF (&(Device
->MaxLat
)),
3406 Explain the bridge specific part of data in PCI configuration space.
3408 @param[in] Bridge Bridge specific data region in PCI configuration space.
3409 @param[in] Address Address used to access configuration space of this PCI device.
3410 @param[in] IoDev Handle used to access configuration space of PCI device.
3412 @retval EFI_SUCCESS The command completed successfully.
3415 PciExplainBridgeData (
3416 IN PCI_BRIDGE_HEADER
*Bridge
,
3418 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
3428 // Print Base Address Registers. When Bar = 0, this Bar does not
3429 // exist. If these no Bar for this function, print "none", otherwise
3430 // list detail information about this Bar.
3432 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_BASE_ADDRESS
), gShellDebug1HiiHandle
, INDEX_OF (&(Bridge
->Bar
)));
3435 BarCount
= sizeof (Bridge
->Bar
) / sizeof (Bridge
->Bar
[0]);
3437 for (Index
= 0; Index
< BarCount
; Index
++) {
3438 if (Bridge
->Bar
[Index
] == 0) {
3444 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_START_TYPE_2
), gShellDebug1HiiHandle
);
3445 ShellPrintEx (-1, -1, L
" --------------------------------------------------------------------------");
3448 Status
= PciExplainBar (
3449 &(Bridge
->Bar
[Index
]),
3450 &(mConfigSpace
->Common
.Command
),
3456 if (EFI_ERROR (Status
)) {
3462 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_NONE
), gShellDebug1HiiHandle
);
3464 ShellPrintEx (-1, -1, L
"\r\n --------------------------------------------------------------------------");
3468 // Expansion register ROM Base Address
3470 if ((Bridge
->ROMBar
& PCI_BIT_0
) == 0) {
3471 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_NO_EXPANSION_ROM
), gShellDebug1HiiHandle
, INDEX_OF (&(Bridge
->ROMBar
)));
3474 ShellPrintHiiEx(-1, -1, NULL
,
3475 STRING_TOKEN (STR_PCI2_EXPANSION_ROM_BASE_2
),
3476 gShellDebug1HiiHandle
,
3477 INDEX_OF (&(Bridge
->ROMBar
)),
3482 // Print Bus Numbers(Primary, Secondary, and Subordinate
3484 ShellPrintHiiEx(-1, -1, NULL
,
3485 STRING_TOKEN (STR_PCI2_BUS_NUMBERS
),
3486 gShellDebug1HiiHandle
,
3487 INDEX_OF (&(Bridge
->PrimaryBus
)),
3488 INDEX_OF (&(Bridge
->SecondaryBus
)),
3489 INDEX_OF (&(Bridge
->SubordinateBus
))
3492 ShellPrintEx (-1, -1, L
" ------------------------------------------------------\r\n");
3494 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_BRIDGE
), gShellDebug1HiiHandle
, Bridge
->PrimaryBus
);
3495 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_BRIDGE
), gShellDebug1HiiHandle
, Bridge
->SecondaryBus
);
3496 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_BRIDGE
), gShellDebug1HiiHandle
, Bridge
->SubordinateBus
);
3499 // Print register Secondary Latency Timer
3501 ShellPrintHiiEx(-1, -1, NULL
,
3502 STRING_TOKEN (STR_PCI2_SECONDARY_TIMER
),
3503 gShellDebug1HiiHandle
,
3504 INDEX_OF (&(Bridge
->SecondaryLatencyTimer
)),
3505 Bridge
->SecondaryLatencyTimer
3509 // Print register Secondary Status
3511 PciExplainStatus (&(Bridge
->SecondaryStatus
), FALSE
, PciP2pBridge
);
3514 // Print I/O and memory ranges this bridge forwards. There are 3 resource
3515 // types: I/O, memory, and pre-fetchable memory. For each resource type,
3516 // base and limit address are listed.
3518 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_RESOURCE_TYPE
), gShellDebug1HiiHandle
);
3519 ShellPrintEx (-1, -1, L
"----------------------------------------------------------------------\r\n");
3524 IoAddress32
= (Bridge
->IoBaseUpper
<< 16 | Bridge
->IoBase
<< 8);
3525 IoAddress32
&= 0xfffff000;
3526 ShellPrintHiiEx(-1, -1, NULL
,
3527 STRING_TOKEN (STR_PCI2_TWO_VARS
),
3528 gShellDebug1HiiHandle
,
3529 INDEX_OF (&(Bridge
->IoBase
)),
3533 IoAddress32
= (Bridge
->IoLimitUpper
<< 16 | Bridge
->IoLimit
<< 8);
3534 IoAddress32
|= 0x00000fff;
3535 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_ONE_VAR
), gShellDebug1HiiHandle
, IoAddress32
);
3538 // Memory Base & Limit
3540 ShellPrintHiiEx(-1, -1, NULL
,
3541 STRING_TOKEN (STR_PCI2_MEMORY
),
3542 gShellDebug1HiiHandle
,
3543 INDEX_OF (&(Bridge
->MemoryBase
)),
3544 (Bridge
->MemoryBase
<< 16) & 0xfff00000
3547 ShellPrintHiiEx(-1, -1, NULL
,
3548 STRING_TOKEN (STR_PCI2_ONE_VAR
),
3549 gShellDebug1HiiHandle
,
3550 (Bridge
->MemoryLimit
<< 16) | 0x000fffff
3554 // Pre-fetch-able Memory Base & Limit
3556 ShellPrintHiiEx(-1, -1, NULL
,
3557 STRING_TOKEN (STR_PCI2_PREFETCHABLE
),
3558 gShellDebug1HiiHandle
,
3559 INDEX_OF (&(Bridge
->PrefetchableMemBase
)),
3560 Bridge
->PrefetchableBaseUpper
,
3561 (Bridge
->PrefetchableMemBase
<< 16) & 0xfff00000
3564 ShellPrintHiiEx(-1, -1, NULL
,
3565 STRING_TOKEN (STR_PCI2_TWO_VARS_2
),
3566 gShellDebug1HiiHandle
,
3567 Bridge
->PrefetchableLimitUpper
,
3568 (Bridge
->PrefetchableMemLimit
<< 16) | 0x000fffff
3572 // Print register Capabilities Pointer
3574 ShellPrintHiiEx(-1, -1, NULL
,
3575 STRING_TOKEN (STR_PCI2_CAPABILITIES_PTR_2
),
3576 gShellDebug1HiiHandle
,
3577 INDEX_OF (&(Bridge
->CapabilitiesPtr
)),
3578 Bridge
->CapabilitiesPtr
3582 // Print register Bridge Control
3584 PciExplainBridgeControl (&(Bridge
->BridgeControl
), PciP2pBridge
);
3587 // Print register Interrupt Line & PIN
3589 ShellPrintHiiEx(-1, -1, NULL
,
3590 STRING_TOKEN (STR_PCI2_INTERRUPT_LINE_2
),
3591 gShellDebug1HiiHandle
,
3592 INDEX_OF (&(Bridge
->InterruptLine
)),
3593 Bridge
->InterruptLine
3596 ShellPrintHiiEx(-1, -1, NULL
,
3597 STRING_TOKEN (STR_PCI2_INTERRUPT_PIN
),
3598 gShellDebug1HiiHandle
,
3599 INDEX_OF (&(Bridge
->InterruptPin
)),
3600 Bridge
->InterruptPin
3607 Explain the Base Address Register(Bar) in PCI configuration space.
3609 @param[in] Bar Points to the Base Address Register intended to interpret.
3610 @param[in] Command Points to the register Command.
3611 @param[in] Address Address used to access configuration space of this PCI device.
3612 @param[in] IoDev Handle used to access configuration space of PCI device.
3613 @param[in, out] Index The Index.
3615 @retval EFI_SUCCESS The command completed successfully.
3622 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
,
3643 // According the bar type, list detail about this bar, for example: 32 or
3644 // 64 bits; pre-fetchable or not.
3646 if ((*Bar
& PCI_BIT_0
) == 0) {
3648 // This bar is of memory type
3652 if ((*Bar
& PCI_BIT_1
) == 0 && (*Bar
& PCI_BIT_2
) == 0) {
3653 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_BAR
), gShellDebug1HiiHandle
, *Bar
& 0xfffffff0);
3654 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_MEM
), gShellDebug1HiiHandle
);
3655 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_32_BITS
), gShellDebug1HiiHandle
);
3657 } else if ((*Bar
& PCI_BIT_1
) == 0 && (*Bar
& PCI_BIT_2
) != 0) {
3659 CopyMem (&Bar64
, Bar
, sizeof (UINT64
));
3660 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_ONE_VAR_2
), gShellDebug1HiiHandle
, (UINT32
) RShiftU64 ((Bar64
& 0xfffffffffffffff0ULL
), 32));
3661 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_ONE_VAR_3
), gShellDebug1HiiHandle
, (UINT32
) (Bar64
& 0xfffffffffffffff0ULL
));
3662 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_MEM
), gShellDebug1HiiHandle
);
3663 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_64_BITS
), gShellDebug1HiiHandle
);
3671 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_BAR
), gShellDebug1HiiHandle
, *Bar
& 0xfffffff0);
3672 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_MEM_2
), gShellDebug1HiiHandle
);
3675 if ((*Bar
& PCI_BIT_3
) == 0) {
3676 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_NO
), gShellDebug1HiiHandle
);
3679 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_YES
), gShellDebug1HiiHandle
);
3684 // This bar is of io type
3687 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_ONE_VAR_4
), gShellDebug1HiiHandle
, *Bar
& 0xfffffffc);
3688 ShellPrintEx (-1, -1, L
"I/O ");
3692 // Get BAR length(or the amount of resource this bar demands for). To get
3693 // Bar length, first we should temporarily disable I/O and memory access
3694 // of this function(by set bits in the register Command), then write all
3695 // "1"s to this bar. The bar value read back is the amount of resource
3696 // this bar demands for.
3699 // Disable io & mem access
3701 OldCommand
= *Command
;
3702 NewCommand
= (UINT16
) (OldCommand
& 0xfffc);
3703 RegAddress
= Address
| INDEX_OF (Command
);
3704 IoDev
->Pci
.Write (IoDev
, EfiPciWidthUint16
, RegAddress
, 1, &NewCommand
);
3706 RegAddress
= Address
| INDEX_OF (Bar
);
3709 // Read after write the BAR to get the size
3713 NewBar32
= 0xffffffff;
3715 IoDev
->Pci
.Write (IoDev
, EfiPciWidthUint32
, RegAddress
, 1, &NewBar32
);
3716 IoDev
->Pci
.Read (IoDev
, EfiPciWidthUint32
, RegAddress
, 1, &NewBar32
);
3717 IoDev
->Pci
.Write (IoDev
, EfiPciWidthUint32
, RegAddress
, 1, &OldBar32
);
3720 NewBar32
= NewBar32
& 0xfffffff0;
3721 NewBar32
= (~NewBar32
) + 1;
3724 NewBar32
= NewBar32
& 0xfffffffc;
3725 NewBar32
= (~NewBar32
) + 1;
3726 NewBar32
= NewBar32
& 0x0000ffff;
3731 CopyMem (&OldBar64
, Bar
, sizeof (UINT64
));
3732 NewBar64
= 0xffffffffffffffffULL
;
3734 IoDev
->Pci
.Write (IoDev
, EfiPciWidthUint32
, RegAddress
, 2, &NewBar64
);
3735 IoDev
->Pci
.Read (IoDev
, EfiPciWidthUint32
, RegAddress
, 2, &NewBar64
);
3736 IoDev
->Pci
.Write (IoDev
, EfiPciWidthUint32
, RegAddress
, 2, &OldBar64
);
3739 NewBar64
= NewBar64
& 0xfffffffffffffff0ULL
;
3740 NewBar64
= (~NewBar64
) + 1;
3743 NewBar64
= NewBar64
& 0xfffffffffffffffcULL
;
3744 NewBar64
= (~NewBar64
) + 1;
3745 NewBar64
= NewBar64
& 0x000000000000ffff;
3749 // Enable io & mem access
3751 RegAddress
= Address
| INDEX_OF (Command
);
3752 IoDev
->Pci
.Write (IoDev
, EfiPciWidthUint16
, RegAddress
, 1, &OldCommand
);
3756 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_NEWBAR_32
), gShellDebug1HiiHandle
, NewBar32
);
3757 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_NEWBAR_32_2
), gShellDebug1HiiHandle
, NewBar32
+ (*Bar
& 0xfffffff0) - 1);
3760 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_RSHIFT
), gShellDebug1HiiHandle
, (UINT32
) RShiftU64 (NewBar64
, 32));
3761 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_RSHIFT
), gShellDebug1HiiHandle
, (UINT32
) NewBar64
);
3762 ShellPrintEx (-1, -1, L
" ");
3763 ShellPrintHiiEx(-1, -1, NULL
,
3764 STRING_TOKEN (STR_PCI2_RSHIFT
),
3765 gShellDebug1HiiHandle
,
3766 (UINT32
) RShiftU64 ((NewBar64
+ (Bar64
& 0xfffffffffffffff0ULL
) - 1), 32)
3768 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_RSHIFT
), gShellDebug1HiiHandle
, (UINT32
) (NewBar64
+ (Bar64
& 0xfffffffffffffff0ULL
) - 1));
3772 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_NEWBAR_32_3
), gShellDebug1HiiHandle
, NewBar32
);
3773 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_NEWBAR_32_4
), gShellDebug1HiiHandle
, NewBar32
+ (*Bar
& 0xfffffffc) - 1);
3780 Explain the cardbus specific part of data in PCI configuration space.
3782 @param[in] CardBus CardBus specific region of PCI configuration space.
3783 @param[in] Address Address used to access configuration space of this PCI device.
3784 @param[in] IoDev Handle used to access configuration space of PCI device.
3786 @retval EFI_SUCCESS The command completed successfully.
3789 PciExplainCardBusData (
3790 IN PCI_CARDBUS_HEADER
*CardBus
,
3792 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
3796 PCI_CARDBUS_DATA
*CardBusData
;
3798 ShellPrintHiiEx(-1, -1, NULL
,
3799 STRING_TOKEN (STR_PCI2_CARDBUS_SOCKET
),
3800 gShellDebug1HiiHandle
,
3801 INDEX_OF (&(CardBus
->CardBusSocketReg
)),
3802 CardBus
->CardBusSocketReg
3806 // Print Secondary Status
3808 PciExplainStatus (&(CardBus
->SecondaryStatus
), FALSE
, PciCardBusBridge
);
3811 // Print Bus Numbers(Primary bus number, CardBus bus number, and
3812 // Subordinate bus number
3814 ShellPrintHiiEx(-1, -1, NULL
,
3815 STRING_TOKEN (STR_PCI2_BUS_NUMBERS_2
),
3816 gShellDebug1HiiHandle
,
3817 INDEX_OF (&(CardBus
->PciBusNumber
)),
3818 INDEX_OF (&(CardBus
->CardBusBusNumber
)),
3819 INDEX_OF (&(CardBus
->SubordinateBusNumber
))
3822 ShellPrintEx (-1, -1, L
" ------------------------------------------------------\r\n");
3824 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_CARDBUS
), gShellDebug1HiiHandle
, CardBus
->PciBusNumber
);
3825 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_CARDBUS_2
), gShellDebug1HiiHandle
, CardBus
->CardBusBusNumber
);
3826 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_CARDBUS_3
), gShellDebug1HiiHandle
, CardBus
->SubordinateBusNumber
);
3829 // Print CardBus Latency Timer
3831 ShellPrintHiiEx(-1, -1, NULL
,
3832 STRING_TOKEN (STR_PCI2_CARDBUS_LATENCY
),
3833 gShellDebug1HiiHandle
,
3834 INDEX_OF (&(CardBus
->CardBusLatencyTimer
)),
3835 CardBus
->CardBusLatencyTimer
3839 // Print Memory/Io ranges this cardbus bridge forwards
3841 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_RESOURCE_TYPE_2
), gShellDebug1HiiHandle
);
3842 ShellPrintEx (-1, -1, L
"----------------------------------------------------------------------\r\n");
3844 ShellPrintHiiEx(-1, -1, NULL
,
3845 STRING_TOKEN (STR_PCI2_MEM_3
),
3846 gShellDebug1HiiHandle
,
3847 INDEX_OF (&(CardBus
->MemoryBase0
)),
3848 CardBus
->BridgeControl
& PCI_BIT_8
? L
" Prefetchable" : L
"Non-Prefetchable",
3849 CardBus
->MemoryBase0
& 0xfffff000,
3850 CardBus
->MemoryLimit0
| 0x00000fff
3853 ShellPrintHiiEx(-1, -1, NULL
,
3854 STRING_TOKEN (STR_PCI2_MEM_3
),
3855 gShellDebug1HiiHandle
,
3856 INDEX_OF (&(CardBus
->MemoryBase1
)),
3857 CardBus
->BridgeControl
& PCI_BIT_9
? L
" Prefetchable" : L
"Non-Prefetchable",
3858 CardBus
->MemoryBase1
& 0xfffff000,
3859 CardBus
->MemoryLimit1
| 0x00000fff
3862 Io32Bit
= (BOOLEAN
) (CardBus
->IoBase0
& PCI_BIT_0
);
3863 ShellPrintHiiEx(-1, -1, NULL
,
3864 STRING_TOKEN (STR_PCI2_IO_2
),
3865 gShellDebug1HiiHandle
,
3866 INDEX_OF (&(CardBus
->IoBase0
)),
3867 Io32Bit
? L
" 32 bit" : L
" 16 bit",
3868 CardBus
->IoBase0
& (Io32Bit
? 0xfffffffc : 0x0000fffc),
3869 (CardBus
->IoLimit0
& (Io32Bit
? 0xffffffff : 0x0000ffff)) | 0x00000003
3872 Io32Bit
= (BOOLEAN
) (CardBus
->IoBase1
& PCI_BIT_0
);
3873 ShellPrintHiiEx(-1, -1, NULL
,
3874 STRING_TOKEN (STR_PCI2_IO_2
),
3875 gShellDebug1HiiHandle
,
3876 INDEX_OF (&(CardBus
->IoBase1
)),
3877 Io32Bit
? L
" 32 bit" : L
" 16 bit",
3878 CardBus
->IoBase1
& (Io32Bit
? 0xfffffffc : 0x0000fffc),
3879 (CardBus
->IoLimit1
& (Io32Bit
? 0xffffffff : 0x0000ffff)) | 0x00000003
3883 // Print register Interrupt Line & PIN
3885 ShellPrintHiiEx(-1, -1, NULL
,
3886 STRING_TOKEN (STR_PCI2_INTERRUPT_LINE_3
),
3887 gShellDebug1HiiHandle
,
3888 INDEX_OF (&(CardBus
->InterruptLine
)),
3889 CardBus
->InterruptLine
,
3890 INDEX_OF (&(CardBus
->InterruptPin
)),
3891 CardBus
->InterruptPin
3895 // Print register Bridge Control
3897 PciExplainBridgeControl (&(CardBus
->BridgeControl
), PciCardBusBridge
);
3900 // Print some registers in data region of PCI configuration space for cardbus
3901 // bridge. Fields include: Sub VendorId, Subsystem ID, and Legacy Mode Base
3904 CardBusData
= (PCI_CARDBUS_DATA
*) ((UINT8
*) CardBus
+ sizeof (PCI_CARDBUS_HEADER
));
3906 ShellPrintHiiEx(-1, -1, NULL
,
3907 STRING_TOKEN (STR_PCI2_SUB_VENDOR_ID_2
),
3908 gShellDebug1HiiHandle
,
3909 INDEX_OF (&(CardBusData
->SubVendorId
)),
3910 CardBusData
->SubVendorId
,
3911 INDEX_OF (&(CardBusData
->SubSystemId
)),
3912 CardBusData
->SubSystemId
3915 ShellPrintHiiEx(-1, -1, NULL
,
3916 STRING_TOKEN (STR_PCI2_OPTIONAL
),
3917 gShellDebug1HiiHandle
,
3918 INDEX_OF (&(CardBusData
->LegacyBase
)),
3919 CardBusData
->LegacyBase
3926 Explain each meaningful bit of register Status. The definition of Status is
3927 slightly different depending on the PCI header type.
3929 @param[in] Status Points to the content of register Status.
3930 @param[in] MainStatus Indicates if this register is main status(not secondary
3932 @param[in] HeaderType Header type of this PCI device.
3934 @retval EFI_SUCCESS The command completed successfully.
3939 IN BOOLEAN MainStatus
,
3940 IN PCI_HEADER_TYPE HeaderType
3944 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_STATUS
), gShellDebug1HiiHandle
, INDEX_OF (Status
), *Status
);
3947 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_SECONDARY_STATUS
), gShellDebug1HiiHandle
, INDEX_OF (Status
), *Status
);
3950 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_NEW_CAPABILITIES
), gShellDebug1HiiHandle
, (*Status
& PCI_BIT_4
) != 0);
3953 // Bit 5 is meaningless for CardBus Bridge
3955 if (HeaderType
== PciCardBusBridge
) {
3956 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_66_CAPABLE
), gShellDebug1HiiHandle
, (*Status
& PCI_BIT_5
) != 0);
3959 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_66_CAPABLE_2
), gShellDebug1HiiHandle
, (*Status
& PCI_BIT_5
) != 0);
3962 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_FAST_BACK
), gShellDebug1HiiHandle
, (*Status
& PCI_BIT_7
) != 0);
3964 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_MASTER_DATA
), gShellDebug1HiiHandle
, (*Status
& PCI_BIT_8
) != 0);
3966 // Bit 9 and bit 10 together decides the DEVSEL timing
3968 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_DEVSEL_TIMING
), gShellDebug1HiiHandle
);
3969 if ((*Status
& PCI_BIT_9
) == 0 && (*Status
& PCI_BIT_10
) == 0) {
3970 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_FAST
), gShellDebug1HiiHandle
);
3972 } else if ((*Status
& PCI_BIT_9
) != 0 && (*Status
& PCI_BIT_10
) == 0) {
3973 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_MEDIUM
), gShellDebug1HiiHandle
);
3975 } else if ((*Status
& PCI_BIT_9
) == 0 && (*Status
& PCI_BIT_10
) != 0) {
3976 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_SLOW
), gShellDebug1HiiHandle
);
3979 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_RESERVED_2
), gShellDebug1HiiHandle
);
3982 ShellPrintHiiEx(-1, -1, NULL
,
3983 STRING_TOKEN (STR_PCI2_SIGNALED_TARGET
),
3984 gShellDebug1HiiHandle
,
3985 (*Status
& PCI_BIT_11
) != 0
3988 ShellPrintHiiEx(-1, -1, NULL
,
3989 STRING_TOKEN (STR_PCI2_RECEIVED_TARGET
),
3990 gShellDebug1HiiHandle
,
3991 (*Status
& PCI_BIT_12
) != 0
3994 ShellPrintHiiEx(-1, -1, NULL
,
3995 STRING_TOKEN (STR_PCI2_RECEIVED_MASTER
),
3996 gShellDebug1HiiHandle
,
3997 (*Status
& PCI_BIT_13
) != 0
4001 ShellPrintHiiEx(-1, -1, NULL
,
4002 STRING_TOKEN (STR_PCI2_SIGNALED_ERROR
),
4003 gShellDebug1HiiHandle
,
4004 (*Status
& PCI_BIT_14
) != 0
4008 ShellPrintHiiEx(-1, -1, NULL
,
4009 STRING_TOKEN (STR_PCI2_RECEIVED_ERROR
),
4010 gShellDebug1HiiHandle
,
4011 (*Status
& PCI_BIT_14
) != 0
4015 ShellPrintHiiEx(-1, -1, NULL
,
4016 STRING_TOKEN (STR_PCI2_DETECTED_ERROR
),
4017 gShellDebug1HiiHandle
,
4018 (*Status
& PCI_BIT_15
) != 0
4025 Explain each meaningful bit of register Command.
4027 @param[in] Command Points to the content of register Command.
4029 @retval EFI_SUCCESS The command completed successfully.
4037 // Print the binary value of register Command
4039 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_COMMAND
), gShellDebug1HiiHandle
, INDEX_OF (Command
), *Command
);
4042 // Explain register Command bit by bit
4044 ShellPrintHiiEx(-1, -1, NULL
,
4045 STRING_TOKEN (STR_PCI2_SPACE_ACCESS_DENIED
),
4046 gShellDebug1HiiHandle
,
4047 (*Command
& PCI_BIT_0
) != 0
4050 ShellPrintHiiEx(-1, -1, NULL
,
4051 STRING_TOKEN (STR_PCI2_MEMORY_SPACE
),
4052 gShellDebug1HiiHandle
,
4053 (*Command
& PCI_BIT_1
) != 0
4056 ShellPrintHiiEx(-1, -1, NULL
,
4057 STRING_TOKEN (STR_PCI2_BEHAVE_BUS_MASTER
),
4058 gShellDebug1HiiHandle
,
4059 (*Command
& PCI_BIT_2
) != 0
4062 ShellPrintHiiEx(-1, -1, NULL
,
4063 STRING_TOKEN (STR_PCI2_MONITOR_SPECIAL_CYCLE
),
4064 gShellDebug1HiiHandle
,
4065 (*Command
& PCI_BIT_3
) != 0
4068 ShellPrintHiiEx(-1, -1, NULL
,
4069 STRING_TOKEN (STR_PCI2_MEM_WRITE_INVALIDATE
),
4070 gShellDebug1HiiHandle
,
4071 (*Command
& PCI_BIT_4
) != 0
4074 ShellPrintHiiEx(-1, -1, NULL
,
4075 STRING_TOKEN (STR_PCI2_PALETTE_SNOOPING
),
4076 gShellDebug1HiiHandle
,
4077 (*Command
& PCI_BIT_5
) != 0
4080 ShellPrintHiiEx(-1, -1, NULL
,
4081 STRING_TOKEN (STR_PCI2_ASSERT_PERR
),
4082 gShellDebug1HiiHandle
,
4083 (*Command
& PCI_BIT_6
) != 0
4086 ShellPrintHiiEx(-1, -1, NULL
,
4087 STRING_TOKEN (STR_PCI2_DO_ADDR_STEPPING
),
4088 gShellDebug1HiiHandle
,
4089 (*Command
& PCI_BIT_7
) != 0
4092 ShellPrintHiiEx(-1, -1, NULL
,
4093 STRING_TOKEN (STR_PCI2_SERR_DRIVER
),
4094 gShellDebug1HiiHandle
,
4095 (*Command
& PCI_BIT_8
) != 0
4098 ShellPrintHiiEx(-1, -1, NULL
,
4099 STRING_TOKEN (STR_PCI2_FAST_BACK_2
),
4100 gShellDebug1HiiHandle
,
4101 (*Command
& PCI_BIT_9
) != 0
4108 Explain each meaningful bit of register Bridge Control.
4110 @param[in] BridgeControl Points to the content of register Bridge Control.
4111 @param[in] HeaderType The headertype.
4113 @retval EFI_SUCCESS The command completed successfully.
4116 PciExplainBridgeControl (
4117 IN UINT16
*BridgeControl
,
4118 IN PCI_HEADER_TYPE HeaderType
4121 ShellPrintHiiEx(-1, -1, NULL
,
4122 STRING_TOKEN (STR_PCI2_BRIDGE_CONTROL
),
4123 gShellDebug1HiiHandle
,
4124 INDEX_OF (BridgeControl
),
4128 ShellPrintHiiEx(-1, -1, NULL
,
4129 STRING_TOKEN (STR_PCI2_PARITY_ERROR
),
4130 gShellDebug1HiiHandle
,
4131 (*BridgeControl
& PCI_BIT_0
) != 0
4133 ShellPrintHiiEx(-1, -1, NULL
,
4134 STRING_TOKEN (STR_PCI2_SERR_ENABLE
),
4135 gShellDebug1HiiHandle
,
4136 (*BridgeControl
& PCI_BIT_1
) != 0
4138 ShellPrintHiiEx(-1, -1, NULL
,
4139 STRING_TOKEN (STR_PCI2_ISA_ENABLE
),
4140 gShellDebug1HiiHandle
,
4141 (*BridgeControl
& PCI_BIT_2
) != 0
4143 ShellPrintHiiEx(-1, -1, NULL
,
4144 STRING_TOKEN (STR_PCI2_VGA_ENABLE
),
4145 gShellDebug1HiiHandle
,
4146 (*BridgeControl
& PCI_BIT_3
) != 0
4148 ShellPrintHiiEx(-1, -1, NULL
,
4149 STRING_TOKEN (STR_PCI2_MASTER_ABORT
),
4150 gShellDebug1HiiHandle
,
4151 (*BridgeControl
& PCI_BIT_5
) != 0
4155 // Register Bridge Control has some slight differences between P2P bridge
4156 // and Cardbus bridge from bit 6 to bit 11.
4158 if (HeaderType
== PciP2pBridge
) {
4159 ShellPrintHiiEx(-1, -1, NULL
,
4160 STRING_TOKEN (STR_PCI2_SECONDARY_BUS_RESET
),
4161 gShellDebug1HiiHandle
,
4162 (*BridgeControl
& PCI_BIT_6
) != 0
4164 ShellPrintHiiEx(-1, -1, NULL
,
4165 STRING_TOKEN (STR_PCI2_FAST_ENABLE
),
4166 gShellDebug1HiiHandle
,
4167 (*BridgeControl
& PCI_BIT_7
) != 0
4169 ShellPrintHiiEx(-1, -1, NULL
,
4170 STRING_TOKEN (STR_PCI2_PRIMARY_DISCARD_TIMER
),
4171 gShellDebug1HiiHandle
,
4172 (*BridgeControl
& PCI_BIT_8
)!=0 ? L
"2^10" : L
"2^15"
4174 ShellPrintHiiEx(-1, -1, NULL
,
4175 STRING_TOKEN (STR_PCI2_SECONDARY_DISCARD_TIMER
),
4176 gShellDebug1HiiHandle
,
4177 (*BridgeControl
& PCI_BIT_9
)!=0 ? L
"2^10" : L
"2^15"
4179 ShellPrintHiiEx(-1, -1, NULL
,
4180 STRING_TOKEN (STR_PCI2_DISCARD_TIMER_STATUS
),
4181 gShellDebug1HiiHandle
,
4182 (*BridgeControl
& PCI_BIT_10
) != 0
4184 ShellPrintHiiEx(-1, -1, NULL
,
4185 STRING_TOKEN (STR_PCI2_DISCARD_TIMER_SERR
),
4186 gShellDebug1HiiHandle
,
4187 (*BridgeControl
& PCI_BIT_11
) != 0
4191 ShellPrintHiiEx(-1, -1, NULL
,
4192 STRING_TOKEN (STR_PCI2_CARDBUS_RESET
),
4193 gShellDebug1HiiHandle
,
4194 (*BridgeControl
& PCI_BIT_6
) != 0
4196 ShellPrintHiiEx(-1, -1, NULL
,
4197 STRING_TOKEN (STR_PCI2_IREQ_ENABLE
),
4198 gShellDebug1HiiHandle
,
4199 (*BridgeControl
& PCI_BIT_7
) != 0
4201 ShellPrintHiiEx(-1, -1, NULL
,
4202 STRING_TOKEN (STR_PCI2_WRITE_POSTING_ENABLE
),
4203 gShellDebug1HiiHandle
,
4204 (*BridgeControl
& PCI_BIT_10
) != 0
4212 Print each capability structure.
4214 @param[in] IoDev The pointer to the deivce.
4215 @param[in] Address The address to start at.
4216 @param[in] CapPtr The offset from the address.
4217 @param[in] EnhancedDump The print format for the dump data.
4219 @retval EFI_SUCCESS The operation was successful.
4222 PciExplainCapabilityStruct (
4223 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
,
4226 IN CONST UINT16 EnhancedDump
4229 UINT8 CapabilityPtr
;
4230 UINT16 CapabilityEntry
;
4234 CapabilityPtr
= CapPtr
;
4237 // Go through the Capability list
4239 while ((CapabilityPtr
>= 0x40) && ((CapabilityPtr
& 0x03) == 0x00)) {
4240 RegAddress
= Address
+ CapabilityPtr
;
4241 IoDev
->Pci
.Read (IoDev
, EfiPciWidthUint16
, RegAddress
, 1, &CapabilityEntry
);
4243 CapabilityID
= (UINT8
) CapabilityEntry
;
4246 // Explain PciExpress data
4248 if (EFI_PCI_CAPABILITY_ID_PCIEXP
== CapabilityID
) {
4249 PciExplainPciExpress (IoDev
, Address
, CapabilityPtr
, EnhancedDump
);
4253 // Explain other capabilities here
4255 CapabilityPtr
= (UINT8
) (CapabilityEntry
>> 8);
4262 Print out information of the capability information.
4264 @param[in] PciExpressCap The pointer to the structure about the device.
4266 @retval EFI_SUCCESS The operation was successful.
4270 IN PCIE_CAP_STRUCTURE
*PciExpressCap
4274 CHAR16
*DevicePortType
;
4276 PcieCapReg
= PciExpressCap
->PcieCapReg
;
4277 ShellPrintEx (-1, -1,
4278 L
" Capability Version(3:0): %E0x%04x%N\r\n",
4279 PCIE_CAP_VERSION (PcieCapReg
)
4281 if ((UINT8
) PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg
) < PCIE_DEVICE_PORT_TYPE_MAX
) {
4282 DevicePortType
= DevicePortTypeTable
[PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg
)];
4284 DevicePortType
= L
"Unknown Type";
4286 ShellPrintEx (-1, -1,
4287 L
" Device/PortType(7:4): %E%s%N\r\n",
4291 // 'Slot Implemented' is only valid for:
4292 // a) Root Port of PCI Express Root Complex, or
4293 // b) Downstream Port of PCI Express Switch
4295 if (PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg
) == PCIE_ROOT_COMPLEX_ROOT_PORT
||
4296 PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg
) == PCIE_SWITCH_DOWNSTREAM_PORT
) {
4297 ShellPrintEx (-1, -1,
4298 L
" Slot Implemented(8): %E%d%N\r\n",
4299 PCIE_CAP_SLOT_IMPLEMENTED (PcieCapReg
)
4302 ShellPrintEx (-1, -1,
4303 L
" Interrupt Message Number(13:9): %E0x%05x%N\r\n",
4304 PCIE_CAP_INT_MSG_NUM (PcieCapReg
)
4310 Print out information of the device capability information.
4312 @param[in] PciExpressCap The pointer to the structure about the device.
4314 @retval EFI_SUCCESS The operation was successful.
4317 ExplainPcieDeviceCap (
4318 IN PCIE_CAP_STRUCTURE
*PciExpressCap
4322 UINT32 PcieDeviceCap
;
4323 UINT8 DevicePortType
;
4327 PcieCapReg
= PciExpressCap
->PcieCapReg
;
4328 PcieDeviceCap
= PciExpressCap
->PcieDeviceCap
;
4329 DevicePortType
= (UINT8
) PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg
);
4330 ShellPrintEx (-1, -1, L
" Max_Payload_Size Supported(2:0): ");
4331 if (PCIE_CAP_MAX_PAYLOAD (PcieDeviceCap
) < 6) {
4332 ShellPrintEx (-1, -1, L
"%E%d bytes%N\r\n", 1 << (PCIE_CAP_MAX_PAYLOAD (PcieDeviceCap
) + 7));
4334 ShellPrintEx (-1, -1, L
"%EUnknown%N\r\n");
4336 ShellPrintEx (-1, -1,
4337 L
" Phantom Functions Supported(4:3): %E%d%N\r\n",
4338 PCIE_CAP_PHANTOM_FUNC (PcieDeviceCap
)
4340 ShellPrintEx (-1, -1,
4341 L
" Extended Tag Field Supported(5): %E%d-bit Tag field supported%N\r\n",
4342 PCIE_CAP_EXTENDED_TAG (PcieDeviceCap
) ? 8 : 5
4345 // Endpoint L0s and L1 Acceptable Latency is only valid for Endpoint
4347 if (IS_PCIE_ENDPOINT (DevicePortType
)) {
4348 L0sLatency
= (UINT8
) PCIE_CAP_L0SLATENCY (PcieDeviceCap
);
4349 L1Latency
= (UINT8
) PCIE_CAP_L1LATENCY (PcieDeviceCap
);
4350 ShellPrintEx (-1, -1, L
" Endpoint L0s Acceptable Latency(8:6): ");
4351 if (L0sLatency
< 4) {
4352 ShellPrintEx (-1, -1, L
"%EMaximum of %d ns%N\r\n", 1 << (L0sLatency
+ 6));
4354 if (L0sLatency
< 7) {
4355 ShellPrintEx (-1, -1, L
"%EMaximum of %d us%N\r\n", 1 << (L0sLatency
- 3));
4357 ShellPrintEx (-1, -1, L
"%ENo limit%N\r\n");
4360 ShellPrintEx (-1, -1, L
" Endpoint L1 Acceptable Latency(11:9): ");
4361 if (L1Latency
< 7) {
4362 ShellPrintEx (-1, -1, L
"%EMaximum of %d us%N\r\n", 1 << (L1Latency
+ 1));
4364 ShellPrintEx (-1, -1, L
"%ENo limit%N\r\n");
4367 ShellPrintEx (-1, -1,
4368 L
" Role-based Error Reporting(15): %E%d%N\r\n",
4369 PCIE_CAP_ERR_REPORTING (PcieDeviceCap
)
4372 // Only valid for Upstream Port:
4373 // a) Captured Slot Power Limit Value
4374 // b) Captured Slot Power Scale
4376 if (DevicePortType
== PCIE_SWITCH_UPSTREAM_PORT
) {
4377 ShellPrintEx (-1, -1,
4378 L
" Captured Slot Power Limit Value(25:18): %E0x%02x%N\r\n",
4379 PCIE_CAP_SLOT_POWER_VALUE (PcieDeviceCap
)
4381 ShellPrintEx (-1, -1,
4382 L
" Captured Slot Power Limit Scale(27:26): %E%s%N\r\n",
4383 SlotPwrLmtScaleTable
[PCIE_CAP_SLOT_POWER_SCALE (PcieDeviceCap
)]
4387 // Function Level Reset Capability is only valid for Endpoint
4389 if (IS_PCIE_ENDPOINT (DevicePortType
)) {
4390 ShellPrintEx (-1, -1,
4391 L
" Function Level Reset Capability(28): %E%d%N\r\n",
4392 PCIE_CAP_FUNC_LEVEL_RESET (PcieDeviceCap
)
4399 Print out information of the device control information.
4401 @param[in] PciExpressCap The pointer to the structure about the device.
4403 @retval EFI_SUCCESS The operation was successful.
4406 ExplainPcieDeviceControl (
4407 IN PCIE_CAP_STRUCTURE
*PciExpressCap
4411 UINT16 PcieDeviceControl
;
4413 PcieCapReg
= PciExpressCap
->PcieCapReg
;
4414 PcieDeviceControl
= PciExpressCap
->DeviceControl
;
4415 ShellPrintEx (-1, -1,
4416 L
" Correctable Error Reporting Enable(0): %E%d%N\r\n",
4417 PCIE_CAP_COR_ERR_REPORTING_ENABLE (PcieDeviceControl
)
4419 ShellPrintEx (-1, -1,
4420 L
" Non-Fatal Error Reporting Enable(1): %E%d%N\r\n",
4421 PCIE_CAP_NONFAT_ERR_REPORTING_ENABLE (PcieDeviceControl
)
4423 ShellPrintEx (-1, -1,
4424 L
" Fatal Error Reporting Enable(2): %E%d%N\r\n",
4425 PCIE_CAP_FATAL_ERR_REPORTING_ENABLE (PcieDeviceControl
)
4427 ShellPrintEx (-1, -1,
4428 L
" Unsupported Request Reporting Enable(3): %E%d%N\r\n",
4429 PCIE_CAP_UNSUP_REQ_REPORTING_ENABLE (PcieDeviceControl
)
4431 ShellPrintEx (-1, -1,
4432 L
" Enable Relaxed Ordering(4): %E%d%N\r\n",
4433 PCIE_CAP_RELAXED_ORDERING_ENABLE (PcieDeviceControl
)
4435 ShellPrintEx (-1, -1, L
" Max_Payload_Size(7:5): ");
4436 if (PCIE_CAP_MAX_PAYLOAD_SIZE (PcieDeviceControl
) < 6) {
4437 ShellPrintEx (-1, -1, L
"%E%d bytes%N\r\n", 1 << (PCIE_CAP_MAX_PAYLOAD_SIZE (PcieDeviceControl
) + 7));
4439 ShellPrintEx (-1, -1, L
"%EUnknown%N\r\n");
4441 ShellPrintEx (-1, -1,
4442 L
" Extended Tag Field Enable(8): %E%d%N\r\n",
4443 PCIE_CAP_EXTENDED_TAG_ENABLE (PcieDeviceControl
)
4445 ShellPrintEx (-1, -1,
4446 L
" Phantom Functions Enable(9): %E%d%N\r\n",
4447 PCIE_CAP_PHANTOM_FUNC_ENABLE (PcieDeviceControl
)
4449 ShellPrintEx (-1, -1,
4450 L
" Auxiliary (AUX) Power PM Enable(10): %E%d%N\r\n",
4451 PCIE_CAP_AUX_PM_ENABLE (PcieDeviceControl
)
4453 ShellPrintEx (-1, -1,
4454 L
" Enable No Snoop(11): %E%d%N\r\n",
4455 PCIE_CAP_NO_SNOOP_ENABLE (PcieDeviceControl
)
4457 ShellPrintEx (-1, -1, L
" Max_Read_Request_Size(14:12): ");
4458 if (PCIE_CAP_MAX_READ_REQ_SIZE (PcieDeviceControl
) < 6) {
4459 ShellPrintEx (-1, -1, L
"%E%d bytes%N\r\n", 1 << (PCIE_CAP_MAX_READ_REQ_SIZE (PcieDeviceControl
) + 7));
4461 ShellPrintEx (-1, -1, L
"%EUnknown%N\r\n");
4464 // Read operation is only valid for PCI Express to PCI/PCI-X Bridges
4466 if (PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg
) == PCIE_PCIE_TO_PCIX_BRIDGE
) {
4467 ShellPrintEx (-1, -1,
4468 L
" Bridge Configuration Retry Enable(15): %E%d%N\r\n",
4469 PCIE_CAP_BRG_CONF_RETRY (PcieDeviceControl
)
4476 Print out information of the device status information.
4478 @param[in] PciExpressCap The pointer to the structure about the device.
4480 @retval EFI_SUCCESS The operation was successful.
4483 ExplainPcieDeviceStatus (
4484 IN PCIE_CAP_STRUCTURE
*PciExpressCap
4487 UINT16 PcieDeviceStatus
;
4489 PcieDeviceStatus
= PciExpressCap
->DeviceStatus
;
4490 ShellPrintEx (-1, -1,
4491 L
" Correctable Error Detected(0): %E%d%N\r\n",
4492 PCIE_CAP_COR_ERR_DETECTED (PcieDeviceStatus
)
4494 ShellPrintEx (-1, -1,
4495 L
" Non-Fatal Error Detected(1): %E%d%N\r\n",
4496 PCIE_CAP_NONFAT_ERR_DETECTED (PcieDeviceStatus
)
4498 ShellPrintEx (-1, -1,
4499 L
" Fatal Error Detected(2): %E%d%N\r\n",
4500 PCIE_CAP_FATAL_ERR_DETECTED (PcieDeviceStatus
)
4502 ShellPrintEx (-1, -1,
4503 L
" Unsupported Request Detected(3): %E%d%N\r\n",
4504 PCIE_CAP_UNSUP_REQ_DETECTED (PcieDeviceStatus
)
4506 ShellPrintEx (-1, -1,
4507 L
" AUX Power Detected(4): %E%d%N\r\n",
4508 PCIE_CAP_AUX_POWER_DETECTED (PcieDeviceStatus
)
4510 ShellPrintEx (-1, -1,
4511 L
" Transactions Pending(5): %E%d%N\r\n",
4512 PCIE_CAP_TRANSACTION_PENDING (PcieDeviceStatus
)
4518 Print out information of the device link information.
4520 @param[in] PciExpressCap The pointer to the structure about the device.
4522 @retval EFI_SUCCESS The operation was successful.
4525 ExplainPcieLinkCap (
4526 IN PCIE_CAP_STRUCTURE
*PciExpressCap
4530 CHAR16
*MaxLinkSpeed
;
4533 PcieLinkCap
= PciExpressCap
->LinkCap
;
4534 switch (PCIE_CAP_MAX_LINK_SPEED (PcieLinkCap
)) {
4536 MaxLinkSpeed
= L
"2.5 GT/s";
4539 MaxLinkSpeed
= L
"5.0 GT/s";
4542 MaxLinkSpeed
= L
"8.0 GT/s";
4545 MaxLinkSpeed
= L
"Unknown";
4548 ShellPrintEx (-1, -1,
4549 L
" Maximum Link Speed(3:0): %E%s%N\r\n",
4552 ShellPrintEx (-1, -1,
4553 L
" Maximum Link Width(9:4): %Ex%d%N\r\n",
4554 PCIE_CAP_MAX_LINK_WIDTH (PcieLinkCap
)
4556 switch (PCIE_CAP_ASPM_SUPPORT (PcieLinkCap
)) {
4567 AspmValue
= L
"L0s and L1";
4570 AspmValue
= L
"Reserved";
4573 ShellPrintEx (-1, -1,
4574 L
" Active State Power Management Support(11:10): %E%s Supported%N\r\n",
4577 ShellPrintEx (-1, -1,
4578 L
" L0s Exit Latency(14:12): %E%s%N\r\n",
4579 L0sLatencyStrTable
[PCIE_CAP_L0S_LATENCY (PcieLinkCap
)]
4581 ShellPrintEx (-1, -1,
4582 L
" L1 Exit Latency(17:15): %E%s%N\r\n",
4583 L1LatencyStrTable
[PCIE_CAP_L0S_LATENCY (PcieLinkCap
)]
4585 ShellPrintEx (-1, -1,
4586 L
" Clock Power Management(18): %E%d%N\r\n",
4587 PCIE_CAP_CLOCK_PM (PcieLinkCap
)
4589 ShellPrintEx (-1, -1,
4590 L
" Surprise Down Error Reporting Capable(19): %E%d%N\r\n",
4591 PCIE_CAP_SUP_DOWN_ERR_REPORTING (PcieLinkCap
)
4593 ShellPrintEx (-1, -1,
4594 L
" Data Link Layer Link Active Reporting Capable(20): %E%d%N\r\n",
4595 PCIE_CAP_LINK_ACTIVE_REPORTING (PcieLinkCap
)
4597 ShellPrintEx (-1, -1,
4598 L
" Link Bandwidth Notification Capability(21): %E%d%N\r\n",
4599 PCIE_CAP_LINK_BWD_NOTIF_CAP (PcieLinkCap
)
4601 ShellPrintEx (-1, -1,
4602 L
" Port Number(31:24): %E0x%02x%N\r\n",
4603 PCIE_CAP_PORT_NUMBER (PcieLinkCap
)
4609 Print out information of the device link control information.
4611 @param[in] PciExpressCap The pointer to the structure about the device.
4613 @retval EFI_SUCCESS The operation was successful.
4616 ExplainPcieLinkControl (
4617 IN PCIE_CAP_STRUCTURE
*PciExpressCap
4620 UINT16 PcieLinkControl
;
4621 UINT8 DevicePortType
;
4623 PcieLinkControl
= PciExpressCap
->LinkControl
;
4624 DevicePortType
= (UINT8
) PCIE_CAP_DEVICEPORT_TYPE (PciExpressCap
->PcieCapReg
);
4625 ShellPrintEx (-1, -1,
4626 L
" Active State Power Management Control(1:0): %E%s%N\r\n",
4627 ASPMCtrlStrTable
[PCIE_CAP_ASPM_CONTROL (PcieLinkControl
)]
4630 // RCB is not applicable to switches
4632 if (!IS_PCIE_SWITCH(DevicePortType
)) {
4633 ShellPrintEx (-1, -1,
4634 L
" Read Completion Boundary (RCB)(3): %E%d byte%N\r\n",
4635 1 << (PCIE_CAP_RCB (PcieLinkControl
) + 6)
4639 // Link Disable is reserved on
4641 // b) PCI Express to PCI/PCI-X bridges
4642 // c) Upstream Ports of Switches
4644 if (!IS_PCIE_ENDPOINT (DevicePortType
) &&
4645 DevicePortType
!= PCIE_SWITCH_UPSTREAM_PORT
&&
4646 DevicePortType
!= PCIE_PCIE_TO_PCIX_BRIDGE
) {
4647 ShellPrintEx (-1, -1,
4648 L
" Link Disable(4): %E%d%N\r\n",
4649 PCIE_CAP_LINK_DISABLE (PcieLinkControl
)
4652 ShellPrintEx (-1, -1,
4653 L
" Common Clock Configuration(6): %E%d%N\r\n",
4654 PCIE_CAP_COMMON_CLK_CONF (PcieLinkControl
)
4656 ShellPrintEx (-1, -1,
4657 L
" Extended Synch(7): %E%d%N\r\n",
4658 PCIE_CAP_EXT_SYNC (PcieLinkControl
)
4660 ShellPrintEx (-1, -1,
4661 L
" Enable Clock Power Management(8): %E%d%N\r\n",
4662 PCIE_CAP_CLK_PWR_MNG (PcieLinkControl
)
4664 ShellPrintEx (-1, -1,
4665 L
" Hardware Autonomous Width Disable(9): %E%d%N\r\n",
4666 PCIE_CAP_HW_AUTO_WIDTH_DISABLE (PcieLinkControl
)
4668 ShellPrintEx (-1, -1,
4669 L
" Link Bandwidth Management Interrupt Enable(10): %E%d%N\r\n",
4670 PCIE_CAP_LINK_BDW_MNG_INT_EN (PcieLinkControl
)
4672 ShellPrintEx (-1, -1,
4673 L
" Link Autonomous Bandwidth Interrupt Enable(11): %E%d%N\r\n",
4674 PCIE_CAP_LINK_AUTO_BDW_INT_EN (PcieLinkControl
)
4680 Print out information of the device link status information.
4682 @param[in] PciExpressCap The pointer to the structure about the device.
4684 @retval EFI_SUCCESS The operation was successful.
4687 ExplainPcieLinkStatus (
4688 IN PCIE_CAP_STRUCTURE
*PciExpressCap
4691 UINT16 PcieLinkStatus
;
4692 CHAR16
*CurLinkSpeed
;
4694 PcieLinkStatus
= PciExpressCap
->LinkStatus
;
4695 switch (PCIE_CAP_CUR_LINK_SPEED (PcieLinkStatus
)) {
4697 CurLinkSpeed
= L
"2.5 GT/s";
4700 CurLinkSpeed
= L
"5.0 GT/s";
4703 CurLinkSpeed
= L
"8.0 GT/s";
4706 CurLinkSpeed
= L
"Reserved";
4709 ShellPrintEx (-1, -1,
4710 L
" Current Link Speed(3:0): %E%s%N\r\n",
4713 ShellPrintEx (-1, -1,
4714 L
" Negotiated Link Width(9:4): %Ex%d%N\r\n",
4715 PCIE_CAP_NEGO_LINK_WIDTH (PcieLinkStatus
)
4717 ShellPrintEx (-1, -1,
4718 L
" Link Training(11): %E%d%N\r\n",
4719 PCIE_CAP_LINK_TRAINING (PcieLinkStatus
)
4721 ShellPrintEx (-1, -1,
4722 L
" Slot Clock Configuration(12): %E%d%N\r\n",
4723 PCIE_CAP_SLOT_CLK_CONF (PcieLinkStatus
)
4725 ShellPrintEx (-1, -1,
4726 L
" Data Link Layer Link Active(13): %E%d%N\r\n",
4727 PCIE_CAP_DATA_LINK_ACTIVE (PcieLinkStatus
)
4729 ShellPrintEx (-1, -1,
4730 L
" Link Bandwidth Management Status(14): %E%d%N\r\n",
4731 PCIE_CAP_LINK_BDW_MNG_STAT (PcieLinkStatus
)
4733 ShellPrintEx (-1, -1,
4734 L
" Link Autonomous Bandwidth Status(15): %E%d%N\r\n",
4735 PCIE_CAP_LINK_AUTO_BDW_STAT (PcieLinkStatus
)
4741 Print out information of the device slot information.
4743 @param[in] PciExpressCap The pointer to the structure about the device.
4745 @retval EFI_SUCCESS The operation was successful.
4748 ExplainPcieSlotCap (
4749 IN PCIE_CAP_STRUCTURE
*PciExpressCap
4754 PcieSlotCap
= PciExpressCap
->SlotCap
;
4756 ShellPrintEx (-1, -1,
4757 L
" Attention Button Present(0): %E%d%N\r\n",
4758 PCIE_CAP_ATT_BUT_PRESENT (PcieSlotCap
)
4760 ShellPrintEx (-1, -1,
4761 L
" Power Controller Present(1): %E%d%N\r\n",
4762 PCIE_CAP_PWR_CTRLLER_PRESENT (PcieSlotCap
)
4764 ShellPrintEx (-1, -1,
4765 L
" MRL Sensor Present(2): %E%d%N\r\n",
4766 PCIE_CAP_MRL_SENSOR_PRESENT (PcieSlotCap
)
4768 ShellPrintEx (-1, -1,
4769 L
" Attention Indicator Present(3): %E%d%N\r\n",
4770 PCIE_CAP_ATT_IND_PRESENT (PcieSlotCap
)
4772 ShellPrintEx (-1, -1,
4773 L
" Power Indicator Present(4): %E%d%N\r\n",
4774 PCIE_CAP_PWD_IND_PRESENT (PcieSlotCap
)
4776 ShellPrintEx (-1, -1,
4777 L
" Hot-Plug Surprise(5): %E%d%N\r\n",
4778 PCIE_CAP_HOTPLUG_SUPPRISE (PcieSlotCap
)
4780 ShellPrintEx (-1, -1,
4781 L
" Hot-Plug Capable(6): %E%d%N\r\n",
4782 PCIE_CAP_HOTPLUG_CAPABLE (PcieSlotCap
)
4784 ShellPrintEx (-1, -1,
4785 L
" Slot Power Limit Value(14:7): %E0x%02x%N\r\n",
4786 PCIE_CAP_SLOT_PWR_LIMIT_VALUE (PcieSlotCap
)
4788 ShellPrintEx (-1, -1,
4789 L
" Slot Power Limit Scale(16:15): %E%s%N\r\n",
4790 SlotPwrLmtScaleTable
[PCIE_CAP_SLOT_PWR_LIMIT_SCALE (PcieSlotCap
)]
4792 ShellPrintEx (-1, -1,
4793 L
" Electromechanical Interlock Present(17): %E%d%N\r\n",
4794 PCIE_CAP_ELEC_INTERLOCK_PRESENT (PcieSlotCap
)
4796 ShellPrintEx (-1, -1,
4797 L
" No Command Completed Support(18): %E%d%N\r\n",
4798 PCIE_CAP_NO_COMM_COMPLETED_SUP (PcieSlotCap
)
4800 ShellPrintEx (-1, -1,
4801 L
" Physical Slot Number(31:19): %E%d%N\r\n",
4802 PCIE_CAP_PHY_SLOT_NUM (PcieSlotCap
)
4809 Print out information of the device slot control information.
4811 @param[in] PciExpressCap The pointer to the structure about the device.
4813 @retval EFI_SUCCESS The operation was successful.
4816 ExplainPcieSlotControl (
4817 IN PCIE_CAP_STRUCTURE
*PciExpressCap
4820 UINT16 PcieSlotControl
;
4822 PcieSlotControl
= PciExpressCap
->SlotControl
;
4823 ShellPrintEx (-1, -1,
4824 L
" Attention Button Pressed Enable(0): %E%d%N\r\n",
4825 PCIE_CAP_ATT_BUT_ENABLE (PcieSlotControl
)
4827 ShellPrintEx (-1, -1,
4828 L
" Power Fault Detected Enable(1): %E%d%N\r\n",
4829 PCIE_CAP_PWR_FLT_DETECT_ENABLE (PcieSlotControl
)
4831 ShellPrintEx (-1, -1,
4832 L
" MRL Sensor Changed Enable(2): %E%d%N\r\n",
4833 PCIE_CAP_MRL_SENSOR_CHANGE_ENABLE (PcieSlotControl
)
4835 ShellPrintEx (-1, -1,
4836 L
" Presence Detect Changed Enable(3): %E%d%N\r\n",
4837 PCIE_CAP_PRES_DETECT_CHANGE_ENABLE (PcieSlotControl
)
4839 ShellPrintEx (-1, -1,
4840 L
" Command Completed Interrupt Enable(4): %E%d%N\r\n",
4841 PCIE_CAP_COMM_CMPL_INT_ENABLE (PcieSlotControl
)
4843 ShellPrintEx (-1, -1,
4844 L
" Hot-Plug Interrupt Enable(5): %E%d%N\r\n",
4845 PCIE_CAP_HOTPLUG_INT_ENABLE (PcieSlotControl
)
4847 ShellPrintEx (-1, -1,
4848 L
" Attention Indicator Control(7:6): %E%s%N\r\n",
4849 IndicatorTable
[PCIE_CAP_ATT_IND_CTRL (PcieSlotControl
)]
4851 ShellPrintEx (-1, -1,
4852 L
" Power Indicator Control(9:8): %E%s%N\r\n",
4853 IndicatorTable
[PCIE_CAP_PWR_IND_CTRL (PcieSlotControl
)]
4855 ShellPrintEx (-1, -1, L
" Power Controller Control(10): %EPower ");
4856 if (PCIE_CAP_PWR_CTRLLER_CTRL (PcieSlotControl
)) {
4857 ShellPrintEx (-1, -1, L
"Off%N\r\n");
4859 ShellPrintEx (-1, -1, L
"On%N\r\n");
4861 ShellPrintEx (-1, -1,
4862 L
" Electromechanical Interlock Control(11): %E%d%N\r\n",
4863 PCIE_CAP_ELEC_INTERLOCK_CTRL (PcieSlotControl
)
4865 ShellPrintEx (-1, -1,
4866 L
" Data Link Layer State Changed Enable(12): %E%d%N\r\n",
4867 PCIE_CAP_DLINK_STAT_CHANGE_ENABLE (PcieSlotControl
)
4873 Print out information of the device slot status information.
4875 @param[in] PciExpressCap The pointer to the structure about the device.
4877 @retval EFI_SUCCESS The operation was successful.
4880 ExplainPcieSlotStatus (
4881 IN PCIE_CAP_STRUCTURE
*PciExpressCap
4884 UINT16 PcieSlotStatus
;
4886 PcieSlotStatus
= PciExpressCap
->SlotStatus
;
4888 ShellPrintEx (-1, -1,
4889 L
" Attention Button Pressed(0): %E%d%N\r\n",
4890 PCIE_CAP_ATT_BUT_PRESSED (PcieSlotStatus
)
4892 ShellPrintEx (-1, -1,
4893 L
" Power Fault Detected(1): %E%d%N\r\n",
4894 PCIE_CAP_PWR_FLT_DETECTED (PcieSlotStatus
)
4896 ShellPrintEx (-1, -1,
4897 L
" MRL Sensor Changed(2): %E%d%N\r\n",
4898 PCIE_CAP_MRL_SENSOR_CHANGED (PcieSlotStatus
)
4900 ShellPrintEx (-1, -1,
4901 L
" Presence Detect Changed(3): %E%d%N\r\n",
4902 PCIE_CAP_PRES_DETECT_CHANGED (PcieSlotStatus
)
4904 ShellPrintEx (-1, -1,
4905 L
" Command Completed(4): %E%d%N\r\n",
4906 PCIE_CAP_COMM_COMPLETED (PcieSlotStatus
)
4908 ShellPrintEx (-1, -1, L
" MRL Sensor State(5): %EMRL ");
4909 if (PCIE_CAP_MRL_SENSOR_STATE (PcieSlotStatus
)) {
4910 ShellPrintEx (-1, -1, L
" Opened%N\r\n");
4912 ShellPrintEx (-1, -1, L
" Closed%N\r\n");
4914 ShellPrintEx (-1, -1, L
" Presence Detect State(6): ");
4915 if (PCIE_CAP_PRES_DETECT_STATE (PcieSlotStatus
)) {
4916 ShellPrintEx (-1, -1, L
"%ECard Present in slot%N\r\n");
4918 ShellPrintEx (-1, -1, L
"%ESlot Empty%N\r\n");
4920 ShellPrintEx (-1, -1, L
" Electromechanical Interlock Status(7): %EElectromechanical Interlock ");
4921 if (PCIE_CAP_ELEC_INTERLOCK_STATE (PcieSlotStatus
)) {
4922 ShellPrintEx (-1, -1, L
"Engaged%N\r\n");
4924 ShellPrintEx (-1, -1, L
"Disengaged%N\r\n");
4926 ShellPrintEx (-1, -1,
4927 L
" Data Link Layer State Changed(8): %E%d%N\r\n",
4928 PCIE_CAP_DLINK_STAT_CHANGED (PcieSlotStatus
)
4934 Print out information of the device root information.
4936 @param[in] PciExpressCap The pointer to the structure about the device.
4938 @retval EFI_SUCCESS The operation was successful.
4941 ExplainPcieRootControl (
4942 IN PCIE_CAP_STRUCTURE
*PciExpressCap
4945 UINT16 PcieRootControl
;
4947 PcieRootControl
= PciExpressCap
->RootControl
;
4949 ShellPrintEx (-1, -1,
4950 L
" System Error on Correctable Error Enable(0): %E%d%N\r\n",
4951 PCIE_CAP_SYSERR_ON_CORERR_EN (PcieRootControl
)
4953 ShellPrintEx (-1, -1,
4954 L
" System Error on Non-Fatal Error Enable(1): %E%d%N\r\n",
4955 PCIE_CAP_SYSERR_ON_NONFATERR_EN (PcieRootControl
)
4957 ShellPrintEx (-1, -1,
4958 L
" System Error on Fatal Error Enable(2): %E%d%N\r\n",
4959 PCIE_CAP_SYSERR_ON_FATERR_EN (PcieRootControl
)
4961 ShellPrintEx (-1, -1,
4962 L
" PME Interrupt Enable(3): %E%d%N\r\n",
4963 PCIE_CAP_PME_INT_ENABLE (PcieRootControl
)
4965 ShellPrintEx (-1, -1,
4966 L
" CRS Software Visibility Enable(4): %E%d%N\r\n",
4967 PCIE_CAP_CRS_SW_VIS_ENABLE (PcieRootControl
)
4974 Print out information of the device root capability information.
4976 @param[in] PciExpressCap The pointer to the structure about the device.
4978 @retval EFI_SUCCESS The operation was successful.
4981 ExplainPcieRootCap (
4982 IN PCIE_CAP_STRUCTURE
*PciExpressCap
4987 PcieRootCap
= PciExpressCap
->RsvdP
;
4989 ShellPrintEx (-1, -1,
4990 L
" CRS Software Visibility(0): %E%d%N\r\n",
4991 PCIE_CAP_CRS_SW_VIS (PcieRootCap
)
4998 Print out information of the device root status information.
5000 @param[in] PciExpressCap The pointer to the structure about the device.
5002 @retval EFI_SUCCESS The operation was successful.
5005 ExplainPcieRootStatus (
5006 IN PCIE_CAP_STRUCTURE
*PciExpressCap
5009 UINT32 PcieRootStatus
;
5011 PcieRootStatus
= PciExpressCap
->RootStatus
;
5013 ShellPrintEx (-1, -1,
5014 L
" PME Requester ID(15:0): %E0x%04x%N\r\n",
5015 PCIE_CAP_PME_REQ_ID (PcieRootStatus
)
5017 ShellPrintEx (-1, -1,
5018 L
" PME Status(16): %E%d%N\r\n",
5019 PCIE_CAP_PME_STATUS (PcieRootStatus
)
5021 ShellPrintEx (-1, -1,
5022 L
" PME Pending(17): %E%d%N\r\n",
5023 PCIE_CAP_PME_PENDING (PcieRootStatus
)
5029 Function to interpret and print out the link control structure
5031 @param[in] HeaderAddress The Address of this capability header.
5032 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5036 PrintInterpretedExtendedCompatibilityLinkControl (
5037 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5038 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
5041 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_INTERNAL_LINK_CONTROL
*Header
;
5042 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_INTERNAL_LINK_CONTROL
*)HeaderAddress
;
5046 STRING_TOKEN (STR_PCI_EXT_CAP_LINK_CONTROL
),
5047 gShellDebug1HiiHandle
,
5048 Header
->RootComplexLinkCapabilities
,
5049 Header
->RootComplexLinkControl
,
5050 Header
->RootComplexLinkStatus
5054 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5055 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_INTERNAL_LINK_CONTROL
),
5056 (VOID
*) (HeaderAddress
)
5058 return (EFI_SUCCESS
);
5062 Function to interpret and print out the power budgeting structure
5064 @param[in] HeaderAddress The Address of this capability header.
5065 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5069 PrintInterpretedExtendedCompatibilityPowerBudgeting (
5070 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5071 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
5074 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_POWER_BUDGETING
*Header
;
5075 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_POWER_BUDGETING
*)HeaderAddress
;
5079 STRING_TOKEN (STR_PCI_EXT_CAP_POWER
),
5080 gShellDebug1HiiHandle
,
5083 Header
->PowerBudgetCapability
5087 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5088 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_POWER_BUDGETING
),
5089 (VOID
*) (HeaderAddress
)
5091 return (EFI_SUCCESS
);
5095 Function to interpret and print out the ACS structure
5097 @param[in] HeaderAddress The Address of this capability header.
5098 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5102 PrintInterpretedExtendedCompatibilityAcs (
5103 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5104 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
5107 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_ACS_EXTENDED
*Header
;
5111 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_ACS_EXTENDED
*)HeaderAddress
;
5116 STRING_TOKEN (STR_PCI_EXT_CAP_ACS
),
5117 gShellDebug1HiiHandle
,
5118 Header
->AcsCapability
,
5121 if (PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_GET_EGRES_CONTROL(Header
)) {
5122 VectorSize
= PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_GET_EGRES_VECTOR_SIZE(Header
);
5123 if (VectorSize
== 0) {
5126 for (LoopCounter
= 0 ; LoopCounter
* 8 < VectorSize
; LoopCounter
++) {
5129 STRING_TOKEN (STR_PCI_EXT_CAP_ACS2
),
5130 gShellDebug1HiiHandle
,
5132 Header
->EgressControlVectorArray
[LoopCounter
]
5138 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5139 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_ACS_EXTENDED
) + (VectorSize
/ 8) - 1,
5140 (VOID
*) (HeaderAddress
)
5142 return (EFI_SUCCESS
);
5146 Function to interpret and print out the latency tolerance reporting structure
5148 @param[in] HeaderAddress The Address of this capability header.
5149 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5153 PrintInterpretedExtendedCompatibilityLatencyToleranceReporting (
5154 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5155 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
5158 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_LATENCE_TOLERANCE_REPORTING
*Header
;
5159 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_LATENCE_TOLERANCE_REPORTING
*)HeaderAddress
;
5163 STRING_TOKEN (STR_PCI_EXT_CAP_LAT
),
5164 gShellDebug1HiiHandle
,
5165 Header
->MaxSnoopLatency
,
5166 Header
->MaxNoSnoopLatency
5170 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5171 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_LATENCE_TOLERANCE_REPORTING
),
5172 (VOID
*) (HeaderAddress
)
5174 return (EFI_SUCCESS
);
5178 Function to interpret and print out the serial number structure
5180 @param[in] HeaderAddress The Address of this capability header.
5181 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5185 PrintInterpretedExtendedCompatibilitySerialNumber (
5186 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5187 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
5190 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_SERIAL_NUMBER
*Header
;
5191 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_SERIAL_NUMBER
*)HeaderAddress
;
5195 STRING_TOKEN (STR_PCI_EXT_CAP_SN
),
5196 gShellDebug1HiiHandle
,
5197 Header
->SerialNumber
5201 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5202 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_SERIAL_NUMBER
),
5203 (VOID
*) (HeaderAddress
)
5205 return (EFI_SUCCESS
);
5209 Function to interpret and print out the RCRB structure
5211 @param[in] HeaderAddress The Address of this capability header.
5212 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5216 PrintInterpretedExtendedCompatibilityRcrb (
5217 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5218 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
5221 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_RCRB_HEADER
*Header
;
5222 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_RCRB_HEADER
*)HeaderAddress
;
5226 STRING_TOKEN (STR_PCI_EXT_CAP_RCRB
),
5227 gShellDebug1HiiHandle
,
5230 Header
->RcrbCapabilities
,
5235 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5236 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_RCRB_HEADER
),
5237 (VOID
*) (HeaderAddress
)
5239 return (EFI_SUCCESS
);
5243 Function to interpret and print out the vendor specific structure
5245 @param[in] HeaderAddress The Address of this capability header.
5246 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5250 PrintInterpretedExtendedCompatibilityVendorSpecific (
5251 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5252 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
5255 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_VENDOR_SPECIFIC
*Header
;
5256 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_VENDOR_SPECIFIC
*)HeaderAddress
;
5260 STRING_TOKEN (STR_PCI_EXT_CAP_VEN
),
5261 gShellDebug1HiiHandle
,
5262 Header
->VendorSpecificHeader
5266 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5267 PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_GET_SIZE(Header
),
5268 (VOID
*) (HeaderAddress
)
5270 return (EFI_SUCCESS
);
5274 Function to interpret and print out the Event Collector Endpoint Association structure
5276 @param[in] HeaderAddress The Address of this capability header.
5277 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5281 PrintInterpretedExtendedCompatibilityECEA (
5282 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5283 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
5286 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION
*Header
;
5287 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION
*)HeaderAddress
;
5291 STRING_TOKEN (STR_PCI_EXT_CAP_ECEA
),
5292 gShellDebug1HiiHandle
,
5293 Header
->AssociationBitmap
5297 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5298 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION
),
5299 (VOID
*) (HeaderAddress
)
5301 return (EFI_SUCCESS
);
5305 Function to interpret and print out the ARI structure
5307 @param[in] HeaderAddress The Address of this capability header.
5308 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5312 PrintInterpretedExtendedCompatibilityAri (
5313 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5314 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
5317 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_ARI_CAPABILITY
*Header
;
5318 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_ARI_CAPABILITY
*)HeaderAddress
;
5322 STRING_TOKEN (STR_PCI_EXT_CAP_ARI
),
5323 gShellDebug1HiiHandle
,
5324 Header
->AriCapability
,
5329 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5330 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_ARI_CAPABILITY
),
5331 (VOID
*) (HeaderAddress
)
5333 return (EFI_SUCCESS
);
5337 Function to interpret and print out the DPA structure
5339 @param[in] HeaderAddress The Address of this capability header.
5340 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5344 PrintInterpretedExtendedCompatibilityDynamicPowerAllocation (
5345 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5346 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
5349 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_DYNAMIC_POWER_ALLOCATION
*Header
;
5351 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_DYNAMIC_POWER_ALLOCATION
*)HeaderAddress
;
5355 STRING_TOKEN (STR_PCI_EXT_CAP_DPA
),
5356 gShellDebug1HiiHandle
,
5357 Header
->DpaCapability
,
5358 Header
->DpaLatencyIndicator
,
5362 for (LinkCount
= 0 ; LinkCount
< PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_GET_SUBSTATE_MAX(Header
) + 1 ; LinkCount
++) {
5365 STRING_TOKEN (STR_PCI_EXT_CAP_DPA2
),
5366 gShellDebug1HiiHandle
,
5368 Header
->DpaPowerAllocationArray
[LinkCount
]
5373 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5374 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_DYNAMIC_POWER_ALLOCATION
) - 1 + PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_GET_SUBSTATE_MAX(Header
),
5375 (VOID
*) (HeaderAddress
)
5377 return (EFI_SUCCESS
);
5381 Function to interpret and print out the link declaration structure
5383 @param[in] HeaderAddress The Address of this capability header.
5384 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5388 PrintInterpretedExtendedCompatibilityLinkDeclaration (
5389 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5390 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
5393 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_LINK_DECLARATION
*Header
;
5395 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_LINK_DECLARATION
*)HeaderAddress
;
5399 STRING_TOKEN (STR_PCI_EXT_CAP_LINK_DECLAR
),
5400 gShellDebug1HiiHandle
,
5401 Header
->ElementSelfDescription
5404 for (LinkCount
= 0 ; LinkCount
< PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_GET_LINK_COUNT(Header
) ; LinkCount
++) {
5407 STRING_TOKEN (STR_PCI_EXT_CAP_LINK_DECLAR2
),
5408 gShellDebug1HiiHandle
,
5410 Header
->LinkEntry
[LinkCount
]
5415 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5416 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_LINK_DECLARATION
) + (PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_GET_LINK_COUNT(Header
)-1)*sizeof(UINT32
),
5417 (VOID
*) (HeaderAddress
)
5419 return (EFI_SUCCESS
);
5423 Function to interpret and print out the Advanced Error Reporting structure
5425 @param[in] HeaderAddress The Address of this capability header.
5426 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5430 PrintInterpretedExtendedCompatibilityAer (
5431 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5432 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
5435 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_ADVANCED_ERROR_REPORTING
*Header
;
5436 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_ADVANCED_ERROR_REPORTING
*)HeaderAddress
;
5440 STRING_TOKEN (STR_PCI_EXT_CAP_AER
),
5441 gShellDebug1HiiHandle
,
5442 Header
->UncorrectableErrorStatus
,
5443 Header
->UncorrectableErrorMask
,
5444 Header
->UncorrectableErrorSeverity
,
5445 Header
->CorrectableErrorStatus
,
5446 Header
->CorrectableErrorMask
,
5447 Header
->AdvancedErrorCapabilitiesAndControl
,
5448 Header
->HeaderLog
[0],
5449 Header
->HeaderLog
[1],
5450 Header
->HeaderLog
[2],
5451 Header
->HeaderLog
[3],
5452 Header
->RootErrorCommand
,
5453 Header
->RootErrorStatus
,
5454 Header
->ErrorSourceIdentification
,
5455 Header
->CorrectableErrorSourceIdentification
,
5456 Header
->TlpPrefixLog
[0],
5457 Header
->TlpPrefixLog
[1],
5458 Header
->TlpPrefixLog
[2],
5459 Header
->TlpPrefixLog
[3]
5463 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5464 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_ADVANCED_ERROR_REPORTING
),
5465 (VOID
*) (HeaderAddress
)
5467 return (EFI_SUCCESS
);
5471 Function to interpret and print out the multicast structure
5473 @param[in] HeaderAddress The Address of this capability header.
5474 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5475 @param[in] PciExpressCapPtr The address of the PCIe capabilities structure.
5479 PrintInterpretedExtendedCompatibilityMulticast (
5480 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5481 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
,
5482 IN CONST PCIE_CAP_STRUCTURE
*PciExpressCapPtr
5485 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTICAST
*Header
;
5486 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTICAST
*)HeaderAddress
;
5490 STRING_TOKEN (STR_PCI_EXT_CAP_MULTICAST
),
5491 gShellDebug1HiiHandle
,
5492 Header
->MultiCastCapability
,
5493 Header
->MulticastControl
,
5494 Header
->McBaseAddress
,
5495 Header
->McReceiveAddress
,
5497 Header
->McBlockUntranslated
,
5498 Header
->McOverlayBar
5503 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5504 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTICAST
),
5505 (VOID
*) (HeaderAddress
)
5508 return (EFI_SUCCESS
);
5512 Function to interpret and print out the virtual channel and multi virtual channel structure
5514 @param[in] HeaderAddress The Address of this capability header.
5515 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5519 PrintInterpretedExtendedCompatibilityVirtualChannel (
5520 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5521 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
5524 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY
*Header
;
5525 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_VC
*CapabilityItem
;
5527 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY
*)HeaderAddress
;
5531 STRING_TOKEN (STR_PCI_EXT_CAP_VC_BASE
),
5532 gShellDebug1HiiHandle
,
5533 Header
->ExtendedVcCount
,
5534 Header
->PortVcCapability1
,
5535 Header
->PortVcCapability2
,
5536 Header
->VcArbTableOffset
,
5537 Header
->PortVcControl
,
5538 Header
->PortVcStatus
5540 for (ItemCount
= 0 ; ItemCount
< Header
->ExtendedVcCount
; ItemCount
++) {
5541 CapabilityItem
= &Header
->Capability
[ItemCount
];
5544 STRING_TOKEN (STR_PCI_EXT_CAP_VC_ITEM
),
5545 gShellDebug1HiiHandle
,
5547 CapabilityItem
->VcResourceCapability
,
5548 CapabilityItem
->PortArbTableOffset
,
5549 CapabilityItem
->VcResourceControl
,
5550 CapabilityItem
->VcResourceStatus
5556 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5557 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_VC
) + (Header
->ExtendedVcCount
- 1) * sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY
),
5558 (VOID
*) (HeaderAddress
)
5561 return (EFI_SUCCESS
);
5565 Function to interpret and print out the resizeable bar structure
5567 @param[in] HeaderAddress The Address of this capability header.
5568 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5572 PrintInterpretedExtendedCompatibilityResizeableBar (
5573 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5574 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
5577 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR
*Header
;
5579 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR
*)HeaderAddress
;
5581 for (ItemCount
= 0 ; ItemCount
< (UINT32
)GET_NUMBER_RESIZABLE_BARS(Header
) ; ItemCount
++) {
5584 STRING_TOKEN (STR_PCI_EXT_CAP_RESIZE_BAR
),
5585 gShellDebug1HiiHandle
,
5587 Header
->Capability
[ItemCount
].ResizableBarCapability
,
5588 Header
->Capability
[ItemCount
].ResizableBarControl
5594 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5595 (UINT32
)GET_NUMBER_RESIZABLE_BARS(Header
) * sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY
),
5596 (VOID
*) (HeaderAddress
)
5599 return (EFI_SUCCESS
);
5603 Function to interpret and print out the TPH structure
5605 @param[in] HeaderAddress The Address of this capability header.
5606 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5610 PrintInterpretedExtendedCompatibilityTph (
5611 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5612 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
5615 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH
*Header
;
5616 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH
*)HeaderAddress
;
5620 STRING_TOKEN (STR_PCI_EXT_CAP_TPH
),
5621 gShellDebug1HiiHandle
,
5622 Header
->TphRequesterCapability
,
5623 Header
->TphRequesterControl
5627 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)Header
->TphStTable
- (UINT8
*)HeadersBaseAddress
),
5628 GET_TPH_TABLE_SIZE(Header
),
5629 (VOID
*)Header
->TphStTable
5634 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5635 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH
) + GET_TPH_TABLE_SIZE(Header
) - sizeof(UINT16
),
5636 (VOID
*) (HeaderAddress
)
5639 return (EFI_SUCCESS
);
5643 Function to interpret and print out the secondary PCIe capability structure
5645 @param[in] HeaderAddress The Address of this capability header.
5646 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5647 @param[in] PciExpressCapPtr The address of the PCIe capabilities structure.
5651 PrintInterpretedExtendedCompatibilitySecondary (
5652 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5653 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
,
5654 IN CONST PCIE_CAP_STRUCTURE
*PciExpressCapPtr
5657 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_SECONDARY_PCIE
*Header
;
5658 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_SECONDARY_PCIE
*)HeaderAddress
;
5662 STRING_TOKEN (STR_PCI_EXT_CAP_SECONDARY
),
5663 gShellDebug1HiiHandle
,
5664 Header
->LinkControl3
,
5665 Header
->LaneErrorStatus
5669 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)Header
->EqualizationControl
- (UINT8
*)HeadersBaseAddress
),
5670 PCIE_CAP_MAX_LINK_WIDTH(PciExpressCapPtr
->LinkCap
),
5671 (VOID
*)Header
->EqualizationControl
5676 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5677 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH
) - sizeof(Header
->EqualizationControl
) + PCIE_CAP_MAX_LINK_WIDTH(PciExpressCapPtr
->LinkCap
),
5678 (VOID
*) (HeaderAddress
)
5681 return (EFI_SUCCESS
);
5685 Display Pcie extended capability details
5687 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5688 @param[in] HeaderAddress The address of this capability header.
5689 @param[in] PciExpressCapPtr The address of the PCIe capabilities structure.
5693 PrintPciExtendedCapabilityDetails(
5694 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
,
5695 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5696 IN CONST PCIE_CAP_STRUCTURE
*PciExpressCapPtr
5699 switch (HeaderAddress
->CapabilityId
){
5700 case PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_ID
:
5701 return PrintInterpretedExtendedCompatibilityAer(HeaderAddress
, HeadersBaseAddress
);
5702 case PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_CONTROL_ID
:
5703 return PrintInterpretedExtendedCompatibilityLinkControl(HeaderAddress
, HeadersBaseAddress
);
5704 case PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_ID
:
5705 return PrintInterpretedExtendedCompatibilityLinkDeclaration(HeaderAddress
, HeadersBaseAddress
);
5706 case PCI_EXPRESS_EXTENDED_CAPABILITY_SERIAL_NUMBER_ID
:
5707 return PrintInterpretedExtendedCompatibilitySerialNumber(HeaderAddress
, HeadersBaseAddress
);
5708 case PCI_EXPRESS_EXTENDED_CAPABILITY_POWER_BUDGETING_ID
:
5709 return PrintInterpretedExtendedCompatibilityPowerBudgeting(HeaderAddress
, HeadersBaseAddress
);
5710 case PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_ID
:
5711 return PrintInterpretedExtendedCompatibilityAcs(HeaderAddress
, HeadersBaseAddress
);
5712 case PCI_EXPRESS_EXTENDED_CAPABILITY_LATENCE_TOLERANCE_REPORTING_ID
:
5713 return PrintInterpretedExtendedCompatibilityLatencyToleranceReporting(HeaderAddress
, HeadersBaseAddress
);
5714 case PCI_EXPRESS_EXTENDED_CAPABILITY_ARI_CAPABILITY_ID
:
5715 return PrintInterpretedExtendedCompatibilityAri(HeaderAddress
, HeadersBaseAddress
);
5716 case PCI_EXPRESS_EXTENDED_CAPABILITY_RCRB_HEADER_ID
:
5717 return PrintInterpretedExtendedCompatibilityRcrb(HeaderAddress
, HeadersBaseAddress
);
5718 case PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_ID
:
5719 return PrintInterpretedExtendedCompatibilityVendorSpecific(HeaderAddress
, HeadersBaseAddress
);
5720 case PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_ID
:
5721 return PrintInterpretedExtendedCompatibilityDynamicPowerAllocation(HeaderAddress
, HeadersBaseAddress
);
5722 case PCI_EXPRESS_EXTENDED_CAPABILITY_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION_ID
:
5723 return PrintInterpretedExtendedCompatibilityECEA(HeaderAddress
, HeadersBaseAddress
);
5724 case PCI_EXPRESS_EXTENDED_CAPABILITY_VIRTUAL_CHANNEL_ID
:
5725 case PCI_EXPRESS_EXTENDED_CAPABILITY_MULTI_FUNCTION_VIRTUAL_CHANNEL_ID
:
5726 return PrintInterpretedExtendedCompatibilityVirtualChannel(HeaderAddress
, HeadersBaseAddress
);
5727 case PCI_EXPRESS_EXTENDED_CAPABILITY_MULTICAST_ID
:
5729 // should only be present if PCIE_CAP_DEVICEPORT_TYPE(PciExpressCapPtr->PcieCapReg) == 0100b, 0101b, or 0110b
5731 return PrintInterpretedExtendedCompatibilityMulticast(HeaderAddress
, HeadersBaseAddress
, PciExpressCapPtr
);
5732 case PCI_EXPRESS_EXTENDED_CAPABILITY_RESIZABLE_BAR_ID
:
5733 return PrintInterpretedExtendedCompatibilityResizeableBar(HeaderAddress
, HeadersBaseAddress
);
5734 case PCI_EXPRESS_EXTENDED_CAPABILITY_TPH_ID
:
5735 return PrintInterpretedExtendedCompatibilityTph(HeaderAddress
, HeadersBaseAddress
);
5736 case PCI_EXPRESS_EXTENDED_CAPABILITY_SECONDARY_PCIE_ID
:
5737 return PrintInterpretedExtendedCompatibilitySecondary(HeaderAddress
, HeadersBaseAddress
, PciExpressCapPtr
);
5739 ShellPrintEx (-1, -1,
5740 L
"Unknown PCIe extended capability ID (%04xh). No interpretation available.\r\n",
5741 HeaderAddress
->CapabilityId
5749 Display Pcie device structure.
5751 @param[in] IoDev The pointer to the root pci protocol.
5752 @param[in] Address The Address to start at.
5753 @param[in] CapabilityPtr The offset from the address to start.
5754 @param[in] EnhancedDump The print format for the dump data.
5758 PciExplainPciExpress (
5759 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
,
5761 IN UINT8 CapabilityPtr
,
5762 IN CONST UINT16 EnhancedDump
5766 PCIE_CAP_STRUCTURE PciExpressCap
;
5768 UINT64 CapRegAddress
;
5773 UINTN ExtendRegSize
;
5774 UINT64 Pciex_Address
;
5775 UINT8 DevicePortType
;
5779 PCI_EXP_EXT_HDR
*ExtHdr
;
5781 CapRegAddress
= Address
+ CapabilityPtr
;
5786 sizeof (PciExpressCap
) / sizeof (UINT32
),
5790 DevicePortType
= (UINT8
) PCIE_CAP_DEVICEPORT_TYPE (PciExpressCap
.PcieCapReg
);
5792 ShellPrintEx (-1, -1, L
"\r\nPci Express device capability structure:\r\n");
5794 for (Index
= 0; PcieExplainList
[Index
].Type
< PcieExplainTypeMax
; Index
++) {
5795 if (ShellGetExecutionBreakFlag()) {
5798 RegAddr
= ((UINT8
*) &PciExpressCap
) + PcieExplainList
[Index
].Offset
;
5799 switch (PcieExplainList
[Index
].Width
) {
5800 case FieldWidthUINT8
:
5801 RegValue
= *(UINT8
*) RegAddr
;
5803 case FieldWidthUINT16
:
5804 RegValue
= *(UINT16
*) RegAddr
;
5806 case FieldWidthUINT32
:
5807 RegValue
= *(UINT32
*) RegAddr
;
5813 ShellPrintHiiEx(-1, -1, NULL
,
5814 PcieExplainList
[Index
].Token
,
5815 gShellDebug1HiiHandle
,
5816 PcieExplainList
[Index
].Offset
,
5819 if (PcieExplainList
[Index
].Func
== NULL
) {
5822 switch (PcieExplainList
[Index
].Type
) {
5823 case PcieExplainTypeLink
:
5825 // Link registers should not be used by
5826 // a) Root Complex Integrated Endpoint
5827 // b) Root Complex Event Collector
5829 if (DevicePortType
== PCIE_ROOT_COMPLEX_INTEGRATED_PORT
||
5830 DevicePortType
== PCIE_ROOT_COMPLEX_EVENT_COLLECTOR
) {
5834 case PcieExplainTypeSlot
:
5836 // Slot registers are only valid for
5837 // a) Root Port of PCI Express Root Complex
5838 // b) Downstream Port of PCI Express Switch
5839 // and when SlotImplemented bit is set in PCIE cap register.
5841 if ((DevicePortType
!= PCIE_ROOT_COMPLEX_ROOT_PORT
&&
5842 DevicePortType
!= PCIE_SWITCH_DOWNSTREAM_PORT
) ||
5843 !PCIE_CAP_SLOT_IMPLEMENTED (PciExpressCap
.PcieCapReg
)) {
5847 case PcieExplainTypeRoot
:
5849 // Root registers are only valid for
5850 // Root Port of PCI Express Root Complex
5852 if (DevicePortType
!= PCIE_ROOT_COMPLEX_ROOT_PORT
) {
5859 PcieExplainList
[Index
].Func (&PciExpressCap
);
5862 Bus
= (UINT8
) (RShiftU64 (Address
, 24));
5863 Dev
= (UINT8
) (RShiftU64 (Address
, 16));
5864 Func
= (UINT8
) (RShiftU64 (Address
, 8));
5866 Pciex_Address
= CALC_EFI_PCIEX_ADDRESS (Bus
, Dev
, Func
, EFI_PCIE_CAPABILITY_BASE_OFFSET
);
5868 ExtendRegSize
= 0x1000 - EFI_PCIE_CAPABILITY_BASE_OFFSET
;
5870 ExRegBuffer
= (UINT8
*) AllocateZeroPool (ExtendRegSize
);
5873 // PciRootBridgeIo protocol should support pci express extend space IO
5874 // (Begins at offset EFI_PCIE_CAPABILITY_BASE_OFFSET)
5876 Status
= IoDev
->Pci
.Read (
5880 (ExtendRegSize
) / sizeof (UINT32
),
5881 (VOID
*) (ExRegBuffer
)
5883 if (EFI_ERROR (Status
) || ExRegBuffer
== NULL
) {
5884 SHELL_FREE_NON_NULL(ExRegBuffer
);
5885 return EFI_UNSUPPORTED
;
5888 if (EnhancedDump
== 0) {
5890 // Print the PciEx extend space in raw bytes ( 0xFF-0xFFF)
5892 ShellPrintEx (-1, -1, L
"\r\n%HStart dumping PCIex extended configuration space (0x100 - 0xFFF).%N\r\n\r\n");
5896 EFI_PCIE_CAPABILITY_BASE_OFFSET
,
5898 (VOID
*) (ExRegBuffer
)
5901 ExtHdr
= (PCI_EXP_EXT_HDR
*)ExRegBuffer
;
5902 while (ExtHdr
->CapabilityId
!= 0 && ExtHdr
->CapabilityVersion
!= 0) {
5904 // Process this item
5906 if (EnhancedDump
== 0xFFFF || EnhancedDump
== ExtHdr
->CapabilityId
) {
5910 PrintPciExtendedCapabilityDetails((PCI_EXP_EXT_HDR
*)ExRegBuffer
, ExtHdr
, &PciExpressCap
);
5914 // Advance to the next item if it exists
5916 if (ExtHdr
->NextCapabilityOffset
!= 0) {
5917 ExtHdr
= (PCI_EXP_EXT_HDR
*)((UINT8
*)ExRegBuffer
+ ExtHdr
->NextCapabilityOffset
);
5923 SHELL_FREE_NON_NULL(ExRegBuffer
);