2 Main file for Pci shell Debug1 function.
4 Copyright (c) 2005 - 2017, Intel Corporation. All rights reserved.<BR>
5 (C) Copyright 2013-2015 Hewlett-Packard Development Company, L.P.<BR>
6 (C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>
7 This program and the accompanying materials
8 are licensed and made available under the terms and conditions of the BSD License
9 which accompanies this distribution. The full text of the license may be found at
10 http://opensource.org/licenses/bsd-license.php
12 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
13 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
17 #include "UefiShellDebug1CommandsLib.h"
18 #include <Protocol/PciRootBridgeIo.h>
19 #include <Library/ShellLib.h>
20 #include <IndustryStandard/Pci.h>
21 #include <IndustryStandard/Acpi.h>
25 // Printable strings for Pci class code
28 CHAR16
*BaseClass
; // Pointer to the PCI base class string
29 CHAR16
*SubClass
; // Pointer to the PCI sub class string
30 CHAR16
*PIFClass
; // Pointer to the PCI programming interface string
34 // a structure holding a single entry, which also points to its lower level
37 typedef struct PCI_CLASS_ENTRY_TAG
{
38 UINT8 Code
; // Class, subclass or I/F code
39 CHAR16
*DescText
; // Description string
40 struct PCI_CLASS_ENTRY_TAG
*LowerLevelClass
; // Subclass or I/F if any
44 // Declarations of entries which contain printable strings for class codes
45 // in PCI configuration space
47 PCI_CLASS_ENTRY PCIBlankEntry
[];
48 PCI_CLASS_ENTRY PCISubClass_00
[];
49 PCI_CLASS_ENTRY PCISubClass_01
[];
50 PCI_CLASS_ENTRY PCISubClass_02
[];
51 PCI_CLASS_ENTRY PCISubClass_03
[];
52 PCI_CLASS_ENTRY PCISubClass_04
[];
53 PCI_CLASS_ENTRY PCISubClass_05
[];
54 PCI_CLASS_ENTRY PCISubClass_06
[];
55 PCI_CLASS_ENTRY PCISubClass_07
[];
56 PCI_CLASS_ENTRY PCISubClass_08
[];
57 PCI_CLASS_ENTRY PCISubClass_09
[];
58 PCI_CLASS_ENTRY PCISubClass_0a
[];
59 PCI_CLASS_ENTRY PCISubClass_0b
[];
60 PCI_CLASS_ENTRY PCISubClass_0c
[];
61 PCI_CLASS_ENTRY PCISubClass_0d
[];
62 PCI_CLASS_ENTRY PCISubClass_0e
[];
63 PCI_CLASS_ENTRY PCISubClass_0f
[];
64 PCI_CLASS_ENTRY PCISubClass_10
[];
65 PCI_CLASS_ENTRY PCISubClass_11
[];
66 PCI_CLASS_ENTRY PCISubClass_12
[];
67 PCI_CLASS_ENTRY PCISubClass_13
[];
68 PCI_CLASS_ENTRY PCIPIFClass_0100
[];
69 PCI_CLASS_ENTRY PCIPIFClass_0101
[];
70 PCI_CLASS_ENTRY PCIPIFClass_0105
[];
71 PCI_CLASS_ENTRY PCIPIFClass_0106
[];
72 PCI_CLASS_ENTRY PCIPIFClass_0107
[];
73 PCI_CLASS_ENTRY PCIPIFClass_0108
[];
74 PCI_CLASS_ENTRY PCIPIFClass_0109
[];
75 PCI_CLASS_ENTRY PCIPIFClass_0300
[];
76 PCI_CLASS_ENTRY PCIPIFClass_0604
[];
77 PCI_CLASS_ENTRY PCIPIFClass_0609
[];
78 PCI_CLASS_ENTRY PCIPIFClass_060b
[];
79 PCI_CLASS_ENTRY PCIPIFClass_0700
[];
80 PCI_CLASS_ENTRY PCIPIFClass_0701
[];
81 PCI_CLASS_ENTRY PCIPIFClass_0703
[];
82 PCI_CLASS_ENTRY PCIPIFClass_0800
[];
83 PCI_CLASS_ENTRY PCIPIFClass_0801
[];
84 PCI_CLASS_ENTRY PCIPIFClass_0802
[];
85 PCI_CLASS_ENTRY PCIPIFClass_0803
[];
86 PCI_CLASS_ENTRY PCIPIFClass_0904
[];
87 PCI_CLASS_ENTRY PCIPIFClass_0c00
[];
88 PCI_CLASS_ENTRY PCIPIFClass_0c03
[];
89 PCI_CLASS_ENTRY PCIPIFClass_0c07
[];
90 PCI_CLASS_ENTRY PCIPIFClass_0d01
[];
91 PCI_CLASS_ENTRY PCIPIFClass_0e00
[];
94 // Base class strings entries
96 PCI_CLASS_ENTRY gClassStringList
[] = {
104 L
"Mass Storage Controller",
109 L
"Network Controller",
114 L
"Display Controller",
119 L
"Multimedia Device",
124 L
"Memory Controller",
134 L
"Simple Communications Controllers",
139 L
"Base System Peripherals",
159 L
"Serial Bus Controllers",
164 L
"Wireless Controllers",
169 L
"Intelligent IO Controllers",
174 L
"Satellite Communications Controllers",
179 L
"Encryption/Decryption Controllers",
184 L
"Data Acquisition & Signal Processing Controllers",
189 L
"Processing Accelerators",
194 L
"Non-Essential Instrumentation",
199 L
"Device does not fit in any defined classes",
205 /* null string ends the list */NULL
210 // Subclass strings entries
212 PCI_CLASS_ENTRY PCIBlankEntry
[] = {
221 /* null string ends the list */NULL
225 PCI_CLASS_ENTRY PCISubClass_00
[] = {
228 L
"All devices other than VGA",
233 L
"VGA-compatible devices",
239 /* null string ends the list */NULL
243 PCI_CLASS_ENTRY PCISubClass_01
[] = {
256 L
"Floppy disk controller",
271 L
"ATA controller with ADMA interface",
276 L
"Serial ATA controller",
281 L
"Serial Attached SCSI (SAS) controller ",
286 L
"Non-volatile memory subsystem",
291 L
"Universal Flash Storage (UFS) controller ",
296 L
"Other mass storage controller",
302 /* null string ends the list */NULL
306 PCI_CLASS_ENTRY PCISubClass_02
[] = {
309 L
"Ethernet controller",
314 L
"Token ring controller",
334 L
"WorldFip controller",
339 L
"PICMG 2.14 Multi Computing",
344 L
"InfiniBand controller",
349 L
"Other network controller",
355 /* null string ends the list */NULL
359 PCI_CLASS_ENTRY PCISubClass_03
[] = {
362 L
"VGA/8514 controller",
377 L
"Other display controller",
383 /* null string ends the list */PCIBlankEntry
387 PCI_CLASS_ENTRY PCISubClass_04
[] = {
400 L
"Computer Telephony device",
405 L
"Mixed mode device",
410 L
"Other multimedia device",
416 /* null string ends the list */NULL
420 PCI_CLASS_ENTRY PCISubClass_05
[] = {
423 L
"RAM memory controller",
428 L
"Flash memory controller",
433 L
"Other memory controller",
439 /* null string ends the list */NULL
443 PCI_CLASS_ENTRY PCISubClass_06
[] = {
461 L
"PCI/Micro Channel bridge",
471 L
"PCI/PCMCIA bridge",
491 L
"Semi-transparent PCI-to-PCI bridge",
496 L
"InfiniBand-to-PCI host bridge",
501 L
"Advanced Switching to PCI host bridge",
506 L
"Other bridge type",
512 /* null string ends the list */NULL
516 PCI_CLASS_ENTRY PCISubClass_07
[] = {
519 L
"Serial controller",
529 L
"Multiport serial controller",
539 L
"GPIB (IEEE 488.1/2) controller",
549 L
"Other communication device",
555 /* null string ends the list */NULL
559 PCI_CLASS_ENTRY PCISubClass_08
[] = {
582 L
"Generic PCI Hot-Plug controller",
587 L
"SD Host controller",
597 L
"Root Complex Event Collector",
602 L
"Other system peripheral",
608 /* null string ends the list */NULL
612 PCI_CLASS_ENTRY PCISubClass_09
[] = {
615 L
"Keyboard controller",
630 L
"Scanner controller",
635 L
"Gameport controller",
640 L
"Other input controller",
646 /* null string ends the list */NULL
650 PCI_CLASS_ENTRY PCISubClass_0a
[] = {
653 L
"Generic docking station",
658 L
"Other type of docking station",
664 /* null string ends the list */NULL
668 PCI_CLASS_ENTRY PCISubClass_0b
[] = {
712 /* null string ends the list */NULL
716 PCI_CLASS_ENTRY PCISubClass_0c
[] = {
744 L
"System Management Bus",
759 L
"SERCOS Interface Standard (IEC 61491)",
775 /* null string ends the list */NULL
779 PCI_CLASS_ENTRY PCISubClass_0d
[] = {
782 L
"iRDA compatible controller",
807 L
"Ethernet (802.11a - 5 GHz)",
812 L
"Ethernet (802.11b - 2.4 GHz)",
817 L
"Other type of wireless controller",
823 /* null string ends the list */NULL
827 PCI_CLASS_ENTRY PCISubClass_0e
[] = {
836 /* null string ends the list */NULL
840 PCI_CLASS_ENTRY PCISubClass_0f
[] = {
863 L
"Other satellite communication controller",
869 /* null string ends the list */NULL
873 PCI_CLASS_ENTRY PCISubClass_10
[] = {
876 L
"Network & computing Encrypt/Decrypt",
881 L
"Entertainment Encrypt/Decrypt",
886 L
"Other Encrypt/Decrypt",
892 /* null string ends the list */NULL
896 PCI_CLASS_ENTRY PCISubClass_11
[] = {
904 L
"Performance Counters",
909 L
"Communications synchronization plus time and frequency test/measurement ",
919 L
"Other DAQ & SP controllers",
925 /* null string ends the list */NULL
929 PCI_CLASS_ENTRY PCISubClass_12
[] = {
932 L
"Processing Accelerator",
938 /* null string ends the list */NULL
942 PCI_CLASS_ENTRY PCISubClass_13
[] = {
945 L
"Non-Essential Instrumentation Function",
951 /* null string ends the list */NULL
956 // Programming Interface entries
958 PCI_CLASS_ENTRY PCIPIFClass_0100
[] = {
966 L
"SCSI storage device SOP using PQI",
971 L
"SCSI controller SOP using PQI",
976 L
"SCSI storage device and controller SOP using PQI",
981 L
"SCSI storage device SOP using NVMe",
987 /* null string ends the list */NULL
991 PCI_CLASS_ENTRY PCIPIFClass_0101
[] = {
1019 L
"OM-primary, OM-secondary",
1024 L
"PI-primary, OM-secondary",
1029 L
"OM/PI-primary, OM-secondary",
1039 L
"OM-primary, PI-secondary",
1044 L
"PI-primary, PI-secondary",
1049 L
"OM/PI-primary, PI-secondary",
1059 L
"OM-primary, OM/PI-secondary",
1064 L
"PI-primary, OM/PI-secondary",
1069 L
"OM/PI-primary, OM/PI-secondary",
1079 L
"Master, OM-primary",
1084 L
"Master, PI-primary",
1089 L
"Master, OM/PI-primary",
1094 L
"Master, OM-secondary",
1099 L
"Master, OM-primary, OM-secondary",
1104 L
"Master, PI-primary, OM-secondary",
1109 L
"Master, OM/PI-primary, OM-secondary",
1114 L
"Master, OM-secondary",
1119 L
"Master, OM-primary, PI-secondary",
1124 L
"Master, PI-primary, PI-secondary",
1129 L
"Master, OM/PI-primary, PI-secondary",
1134 L
"Master, OM-secondary",
1139 L
"Master, OM-primary, OM/PI-secondary",
1144 L
"Master, PI-primary, OM/PI-secondary",
1149 L
"Master, OM/PI-primary, OM/PI-secondary",
1155 /* null string ends the list */NULL
1159 PCI_CLASS_ENTRY PCIPIFClass_0105
[] = {
1167 L
"Continuous operation",
1173 /* null string ends the list */NULL
1177 PCI_CLASS_ENTRY PCIPIFClass_0106
[] = {
1190 L
"Serial Storage Bus",
1196 /* null string ends the list */NULL
1200 PCI_CLASS_ENTRY PCIPIFClass_0107
[] = {
1214 /* null string ends the list */NULL
1218 PCI_CLASS_ENTRY PCIPIFClass_0108
[] = {
1237 /* null string ends the list */NULL
1241 PCI_CLASS_ENTRY PCIPIFClass_0109
[] = {
1255 /* null string ends the list */NULL
1259 PCI_CLASS_ENTRY PCIPIFClass_0300
[] = {
1273 /* null string ends the list */NULL
1277 PCI_CLASS_ENTRY PCIPIFClass_0604
[] = {
1285 L
"Subtractive decode",
1291 /* null string ends the list */NULL
1295 PCI_CLASS_ENTRY PCIPIFClass_0609
[] = {
1298 L
"Primary PCI bus side facing the system host processor",
1303 L
"Secondary PCI bus side facing the system host processor",
1309 /* null string ends the list */NULL
1313 PCI_CLASS_ENTRY PCIPIFClass_060b
[] = {
1321 L
"ASI-SIG Defined Portal",
1327 /* null string ends the list */NULL
1331 PCI_CLASS_ENTRY PCIPIFClass_0700
[] = {
1334 L
"Generic XT-compatible",
1339 L
"16450-compatible",
1344 L
"16550-compatible",
1349 L
"16650-compatible",
1354 L
"16750-compatible",
1359 L
"16850-compatible",
1364 L
"16950-compatible",
1370 /* null string ends the list */NULL
1374 PCI_CLASS_ENTRY PCIPIFClass_0701
[] = {
1387 L
"ECP 1.X-compliant",
1397 L
"IEEE 1284 target (not a controller)",
1403 /* null string ends the list */NULL
1407 PCI_CLASS_ENTRY PCIPIFClass_0703
[] = {
1415 L
"Hayes-compatible 16450",
1420 L
"Hayes-compatible 16550",
1425 L
"Hayes-compatible 16650",
1430 L
"Hayes-compatible 16750",
1436 /* null string ends the list */NULL
1440 PCI_CLASS_ENTRY PCIPIFClass_0800
[] = {
1463 L
"IO(x) APIC interrupt controller",
1469 /* null string ends the list */NULL
1473 PCI_CLASS_ENTRY PCIPIFClass_0801
[] = {
1492 /* null string ends the list */NULL
1496 PCI_CLASS_ENTRY PCIPIFClass_0802
[] = {
1515 /* null string ends the list */NULL
1519 PCI_CLASS_ENTRY PCIPIFClass_0803
[] = {
1538 /* null string ends the list */NULL
1542 PCI_CLASS_ENTRY PCIPIFClass_0904
[] = {
1556 /* null string ends the list */NULL
1560 PCI_CLASS_ENTRY PCIPIFClass_0c00
[] = {
1568 L
"Using 1394 OpenHCI spec",
1574 /* null string ends the list */NULL
1578 PCI_CLASS_ENTRY PCIPIFClass_0c03
[] = {
1601 L
"No specific programming interface",
1606 L
"(Not Host Controller)",
1612 /* null string ends the list */NULL
1616 PCI_CLASS_ENTRY PCIPIFClass_0c07
[] = {
1624 L
"Keyboard Controller Style",
1635 /* null string ends the list */NULL
1639 PCI_CLASS_ENTRY PCIPIFClass_0d01
[] = {
1642 L
"Consumer IR controller",
1647 L
"UWB Radio controller",
1653 /* null string ends the list */NULL
1657 PCI_CLASS_ENTRY PCIPIFClass_0e00
[] = {
1660 L
"Message FIFO at offset 40h",
1671 /* null string ends the list */NULL
1677 Generates printable Unicode strings that represent PCI device class,
1678 subclass and programmed I/F based on a value passed to the function.
1680 @param[in] ClassCode Value representing the PCI "Class Code" register read from a
1681 PCI device. The encodings are:
1682 bits 23:16 - Base Class Code
1683 bits 15:8 - Sub-Class Code
1684 bits 7:0 - Programming Interface
1685 @param[in, out] ClassStrings Pointer of PCI_CLASS_STRINGS structure, which contains
1686 printable class strings corresponding to ClassCode. The
1687 caller must not modify the strings that are pointed by
1688 the fields in ClassStrings.
1691 PciGetClassStrings (
1692 IN UINT32 ClassCode
,
1693 IN OUT PCI_CLASS_STRINGS
*ClassStrings
1698 PCI_CLASS_ENTRY
*CurrentClass
;
1701 // Assume no strings found
1703 ClassStrings
->BaseClass
= L
"UNDEFINED";
1704 ClassStrings
->SubClass
= L
"UNDEFINED";
1705 ClassStrings
->PIFClass
= L
"UNDEFINED";
1707 CurrentClass
= gClassStringList
;
1708 Code
= (UINT8
) (ClassCode
>> 16);
1712 // Go through all entries of the base class, until the entry with a matching
1713 // base class code is found. If reaches an entry with a null description
1714 // text, the last entry is met, which means no text for the base class was
1715 // found, so no more action is needed.
1717 while (Code
!= CurrentClass
[Index
].Code
) {
1718 if (NULL
== CurrentClass
[Index
].DescText
) {
1725 // A base class was found. Assign description, and check if this class has
1726 // sub-class defined. If sub-class defined, no more action is needed,
1727 // otherwise, continue to find description for the sub-class code.
1729 ClassStrings
->BaseClass
= CurrentClass
[Index
].DescText
;
1730 if (NULL
== CurrentClass
[Index
].LowerLevelClass
) {
1734 // find Subclass entry
1736 CurrentClass
= CurrentClass
[Index
].LowerLevelClass
;
1737 Code
= (UINT8
) (ClassCode
>> 8);
1741 // Go through all entries of the sub-class, until the entry with a matching
1742 // sub-class code is found. If reaches an entry with a null description
1743 // text, the last entry is met, which means no text for the sub-class was
1744 // found, so no more action is needed.
1746 while (Code
!= CurrentClass
[Index
].Code
) {
1747 if (NULL
== CurrentClass
[Index
].DescText
) {
1754 // A class was found for the sub-class code. Assign description, and check if
1755 // this sub-class has programming interface defined. If no, no more action is
1756 // needed, otherwise, continue to find description for the programming
1759 ClassStrings
->SubClass
= CurrentClass
[Index
].DescText
;
1760 if (NULL
== CurrentClass
[Index
].LowerLevelClass
) {
1764 // Find programming interface entry
1766 CurrentClass
= CurrentClass
[Index
].LowerLevelClass
;
1767 Code
= (UINT8
) ClassCode
;
1771 // Go through all entries of the I/F entries, until the entry with a
1772 // matching I/F code is found. If reaches an entry with a null description
1773 // text, the last entry is met, which means no text was found, so no more
1774 // action is needed.
1776 while (Code
!= CurrentClass
[Index
].Code
) {
1777 if (NULL
== CurrentClass
[Index
].DescText
) {
1784 // A class was found for the I/F code. Assign description, done!
1786 ClassStrings
->PIFClass
= CurrentClass
[Index
].DescText
;
1791 Print strings that represent PCI device class, subclass and programmed I/F.
1793 @param[in] ClassCodePtr Points to the memory which stores register Class Code in PCI
1794 configuration space.
1795 @param[in] IncludePIF If the printed string should include the programming I/F part
1799 IN UINT8
*ClassCodePtr
,
1800 IN BOOLEAN IncludePIF
1804 PCI_CLASS_STRINGS ClassStrings
;
1807 ClassCode
|= (UINT32
)ClassCodePtr
[0];
1808 ClassCode
|= (UINT32
)(ClassCodePtr
[1] << 8);
1809 ClassCode
|= (UINT32
)(ClassCodePtr
[2] << 16);
1812 // Get name from class code
1814 PciGetClassStrings (ClassCode
, &ClassStrings
);
1818 // Print base class, sub class, and programming inferface name
1820 ShellPrintEx (-1, -1, L
"%s - %s - %s",
1821 ClassStrings
.BaseClass
,
1822 ClassStrings
.SubClass
,
1823 ClassStrings
.PIFClass
1828 // Only print base class and sub class name
1830 ShellPrintEx (-1, -1, L
"%s - %s",
1831 ClassStrings
.BaseClass
,
1832 ClassStrings
.SubClass
1838 This function finds out the protocol which is in charge of the given
1839 segment, and its bus range covers the current bus number. It lookes
1840 each instances of RootBridgeIoProtocol handle, until the one meets the
1843 @param[in] HandleBuf Buffer which holds all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.
1844 @param[in] HandleCount Count of all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.
1845 @param[in] Segment Segment number of device we are dealing with.
1846 @param[in] Bus Bus number of device we are dealing with.
1847 @param[out] IoDev Handle used to access configuration space of PCI device.
1849 @retval EFI_SUCCESS The command completed successfully.
1850 @retval EFI_INVALID_PARAMETER Invalid parameter.
1854 PciFindProtocolInterface (
1855 IN EFI_HANDLE
*HandleBuf
,
1856 IN UINTN HandleCount
,
1859 OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
**IoDev
1863 This function gets the protocol interface from the given handle, and
1864 obtains its address space descriptors.
1866 @param[in] Handle The PCI_ROOT_BRIDIGE_IO_PROTOCOL handle.
1867 @param[out] IoDev Handle used to access configuration space of PCI device.
1868 @param[out] Descriptors Points to the address space descriptors.
1870 @retval EFI_SUCCESS The command completed successfully
1873 PciGetProtocolAndResource (
1874 IN EFI_HANDLE Handle
,
1875 OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
**IoDev
,
1876 OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
**Descriptors
1880 This function get the next bus range of given address space descriptors.
1881 It also moves the pointer backward a node, to get prepared to be called
1884 @param[in, out] Descriptors Points to current position of a serial of address space
1886 @param[out] MinBus The lower range of bus number.
1887 @param[out] MaxBus The upper range of bus number.
1888 @param[out] IsEnd Meet end of the serial of descriptors.
1890 @retval EFI_SUCCESS The command completed successfully.
1893 PciGetNextBusRange (
1894 IN OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
**Descriptors
,
1901 Explain the data in PCI configuration space. The part which is common for
1902 PCI device and bridge is interpreted in this function. It calls other
1903 functions to interpret data unique for device or bridge.
1905 @param[in] ConfigSpace Data in PCI configuration space.
1906 @param[in] Address Address used to access configuration space of this PCI device.
1907 @param[in] IoDev Handle used to access configuration space of PCI device.
1908 @param[in] EnhancedDump The print format for the dump data.
1910 @retval EFI_SUCCESS The command completed successfully.
1914 IN PCI_CONFIG_SPACE
*ConfigSpace
,
1916 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
,
1917 IN CONST UINT16 EnhancedDump
1921 Explain the device specific part of data in PCI configuration space.
1923 @param[in] Device Data in PCI configuration space.
1924 @param[in] Address Address used to access configuration space of this PCI device.
1925 @param[in] IoDev Handle used to access configuration space of PCI device.
1927 @retval EFI_SUCCESS The command completed successfully.
1930 PciExplainDeviceData (
1931 IN PCI_DEVICE_HEADER_TYPE_REGION
*Device
,
1933 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
1937 Explain the bridge specific part of data in PCI configuration space.
1939 @param[in] Bridge Bridge specific data region in PCI configuration space.
1940 @param[in] Address Address used to access configuration space of this PCI device.
1941 @param[in] IoDev Handle used to access configuration space of PCI device.
1943 @retval EFI_SUCCESS The command completed successfully.
1946 PciExplainBridgeData (
1947 IN PCI_BRIDGE_CONTROL_REGISTER
*Bridge
,
1949 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
1953 Explain the Base Address Register(Bar) in PCI configuration space.
1955 @param[in] Bar Points to the Base Address Register intended to interpret.
1956 @param[in] Command Points to the register Command.
1957 @param[in] Address Address used to access configuration space of this PCI device.
1958 @param[in] IoDev Handle used to access configuration space of PCI device.
1959 @param[in, out] Index The Index.
1961 @retval EFI_SUCCESS The command completed successfully.
1968 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
,
1973 Explain the cardbus specific part of data in PCI configuration space.
1975 @param[in] CardBus CardBus specific region of PCI configuration space.
1976 @param[in] Address Address used to access configuration space of this PCI device.
1977 @param[in] IoDev Handle used to access configuration space of PCI device.
1979 @retval EFI_SUCCESS The command completed successfully.
1982 PciExplainCardBusData (
1983 IN PCI_CARDBUS_CONTROL_REGISTER
*CardBus
,
1985 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
1989 Explain each meaningful bit of register Status. The definition of Status is
1990 slightly different depending on the PCI header type.
1992 @param[in] Status Points to the content of register Status.
1993 @param[in] MainStatus Indicates if this register is main status(not secondary
1995 @param[in] HeaderType Header type of this PCI device.
1997 @retval EFI_SUCCESS The command completed successfully.
2002 IN BOOLEAN MainStatus
,
2003 IN PCI_HEADER_TYPE HeaderType
2007 Explain each meaningful bit of register Command.
2009 @param[in] Command Points to the content of register Command.
2011 @retval EFI_SUCCESS The command completed successfully.
2019 Explain each meaningful bit of register Bridge Control.
2021 @param[in] BridgeControl Points to the content of register Bridge Control.
2022 @param[in] HeaderType The headertype.
2024 @retval EFI_SUCCESS The command completed successfully.
2027 PciExplainBridgeControl (
2028 IN UINT16
*BridgeControl
,
2029 IN PCI_HEADER_TYPE HeaderType
2033 Print each capability structure.
2035 @param[in] IoDev The pointer to the deivce.
2036 @param[in] Address The address to start at.
2037 @param[in] CapPtr The offset from the address.
2038 @param[in] EnhancedDump The print format for the dump data.
2040 @retval EFI_SUCCESS The operation was successful.
2043 PciExplainCapabilityStruct (
2044 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
,
2047 IN CONST UINT16 EnhancedDump
2051 Display Pcie device structure.
2053 @param[in] IoDev The pointer to the root pci protocol.
2054 @param[in] Address The Address to start at.
2055 @param[in] CapabilityPtr The offset from the address to start.
2056 @param[in] EnhancedDump The print format for the dump data.
2058 @retval EFI_SUCCESS The command completed successfully.
2059 @retval @retval EFI_SUCCESS Pci express extend space IO is not suppoted.
2062 PciExplainPciExpress (
2063 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
,
2065 IN UINT8 CapabilityPtr
,
2066 IN CONST UINT16 EnhancedDump
2070 Print out information of the capability information.
2072 @param[in] PciExpressCap The pointer to the structure about the device.
2074 @retval EFI_SUCCESS The operation was successful.
2078 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
2082 Print out information of the device capability information.
2084 @param[in] PciExpressCap The pointer to the structure about the device.
2086 @retval EFI_SUCCESS The operation was successful.
2089 ExplainPcieDeviceCap (
2090 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
2094 Print out information of the device control information.
2096 @param[in] PciExpressCap The pointer to the structure about the device.
2098 @retval EFI_SUCCESS The operation was successful.
2101 ExplainPcieDeviceControl (
2102 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
2106 Print out information of the device status information.
2108 @param[in] PciExpressCap The pointer to the structure about the device.
2110 @retval EFI_SUCCESS The operation was successful.
2113 ExplainPcieDeviceStatus (
2114 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
2118 Print out information of the device link information.
2120 @param[in] PciExpressCap The pointer to the structure about the device.
2122 @retval EFI_SUCCESS The operation was successful.
2125 ExplainPcieLinkCap (
2126 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
2130 Print out information of the device link control information.
2132 @param[in] PciExpressCap The pointer to the structure about the device.
2134 @retval EFI_SUCCESS The operation was successful.
2137 ExplainPcieLinkControl (
2138 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
2142 Print out information of the device link status information.
2144 @param[in] PciExpressCap The pointer to the structure about the device.
2146 @retval EFI_SUCCESS The operation was successful.
2149 ExplainPcieLinkStatus (
2150 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
2154 Print out information of the device slot information.
2156 @param[in] PciExpressCap The pointer to the structure about the device.
2158 @retval EFI_SUCCESS The operation was successful.
2161 ExplainPcieSlotCap (
2162 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
2166 Print out information of the device slot control information.
2168 @param[in] PciExpressCap The pointer to the structure about the device.
2170 @retval EFI_SUCCESS The operation was successful.
2173 ExplainPcieSlotControl (
2174 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
2178 Print out information of the device slot status information.
2180 @param[in] PciExpressCap The pointer to the structure about the device.
2182 @retval EFI_SUCCESS The operation was successful.
2185 ExplainPcieSlotStatus (
2186 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
2190 Print out information of the device root information.
2192 @param[in] PciExpressCap The pointer to the structure about the device.
2194 @retval EFI_SUCCESS The operation was successful.
2197 ExplainPcieRootControl (
2198 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
2202 Print out information of the device root capability information.
2204 @param[in] PciExpressCap The pointer to the structure about the device.
2206 @retval EFI_SUCCESS The operation was successful.
2209 ExplainPcieRootCap (
2210 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
2214 Print out information of the device root status information.
2216 @param[in] PciExpressCap The pointer to the structure about the device.
2218 @retval EFI_SUCCESS The operation was successful.
2221 ExplainPcieRootStatus (
2222 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
2225 typedef EFI_STATUS (*PCIE_EXPLAIN_FUNCTION
) (IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
);
2231 } PCIE_CAPREG_FIELD_WIDTH
;
2234 PcieExplainTypeCommon
,
2235 PcieExplainTypeDevice
,
2236 PcieExplainTypeLink
,
2237 PcieExplainTypeSlot
,
2238 PcieExplainTypeRoot
,
2240 } PCIE_EXPLAIN_TYPE
;
2246 PCIE_CAPREG_FIELD_WIDTH Width
;
2247 PCIE_EXPLAIN_FUNCTION Func
;
2248 PCIE_EXPLAIN_TYPE Type
;
2249 } PCIE_EXPLAIN_STRUCT
;
2251 PCIE_EXPLAIN_STRUCT PcieExplainList
[] = {
2253 STRING_TOKEN (STR_PCIEX_CAPABILITY_CAPID
),
2257 PcieExplainTypeCommon
2260 STRING_TOKEN (STR_PCIEX_NEXTCAP_PTR
),
2264 PcieExplainTypeCommon
2267 STRING_TOKEN (STR_PCIEX_CAP_REGISTER
),
2271 PcieExplainTypeCommon
2274 STRING_TOKEN (STR_PCIEX_DEVICE_CAP
),
2277 ExplainPcieDeviceCap
,
2278 PcieExplainTypeDevice
2281 STRING_TOKEN (STR_PCIEX_DEVICE_CONTROL
),
2284 ExplainPcieDeviceControl
,
2285 PcieExplainTypeDevice
2288 STRING_TOKEN (STR_PCIEX_DEVICE_STATUS
),
2291 ExplainPcieDeviceStatus
,
2292 PcieExplainTypeDevice
2295 STRING_TOKEN (STR_PCIEX_LINK_CAPABILITIES
),
2302 STRING_TOKEN (STR_PCIEX_LINK_CONTROL
),
2305 ExplainPcieLinkControl
,
2309 STRING_TOKEN (STR_PCIEX_LINK_STATUS
),
2312 ExplainPcieLinkStatus
,
2316 STRING_TOKEN (STR_PCIEX_SLOT_CAPABILITIES
),
2323 STRING_TOKEN (STR_PCIEX_SLOT_CONTROL
),
2326 ExplainPcieSlotControl
,
2330 STRING_TOKEN (STR_PCIEX_SLOT_STATUS
),
2333 ExplainPcieSlotStatus
,
2337 STRING_TOKEN (STR_PCIEX_ROOT_CONTROL
),
2340 ExplainPcieRootControl
,
2344 STRING_TOKEN (STR_PCIEX_RSVDP
),
2351 STRING_TOKEN (STR_PCIEX_ROOT_STATUS
),
2354 ExplainPcieRootStatus
,
2360 (PCIE_CAPREG_FIELD_WIDTH
)0,
2369 PCI_CONFIG_SPACE
*mConfigSpace
= NULL
;
2370 STATIC CONST SHELL_PARAM_ITEM ParamList
[] = {
2373 {L
"-ec", TypeValue
},
2377 CHAR16
*DevicePortTypeTable
[] = {
2378 L
"PCI Express Endpoint",
2379 L
"Legacy PCI Express Endpoint",
2382 L
"Root Port of PCI Express Root Complex",
2383 L
"Upstream Port of PCI Express Switch",
2384 L
"Downstream Port of PCI Express Switch",
2385 L
"PCI Express to PCI/PCI-X Bridge",
2386 L
"PCI/PCI-X to PCI Express Bridge",
2387 L
"Root Complex Integrated Endpoint",
2388 L
"Root Complex Event Collector"
2391 CHAR16
*L0sLatencyStrTable
[] = {
2393 L
"64ns to less than 128ns",
2394 L
"128ns to less than 256ns",
2395 L
"256ns to less than 512ns",
2396 L
"512ns to less than 1us",
2397 L
"1us to less than 2us",
2402 CHAR16
*L1LatencyStrTable
[] = {
2404 L
"1us to less than 2us",
2405 L
"2us to less than 4us",
2406 L
"4us to less than 8us",
2407 L
"8us to less than 16us",
2408 L
"16us to less than 32us",
2413 CHAR16
*ASPMCtrlStrTable
[] = {
2415 L
"L0s Entry Enabled",
2416 L
"L1 Entry Enabled",
2417 L
"L0s and L1 Entry Enabled"
2420 CHAR16
*SlotPwrLmtScaleTable
[] = {
2427 CHAR16
*IndicatorTable
[] = {
2436 Function for 'pci' command.
2438 @param[in] ImageHandle Handle to the Image (NULL if Internal).
2439 @param[in] SystemTable Pointer to the System Table (NULL if Internal).
2443 ShellCommandRunPci (
2444 IN EFI_HANDLE ImageHandle
,
2445 IN EFI_SYSTEM_TABLE
*SystemTable
2453 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
;
2455 PCI_DEVICE_INDEPENDENT_REGION PciHeader
;
2456 PCI_CONFIG_SPACE ConfigSpace
;
2460 BOOLEAN ExplainData
;
2464 UINTN HandleBufSize
;
2465 EFI_HANDLE
*HandleBuf
;
2467 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
*Descriptors
;
2471 LIST_ENTRY
*Package
;
2472 CHAR16
*ProblemParam
;
2473 SHELL_STATUS ShellStatus
;
2476 UINT16 EnhancedDump
;
2478 ShellStatus
= SHELL_SUCCESS
;
2479 Status
= EFI_SUCCESS
;
2486 // initialize the shell lib (we must be in non-auto-init...)
2488 Status
= ShellInitialize();
2489 ASSERT_EFI_ERROR(Status
);
2491 Status
= CommandInit();
2492 ASSERT_EFI_ERROR(Status
);
2495 // parse the command line
2497 Status
= ShellCommandLineParse (ParamList
, &Package
, &ProblemParam
, TRUE
);
2498 if (EFI_ERROR(Status
)) {
2499 if (Status
== EFI_VOLUME_CORRUPTED
&& ProblemParam
!= NULL
) {
2500 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_GEN_PROBLEM
), gShellDebug1HiiHandle
, L
"pci", ProblemParam
);
2501 FreePool(ProblemParam
);
2502 ShellStatus
= SHELL_INVALID_PARAMETER
;
2508 if (ShellCommandLineGetCount(Package
) == 2) {
2509 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_GEN_TOO_FEW
), gShellDebug1HiiHandle
, L
"pci");
2510 ShellStatus
= SHELL_INVALID_PARAMETER
;
2514 if (ShellCommandLineGetCount(Package
) > 4) {
2515 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_GEN_TOO_MANY
), gShellDebug1HiiHandle
, L
"pci");
2516 ShellStatus
= SHELL_INVALID_PARAMETER
;
2519 if (ShellCommandLineGetFlag(Package
, L
"-ec") && ShellCommandLineGetValue(Package
, L
"-ec") == NULL
) {
2520 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_GEN_NO_VALUE
), gShellDebug1HiiHandle
, L
"pci", L
"-ec");
2521 ShellStatus
= SHELL_INVALID_PARAMETER
;
2524 if (ShellCommandLineGetFlag(Package
, L
"-s") && ShellCommandLineGetValue(Package
, L
"-s") == NULL
) {
2525 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_GEN_NO_VALUE
), gShellDebug1HiiHandle
, L
"pci", L
"-s");
2526 ShellStatus
= SHELL_INVALID_PARAMETER
;
2530 // Get all instances of PciRootBridgeIo. Allocate space for 1 EFI_HANDLE and
2531 // call LibLocateHandle(), if EFI_BUFFER_TOO_SMALL is returned, allocate enough
2532 // space for handles and call it again.
2534 HandleBufSize
= sizeof (EFI_HANDLE
);
2535 HandleBuf
= (EFI_HANDLE
*) AllocateZeroPool (HandleBufSize
);
2536 if (HandleBuf
== NULL
) {
2537 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_GEN_OUT_MEM
), gShellDebug1HiiHandle
, L
"pci");
2538 ShellStatus
= SHELL_OUT_OF_RESOURCES
;
2542 Status
= gBS
->LocateHandle (
2544 &gEfiPciRootBridgeIoProtocolGuid
,
2550 if (Status
== EFI_BUFFER_TOO_SMALL
) {
2551 HandleBuf
= ReallocatePool (sizeof (EFI_HANDLE
), HandleBufSize
, HandleBuf
);
2552 if (HandleBuf
== NULL
) {
2553 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_GEN_OUT_MEM
), gShellDebug1HiiHandle
, L
"pci");
2554 ShellStatus
= SHELL_OUT_OF_RESOURCES
;
2558 Status
= gBS
->LocateHandle (
2560 &gEfiPciRootBridgeIoProtocolGuid
,
2567 if (EFI_ERROR (Status
)) {
2568 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_GEN_PCIRBIO_NF
), gShellDebug1HiiHandle
, L
"pci");
2569 ShellStatus
= SHELL_NOT_FOUND
;
2573 HandleCount
= HandleBufSize
/ sizeof (EFI_HANDLE
);
2575 // Argument Count == 1(no other argument): enumerate all pci functions
2577 if (ShellCommandLineGetCount(Package
) == 1) {
2578 gST
->ConOut
->QueryMode (
2580 gST
->ConOut
->Mode
->Mode
,
2587 if ((ScreenSize
& 1) == 1) {
2594 // For each handle, which decides a segment and a bus number range,
2595 // enumerate all devices on it.
2597 for (Index
= 0; Index
< HandleCount
; Index
++) {
2598 Status
= PciGetProtocolAndResource (
2603 if (EFI_ERROR (Status
)) {
2604 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_PCI_HANDLE_CFG_ERR
), gShellDebug1HiiHandle
, L
"pci");
2605 ShellStatus
= SHELL_NOT_FOUND
;
2609 // No document say it's impossible for a RootBridgeIo protocol handle
2610 // to have more than one address space descriptors, so find out every
2611 // bus range and for each of them do device enumeration.
2614 Status
= PciGetNextBusRange (&Descriptors
, &MinBus
, &MaxBus
, &IsEnd
);
2616 if (EFI_ERROR (Status
)) {
2617 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_PCI_BUS_RANGE_ERR
), gShellDebug1HiiHandle
, L
"pci");
2618 ShellStatus
= SHELL_NOT_FOUND
;
2626 for (Bus
= MinBus
; Bus
<= MaxBus
; Bus
++) {
2628 // For each devices, enumerate all functions it contains
2630 for (Device
= 0; Device
<= PCI_MAX_DEVICE
; Device
++) {
2632 // For each function, read its configuration space and print summary
2634 for (Func
= 0; Func
<= PCI_MAX_FUNC
; Func
++) {
2635 if (ShellGetExecutionBreakFlag ()) {
2636 ShellStatus
= SHELL_ABORTED
;
2639 Address
= EFI_PCI_ADDRESS (Bus
, Device
, Func
, 0);
2649 // If VendorId = 0xffff, there does not exist a device at this
2650 // location. For each device, if there is any function on it,
2651 // there must be 1 function at Function 0. So if Func = 0, there
2652 // will be no more functions in the same device, so we can break
2653 // loop to deal with the next device.
2655 if (PciHeader
.VendorId
== 0xffff && Func
== 0) {
2659 if (PciHeader
.VendorId
!= 0xffff) {
2662 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_PCI_TITLE
), gShellDebug1HiiHandle
);
2670 sizeof (PciHeader
) / sizeof (UINT32
),
2675 -1, -1, NULL
, STRING_TOKEN (STR_PCI_LINE_P1
), gShellDebug1HiiHandle
,
2676 IoDev
->SegmentNumber
,
2682 PciPrintClassCode (PciHeader
.ClassCode
, FALSE
);
2684 -1, -1, NULL
, STRING_TOKEN (STR_PCI_LINE_P2
), gShellDebug1HiiHandle
,
2687 PciHeader
.ClassCode
[0]
2691 if (ScreenCount
>= ScreenSize
&& ScreenSize
!= 0) {
2693 // If ScreenSize == 0 we have the console redirected so don't
2699 // If this is not a multi-function device, we can leave the loop
2700 // to deal with the next device.
2702 if (Func
== 0 && ((PciHeader
.HeaderType
& HEADER_TYPE_MULTI_FUNCTION
) == 0x00)) {
2710 // If Descriptor is NULL, Configuration() returns EFI_UNSUPPRORED,
2711 // we assume the bus range is 0~PCI_MAX_BUS. After enumerated all
2712 // devices on all bus, we can leave loop.
2714 if (Descriptors
== NULL
) {
2720 Status
= EFI_SUCCESS
;
2724 ExplainData
= FALSE
;
2729 EnhancedDump
= 0xFFFF;
2730 if (ShellCommandLineGetFlag(Package
, L
"-i")) {
2734 Temp
= ShellCommandLineGetValue(Package
, L
"-s");
2737 // Input converted to hexadecimal number.
2739 if (!EFI_ERROR (ShellConvertStringToUint64 (Temp
, &RetVal
, TRUE
, TRUE
))) {
2740 Segment
= (UINT16
) RetVal
;
2742 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_GEN_PARAM_INV_HEX
), gShellDebug1HiiHandle
, L
"pci", Temp
);
2743 ShellStatus
= SHELL_INVALID_PARAMETER
;
2749 // The first Argument(except "-i") is assumed to be Bus number, second
2750 // to be Device number, and third to be Func number.
2752 Temp
= ShellCommandLineGetRawValue(Package
, 1);
2755 // Input converted to hexadecimal number.
2757 if (!EFI_ERROR (ShellConvertStringToUint64 (Temp
, &RetVal
, TRUE
, TRUE
))) {
2758 Bus
= (UINT16
) RetVal
;
2760 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_GEN_PARAM_INV_HEX
), gShellDebug1HiiHandle
, L
"pci", Temp
);
2761 ShellStatus
= SHELL_INVALID_PARAMETER
;
2765 if (Bus
> PCI_MAX_BUS
) {
2766 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_GEN_PARAM_INV
), gShellDebug1HiiHandle
, L
"pci", Temp
);
2767 ShellStatus
= SHELL_INVALID_PARAMETER
;
2771 Temp
= ShellCommandLineGetRawValue(Package
, 2);
2774 // Input converted to hexadecimal number.
2776 if (!EFI_ERROR (ShellConvertStringToUint64 (Temp
, &RetVal
, TRUE
, TRUE
))) {
2777 Device
= (UINT16
) RetVal
;
2779 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_GEN_PARAM_INV_HEX
), gShellDebug1HiiHandle
, L
"pci", Temp
);
2780 ShellStatus
= SHELL_INVALID_PARAMETER
;
2784 if (Device
> PCI_MAX_DEVICE
){
2785 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_GEN_PARAM_INV
), gShellDebug1HiiHandle
, L
"pci", Temp
);
2786 ShellStatus
= SHELL_INVALID_PARAMETER
;
2791 Temp
= ShellCommandLineGetRawValue(Package
, 3);
2794 // Input converted to hexadecimal number.
2796 if (!EFI_ERROR (ShellConvertStringToUint64 (Temp
, &RetVal
, TRUE
, TRUE
))) {
2797 Func
= (UINT16
) RetVal
;
2799 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_GEN_PARAM_INV_HEX
), gShellDebug1HiiHandle
, L
"pci", Temp
);
2800 ShellStatus
= SHELL_INVALID_PARAMETER
;
2804 if (Func
> PCI_MAX_FUNC
){
2805 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_GEN_PARAM_INV
), gShellDebug1HiiHandle
, L
"pci", Temp
);
2806 ShellStatus
= SHELL_INVALID_PARAMETER
;
2811 Temp
= ShellCommandLineGetValue (Package
, L
"-ec");
2814 // Input converted to hexadecimal number.
2816 if (!EFI_ERROR (ShellConvertStringToUint64 (Temp
, &RetVal
, TRUE
, TRUE
))) {
2817 EnhancedDump
= (UINT16
) RetVal
;
2819 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_GEN_PARAM_INV_HEX
), gShellDebug1HiiHandle
, L
"pci", Temp
);
2820 ShellStatus
= SHELL_INVALID_PARAMETER
;
2826 // Find the protocol interface who's in charge of current segment, and its
2827 // bus range covers the current bus
2829 Status
= PciFindProtocolInterface (
2837 if (EFI_ERROR (Status
)) {
2839 -1, -1, NULL
, STRING_TOKEN (STR_PCI_NO_FIND
), gShellDebug1HiiHandle
, L
"pci",
2843 ShellStatus
= SHELL_NOT_FOUND
;
2847 Address
= EFI_PCI_ADDRESS (Bus
, Device
, Func
, 0);
2848 Status
= IoDev
->Pci
.Read (
2852 sizeof (ConfigSpace
),
2856 if (EFI_ERROR (Status
)) {
2857 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_PCI_NO_CFG
), gShellDebug1HiiHandle
, L
"pci");
2858 ShellStatus
= SHELL_ACCESS_DENIED
;
2862 mConfigSpace
= &ConfigSpace
;
2867 STRING_TOKEN (STR_PCI_INFO
),
2868 gShellDebug1HiiHandle
,
2880 // Dump standard header of configuration space
2882 SizeOfHeader
= sizeof (ConfigSpace
.Common
) + sizeof (ConfigSpace
.NonCommon
);
2884 DumpHex (2, 0, SizeOfHeader
, &ConfigSpace
);
2885 ShellPrintEx(-1,-1, L
"\r\n");
2888 // Dump device dependent Part of configuration space
2893 sizeof (ConfigSpace
) - SizeOfHeader
,
2898 // If "-i" appears in command line, interpret data in configuration space
2901 Status
= PciExplainData (&ConfigSpace
, Address
, IoDev
, EnhancedDump
);
2905 if (HandleBuf
!= NULL
) {
2906 FreePool (HandleBuf
);
2908 if (Package
!= NULL
) {
2909 ShellCommandLineFreeVarList (Package
);
2911 mConfigSpace
= NULL
;
2916 This function finds out the protocol which is in charge of the given
2917 segment, and its bus range covers the current bus number. It lookes
2918 each instances of RootBridgeIoProtocol handle, until the one meets the
2921 @param[in] HandleBuf Buffer which holds all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.
2922 @param[in] HandleCount Count of all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.
2923 @param[in] Segment Segment number of device we are dealing with.
2924 @param[in] Bus Bus number of device we are dealing with.
2925 @param[out] IoDev Handle used to access configuration space of PCI device.
2927 @retval EFI_SUCCESS The command completed successfully.
2928 @retval EFI_INVALID_PARAMETER Invalid parameter.
2932 PciFindProtocolInterface (
2933 IN EFI_HANDLE
*HandleBuf
,
2934 IN UINTN HandleCount
,
2937 OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
**IoDev
2942 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
*Descriptors
;
2948 // Go through all handles, until the one meets the criteria is found
2950 for (Index
= 0; Index
< HandleCount
; Index
++) {
2951 Status
= PciGetProtocolAndResource (HandleBuf
[Index
], IoDev
, &Descriptors
);
2952 if (EFI_ERROR (Status
)) {
2956 // When Descriptors == NULL, the Configuration() is not implemented,
2957 // so we only check the Segment number
2959 if (Descriptors
== NULL
&& Segment
== (*IoDev
)->SegmentNumber
) {
2963 if ((*IoDev
)->SegmentNumber
!= Segment
) {
2968 Status
= PciGetNextBusRange (&Descriptors
, &MinBus
, &MaxBus
, &IsEnd
);
2969 if (EFI_ERROR (Status
)) {
2977 if (MinBus
<= Bus
&& MaxBus
>= Bus
) {
2983 return EFI_NOT_FOUND
;
2987 This function gets the protocol interface from the given handle, and
2988 obtains its address space descriptors.
2990 @param[in] Handle The PCI_ROOT_BRIDIGE_IO_PROTOCOL handle.
2991 @param[out] IoDev Handle used to access configuration space of PCI device.
2992 @param[out] Descriptors Points to the address space descriptors.
2994 @retval EFI_SUCCESS The command completed successfully
2997 PciGetProtocolAndResource (
2998 IN EFI_HANDLE Handle
,
2999 OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
**IoDev
,
3000 OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
**Descriptors
3006 // Get inferface from protocol
3008 Status
= gBS
->HandleProtocol (
3010 &gEfiPciRootBridgeIoProtocolGuid
,
3014 if (EFI_ERROR (Status
)) {
3018 // Call Configuration() to get address space descriptors
3020 Status
= (*IoDev
)->Configuration (*IoDev
, (VOID
**)Descriptors
);
3021 if (Status
== EFI_UNSUPPORTED
) {
3022 *Descriptors
= NULL
;
3031 This function get the next bus range of given address space descriptors.
3032 It also moves the pointer backward a node, to get prepared to be called
3035 @param[in, out] Descriptors Points to current position of a serial of address space
3037 @param[out] MinBus The lower range of bus number.
3038 @param[out] MaxBus The upper range of bus number.
3039 @param[out] IsEnd Meet end of the serial of descriptors.
3041 @retval EFI_SUCCESS The command completed successfully.
3044 PciGetNextBusRange (
3045 IN OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
**Descriptors
,
3054 // When *Descriptors is NULL, Configuration() is not implemented, so assume
3055 // range is 0~PCI_MAX_BUS
3057 if ((*Descriptors
) == NULL
) {
3059 *MaxBus
= PCI_MAX_BUS
;
3063 // *Descriptors points to one or more address space descriptors, which
3064 // ends with a end tagged descriptor. Examine each of the descriptors,
3065 // if a bus typed one is found and its bus range covers bus, this handle
3066 // is the handle we are looking for.
3069 while ((*Descriptors
)->Desc
!= ACPI_END_TAG_DESCRIPTOR
) {
3070 if ((*Descriptors
)->ResType
== ACPI_ADDRESS_SPACE_TYPE_BUS
) {
3071 *MinBus
= (UINT16
) (*Descriptors
)->AddrRangeMin
;
3072 *MaxBus
= (UINT16
) (*Descriptors
)->AddrRangeMax
;
3074 return (EFI_SUCCESS
);
3080 if ((*Descriptors
)->Desc
== ACPI_END_TAG_DESCRIPTOR
) {
3088 Explain the data in PCI configuration space. The part which is common for
3089 PCI device and bridge is interpreted in this function. It calls other
3090 functions to interpret data unique for device or bridge.
3092 @param[in] ConfigSpace Data in PCI configuration space.
3093 @param[in] Address Address used to access configuration space of this PCI device.
3094 @param[in] IoDev Handle used to access configuration space of PCI device.
3095 @param[in] EnhancedDump The print format for the dump data.
3097 @retval EFI_SUCCESS The command completed successfully.
3101 IN PCI_CONFIG_SPACE
*ConfigSpace
,
3103 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
,
3104 IN CONST UINT16 EnhancedDump
3107 PCI_DEVICE_INDEPENDENT_REGION
*Common
;
3108 PCI_HEADER_TYPE HeaderType
;
3112 Common
= &(ConfigSpace
->Common
);
3114 ShellPrintEx (-1, -1, L
"\r\n");
3117 // Print Vendor Id and Device Id
3119 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_PCI_LINE_VID_DID
), gShellDebug1HiiHandle
,
3120 INDEX_OF (&(Common
->VendorId
)),
3122 INDEX_OF (&(Common
->DeviceId
)),
3127 // Print register Command
3129 PciExplainCommand (&(Common
->Command
));
3132 // Print register Status
3134 PciExplainStatus (&(Common
->Status
), TRUE
, PciUndefined
);
3137 // Print register Revision ID
3139 ShellPrintEx(-1, -1, L
"\r\n");
3140 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_PCI_LINE_RID
), gShellDebug1HiiHandle
,
3141 INDEX_OF (&(Common
->RevisionID
)),
3146 // Print register BIST
3148 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_PCI_LINE_BIST
), gShellDebug1HiiHandle
, INDEX_OF (&(Common
->BIST
)));
3149 if ((Common
->BIST
& BIT7
) != 0) {
3150 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_PCI_LINE_CAP
), gShellDebug1HiiHandle
, 0x0f & Common
->BIST
);
3152 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_PCI_LINE_CAP_NO
), gShellDebug1HiiHandle
);
3155 // Print register Cache Line Size
3157 ShellPrintHiiEx(-1, -1, NULL
,
3158 STRING_TOKEN (STR_PCI2_CACHE_LINE_SIZE
),
3159 gShellDebug1HiiHandle
,
3160 INDEX_OF (&(Common
->CacheLineSize
)),
3161 Common
->CacheLineSize
3165 // Print register Latency Timer
3167 ShellPrintHiiEx(-1, -1, NULL
,
3168 STRING_TOKEN (STR_PCI2_LATENCY_TIMER
),
3169 gShellDebug1HiiHandle
,
3170 INDEX_OF (&(Common
->LatencyTimer
)),
3171 Common
->LatencyTimer
3175 // Print register Header Type
3177 ShellPrintHiiEx(-1, -1, NULL
,
3178 STRING_TOKEN (STR_PCI2_HEADER_TYPE
),
3179 gShellDebug1HiiHandle
,
3180 INDEX_OF (&(Common
->HeaderType
)),
3184 if ((Common
->HeaderType
& BIT7
) != 0) {
3185 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_MULTI_FUNCTION
), gShellDebug1HiiHandle
);
3188 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_SINGLE_FUNCTION
), gShellDebug1HiiHandle
);
3191 HeaderType
= (PCI_HEADER_TYPE
)(UINT8
) (Common
->HeaderType
& 0x7f);
3192 switch (HeaderType
) {
3194 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_PCI_DEVICE
), gShellDebug1HiiHandle
);
3198 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_P2P_BRIDGE
), gShellDebug1HiiHandle
);
3201 case PciCardBusBridge
:
3202 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_CARDBUS_BRIDGE
), gShellDebug1HiiHandle
);
3206 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_RESERVED
), gShellDebug1HiiHandle
);
3207 HeaderType
= PciUndefined
;
3211 // Print register Class Code
3213 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_CLASS
), gShellDebug1HiiHandle
);
3214 PciPrintClassCode ((UINT8
*) Common
->ClassCode
, TRUE
);
3215 ShellPrintEx (-1, -1, L
"\r\n");
3217 if (ShellGetExecutionBreakFlag()) {
3222 // Interpret remaining part of PCI configuration header depending on
3226 Status
= EFI_SUCCESS
;
3227 switch (HeaderType
) {
3229 Status
= PciExplainDeviceData (
3230 &(ConfigSpace
->NonCommon
.Device
),
3234 CapPtr
= ConfigSpace
->NonCommon
.Device
.CapabilityPtr
;
3238 Status
= PciExplainBridgeData (
3239 &(ConfigSpace
->NonCommon
.Bridge
),
3243 CapPtr
= ConfigSpace
->NonCommon
.Bridge
.CapabilityPtr
;
3246 case PciCardBusBridge
:
3247 Status
= PciExplainCardBusData (
3248 &(ConfigSpace
->NonCommon
.CardBus
),
3252 CapPtr
= ConfigSpace
->NonCommon
.CardBus
.Cap_Ptr
;
3259 // If Status bit4 is 1, dump or explain capability structure
3261 if ((Common
->Status
) & EFI_PCI_STATUS_CAPABILITY
) {
3262 PciExplainCapabilityStruct (IoDev
, Address
, CapPtr
, EnhancedDump
);
3269 Explain the device specific part of data in PCI configuration space.
3271 @param[in] Device Data in PCI configuration space.
3272 @param[in] Address Address used to access configuration space of this PCI device.
3273 @param[in] IoDev Handle used to access configuration space of PCI device.
3275 @retval EFI_SUCCESS The command completed successfully.
3278 PciExplainDeviceData (
3279 IN PCI_DEVICE_HEADER_TYPE_REGION
*Device
,
3281 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
3290 // Print Base Address Registers(Bar). When Bar = 0, this Bar does not
3291 // exist. If these no Bar for this function, print "none", otherwise
3292 // list detail information about this Bar.
3294 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_BASE_ADDR
), gShellDebug1HiiHandle
, INDEX_OF (Device
->Bar
));
3297 BarCount
= sizeof (Device
->Bar
) / sizeof (Device
->Bar
[0]);
3298 for (Index
= 0; Index
< BarCount
; Index
++) {
3299 if (Device
->Bar
[Index
] == 0) {
3305 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_START_TYPE
), gShellDebug1HiiHandle
);
3306 ShellPrintEx (-1, -1, L
" --------------------------------------------------------------------------");
3309 Status
= PciExplainBar (
3310 &(Device
->Bar
[Index
]),
3311 &(mConfigSpace
->Common
.Command
),
3317 if (EFI_ERROR (Status
)) {
3323 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_NONE
), gShellDebug1HiiHandle
);
3326 ShellPrintEx (-1, -1, L
"\r\n --------------------------------------------------------------------------");
3330 // Print register Expansion ROM Base Address
3332 if ((Device
->ExpansionRomBar
& BIT0
) == 0) {
3333 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_EXPANSION_ROM_DISABLED
), gShellDebug1HiiHandle
, INDEX_OF (&(Device
->ExpansionRomBar
)));
3336 ShellPrintHiiEx(-1, -1, NULL
,
3337 STRING_TOKEN (STR_PCI2_EXPANSION_ROM_BASE
),
3338 gShellDebug1HiiHandle
,
3339 INDEX_OF (&(Device
->ExpansionRomBar
)),
3340 Device
->ExpansionRomBar
3344 // Print register Cardbus CIS ptr
3346 ShellPrintHiiEx(-1, -1, NULL
,
3347 STRING_TOKEN (STR_PCI2_CARDBUS_CIS
),
3348 gShellDebug1HiiHandle
,
3349 INDEX_OF (&(Device
->CISPtr
)),
3354 // Print register Sub-vendor ID and subsystem ID
3356 ShellPrintHiiEx(-1, -1, NULL
,
3357 STRING_TOKEN (STR_PCI2_SUB_VENDOR_ID
),
3358 gShellDebug1HiiHandle
,
3359 INDEX_OF (&(Device
->SubsystemVendorID
)),
3360 Device
->SubsystemVendorID
3363 ShellPrintHiiEx(-1, -1, NULL
,
3364 STRING_TOKEN (STR_PCI2_SUBSYSTEM_ID
),
3365 gShellDebug1HiiHandle
,
3366 INDEX_OF (&(Device
->SubsystemID
)),
3371 // Print register Capabilities Ptr
3373 ShellPrintHiiEx(-1, -1, NULL
,
3374 STRING_TOKEN (STR_PCI2_CAPABILITIES_PTR
),
3375 gShellDebug1HiiHandle
,
3376 INDEX_OF (&(Device
->CapabilityPtr
)),
3377 Device
->CapabilityPtr
3381 // Print register Interrupt Line and interrupt pin
3383 ShellPrintHiiEx(-1, -1, NULL
,
3384 STRING_TOKEN (STR_PCI2_INTERRUPT_LINE
),
3385 gShellDebug1HiiHandle
,
3386 INDEX_OF (&(Device
->InterruptLine
)),
3387 Device
->InterruptLine
3390 ShellPrintHiiEx(-1, -1, NULL
,
3391 STRING_TOKEN (STR_PCI2_INTERRUPT_PIN
),
3392 gShellDebug1HiiHandle
,
3393 INDEX_OF (&(Device
->InterruptPin
)),
3394 Device
->InterruptPin
3398 // Print register Min_Gnt and Max_Lat
3400 ShellPrintHiiEx(-1, -1, NULL
,
3401 STRING_TOKEN (STR_PCI2_MIN_GNT
),
3402 gShellDebug1HiiHandle
,
3403 INDEX_OF (&(Device
->MinGnt
)),
3407 ShellPrintHiiEx(-1, -1, NULL
,
3408 STRING_TOKEN (STR_PCI2_MAX_LAT
),
3409 gShellDebug1HiiHandle
,
3410 INDEX_OF (&(Device
->MaxLat
)),
3418 Explain the bridge specific part of data in PCI configuration space.
3420 @param[in] Bridge Bridge specific data region in PCI configuration space.
3421 @param[in] Address Address used to access configuration space of this PCI device.
3422 @param[in] IoDev Handle used to access configuration space of PCI device.
3424 @retval EFI_SUCCESS The command completed successfully.
3427 PciExplainBridgeData (
3428 IN PCI_BRIDGE_CONTROL_REGISTER
*Bridge
,
3430 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
3440 // Print Base Address Registers. When Bar = 0, this Bar does not
3441 // exist. If these no Bar for this function, print "none", otherwise
3442 // list detail information about this Bar.
3444 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_BASE_ADDRESS
), gShellDebug1HiiHandle
, INDEX_OF (&(Bridge
->Bar
)));
3447 BarCount
= sizeof (Bridge
->Bar
) / sizeof (Bridge
->Bar
[0]);
3449 for (Index
= 0; Index
< BarCount
; Index
++) {
3450 if (Bridge
->Bar
[Index
] == 0) {
3456 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_START_TYPE_2
), gShellDebug1HiiHandle
);
3457 ShellPrintEx (-1, -1, L
" --------------------------------------------------------------------------");
3460 Status
= PciExplainBar (
3461 &(Bridge
->Bar
[Index
]),
3462 &(mConfigSpace
->Common
.Command
),
3468 if (EFI_ERROR (Status
)) {
3474 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_NONE
), gShellDebug1HiiHandle
);
3476 ShellPrintEx (-1, -1, L
"\r\n --------------------------------------------------------------------------");
3480 // Expansion register ROM Base Address
3482 if ((Bridge
->ExpansionRomBAR
& BIT0
) == 0) {
3483 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_NO_EXPANSION_ROM
), gShellDebug1HiiHandle
, INDEX_OF (&(Bridge
->ExpansionRomBAR
)));
3486 ShellPrintHiiEx(-1, -1, NULL
,
3487 STRING_TOKEN (STR_PCI2_EXPANSION_ROM_BASE_2
),
3488 gShellDebug1HiiHandle
,
3489 INDEX_OF (&(Bridge
->ExpansionRomBAR
)),
3490 Bridge
->ExpansionRomBAR
3494 // Print Bus Numbers(Primary, Secondary, and Subordinate
3496 ShellPrintHiiEx(-1, -1, NULL
,
3497 STRING_TOKEN (STR_PCI2_BUS_NUMBERS
),
3498 gShellDebug1HiiHandle
,
3499 INDEX_OF (&(Bridge
->PrimaryBus
)),
3500 INDEX_OF (&(Bridge
->SecondaryBus
)),
3501 INDEX_OF (&(Bridge
->SubordinateBus
))
3504 ShellPrintEx (-1, -1, L
" ------------------------------------------------------\r\n");
3506 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_BRIDGE
), gShellDebug1HiiHandle
, Bridge
->PrimaryBus
);
3507 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_BRIDGE
), gShellDebug1HiiHandle
, Bridge
->SecondaryBus
);
3508 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_BRIDGE
), gShellDebug1HiiHandle
, Bridge
->SubordinateBus
);
3511 // Print register Secondary Latency Timer
3513 ShellPrintHiiEx(-1, -1, NULL
,
3514 STRING_TOKEN (STR_PCI2_SECONDARY_TIMER
),
3515 gShellDebug1HiiHandle
,
3516 INDEX_OF (&(Bridge
->SecondaryLatencyTimer
)),
3517 Bridge
->SecondaryLatencyTimer
3521 // Print register Secondary Status
3523 PciExplainStatus (&(Bridge
->SecondaryStatus
), FALSE
, PciP2pBridge
);
3526 // Print I/O and memory ranges this bridge forwards. There are 3 resource
3527 // types: I/O, memory, and pre-fetchable memory. For each resource type,
3528 // base and limit address are listed.
3530 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_RESOURCE_TYPE
), gShellDebug1HiiHandle
);
3531 ShellPrintEx (-1, -1, L
"----------------------------------------------------------------------\r\n");
3536 IoAddress32
= (Bridge
->IoBaseUpper16
<< 16 | Bridge
->IoBase
<< 8);
3537 IoAddress32
&= 0xfffff000;
3538 ShellPrintHiiEx(-1, -1, NULL
,
3539 STRING_TOKEN (STR_PCI2_TWO_VARS
),
3540 gShellDebug1HiiHandle
,
3541 INDEX_OF (&(Bridge
->IoBase
)),
3545 IoAddress32
= (Bridge
->IoLimitUpper16
<< 16 | Bridge
->IoLimit
<< 8);
3546 IoAddress32
|= 0x00000fff;
3547 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_ONE_VAR
), gShellDebug1HiiHandle
, IoAddress32
);
3550 // Memory Base & Limit
3552 ShellPrintHiiEx(-1, -1, NULL
,
3553 STRING_TOKEN (STR_PCI2_MEMORY
),
3554 gShellDebug1HiiHandle
,
3555 INDEX_OF (&(Bridge
->MemoryBase
)),
3556 (Bridge
->MemoryBase
<< 16) & 0xfff00000
3559 ShellPrintHiiEx(-1, -1, NULL
,
3560 STRING_TOKEN (STR_PCI2_ONE_VAR
),
3561 gShellDebug1HiiHandle
,
3562 (Bridge
->MemoryLimit
<< 16) | 0x000fffff
3566 // Pre-fetch-able Memory Base & Limit
3568 ShellPrintHiiEx(-1, -1, NULL
,
3569 STRING_TOKEN (STR_PCI2_PREFETCHABLE
),
3570 gShellDebug1HiiHandle
,
3571 INDEX_OF (&(Bridge
->PrefetchableMemoryBase
)),
3572 Bridge
->PrefetchableBaseUpper32
,
3573 (Bridge
->PrefetchableMemoryBase
<< 16) & 0xfff00000
3576 ShellPrintHiiEx(-1, -1, NULL
,
3577 STRING_TOKEN (STR_PCI2_TWO_VARS_2
),
3578 gShellDebug1HiiHandle
,
3579 Bridge
->PrefetchableLimitUpper32
,
3580 (Bridge
->PrefetchableMemoryLimit
<< 16) | 0x000fffff
3584 // Print register Capabilities Pointer
3586 ShellPrintHiiEx(-1, -1, NULL
,
3587 STRING_TOKEN (STR_PCI2_CAPABILITIES_PTR_2
),
3588 gShellDebug1HiiHandle
,
3589 INDEX_OF (&(Bridge
->CapabilityPtr
)),
3590 Bridge
->CapabilityPtr
3594 // Print register Bridge Control
3596 PciExplainBridgeControl (&(Bridge
->BridgeControl
), PciP2pBridge
);
3599 // Print register Interrupt Line & PIN
3601 ShellPrintHiiEx(-1, -1, NULL
,
3602 STRING_TOKEN (STR_PCI2_INTERRUPT_LINE_2
),
3603 gShellDebug1HiiHandle
,
3604 INDEX_OF (&(Bridge
->InterruptLine
)),
3605 Bridge
->InterruptLine
3608 ShellPrintHiiEx(-1, -1, NULL
,
3609 STRING_TOKEN (STR_PCI2_INTERRUPT_PIN
),
3610 gShellDebug1HiiHandle
,
3611 INDEX_OF (&(Bridge
->InterruptPin
)),
3612 Bridge
->InterruptPin
3619 Explain the Base Address Register(Bar) in PCI configuration space.
3621 @param[in] Bar Points to the Base Address Register intended to interpret.
3622 @param[in] Command Points to the register Command.
3623 @param[in] Address Address used to access configuration space of this PCI device.
3624 @param[in] IoDev Handle used to access configuration space of PCI device.
3625 @param[in, out] Index The Index.
3627 @retval EFI_SUCCESS The command completed successfully.
3634 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
,
3655 // According the bar type, list detail about this bar, for example: 32 or
3656 // 64 bits; pre-fetchable or not.
3658 if ((*Bar
& BIT0
) == 0) {
3660 // This bar is of memory type
3664 if ((*Bar
& BIT1
) == 0 && (*Bar
& BIT2
) == 0) {
3665 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_BAR
), gShellDebug1HiiHandle
, *Bar
& 0xfffffff0);
3666 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_MEM
), gShellDebug1HiiHandle
);
3667 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_32_BITS
), gShellDebug1HiiHandle
);
3669 } else if ((*Bar
& BIT1
) == 0 && (*Bar
& BIT2
) != 0) {
3671 CopyMem (&Bar64
, Bar
, sizeof (UINT64
));
3672 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_ONE_VAR_2
), gShellDebug1HiiHandle
, (UINT32
) RShiftU64 ((Bar64
& 0xfffffffffffffff0ULL
), 32));
3673 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_ONE_VAR_3
), gShellDebug1HiiHandle
, (UINT32
) (Bar64
& 0xfffffffffffffff0ULL
));
3674 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_MEM
), gShellDebug1HiiHandle
);
3675 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_64_BITS
), gShellDebug1HiiHandle
);
3683 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_BAR
), gShellDebug1HiiHandle
, *Bar
& 0xfffffff0);
3684 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_MEM_2
), gShellDebug1HiiHandle
);
3687 if ((*Bar
& BIT3
) == 0) {
3688 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_NO
), gShellDebug1HiiHandle
);
3691 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_YES
), gShellDebug1HiiHandle
);
3696 // This bar is of io type
3699 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_ONE_VAR_4
), gShellDebug1HiiHandle
, *Bar
& 0xfffffffc);
3700 ShellPrintEx (-1, -1, L
"I/O ");
3704 // Get BAR length(or the amount of resource this bar demands for). To get
3705 // Bar length, first we should temporarily disable I/O and memory access
3706 // of this function(by set bits in the register Command), then write all
3707 // "1"s to this bar. The bar value read back is the amount of resource
3708 // this bar demands for.
3711 // Disable io & mem access
3713 OldCommand
= *Command
;
3714 NewCommand
= (UINT16
) (OldCommand
& 0xfffc);
3715 RegAddress
= Address
| INDEX_OF (Command
);
3716 IoDev
->Pci
.Write (IoDev
, EfiPciWidthUint16
, RegAddress
, 1, &NewCommand
);
3718 RegAddress
= Address
| INDEX_OF (Bar
);
3721 // Read after write the BAR to get the size
3725 NewBar32
= 0xffffffff;
3727 IoDev
->Pci
.Write (IoDev
, EfiPciWidthUint32
, RegAddress
, 1, &NewBar32
);
3728 IoDev
->Pci
.Read (IoDev
, EfiPciWidthUint32
, RegAddress
, 1, &NewBar32
);
3729 IoDev
->Pci
.Write (IoDev
, EfiPciWidthUint32
, RegAddress
, 1, &OldBar32
);
3732 NewBar32
= NewBar32
& 0xfffffff0;
3733 NewBar32
= (~NewBar32
) + 1;
3736 NewBar32
= NewBar32
& 0xfffffffc;
3737 NewBar32
= (~NewBar32
) + 1;
3738 NewBar32
= NewBar32
& 0x0000ffff;
3743 CopyMem (&OldBar64
, Bar
, sizeof (UINT64
));
3744 NewBar64
= 0xffffffffffffffffULL
;
3746 IoDev
->Pci
.Write (IoDev
, EfiPciWidthUint32
, RegAddress
, 2, &NewBar64
);
3747 IoDev
->Pci
.Read (IoDev
, EfiPciWidthUint32
, RegAddress
, 2, &NewBar64
);
3748 IoDev
->Pci
.Write (IoDev
, EfiPciWidthUint32
, RegAddress
, 2, &OldBar64
);
3751 NewBar64
= NewBar64
& 0xfffffffffffffff0ULL
;
3752 NewBar64
= (~NewBar64
) + 1;
3755 NewBar64
= NewBar64
& 0xfffffffffffffffcULL
;
3756 NewBar64
= (~NewBar64
) + 1;
3757 NewBar64
= NewBar64
& 0x000000000000ffff;
3761 // Enable io & mem access
3763 RegAddress
= Address
| INDEX_OF (Command
);
3764 IoDev
->Pci
.Write (IoDev
, EfiPciWidthUint16
, RegAddress
, 1, &OldCommand
);
3768 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_NEWBAR_32
), gShellDebug1HiiHandle
, NewBar32
);
3769 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_NEWBAR_32_2
), gShellDebug1HiiHandle
, NewBar32
+ (*Bar
& 0xfffffff0) - 1);
3772 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_RSHIFT
), gShellDebug1HiiHandle
, (UINT32
) RShiftU64 (NewBar64
, 32));
3773 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_RSHIFT
), gShellDebug1HiiHandle
, (UINT32
) NewBar64
);
3774 ShellPrintEx (-1, -1, L
" ");
3775 ShellPrintHiiEx(-1, -1, NULL
,
3776 STRING_TOKEN (STR_PCI2_RSHIFT
),
3777 gShellDebug1HiiHandle
,
3778 (UINT32
) RShiftU64 ((NewBar64
+ (Bar64
& 0xfffffffffffffff0ULL
) - 1), 32)
3780 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_RSHIFT
), gShellDebug1HiiHandle
, (UINT32
) (NewBar64
+ (Bar64
& 0xfffffffffffffff0ULL
) - 1));
3784 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_NEWBAR_32_3
), gShellDebug1HiiHandle
, NewBar32
);
3785 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_NEWBAR_32_4
), gShellDebug1HiiHandle
, NewBar32
+ (*Bar
& 0xfffffffc) - 1);
3792 Explain the cardbus specific part of data in PCI configuration space.
3794 @param[in] CardBus CardBus specific region of PCI configuration space.
3795 @param[in] Address Address used to access configuration space of this PCI device.
3796 @param[in] IoDev Handle used to access configuration space of PCI device.
3798 @retval EFI_SUCCESS The command completed successfully.
3801 PciExplainCardBusData (
3802 IN PCI_CARDBUS_CONTROL_REGISTER
*CardBus
,
3804 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
3808 PCI_CARDBUS_DATA
*CardBusData
;
3810 ShellPrintHiiEx(-1, -1, NULL
,
3811 STRING_TOKEN (STR_PCI2_CARDBUS_SOCKET
),
3812 gShellDebug1HiiHandle
,
3813 INDEX_OF (&(CardBus
->CardBusSocketReg
)),
3814 CardBus
->CardBusSocketReg
3818 // Print Secondary Status
3820 PciExplainStatus (&(CardBus
->SecondaryStatus
), FALSE
, PciCardBusBridge
);
3823 // Print Bus Numbers(Primary bus number, CardBus bus number, and
3824 // Subordinate bus number
3826 ShellPrintHiiEx(-1, -1, NULL
,
3827 STRING_TOKEN (STR_PCI2_BUS_NUMBERS_2
),
3828 gShellDebug1HiiHandle
,
3829 INDEX_OF (&(CardBus
->PciBusNumber
)),
3830 INDEX_OF (&(CardBus
->CardBusBusNumber
)),
3831 INDEX_OF (&(CardBus
->SubordinateBusNumber
))
3834 ShellPrintEx (-1, -1, L
" ------------------------------------------------------\r\n");
3836 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_CARDBUS
), gShellDebug1HiiHandle
, CardBus
->PciBusNumber
);
3837 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_CARDBUS_2
), gShellDebug1HiiHandle
, CardBus
->CardBusBusNumber
);
3838 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_CARDBUS_3
), gShellDebug1HiiHandle
, CardBus
->SubordinateBusNumber
);
3841 // Print CardBus Latency Timer
3843 ShellPrintHiiEx(-1, -1, NULL
,
3844 STRING_TOKEN (STR_PCI2_CARDBUS_LATENCY
),
3845 gShellDebug1HiiHandle
,
3846 INDEX_OF (&(CardBus
->CardBusLatencyTimer
)),
3847 CardBus
->CardBusLatencyTimer
3851 // Print Memory/Io ranges this cardbus bridge forwards
3853 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_RESOURCE_TYPE_2
), gShellDebug1HiiHandle
);
3854 ShellPrintEx (-1, -1, L
"----------------------------------------------------------------------\r\n");
3856 ShellPrintHiiEx(-1, -1, NULL
,
3857 STRING_TOKEN (STR_PCI2_MEM_3
),
3858 gShellDebug1HiiHandle
,
3859 INDEX_OF (&(CardBus
->MemoryBase0
)),
3860 CardBus
->BridgeControl
& BIT8
? L
" Prefetchable" : L
"Non-Prefetchable",
3861 CardBus
->MemoryBase0
& 0xfffff000,
3862 CardBus
->MemoryLimit0
| 0x00000fff
3865 ShellPrintHiiEx(-1, -1, NULL
,
3866 STRING_TOKEN (STR_PCI2_MEM_3
),
3867 gShellDebug1HiiHandle
,
3868 INDEX_OF (&(CardBus
->MemoryBase1
)),
3869 CardBus
->BridgeControl
& BIT9
? L
" Prefetchable" : L
"Non-Prefetchable",
3870 CardBus
->MemoryBase1
& 0xfffff000,
3871 CardBus
->MemoryLimit1
| 0x00000fff
3874 Io32Bit
= (BOOLEAN
) (CardBus
->IoBase0
& BIT0
);
3875 ShellPrintHiiEx(-1, -1, NULL
,
3876 STRING_TOKEN (STR_PCI2_IO_2
),
3877 gShellDebug1HiiHandle
,
3878 INDEX_OF (&(CardBus
->IoBase0
)),
3879 Io32Bit
? L
" 32 bit" : L
" 16 bit",
3880 CardBus
->IoBase0
& (Io32Bit
? 0xfffffffc : 0x0000fffc),
3881 (CardBus
->IoLimit0
& (Io32Bit
? 0xffffffff : 0x0000ffff)) | 0x00000003
3884 Io32Bit
= (BOOLEAN
) (CardBus
->IoBase1
& BIT0
);
3885 ShellPrintHiiEx(-1, -1, NULL
,
3886 STRING_TOKEN (STR_PCI2_IO_2
),
3887 gShellDebug1HiiHandle
,
3888 INDEX_OF (&(CardBus
->IoBase1
)),
3889 Io32Bit
? L
" 32 bit" : L
" 16 bit",
3890 CardBus
->IoBase1
& (Io32Bit
? 0xfffffffc : 0x0000fffc),
3891 (CardBus
->IoLimit1
& (Io32Bit
? 0xffffffff : 0x0000ffff)) | 0x00000003
3895 // Print register Interrupt Line & PIN
3897 ShellPrintHiiEx(-1, -1, NULL
,
3898 STRING_TOKEN (STR_PCI2_INTERRUPT_LINE_3
),
3899 gShellDebug1HiiHandle
,
3900 INDEX_OF (&(CardBus
->InterruptLine
)),
3901 CardBus
->InterruptLine
,
3902 INDEX_OF (&(CardBus
->InterruptPin
)),
3903 CardBus
->InterruptPin
3907 // Print register Bridge Control
3909 PciExplainBridgeControl (&(CardBus
->BridgeControl
), PciCardBusBridge
);
3912 // Print some registers in data region of PCI configuration space for cardbus
3913 // bridge. Fields include: Sub VendorId, Subsystem ID, and Legacy Mode Base
3916 CardBusData
= (PCI_CARDBUS_DATA
*) ((UINT8
*) CardBus
+ sizeof (PCI_CARDBUS_CONTROL_REGISTER
));
3918 ShellPrintHiiEx(-1, -1, NULL
,
3919 STRING_TOKEN (STR_PCI2_SUB_VENDOR_ID_2
),
3920 gShellDebug1HiiHandle
,
3921 INDEX_OF (&(CardBusData
->SubVendorId
)),
3922 CardBusData
->SubVendorId
,
3923 INDEX_OF (&(CardBusData
->SubSystemId
)),
3924 CardBusData
->SubSystemId
3927 ShellPrintHiiEx(-1, -1, NULL
,
3928 STRING_TOKEN (STR_PCI2_OPTIONAL
),
3929 gShellDebug1HiiHandle
,
3930 INDEX_OF (&(CardBusData
->LegacyBase
)),
3931 CardBusData
->LegacyBase
3938 Explain each meaningful bit of register Status. The definition of Status is
3939 slightly different depending on the PCI header type.
3941 @param[in] Status Points to the content of register Status.
3942 @param[in] MainStatus Indicates if this register is main status(not secondary
3944 @param[in] HeaderType Header type of this PCI device.
3946 @retval EFI_SUCCESS The command completed successfully.
3951 IN BOOLEAN MainStatus
,
3952 IN PCI_HEADER_TYPE HeaderType
3956 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_STATUS
), gShellDebug1HiiHandle
, INDEX_OF (Status
), *Status
);
3959 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_SECONDARY_STATUS
), gShellDebug1HiiHandle
, INDEX_OF (Status
), *Status
);
3962 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_NEW_CAPABILITIES
), gShellDebug1HiiHandle
, (*Status
& BIT4
) != 0);
3965 // Bit 5 is meaningless for CardBus Bridge
3967 if (HeaderType
== PciCardBusBridge
) {
3968 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_66_CAPABLE
), gShellDebug1HiiHandle
, (*Status
& BIT5
) != 0);
3971 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_66_CAPABLE_2
), gShellDebug1HiiHandle
, (*Status
& BIT5
) != 0);
3974 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_FAST_BACK
), gShellDebug1HiiHandle
, (*Status
& BIT7
) != 0);
3976 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_MASTER_DATA
), gShellDebug1HiiHandle
, (*Status
& BIT8
) != 0);
3978 // Bit 9 and bit 10 together decides the DEVSEL timing
3980 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_DEVSEL_TIMING
), gShellDebug1HiiHandle
);
3981 if ((*Status
& BIT9
) == 0 && (*Status
& BIT10
) == 0) {
3982 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_FAST
), gShellDebug1HiiHandle
);
3984 } else if ((*Status
& BIT9
) != 0 && (*Status
& BIT10
) == 0) {
3985 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_MEDIUM
), gShellDebug1HiiHandle
);
3987 } else if ((*Status
& BIT9
) == 0 && (*Status
& BIT10
) != 0) {
3988 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_SLOW
), gShellDebug1HiiHandle
);
3991 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_RESERVED_2
), gShellDebug1HiiHandle
);
3994 ShellPrintHiiEx(-1, -1, NULL
,
3995 STRING_TOKEN (STR_PCI2_SIGNALED_TARGET
),
3996 gShellDebug1HiiHandle
,
3997 (*Status
& BIT11
) != 0
4000 ShellPrintHiiEx(-1, -1, NULL
,
4001 STRING_TOKEN (STR_PCI2_RECEIVED_TARGET
),
4002 gShellDebug1HiiHandle
,
4003 (*Status
& BIT12
) != 0
4006 ShellPrintHiiEx(-1, -1, NULL
,
4007 STRING_TOKEN (STR_PCI2_RECEIVED_MASTER
),
4008 gShellDebug1HiiHandle
,
4009 (*Status
& BIT13
) != 0
4013 ShellPrintHiiEx(-1, -1, NULL
,
4014 STRING_TOKEN (STR_PCI2_SIGNALED_ERROR
),
4015 gShellDebug1HiiHandle
,
4016 (*Status
& BIT14
) != 0
4020 ShellPrintHiiEx(-1, -1, NULL
,
4021 STRING_TOKEN (STR_PCI2_RECEIVED_ERROR
),
4022 gShellDebug1HiiHandle
,
4023 (*Status
& BIT14
) != 0
4027 ShellPrintHiiEx(-1, -1, NULL
,
4028 STRING_TOKEN (STR_PCI2_DETECTED_ERROR
),
4029 gShellDebug1HiiHandle
,
4030 (*Status
& BIT15
) != 0
4037 Explain each meaningful bit of register Command.
4039 @param[in] Command Points to the content of register Command.
4041 @retval EFI_SUCCESS The command completed successfully.
4049 // Print the binary value of register Command
4051 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_COMMAND
), gShellDebug1HiiHandle
, INDEX_OF (Command
), *Command
);
4054 // Explain register Command bit by bit
4056 ShellPrintHiiEx(-1, -1, NULL
,
4057 STRING_TOKEN (STR_PCI2_SPACE_ACCESS_DENIED
),
4058 gShellDebug1HiiHandle
,
4059 (*Command
& BIT0
) != 0
4062 ShellPrintHiiEx(-1, -1, NULL
,
4063 STRING_TOKEN (STR_PCI2_MEMORY_SPACE
),
4064 gShellDebug1HiiHandle
,
4065 (*Command
& BIT1
) != 0
4068 ShellPrintHiiEx(-1, -1, NULL
,
4069 STRING_TOKEN (STR_PCI2_BEHAVE_BUS_MASTER
),
4070 gShellDebug1HiiHandle
,
4071 (*Command
& BIT2
) != 0
4074 ShellPrintHiiEx(-1, -1, NULL
,
4075 STRING_TOKEN (STR_PCI2_MONITOR_SPECIAL_CYCLE
),
4076 gShellDebug1HiiHandle
,
4077 (*Command
& BIT3
) != 0
4080 ShellPrintHiiEx(-1, -1, NULL
,
4081 STRING_TOKEN (STR_PCI2_MEM_WRITE_INVALIDATE
),
4082 gShellDebug1HiiHandle
,
4083 (*Command
& BIT4
) != 0
4086 ShellPrintHiiEx(-1, -1, NULL
,
4087 STRING_TOKEN (STR_PCI2_PALETTE_SNOOPING
),
4088 gShellDebug1HiiHandle
,
4089 (*Command
& BIT5
) != 0
4092 ShellPrintHiiEx(-1, -1, NULL
,
4093 STRING_TOKEN (STR_PCI2_ASSERT_PERR
),
4094 gShellDebug1HiiHandle
,
4095 (*Command
& BIT6
) != 0
4098 ShellPrintHiiEx(-1, -1, NULL
,
4099 STRING_TOKEN (STR_PCI2_DO_ADDR_STEPPING
),
4100 gShellDebug1HiiHandle
,
4101 (*Command
& BIT7
) != 0
4104 ShellPrintHiiEx(-1, -1, NULL
,
4105 STRING_TOKEN (STR_PCI2_SERR_DRIVER
),
4106 gShellDebug1HiiHandle
,
4107 (*Command
& BIT8
) != 0
4110 ShellPrintHiiEx(-1, -1, NULL
,
4111 STRING_TOKEN (STR_PCI2_FAST_BACK_2
),
4112 gShellDebug1HiiHandle
,
4113 (*Command
& BIT9
) != 0
4120 Explain each meaningful bit of register Bridge Control.
4122 @param[in] BridgeControl Points to the content of register Bridge Control.
4123 @param[in] HeaderType The headertype.
4125 @retval EFI_SUCCESS The command completed successfully.
4128 PciExplainBridgeControl (
4129 IN UINT16
*BridgeControl
,
4130 IN PCI_HEADER_TYPE HeaderType
4133 ShellPrintHiiEx(-1, -1, NULL
,
4134 STRING_TOKEN (STR_PCI2_BRIDGE_CONTROL
),
4135 gShellDebug1HiiHandle
,
4136 INDEX_OF (BridgeControl
),
4140 ShellPrintHiiEx(-1, -1, NULL
,
4141 STRING_TOKEN (STR_PCI2_PARITY_ERROR
),
4142 gShellDebug1HiiHandle
,
4143 (*BridgeControl
& BIT0
) != 0
4145 ShellPrintHiiEx(-1, -1, NULL
,
4146 STRING_TOKEN (STR_PCI2_SERR_ENABLE
),
4147 gShellDebug1HiiHandle
,
4148 (*BridgeControl
& BIT1
) != 0
4150 ShellPrintHiiEx(-1, -1, NULL
,
4151 STRING_TOKEN (STR_PCI2_ISA_ENABLE
),
4152 gShellDebug1HiiHandle
,
4153 (*BridgeControl
& BIT2
) != 0
4155 ShellPrintHiiEx(-1, -1, NULL
,
4156 STRING_TOKEN (STR_PCI2_VGA_ENABLE
),
4157 gShellDebug1HiiHandle
,
4158 (*BridgeControl
& BIT3
) != 0
4160 ShellPrintHiiEx(-1, -1, NULL
,
4161 STRING_TOKEN (STR_PCI2_MASTER_ABORT
),
4162 gShellDebug1HiiHandle
,
4163 (*BridgeControl
& BIT5
) != 0
4167 // Register Bridge Control has some slight differences between P2P bridge
4168 // and Cardbus bridge from bit 6 to bit 11.
4170 if (HeaderType
== PciP2pBridge
) {
4171 ShellPrintHiiEx(-1, -1, NULL
,
4172 STRING_TOKEN (STR_PCI2_SECONDARY_BUS_RESET
),
4173 gShellDebug1HiiHandle
,
4174 (*BridgeControl
& BIT6
) != 0
4176 ShellPrintHiiEx(-1, -1, NULL
,
4177 STRING_TOKEN (STR_PCI2_FAST_ENABLE
),
4178 gShellDebug1HiiHandle
,
4179 (*BridgeControl
& BIT7
) != 0
4181 ShellPrintHiiEx(-1, -1, NULL
,
4182 STRING_TOKEN (STR_PCI2_PRIMARY_DISCARD_TIMER
),
4183 gShellDebug1HiiHandle
,
4184 (*BridgeControl
& BIT8
)!=0 ? L
"2^10" : L
"2^15"
4186 ShellPrintHiiEx(-1, -1, NULL
,
4187 STRING_TOKEN (STR_PCI2_SECONDARY_DISCARD_TIMER
),
4188 gShellDebug1HiiHandle
,
4189 (*BridgeControl
& BIT9
)!=0 ? L
"2^10" : L
"2^15"
4191 ShellPrintHiiEx(-1, -1, NULL
,
4192 STRING_TOKEN (STR_PCI2_DISCARD_TIMER_STATUS
),
4193 gShellDebug1HiiHandle
,
4194 (*BridgeControl
& BIT10
) != 0
4196 ShellPrintHiiEx(-1, -1, NULL
,
4197 STRING_TOKEN (STR_PCI2_DISCARD_TIMER_SERR
),
4198 gShellDebug1HiiHandle
,
4199 (*BridgeControl
& BIT11
) != 0
4203 ShellPrintHiiEx(-1, -1, NULL
,
4204 STRING_TOKEN (STR_PCI2_CARDBUS_RESET
),
4205 gShellDebug1HiiHandle
,
4206 (*BridgeControl
& BIT6
) != 0
4208 ShellPrintHiiEx(-1, -1, NULL
,
4209 STRING_TOKEN (STR_PCI2_IREQ_ENABLE
),
4210 gShellDebug1HiiHandle
,
4211 (*BridgeControl
& BIT7
) != 0
4213 ShellPrintHiiEx(-1, -1, NULL
,
4214 STRING_TOKEN (STR_PCI2_WRITE_POSTING_ENABLE
),
4215 gShellDebug1HiiHandle
,
4216 (*BridgeControl
& BIT10
) != 0
4224 Print each capability structure.
4226 @param[in] IoDev The pointer to the deivce.
4227 @param[in] Address The address to start at.
4228 @param[in] CapPtr The offset from the address.
4229 @param[in] EnhancedDump The print format for the dump data.
4231 @retval EFI_SUCCESS The operation was successful.
4234 PciExplainCapabilityStruct (
4235 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
,
4238 IN CONST UINT16 EnhancedDump
4241 UINT8 CapabilityPtr
;
4242 UINT16 CapabilityEntry
;
4246 CapabilityPtr
= CapPtr
;
4249 // Go through the Capability list
4251 while ((CapabilityPtr
>= 0x40) && ((CapabilityPtr
& 0x03) == 0x00)) {
4252 RegAddress
= Address
+ CapabilityPtr
;
4253 IoDev
->Pci
.Read (IoDev
, EfiPciWidthUint16
, RegAddress
, 1, &CapabilityEntry
);
4255 CapabilityID
= (UINT8
) CapabilityEntry
;
4258 // Explain PciExpress data
4260 if (EFI_PCI_CAPABILITY_ID_PCIEXP
== CapabilityID
) {
4261 PciExplainPciExpress (IoDev
, Address
, CapabilityPtr
, EnhancedDump
);
4265 // Explain other capabilities here
4267 CapabilityPtr
= (UINT8
) (CapabilityEntry
>> 8);
4274 Print out information of the capability information.
4276 @param[in] PciExpressCap The pointer to the structure about the device.
4278 @retval EFI_SUCCESS The operation was successful.
4282 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
4285 CHAR16
*DevicePortType
;
4287 ShellPrintEx (-1, -1,
4288 L
" Capability Version(3:0): %E0x%04x%N\r\n",
4289 PciExpressCap
->Capability
.Bits
.Version
4291 if (PciExpressCap
->Capability
.Bits
.DevicePortType
< ARRAY_SIZE (DevicePortTypeTable
)) {
4292 DevicePortType
= DevicePortTypeTable
[PciExpressCap
->Capability
.Bits
.DevicePortType
];
4294 DevicePortType
= L
"Unknown Type";
4296 ShellPrintEx (-1, -1,
4297 L
" Device/PortType(7:4): %E%s%N\r\n",
4301 // 'Slot Implemented' is only valid for:
4302 // a) Root Port of PCI Express Root Complex, or
4303 // b) Downstream Port of PCI Express Switch
4305 if (PciExpressCap
->Capability
.Bits
.DevicePortType
== PCIE_DEVICE_PORT_TYPE_ROOT_PORT
||
4306 PciExpressCap
->Capability
.Bits
.DevicePortType
== PCIE_DEVICE_PORT_TYPE_DOWNSTREAM_PORT
) {
4307 ShellPrintEx (-1, -1,
4308 L
" Slot Implemented(8): %E%d%N\r\n",
4309 PciExpressCap
->Capability
.Bits
.SlotImplemented
4312 ShellPrintEx (-1, -1,
4313 L
" Interrupt Message Number(13:9): %E0x%05x%N\r\n",
4314 PciExpressCap
->Capability
.Bits
.InterruptMessageNumber
4320 Print out information of the device capability information.
4322 @param[in] PciExpressCap The pointer to the structure about the device.
4324 @retval EFI_SUCCESS The operation was successful.
4327 ExplainPcieDeviceCap (
4328 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
4331 UINT8 DevicePortType
;
4335 DevicePortType
= (UINT8
)PciExpressCap
->Capability
.Bits
.DevicePortType
;
4336 ShellPrintEx (-1, -1, L
" Max_Payload_Size Supported(2:0): ");
4337 if (PciExpressCap
->DeviceCapability
.Bits
.MaxPayloadSize
< 6) {
4338 ShellPrintEx (-1, -1, L
"%E%d bytes%N\r\n", 1 << (PciExpressCap
->DeviceCapability
.Bits
.MaxPayloadSize
+ 7));
4340 ShellPrintEx (-1, -1, L
"%EUnknown%N\r\n");
4342 ShellPrintEx (-1, -1,
4343 L
" Phantom Functions Supported(4:3): %E%d%N\r\n",
4344 PciExpressCap
->DeviceCapability
.Bits
.PhantomFunctions
4346 ShellPrintEx (-1, -1,
4347 L
" Extended Tag Field Supported(5): %E%d-bit Tag field supported%N\r\n",
4348 PciExpressCap
->DeviceCapability
.Bits
.ExtendedTagField
? 8 : 5
4351 // Endpoint L0s and L1 Acceptable Latency is only valid for Endpoint
4353 if (IS_PCIE_ENDPOINT (DevicePortType
)) {
4354 L0sLatency
= (UINT8
)PciExpressCap
->DeviceCapability
.Bits
.EndpointL0sAcceptableLatency
;
4355 L1Latency
= (UINT8
)PciExpressCap
->DeviceCapability
.Bits
.EndpointL1AcceptableLatency
;
4356 ShellPrintEx (-1, -1, L
" Endpoint L0s Acceptable Latency(8:6): ");
4357 if (L0sLatency
< 4) {
4358 ShellPrintEx (-1, -1, L
"%EMaximum of %d ns%N\r\n", 1 << (L0sLatency
+ 6));
4360 if (L0sLatency
< 7) {
4361 ShellPrintEx (-1, -1, L
"%EMaximum of %d us%N\r\n", 1 << (L0sLatency
- 3));
4363 ShellPrintEx (-1, -1, L
"%ENo limit%N\r\n");
4366 ShellPrintEx (-1, -1, L
" Endpoint L1 Acceptable Latency(11:9): ");
4367 if (L1Latency
< 7) {
4368 ShellPrintEx (-1, -1, L
"%EMaximum of %d us%N\r\n", 1 << (L1Latency
+ 1));
4370 ShellPrintEx (-1, -1, L
"%ENo limit%N\r\n");
4373 ShellPrintEx (-1, -1,
4374 L
" Role-based Error Reporting(15): %E%d%N\r\n",
4375 PciExpressCap
->DeviceCapability
.Bits
.RoleBasedErrorReporting
4378 // Only valid for Upstream Port:
4379 // a) Captured Slot Power Limit Value
4380 // b) Captured Slot Power Scale
4382 if (DevicePortType
== PCIE_DEVICE_PORT_TYPE_UPSTREAM_PORT
) {
4383 ShellPrintEx (-1, -1,
4384 L
" Captured Slot Power Limit Value(25:18): %E0x%02x%N\r\n",
4385 PciExpressCap
->DeviceCapability
.Bits
.CapturedSlotPowerLimitValue
4387 ShellPrintEx (-1, -1,
4388 L
" Captured Slot Power Limit Scale(27:26): %E%s%N\r\n",
4389 SlotPwrLmtScaleTable
[PciExpressCap
->DeviceCapability
.Bits
.CapturedSlotPowerLimitScale
]
4393 // Function Level Reset Capability is only valid for Endpoint
4395 if (IS_PCIE_ENDPOINT (DevicePortType
)) {
4396 ShellPrintEx (-1, -1,
4397 L
" Function Level Reset Capability(28): %E%d%N\r\n",
4398 PciExpressCap
->DeviceCapability
.Bits
.FunctionLevelReset
4405 Print out information of the device control information.
4407 @param[in] PciExpressCap The pointer to the structure about the device.
4409 @retval EFI_SUCCESS The operation was successful.
4412 ExplainPcieDeviceControl (
4413 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
4416 ShellPrintEx (-1, -1,
4417 L
" Correctable Error Reporting Enable(0): %E%d%N\r\n",
4418 PciExpressCap
->DeviceControl
.Bits
.CorrectableError
4420 ShellPrintEx (-1, -1,
4421 L
" Non-Fatal Error Reporting Enable(1): %E%d%N\r\n",
4422 PciExpressCap
->DeviceControl
.Bits
.NonFatalError
4424 ShellPrintEx (-1, -1,
4425 L
" Fatal Error Reporting Enable(2): %E%d%N\r\n",
4426 PciExpressCap
->DeviceControl
.Bits
.FatalError
4428 ShellPrintEx (-1, -1,
4429 L
" Unsupported Request Reporting Enable(3): %E%d%N\r\n",
4430 PciExpressCap
->DeviceControl
.Bits
.UnsupportedRequest
4432 ShellPrintEx (-1, -1,
4433 L
" Enable Relaxed Ordering(4): %E%d%N\r\n",
4434 PciExpressCap
->DeviceControl
.Bits
.RelaxedOrdering
4436 ShellPrintEx (-1, -1, L
" Max_Payload_Size(7:5): ");
4437 if (PciExpressCap
->DeviceControl
.Bits
.MaxPayloadSize
< 6) {
4438 ShellPrintEx (-1, -1, L
"%E%d bytes%N\r\n", 1 << (PciExpressCap
->DeviceControl
.Bits
.MaxPayloadSize
+ 7));
4440 ShellPrintEx (-1, -1, L
"%EUnknown%N\r\n");
4442 ShellPrintEx (-1, -1,
4443 L
" Extended Tag Field Enable(8): %E%d%N\r\n",
4444 PciExpressCap
->DeviceControl
.Bits
.ExtendedTagField
4446 ShellPrintEx (-1, -1,
4447 L
" Phantom Functions Enable(9): %E%d%N\r\n",
4448 PciExpressCap
->DeviceControl
.Bits
.PhantomFunctions
4450 ShellPrintEx (-1, -1,
4451 L
" Auxiliary (AUX) Power PM Enable(10): %E%d%N\r\n",
4452 PciExpressCap
->DeviceControl
.Bits
.AuxPower
4454 ShellPrintEx (-1, -1,
4455 L
" Enable No Snoop(11): %E%d%N\r\n",
4456 PciExpressCap
->DeviceControl
.Bits
.NoSnoop
4458 ShellPrintEx (-1, -1, L
" Max_Read_Request_Size(14:12): ");
4459 if (PciExpressCap
->DeviceControl
.Bits
.MaxReadRequestSize
< 6) {
4460 ShellPrintEx (-1, -1, L
"%E%d bytes%N\r\n", 1 << (PciExpressCap
->DeviceControl
.Bits
.MaxReadRequestSize
+ 7));
4462 ShellPrintEx (-1, -1, L
"%EUnknown%N\r\n");
4465 // Read operation is only valid for PCI Express to PCI/PCI-X Bridges
4467 if (PciExpressCap
->Capability
.Bits
.DevicePortType
== PCIE_DEVICE_PORT_TYPE_PCIE_TO_PCI_BRIDGE
) {
4468 ShellPrintEx (-1, -1,
4469 L
" Bridge Configuration Retry Enable(15): %E%d%N\r\n",
4470 PciExpressCap
->DeviceControl
.Bits
.BridgeConfigurationRetryOrFunctionLevelReset
4477 Print out information of the device status information.
4479 @param[in] PciExpressCap The pointer to the structure about the device.
4481 @retval EFI_SUCCESS The operation was successful.
4484 ExplainPcieDeviceStatus (
4485 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
4488 ShellPrintEx (-1, -1,
4489 L
" Correctable Error Detected(0): %E%d%N\r\n",
4490 PciExpressCap
->DeviceStatus
.Bits
.CorrectableError
4492 ShellPrintEx (-1, -1,
4493 L
" Non-Fatal Error Detected(1): %E%d%N\r\n",
4494 PciExpressCap
->DeviceStatus
.Bits
.NonFatalError
4496 ShellPrintEx (-1, -1,
4497 L
" Fatal Error Detected(2): %E%d%N\r\n",
4498 PciExpressCap
->DeviceStatus
.Bits
.FatalError
4500 ShellPrintEx (-1, -1,
4501 L
" Unsupported Request Detected(3): %E%d%N\r\n",
4502 PciExpressCap
->DeviceStatus
.Bits
.UnsupportedRequest
4504 ShellPrintEx (-1, -1,
4505 L
" AUX Power Detected(4): %E%d%N\r\n",
4506 PciExpressCap
->DeviceStatus
.Bits
.AuxPower
4508 ShellPrintEx (-1, -1,
4509 L
" Transactions Pending(5): %E%d%N\r\n",
4510 PciExpressCap
->DeviceStatus
.Bits
.TransactionsPending
4516 Print out information of the device link information.
4518 @param[in] PciExpressCap The pointer to the structure about the device.
4520 @retval EFI_SUCCESS The operation was successful.
4523 ExplainPcieLinkCap (
4524 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
4527 CHAR16
*MaxLinkSpeed
;
4530 switch (PciExpressCap
->LinkCapability
.Bits
.MaxLinkSpeed
) {
4532 MaxLinkSpeed
= L
"2.5 GT/s";
4535 MaxLinkSpeed
= L
"5.0 GT/s";
4538 MaxLinkSpeed
= L
"8.0 GT/s";
4541 MaxLinkSpeed
= L
"Unknown";
4544 ShellPrintEx (-1, -1,
4545 L
" Maximum Link Speed(3:0): %E%s%N\r\n",
4548 ShellPrintEx (-1, -1,
4549 L
" Maximum Link Width(9:4): %Ex%d%N\r\n",
4550 PciExpressCap
->LinkCapability
.Bits
.MaxLinkWidth
4552 switch (PciExpressCap
->LinkCapability
.Bits
.Aspm
) {
4563 AspmValue
= L
"L0s and L1";
4566 AspmValue
= L
"Reserved";
4569 ShellPrintEx (-1, -1,
4570 L
" Active State Power Management Support(11:10): %E%s Supported%N\r\n",
4573 ShellPrintEx (-1, -1,
4574 L
" L0s Exit Latency(14:12): %E%s%N\r\n",
4575 L0sLatencyStrTable
[PciExpressCap
->LinkCapability
.Bits
.L0sExitLatency
]
4577 ShellPrintEx (-1, -1,
4578 L
" L1 Exit Latency(17:15): %E%s%N\r\n",
4579 L1LatencyStrTable
[PciExpressCap
->LinkCapability
.Bits
.L1ExitLatency
]
4581 ShellPrintEx (-1, -1,
4582 L
" Clock Power Management(18): %E%d%N\r\n",
4583 PciExpressCap
->LinkCapability
.Bits
.ClockPowerManagement
4585 ShellPrintEx (-1, -1,
4586 L
" Surprise Down Error Reporting Capable(19): %E%d%N\r\n",
4587 PciExpressCap
->LinkCapability
.Bits
.SurpriseDownError
4589 ShellPrintEx (-1, -1,
4590 L
" Data Link Layer Link Active Reporting Capable(20): %E%d%N\r\n",
4591 PciExpressCap
->LinkCapability
.Bits
.DataLinkLayerLinkActive
4593 ShellPrintEx (-1, -1,
4594 L
" Link Bandwidth Notification Capability(21): %E%d%N\r\n",
4595 PciExpressCap
->LinkCapability
.Bits
.LinkBandwidthNotification
4597 ShellPrintEx (-1, -1,
4598 L
" Port Number(31:24): %E0x%02x%N\r\n",
4599 PciExpressCap
->LinkCapability
.Bits
.PortNumber
4605 Print out information of the device link control information.
4607 @param[in] PciExpressCap The pointer to the structure about the device.
4609 @retval EFI_SUCCESS The operation was successful.
4612 ExplainPcieLinkControl (
4613 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
4616 UINT8 DevicePortType
;
4618 DevicePortType
= (UINT8
)PciExpressCap
->Capability
.Bits
.DevicePortType
;
4619 ShellPrintEx (-1, -1,
4620 L
" Active State Power Management Control(1:0): %E%s%N\r\n",
4621 ASPMCtrlStrTable
[PciExpressCap
->LinkControl
.Bits
.AspmControl
]
4624 // RCB is not applicable to switches
4626 if (!IS_PCIE_SWITCH(DevicePortType
)) {
4627 ShellPrintEx (-1, -1,
4628 L
" Read Completion Boundary (RCB)(3): %E%d byte%N\r\n",
4629 1 << (PciExpressCap
->LinkControl
.Bits
.ReadCompletionBoundary
+ 6)
4633 // Link Disable is reserved on
4635 // b) PCI Express to PCI/PCI-X bridges
4636 // c) Upstream Ports of Switches
4638 if (!IS_PCIE_ENDPOINT (DevicePortType
) &&
4639 DevicePortType
!= PCIE_DEVICE_PORT_TYPE_UPSTREAM_PORT
&&
4640 DevicePortType
!= PCIE_DEVICE_PORT_TYPE_PCIE_TO_PCI_BRIDGE
) {
4641 ShellPrintEx (-1, -1,
4642 L
" Link Disable(4): %E%d%N\r\n",
4643 PciExpressCap
->LinkControl
.Bits
.LinkDisable
4646 ShellPrintEx (-1, -1,
4647 L
" Common Clock Configuration(6): %E%d%N\r\n",
4648 PciExpressCap
->LinkControl
.Bits
.CommonClockConfiguration
4650 ShellPrintEx (-1, -1,
4651 L
" Extended Synch(7): %E%d%N\r\n",
4652 PciExpressCap
->LinkControl
.Bits
.ExtendedSynch
4654 ShellPrintEx (-1, -1,
4655 L
" Enable Clock Power Management(8): %E%d%N\r\n",
4656 PciExpressCap
->LinkControl
.Bits
.ClockPowerManagement
4658 ShellPrintEx (-1, -1,
4659 L
" Hardware Autonomous Width Disable(9): %E%d%N\r\n",
4660 PciExpressCap
->LinkControl
.Bits
.HardwareAutonomousWidthDisable
4662 ShellPrintEx (-1, -1,
4663 L
" Link Bandwidth Management Interrupt Enable(10): %E%d%N\r\n",
4664 PciExpressCap
->LinkControl
.Bits
.LinkBandwidthManagementInterrupt
4666 ShellPrintEx (-1, -1,
4667 L
" Link Autonomous Bandwidth Interrupt Enable(11): %E%d%N\r\n",
4668 PciExpressCap
->LinkControl
.Bits
.LinkAutonomousBandwidthInterrupt
4674 Print out information of the device link status information.
4676 @param[in] PciExpressCap The pointer to the structure about the device.
4678 @retval EFI_SUCCESS The operation was successful.
4681 ExplainPcieLinkStatus (
4682 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
4685 CHAR16
*CurLinkSpeed
;
4687 switch (PciExpressCap
->LinkStatus
.Bits
.CurrentLinkSpeed
) {
4689 CurLinkSpeed
= L
"2.5 GT/s";
4692 CurLinkSpeed
= L
"5.0 GT/s";
4695 CurLinkSpeed
= L
"8.0 GT/s";
4698 CurLinkSpeed
= L
"Reserved";
4701 ShellPrintEx (-1, -1,
4702 L
" Current Link Speed(3:0): %E%s%N\r\n",
4705 ShellPrintEx (-1, -1,
4706 L
" Negotiated Link Width(9:4): %Ex%d%N\r\n",
4707 PciExpressCap
->LinkStatus
.Bits
.NegotiatedLinkWidth
4709 ShellPrintEx (-1, -1,
4710 L
" Link Training(11): %E%d%N\r\n",
4711 PciExpressCap
->LinkStatus
.Bits
.LinkTraining
4713 ShellPrintEx (-1, -1,
4714 L
" Slot Clock Configuration(12): %E%d%N\r\n",
4715 PciExpressCap
->LinkStatus
.Bits
.SlotClockConfiguration
4717 ShellPrintEx (-1, -1,
4718 L
" Data Link Layer Link Active(13): %E%d%N\r\n",
4719 PciExpressCap
->LinkStatus
.Bits
.DataLinkLayerLinkActive
4721 ShellPrintEx (-1, -1,
4722 L
" Link Bandwidth Management Status(14): %E%d%N\r\n",
4723 PciExpressCap
->LinkStatus
.Bits
.LinkBandwidthManagement
4725 ShellPrintEx (-1, -1,
4726 L
" Link Autonomous Bandwidth Status(15): %E%d%N\r\n",
4727 PciExpressCap
->LinkStatus
.Bits
.LinkAutonomousBandwidth
4733 Print out information of the device slot information.
4735 @param[in] PciExpressCap The pointer to the structure about the device.
4737 @retval EFI_SUCCESS The operation was successful.
4740 ExplainPcieSlotCap (
4741 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
4744 ShellPrintEx (-1, -1,
4745 L
" Attention Button Present(0): %E%d%N\r\n",
4746 PciExpressCap
->SlotCapability
.Bits
.AttentionButton
4748 ShellPrintEx (-1, -1,
4749 L
" Power Controller Present(1): %E%d%N\r\n",
4750 PciExpressCap
->SlotCapability
.Bits
.PowerController
4752 ShellPrintEx (-1, -1,
4753 L
" MRL Sensor Present(2): %E%d%N\r\n",
4754 PciExpressCap
->SlotCapability
.Bits
.MrlSensor
4756 ShellPrintEx (-1, -1,
4757 L
" Attention Indicator Present(3): %E%d%N\r\n",
4758 PciExpressCap
->SlotCapability
.Bits
.AttentionIndicator
4760 ShellPrintEx (-1, -1,
4761 L
" Power Indicator Present(4): %E%d%N\r\n",
4762 PciExpressCap
->SlotCapability
.Bits
.PowerIndicator
4764 ShellPrintEx (-1, -1,
4765 L
" Hot-Plug Surprise(5): %E%d%N\r\n",
4766 PciExpressCap
->SlotCapability
.Bits
.HotPlugSurprise
4768 ShellPrintEx (-1, -1,
4769 L
" Hot-Plug Capable(6): %E%d%N\r\n",
4770 PciExpressCap
->SlotCapability
.Bits
.HotPlugCapable
4772 ShellPrintEx (-1, -1,
4773 L
" Slot Power Limit Value(14:7): %E0x%02x%N\r\n",
4774 PciExpressCap
->SlotCapability
.Bits
.SlotPowerLimitValue
4776 ShellPrintEx (-1, -1,
4777 L
" Slot Power Limit Scale(16:15): %E%s%N\r\n",
4778 SlotPwrLmtScaleTable
[PciExpressCap
->SlotCapability
.Bits
.SlotPowerLimitScale
]
4780 ShellPrintEx (-1, -1,
4781 L
" Electromechanical Interlock Present(17): %E%d%N\r\n",
4782 PciExpressCap
->SlotCapability
.Bits
.ElectromechanicalInterlock
4784 ShellPrintEx (-1, -1,
4785 L
" No Command Completed Support(18): %E%d%N\r\n",
4786 PciExpressCap
->SlotCapability
.Bits
.NoCommandCompleted
4788 ShellPrintEx (-1, -1,
4789 L
" Physical Slot Number(31:19): %E%d%N\r\n",
4790 PciExpressCap
->SlotCapability
.Bits
.PhysicalSlotNumber
4797 Print out information of the device slot control information.
4799 @param[in] PciExpressCap The pointer to the structure about the device.
4801 @retval EFI_SUCCESS The operation was successful.
4804 ExplainPcieSlotControl (
4805 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
4808 ShellPrintEx (-1, -1,
4809 L
" Attention Button Pressed Enable(0): %E%d%N\r\n",
4810 PciExpressCap
->SlotControl
.Bits
.AttentionButtonPressed
4812 ShellPrintEx (-1, -1,
4813 L
" Power Fault Detected Enable(1): %E%d%N\r\n",
4814 PciExpressCap
->SlotControl
.Bits
.PowerFaultDetected
4816 ShellPrintEx (-1, -1,
4817 L
" MRL Sensor Changed Enable(2): %E%d%N\r\n",
4818 PciExpressCap
->SlotControl
.Bits
.MrlSensorChanged
4820 ShellPrintEx (-1, -1,
4821 L
" Presence Detect Changed Enable(3): %E%d%N\r\n",
4822 PciExpressCap
->SlotControl
.Bits
.PresenceDetectChanged
4824 ShellPrintEx (-1, -1,
4825 L
" Command Completed Interrupt Enable(4): %E%d%N\r\n",
4826 PciExpressCap
->SlotControl
.Bits
.CommandCompletedInterrupt
4828 ShellPrintEx (-1, -1,
4829 L
" Hot-Plug Interrupt Enable(5): %E%d%N\r\n",
4830 PciExpressCap
->SlotControl
.Bits
.HotPlugInterrupt
4832 ShellPrintEx (-1, -1,
4833 L
" Attention Indicator Control(7:6): %E%s%N\r\n",
4835 PciExpressCap
->SlotControl
.Bits
.AttentionIndicator
]
4837 ShellPrintEx (-1, -1,
4838 L
" Power Indicator Control(9:8): %E%s%N\r\n",
4839 IndicatorTable
[PciExpressCap
->SlotControl
.Bits
.PowerIndicator
]
4841 ShellPrintEx (-1, -1, L
" Power Controller Control(10): %EPower ");
4843 PciExpressCap
->SlotControl
.Bits
.PowerController
) {
4844 ShellPrintEx (-1, -1, L
"Off%N\r\n");
4846 ShellPrintEx (-1, -1, L
"On%N\r\n");
4848 ShellPrintEx (-1, -1,
4849 L
" Electromechanical Interlock Control(11): %E%d%N\r\n",
4850 PciExpressCap
->SlotControl
.Bits
.ElectromechanicalInterlock
4852 ShellPrintEx (-1, -1,
4853 L
" Data Link Layer State Changed Enable(12): %E%d%N\r\n",
4854 PciExpressCap
->SlotControl
.Bits
.DataLinkLayerStateChanged
4860 Print out information of the device slot status information.
4862 @param[in] PciExpressCap The pointer to the structure about the device.
4864 @retval EFI_SUCCESS The operation was successful.
4867 ExplainPcieSlotStatus (
4868 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
4871 ShellPrintEx (-1, -1,
4872 L
" Attention Button Pressed(0): %E%d%N\r\n",
4873 PciExpressCap
->SlotStatus
.Bits
.AttentionButtonPressed
4875 ShellPrintEx (-1, -1,
4876 L
" Power Fault Detected(1): %E%d%N\r\n",
4877 PciExpressCap
->SlotStatus
.Bits
.PowerFaultDetected
4879 ShellPrintEx (-1, -1,
4880 L
" MRL Sensor Changed(2): %E%d%N\r\n",
4881 PciExpressCap
->SlotStatus
.Bits
.MrlSensorChanged
4883 ShellPrintEx (-1, -1,
4884 L
" Presence Detect Changed(3): %E%d%N\r\n",
4885 PciExpressCap
->SlotStatus
.Bits
.PresenceDetectChanged
4887 ShellPrintEx (-1, -1,
4888 L
" Command Completed(4): %E%d%N\r\n",
4889 PciExpressCap
->SlotStatus
.Bits
.CommandCompleted
4891 ShellPrintEx (-1, -1, L
" MRL Sensor State(5): %EMRL ");
4893 PciExpressCap
->SlotStatus
.Bits
.MrlSensor
) {
4894 ShellPrintEx (-1, -1, L
" Opened%N\r\n");
4896 ShellPrintEx (-1, -1, L
" Closed%N\r\n");
4898 ShellPrintEx (-1, -1, L
" Presence Detect State(6): ");
4900 PciExpressCap
->SlotStatus
.Bits
.PresenceDetect
) {
4901 ShellPrintEx (-1, -1, L
"%ECard Present in slot%N\r\n");
4903 ShellPrintEx (-1, -1, L
"%ESlot Empty%N\r\n");
4905 ShellPrintEx (-1, -1, L
" Electromechanical Interlock Status(7): %EElectromechanical Interlock ");
4907 PciExpressCap
->SlotStatus
.Bits
.ElectromechanicalInterlock
) {
4908 ShellPrintEx (-1, -1, L
"Engaged%N\r\n");
4910 ShellPrintEx (-1, -1, L
"Disengaged%N\r\n");
4912 ShellPrintEx (-1, -1,
4913 L
" Data Link Layer State Changed(8): %E%d%N\r\n",
4914 PciExpressCap
->SlotStatus
.Bits
.DataLinkLayerStateChanged
4920 Print out information of the device root information.
4922 @param[in] PciExpressCap The pointer to the structure about the device.
4924 @retval EFI_SUCCESS The operation was successful.
4927 ExplainPcieRootControl (
4928 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
4931 ShellPrintEx (-1, -1,
4932 L
" System Error on Correctable Error Enable(0): %E%d%N\r\n",
4933 PciExpressCap
->RootControl
.Bits
.SystemErrorOnCorrectableError
4935 ShellPrintEx (-1, -1,
4936 L
" System Error on Non-Fatal Error Enable(1): %E%d%N\r\n",
4937 PciExpressCap
->RootControl
.Bits
.SystemErrorOnNonFatalError
4939 ShellPrintEx (-1, -1,
4940 L
" System Error on Fatal Error Enable(2): %E%d%N\r\n",
4941 PciExpressCap
->RootControl
.Bits
.SystemErrorOnFatalError
4943 ShellPrintEx (-1, -1,
4944 L
" PME Interrupt Enable(3): %E%d%N\r\n",
4945 PciExpressCap
->RootControl
.Bits
.PmeInterrupt
4947 ShellPrintEx (-1, -1,
4948 L
" CRS Software Visibility Enable(4): %E%d%N\r\n",
4949 PciExpressCap
->RootControl
.Bits
.CrsSoftwareVisibility
4956 Print out information of the device root capability information.
4958 @param[in] PciExpressCap The pointer to the structure about the device.
4960 @retval EFI_SUCCESS The operation was successful.
4963 ExplainPcieRootCap (
4964 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
4967 ShellPrintEx (-1, -1,
4968 L
" CRS Software Visibility(0): %E%d%N\r\n",
4969 PciExpressCap
->RootCapability
.Bits
.CrsSoftwareVisibility
4976 Print out information of the device root status information.
4978 @param[in] PciExpressCap The pointer to the structure about the device.
4980 @retval EFI_SUCCESS The operation was successful.
4983 ExplainPcieRootStatus (
4984 IN PCI_CAPABILITY_PCIEXP
*PciExpressCap
4987 ShellPrintEx (-1, -1,
4988 L
" PME Requester ID(15:0): %E0x%04x%N\r\n",
4989 PciExpressCap
->RootStatus
.Bits
.PmeRequesterId
4991 ShellPrintEx (-1, -1,
4992 L
" PME Status(16): %E%d%N\r\n",
4993 PciExpressCap
->RootStatus
.Bits
.PmeStatus
4995 ShellPrintEx (-1, -1,
4996 L
" PME Pending(17): %E%d%N\r\n",
4997 PciExpressCap
->RootStatus
.Bits
.PmePending
5003 Function to interpret and print out the link control structure
5005 @param[in] HeaderAddress The Address of this capability header.
5006 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5009 PrintInterpretedExtendedCompatibilityLinkControl (
5010 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5011 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
5014 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_INTERNAL_LINK_CONTROL
*Header
;
5015 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_INTERNAL_LINK_CONTROL
*)HeaderAddress
;
5019 STRING_TOKEN (STR_PCI_EXT_CAP_LINK_CONTROL
),
5020 gShellDebug1HiiHandle
,
5021 Header
->RootComplexLinkCapabilities
,
5022 Header
->RootComplexLinkControl
,
5023 Header
->RootComplexLinkStatus
5027 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5028 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_INTERNAL_LINK_CONTROL
),
5029 (VOID
*) (HeaderAddress
)
5031 return (EFI_SUCCESS
);
5035 Function to interpret and print out the power budgeting structure
5037 @param[in] HeaderAddress The Address of this capability header.
5038 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5041 PrintInterpretedExtendedCompatibilityPowerBudgeting (
5042 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5043 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
5046 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_POWER_BUDGETING
*Header
;
5047 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_POWER_BUDGETING
*)HeaderAddress
;
5051 STRING_TOKEN (STR_PCI_EXT_CAP_POWER
),
5052 gShellDebug1HiiHandle
,
5055 Header
->PowerBudgetCapability
5059 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5060 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_POWER_BUDGETING
),
5061 (VOID
*) (HeaderAddress
)
5063 return (EFI_SUCCESS
);
5067 Function to interpret and print out the ACS structure
5069 @param[in] HeaderAddress The Address of this capability header.
5070 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5073 PrintInterpretedExtendedCompatibilityAcs (
5074 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5075 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
5078 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_ACS_EXTENDED
*Header
;
5082 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_ACS_EXTENDED
*)HeaderAddress
;
5087 STRING_TOKEN (STR_PCI_EXT_CAP_ACS
),
5088 gShellDebug1HiiHandle
,
5089 Header
->AcsCapability
,
5092 if (PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_GET_EGRES_CONTROL(Header
)) {
5093 VectorSize
= PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_GET_EGRES_VECTOR_SIZE(Header
);
5094 if (VectorSize
== 0) {
5097 for (LoopCounter
= 0 ; LoopCounter
* 8 < VectorSize
; LoopCounter
++) {
5100 STRING_TOKEN (STR_PCI_EXT_CAP_ACS2
),
5101 gShellDebug1HiiHandle
,
5103 Header
->EgressControlVectorArray
[LoopCounter
]
5109 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5110 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_ACS_EXTENDED
) + (VectorSize
/ 8) - 1,
5111 (VOID
*) (HeaderAddress
)
5113 return (EFI_SUCCESS
);
5117 Function to interpret and print out the latency tolerance reporting structure
5119 @param[in] HeaderAddress The Address of this capability header.
5120 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5123 PrintInterpretedExtendedCompatibilityLatencyToleranceReporting (
5124 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5125 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
5128 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_LATENCE_TOLERANCE_REPORTING
*Header
;
5129 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_LATENCE_TOLERANCE_REPORTING
*)HeaderAddress
;
5133 STRING_TOKEN (STR_PCI_EXT_CAP_LAT
),
5134 gShellDebug1HiiHandle
,
5135 Header
->MaxSnoopLatency
,
5136 Header
->MaxNoSnoopLatency
5140 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5141 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_LATENCE_TOLERANCE_REPORTING
),
5142 (VOID
*) (HeaderAddress
)
5144 return (EFI_SUCCESS
);
5148 Function to interpret and print out the serial number structure
5150 @param[in] HeaderAddress The Address of this capability header.
5151 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5154 PrintInterpretedExtendedCompatibilitySerialNumber (
5155 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5156 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
5159 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_SERIAL_NUMBER
*Header
;
5160 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_SERIAL_NUMBER
*)HeaderAddress
;
5164 STRING_TOKEN (STR_PCI_EXT_CAP_SN
),
5165 gShellDebug1HiiHandle
,
5166 Header
->SerialNumber
5170 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5171 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_SERIAL_NUMBER
),
5172 (VOID
*) (HeaderAddress
)
5174 return (EFI_SUCCESS
);
5178 Function to interpret and print out the RCRB structure
5180 @param[in] HeaderAddress The Address of this capability header.
5181 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5184 PrintInterpretedExtendedCompatibilityRcrb (
5185 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5186 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
5189 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_RCRB_HEADER
*Header
;
5190 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_RCRB_HEADER
*)HeaderAddress
;
5194 STRING_TOKEN (STR_PCI_EXT_CAP_RCRB
),
5195 gShellDebug1HiiHandle
,
5198 Header
->RcrbCapabilities
,
5203 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5204 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_RCRB_HEADER
),
5205 (VOID
*) (HeaderAddress
)
5207 return (EFI_SUCCESS
);
5211 Function to interpret and print out the vendor specific structure
5213 @param[in] HeaderAddress The Address of this capability header.
5214 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5217 PrintInterpretedExtendedCompatibilityVendorSpecific (
5218 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5219 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
5222 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_VENDOR_SPECIFIC
*Header
;
5223 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_VENDOR_SPECIFIC
*)HeaderAddress
;
5227 STRING_TOKEN (STR_PCI_EXT_CAP_VEN
),
5228 gShellDebug1HiiHandle
,
5229 Header
->VendorSpecificHeader
5233 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5234 PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_GET_SIZE(Header
),
5235 (VOID
*) (HeaderAddress
)
5237 return (EFI_SUCCESS
);
5241 Function to interpret and print out the Event Collector Endpoint Association structure
5243 @param[in] HeaderAddress The Address of this capability header.
5244 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5247 PrintInterpretedExtendedCompatibilityECEA (
5248 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5249 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
5252 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION
*Header
;
5253 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION
*)HeaderAddress
;
5257 STRING_TOKEN (STR_PCI_EXT_CAP_ECEA
),
5258 gShellDebug1HiiHandle
,
5259 Header
->AssociationBitmap
5263 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5264 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION
),
5265 (VOID
*) (HeaderAddress
)
5267 return (EFI_SUCCESS
);
5271 Function to interpret and print out the ARI structure
5273 @param[in] HeaderAddress The Address of this capability header.
5274 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5277 PrintInterpretedExtendedCompatibilityAri (
5278 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5279 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
5282 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_ARI_CAPABILITY
*Header
;
5283 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_ARI_CAPABILITY
*)HeaderAddress
;
5287 STRING_TOKEN (STR_PCI_EXT_CAP_ARI
),
5288 gShellDebug1HiiHandle
,
5289 Header
->AriCapability
,
5294 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5295 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_ARI_CAPABILITY
),
5296 (VOID
*) (HeaderAddress
)
5298 return (EFI_SUCCESS
);
5302 Function to interpret and print out the DPA structure
5304 @param[in] HeaderAddress The Address of this capability header.
5305 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5308 PrintInterpretedExtendedCompatibilityDynamicPowerAllocation (
5309 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5310 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
5313 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_DYNAMIC_POWER_ALLOCATION
*Header
;
5315 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_DYNAMIC_POWER_ALLOCATION
*)HeaderAddress
;
5319 STRING_TOKEN (STR_PCI_EXT_CAP_DPA
),
5320 gShellDebug1HiiHandle
,
5321 Header
->DpaCapability
,
5322 Header
->DpaLatencyIndicator
,
5326 for (LinkCount
= 0 ; LinkCount
< PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_GET_SUBSTATE_MAX(Header
) + 1 ; LinkCount
++) {
5329 STRING_TOKEN (STR_PCI_EXT_CAP_DPA2
),
5330 gShellDebug1HiiHandle
,
5332 Header
->DpaPowerAllocationArray
[LinkCount
]
5337 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5338 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_DYNAMIC_POWER_ALLOCATION
) - 1 + PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_GET_SUBSTATE_MAX(Header
),
5339 (VOID
*) (HeaderAddress
)
5341 return (EFI_SUCCESS
);
5345 Function to interpret and print out the link declaration structure
5347 @param[in] HeaderAddress The Address of this capability header.
5348 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5351 PrintInterpretedExtendedCompatibilityLinkDeclaration (
5352 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5353 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
5356 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_LINK_DECLARATION
*Header
;
5358 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_LINK_DECLARATION
*)HeaderAddress
;
5362 STRING_TOKEN (STR_PCI_EXT_CAP_LINK_DECLAR
),
5363 gShellDebug1HiiHandle
,
5364 Header
->ElementSelfDescription
5367 for (LinkCount
= 0 ; LinkCount
< PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_GET_LINK_COUNT(Header
) ; LinkCount
++) {
5370 STRING_TOKEN (STR_PCI_EXT_CAP_LINK_DECLAR2
),
5371 gShellDebug1HiiHandle
,
5373 Header
->LinkEntry
[LinkCount
]
5378 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5379 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_LINK_DECLARATION
) + (PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_GET_LINK_COUNT(Header
)-1)*sizeof(UINT32
),
5380 (VOID
*) (HeaderAddress
)
5382 return (EFI_SUCCESS
);
5386 Function to interpret and print out the Advanced Error Reporting structure
5388 @param[in] HeaderAddress The Address of this capability header.
5389 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5392 PrintInterpretedExtendedCompatibilityAer (
5393 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5394 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
5397 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_ADVANCED_ERROR_REPORTING
*Header
;
5398 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_ADVANCED_ERROR_REPORTING
*)HeaderAddress
;
5402 STRING_TOKEN (STR_PCI_EXT_CAP_AER
),
5403 gShellDebug1HiiHandle
,
5404 Header
->UncorrectableErrorStatus
,
5405 Header
->UncorrectableErrorMask
,
5406 Header
->UncorrectableErrorSeverity
,
5407 Header
->CorrectableErrorStatus
,
5408 Header
->CorrectableErrorMask
,
5409 Header
->AdvancedErrorCapabilitiesAndControl
,
5410 Header
->HeaderLog
[0],
5411 Header
->HeaderLog
[1],
5412 Header
->HeaderLog
[2],
5413 Header
->HeaderLog
[3],
5414 Header
->RootErrorCommand
,
5415 Header
->RootErrorStatus
,
5416 Header
->ErrorSourceIdentification
,
5417 Header
->CorrectableErrorSourceIdentification
,
5418 Header
->TlpPrefixLog
[0],
5419 Header
->TlpPrefixLog
[1],
5420 Header
->TlpPrefixLog
[2],
5421 Header
->TlpPrefixLog
[3]
5425 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5426 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_ADVANCED_ERROR_REPORTING
),
5427 (VOID
*) (HeaderAddress
)
5429 return (EFI_SUCCESS
);
5433 Function to interpret and print out the multicast structure
5435 @param[in] HeaderAddress The Address of this capability header.
5436 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5437 @param[in] PciExpressCapPtr The address of the PCIe capabilities structure.
5440 PrintInterpretedExtendedCompatibilityMulticast (
5441 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5442 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
,
5443 IN CONST PCI_CAPABILITY_PCIEXP
*PciExpressCapPtr
5446 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTICAST
*Header
;
5447 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTICAST
*)HeaderAddress
;
5451 STRING_TOKEN (STR_PCI_EXT_CAP_MULTICAST
),
5452 gShellDebug1HiiHandle
,
5453 Header
->MultiCastCapability
,
5454 Header
->MulticastControl
,
5455 Header
->McBaseAddress
,
5456 Header
->McReceiveAddress
,
5458 Header
->McBlockUntranslated
,
5459 Header
->McOverlayBar
5464 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5465 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTICAST
),
5466 (VOID
*) (HeaderAddress
)
5469 return (EFI_SUCCESS
);
5473 Function to interpret and print out the virtual channel and multi virtual channel structure
5475 @param[in] HeaderAddress The Address of this capability header.
5476 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5479 PrintInterpretedExtendedCompatibilityVirtualChannel (
5480 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5481 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
5484 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY
*Header
;
5485 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_VC
*CapabilityItem
;
5487 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY
*)HeaderAddress
;
5491 STRING_TOKEN (STR_PCI_EXT_CAP_VC_BASE
),
5492 gShellDebug1HiiHandle
,
5493 Header
->ExtendedVcCount
,
5494 Header
->PortVcCapability1
,
5495 Header
->PortVcCapability2
,
5496 Header
->VcArbTableOffset
,
5497 Header
->PortVcControl
,
5498 Header
->PortVcStatus
5500 for (ItemCount
= 0 ; ItemCount
< Header
->ExtendedVcCount
; ItemCount
++) {
5501 CapabilityItem
= &Header
->Capability
[ItemCount
];
5504 STRING_TOKEN (STR_PCI_EXT_CAP_VC_ITEM
),
5505 gShellDebug1HiiHandle
,
5507 CapabilityItem
->VcResourceCapability
,
5508 CapabilityItem
->PortArbTableOffset
,
5509 CapabilityItem
->VcResourceControl
,
5510 CapabilityItem
->VcResourceStatus
5516 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5517 sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY
)
5518 + Header
->ExtendedVcCount
* sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_VC
),
5519 (VOID
*) (HeaderAddress
)
5522 return (EFI_SUCCESS
);
5526 Function to interpret and print out the resizeable bar structure
5528 @param[in] HeaderAddress The Address of this capability header.
5529 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5532 PrintInterpretedExtendedCompatibilityResizeableBar (
5533 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5534 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
5537 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR
*Header
;
5539 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR
*)HeaderAddress
;
5541 for (ItemCount
= 0 ; ItemCount
< (UINT32
)GET_NUMBER_RESIZABLE_BARS(Header
) ; ItemCount
++) {
5544 STRING_TOKEN (STR_PCI_EXT_CAP_RESIZE_BAR
),
5545 gShellDebug1HiiHandle
,
5547 Header
->Capability
[ItemCount
].ResizableBarCapability
,
5548 Header
->Capability
[ItemCount
].ResizableBarControl
5554 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5555 (UINT32
)GET_NUMBER_RESIZABLE_BARS(Header
) * sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY
),
5556 (VOID
*) (HeaderAddress
)
5559 return (EFI_SUCCESS
);
5563 Function to interpret and print out the TPH structure
5565 @param[in] HeaderAddress The Address of this capability header.
5566 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5569 PrintInterpretedExtendedCompatibilityTph (
5570 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5571 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
5574 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH
*Header
;
5575 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH
*)HeaderAddress
;
5579 STRING_TOKEN (STR_PCI_EXT_CAP_TPH
),
5580 gShellDebug1HiiHandle
,
5581 Header
->TphRequesterCapability
,
5582 Header
->TphRequesterControl
5586 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)Header
->TphStTable
- (UINT8
*)HeadersBaseAddress
),
5587 GET_TPH_TABLE_SIZE(Header
),
5588 (VOID
*)Header
->TphStTable
5593 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5594 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH
) + GET_TPH_TABLE_SIZE(Header
) - sizeof(UINT16
),
5595 (VOID
*) (HeaderAddress
)
5598 return (EFI_SUCCESS
);
5602 Function to interpret and print out the secondary PCIe capability structure
5604 @param[in] HeaderAddress The Address of this capability header.
5605 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5606 @param[in] PciExpressCapPtr The address of the PCIe capabilities structure.
5609 PrintInterpretedExtendedCompatibilitySecondary (
5610 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5611 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
,
5612 IN CONST PCI_CAPABILITY_PCIEXP
*PciExpressCap
5615 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_SECONDARY_PCIE
*Header
;
5616 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_SECONDARY_PCIE
*)HeaderAddress
;
5620 STRING_TOKEN (STR_PCI_EXT_CAP_SECONDARY
),
5621 gShellDebug1HiiHandle
,
5622 Header
->LinkControl3
.Uint32
,
5623 Header
->LaneErrorStatus
5627 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)Header
->EqualizationControl
- (UINT8
*)HeadersBaseAddress
),
5628 PciExpressCap
->LinkCapability
.Bits
.MaxLinkWidth
* sizeof (PCI_EXPRESS_REG_LANE_EQUALIZATION_CONTROL
),
5629 (VOID
*)Header
->EqualizationControl
5634 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5635 sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_SECONDARY_PCIE
) - sizeof (Header
->EqualizationControl
)
5636 + PciExpressCap
->LinkCapability
.Bits
.MaxLinkWidth
* sizeof (PCI_EXPRESS_REG_LANE_EQUALIZATION_CONTROL
),
5637 (VOID
*) (HeaderAddress
)
5640 return (EFI_SUCCESS
);
5644 Display Pcie extended capability details
5646 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5647 @param[in] HeaderAddress The address of this capability header.
5648 @param[in] PciExpressCapPtr The address of the PCIe capabilities structure.
5651 PrintPciExtendedCapabilityDetails(
5652 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
,
5653 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5654 IN CONST PCI_CAPABILITY_PCIEXP
*PciExpressCapPtr
5657 switch (HeaderAddress
->CapabilityId
){
5658 case PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_ID
:
5659 return PrintInterpretedExtendedCompatibilityAer(HeaderAddress
, HeadersBaseAddress
);
5660 case PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_CONTROL_ID
:
5661 return PrintInterpretedExtendedCompatibilityLinkControl(HeaderAddress
, HeadersBaseAddress
);
5662 case PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_ID
:
5663 return PrintInterpretedExtendedCompatibilityLinkDeclaration(HeaderAddress
, HeadersBaseAddress
);
5664 case PCI_EXPRESS_EXTENDED_CAPABILITY_SERIAL_NUMBER_ID
:
5665 return PrintInterpretedExtendedCompatibilitySerialNumber(HeaderAddress
, HeadersBaseAddress
);
5666 case PCI_EXPRESS_EXTENDED_CAPABILITY_POWER_BUDGETING_ID
:
5667 return PrintInterpretedExtendedCompatibilityPowerBudgeting(HeaderAddress
, HeadersBaseAddress
);
5668 case PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_ID
:
5669 return PrintInterpretedExtendedCompatibilityAcs(HeaderAddress
, HeadersBaseAddress
);
5670 case PCI_EXPRESS_EXTENDED_CAPABILITY_LATENCE_TOLERANCE_REPORTING_ID
:
5671 return PrintInterpretedExtendedCompatibilityLatencyToleranceReporting(HeaderAddress
, HeadersBaseAddress
);
5672 case PCI_EXPRESS_EXTENDED_CAPABILITY_ARI_CAPABILITY_ID
:
5673 return PrintInterpretedExtendedCompatibilityAri(HeaderAddress
, HeadersBaseAddress
);
5674 case PCI_EXPRESS_EXTENDED_CAPABILITY_RCRB_HEADER_ID
:
5675 return PrintInterpretedExtendedCompatibilityRcrb(HeaderAddress
, HeadersBaseAddress
);
5676 case PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_ID
:
5677 return PrintInterpretedExtendedCompatibilityVendorSpecific(HeaderAddress
, HeadersBaseAddress
);
5678 case PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_ID
:
5679 return PrintInterpretedExtendedCompatibilityDynamicPowerAllocation(HeaderAddress
, HeadersBaseAddress
);
5680 case PCI_EXPRESS_EXTENDED_CAPABILITY_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION_ID
:
5681 return PrintInterpretedExtendedCompatibilityECEA(HeaderAddress
, HeadersBaseAddress
);
5682 case PCI_EXPRESS_EXTENDED_CAPABILITY_VIRTUAL_CHANNEL_ID
:
5683 case PCI_EXPRESS_EXTENDED_CAPABILITY_MULTI_FUNCTION_VIRTUAL_CHANNEL_ID
:
5684 return PrintInterpretedExtendedCompatibilityVirtualChannel(HeaderAddress
, HeadersBaseAddress
);
5685 case PCI_EXPRESS_EXTENDED_CAPABILITY_MULTICAST_ID
:
5687 // should only be present if PCIE_CAP_DEVICEPORT_TYPE(PciExpressCapPtr->PcieCapReg) == 0100b, 0101b, or 0110b
5689 return PrintInterpretedExtendedCompatibilityMulticast(HeaderAddress
, HeadersBaseAddress
, PciExpressCapPtr
);
5690 case PCI_EXPRESS_EXTENDED_CAPABILITY_RESIZABLE_BAR_ID
:
5691 return PrintInterpretedExtendedCompatibilityResizeableBar(HeaderAddress
, HeadersBaseAddress
);
5692 case PCI_EXPRESS_EXTENDED_CAPABILITY_TPH_ID
:
5693 return PrintInterpretedExtendedCompatibilityTph(HeaderAddress
, HeadersBaseAddress
);
5694 case PCI_EXPRESS_EXTENDED_CAPABILITY_SECONDARY_PCIE_ID
:
5695 return PrintInterpretedExtendedCompatibilitySecondary(HeaderAddress
, HeadersBaseAddress
, PciExpressCapPtr
);
5697 ShellPrintEx (-1, -1,
5698 L
"Unknown PCIe extended capability ID (%04xh). No interpretation available.\r\n",
5699 HeaderAddress
->CapabilityId
5707 Display Pcie device structure.
5709 @param[in] IoDev The pointer to the root pci protocol.
5710 @param[in] Address The Address to start at.
5711 @param[in] CapabilityPtr The offset from the address to start.
5712 @param[in] EnhancedDump The print format for the dump data.
5716 PciExplainPciExpress (
5717 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
,
5719 IN UINT8 CapabilityPtr
,
5720 IN CONST UINT16 EnhancedDump
5723 PCI_CAPABILITY_PCIEXP PciExpressCap
;
5725 UINT64 CapRegAddress
;
5730 UINTN ExtendRegSize
;
5731 UINT64 Pciex_Address
;
5732 UINT8 DevicePortType
;
5736 PCI_EXP_EXT_HDR
*ExtHdr
;
5738 CapRegAddress
= Address
+ CapabilityPtr
;
5743 sizeof (PciExpressCap
) / sizeof (UINT32
),
5747 DevicePortType
= (UINT8
)PciExpressCap
.Capability
.Bits
.DevicePortType
;
5749 ShellPrintEx (-1, -1, L
"\r\nPci Express device capability structure:\r\n");
5751 for (Index
= 0; PcieExplainList
[Index
].Type
< PcieExplainTypeMax
; Index
++) {
5752 if (ShellGetExecutionBreakFlag()) {
5755 RegAddr
= ((UINT8
*) &PciExpressCap
) + PcieExplainList
[Index
].Offset
;
5756 switch (PcieExplainList
[Index
].Width
) {
5757 case FieldWidthUINT8
:
5758 RegValue
= *(UINT8
*) RegAddr
;
5760 case FieldWidthUINT16
:
5761 RegValue
= *(UINT16
*) RegAddr
;
5763 case FieldWidthUINT32
:
5764 RegValue
= *(UINT32
*) RegAddr
;
5770 ShellPrintHiiEx(-1, -1, NULL
,
5771 PcieExplainList
[Index
].Token
,
5772 gShellDebug1HiiHandle
,
5773 PcieExplainList
[Index
].Offset
,
5776 if (PcieExplainList
[Index
].Func
== NULL
) {
5779 switch (PcieExplainList
[Index
].Type
) {
5780 case PcieExplainTypeLink
:
5782 // Link registers should not be used by
5783 // a) Root Complex Integrated Endpoint
5784 // b) Root Complex Event Collector
5786 if (DevicePortType
== PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX_INTEGRATED_ENDPOINT
||
5787 DevicePortType
== PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX_EVENT_COLLECTOR
) {
5791 case PcieExplainTypeSlot
:
5793 // Slot registers are only valid for
5794 // a) Root Port of PCI Express Root Complex
5795 // b) Downstream Port of PCI Express Switch
5796 // and when SlotImplemented bit is set in PCIE cap register.
5798 if ((DevicePortType
!= PCIE_DEVICE_PORT_TYPE_ROOT_PORT
&&
5799 DevicePortType
!= PCIE_DEVICE_PORT_TYPE_DOWNSTREAM_PORT
) ||
5800 !PciExpressCap
.Capability
.Bits
.SlotImplemented
) {
5804 case PcieExplainTypeRoot
:
5806 // Root registers are only valid for
5807 // Root Port of PCI Express Root Complex
5809 if (DevicePortType
!= PCIE_DEVICE_PORT_TYPE_ROOT_PORT
) {
5816 PcieExplainList
[Index
].Func (&PciExpressCap
);
5819 Bus
= (UINT8
) (RShiftU64 (Address
, 24));
5820 Dev
= (UINT8
) (RShiftU64 (Address
, 16));
5821 Func
= (UINT8
) (RShiftU64 (Address
, 8));
5823 Pciex_Address
= EFI_PCI_ADDRESS (Bus
, Dev
, Func
, EFI_PCIE_CAPABILITY_BASE_OFFSET
);
5825 ExtendRegSize
= 0x1000 - EFI_PCIE_CAPABILITY_BASE_OFFSET
;
5827 ExRegBuffer
= (UINT8
*) AllocateZeroPool (ExtendRegSize
);
5830 // PciRootBridgeIo protocol should support pci express extend space IO
5831 // (Begins at offset EFI_PCIE_CAPABILITY_BASE_OFFSET)
5833 Status
= IoDev
->Pci
.Read (
5837 (ExtendRegSize
) / sizeof (UINT32
),
5838 (VOID
*) (ExRegBuffer
)
5840 if (EFI_ERROR (Status
) || ExRegBuffer
== NULL
) {
5841 SHELL_FREE_NON_NULL(ExRegBuffer
);
5842 return EFI_UNSUPPORTED
;
5845 ExtHdr
= (PCI_EXP_EXT_HDR
*)ExRegBuffer
;
5846 while (ExtHdr
->CapabilityId
!= 0 && ExtHdr
->CapabilityVersion
!= 0) {
5848 // Process this item
5850 if (EnhancedDump
== 0xFFFF || EnhancedDump
== ExtHdr
->CapabilityId
) {
5854 PrintPciExtendedCapabilityDetails((PCI_EXP_EXT_HDR
*)ExRegBuffer
, ExtHdr
, &PciExpressCap
);
5858 // Advance to the next item if it exists
5860 if (ExtHdr
->NextCapabilityOffset
!= 0) {
5861 ExtHdr
= (PCI_EXP_EXT_HDR
*)((UINT8
*)ExRegBuffer
+ ExtHdr
->NextCapabilityOffset
- EFI_PCIE_CAPABILITY_BASE_OFFSET
);
5866 SHELL_FREE_NON_NULL(ExRegBuffer
);