2 Main file for Pci shell Debug1 function.
4 Copyright (c) 2013 Hewlett-Packard Development Company, L.P.
5 Copyright (c) 2005 - 2014, Intel Corporation. All rights reserved.<BR>
6 This program and the accompanying materials
7 are licensed and made available under the terms and conditions of the BSD License
8 which accompanies this distribution. The full text of the license may be found at
9 http://opensource.org/licenses/bsd-license.php
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
16 #include "UefiShellDebug1CommandsLib.h"
17 #include <Protocol/PciRootBridgeIo.h>
18 #include <Library/ShellLib.h>
19 #include <IndustryStandard/Pci.h>
20 #include <IndustryStandard/Acpi.h>
23 #define PCI_CLASS_STRING_LIMIT 54
25 // Printable strings for Pci class code
28 CHAR16
*BaseClass
; // Pointer to the PCI base class string
29 CHAR16
*SubClass
; // Pointer to the PCI sub class string
30 CHAR16
*PIFClass
; // Pointer to the PCI programming interface string
34 // a structure holding a single entry, which also points to its lower level
37 typedef struct PCI_CLASS_ENTRY_TAG
{
38 UINT8 Code
; // Class, subclass or I/F code
39 CHAR16
*DescText
; // Description string
40 struct PCI_CLASS_ENTRY_TAG
*LowerLevelClass
; // Subclass or I/F if any
44 // Declarations of entries which contain printable strings for class codes
45 // in PCI configuration space
47 PCI_CLASS_ENTRY PCIBlankEntry
[];
48 PCI_CLASS_ENTRY PCISubClass_00
[];
49 PCI_CLASS_ENTRY PCISubClass_01
[];
50 PCI_CLASS_ENTRY PCISubClass_02
[];
51 PCI_CLASS_ENTRY PCISubClass_03
[];
52 PCI_CLASS_ENTRY PCISubClass_04
[];
53 PCI_CLASS_ENTRY PCISubClass_05
[];
54 PCI_CLASS_ENTRY PCISubClass_06
[];
55 PCI_CLASS_ENTRY PCISubClass_07
[];
56 PCI_CLASS_ENTRY PCISubClass_08
[];
57 PCI_CLASS_ENTRY PCISubClass_09
[];
58 PCI_CLASS_ENTRY PCISubClass_0a
[];
59 PCI_CLASS_ENTRY PCISubClass_0b
[];
60 PCI_CLASS_ENTRY PCISubClass_0c
[];
61 PCI_CLASS_ENTRY PCISubClass_0d
[];
62 PCI_CLASS_ENTRY PCISubClass_0e
[];
63 PCI_CLASS_ENTRY PCISubClass_0f
[];
64 PCI_CLASS_ENTRY PCISubClass_10
[];
65 PCI_CLASS_ENTRY PCISubClass_11
[];
66 PCI_CLASS_ENTRY PCIPIFClass_0101
[];
67 PCI_CLASS_ENTRY PCIPIFClass_0300
[];
68 PCI_CLASS_ENTRY PCIPIFClass_0604
[];
69 PCI_CLASS_ENTRY PCIPIFClass_0700
[];
70 PCI_CLASS_ENTRY PCIPIFClass_0701
[];
71 PCI_CLASS_ENTRY PCIPIFClass_0703
[];
72 PCI_CLASS_ENTRY PCIPIFClass_0800
[];
73 PCI_CLASS_ENTRY PCIPIFClass_0801
[];
74 PCI_CLASS_ENTRY PCIPIFClass_0802
[];
75 PCI_CLASS_ENTRY PCIPIFClass_0803
[];
76 PCI_CLASS_ENTRY PCIPIFClass_0904
[];
77 PCI_CLASS_ENTRY PCIPIFClass_0c00
[];
78 PCI_CLASS_ENTRY PCIPIFClass_0c03
[];
79 PCI_CLASS_ENTRY PCIPIFClass_0e00
[];
82 // Base class strings entries
84 PCI_CLASS_ENTRY gClassStringList
[] = {
92 L
"Mass Storage Controller",
97 L
"Network Controller",
102 L
"Display Controller",
107 L
"Multimedia Device",
112 L
"Memory Controller",
122 L
"Simple Communications Controllers",
127 L
"Base System Peripherals",
147 L
"Serial Bus Controllers",
152 L
"Wireless Controllers",
157 L
"Intelligent IO Controllers",
162 L
"Satellite Communications Controllers",
167 L
"Encryption/Decryption Controllers",
172 L
"Data Acquisition & Signal Processing Controllers",
177 L
"Device does not fit in any defined classes",
183 /* null string ends the list */NULL
188 // Subclass strings entries
190 PCI_CLASS_ENTRY PCIBlankEntry
[] = {
199 /* null string ends the list */NULL
203 PCI_CLASS_ENTRY PCISubClass_00
[] = {
206 L
"All devices other than VGA",
211 L
"VGA-compatible devices",
217 /* null string ends the list */NULL
221 PCI_CLASS_ENTRY PCISubClass_01
[] = {
234 L
"Floppy disk controller",
249 L
"Other mass storage controller",
255 /* null string ends the list */NULL
259 PCI_CLASS_ENTRY PCISubClass_02
[] = {
262 L
"Ethernet controller",
267 L
"Token ring controller",
287 L
"Other network controller",
293 /* null string ends the list */NULL
297 PCI_CLASS_ENTRY PCISubClass_03
[] = {
300 L
"VGA/8514 controller",
315 L
"Other display controller",
321 /* null string ends the list */PCIBlankEntry
325 PCI_CLASS_ENTRY PCISubClass_04
[] = {
338 L
"Computer Telephony device",
343 L
"Other multimedia device",
349 /* null string ends the list */NULL
353 PCI_CLASS_ENTRY PCISubClass_05
[] = {
356 L
"RAM memory controller",
361 L
"Flash memory controller",
366 L
"Other memory controller",
372 /* null string ends the list */NULL
376 PCI_CLASS_ENTRY PCISubClass_06
[] = {
394 L
"PCI/Micro Channel bridge",
404 L
"PCI/PCMCIA bridge",
424 L
"Other bridge type",
430 /* null string ends the list */NULL
434 PCI_CLASS_ENTRY PCISubClass_07
[] = {
437 L
"Serial controller",
447 L
"Multiport serial controller",
457 L
"Other communication device",
463 /* null string ends the list */NULL
467 PCI_CLASS_ENTRY PCISubClass_08
[] = {
490 L
"Generic PCI Hot-Plug controller",
495 L
"Other system peripheral",
501 /* null string ends the list */NULL
505 PCI_CLASS_ENTRY PCISubClass_09
[] = {
508 L
"Keyboard controller",
523 L
"Scanner controller",
528 L
"Gameport controller",
533 L
"Other input controller",
539 /* null string ends the list */NULL
543 PCI_CLASS_ENTRY PCISubClass_0a
[] = {
546 L
"Generic docking station",
551 L
"Other type of docking station",
557 /* null string ends the list */NULL
561 PCI_CLASS_ENTRY PCISubClass_0b
[] = {
605 /* null string ends the list */NULL
609 PCI_CLASS_ENTRY PCISubClass_0c
[] = {
612 L
"Firewire(IEEE 1394)",
637 L
"System Management Bus",
648 /* null string ends the list */NULL
652 PCI_CLASS_ENTRY PCISubClass_0d
[] = {
655 L
"iRDA compatible controller",
660 L
"Consumer IR controller",
670 L
"Other type of wireless controller",
676 /* null string ends the list */NULL
680 PCI_CLASS_ENTRY PCISubClass_0e
[] = {
689 /* null string ends the list */NULL
693 PCI_CLASS_ENTRY PCISubClass_0f
[] = {
717 /* null string ends the list */NULL
721 PCI_CLASS_ENTRY PCISubClass_10
[] = {
724 L
"Network & computing Encrypt/Decrypt",
729 L
"Entertainment Encrypt/Decrypt",
734 L
"Other Encrypt/Decrypt",
740 /* null string ends the list */NULL
744 PCI_CLASS_ENTRY PCISubClass_11
[] = {
752 L
"Other DAQ & SP controllers",
758 /* null string ends the list */NULL
763 // Programming Interface entries
765 PCI_CLASS_ENTRY PCIPIFClass_0101
[] = {
793 L
"OM-primary, OM-secondary",
798 L
"PI-primary, OM-secondary",
803 L
"OM/PI-primary, OM-secondary",
813 L
"OM-primary, PI-secondary",
818 L
"PI-primary, PI-secondary",
823 L
"OM/PI-primary, PI-secondary",
833 L
"OM-primary, OM/PI-secondary",
838 L
"PI-primary, OM/PI-secondary",
843 L
"OM/PI-primary, OM/PI-secondary",
853 L
"Master, OM-primary",
858 L
"Master, PI-primary",
863 L
"Master, OM/PI-primary",
868 L
"Master, OM-secondary",
873 L
"Master, OM-primary, OM-secondary",
878 L
"Master, PI-primary, OM-secondary",
883 L
"Master, OM/PI-primary, OM-secondary",
888 L
"Master, OM-secondary",
893 L
"Master, OM-primary, PI-secondary",
898 L
"Master, PI-primary, PI-secondary",
903 L
"Master, OM/PI-primary, PI-secondary",
908 L
"Master, OM-secondary",
913 L
"Master, OM-primary, OM/PI-secondary",
918 L
"Master, PI-primary, OM/PI-secondary",
923 L
"Master, OM/PI-primary, OM/PI-secondary",
929 /* null string ends the list */NULL
933 PCI_CLASS_ENTRY PCIPIFClass_0300
[] = {
947 /* null string ends the list */NULL
951 PCI_CLASS_ENTRY PCIPIFClass_0604
[] = {
959 L
"Subtractive decode",
965 /* null string ends the list */NULL
969 PCI_CLASS_ENTRY PCIPIFClass_0700
[] = {
972 L
"Generic XT-compatible",
1002 L
"16950-compatible",
1008 /* null string ends the list */NULL
1012 PCI_CLASS_ENTRY PCIPIFClass_0701
[] = {
1025 L
"ECP 1.X-compliant",
1035 L
"IEEE 1284 target (not a controller)",
1041 /* null string ends the list */NULL
1045 PCI_CLASS_ENTRY PCIPIFClass_0703
[] = {
1053 L
"Hayes-compatible 16450",
1058 L
"Hayes-compatible 16550",
1063 L
"Hayes-compatible 16650",
1068 L
"Hayes-compatible 16750",
1074 /* null string ends the list */NULL
1078 PCI_CLASS_ENTRY PCIPIFClass_0800
[] = {
1101 L
"IO(x) APIC interrupt controller",
1107 /* null string ends the list */NULL
1111 PCI_CLASS_ENTRY PCIPIFClass_0801
[] = {
1130 /* null string ends the list */NULL
1134 PCI_CLASS_ENTRY PCIPIFClass_0802
[] = {
1153 /* null string ends the list */NULL
1157 PCI_CLASS_ENTRY PCIPIFClass_0803
[] = {
1176 /* null string ends the list */NULL
1180 PCI_CLASS_ENTRY PCIPIFClass_0904
[] = {
1194 /* null string ends the list */NULL
1198 PCI_CLASS_ENTRY PCIPIFClass_0c00
[] = {
1201 L
"Universal Host Controller spec",
1206 L
"Open Host Controller spec",
1211 L
"No specific programming interface",
1216 L
"(Not Host Controller)",
1222 /* null string ends the list */NULL
1226 PCI_CLASS_ENTRY PCIPIFClass_0c03
[] = {
1234 L
"Using 1394 OpenHCI spec",
1240 /* null string ends the list */NULL
1244 PCI_CLASS_ENTRY PCIPIFClass_0e00
[] = {
1247 L
"Message FIFO at offset 40h",
1258 /* null string ends the list */NULL
1264 Generates printable Unicode strings that represent PCI device class,
1265 subclass and programmed I/F based on a value passed to the function.
1267 @param[in] ClassCode Value representing the PCI "Class Code" register read from a
1268 PCI device. The encodings are:
1269 bits 23:16 - Base Class Code
1270 bits 15:8 - Sub-Class Code
1271 bits 7:0 - Programming Interface
1272 @param[in, out] ClassStrings Pointer of PCI_CLASS_STRINGS structure, which contains
1273 printable class strings corresponding to ClassCode. The
1274 caller must not modify the strings that are pointed by
1275 the fields in ClassStrings.
1278 PciGetClassStrings (
1279 IN UINT32 ClassCode
,
1280 IN OUT PCI_CLASS_STRINGS
*ClassStrings
1285 PCI_CLASS_ENTRY
*CurrentClass
;
1288 // Assume no strings found
1290 ClassStrings
->BaseClass
= L
"UNDEFINED";
1291 ClassStrings
->SubClass
= L
"UNDEFINED";
1292 ClassStrings
->PIFClass
= L
"UNDEFINED";
1294 CurrentClass
= gClassStringList
;
1295 Code
= (UINT8
) (ClassCode
>> 16);
1299 // Go through all entries of the base class, until the entry with a matching
1300 // base class code is found. If reaches an entry with a null description
1301 // text, the last entry is met, which means no text for the base class was
1302 // found, so no more action is needed.
1304 while (Code
!= CurrentClass
[Index
].Code
) {
1305 if (NULL
== CurrentClass
[Index
].DescText
) {
1312 // A base class was found. Assign description, and check if this class has
1313 // sub-class defined. If sub-class defined, no more action is needed,
1314 // otherwise, continue to find description for the sub-class code.
1316 ClassStrings
->BaseClass
= CurrentClass
[Index
].DescText
;
1317 if (NULL
== CurrentClass
[Index
].LowerLevelClass
) {
1321 // find Subclass entry
1323 CurrentClass
= CurrentClass
[Index
].LowerLevelClass
;
1324 Code
= (UINT8
) (ClassCode
>> 8);
1328 // Go through all entries of the sub-class, until the entry with a matching
1329 // sub-class code is found. If reaches an entry with a null description
1330 // text, the last entry is met, which means no text for the sub-class was
1331 // found, so no more action is needed.
1333 while (Code
!= CurrentClass
[Index
].Code
) {
1334 if (NULL
== CurrentClass
[Index
].DescText
) {
1341 // A class was found for the sub-class code. Assign description, and check if
1342 // this sub-class has programming interface defined. If no, no more action is
1343 // needed, otherwise, continue to find description for the programming
1346 ClassStrings
->SubClass
= CurrentClass
[Index
].DescText
;
1347 if (NULL
== CurrentClass
[Index
].LowerLevelClass
) {
1351 // Find programming interface entry
1353 CurrentClass
= CurrentClass
[Index
].LowerLevelClass
;
1354 Code
= (UINT8
) ClassCode
;
1358 // Go through all entries of the I/F entries, until the entry with a
1359 // matching I/F code is found. If reaches an entry with a null description
1360 // text, the last entry is met, which means no text was found, so no more
1361 // action is needed.
1363 while (Code
!= CurrentClass
[Index
].Code
) {
1364 if (NULL
== CurrentClass
[Index
].DescText
) {
1371 // A class was found for the I/F code. Assign description, done!
1373 ClassStrings
->PIFClass
= CurrentClass
[Index
].DescText
;
1378 Print strings that represent PCI device class, subclass and programmed I/F.
1380 @param[in] ClassCodePtr Points to the memory which stores register Class Code in PCI
1382 @param[in] IncludePIF If the printed string should include the programming I/F part
1386 IN UINT8
*ClassCodePtr
,
1387 IN BOOLEAN IncludePIF
1391 PCI_CLASS_STRINGS ClassStrings
;
1394 ClassCode
|= ClassCodePtr
[0];
1395 ClassCode
|= (ClassCodePtr
[1] << 8);
1396 ClassCode
|= (ClassCodePtr
[2] << 16);
1399 // Get name from class code
1401 PciGetClassStrings (ClassCode
, &ClassStrings
);
1405 // Print base class, sub class, and programming inferface name
1407 ShellPrintEx (-1, -1, L
"%s - %s - %s",
1408 ClassStrings
.BaseClass
,
1409 ClassStrings
.SubClass
,
1410 ClassStrings
.PIFClass
1415 // Only print base class and sub class name
1417 ShellPrintEx (-1, -1, L
"%s - %s",
1418 ClassStrings
.BaseClass
,
1419 ClassStrings
.SubClass
1425 This function finds out the protocol which is in charge of the given
1426 segment, and its bus range covers the current bus number. It lookes
1427 each instances of RootBridgeIoProtocol handle, until the one meets the
1430 @param[in] HandleBuf Buffer which holds all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.
1431 @param[in] HandleCount Count of all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.
1432 @param[in] Segment Segment number of device we are dealing with.
1433 @param[in] Bus Bus number of device we are dealing with.
1434 @param[out] IoDev Handle used to access configuration space of PCI device.
1436 @retval EFI_SUCCESS The command completed successfully.
1437 @retval EFI_INVALID_PARAMETER Invalid parameter.
1441 PciFindProtocolInterface (
1442 IN EFI_HANDLE
*HandleBuf
,
1443 IN UINTN HandleCount
,
1446 OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
**IoDev
1450 This function gets the protocol interface from the given handle, and
1451 obtains its address space descriptors.
1453 @param[in] Handle The PCI_ROOT_BRIDIGE_IO_PROTOCOL handle.
1454 @param[out] IoDev Handle used to access configuration space of PCI device.
1455 @param[out] Descriptors Points to the address space descriptors.
1457 @retval EFI_SUCCESS The command completed successfully
1460 PciGetProtocolAndResource (
1461 IN EFI_HANDLE Handle
,
1462 OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
**IoDev
,
1463 OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
**Descriptors
1467 This function get the next bus range of given address space descriptors.
1468 It also moves the pointer backward a node, to get prepared to be called
1471 @param[in, out] Descriptors Points to current position of a serial of address space
1473 @param[out] MinBus The lower range of bus number.
1474 @param[out] MaxBus The upper range of bus number.
1475 @param[out] IsEnd Meet end of the serial of descriptors.
1477 @retval EFI_SUCCESS The command completed successfully.
1480 PciGetNextBusRange (
1481 IN OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
**Descriptors
,
1488 Explain the data in PCI configuration space. The part which is common for
1489 PCI device and bridge is interpreted in this function. It calls other
1490 functions to interpret data unique for device or bridge.
1492 @param[in] ConfigSpace Data in PCI configuration space.
1493 @param[in] Address Address used to access configuration space of this PCI device.
1494 @param[in] IoDev Handle used to access configuration space of PCI device.
1495 @param[in] EnhancedDump The print format for the dump data.
1497 @retval EFI_SUCCESS The command completed successfully.
1501 IN PCI_CONFIG_SPACE
*ConfigSpace
,
1503 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
,
1504 IN CONST UINT16 EnhancedDump
1508 Explain the device specific part of data in PCI configuration space.
1510 @param[in] Device Data in PCI configuration space.
1511 @param[in] Address Address used to access configuration space of this PCI device.
1512 @param[in] IoDev Handle used to access configuration space of PCI device.
1514 @retval EFI_SUCCESS The command completed successfully.
1517 PciExplainDeviceData (
1518 IN PCI_DEVICE_HEADER
*Device
,
1520 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
1524 Explain the bridge specific part of data in PCI configuration space.
1526 @param[in] Bridge Bridge specific data region in PCI configuration space.
1527 @param[in] Address Address used to access configuration space of this PCI device.
1528 @param[in] IoDev Handle used to access configuration space of PCI device.
1530 @retval EFI_SUCCESS The command completed successfully.
1533 PciExplainBridgeData (
1534 IN PCI_BRIDGE_HEADER
*Bridge
,
1536 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
1540 Explain the Base Address Register(Bar) in PCI configuration space.
1542 @param[in] Bar Points to the Base Address Register intended to interpret.
1543 @param[in] Command Points to the register Command.
1544 @param[in] Address Address used to access configuration space of this PCI device.
1545 @param[in] IoDev Handle used to access configuration space of PCI device.
1546 @param[in, out] Index The Index.
1548 @retval EFI_SUCCESS The command completed successfully.
1555 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
,
1560 Explain the cardbus specific part of data in PCI configuration space.
1562 @param[in] CardBus CardBus specific region of PCI configuration space.
1563 @param[in] Address Address used to access configuration space of this PCI device.
1564 @param[in] IoDev Handle used to access configuration space of PCI device.
1566 @retval EFI_SUCCESS The command completed successfully.
1569 PciExplainCardBusData (
1570 IN PCI_CARDBUS_HEADER
*CardBus
,
1572 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
1576 Explain each meaningful bit of register Status. The definition of Status is
1577 slightly different depending on the PCI header type.
1579 @param[in] Status Points to the content of register Status.
1580 @param[in] MainStatus Indicates if this register is main status(not secondary
1582 @param[in] HeaderType Header type of this PCI device.
1584 @retval EFI_SUCCESS The command completed successfully.
1589 IN BOOLEAN MainStatus
,
1590 IN PCI_HEADER_TYPE HeaderType
1594 Explain each meaningful bit of register Command.
1596 @param[in] Command Points to the content of register Command.
1598 @retval EFI_SUCCESS The command completed successfully.
1606 Explain each meaningful bit of register Bridge Control.
1608 @param[in] BridgeControl Points to the content of register Bridge Control.
1609 @param[in] HeaderType The headertype.
1611 @retval EFI_SUCCESS The command completed successfully.
1614 PciExplainBridgeControl (
1615 IN UINT16
*BridgeControl
,
1616 IN PCI_HEADER_TYPE HeaderType
1620 Print each capability structure.
1622 @param[in] IoDev The pointer to the deivce.
1623 @param[in] Address The address to start at.
1624 @param[in] CapPtr The offset from the address.
1625 @param[in] EnhancedDump The print format for the dump data.
1627 @retval EFI_SUCCESS The operation was successful.
1630 PciExplainCapabilityStruct (
1631 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
,
1634 IN CONST UINT16 EnhancedDump
1638 Display Pcie device structure.
1640 @param[in] IoDev The pointer to the root pci protocol.
1641 @param[in] Address The Address to start at.
1642 @param[in] CapabilityPtr The offset from the address to start.
1643 @param[in] EnhancedDump The print format for the dump data.
1645 @retval EFI_SUCCESS The command completed successfully.
1646 @retval @retval EFI_SUCCESS Pci express extend space IO is not suppoted.
1649 PciExplainPciExpress (
1650 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
,
1652 IN UINT8 CapabilityPtr
,
1653 IN CONST UINT16 EnhancedDump
1657 Print out information of the capability information.
1659 @param[in] PciExpressCap The pointer to the structure about the device.
1661 @retval EFI_SUCCESS The operation was successful.
1665 IN PCIE_CAP_STURCTURE
*PciExpressCap
1669 Print out information of the device capability information.
1671 @param[in] PciExpressCap The pointer to the structure about the device.
1673 @retval EFI_SUCCESS The operation was successful.
1676 ExplainPcieDeviceCap (
1677 IN PCIE_CAP_STURCTURE
*PciExpressCap
1681 Print out information of the device control information.
1683 @param[in] PciExpressCap The pointer to the structure about the device.
1685 @retval EFI_SUCCESS The operation was successful.
1688 ExplainPcieDeviceControl (
1689 IN PCIE_CAP_STURCTURE
*PciExpressCap
1693 Print out information of the device status information.
1695 @param[in] PciExpressCap The pointer to the structure about the device.
1697 @retval EFI_SUCCESS The operation was successful.
1700 ExplainPcieDeviceStatus (
1701 IN PCIE_CAP_STURCTURE
*PciExpressCap
1705 Print out information of the device link information.
1707 @param[in] PciExpressCap The pointer to the structure about the device.
1709 @retval EFI_SUCCESS The operation was successful.
1712 ExplainPcieLinkCap (
1713 IN PCIE_CAP_STURCTURE
*PciExpressCap
1717 Print out information of the device link control information.
1719 @param[in] PciExpressCap The pointer to the structure about the device.
1721 @retval EFI_SUCCESS The operation was successful.
1724 ExplainPcieLinkControl (
1725 IN PCIE_CAP_STURCTURE
*PciExpressCap
1729 Print out information of the device link status information.
1731 @param[in] PciExpressCap The pointer to the structure about the device.
1733 @retval EFI_SUCCESS The operation was successful.
1736 ExplainPcieLinkStatus (
1737 IN PCIE_CAP_STURCTURE
*PciExpressCap
1741 Print out information of the device slot information.
1743 @param[in] PciExpressCap The pointer to the structure about the device.
1745 @retval EFI_SUCCESS The operation was successful.
1748 ExplainPcieSlotCap (
1749 IN PCIE_CAP_STURCTURE
*PciExpressCap
1753 Print out information of the device slot control information.
1755 @param[in] PciExpressCap The pointer to the structure about the device.
1757 @retval EFI_SUCCESS The operation was successful.
1760 ExplainPcieSlotControl (
1761 IN PCIE_CAP_STURCTURE
*PciExpressCap
1765 Print out information of the device slot status information.
1767 @param[in] PciExpressCap The pointer to the structure about the device.
1769 @retval EFI_SUCCESS The operation was successful.
1772 ExplainPcieSlotStatus (
1773 IN PCIE_CAP_STURCTURE
*PciExpressCap
1777 Print out information of the device root information.
1779 @param[in] PciExpressCap The pointer to the structure about the device.
1781 @retval EFI_SUCCESS The operation was successful.
1784 ExplainPcieRootControl (
1785 IN PCIE_CAP_STURCTURE
*PciExpressCap
1789 Print out information of the device root capability information.
1791 @param[in] PciExpressCap The pointer to the structure about the device.
1793 @retval EFI_SUCCESS The operation was successful.
1796 ExplainPcieRootCap (
1797 IN PCIE_CAP_STURCTURE
*PciExpressCap
1801 Print out information of the device root status information.
1803 @param[in] PciExpressCap The pointer to the structure about the device.
1805 @retval EFI_SUCCESS The operation was successful.
1808 ExplainPcieRootStatus (
1809 IN PCIE_CAP_STURCTURE
*PciExpressCap
1812 typedef EFI_STATUS (*PCIE_EXPLAIN_FUNCTION
) (IN PCIE_CAP_STURCTURE
*PciExpressCap
);
1818 } PCIE_CAPREG_FIELD_WIDTH
;
1821 PcieExplainTypeCommon
,
1822 PcieExplainTypeDevice
,
1823 PcieExplainTypeLink
,
1824 PcieExplainTypeSlot
,
1825 PcieExplainTypeRoot
,
1827 } PCIE_EXPLAIN_TYPE
;
1833 PCIE_CAPREG_FIELD_WIDTH Width
;
1834 PCIE_EXPLAIN_FUNCTION Func
;
1835 PCIE_EXPLAIN_TYPE Type
;
1836 } PCIE_EXPLAIN_STRUCT
;
1838 PCIE_EXPLAIN_STRUCT PcieExplainList
[] = {
1840 STRING_TOKEN (STR_PCIEX_CAPABILITY_CAPID
),
1844 PcieExplainTypeCommon
1847 STRING_TOKEN (STR_PCIEX_NEXTCAP_PTR
),
1851 PcieExplainTypeCommon
1854 STRING_TOKEN (STR_PCIEX_CAP_REGISTER
),
1858 PcieExplainTypeCommon
1861 STRING_TOKEN (STR_PCIEX_DEVICE_CAP
),
1864 ExplainPcieDeviceCap
,
1865 PcieExplainTypeDevice
1868 STRING_TOKEN (STR_PCIEX_DEVICE_CONTROL
),
1871 ExplainPcieDeviceControl
,
1872 PcieExplainTypeDevice
1875 STRING_TOKEN (STR_PCIEX_DEVICE_STATUS
),
1878 ExplainPcieDeviceStatus
,
1879 PcieExplainTypeDevice
1882 STRING_TOKEN (STR_PCIEX_LINK_CAPABILITIES
),
1889 STRING_TOKEN (STR_PCIEX_LINK_CONTROL
),
1892 ExplainPcieLinkControl
,
1896 STRING_TOKEN (STR_PCIEX_LINK_STATUS
),
1899 ExplainPcieLinkStatus
,
1903 STRING_TOKEN (STR_PCIEX_SLOT_CAPABILITIES
),
1910 STRING_TOKEN (STR_PCIEX_SLOT_CONTROL
),
1913 ExplainPcieSlotControl
,
1917 STRING_TOKEN (STR_PCIEX_SLOT_STATUS
),
1920 ExplainPcieSlotStatus
,
1924 STRING_TOKEN (STR_PCIEX_ROOT_CONTROL
),
1927 ExplainPcieRootControl
,
1931 STRING_TOKEN (STR_PCIEX_RSVDP
),
1938 STRING_TOKEN (STR_PCIEX_ROOT_STATUS
),
1941 ExplainPcieRootStatus
,
1947 (PCIE_CAPREG_FIELD_WIDTH
)0,
1956 PCI_CONFIG_SPACE
*mConfigSpace
= NULL
;
1957 STATIC CONST SHELL_PARAM_ITEM ParamList
[] = {
1963 CHAR16
*DevicePortTypeTable
[] = {
1964 L
"PCI Express Endpoint",
1965 L
"Legacy PCI Express Endpoint",
1968 L
"Root Port of PCI Express Root Complex",
1969 L
"Upstream Port of PCI Express Switch",
1970 L
"Downstream Port of PCI Express Switch",
1971 L
"PCI Express to PCI/PCI-X Bridge",
1972 L
"PCI/PCI-X to PCI Express Bridge",
1973 L
"Root Complex Integrated Endpoint",
1974 L
"Root Complex Event Collector"
1977 CHAR16
*L0sLatencyStrTable
[] = {
1979 L
"64ns to less than 128ns",
1980 L
"128ns to less than 256ns",
1981 L
"256ns to less than 512ns",
1982 L
"512ns to less than 1us",
1983 L
"1us to less than 2us",
1988 CHAR16
*L1LatencyStrTable
[] = {
1990 L
"1us to less than 2us",
1991 L
"2us to less than 4us",
1992 L
"4us to less than 8us",
1993 L
"8us to less than 16us",
1994 L
"16us to less than 32us",
1999 CHAR16
*ASPMCtrlStrTable
[] = {
2001 L
"L0s Entry Enabled",
2002 L
"L1 Entry Enabled",
2003 L
"L0s and L1 Entry Enabled"
2006 CHAR16
*SlotPwrLmtScaleTable
[] = {
2013 CHAR16
*IndicatorTable
[] = {
2022 Function for 'pci' command.
2024 @param[in] ImageHandle Handle to the Image (NULL if Internal).
2025 @param[in] SystemTable Pointer to the System Table (NULL if Internal).
2029 ShellCommandRunPci (
2030 IN EFI_HANDLE ImageHandle
,
2031 IN EFI_SYSTEM_TABLE
*SystemTable
2039 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
;
2041 PCI_COMMON_HEADER PciHeader
;
2042 PCI_CONFIG_SPACE ConfigSpace
;
2046 BOOLEAN ExplainData
;
2050 UINTN HandleBufSize
;
2051 EFI_HANDLE
*HandleBuf
;
2053 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
*Descriptors
;
2057 LIST_ENTRY
*Package
;
2058 CHAR16
*ProblemParam
;
2059 SHELL_STATUS ShellStatus
;
2062 UINT16 EnhancedDump
;
2064 ShellStatus
= SHELL_SUCCESS
;
2065 Status
= EFI_SUCCESS
;
2072 // initialize the shell lib (we must be in non-auto-init...)
2074 Status
= ShellInitialize();
2075 ASSERT_EFI_ERROR(Status
);
2077 Status
= CommandInit();
2078 ASSERT_EFI_ERROR(Status
);
2081 // parse the command line
2083 Status
= ShellCommandLineParse (ParamList
, &Package
, &ProblemParam
, TRUE
);
2084 if (EFI_ERROR(Status
)) {
2085 if (Status
== EFI_VOLUME_CORRUPTED
&& ProblemParam
!= NULL
) {
2086 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_GEN_PROBLEM
), gShellDebug1HiiHandle
, ProblemParam
);
2087 FreePool(ProblemParam
);
2088 ShellStatus
= SHELL_INVALID_PARAMETER
;
2094 if (ShellCommandLineGetCount(Package
) == 2) {
2095 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_GEN_TOO_FEW
), gShellDebug1HiiHandle
);
2096 ShellStatus
= SHELL_INVALID_PARAMETER
;
2100 if (ShellCommandLineGetCount(Package
) > 4) {
2101 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_GEN_TOO_MANY
), gShellDebug1HiiHandle
);
2102 ShellStatus
= SHELL_INVALID_PARAMETER
;
2105 if (ShellCommandLineGetFlag(Package
, L
"-s") && ShellCommandLineGetValue(Package
, L
"-s") == NULL
) {
2106 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_GEN_NO_VALUE
), gShellDebug1HiiHandle
, L
"-s");
2107 ShellStatus
= SHELL_INVALID_PARAMETER
;
2111 // Get all instances of PciRootBridgeIo. Allocate space for 1 EFI_HANDLE and
2112 // call LibLocateHandle(), if EFI_BUFFER_TOO_SMALL is returned, allocate enough
2113 // space for handles and call it again.
2115 HandleBufSize
= sizeof (EFI_HANDLE
);
2116 HandleBuf
= (EFI_HANDLE
*) AllocateZeroPool (HandleBufSize
);
2117 if (HandleBuf
== NULL
) {
2118 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_GEN_OUT_MEM
), gShellDebug1HiiHandle
);
2119 ShellStatus
= SHELL_OUT_OF_RESOURCES
;
2123 Status
= gBS
->LocateHandle (
2125 &gEfiPciRootBridgeIoProtocolGuid
,
2131 if (Status
== EFI_BUFFER_TOO_SMALL
) {
2132 HandleBuf
= ReallocatePool (sizeof (EFI_HANDLE
), HandleBufSize
, HandleBuf
);
2133 if (HandleBuf
== NULL
) {
2134 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_GEN_OUT_MEM
), gShellDebug1HiiHandle
);
2135 ShellStatus
= SHELL_OUT_OF_RESOURCES
;
2139 Status
= gBS
->LocateHandle (
2141 &gEfiPciRootBridgeIoProtocolGuid
,
2148 if (EFI_ERROR (Status
)) {
2149 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_GEN_PCIRBIO_NF
), gShellDebug1HiiHandle
);
2150 ShellStatus
= SHELL_NOT_FOUND
;
2154 HandleCount
= HandleBufSize
/ sizeof (EFI_HANDLE
);
2156 // Argument Count == 1(no other argument): enumerate all pci functions
2158 if (ShellCommandLineGetCount(Package
) == 1) {
2159 gST
->ConOut
->QueryMode (
2161 gST
->ConOut
->Mode
->Mode
,
2168 if ((ScreenSize
& 1) == 1) {
2175 // For each handle, which decides a segment and a bus number range,
2176 // enumerate all devices on it.
2178 for (Index
= 0; Index
< HandleCount
; Index
++) {
2179 Status
= PciGetProtocolAndResource (
2184 if (EFI_ERROR (Status
)) {
2185 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_PCI_HANDLE_CFG_ERR
), gShellDebug1HiiHandle
, Status
);
2186 ShellStatus
= SHELL_NOT_FOUND
;
2190 // No document say it's impossible for a RootBridgeIo protocol handle
2191 // to have more than one address space descriptors, so find out every
2192 // bus range and for each of them do device enumeration.
2195 Status
= PciGetNextBusRange (&Descriptors
, &MinBus
, &MaxBus
, &IsEnd
);
2197 if (EFI_ERROR (Status
)) {
2198 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_PCI_BUS_RANGE_ERR
), gShellDebug1HiiHandle
, Status
);
2199 ShellStatus
= SHELL_NOT_FOUND
;
2207 for (Bus
= MinBus
; Bus
<= MaxBus
; Bus
++) {
2209 // For each devices, enumerate all functions it contains
2211 for (Device
= 0; Device
<= PCI_MAX_DEVICE
; Device
++) {
2213 // For each function, read its configuration space and print summary
2215 for (Func
= 0; Func
<= PCI_MAX_FUNC
; Func
++) {
2216 if (ShellGetExecutionBreakFlag ()) {
2217 ShellStatus
= SHELL_ABORTED
;
2220 Address
= CALC_EFI_PCI_ADDRESS (Bus
, Device
, Func
, 0);
2230 // If VendorId = 0xffff, there does not exist a device at this
2231 // location. For each device, if there is any function on it,
2232 // there must be 1 function at Function 0. So if Func = 0, there
2233 // will be no more functions in the same device, so we can break
2234 // loop to deal with the next device.
2236 if (PciHeader
.VendorId
== 0xffff && Func
== 0) {
2240 if (PciHeader
.VendorId
!= 0xffff) {
2243 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_PCI_TITLE
), gShellDebug1HiiHandle
);
2251 sizeof (PciHeader
) / sizeof (UINT32
),
2256 -1, -1, NULL
, STRING_TOKEN (STR_PCI_LINE_P1
), gShellDebug1HiiHandle
,
2257 IoDev
->SegmentNumber
,
2263 PciPrintClassCode (PciHeader
.ClassCode
, FALSE
);
2265 -1, -1, NULL
, STRING_TOKEN (STR_PCI_LINE_P2
), gShellDebug1HiiHandle
,
2268 PciHeader
.ClassCode
[0]
2272 if (ScreenCount
>= ScreenSize
&& ScreenSize
!= 0) {
2274 // If ScreenSize == 0 we have the console redirected so don't
2280 // If this is not a multi-function device, we can leave the loop
2281 // to deal with the next device.
2283 if (Func
== 0 && ((PciHeader
.HeaderType
& HEADER_TYPE_MULTI_FUNCTION
) == 0x00)) {
2291 // If Descriptor is NULL, Configuration() returns EFI_UNSUPPRORED,
2292 // we assume the bus range is 0~PCI_MAX_BUS. After enumerated all
2293 // devices on all bus, we can leave loop.
2295 if (Descriptors
== NULL
) {
2301 Status
= EFI_SUCCESS
;
2305 ExplainData
= FALSE
;
2310 if (ShellCommandLineGetFlag(Package
, L
"-i")) {
2314 Temp
= ShellCommandLineGetValue(Package
, L
"-s");
2317 // Input converted to hexadecimal number.
2319 if (!EFI_ERROR (ShellConvertStringToUint64 (Temp
, &RetVal
, TRUE
, TRUE
))) {
2320 Segment
= (UINT16
) RetVal
;
2322 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_GEN_PARAM_INV_HEX
), gShellDebug1HiiHandle
);
2323 ShellStatus
= SHELL_INVALID_PARAMETER
;
2329 // The first Argument(except "-i") is assumed to be Bus number, second
2330 // to be Device number, and third to be Func number.
2332 Temp
= ShellCommandLineGetRawValue(Package
, 1);
2335 // Input converted to hexadecimal number.
2337 if (!EFI_ERROR (ShellConvertStringToUint64 (Temp
, &RetVal
, TRUE
, TRUE
))) {
2338 Bus
= (UINT16
) RetVal
;
2340 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_GEN_PARAM_INV_HEX
), gShellDebug1HiiHandle
);
2341 ShellStatus
= SHELL_INVALID_PARAMETER
;
2345 if (Bus
> MAX_BUS_NUMBER
) {
2346 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_GEN_PROBLEM
), gShellDebug1HiiHandle
, Temp
);
2347 ShellStatus
= SHELL_INVALID_PARAMETER
;
2351 Temp
= ShellCommandLineGetRawValue(Package
, 2);
2354 // Input converted to hexadecimal number.
2356 if (!EFI_ERROR (ShellConvertStringToUint64 (Temp
, &RetVal
, TRUE
, TRUE
))) {
2357 Device
= (UINT16
) RetVal
;
2359 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_GEN_PARAM_INV_HEX
), gShellDebug1HiiHandle
);
2360 ShellStatus
= SHELL_INVALID_PARAMETER
;
2364 if (Device
> MAX_DEVICE_NUMBER
){
2365 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_GEN_PROBLEM
), gShellDebug1HiiHandle
, Temp
);
2366 ShellStatus
= SHELL_INVALID_PARAMETER
;
2371 Temp
= ShellCommandLineGetRawValue(Package
, 3);
2374 // Input converted to hexadecimal number.
2376 if (!EFI_ERROR (ShellConvertStringToUint64 (Temp
, &RetVal
, TRUE
, TRUE
))) {
2377 Func
= (UINT16
) RetVal
;
2379 ShellPrintHiiEx (-1, -1, NULL
, STRING_TOKEN (STR_GEN_PARAM_INV_HEX
), gShellDebug1HiiHandle
);
2380 ShellStatus
= SHELL_INVALID_PARAMETER
;
2384 if (Func
> MAX_FUNCTION_NUMBER
){
2385 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_GEN_PROBLEM
), gShellDebug1HiiHandle
, Temp
);
2386 ShellStatus
= SHELL_INVALID_PARAMETER
;
2392 // Find the protocol interface who's in charge of current segment, and its
2393 // bus range covers the current bus
2395 Status
= PciFindProtocolInterface (
2403 if (EFI_ERROR (Status
)) {
2405 -1, -1, NULL
, STRING_TOKEN (STR_PCI_NO_FIND
), gShellDebug1HiiHandle
,
2409 ShellStatus
= SHELL_NOT_FOUND
;
2413 Address
= CALC_EFI_PCI_ADDRESS (Bus
, Device
, Func
, 0);
2414 Status
= IoDev
->Pci
.Read (
2418 sizeof (ConfigSpace
),
2422 if (EFI_ERROR (Status
)) {
2423 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_PCI_NO_CFG
), gShellDebug1HiiHandle
, Status
);
2424 ShellStatus
= SHELL_ACCESS_DENIED
;
2428 mConfigSpace
= &ConfigSpace
;
2433 STRING_TOKEN (STR_PCI_INFO
),
2434 gShellDebug1HiiHandle
,
2446 // Dump standard header of configuration space
2448 SizeOfHeader
= sizeof (ConfigSpace
.Common
) + sizeof (ConfigSpace
.NonCommon
);
2450 DumpHex (2, 0, SizeOfHeader
, &ConfigSpace
);
2451 ShellPrintEx(-1,-1, L
"\r\n");
2454 // Dump device dependent Part of configuration space
2459 sizeof (ConfigSpace
) - SizeOfHeader
,
2464 // If "-i" appears in command line, interpret data in configuration space
2468 if (ShellCommandLineGetFlag(Package
, L
"-_e")) {
2469 EnhancedDump
= 0xFFFF;
2470 Temp
= ShellCommandLineGetValue(Package
, L
"-_e");
2472 EnhancedDump
= (UINT16
) ShellHexStrToUintn (Temp
);
2475 Status
= PciExplainData (&ConfigSpace
, Address
, IoDev
, EnhancedDump
);
2479 if (HandleBuf
!= NULL
) {
2480 FreePool (HandleBuf
);
2482 if (Package
!= NULL
) {
2483 ShellCommandLineFreeVarList (Package
);
2485 mConfigSpace
= NULL
;
2490 This function finds out the protocol which is in charge of the given
2491 segment, and its bus range covers the current bus number. It lookes
2492 each instances of RootBridgeIoProtocol handle, until the one meets the
2495 @param[in] HandleBuf Buffer which holds all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.
2496 @param[in] HandleCount Count of all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.
2497 @param[in] Segment Segment number of device we are dealing with.
2498 @param[in] Bus Bus number of device we are dealing with.
2499 @param[out] IoDev Handle used to access configuration space of PCI device.
2501 @retval EFI_SUCCESS The command completed successfully.
2502 @retval EFI_INVALID_PARAMETER Invalid parameter.
2506 PciFindProtocolInterface (
2507 IN EFI_HANDLE
*HandleBuf
,
2508 IN UINTN HandleCount
,
2511 OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
**IoDev
2516 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
*Descriptors
;
2522 // Go through all handles, until the one meets the criteria is found
2524 for (Index
= 0; Index
< HandleCount
; Index
++) {
2525 Status
= PciGetProtocolAndResource (HandleBuf
[Index
], IoDev
, &Descriptors
);
2526 if (EFI_ERROR (Status
)) {
2530 // When Descriptors == NULL, the Configuration() is not implemented,
2531 // so we only check the Segment number
2533 if (Descriptors
== NULL
&& Segment
== (*IoDev
)->SegmentNumber
) {
2537 if ((*IoDev
)->SegmentNumber
!= Segment
) {
2542 Status
= PciGetNextBusRange (&Descriptors
, &MinBus
, &MaxBus
, &IsEnd
);
2543 if (EFI_ERROR (Status
)) {
2551 if (MinBus
<= Bus
&& MaxBus
>= Bus
) {
2557 return EFI_NOT_FOUND
;
2561 This function gets the protocol interface from the given handle, and
2562 obtains its address space descriptors.
2564 @param[in] Handle The PCI_ROOT_BRIDIGE_IO_PROTOCOL handle.
2565 @param[out] IoDev Handle used to access configuration space of PCI device.
2566 @param[out] Descriptors Points to the address space descriptors.
2568 @retval EFI_SUCCESS The command completed successfully
2571 PciGetProtocolAndResource (
2572 IN EFI_HANDLE Handle
,
2573 OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
**IoDev
,
2574 OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
**Descriptors
2580 // Get inferface from protocol
2582 Status
= gBS
->HandleProtocol (
2584 &gEfiPciRootBridgeIoProtocolGuid
,
2588 if (EFI_ERROR (Status
)) {
2592 // Call Configuration() to get address space descriptors
2594 Status
= (*IoDev
)->Configuration (*IoDev
, (VOID
**)Descriptors
);
2595 if (Status
== EFI_UNSUPPORTED
) {
2596 *Descriptors
= NULL
;
2605 This function get the next bus range of given address space descriptors.
2606 It also moves the pointer backward a node, to get prepared to be called
2609 @param[in, out] Descriptors Points to current position of a serial of address space
2611 @param[out] MinBus The lower range of bus number.
2612 @param[out] MaxBus The upper range of bus number.
2613 @param[out] IsEnd Meet end of the serial of descriptors.
2615 @retval EFI_SUCCESS The command completed successfully.
2618 PciGetNextBusRange (
2619 IN OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
**Descriptors
,
2628 // When *Descriptors is NULL, Configuration() is not implemented, so assume
2629 // range is 0~PCI_MAX_BUS
2631 if ((*Descriptors
) == NULL
) {
2633 *MaxBus
= PCI_MAX_BUS
;
2637 // *Descriptors points to one or more address space descriptors, which
2638 // ends with a end tagged descriptor. Examine each of the descriptors,
2639 // if a bus typed one is found and its bus range covers bus, this handle
2640 // is the handle we are looking for.
2643 while ((*Descriptors
)->Desc
!= ACPI_END_TAG_DESCRIPTOR
) {
2644 if ((*Descriptors
)->ResType
== ACPI_ADDRESS_SPACE_TYPE_BUS
) {
2645 *MinBus
= (UINT16
) (*Descriptors
)->AddrRangeMin
;
2646 *MaxBus
= (UINT16
) (*Descriptors
)->AddrRangeMax
;
2648 return (EFI_SUCCESS
);
2654 if ((*Descriptors
)->Desc
== ACPI_END_TAG_DESCRIPTOR
) {
2662 Explain the data in PCI configuration space. The part which is common for
2663 PCI device and bridge is interpreted in this function. It calls other
2664 functions to interpret data unique for device or bridge.
2666 @param[in] ConfigSpace Data in PCI configuration space.
2667 @param[in] Address Address used to access configuration space of this PCI device.
2668 @param[in] IoDev Handle used to access configuration space of PCI device.
2669 @param[in] EnhancedDump The print format for the dump data.
2671 @retval EFI_SUCCESS The command completed successfully.
2675 IN PCI_CONFIG_SPACE
*ConfigSpace
,
2677 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
,
2678 IN CONST UINT16 EnhancedDump
2681 PCI_COMMON_HEADER
*Common
;
2682 PCI_HEADER_TYPE HeaderType
;
2686 Common
= &(ConfigSpace
->Common
);
2688 ShellPrintEx (-1, -1, L
"\r\n");
2691 // Print Vendor Id and Device Id
2693 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_PCI_LINE_VID_DID
), gShellDebug1HiiHandle
,
2694 INDEX_OF (&(Common
->VendorId
)),
2696 INDEX_OF (&(Common
->DeviceId
)),
2701 // Print register Command
2703 PciExplainCommand (&(Common
->Command
));
2706 // Print register Status
2708 PciExplainStatus (&(Common
->Status
), TRUE
, PciUndefined
);
2711 // Print register Revision ID
2713 ShellPrintEx(-1, -1, L
"\r\n");
2714 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_PCI_LINE_RID
), gShellDebug1HiiHandle
,
2715 INDEX_OF (&(Common
->RevisionId
)),
2720 // Print register BIST
2722 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_PCI_LINE_BIST
), gShellDebug1HiiHandle
, INDEX_OF (&(Common
->Bist
)));
2723 if ((Common
->Bist
& PCI_BIT_7
) != 0) {
2724 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_PCI_LINE_CAP
), gShellDebug1HiiHandle
, 0x0f & Common
->Bist
);
2726 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_PCI_LINE_CAP_NO
), gShellDebug1HiiHandle
);
2729 // Print register Cache Line Size
2731 ShellPrintHiiEx(-1, -1, NULL
,
2732 STRING_TOKEN (STR_PCI2_CACHE_LINE_SIZE
),
2733 gShellDebug1HiiHandle
,
2734 INDEX_OF (&(Common
->CacheLineSize
)),
2735 Common
->CacheLineSize
2739 // Print register Latency Timer
2741 ShellPrintHiiEx(-1, -1, NULL
,
2742 STRING_TOKEN (STR_PCI2_LATENCY_TIMER
),
2743 gShellDebug1HiiHandle
,
2744 INDEX_OF (&(Common
->PrimaryLatencyTimer
)),
2745 Common
->PrimaryLatencyTimer
2749 // Print register Header Type
2751 ShellPrintHiiEx(-1, -1, NULL
,
2752 STRING_TOKEN (STR_PCI2_HEADER_TYPE
),
2753 gShellDebug1HiiHandle
,
2754 INDEX_OF (&(Common
->HeaderType
)),
2758 if ((Common
->HeaderType
& PCI_BIT_7
) != 0) {
2759 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_MULTI_FUNCTION
), gShellDebug1HiiHandle
);
2762 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_SINGLE_FUNCTION
), gShellDebug1HiiHandle
);
2765 HeaderType
= (PCI_HEADER_TYPE
)(UINT8
) (Common
->HeaderType
& 0x7f);
2766 switch (HeaderType
) {
2768 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_PCI_DEVICE
), gShellDebug1HiiHandle
);
2772 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_P2P_BRIDGE
), gShellDebug1HiiHandle
);
2775 case PciCardBusBridge
:
2776 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_CARDBUS_BRIDGE
), gShellDebug1HiiHandle
);
2780 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_RESERVED
), gShellDebug1HiiHandle
);
2781 HeaderType
= PciUndefined
;
2785 // Print register Class Code
2787 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_CLASS
), gShellDebug1HiiHandle
);
2788 PciPrintClassCode ((UINT8
*) Common
->ClassCode
, TRUE
);
2789 ShellPrintEx (-1, -1, L
"\r\n");
2791 if (ShellGetExecutionBreakFlag()) {
2796 // Interpret remaining part of PCI configuration header depending on
2800 Status
= EFI_SUCCESS
;
2801 switch (HeaderType
) {
2803 Status
= PciExplainDeviceData (
2804 &(ConfigSpace
->NonCommon
.Device
),
2808 CapPtr
= ConfigSpace
->NonCommon
.Device
.CapabilitiesPtr
;
2812 Status
= PciExplainBridgeData (
2813 &(ConfigSpace
->NonCommon
.Bridge
),
2817 CapPtr
= ConfigSpace
->NonCommon
.Bridge
.CapabilitiesPtr
;
2820 case PciCardBusBridge
:
2821 Status
= PciExplainCardBusData (
2822 &(ConfigSpace
->NonCommon
.CardBus
),
2826 CapPtr
= ConfigSpace
->NonCommon
.CardBus
.CapabilitiesPtr
;
2833 // If Status bit4 is 1, dump or explain capability structure
2835 if ((Common
->Status
) & EFI_PCI_STATUS_CAPABILITY
) {
2836 PciExplainCapabilityStruct (IoDev
, Address
, CapPtr
, EnhancedDump
);
2843 Explain the device specific part of data in PCI configuration space.
2845 @param[in] Device Data in PCI configuration space.
2846 @param[in] Address Address used to access configuration space of this PCI device.
2847 @param[in] IoDev Handle used to access configuration space of PCI device.
2849 @retval EFI_SUCCESS The command completed successfully.
2852 PciExplainDeviceData (
2853 IN PCI_DEVICE_HEADER
*Device
,
2855 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
2864 // Print Base Address Registers(Bar). When Bar = 0, this Bar does not
2865 // exist. If these no Bar for this function, print "none", otherwise
2866 // list detail information about this Bar.
2868 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_BASE_ADDR
), gShellDebug1HiiHandle
, INDEX_OF (Device
->Bar
));
2871 BarCount
= sizeof (Device
->Bar
) / sizeof (Device
->Bar
[0]);
2872 for (Index
= 0; Index
< BarCount
; Index
++) {
2873 if (Device
->Bar
[Index
] == 0) {
2879 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_START_TYPE
), gShellDebug1HiiHandle
);
2880 ShellPrintEx (-1, -1, L
" --------------------------------------------------------------------------");
2883 Status
= PciExplainBar (
2884 &(Device
->Bar
[Index
]),
2885 &(mConfigSpace
->Common
.Command
),
2891 if (EFI_ERROR (Status
)) {
2897 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_NONE
), gShellDebug1HiiHandle
);
2900 ShellPrintEx (-1, -1, L
"\r\n --------------------------------------------------------------------------");
2904 // Print register Expansion ROM Base Address
2906 if ((Device
->ROMBar
& PCI_BIT_0
) == 0) {
2907 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_EXPANSION_ROM_DISABLED
), gShellDebug1HiiHandle
, INDEX_OF (&(Device
->ROMBar
)));
2910 ShellPrintHiiEx(-1, -1, NULL
,
2911 STRING_TOKEN (STR_PCI2_EXPANSION_ROM_BASE
),
2912 gShellDebug1HiiHandle
,
2913 INDEX_OF (&(Device
->ROMBar
)),
2918 // Print register Cardbus CIS ptr
2920 ShellPrintHiiEx(-1, -1, NULL
,
2921 STRING_TOKEN (STR_PCI2_CARDBUS_CIS
),
2922 gShellDebug1HiiHandle
,
2923 INDEX_OF (&(Device
->CardBusCISPtr
)),
2924 Device
->CardBusCISPtr
2928 // Print register Sub-vendor ID and subsystem ID
2930 ShellPrintHiiEx(-1, -1, NULL
,
2931 STRING_TOKEN (STR_PCI2_SUB_VENDOR_ID
),
2932 gShellDebug1HiiHandle
,
2933 INDEX_OF (&(Device
->SubVendorId
)),
2937 ShellPrintHiiEx(-1, -1, NULL
,
2938 STRING_TOKEN (STR_PCI2_SUBSYSTEM_ID
),
2939 gShellDebug1HiiHandle
,
2940 INDEX_OF (&(Device
->SubSystemId
)),
2945 // Print register Capabilities Ptr
2947 ShellPrintHiiEx(-1, -1, NULL
,
2948 STRING_TOKEN (STR_PCI2_CAPABILITIES_PTR
),
2949 gShellDebug1HiiHandle
,
2950 INDEX_OF (&(Device
->CapabilitiesPtr
)),
2951 Device
->CapabilitiesPtr
2955 // Print register Interrupt Line and interrupt pin
2957 ShellPrintHiiEx(-1, -1, NULL
,
2958 STRING_TOKEN (STR_PCI2_INTERRUPT_LINE
),
2959 gShellDebug1HiiHandle
,
2960 INDEX_OF (&(Device
->InterruptLine
)),
2961 Device
->InterruptLine
2964 ShellPrintHiiEx(-1, -1, NULL
,
2965 STRING_TOKEN (STR_PCI2_INTERRUPT_PIN
),
2966 gShellDebug1HiiHandle
,
2967 INDEX_OF (&(Device
->InterruptPin
)),
2968 Device
->InterruptPin
2972 // Print register Min_Gnt and Max_Lat
2974 ShellPrintHiiEx(-1, -1, NULL
,
2975 STRING_TOKEN (STR_PCI2_MIN_GNT
),
2976 gShellDebug1HiiHandle
,
2977 INDEX_OF (&(Device
->MinGnt
)),
2981 ShellPrintHiiEx(-1, -1, NULL
,
2982 STRING_TOKEN (STR_PCI2_MAX_LAT
),
2983 gShellDebug1HiiHandle
,
2984 INDEX_OF (&(Device
->MaxLat
)),
2992 Explain the bridge specific part of data in PCI configuration space.
2994 @param[in] Bridge Bridge specific data region in PCI configuration space.
2995 @param[in] Address Address used to access configuration space of this PCI device.
2996 @param[in] IoDev Handle used to access configuration space of PCI device.
2998 @retval EFI_SUCCESS The command completed successfully.
3001 PciExplainBridgeData (
3002 IN PCI_BRIDGE_HEADER
*Bridge
,
3004 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
3014 // Print Base Address Registers. When Bar = 0, this Bar does not
3015 // exist. If these no Bar for this function, print "none", otherwise
3016 // list detail information about this Bar.
3018 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_BASE_ADDRESS
), gShellDebug1HiiHandle
, INDEX_OF (&(Bridge
->Bar
)));
3021 BarCount
= sizeof (Bridge
->Bar
) / sizeof (Bridge
->Bar
[0]);
3023 for (Index
= 0; Index
< BarCount
; Index
++) {
3024 if (Bridge
->Bar
[Index
] == 0) {
3030 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_START_TYPE_2
), gShellDebug1HiiHandle
);
3031 ShellPrintEx (-1, -1, L
" --------------------------------------------------------------------------");
3034 Status
= PciExplainBar (
3035 &(Bridge
->Bar
[Index
]),
3036 &(mConfigSpace
->Common
.Command
),
3042 if (EFI_ERROR (Status
)) {
3048 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_NONE
), gShellDebug1HiiHandle
);
3050 ShellPrintEx (-1, -1, L
"\r\n --------------------------------------------------------------------------");
3054 // Expansion register ROM Base Address
3056 if ((Bridge
->ROMBar
& PCI_BIT_0
) == 0) {
3057 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_NO_EXPANSION_ROM
), gShellDebug1HiiHandle
, INDEX_OF (&(Bridge
->ROMBar
)));
3060 ShellPrintHiiEx(-1, -1, NULL
,
3061 STRING_TOKEN (STR_PCI2_EXPANSION_ROM_BASE_2
),
3062 gShellDebug1HiiHandle
,
3063 INDEX_OF (&(Bridge
->ROMBar
)),
3068 // Print Bus Numbers(Primary, Secondary, and Subordinate
3070 ShellPrintHiiEx(-1, -1, NULL
,
3071 STRING_TOKEN (STR_PCI2_BUS_NUMBERS
),
3072 gShellDebug1HiiHandle
,
3073 INDEX_OF (&(Bridge
->PrimaryBus
)),
3074 INDEX_OF (&(Bridge
->SecondaryBus
)),
3075 INDEX_OF (&(Bridge
->SubordinateBus
))
3078 ShellPrintEx (-1, -1, L
" ------------------------------------------------------\r\n");
3080 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_BRIDGE
), gShellDebug1HiiHandle
, Bridge
->PrimaryBus
);
3081 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_BRIDGE
), gShellDebug1HiiHandle
, Bridge
->SecondaryBus
);
3082 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_BRIDGE
), gShellDebug1HiiHandle
, Bridge
->SubordinateBus
);
3085 // Print register Secondary Latency Timer
3087 ShellPrintHiiEx(-1, -1, NULL
,
3088 STRING_TOKEN (STR_PCI2_SECONDARY_TIMER
),
3089 gShellDebug1HiiHandle
,
3090 INDEX_OF (&(Bridge
->SecondaryLatencyTimer
)),
3091 Bridge
->SecondaryLatencyTimer
3095 // Print register Secondary Status
3097 PciExplainStatus (&(Bridge
->SecondaryStatus
), FALSE
, PciP2pBridge
);
3100 // Print I/O and memory ranges this bridge forwards. There are 3 resource
3101 // types: I/O, memory, and pre-fetchable memory. For each resource type,
3102 // base and limit address are listed.
3104 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_RESOURCE_TYPE
), gShellDebug1HiiHandle
);
3105 ShellPrintEx (-1, -1, L
"----------------------------------------------------------------------\r\n");
3110 IoAddress32
= (Bridge
->IoBaseUpper
<< 16 | Bridge
->IoBase
<< 8);
3111 IoAddress32
&= 0xfffff000;
3112 ShellPrintHiiEx(-1, -1, NULL
,
3113 STRING_TOKEN (STR_PCI2_TWO_VARS
),
3114 gShellDebug1HiiHandle
,
3115 INDEX_OF (&(Bridge
->IoBase
)),
3119 IoAddress32
= (Bridge
->IoLimitUpper
<< 16 | Bridge
->IoLimit
<< 8);
3120 IoAddress32
|= 0x00000fff;
3121 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_ONE_VAR
), gShellDebug1HiiHandle
, IoAddress32
);
3124 // Memory Base & Limit
3126 ShellPrintHiiEx(-1, -1, NULL
,
3127 STRING_TOKEN (STR_PCI2_MEMORY
),
3128 gShellDebug1HiiHandle
,
3129 INDEX_OF (&(Bridge
->MemoryBase
)),
3130 (Bridge
->MemoryBase
<< 16) & 0xfff00000
3133 ShellPrintHiiEx(-1, -1, NULL
,
3134 STRING_TOKEN (STR_PCI2_ONE_VAR
),
3135 gShellDebug1HiiHandle
,
3136 (Bridge
->MemoryLimit
<< 16) | 0x000fffff
3140 // Pre-fetch-able Memory Base & Limit
3142 ShellPrintHiiEx(-1, -1, NULL
,
3143 STRING_TOKEN (STR_PCI2_PREFETCHABLE
),
3144 gShellDebug1HiiHandle
,
3145 INDEX_OF (&(Bridge
->PrefetchableMemBase
)),
3146 Bridge
->PrefetchableBaseUpper
,
3147 (Bridge
->PrefetchableMemBase
<< 16) & 0xfff00000
3150 ShellPrintHiiEx(-1, -1, NULL
,
3151 STRING_TOKEN (STR_PCI2_TWO_VARS_2
),
3152 gShellDebug1HiiHandle
,
3153 Bridge
->PrefetchableLimitUpper
,
3154 (Bridge
->PrefetchableMemLimit
<< 16) | 0x000fffff
3158 // Print register Capabilities Pointer
3160 ShellPrintHiiEx(-1, -1, NULL
,
3161 STRING_TOKEN (STR_PCI2_CAPABILITIES_PTR_2
),
3162 gShellDebug1HiiHandle
,
3163 INDEX_OF (&(Bridge
->CapabilitiesPtr
)),
3164 Bridge
->CapabilitiesPtr
3168 // Print register Bridge Control
3170 PciExplainBridgeControl (&(Bridge
->BridgeControl
), PciP2pBridge
);
3173 // Print register Interrupt Line & PIN
3175 ShellPrintHiiEx(-1, -1, NULL
,
3176 STRING_TOKEN (STR_PCI2_INTERRUPT_LINE_2
),
3177 gShellDebug1HiiHandle
,
3178 INDEX_OF (&(Bridge
->InterruptLine
)),
3179 Bridge
->InterruptLine
3182 ShellPrintHiiEx(-1, -1, NULL
,
3183 STRING_TOKEN (STR_PCI2_INTERRUPT_PIN
),
3184 gShellDebug1HiiHandle
,
3185 INDEX_OF (&(Bridge
->InterruptPin
)),
3186 Bridge
->InterruptPin
3193 Explain the Base Address Register(Bar) in PCI configuration space.
3195 @param[in] Bar Points to the Base Address Register intended to interpret.
3196 @param[in] Command Points to the register Command.
3197 @param[in] Address Address used to access configuration space of this PCI device.
3198 @param[in] IoDev Handle used to access configuration space of PCI device.
3199 @param[in, out] Index The Index.
3201 @retval EFI_SUCCESS The command completed successfully.
3208 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
,
3229 // According the bar type, list detail about this bar, for example: 32 or
3230 // 64 bits; pre-fetchable or not.
3232 if ((*Bar
& PCI_BIT_0
) == 0) {
3234 // This bar is of memory type
3238 if ((*Bar
& PCI_BIT_1
) == 0 && (*Bar
& PCI_BIT_2
) == 0) {
3239 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_BAR
), gShellDebug1HiiHandle
, *Bar
& 0xfffffff0);
3240 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_MEM
), gShellDebug1HiiHandle
);
3241 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_32_BITS
), gShellDebug1HiiHandle
);
3243 } else if ((*Bar
& PCI_BIT_1
) == 0 && (*Bar
& PCI_BIT_2
) != 0) {
3245 CopyMem (&Bar64
, Bar
, sizeof (UINT64
));
3246 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_ONE_VAR_2
), gShellDebug1HiiHandle
, (UINT32
) RShiftU64 ((Bar64
& 0xfffffffffffffff0ULL
), 32));
3247 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_ONE_VAR_3
), gShellDebug1HiiHandle
, (UINT32
) (Bar64
& 0xfffffffffffffff0ULL
));
3248 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_MEM
), gShellDebug1HiiHandle
);
3249 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_64_BITS
), gShellDebug1HiiHandle
);
3257 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_BAR
), gShellDebug1HiiHandle
, *Bar
& 0xfffffff0);
3258 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_MEM_2
), gShellDebug1HiiHandle
);
3261 if ((*Bar
& PCI_BIT_3
) == 0) {
3262 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_NO
), gShellDebug1HiiHandle
);
3265 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_YES
), gShellDebug1HiiHandle
);
3270 // This bar is of io type
3273 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_ONE_VAR_4
), gShellDebug1HiiHandle
, *Bar
& 0xfffffffc);
3274 ShellPrintEx (-1, -1, L
"I/O ");
3278 // Get BAR length(or the amount of resource this bar demands for). To get
3279 // Bar length, first we should temporarily disable I/O and memory access
3280 // of this function(by set bits in the register Command), then write all
3281 // "1"s to this bar. The bar value read back is the amount of resource
3282 // this bar demands for.
3285 // Disable io & mem access
3287 OldCommand
= *Command
;
3288 NewCommand
= (UINT16
) (OldCommand
& 0xfffc);
3289 RegAddress
= Address
| INDEX_OF (Command
);
3290 IoDev
->Pci
.Write (IoDev
, EfiPciWidthUint16
, RegAddress
, 1, &NewCommand
);
3292 RegAddress
= Address
| INDEX_OF (Bar
);
3295 // Read after write the BAR to get the size
3299 NewBar32
= 0xffffffff;
3301 IoDev
->Pci
.Write (IoDev
, EfiPciWidthUint32
, RegAddress
, 1, &NewBar32
);
3302 IoDev
->Pci
.Read (IoDev
, EfiPciWidthUint32
, RegAddress
, 1, &NewBar32
);
3303 IoDev
->Pci
.Write (IoDev
, EfiPciWidthUint32
, RegAddress
, 1, &OldBar32
);
3306 NewBar32
= NewBar32
& 0xfffffff0;
3307 NewBar32
= (~NewBar32
) + 1;
3310 NewBar32
= NewBar32
& 0xfffffffc;
3311 NewBar32
= (~NewBar32
) + 1;
3312 NewBar32
= NewBar32
& 0x0000ffff;
3317 CopyMem (&OldBar64
, Bar
, sizeof (UINT64
));
3318 NewBar64
= 0xffffffffffffffffULL
;
3320 IoDev
->Pci
.Write (IoDev
, EfiPciWidthUint32
, RegAddress
, 2, &NewBar64
);
3321 IoDev
->Pci
.Read (IoDev
, EfiPciWidthUint32
, RegAddress
, 2, &NewBar64
);
3322 IoDev
->Pci
.Write (IoDev
, EfiPciWidthUint32
, RegAddress
, 2, &OldBar64
);
3325 NewBar64
= NewBar64
& 0xfffffffffffffff0ULL
;
3326 NewBar64
= (~NewBar64
) + 1;
3329 NewBar64
= NewBar64
& 0xfffffffffffffffcULL
;
3330 NewBar64
= (~NewBar64
) + 1;
3331 NewBar64
= NewBar64
& 0x000000000000ffff;
3335 // Enable io & mem access
3337 RegAddress
= Address
| INDEX_OF (Command
);
3338 IoDev
->Pci
.Write (IoDev
, EfiPciWidthUint16
, RegAddress
, 1, &OldCommand
);
3342 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_NEWBAR_32
), gShellDebug1HiiHandle
, NewBar32
);
3343 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_NEWBAR_32_2
), gShellDebug1HiiHandle
, NewBar32
+ (*Bar
& 0xfffffff0) - 1);
3346 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_RSHIFT
), gShellDebug1HiiHandle
, (UINT32
) RShiftU64 (NewBar64
, 32));
3347 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_RSHIFT
), gShellDebug1HiiHandle
, (UINT32
) NewBar64
);
3348 ShellPrintEx (-1, -1, L
" ");
3349 ShellPrintHiiEx(-1, -1, NULL
,
3350 STRING_TOKEN (STR_PCI2_RSHIFT
),
3351 gShellDebug1HiiHandle
,
3352 (UINT32
) RShiftU64 ((NewBar64
+ (Bar64
& 0xfffffffffffffff0ULL
) - 1), 32)
3354 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_RSHIFT
), gShellDebug1HiiHandle
, (UINT32
) (NewBar64
+ (Bar64
& 0xfffffffffffffff0ULL
) - 1));
3358 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_NEWBAR_32_3
), gShellDebug1HiiHandle
, NewBar32
);
3359 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_NEWBAR_32_4
), gShellDebug1HiiHandle
, NewBar32
+ (*Bar
& 0xfffffffc) - 1);
3366 Explain the cardbus specific part of data in PCI configuration space.
3368 @param[in] CardBus CardBus specific region of PCI configuration space.
3369 @param[in] Address Address used to access configuration space of this PCI device.
3370 @param[in] IoDev Handle used to access configuration space of PCI device.
3372 @retval EFI_SUCCESS The command completed successfully.
3375 PciExplainCardBusData (
3376 IN PCI_CARDBUS_HEADER
*CardBus
,
3378 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
3382 PCI_CARDBUS_DATA
*CardBusData
;
3384 ShellPrintHiiEx(-1, -1, NULL
,
3385 STRING_TOKEN (STR_PCI2_CARDBUS_SOCKET
),
3386 gShellDebug1HiiHandle
,
3387 INDEX_OF (&(CardBus
->CardBusSocketReg
)),
3388 CardBus
->CardBusSocketReg
3392 // Print Secondary Status
3394 PciExplainStatus (&(CardBus
->SecondaryStatus
), FALSE
, PciCardBusBridge
);
3397 // Print Bus Numbers(Primary bus number, CardBus bus number, and
3398 // Subordinate bus number
3400 ShellPrintHiiEx(-1, -1, NULL
,
3401 STRING_TOKEN (STR_PCI2_BUS_NUMBERS_2
),
3402 gShellDebug1HiiHandle
,
3403 INDEX_OF (&(CardBus
->PciBusNumber
)),
3404 INDEX_OF (&(CardBus
->CardBusBusNumber
)),
3405 INDEX_OF (&(CardBus
->SubordinateBusNumber
))
3408 ShellPrintEx (-1, -1, L
" ------------------------------------------------------\r\n");
3410 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_CARDBUS
), gShellDebug1HiiHandle
, CardBus
->PciBusNumber
);
3411 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_CARDBUS_2
), gShellDebug1HiiHandle
, CardBus
->CardBusBusNumber
);
3412 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_CARDBUS_3
), gShellDebug1HiiHandle
, CardBus
->SubordinateBusNumber
);
3415 // Print CardBus Latency Timer
3417 ShellPrintHiiEx(-1, -1, NULL
,
3418 STRING_TOKEN (STR_PCI2_CARDBUS_LATENCY
),
3419 gShellDebug1HiiHandle
,
3420 INDEX_OF (&(CardBus
->CardBusLatencyTimer
)),
3421 CardBus
->CardBusLatencyTimer
3425 // Print Memory/Io ranges this cardbus bridge forwards
3427 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_RESOURCE_TYPE_2
), gShellDebug1HiiHandle
);
3428 ShellPrintEx (-1, -1, L
"----------------------------------------------------------------------\r\n");
3430 ShellPrintHiiEx(-1, -1, NULL
,
3431 STRING_TOKEN (STR_PCI2_MEM_3
),
3432 gShellDebug1HiiHandle
,
3433 INDEX_OF (&(CardBus
->MemoryBase0
)),
3434 CardBus
->BridgeControl
& PCI_BIT_8
? L
" Prefetchable" : L
"Non-Prefetchable",
3435 CardBus
->MemoryBase0
& 0xfffff000,
3436 CardBus
->MemoryLimit0
| 0x00000fff
3439 ShellPrintHiiEx(-1, -1, NULL
,
3440 STRING_TOKEN (STR_PCI2_MEM_3
),
3441 gShellDebug1HiiHandle
,
3442 INDEX_OF (&(CardBus
->MemoryBase1
)),
3443 CardBus
->BridgeControl
& PCI_BIT_9
? L
" Prefetchable" : L
"Non-Prefetchable",
3444 CardBus
->MemoryBase1
& 0xfffff000,
3445 CardBus
->MemoryLimit1
| 0x00000fff
3448 Io32Bit
= (BOOLEAN
) (CardBus
->IoBase0
& PCI_BIT_0
);
3449 ShellPrintHiiEx(-1, -1, NULL
,
3450 STRING_TOKEN (STR_PCI2_IO_2
),
3451 gShellDebug1HiiHandle
,
3452 INDEX_OF (&(CardBus
->IoBase0
)),
3453 Io32Bit
? L
" 32 bit" : L
" 16 bit",
3454 CardBus
->IoBase0
& (Io32Bit
? 0xfffffffc : 0x0000fffc),
3455 (CardBus
->IoLimit0
& (Io32Bit
? 0xffffffff : 0x0000ffff)) | 0x00000003
3458 Io32Bit
= (BOOLEAN
) (CardBus
->IoBase1
& PCI_BIT_0
);
3459 ShellPrintHiiEx(-1, -1, NULL
,
3460 STRING_TOKEN (STR_PCI2_IO_2
),
3461 gShellDebug1HiiHandle
,
3462 INDEX_OF (&(CardBus
->IoBase1
)),
3463 Io32Bit
? L
" 32 bit" : L
" 16 bit",
3464 CardBus
->IoBase1
& (Io32Bit
? 0xfffffffc : 0x0000fffc),
3465 (CardBus
->IoLimit1
& (Io32Bit
? 0xffffffff : 0x0000ffff)) | 0x00000003
3469 // Print register Interrupt Line & PIN
3471 ShellPrintHiiEx(-1, -1, NULL
,
3472 STRING_TOKEN (STR_PCI2_INTERRUPT_LINE_3
),
3473 gShellDebug1HiiHandle
,
3474 INDEX_OF (&(CardBus
->InterruptLine
)),
3475 CardBus
->InterruptLine
,
3476 INDEX_OF (&(CardBus
->InterruptPin
)),
3477 CardBus
->InterruptPin
3481 // Print register Bridge Control
3483 PciExplainBridgeControl (&(CardBus
->BridgeControl
), PciCardBusBridge
);
3486 // Print some registers in data region of PCI configuration space for cardbus
3487 // bridge. Fields include: Sub VendorId, Subsystem ID, and Legacy Mode Base
3490 CardBusData
= (PCI_CARDBUS_DATA
*) ((UINT8
*) CardBus
+ sizeof (PCI_CARDBUS_HEADER
));
3492 ShellPrintHiiEx(-1, -1, NULL
,
3493 STRING_TOKEN (STR_PCI2_SUB_VENDOR_ID_2
),
3494 gShellDebug1HiiHandle
,
3495 INDEX_OF (&(CardBusData
->SubVendorId
)),
3496 CardBusData
->SubVendorId
,
3497 INDEX_OF (&(CardBusData
->SubSystemId
)),
3498 CardBusData
->SubSystemId
3501 ShellPrintHiiEx(-1, -1, NULL
,
3502 STRING_TOKEN (STR_PCI2_OPTIONAL
),
3503 gShellDebug1HiiHandle
,
3504 INDEX_OF (&(CardBusData
->LegacyBase
)),
3505 CardBusData
->LegacyBase
3512 Explain each meaningful bit of register Status. The definition of Status is
3513 slightly different depending on the PCI header type.
3515 @param[in] Status Points to the content of register Status.
3516 @param[in] MainStatus Indicates if this register is main status(not secondary
3518 @param[in] HeaderType Header type of this PCI device.
3520 @retval EFI_SUCCESS The command completed successfully.
3525 IN BOOLEAN MainStatus
,
3526 IN PCI_HEADER_TYPE HeaderType
3530 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_STATUS
), gShellDebug1HiiHandle
, INDEX_OF (Status
), *Status
);
3533 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_SECONDARY_STATUS
), gShellDebug1HiiHandle
, INDEX_OF (Status
), *Status
);
3536 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_NEW_CAPABILITIES
), gShellDebug1HiiHandle
, (*Status
& PCI_BIT_4
) != 0);
3539 // Bit 5 is meaningless for CardBus Bridge
3541 if (HeaderType
== PciCardBusBridge
) {
3542 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_66_CAPABLE
), gShellDebug1HiiHandle
, (*Status
& PCI_BIT_5
) != 0);
3545 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_66_CAPABLE_2
), gShellDebug1HiiHandle
, (*Status
& PCI_BIT_5
) != 0);
3548 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_FAST_BACK
), gShellDebug1HiiHandle
, (*Status
& PCI_BIT_7
) != 0);
3550 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_MASTER_DATA
), gShellDebug1HiiHandle
, (*Status
& PCI_BIT_8
) != 0);
3552 // Bit 9 and bit 10 together decides the DEVSEL timing
3554 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_DEVSEL_TIMING
), gShellDebug1HiiHandle
);
3555 if ((*Status
& PCI_BIT_9
) == 0 && (*Status
& PCI_BIT_10
) == 0) {
3556 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_FAST
), gShellDebug1HiiHandle
);
3558 } else if ((*Status
& PCI_BIT_9
) != 0 && (*Status
& PCI_BIT_10
) == 0) {
3559 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_MEDIUM
), gShellDebug1HiiHandle
);
3561 } else if ((*Status
& PCI_BIT_9
) == 0 && (*Status
& PCI_BIT_10
) != 0) {
3562 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_SLOW
), gShellDebug1HiiHandle
);
3565 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_RESERVED_2
), gShellDebug1HiiHandle
);
3568 ShellPrintHiiEx(-1, -1, NULL
,
3569 STRING_TOKEN (STR_PCI2_SIGNALED_TARGET
),
3570 gShellDebug1HiiHandle
,
3571 (*Status
& PCI_BIT_11
) != 0
3574 ShellPrintHiiEx(-1, -1, NULL
,
3575 STRING_TOKEN (STR_PCI2_RECEIVED_TARGET
),
3576 gShellDebug1HiiHandle
,
3577 (*Status
& PCI_BIT_12
) != 0
3580 ShellPrintHiiEx(-1, -1, NULL
,
3581 STRING_TOKEN (STR_PCI2_RECEIVED_MASTER
),
3582 gShellDebug1HiiHandle
,
3583 (*Status
& PCI_BIT_13
) != 0
3587 ShellPrintHiiEx(-1, -1, NULL
,
3588 STRING_TOKEN (STR_PCI2_SIGNALED_ERROR
),
3589 gShellDebug1HiiHandle
,
3590 (*Status
& PCI_BIT_14
) != 0
3594 ShellPrintHiiEx(-1, -1, NULL
,
3595 STRING_TOKEN (STR_PCI2_RECEIVED_ERROR
),
3596 gShellDebug1HiiHandle
,
3597 (*Status
& PCI_BIT_14
) != 0
3601 ShellPrintHiiEx(-1, -1, NULL
,
3602 STRING_TOKEN (STR_PCI2_DETECTED_ERROR
),
3603 gShellDebug1HiiHandle
,
3604 (*Status
& PCI_BIT_15
) != 0
3611 Explain each meaningful bit of register Command.
3613 @param[in] Command Points to the content of register Command.
3615 @retval EFI_SUCCESS The command completed successfully.
3623 // Print the binary value of register Command
3625 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_COMMAND
), gShellDebug1HiiHandle
, INDEX_OF (Command
), *Command
);
3628 // Explain register Command bit by bit
3630 ShellPrintHiiEx(-1, -1, NULL
,
3631 STRING_TOKEN (STR_PCI2_SPACE_ACCESS_DENIED
),
3632 gShellDebug1HiiHandle
,
3633 (*Command
& PCI_BIT_0
) != 0
3636 ShellPrintHiiEx(-1, -1, NULL
,
3637 STRING_TOKEN (STR_PCI2_MEMORY_SPACE
),
3638 gShellDebug1HiiHandle
,
3639 (*Command
& PCI_BIT_1
) != 0
3642 ShellPrintHiiEx(-1, -1, NULL
,
3643 STRING_TOKEN (STR_PCI2_BEHAVE_BUS_MASTER
),
3644 gShellDebug1HiiHandle
,
3645 (*Command
& PCI_BIT_2
) != 0
3648 ShellPrintHiiEx(-1, -1, NULL
,
3649 STRING_TOKEN (STR_PCI2_MONITOR_SPECIAL_CYCLE
),
3650 gShellDebug1HiiHandle
,
3651 (*Command
& PCI_BIT_3
) != 0
3654 ShellPrintHiiEx(-1, -1, NULL
,
3655 STRING_TOKEN (STR_PCI2_MEM_WRITE_INVALIDATE
),
3656 gShellDebug1HiiHandle
,
3657 (*Command
& PCI_BIT_4
) != 0
3660 ShellPrintHiiEx(-1, -1, NULL
,
3661 STRING_TOKEN (STR_PCI2_PALETTE_SNOOPING
),
3662 gShellDebug1HiiHandle
,
3663 (*Command
& PCI_BIT_5
) != 0
3666 ShellPrintHiiEx(-1, -1, NULL
,
3667 STRING_TOKEN (STR_PCI2_ASSERT_PERR
),
3668 gShellDebug1HiiHandle
,
3669 (*Command
& PCI_BIT_6
) != 0
3672 ShellPrintHiiEx(-1, -1, NULL
,
3673 STRING_TOKEN (STR_PCI2_DO_ADDR_STEPPING
),
3674 gShellDebug1HiiHandle
,
3675 (*Command
& PCI_BIT_7
) != 0
3678 ShellPrintHiiEx(-1, -1, NULL
,
3679 STRING_TOKEN (STR_PCI2_SERR_DRIVER
),
3680 gShellDebug1HiiHandle
,
3681 (*Command
& PCI_BIT_8
) != 0
3684 ShellPrintHiiEx(-1, -1, NULL
,
3685 STRING_TOKEN (STR_PCI2_FAST_BACK_2
),
3686 gShellDebug1HiiHandle
,
3687 (*Command
& PCI_BIT_9
) != 0
3694 Explain each meaningful bit of register Bridge Control.
3696 @param[in] BridgeControl Points to the content of register Bridge Control.
3697 @param[in] HeaderType The headertype.
3699 @retval EFI_SUCCESS The command completed successfully.
3702 PciExplainBridgeControl (
3703 IN UINT16
*BridgeControl
,
3704 IN PCI_HEADER_TYPE HeaderType
3707 ShellPrintHiiEx(-1, -1, NULL
,
3708 STRING_TOKEN (STR_PCI2_BRIDGE_CONTROL
),
3709 gShellDebug1HiiHandle
,
3710 INDEX_OF (BridgeControl
),
3714 ShellPrintHiiEx(-1, -1, NULL
,
3715 STRING_TOKEN (STR_PCI2_PARITY_ERROR
),
3716 gShellDebug1HiiHandle
,
3717 (*BridgeControl
& PCI_BIT_0
) != 0
3719 ShellPrintHiiEx(-1, -1, NULL
,
3720 STRING_TOKEN (STR_PCI2_SERR_ENABLE
),
3721 gShellDebug1HiiHandle
,
3722 (*BridgeControl
& PCI_BIT_1
) != 0
3724 ShellPrintHiiEx(-1, -1, NULL
,
3725 STRING_TOKEN (STR_PCI2_ISA_ENABLE
),
3726 gShellDebug1HiiHandle
,
3727 (*BridgeControl
& PCI_BIT_2
) != 0
3729 ShellPrintHiiEx(-1, -1, NULL
,
3730 STRING_TOKEN (STR_PCI2_VGA_ENABLE
),
3731 gShellDebug1HiiHandle
,
3732 (*BridgeControl
& PCI_BIT_3
) != 0
3734 ShellPrintHiiEx(-1, -1, NULL
,
3735 STRING_TOKEN (STR_PCI2_MASTER_ABORT
),
3736 gShellDebug1HiiHandle
,
3737 (*BridgeControl
& PCI_BIT_5
) != 0
3741 // Register Bridge Control has some slight differences between P2P bridge
3742 // and Cardbus bridge from bit 6 to bit 11.
3744 if (HeaderType
== PciP2pBridge
) {
3745 ShellPrintHiiEx(-1, -1, NULL
,
3746 STRING_TOKEN (STR_PCI2_SECONDARY_BUS_RESET
),
3747 gShellDebug1HiiHandle
,
3748 (*BridgeControl
& PCI_BIT_6
) != 0
3750 ShellPrintHiiEx(-1, -1, NULL
,
3751 STRING_TOKEN (STR_PCI2_FAST_ENABLE
),
3752 gShellDebug1HiiHandle
,
3753 (*BridgeControl
& PCI_BIT_7
) != 0
3755 ShellPrintHiiEx(-1, -1, NULL
,
3756 STRING_TOKEN (STR_PCI2_PRIMARY_DISCARD_TIMER
),
3757 gShellDebug1HiiHandle
,
3758 (*BridgeControl
& PCI_BIT_8
)!=0 ? L
"2^10" : L
"2^15"
3760 ShellPrintHiiEx(-1, -1, NULL
,
3761 STRING_TOKEN (STR_PCI2_SECONDARY_DISCARD_TIMER
),
3762 gShellDebug1HiiHandle
,
3763 (*BridgeControl
& PCI_BIT_9
)!=0 ? L
"2^10" : L
"2^15"
3765 ShellPrintHiiEx(-1, -1, NULL
,
3766 STRING_TOKEN (STR_PCI2_DISCARD_TIMER_STATUS
),
3767 gShellDebug1HiiHandle
,
3768 (*BridgeControl
& PCI_BIT_10
) != 0
3770 ShellPrintHiiEx(-1, -1, NULL
,
3771 STRING_TOKEN (STR_PCI2_DISCARD_TIMER_SERR
),
3772 gShellDebug1HiiHandle
,
3773 (*BridgeControl
& PCI_BIT_11
) != 0
3777 ShellPrintHiiEx(-1, -1, NULL
,
3778 STRING_TOKEN (STR_PCI2_CARDBUS_RESET
),
3779 gShellDebug1HiiHandle
,
3780 (*BridgeControl
& PCI_BIT_6
) != 0
3782 ShellPrintHiiEx(-1, -1, NULL
,
3783 STRING_TOKEN (STR_PCI2_IREQ_ENABLE
),
3784 gShellDebug1HiiHandle
,
3785 (*BridgeControl
& PCI_BIT_7
) != 0
3787 ShellPrintHiiEx(-1, -1, NULL
,
3788 STRING_TOKEN (STR_PCI2_WRITE_POSTING_ENABLE
),
3789 gShellDebug1HiiHandle
,
3790 (*BridgeControl
& PCI_BIT_10
) != 0
3798 Print each capability structure.
3800 @param[in] IoDev The pointer to the deivce.
3801 @param[in] Address The address to start at.
3802 @param[in] CapPtr The offset from the address.
3803 @param[in] EnhancedDump The print format for the dump data.
3805 @retval EFI_SUCCESS The operation was successful.
3808 PciExplainCapabilityStruct (
3809 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
,
3812 IN CONST UINT16 EnhancedDump
3815 UINT8 CapabilityPtr
;
3816 UINT16 CapabilityEntry
;
3820 CapabilityPtr
= CapPtr
;
3823 // Go through the Capability list
3825 while ((CapabilityPtr
>= 0x40) && ((CapabilityPtr
& 0x03) == 0x00)) {
3826 RegAddress
= Address
+ CapabilityPtr
;
3827 IoDev
->Pci
.Read (IoDev
, EfiPciWidthUint16
, RegAddress
, 1, &CapabilityEntry
);
3829 CapabilityID
= (UINT8
) CapabilityEntry
;
3832 // Explain PciExpress data
3834 if (EFI_PCI_CAPABILITY_ID_PCIEXP
== CapabilityID
) {
3835 PciExplainPciExpress (IoDev
, Address
, CapabilityPtr
, EnhancedDump
);
3839 // Explain other capabilities here
3841 CapabilityPtr
= (UINT8
) (CapabilityEntry
>> 8);
3848 Print out information of the capability information.
3850 @param[in] PciExpressCap The pointer to the structure about the device.
3852 @retval EFI_SUCCESS The operation was successful.
3856 IN PCIE_CAP_STURCTURE
*PciExpressCap
3860 CHAR16
*DevicePortType
;
3862 PcieCapReg
= PciExpressCap
->PcieCapReg
;
3863 ShellPrintEx (-1, -1,
3864 L
" Capability Version(3:0): %E0x%04x%N\r\n",
3865 PCIE_CAP_VERSION (PcieCapReg
)
3867 if ((UINT8
) PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg
) < PCIE_DEVICE_PORT_TYPE_MAX
) {
3868 DevicePortType
= DevicePortTypeTable
[PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg
)];
3870 DevicePortType
= L
"Unknown Type";
3872 ShellPrintEx (-1, -1,
3873 L
" Device/PortType(7:4): %E%s%N\r\n",
3877 // 'Slot Implemented' is only valid for:
3878 // a) Root Port of PCI Express Root Complex, or
3879 // b) Downstream Port of PCI Express Switch
3881 if (PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg
) == PCIE_ROOT_COMPLEX_ROOT_PORT
||
3882 PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg
) == PCIE_SWITCH_DOWNSTREAM_PORT
) {
3883 ShellPrintEx (-1, -1,
3884 L
" Slot Implemented(8): %E%d%N\r\n",
3885 PCIE_CAP_SLOT_IMPLEMENTED (PcieCapReg
)
3888 ShellPrintEx (-1, -1,
3889 L
" Interrupt Message Number(13:9): %E0x%05x%N\r\n",
3890 PCIE_CAP_INT_MSG_NUM (PcieCapReg
)
3896 Print out information of the device capability information.
3898 @param[in] PciExpressCap The pointer to the structure about the device.
3900 @retval EFI_SUCCESS The operation was successful.
3903 ExplainPcieDeviceCap (
3904 IN PCIE_CAP_STURCTURE
*PciExpressCap
3908 UINT32 PcieDeviceCap
;
3909 UINT8 DevicePortType
;
3913 PcieCapReg
= PciExpressCap
->PcieCapReg
;
3914 PcieDeviceCap
= PciExpressCap
->PcieDeviceCap
;
3915 DevicePortType
= (UINT8
) PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg
);
3916 ShellPrintEx (-1, -1, L
" Max_Payload_Size Supported(2:0): ");
3917 if (PCIE_CAP_MAX_PAYLOAD (PcieDeviceCap
) < 6) {
3918 ShellPrintEx (-1, -1, L
"%E%d bytes%N\r\n", 1 << (PCIE_CAP_MAX_PAYLOAD (PcieDeviceCap
) + 7));
3920 ShellPrintEx (-1, -1, L
"%EUnknown%N\r\n");
3922 ShellPrintEx (-1, -1,
3923 L
" Phantom Functions Supported(4:3): %E%d%N\r\n",
3924 PCIE_CAP_PHANTOM_FUNC (PcieDeviceCap
)
3926 ShellPrintEx (-1, -1,
3927 L
" Extended Tag Field Supported(5): %E%d-bit Tag field supported%N\r\n",
3928 PCIE_CAP_EXTENDED_TAG (PcieDeviceCap
) ? 8 : 5
3931 // Endpoint L0s and L1 Acceptable Latency is only valid for Endpoint
3933 if (IS_PCIE_ENDPOINT (DevicePortType
)) {
3934 L0sLatency
= (UINT8
) PCIE_CAP_L0SLATENCY (PcieDeviceCap
);
3935 L1Latency
= (UINT8
) PCIE_CAP_L1LATENCY (PcieDeviceCap
);
3936 ShellPrintEx (-1, -1, L
" Endpoint L0s Acceptable Latency(8:6): ");
3937 if (L0sLatency
< 4) {
3938 ShellPrintEx (-1, -1, L
"%EMaximum of %d ns%N\r\n", 1 << (L0sLatency
+ 6));
3940 if (L0sLatency
< 7) {
3941 ShellPrintEx (-1, -1, L
"%EMaximum of %d us%N\r\n", 1 << (L0sLatency
- 3));
3943 ShellPrintEx (-1, -1, L
"%ENo limit%N\r\n");
3946 ShellPrintEx (-1, -1, L
" Endpoint L1 Acceptable Latency(11:9): ");
3947 if (L1Latency
< 7) {
3948 ShellPrintEx (-1, -1, L
"%EMaximum of %d us%N\r\n", 1 << (L1Latency
+ 1));
3950 ShellPrintEx (-1, -1, L
"%ENo limit%N\r\n");
3953 ShellPrintEx (-1, -1,
3954 L
" Role-based Error Reporting(15): %E%d%N\r\n",
3955 PCIE_CAP_ERR_REPORTING (PcieDeviceCap
)
3958 // Only valid for Upstream Port:
3959 // a) Captured Slot Power Limit Value
3960 // b) Captured Slot Power Scale
3962 if (DevicePortType
== PCIE_SWITCH_UPSTREAM_PORT
) {
3963 ShellPrintEx (-1, -1,
3964 L
" Captured Slot Power Limit Value(25:18): %E0x%02x%N\r\n",
3965 PCIE_CAP_SLOT_POWER_VALUE (PcieDeviceCap
)
3967 ShellPrintEx (-1, -1,
3968 L
" Captured Slot Power Limit Scale(27:26): %E%s%N\r\n",
3969 SlotPwrLmtScaleTable
[PCIE_CAP_SLOT_POWER_SCALE (PcieDeviceCap
)]
3973 // Function Level Reset Capability is only valid for Endpoint
3975 if (IS_PCIE_ENDPOINT (DevicePortType
)) {
3976 ShellPrintEx (-1, -1,
3977 L
" Function Level Reset Capability(28): %E%d%N\r\n",
3978 PCIE_CAP_FUNC_LEVEL_RESET (PcieDeviceCap
)
3985 Print out information of the device control information.
3987 @param[in] PciExpressCap The pointer to the structure about the device.
3989 @retval EFI_SUCCESS The operation was successful.
3992 ExplainPcieDeviceControl (
3993 IN PCIE_CAP_STURCTURE
*PciExpressCap
3997 UINT16 PcieDeviceControl
;
3999 PcieCapReg
= PciExpressCap
->PcieCapReg
;
4000 PcieDeviceControl
= PciExpressCap
->DeviceControl
;
4001 ShellPrintEx (-1, -1,
4002 L
" Correctable Error Reporting Enable(0): %E%d%N\r\n",
4003 PCIE_CAP_COR_ERR_REPORTING_ENABLE (PcieDeviceControl
)
4005 ShellPrintEx (-1, -1,
4006 L
" Non-Fatal Error Reporting Enable(1): %E%d%N\r\n",
4007 PCIE_CAP_NONFAT_ERR_REPORTING_ENABLE (PcieDeviceControl
)
4009 ShellPrintEx (-1, -1,
4010 L
" Fatal Error Reporting Enable(2): %E%d%N\r\n",
4011 PCIE_CAP_FATAL_ERR_REPORTING_ENABLE (PcieDeviceControl
)
4013 ShellPrintEx (-1, -1,
4014 L
" Unsupported Request Reporting Enable(3): %E%d%N\r\n",
4015 PCIE_CAP_UNSUP_REQ_REPORTING_ENABLE (PcieDeviceControl
)
4017 ShellPrintEx (-1, -1,
4018 L
" Enable Relaxed Ordering(4): %E%d%N\r\n",
4019 PCIE_CAP_RELAXED_ORDERING_ENABLE (PcieDeviceControl
)
4021 ShellPrintEx (-1, -1, L
" Max_Payload_Size(7:5): ");
4022 if (PCIE_CAP_MAX_PAYLOAD_SIZE (PcieDeviceControl
) < 6) {
4023 ShellPrintEx (-1, -1, L
"%E%d bytes%N\r\n", 1 << (PCIE_CAP_MAX_PAYLOAD_SIZE (PcieDeviceControl
) + 7));
4025 ShellPrintEx (-1, -1, L
"%EUnknown%N\r\n");
4027 ShellPrintEx (-1, -1,
4028 L
" Extended Tag Field Enable(8): %E%d%N\r\n",
4029 PCIE_CAP_EXTENDED_TAG_ENABLE (PcieDeviceControl
)
4031 ShellPrintEx (-1, -1,
4032 L
" Phantom Functions Enable(9): %E%d%N\r\n",
4033 PCIE_CAP_PHANTOM_FUNC_ENABLE (PcieDeviceControl
)
4035 ShellPrintEx (-1, -1,
4036 L
" Auxiliary (AUX) Power PM Enable(10): %E%d%N\r\n",
4037 PCIE_CAP_AUX_PM_ENABLE (PcieDeviceControl
)
4039 ShellPrintEx (-1, -1,
4040 L
" Enable No Snoop(11): %E%d%N\r\n",
4041 PCIE_CAP_NO_SNOOP_ENABLE (PcieDeviceControl
)
4043 ShellPrintEx (-1, -1, L
" Max_Read_Request_Size(14:12): ");
4044 if (PCIE_CAP_MAX_READ_REQ_SIZE (PcieDeviceControl
) < 6) {
4045 ShellPrintEx (-1, -1, L
"%E%d bytes%N\r\n", 1 << (PCIE_CAP_MAX_READ_REQ_SIZE (PcieDeviceControl
) + 7));
4047 ShellPrintEx (-1, -1, L
"%EUnknown%N\r\n");
4050 // Read operation is only valid for PCI Express to PCI/PCI-X Bridges
4052 if (PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg
) == PCIE_PCIE_TO_PCIX_BRIDGE
) {
4053 ShellPrintEx (-1, -1,
4054 L
" Bridge Configuration Retry Enable(15): %E%d%N\r\n",
4055 PCIE_CAP_BRG_CONF_RETRY (PcieDeviceControl
)
4062 Print out information of the device status information.
4064 @param[in] PciExpressCap The pointer to the structure about the device.
4066 @retval EFI_SUCCESS The operation was successful.
4069 ExplainPcieDeviceStatus (
4070 IN PCIE_CAP_STURCTURE
*PciExpressCap
4073 UINT16 PcieDeviceStatus
;
4075 PcieDeviceStatus
= PciExpressCap
->DeviceStatus
;
4076 ShellPrintEx (-1, -1,
4077 L
" Correctable Error Detected(0): %E%d%N\r\n",
4078 PCIE_CAP_COR_ERR_DETECTED (PcieDeviceStatus
)
4080 ShellPrintEx (-1, -1,
4081 L
" Non-Fatal Error Detected(1): %E%d%N\r\n",
4082 PCIE_CAP_NONFAT_ERR_DETECTED (PcieDeviceStatus
)
4084 ShellPrintEx (-1, -1,
4085 L
" Fatal Error Detected(2): %E%d%N\r\n",
4086 PCIE_CAP_FATAL_ERR_DETECTED (PcieDeviceStatus
)
4088 ShellPrintEx (-1, -1,
4089 L
" Unsupported Request Detected(3): %E%d%N\r\n",
4090 PCIE_CAP_UNSUP_REQ_DETECTED (PcieDeviceStatus
)
4092 ShellPrintEx (-1, -1,
4093 L
" AUX Power Detected(4): %E%d%N\r\n",
4094 PCIE_CAP_AUX_POWER_DETECTED (PcieDeviceStatus
)
4096 ShellPrintEx (-1, -1,
4097 L
" Transactions Pending(5): %E%d%N\r\n",
4098 PCIE_CAP_TRANSACTION_PENDING (PcieDeviceStatus
)
4104 Print out information of the device link information.
4106 @param[in] PciExpressCap The pointer to the structure about the device.
4108 @retval EFI_SUCCESS The operation was successful.
4111 ExplainPcieLinkCap (
4112 IN PCIE_CAP_STURCTURE
*PciExpressCap
4116 CHAR16
*MaxLinkSpeed
;
4119 PcieLinkCap
= PciExpressCap
->LinkCap
;
4120 switch (PCIE_CAP_MAX_LINK_SPEED (PcieLinkCap
)) {
4122 MaxLinkSpeed
= L
"2.5 GT/s";
4125 MaxLinkSpeed
= L
"5.0 GT/s";
4128 MaxLinkSpeed
= L
"8.0 GT/s";
4131 MaxLinkSpeed
= L
"Unknown";
4134 ShellPrintEx (-1, -1,
4135 L
" Maximum Link Speed(3:0): %E%s%N\r\n",
4138 ShellPrintEx (-1, -1,
4139 L
" Maximum Link Width(9:4): %Ex%d%N\r\n",
4140 PCIE_CAP_MAX_LINK_WIDTH (PcieLinkCap
)
4142 switch (PCIE_CAP_ASPM_SUPPORT (PcieLinkCap
)) {
4153 AspmValue
= L
"L0s and L1";
4156 AspmValue
= L
"Reserved";
4159 ShellPrintEx (-1, -1,
4160 L
" Active State Power Management Support(11:10): %E%s Supported%N\r\n",
4163 ShellPrintEx (-1, -1,
4164 L
" L0s Exit Latency(14:12): %E%s%N\r\n",
4165 L0sLatencyStrTable
[PCIE_CAP_L0S_LATENCY (PcieLinkCap
)]
4167 ShellPrintEx (-1, -1,
4168 L
" L1 Exit Latency(17:15): %E%s%N\r\n",
4169 L1LatencyStrTable
[PCIE_CAP_L0S_LATENCY (PcieLinkCap
)]
4171 ShellPrintEx (-1, -1,
4172 L
" Clock Power Management(18): %E%d%N\r\n",
4173 PCIE_CAP_CLOCK_PM (PcieLinkCap
)
4175 ShellPrintEx (-1, -1,
4176 L
" Surprise Down Error Reporting Capable(19): %E%d%N\r\n",
4177 PCIE_CAP_SUP_DOWN_ERR_REPORTING (PcieLinkCap
)
4179 ShellPrintEx (-1, -1,
4180 L
" Data Link Layer Link Active Reporting Capable(20): %E%d%N\r\n",
4181 PCIE_CAP_LINK_ACTIVE_REPORTING (PcieLinkCap
)
4183 ShellPrintEx (-1, -1,
4184 L
" Link Bandwidth Notification Capability(21): %E%d%N\r\n",
4185 PCIE_CAP_LINK_BWD_NOTIF_CAP (PcieLinkCap
)
4187 ShellPrintEx (-1, -1,
4188 L
" Port Number(31:24): %E0x%02x%N\r\n",
4189 PCIE_CAP_PORT_NUMBER (PcieLinkCap
)
4195 Print out information of the device link control information.
4197 @param[in] PciExpressCap The pointer to the structure about the device.
4199 @retval EFI_SUCCESS The operation was successful.
4202 ExplainPcieLinkControl (
4203 IN PCIE_CAP_STURCTURE
*PciExpressCap
4206 UINT16 PcieLinkControl
;
4207 UINT8 DevicePortType
;
4209 PcieLinkControl
= PciExpressCap
->LinkControl
;
4210 DevicePortType
= (UINT8
) PCIE_CAP_DEVICEPORT_TYPE (PciExpressCap
->PcieCapReg
);
4211 ShellPrintEx (-1, -1,
4212 L
" Active State Power Management Control(1:0): %E%s%N\r\n",
4213 ASPMCtrlStrTable
[PCIE_CAP_ASPM_CONTROL (PcieLinkControl
)]
4216 // RCB is not applicable to switches
4218 if (!IS_PCIE_SWITCH(DevicePortType
)) {
4219 ShellPrintEx (-1, -1,
4220 L
" Read Completion Boundary (RCB)(3): %E%d byte%N\r\n",
4221 1 << (PCIE_CAP_RCB (PcieLinkControl
) + 6)
4225 // Link Disable is reserved on
4227 // b) PCI Express to PCI/PCI-X bridges
4228 // c) Upstream Ports of Switches
4230 if (!IS_PCIE_ENDPOINT (DevicePortType
) &&
4231 DevicePortType
!= PCIE_SWITCH_UPSTREAM_PORT
&&
4232 DevicePortType
!= PCIE_PCIE_TO_PCIX_BRIDGE
) {
4233 ShellPrintEx (-1, -1,
4234 L
" Link Disable(4): %E%d%N\r\n",
4235 PCIE_CAP_LINK_DISABLE (PcieLinkControl
)
4238 ShellPrintEx (-1, -1,
4239 L
" Common Clock Configuration(6): %E%d%N\r\n",
4240 PCIE_CAP_COMMON_CLK_CONF (PcieLinkControl
)
4242 ShellPrintEx (-1, -1,
4243 L
" Extended Synch(7): %E%d%N\r\n",
4244 PCIE_CAP_EXT_SYNC (PcieLinkControl
)
4246 ShellPrintEx (-1, -1,
4247 L
" Enable Clock Power Management(8): %E%d%N\r\n",
4248 PCIE_CAP_CLK_PWR_MNG (PcieLinkControl
)
4250 ShellPrintEx (-1, -1,
4251 L
" Hardware Autonomous Width Disable(9): %E%d%N\r\n",
4252 PCIE_CAP_HW_AUTO_WIDTH_DISABLE (PcieLinkControl
)
4254 ShellPrintEx (-1, -1,
4255 L
" Link Bandwidth Management Interrupt Enable(10): %E%d%N\r\n",
4256 PCIE_CAP_LINK_BDW_MNG_INT_EN (PcieLinkControl
)
4258 ShellPrintEx (-1, -1,
4259 L
" Link Autonomous Bandwidth Interrupt Enable(11): %E%d%N\r\n",
4260 PCIE_CAP_LINK_AUTO_BDW_INT_EN (PcieLinkControl
)
4266 Print out information of the device link status information.
4268 @param[in] PciExpressCap The pointer to the structure about the device.
4270 @retval EFI_SUCCESS The operation was successful.
4273 ExplainPcieLinkStatus (
4274 IN PCIE_CAP_STURCTURE
*PciExpressCap
4277 UINT16 PcieLinkStatus
;
4278 CHAR16
*CurLinkSpeed
;
4280 PcieLinkStatus
= PciExpressCap
->LinkStatus
;
4281 switch (PCIE_CAP_CUR_LINK_SPEED (PcieLinkStatus
)) {
4283 CurLinkSpeed
= L
"2.5 GT/s";
4286 CurLinkSpeed
= L
"5.0 GT/s";
4289 CurLinkSpeed
= L
"8.0 GT/s";
4292 CurLinkSpeed
= L
"Reserved";
4295 ShellPrintEx (-1, -1,
4296 L
" Current Link Speed(3:0): %E%s%N\r\n",
4299 ShellPrintEx (-1, -1,
4300 L
" Negotiated Link Width(9:4): %Ex%d%N\r\n",
4301 PCIE_CAP_NEGO_LINK_WIDTH (PcieLinkStatus
)
4303 ShellPrintEx (-1, -1,
4304 L
" Link Training(11): %E%d%N\r\n",
4305 PCIE_CAP_LINK_TRAINING (PcieLinkStatus
)
4307 ShellPrintEx (-1, -1,
4308 L
" Slot Clock Configuration(12): %E%d%N\r\n",
4309 PCIE_CAP_SLOT_CLK_CONF (PcieLinkStatus
)
4311 ShellPrintEx (-1, -1,
4312 L
" Data Link Layer Link Active(13): %E%d%N\r\n",
4313 PCIE_CAP_DATA_LINK_ACTIVE (PcieLinkStatus
)
4315 ShellPrintEx (-1, -1,
4316 L
" Link Bandwidth Management Status(14): %E%d%N\r\n",
4317 PCIE_CAP_LINK_BDW_MNG_STAT (PcieLinkStatus
)
4319 ShellPrintEx (-1, -1,
4320 L
" Link Autonomous Bandwidth Status(15): %E%d%N\r\n",
4321 PCIE_CAP_LINK_AUTO_BDW_STAT (PcieLinkStatus
)
4327 Print out information of the device slot information.
4329 @param[in] PciExpressCap The pointer to the structure about the device.
4331 @retval EFI_SUCCESS The operation was successful.
4334 ExplainPcieSlotCap (
4335 IN PCIE_CAP_STURCTURE
*PciExpressCap
4340 PcieSlotCap
= PciExpressCap
->SlotCap
;
4342 ShellPrintEx (-1, -1,
4343 L
" Attention Button Present(0): %E%d%N\r\n",
4344 PCIE_CAP_ATT_BUT_PRESENT (PcieSlotCap
)
4346 ShellPrintEx (-1, -1,
4347 L
" Power Controller Present(1): %E%d%N\r\n",
4348 PCIE_CAP_PWR_CTRLLER_PRESENT (PcieSlotCap
)
4350 ShellPrintEx (-1, -1,
4351 L
" MRL Sensor Present(2): %E%d%N\r\n",
4352 PCIE_CAP_MRL_SENSOR_PRESENT (PcieSlotCap
)
4354 ShellPrintEx (-1, -1,
4355 L
" Attention Indicator Present(3): %E%d%N\r\n",
4356 PCIE_CAP_ATT_IND_PRESENT (PcieSlotCap
)
4358 ShellPrintEx (-1, -1,
4359 L
" Power Indicator Present(4): %E%d%N\r\n",
4360 PCIE_CAP_PWD_IND_PRESENT (PcieSlotCap
)
4362 ShellPrintEx (-1, -1,
4363 L
" Hot-Plug Surprise(5): %E%d%N\r\n",
4364 PCIE_CAP_HOTPLUG_SUPPRISE (PcieSlotCap
)
4366 ShellPrintEx (-1, -1,
4367 L
" Hot-Plug Capable(6): %E%d%N\r\n",
4368 PCIE_CAP_HOTPLUG_CAPABLE (PcieSlotCap
)
4370 ShellPrintEx (-1, -1,
4371 L
" Slot Power Limit Value(14:7): %E0x%02x%N\r\n",
4372 PCIE_CAP_SLOT_PWR_LIMIT_VALUE (PcieSlotCap
)
4374 ShellPrintEx (-1, -1,
4375 L
" Slot Power Limit Scale(16:15): %E%s%N\r\n",
4376 SlotPwrLmtScaleTable
[PCIE_CAP_SLOT_PWR_LIMIT_SCALE (PcieSlotCap
)]
4378 ShellPrintEx (-1, -1,
4379 L
" Electromechanical Interlock Present(17): %E%d%N\r\n",
4380 PCIE_CAP_ELEC_INTERLOCK_PRESENT (PcieSlotCap
)
4382 ShellPrintEx (-1, -1,
4383 L
" No Command Completed Support(18): %E%d%N\r\n",
4384 PCIE_CAP_NO_COMM_COMPLETED_SUP (PcieSlotCap
)
4386 ShellPrintEx (-1, -1,
4387 L
" Physical Slot Number(31:19): %E%d%N\r\n",
4388 PCIE_CAP_PHY_SLOT_NUM (PcieSlotCap
)
4395 Print out information of the device slot control information.
4397 @param[in] PciExpressCap The pointer to the structure about the device.
4399 @retval EFI_SUCCESS The operation was successful.
4402 ExplainPcieSlotControl (
4403 IN PCIE_CAP_STURCTURE
*PciExpressCap
4406 UINT16 PcieSlotControl
;
4408 PcieSlotControl
= PciExpressCap
->SlotControl
;
4409 ShellPrintEx (-1, -1,
4410 L
" Attention Button Pressed Enable(0): %E%d%N\r\n",
4411 PCIE_CAP_ATT_BUT_ENABLE (PcieSlotControl
)
4413 ShellPrintEx (-1, -1,
4414 L
" Power Fault Detected Enable(1): %E%d%N\r\n",
4415 PCIE_CAP_PWR_FLT_DETECT_ENABLE (PcieSlotControl
)
4417 ShellPrintEx (-1, -1,
4418 L
" MRL Sensor Changed Enable(2): %E%d%N\r\n",
4419 PCIE_CAP_MRL_SENSOR_CHANGE_ENABLE (PcieSlotControl
)
4421 ShellPrintEx (-1, -1,
4422 L
" Presence Detect Changed Enable(3): %E%d%N\r\n",
4423 PCIE_CAP_PRES_DETECT_CHANGE_ENABLE (PcieSlotControl
)
4425 ShellPrintEx (-1, -1,
4426 L
" Command Completed Interrupt Enable(4): %E%d%N\r\n",
4427 PCIE_CAP_COMM_CMPL_INT_ENABLE (PcieSlotControl
)
4429 ShellPrintEx (-1, -1,
4430 L
" Hot-Plug Interrupt Enable(5): %E%d%N\r\n",
4431 PCIE_CAP_HOTPLUG_INT_ENABLE (PcieSlotControl
)
4433 ShellPrintEx (-1, -1,
4434 L
" Attention Indicator Control(7:6): %E%s%N\r\n",
4435 IndicatorTable
[PCIE_CAP_ATT_IND_CTRL (PcieSlotControl
)]
4437 ShellPrintEx (-1, -1,
4438 L
" Power Indicator Control(9:8): %E%s%N\r\n",
4439 IndicatorTable
[PCIE_CAP_PWR_IND_CTRL (PcieSlotControl
)]
4441 ShellPrintEx (-1, -1, L
" Power Controller Control(10): %EPower ");
4442 if (PCIE_CAP_PWR_CTRLLER_CTRL (PcieSlotControl
)) {
4443 ShellPrintEx (-1, -1, L
"Off%N\r\n");
4445 ShellPrintEx (-1, -1, L
"On%N\r\n");
4447 ShellPrintEx (-1, -1,
4448 L
" Electromechanical Interlock Control(11): %E%d%N\r\n",
4449 PCIE_CAP_ELEC_INTERLOCK_CTRL (PcieSlotControl
)
4451 ShellPrintEx (-1, -1,
4452 L
" Data Link Layer State Changed Enable(12): %E%d%N\r\n",
4453 PCIE_CAP_DLINK_STAT_CHANGE_ENABLE (PcieSlotControl
)
4459 Print out information of the device slot status information.
4461 @param[in] PciExpressCap The pointer to the structure about the device.
4463 @retval EFI_SUCCESS The operation was successful.
4466 ExplainPcieSlotStatus (
4467 IN PCIE_CAP_STURCTURE
*PciExpressCap
4470 UINT16 PcieSlotStatus
;
4472 PcieSlotStatus
= PciExpressCap
->SlotStatus
;
4474 ShellPrintEx (-1, -1,
4475 L
" Attention Button Pressed(0): %E%d%N\r\n",
4476 PCIE_CAP_ATT_BUT_PRESSED (PcieSlotStatus
)
4478 ShellPrintEx (-1, -1,
4479 L
" Power Fault Detected(1): %E%d%N\r\n",
4480 PCIE_CAP_PWR_FLT_DETECTED (PcieSlotStatus
)
4482 ShellPrintEx (-1, -1,
4483 L
" MRL Sensor Changed(2): %E%d%N\r\n",
4484 PCIE_CAP_MRL_SENSOR_CHANGED (PcieSlotStatus
)
4486 ShellPrintEx (-1, -1,
4487 L
" Presence Detect Changed(3): %E%d%N\r\n",
4488 PCIE_CAP_PRES_DETECT_CHANGED (PcieSlotStatus
)
4490 ShellPrintEx (-1, -1,
4491 L
" Command Completed(4): %E%d%N\r\n",
4492 PCIE_CAP_COMM_COMPLETED (PcieSlotStatus
)
4494 ShellPrintEx (-1, -1, L
" MRL Sensor State(5): %EMRL ");
4495 if (PCIE_CAP_MRL_SENSOR_STATE (PcieSlotStatus
)) {
4496 ShellPrintEx (-1, -1, L
" Opened%N\r\n");
4498 ShellPrintEx (-1, -1, L
" Closed%N\r\n");
4500 ShellPrintEx (-1, -1, L
" Presence Detect State(6): ");
4501 if (PCIE_CAP_PRES_DETECT_STATE (PcieSlotStatus
)) {
4502 ShellPrintEx (-1, -1, L
"%ECard Present in slot%N\r\n");
4504 ShellPrintEx (-1, -1, L
"%ESlot Empty%N\r\n");
4506 ShellPrintEx (-1, -1, L
" Electromechanical Interlock Status(7): %EElectromechanical Interlock ");
4507 if (PCIE_CAP_ELEC_INTERLOCK_STATE (PcieSlotStatus
)) {
4508 ShellPrintEx (-1, -1, L
"Engaged%N\r\n");
4510 ShellPrintEx (-1, -1, L
"Disengaged%N\r\n");
4512 ShellPrintEx (-1, -1,
4513 L
" Data Link Layer State Changed(8): %E%d%N\r\n",
4514 PCIE_CAP_DLINK_STAT_CHANGED (PcieSlotStatus
)
4520 Print out information of the device root information.
4522 @param[in] PciExpressCap The pointer to the structure about the device.
4524 @retval EFI_SUCCESS The operation was successful.
4527 ExplainPcieRootControl (
4528 IN PCIE_CAP_STURCTURE
*PciExpressCap
4531 UINT16 PcieRootControl
;
4533 PcieRootControl
= PciExpressCap
->RootControl
;
4535 ShellPrintEx (-1, -1,
4536 L
" System Error on Correctable Error Enable(0): %E%d%N\r\n",
4537 PCIE_CAP_SYSERR_ON_CORERR_EN (PcieRootControl
)
4539 ShellPrintEx (-1, -1,
4540 L
" System Error on Non-Fatal Error Enable(1): %E%d%N\r\n",
4541 PCIE_CAP_SYSERR_ON_NONFATERR_EN (PcieRootControl
)
4543 ShellPrintEx (-1, -1,
4544 L
" System Error on Fatal Error Enable(2): %E%d%N\r\n",
4545 PCIE_CAP_SYSERR_ON_FATERR_EN (PcieRootControl
)
4547 ShellPrintEx (-1, -1,
4548 L
" PME Interrupt Enable(3): %E%d%N\r\n",
4549 PCIE_CAP_PME_INT_ENABLE (PcieRootControl
)
4551 ShellPrintEx (-1, -1,
4552 L
" CRS Software Visibility Enable(4): %E%d%N\r\n",
4553 PCIE_CAP_CRS_SW_VIS_ENABLE (PcieRootControl
)
4560 Print out information of the device root capability information.
4562 @param[in] PciExpressCap The pointer to the structure about the device.
4564 @retval EFI_SUCCESS The operation was successful.
4567 ExplainPcieRootCap (
4568 IN PCIE_CAP_STURCTURE
*PciExpressCap
4573 PcieRootCap
= PciExpressCap
->RsvdP
;
4575 ShellPrintEx (-1, -1,
4576 L
" CRS Software Visibility(0): %E%d%N\r\n",
4577 PCIE_CAP_CRS_SW_VIS (PcieRootCap
)
4584 Print out information of the device root status information.
4586 @param[in] PciExpressCap The pointer to the structure about the device.
4588 @retval EFI_SUCCESS The operation was successful.
4591 ExplainPcieRootStatus (
4592 IN PCIE_CAP_STURCTURE
*PciExpressCap
4595 UINT32 PcieRootStatus
;
4597 PcieRootStatus
= PciExpressCap
->RootStatus
;
4599 ShellPrintEx (-1, -1,
4600 L
" PME Requester ID(15:0): %E0x%04x%N\r\n",
4601 PCIE_CAP_PME_REQ_ID (PcieRootStatus
)
4603 ShellPrintEx (-1, -1,
4604 L
" PME Status(16): %E%d%N\r\n",
4605 PCIE_CAP_PME_STATUS (PcieRootStatus
)
4607 ShellPrintEx (-1, -1,
4608 L
" PME Pending(17): %E%d%N\r\n",
4609 PCIE_CAP_PME_PENDING (PcieRootStatus
)
4615 Function to interpret and print out the link control structure
4617 @param[in] HeaderAddress The Address of this capability header.
4618 @param[in] HeadersBaseAddress The address of all the extended capability headers.
4622 PrintInterpretedExtendedCompatibilityLinkControl (
4623 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
4624 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
4627 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_INTERNAL_LINK_CONTROL
*Header
;
4628 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_INTERNAL_LINK_CONTROL
*)HeaderAddress
;
4632 STRING_TOKEN (STR_PCI_EXT_CAP_LINK_CONTROL
),
4633 gShellDebug1HiiHandle
,
4634 Header
->RootComplexLinkCapabilities
,
4635 Header
->RootComplexLinkControl
,
4636 Header
->RootComplexLinkStatus
4640 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
4641 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_INTERNAL_LINK_CONTROL
),
4642 (VOID
*) (HeaderAddress
)
4644 return (EFI_SUCCESS
);
4648 Function to interpret and print out the power budgeting structure
4650 @param[in] HeaderAddress The Address of this capability header.
4651 @param[in] HeadersBaseAddress The address of all the extended capability headers.
4655 PrintInterpretedExtendedCompatibilityPowerBudgeting (
4656 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
4657 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
4660 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_POWER_BUDGETING
*Header
;
4661 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_POWER_BUDGETING
*)HeaderAddress
;
4665 STRING_TOKEN (STR_PCI_EXT_CAP_POWER
),
4666 gShellDebug1HiiHandle
,
4669 Header
->PowerBudgetCapability
4673 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
4674 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_POWER_BUDGETING
),
4675 (VOID
*) (HeaderAddress
)
4677 return (EFI_SUCCESS
);
4681 Function to interpret and print out the ACS structure
4683 @param[in] HeaderAddress The Address of this capability header.
4684 @param[in] HeadersBaseAddress The address of all the extended capability headers.
4688 PrintInterpretedExtendedCompatibilityAcs (
4689 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
4690 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
4693 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_ACS_EXTENDED
*Header
;
4697 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_ACS_EXTENDED
*)HeaderAddress
;
4702 STRING_TOKEN (STR_PCI_EXT_CAP_ACS
),
4703 gShellDebug1HiiHandle
,
4704 Header
->AcsCapability
,
4707 if (PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_GET_EGRES_CONTROL(Header
)) {
4708 VectorSize
= PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_GET_EGRES_VECTOR_SIZE(Header
);
4709 if (VectorSize
== 0) {
4712 for (LoopCounter
= 0 ; LoopCounter
* 8 < VectorSize
; LoopCounter
++) {
4715 STRING_TOKEN (STR_PCI_EXT_CAP_ACS2
),
4716 gShellDebug1HiiHandle
,
4718 Header
->EgressControlVectorArray
[LoopCounter
]
4724 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
4725 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_ACS_EXTENDED
) + (VectorSize
/ 8) - 1,
4726 (VOID
*) (HeaderAddress
)
4728 return (EFI_SUCCESS
);
4732 Function to interpret and print out the latency tolerance reporting structure
4734 @param[in] HeaderAddress The Address of this capability header.
4735 @param[in] HeadersBaseAddress The address of all the extended capability headers.
4739 PrintInterpretedExtendedCompatibilityLatencyToleranceReporting (
4740 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
4741 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
4744 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_LATENCE_TOLERANCE_REPORTING
*Header
;
4745 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_LATENCE_TOLERANCE_REPORTING
*)HeaderAddress
;
4749 STRING_TOKEN (STR_PCI_EXT_CAP_LAT
),
4750 gShellDebug1HiiHandle
,
4751 Header
->MaxSnoopLatency
,
4752 Header
->MaxNoSnoopLatency
4756 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
4757 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_LATENCE_TOLERANCE_REPORTING
),
4758 (VOID
*) (HeaderAddress
)
4760 return (EFI_SUCCESS
);
4764 Function to interpret and print out the serial number structure
4766 @param[in] HeaderAddress The Address of this capability header.
4767 @param[in] HeadersBaseAddress The address of all the extended capability headers.
4771 PrintInterpretedExtendedCompatibilitySerialNumber (
4772 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
4773 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
4776 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_SERIAL_NUMBER
*Header
;
4777 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_SERIAL_NUMBER
*)HeaderAddress
;
4781 STRING_TOKEN (STR_PCI_EXT_CAP_SN
),
4782 gShellDebug1HiiHandle
,
4783 Header
->SerialNumber
4787 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
4788 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_SERIAL_NUMBER
),
4789 (VOID
*) (HeaderAddress
)
4791 return (EFI_SUCCESS
);
4795 Function to interpret and print out the RCRB structure
4797 @param[in] HeaderAddress The Address of this capability header.
4798 @param[in] HeadersBaseAddress The address of all the extended capability headers.
4802 PrintInterpretedExtendedCompatibilityRcrb (
4803 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
4804 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
4807 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_RCRB_HEADER
*Header
;
4808 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_RCRB_HEADER
*)HeaderAddress
;
4812 STRING_TOKEN (STR_PCI_EXT_CAP_RCRB
),
4813 gShellDebug1HiiHandle
,
4816 Header
->RcrbCapabilities
,
4821 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
4822 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_RCRB_HEADER
),
4823 (VOID
*) (HeaderAddress
)
4825 return (EFI_SUCCESS
);
4829 Function to interpret and print out the vendor specific structure
4831 @param[in] HeaderAddress The Address of this capability header.
4832 @param[in] HeadersBaseAddress The address of all the extended capability headers.
4836 PrintInterpretedExtendedCompatibilityVendorSpecific (
4837 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
4838 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
4841 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_VENDOR_SPECIFIC
*Header
;
4842 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_VENDOR_SPECIFIC
*)HeaderAddress
;
4846 STRING_TOKEN (STR_PCI_EXT_CAP_VEN
),
4847 gShellDebug1HiiHandle
,
4848 Header
->VendorSpecificHeader
4852 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
4853 PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_GET_SIZE(Header
),
4854 (VOID
*) (HeaderAddress
)
4856 return (EFI_SUCCESS
);
4860 Function to interpret and print out the Event Collector Endpoint Association structure
4862 @param[in] HeaderAddress The Address of this capability header.
4863 @param[in] HeadersBaseAddress The address of all the extended capability headers.
4867 PrintInterpretedExtendedCompatibilityECEA (
4868 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
4869 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
4872 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION
*Header
;
4873 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION
*)HeaderAddress
;
4877 STRING_TOKEN (STR_PCI_EXT_CAP_ECEA
),
4878 gShellDebug1HiiHandle
,
4879 Header
->AssociationBitmap
4883 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
4884 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION
),
4885 (VOID
*) (HeaderAddress
)
4887 return (EFI_SUCCESS
);
4891 Function to interpret and print out the ARI structure
4893 @param[in] HeaderAddress The Address of this capability header.
4894 @param[in] HeadersBaseAddress The address of all the extended capability headers.
4898 PrintInterpretedExtendedCompatibilityAri (
4899 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
4900 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
4903 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_ARI_CAPABILITY
*Header
;
4904 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_ARI_CAPABILITY
*)HeaderAddress
;
4908 STRING_TOKEN (STR_PCI_EXT_CAP_ARI
),
4909 gShellDebug1HiiHandle
,
4910 Header
->AriCapability
,
4915 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
4916 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_ARI_CAPABILITY
),
4917 (VOID
*) (HeaderAddress
)
4919 return (EFI_SUCCESS
);
4923 Function to interpret and print out the DPA structure
4925 @param[in] HeaderAddress The Address of this capability header.
4926 @param[in] HeadersBaseAddress The address of all the extended capability headers.
4930 PrintInterpretedExtendedCompatibilityDynamicPowerAllocation (
4931 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
4932 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
4935 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_DYNAMIC_POWER_ALLOCATION
*Header
;
4937 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_DYNAMIC_POWER_ALLOCATION
*)HeaderAddress
;
4941 STRING_TOKEN (STR_PCI_EXT_CAP_DPA
),
4942 gShellDebug1HiiHandle
,
4943 Header
->DpaCapability
,
4944 Header
->DpaLatencyIndicator
,
4948 for (LinkCount
= 0 ; LinkCount
< PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_GET_SUBSTATE_MAX(Header
) + 1 ; LinkCount
++) {
4951 STRING_TOKEN (STR_PCI_EXT_CAP_DPA2
),
4952 gShellDebug1HiiHandle
,
4954 Header
->DpaPowerAllocationArray
[LinkCount
]
4959 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
4960 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_DYNAMIC_POWER_ALLOCATION
) - 1 + PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_GET_SUBSTATE_MAX(Header
),
4961 (VOID
*) (HeaderAddress
)
4963 return (EFI_SUCCESS
);
4967 Function to interpret and print out the link declaration structure
4969 @param[in] HeaderAddress The Address of this capability header.
4970 @param[in] HeadersBaseAddress The address of all the extended capability headers.
4974 PrintInterpretedExtendedCompatibilityLinkDeclaration (
4975 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
4976 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
4979 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_LINK_DECLARATION
*Header
;
4981 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_LINK_DECLARATION
*)HeaderAddress
;
4985 STRING_TOKEN (STR_PCI_EXT_CAP_LINK_DECLAR
),
4986 gShellDebug1HiiHandle
,
4987 Header
->ElementSelfDescription
4990 for (LinkCount
= 0 ; LinkCount
< PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_GET_LINK_COUNT(Header
) ; LinkCount
++) {
4993 STRING_TOKEN (STR_PCI_EXT_CAP_LINK_DECLAR2
),
4994 gShellDebug1HiiHandle
,
4996 Header
->LinkEntry
[LinkCount
]
5001 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5002 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_LINK_DECLARATION
) + (PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_GET_LINK_COUNT(Header
)-1)*sizeof(UINT32
),
5003 (VOID
*) (HeaderAddress
)
5005 return (EFI_SUCCESS
);
5009 Function to interpret and print out the Advanced Error Reporting structure
5011 @param[in] HeaderAddress The Address of this capability header.
5012 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5016 PrintInterpretedExtendedCompatibilityAer (
5017 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5018 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
5021 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_ADVANCED_ERROR_REPORTING
*Header
;
5022 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_ADVANCED_ERROR_REPORTING
*)HeaderAddress
;
5026 STRING_TOKEN (STR_PCI_EXT_CAP_AER
),
5027 gShellDebug1HiiHandle
,
5028 Header
->UncorrectableErrorStatus
,
5029 Header
->UncorrectableErrorMask
,
5030 Header
->UncorrectableErrorSeverity
,
5031 Header
->CorrectableErrorStatus
,
5032 Header
->CorrectableErrorMask
,
5033 Header
->AdvancedErrorCapabilitiesAndControl
,
5035 Header
->RootErrorCommand
,
5036 Header
->RootErrorStatus
,
5037 Header
->ErrorSourceIdentification
,
5038 Header
->CorrectableErrorSourceIdentification
,
5039 Header
->TlpPrefixLog
[0],
5040 Header
->TlpPrefixLog
[1],
5041 Header
->TlpPrefixLog
[2],
5042 Header
->TlpPrefixLog
[3]
5046 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5047 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_ADVANCED_ERROR_REPORTING
),
5048 (VOID
*) (HeaderAddress
)
5050 return (EFI_SUCCESS
);
5054 Function to interpret and print out the multicast structure
5056 @param[in] HeaderAddress The Address of this capability header.
5057 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5058 @param[in] PciExpressCapPtr The address of the PCIe capabilities structure.
5062 PrintInterpretedExtendedCompatibilityMulticast (
5063 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5064 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
,
5065 IN CONST PCIE_CAP_STURCTURE
*PciExpressCapPtr
5068 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTICAST
*Header
;
5069 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTICAST
*)HeaderAddress
;
5073 STRING_TOKEN (STR_PCI_EXT_CAP_MULTICAST
),
5074 gShellDebug1HiiHandle
,
5075 Header
->MultiCastCapability
,
5076 Header
->MulticastControl
,
5077 Header
->McBaseAddress
,
5078 Header
->McReceiveAddress
,
5080 Header
->McBlockUntranslated
,
5081 Header
->McOverlayBar
5086 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5087 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTICAST
),
5088 (VOID
*) (HeaderAddress
)
5091 return (EFI_SUCCESS
);
5095 Function to interpret and print out the virtual channel and multi virtual channel structure
5097 @param[in] HeaderAddress The Address of this capability header.
5098 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5102 PrintInterpretedExtendedCompatibilityVirtualChannel (
5103 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5104 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
5107 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY
*Header
;
5108 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_VC
*CapabilityItem
;
5110 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY
*)HeaderAddress
;
5114 STRING_TOKEN (STR_PCI_EXT_CAP_VC_BASE
),
5115 gShellDebug1HiiHandle
,
5116 Header
->ExtendedVcCount
,
5117 Header
->PortVcCapability1
,
5118 Header
->PortVcCapability2
,
5119 Header
->VcArbTableOffset
,
5120 Header
->PortVcControl
,
5121 Header
->PortVcStatus
5123 for (ItemCount
= 0 ; ItemCount
< Header
->ExtendedVcCount
; ItemCount
++) {
5124 CapabilityItem
= &Header
->Capability
[ItemCount
];
5127 STRING_TOKEN (STR_PCI_EXT_CAP_VC_ITEM
),
5128 gShellDebug1HiiHandle
,
5130 CapabilityItem
->VcResourceCapability
,
5131 CapabilityItem
->PortArbTableOffset
,
5132 CapabilityItem
->VcResourceControl
,
5133 CapabilityItem
->VcResourceStatus
5139 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5140 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_VC
) + (Header
->ExtendedVcCount
- 1) * sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY
),
5141 (VOID
*) (HeaderAddress
)
5144 return (EFI_SUCCESS
);
5148 Function to interpret and print out the resizeable bar structure
5150 @param[in] HeaderAddress The Address of this capability header.
5151 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5155 PrintInterpretedExtendedCompatibilityResizeableBar (
5156 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5157 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
5160 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR
*Header
;
5162 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR
*)HeaderAddress
;
5164 for (ItemCount
= 0 ; ItemCount
< (UINT32
)GET_NUMBER_RESIZABLE_BARS(Header
) ; ItemCount
++) {
5167 STRING_TOKEN (STR_PCI_EXT_CAP_RESIZE_BAR
),
5168 gShellDebug1HiiHandle
,
5170 Header
->Capability
[ItemCount
].ResizableBarCapability
,
5171 Header
->Capability
[ItemCount
].ResizableBarControl
5177 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5178 (UINT32
)GET_NUMBER_RESIZABLE_BARS(Header
) * sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY
),
5179 (VOID
*) (HeaderAddress
)
5182 return (EFI_SUCCESS
);
5186 Function to interpret and print out the TPH structure
5188 @param[in] HeaderAddress The Address of this capability header.
5189 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5193 PrintInterpretedExtendedCompatibilityTph (
5194 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5195 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
5198 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH
*Header
;
5199 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH
*)HeaderAddress
;
5203 STRING_TOKEN (STR_PCI_EXT_CAP_TPH
),
5204 gShellDebug1HiiHandle
,
5205 Header
->TphRequesterCapability
,
5206 Header
->TphRequesterControl
5210 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)Header
->TphStTable
- (UINT8
*)HeadersBaseAddress
),
5211 GET_TPH_TABLE_SIZE(Header
),
5212 (VOID
*)Header
->TphStTable
5217 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5218 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH
) + GET_TPH_TABLE_SIZE(Header
) - sizeof(UINT16
),
5219 (VOID
*) (HeaderAddress
)
5222 return (EFI_SUCCESS
);
5226 Function to interpret and print out the secondary PCIe capability structure
5228 @param[in] HeaderAddress The Address of this capability header.
5229 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5230 @param[in] PciExpressCapPtr The address of the PCIe capabilities structure.
5234 PrintInterpretedExtendedCompatibilitySecondary (
5235 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5236 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
,
5237 IN CONST PCIE_CAP_STURCTURE
*PciExpressCapPtr
5240 CONST PCI_EXPRESS_EXTENDED_CAPABILITIES_SECONDARY_PCIE
*Header
;
5241 Header
= (PCI_EXPRESS_EXTENDED_CAPABILITIES_SECONDARY_PCIE
*)HeaderAddress
;
5245 STRING_TOKEN (STR_PCI_EXT_CAP_SECONDARY
),
5246 gShellDebug1HiiHandle
,
5247 Header
->LinkControl3
,
5248 Header
->LaneErrorStatus
5252 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)Header
->EqualizationControl
- (UINT8
*)HeadersBaseAddress
),
5253 PCIE_CAP_MAX_LINK_WIDTH(PciExpressCapPtr
->LinkCap
),
5254 (VOID
*)Header
->EqualizationControl
5259 EFI_PCIE_CAPABILITY_BASE_OFFSET
+ ((UINT8
*)HeaderAddress
- (UINT8
*)HeadersBaseAddress
),
5260 sizeof(PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH
) - sizeof(Header
->EqualizationControl
) + PCIE_CAP_MAX_LINK_WIDTH(PciExpressCapPtr
->LinkCap
),
5261 (VOID
*) (HeaderAddress
)
5264 return (EFI_SUCCESS
);
5268 Display Pcie extended capability details
5270 @param[in] HeadersBaseAddress The address of all the extended capability headers.
5271 @param[in] HeaderAddress The address of this capability header.
5272 @param[in] PciExpressCapPtr The address of the PCIe capabilities structure.
5276 PrintPciExtendedCapabilityDetails(
5277 IN CONST PCI_EXP_EXT_HDR
*HeadersBaseAddress
,
5278 IN CONST PCI_EXP_EXT_HDR
*HeaderAddress
,
5279 IN CONST PCIE_CAP_STURCTURE
*PciExpressCapPtr
5282 switch (HeaderAddress
->CapabilityId
){
5283 case PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_ID
:
5284 return PrintInterpretedExtendedCompatibilityAer(HeaderAddress
, HeadersBaseAddress
);
5285 case PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_CONTROL_ID
:
5286 return PrintInterpretedExtendedCompatibilityLinkControl(HeaderAddress
, HeadersBaseAddress
);
5287 case PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_ID
:
5288 return PrintInterpretedExtendedCompatibilityLinkDeclaration(HeaderAddress
, HeadersBaseAddress
);
5289 case PCI_EXPRESS_EXTENDED_CAPABILITY_SERIAL_NUMBER_ID
:
5290 return PrintInterpretedExtendedCompatibilitySerialNumber(HeaderAddress
, HeadersBaseAddress
);
5291 case PCI_EXPRESS_EXTENDED_CAPABILITY_POWER_BUDGETING_ID
:
5292 return PrintInterpretedExtendedCompatibilityPowerBudgeting(HeaderAddress
, HeadersBaseAddress
);
5293 case PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_ID
:
5294 return PrintInterpretedExtendedCompatibilityAcs(HeaderAddress
, HeadersBaseAddress
);
5295 case PCI_EXPRESS_EXTENDED_CAPABILITY_LATENCE_TOLERANCE_REPORTING_ID
:
5296 return PrintInterpretedExtendedCompatibilityLatencyToleranceReporting(HeaderAddress
, HeadersBaseAddress
);
5297 case PCI_EXPRESS_EXTENDED_CAPABILITY_ARI_CAPABILITY_ID
:
5298 return PrintInterpretedExtendedCompatibilityAri(HeaderAddress
, HeadersBaseAddress
);
5299 case PCI_EXPRESS_EXTENDED_CAPABILITY_RCRB_HEADER_ID
:
5300 return PrintInterpretedExtendedCompatibilityRcrb(HeaderAddress
, HeadersBaseAddress
);
5301 case PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_ID
:
5302 return PrintInterpretedExtendedCompatibilityVendorSpecific(HeaderAddress
, HeadersBaseAddress
);
5303 case PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_ID
:
5304 return PrintInterpretedExtendedCompatibilityDynamicPowerAllocation(HeaderAddress
, HeadersBaseAddress
);
5305 case PCI_EXPRESS_EXTENDED_CAPABILITY_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION_ID
:
5306 return PrintInterpretedExtendedCompatibilityECEA(HeaderAddress
, HeadersBaseAddress
);
5307 case PCI_EXPRESS_EXTENDED_CAPABILITY_VIRTUAL_CHANNEL_ID
:
5308 case PCI_EXPRESS_EXTENDED_CAPABILITY_MULTI_FUNCTION_VIRTUAL_CHANNEL_ID
:
5309 return PrintInterpretedExtendedCompatibilityVirtualChannel(HeaderAddress
, HeadersBaseAddress
);
5310 case PCI_EXPRESS_EXTENDED_CAPABILITY_MULTICAST_ID
:
5312 // should only be present if PCIE_CAP_DEVICEPORT_TYPE(PciExpressCapPtr->PcieCapReg) == 0100b, 0101b, or 0110b
5314 return PrintInterpretedExtendedCompatibilityMulticast(HeaderAddress
, HeadersBaseAddress
, PciExpressCapPtr
);
5315 case PCI_EXPRESS_EXTENDED_CAPABILITY_RESIZABLE_BAR_ID
:
5316 return PrintInterpretedExtendedCompatibilityResizeableBar(HeaderAddress
, HeadersBaseAddress
);
5317 case PCI_EXPRESS_EXTENDED_CAPABILITY_TPH_ID
:
5318 return PrintInterpretedExtendedCompatibilityTph(HeaderAddress
, HeadersBaseAddress
);
5319 case PCI_EXPRESS_EXTENDED_CAPABILITY_SECONDARY_PCIE_ID
:
5320 return PrintInterpretedExtendedCompatibilitySecondary(HeaderAddress
, HeadersBaseAddress
, PciExpressCapPtr
);
5322 ShellPrintEx (-1, -1,
5323 L
"Unknown PCIe extended capability ID (%04xh). No interpretation available.\r\n",
5324 HeaderAddress
->CapabilityId
5332 Display Pcie device structure.
5334 @param[in] IoDev The pointer to the root pci protocol.
5335 @param[in] Address The Address to start at.
5336 @param[in] CapabilityPtr The offset from the address to start.
5337 @param[in] EnhancedDump The print format for the dump data.
5341 PciExplainPciExpress (
5342 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
,
5344 IN UINT8 CapabilityPtr
,
5345 IN CONST UINT16 EnhancedDump
5349 PCIE_CAP_STURCTURE PciExpressCap
;
5351 UINT64 CapRegAddress
;
5356 UINTN ExtendRegSize
;
5357 UINT64 Pciex_Address
;
5358 UINT8 DevicePortType
;
5362 PCI_EXP_EXT_HDR
*ExtHdr
;
5364 CapRegAddress
= Address
+ CapabilityPtr
;
5369 sizeof (PciExpressCap
) / sizeof (UINT32
),
5373 DevicePortType
= (UINT8
) PCIE_CAP_DEVICEPORT_TYPE (PciExpressCap
.PcieCapReg
);
5375 ShellPrintEx (-1, -1, L
"\r\nPci Express device capability structure:\r\n");
5377 for (Index
= 0; PcieExplainList
[Index
].Type
< PcieExplainTypeMax
; Index
++) {
5378 if (ShellGetExecutionBreakFlag()) {
5381 RegAddr
= ((UINT8
*) &PciExpressCap
) + PcieExplainList
[Index
].Offset
;
5382 switch (PcieExplainList
[Index
].Width
) {
5383 case FieldWidthUINT8
:
5384 RegValue
= *(UINT8
*) RegAddr
;
5386 case FieldWidthUINT16
:
5387 RegValue
= *(UINT16
*) RegAddr
;
5389 case FieldWidthUINT32
:
5390 RegValue
= *(UINT32
*) RegAddr
;
5396 ShellPrintHiiEx(-1, -1, NULL
,
5397 PcieExplainList
[Index
].Token
,
5398 gShellDebug1HiiHandle
,
5399 PcieExplainList
[Index
].Offset
,
5402 if (PcieExplainList
[Index
].Func
== NULL
) {
5405 switch (PcieExplainList
[Index
].Type
) {
5406 case PcieExplainTypeLink
:
5408 // Link registers should not be used by
5409 // a) Root Complex Integrated Endpoint
5410 // b) Root Complex Event Collector
5412 if (DevicePortType
== PCIE_ROOT_COMPLEX_INTEGRATED_PORT
||
5413 DevicePortType
== PCIE_ROOT_COMPLEX_EVENT_COLLECTOR
) {
5417 case PcieExplainTypeSlot
:
5419 // Slot registers are only valid for
5420 // a) Root Port of PCI Express Root Complex
5421 // b) Downstream Port of PCI Express Switch
5422 // and when SlotImplemented bit is set in PCIE cap register.
5424 if ((DevicePortType
!= PCIE_ROOT_COMPLEX_ROOT_PORT
&&
5425 DevicePortType
!= PCIE_SWITCH_DOWNSTREAM_PORT
) ||
5426 !PCIE_CAP_SLOT_IMPLEMENTED (PciExpressCap
.PcieCapReg
)) {
5430 case PcieExplainTypeRoot
:
5432 // Root registers are only valid for
5433 // Root Port of PCI Express Root Complex
5435 if (DevicePortType
!= PCIE_ROOT_COMPLEX_ROOT_PORT
) {
5442 PcieExplainList
[Index
].Func (&PciExpressCap
);
5445 Bus
= (UINT8
) (RShiftU64 (Address
, 24));
5446 Dev
= (UINT8
) (RShiftU64 (Address
, 16));
5447 Func
= (UINT8
) (RShiftU64 (Address
, 8));
5449 Pciex_Address
= CALC_EFI_PCIEX_ADDRESS (Bus
, Dev
, Func
, EFI_PCIE_CAPABILITY_BASE_OFFSET
);
5451 ExtendRegSize
= 0x1000 - EFI_PCIE_CAPABILITY_BASE_OFFSET
;
5453 ExRegBuffer
= (UINT8
*) AllocateZeroPool (ExtendRegSize
);
5456 // PciRootBridgeIo protocol should support pci express extend space IO
5457 // (Begins at offset EFI_PCIE_CAPABILITY_BASE_OFFSET)
5459 Status
= IoDev
->Pci
.Read (
5463 (ExtendRegSize
) / sizeof (UINT32
),
5464 (VOID
*) (ExRegBuffer
)
5466 if (EFI_ERROR (Status
) || ExRegBuffer
== NULL
) {
5467 SHELL_FREE_NON_NULL(ExRegBuffer
);
5468 return EFI_UNSUPPORTED
;
5471 if (EnhancedDump
== 0) {
5473 // Print the PciEx extend space in raw bytes ( 0xFF-0xFFF)
5475 ShellPrintEx (-1, -1, L
"\r\n%HStart dumping PCIex extended configuration space (0x100 - 0xFFF).%N\r\n\r\n");
5479 EFI_PCIE_CAPABILITY_BASE_OFFSET
,
5481 (VOID
*) (ExRegBuffer
)
5484 ExtHdr
= (PCI_EXP_EXT_HDR
*)ExRegBuffer
;
5485 while (ExtHdr
->CapabilityId
!= 0 && ExtHdr
->CapabilityVersion
!= 0) {
5487 // Process this item
5489 if (EnhancedDump
== 0xFFFF || EnhancedDump
== ExtHdr
->CapabilityId
) {
5493 PrintPciExtendedCapabilityDetails((PCI_EXP_EXT_HDR
*)ExRegBuffer
, ExtHdr
, &PciExpressCap
);
5497 // Advance to the next item if it exists
5499 if (ExtHdr
->NextCapabilityOffset
!= 0) {
5500 ExtHdr
= (PCI_EXP_EXT_HDR
*)((UINT8
*)ExRegBuffer
+ ExtHdr
->NextCapabilityOffset
);
5506 SHELL_FREE_NON_NULL(ExRegBuffer
);