2 Main file for Pci shell Debug1 function.
4 Copyright (c) 2005 - 2011, Intel Corporation. All rights reserved.<BR>
5 This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
15 #include "UefiShellDebug1CommandsLib.h"
16 #include <Protocol/PciRootBridgeIo.h>
17 #include <Library/ShellLib.h>
18 #include <IndustryStandard/Pci.h>
19 #include <IndustryStandard/Acpi.h>
22 #define PCI_CLASS_STRING_LIMIT 54
24 // Printable strings for Pci class code
27 CHAR16
*BaseClass
; // Pointer to the PCI base class string
28 CHAR16
*SubClass
; // Pointer to the PCI sub class string
29 CHAR16
*PIFClass
; // Pointer to the PCI programming interface string
33 // a structure holding a single entry, which also points to its lower level
36 typedef struct PCI_CLASS_ENTRY_TAG
{
37 UINT8 Code
; // Class, subclass or I/F code
38 CHAR16
*DescText
; // Description string
39 struct PCI_CLASS_ENTRY_TAG
*LowerLevelClass
; // Subclass or I/F if any
43 // Declarations of entries which contain printable strings for class codes
44 // in PCI configuration space
46 PCI_CLASS_ENTRY PCIBlankEntry
[];
47 PCI_CLASS_ENTRY PCISubClass_00
[];
48 PCI_CLASS_ENTRY PCISubClass_01
[];
49 PCI_CLASS_ENTRY PCISubClass_02
[];
50 PCI_CLASS_ENTRY PCISubClass_03
[];
51 PCI_CLASS_ENTRY PCISubClass_04
[];
52 PCI_CLASS_ENTRY PCISubClass_05
[];
53 PCI_CLASS_ENTRY PCISubClass_06
[];
54 PCI_CLASS_ENTRY PCISubClass_07
[];
55 PCI_CLASS_ENTRY PCISubClass_08
[];
56 PCI_CLASS_ENTRY PCISubClass_09
[];
57 PCI_CLASS_ENTRY PCISubClass_0a
[];
58 PCI_CLASS_ENTRY PCISubClass_0b
[];
59 PCI_CLASS_ENTRY PCISubClass_0c
[];
60 PCI_CLASS_ENTRY PCISubClass_0d
[];
61 PCI_CLASS_ENTRY PCISubClass_0e
[];
62 PCI_CLASS_ENTRY PCISubClass_0f
[];
63 PCI_CLASS_ENTRY PCISubClass_10
[];
64 PCI_CLASS_ENTRY PCISubClass_11
[];
65 PCI_CLASS_ENTRY PCIPIFClass_0101
[];
66 PCI_CLASS_ENTRY PCIPIFClass_0300
[];
67 PCI_CLASS_ENTRY PCIPIFClass_0604
[];
68 PCI_CLASS_ENTRY PCIPIFClass_0700
[];
69 PCI_CLASS_ENTRY PCIPIFClass_0701
[];
70 PCI_CLASS_ENTRY PCIPIFClass_0703
[];
71 PCI_CLASS_ENTRY PCIPIFClass_0800
[];
72 PCI_CLASS_ENTRY PCIPIFClass_0801
[];
73 PCI_CLASS_ENTRY PCIPIFClass_0802
[];
74 PCI_CLASS_ENTRY PCIPIFClass_0803
[];
75 PCI_CLASS_ENTRY PCIPIFClass_0904
[];
76 PCI_CLASS_ENTRY PCIPIFClass_0c00
[];
77 PCI_CLASS_ENTRY PCIPIFClass_0c03
[];
78 PCI_CLASS_ENTRY PCIPIFClass_0e00
[];
81 // Base class strings entries
83 PCI_CLASS_ENTRY gClassStringList
[] = {
91 L
"Mass Storage Controller",
96 L
"Network Controller",
101 L
"Display Controller",
106 L
"Multimedia Device",
111 L
"Memory Controller",
121 L
"Simple Communications Controllers",
126 L
"Base System Peripherals",
146 L
"Serial Bus Controllers",
151 L
"Wireless Controllers",
156 L
"Intelligent IO Controllers",
161 L
"Satellite Communications Controllers",
166 L
"Encryption/Decryption Controllers",
171 L
"Data Acquisition & Signal Processing Controllers",
176 L
"Device does not fit in any defined classes",
182 /* null string ends the list */NULL
187 // Subclass strings entries
189 PCI_CLASS_ENTRY PCIBlankEntry
[] = {
198 /* null string ends the list */NULL
202 PCI_CLASS_ENTRY PCISubClass_00
[] = {
205 L
"All devices other than VGA",
210 L
"VGA-compatible devices",
216 /* null string ends the list */NULL
220 PCI_CLASS_ENTRY PCISubClass_01
[] = {
233 L
"Floppy disk controller",
248 L
"Other mass storage controller",
254 /* null string ends the list */NULL
258 PCI_CLASS_ENTRY PCISubClass_02
[] = {
261 L
"Ethernet controller",
266 L
"Token ring controller",
286 L
"Other network controller",
292 /* null string ends the list */NULL
296 PCI_CLASS_ENTRY PCISubClass_03
[] = {
299 L
"VGA/8514 controller",
314 L
"Other display controller",
320 /* null string ends the list */PCIBlankEntry
324 PCI_CLASS_ENTRY PCISubClass_04
[] = {
337 L
"Computer Telephony device",
342 L
"Other multimedia device",
348 /* null string ends the list */NULL
352 PCI_CLASS_ENTRY PCISubClass_05
[] = {
355 L
"RAM memory controller",
360 L
"Flash memory controller",
365 L
"Other memory controller",
371 /* null string ends the list */NULL
375 PCI_CLASS_ENTRY PCISubClass_06
[] = {
393 L
"PCI/Micro Channel bridge",
403 L
"PCI/PCMCIA bridge",
423 L
"Other bridge type",
429 /* null string ends the list */NULL
433 PCI_CLASS_ENTRY PCISubClass_07
[] = {
436 L
"Serial controller",
446 L
"Multiport serial controller",
456 L
"Other communication device",
462 /* null string ends the list */NULL
466 PCI_CLASS_ENTRY PCISubClass_08
[] = {
489 L
"Generic PCI Hot-Plug controller",
494 L
"Other system peripheral",
500 /* null string ends the list */NULL
504 PCI_CLASS_ENTRY PCISubClass_09
[] = {
507 L
"Keyboard controller",
522 L
"Scanner controller",
527 L
"Gameport controller",
532 L
"Other input controller",
538 /* null string ends the list */NULL
542 PCI_CLASS_ENTRY PCISubClass_0a
[] = {
545 L
"Generic docking station",
550 L
"Other type of docking station",
556 /* null string ends the list */NULL
560 PCI_CLASS_ENTRY PCISubClass_0b
[] = {
604 /* null string ends the list */NULL
608 PCI_CLASS_ENTRY PCISubClass_0c
[] = {
611 L
"Firewire(IEEE 1394)",
636 L
"System Management Bus",
647 /* null string ends the list */NULL
651 PCI_CLASS_ENTRY PCISubClass_0d
[] = {
654 L
"iRDA compatible controller",
659 L
"Consumer IR controller",
669 L
"Other type of wireless controller",
675 /* null string ends the list */NULL
679 PCI_CLASS_ENTRY PCISubClass_0e
[] = {
688 /* null string ends the list */NULL
692 PCI_CLASS_ENTRY PCISubClass_0f
[] = {
716 /* null string ends the list */NULL
720 PCI_CLASS_ENTRY PCISubClass_10
[] = {
723 L
"Network & computing Encrypt/Decrypt",
728 L
"Entertainment Encrypt/Decrypt",
733 L
"Other Encrypt/Decrypt",
739 /* null string ends the list */NULL
743 PCI_CLASS_ENTRY PCISubClass_11
[] = {
751 L
"Other DAQ & SP controllers",
757 /* null string ends the list */NULL
762 // Programming Interface entries
764 PCI_CLASS_ENTRY PCIPIFClass_0101
[] = {
792 L
"OM-primary, OM-secondary",
797 L
"PI-primary, OM-secondary",
802 L
"OM/PI-primary, OM-secondary",
812 L
"OM-primary, PI-secondary",
817 L
"PI-primary, PI-secondary",
822 L
"OM/PI-primary, PI-secondary",
832 L
"OM-primary, OM/PI-secondary",
837 L
"PI-primary, OM/PI-secondary",
842 L
"OM/PI-primary, OM/PI-secondary",
852 L
"Master, OM-primary",
857 L
"Master, PI-primary",
862 L
"Master, OM/PI-primary",
867 L
"Master, OM-secondary",
872 L
"Master, OM-primary, OM-secondary",
877 L
"Master, PI-primary, OM-secondary",
882 L
"Master, OM/PI-primary, OM-secondary",
887 L
"Master, OM-secondary",
892 L
"Master, OM-primary, PI-secondary",
897 L
"Master, PI-primary, PI-secondary",
902 L
"Master, OM/PI-primary, PI-secondary",
907 L
"Master, OM-secondary",
912 L
"Master, OM-primary, OM/PI-secondary",
917 L
"Master, PI-primary, OM/PI-secondary",
922 L
"Master, OM/PI-primary, OM/PI-secondary",
928 /* null string ends the list */NULL
932 PCI_CLASS_ENTRY PCIPIFClass_0300
[] = {
946 /* null string ends the list */NULL
950 PCI_CLASS_ENTRY PCIPIFClass_0604
[] = {
958 L
"Subtractive decode",
964 /* null string ends the list */NULL
968 PCI_CLASS_ENTRY PCIPIFClass_0700
[] = {
971 L
"Generic XT-compatible",
1001 L
"16950-compatible",
1007 /* null string ends the list */NULL
1011 PCI_CLASS_ENTRY PCIPIFClass_0701
[] = {
1024 L
"ECP 1.X-compliant",
1034 L
"IEEE 1284 target (not a controller)",
1040 /* null string ends the list */NULL
1044 PCI_CLASS_ENTRY PCIPIFClass_0703
[] = {
1052 L
"Hayes-compatible 16450",
1057 L
"Hayes-compatible 16550",
1062 L
"Hayes-compatible 16650",
1067 L
"Hayes-compatible 16750",
1073 /* null string ends the list */NULL
1077 PCI_CLASS_ENTRY PCIPIFClass_0800
[] = {
1100 L
"IO(x) APIC interrupt controller",
1106 /* null string ends the list */NULL
1110 PCI_CLASS_ENTRY PCIPIFClass_0801
[] = {
1129 /* null string ends the list */NULL
1133 PCI_CLASS_ENTRY PCIPIFClass_0802
[] = {
1152 /* null string ends the list */NULL
1156 PCI_CLASS_ENTRY PCIPIFClass_0803
[] = {
1175 /* null string ends the list */NULL
1179 PCI_CLASS_ENTRY PCIPIFClass_0904
[] = {
1193 /* null string ends the list */NULL
1197 PCI_CLASS_ENTRY PCIPIFClass_0c00
[] = {
1200 L
"Universal Host Controller spec",
1205 L
"Open Host Controller spec",
1210 L
"No specific programming interface",
1215 L
"(Not Host Controller)",
1221 /* null string ends the list */NULL
1225 PCI_CLASS_ENTRY PCIPIFClass_0c03
[] = {
1233 L
"Using 1394 OpenHCI spec",
1239 /* null string ends the list */NULL
1243 PCI_CLASS_ENTRY PCIPIFClass_0e00
[] = {
1246 L
"Message FIFO at offset 40h",
1257 /* null string ends the list */NULL
1263 Generates printable Unicode strings that represent PCI device class,
1264 subclass and programmed I/F based on a value passed to the function.
1266 @param[in] ClassCode Value representing the PCI "Class Code" register read from a
1267 PCI device. The encodings are:
1268 bits 23:16 - Base Class Code
1269 bits 15:8 - Sub-Class Code
1270 bits 7:0 - Programming Interface
1271 @param[in, out] ClassStrings Pointer of PCI_CLASS_STRINGS structure, which contains
1272 printable class strings corresponding to ClassCode. The
1273 caller must not modify the strings that are pointed by
1274 the fields in ClassStrings.
1277 PciGetClassStrings (
1278 IN UINT32 ClassCode
,
1279 IN OUT PCI_CLASS_STRINGS
*ClassStrings
1284 PCI_CLASS_ENTRY
*CurrentClass
;
1287 // Assume no strings found
1289 ClassStrings
->BaseClass
= L
"UNDEFINED";
1290 ClassStrings
->SubClass
= L
"UNDEFINED";
1291 ClassStrings
->PIFClass
= L
"UNDEFINED";
1293 CurrentClass
= gClassStringList
;
1294 Code
= (UINT8
) (ClassCode
>> 16);
1298 // Go through all entries of the base class, until the entry with a matching
1299 // base class code is found. If reaches an entry with a null description
1300 // text, the last entry is met, which means no text for the base class was
1301 // found, so no more action is needed.
1303 while (Code
!= CurrentClass
[Index
].Code
) {
1304 if (NULL
== CurrentClass
[Index
].DescText
) {
1311 // A base class was found. Assign description, and check if this class has
1312 // sub-class defined. If sub-class defined, no more action is needed,
1313 // otherwise, continue to find description for the sub-class code.
1315 ClassStrings
->BaseClass
= CurrentClass
[Index
].DescText
;
1316 if (NULL
== CurrentClass
[Index
].LowerLevelClass
) {
1320 // find Subclass entry
1322 CurrentClass
= CurrentClass
[Index
].LowerLevelClass
;
1323 Code
= (UINT8
) (ClassCode
>> 8);
1327 // Go through all entries of the sub-class, until the entry with a matching
1328 // sub-class code is found. If reaches an entry with a null description
1329 // text, the last entry is met, which means no text for the sub-class was
1330 // found, so no more action is needed.
1332 while (Code
!= CurrentClass
[Index
].Code
) {
1333 if (NULL
== CurrentClass
[Index
].DescText
) {
1340 // A class was found for the sub-class code. Assign description, and check if
1341 // this sub-class has programming interface defined. If no, no more action is
1342 // needed, otherwise, continue to find description for the programming
1345 ClassStrings
->SubClass
= CurrentClass
[Index
].DescText
;
1346 if (NULL
== CurrentClass
[Index
].LowerLevelClass
) {
1350 // Find programming interface entry
1352 CurrentClass
= CurrentClass
[Index
].LowerLevelClass
;
1353 Code
= (UINT8
) ClassCode
;
1357 // Go through all entries of the I/F entries, until the entry with a
1358 // matching I/F code is found. If reaches an entry with a null description
1359 // text, the last entry is met, which means no text was found, so no more
1360 // action is needed.
1362 while (Code
!= CurrentClass
[Index
].Code
) {
1363 if (NULL
== CurrentClass
[Index
].DescText
) {
1370 // A class was found for the I/F code. Assign description, done!
1372 ClassStrings
->PIFClass
= CurrentClass
[Index
].DescText
;
1377 Print strings that represent PCI device class, subclass and programmed I/F.
1379 @param[in] ClassCodePtr Points to the memory which stores register Class Code in PCI
1381 @param[in] IncludePIF If the printed string should include the programming I/F part
1385 IN UINT8
*ClassCodePtr
,
1386 IN BOOLEAN IncludePIF
1390 PCI_CLASS_STRINGS ClassStrings
;
1391 CHAR16 OutputString
[PCI_CLASS_STRING_LIMIT
+ 1];
1394 ClassCode
|= ClassCodePtr
[0];
1395 ClassCode
|= (ClassCodePtr
[1] << 8);
1396 ClassCode
|= (ClassCodePtr
[2] << 16);
1399 // Get name from class code
1401 PciGetClassStrings (ClassCode
, &ClassStrings
);
1405 // Only print base class and sub class name
1407 ShellPrintEx(-1,-1, L
"%s - %s - %s",
1408 ClassStrings
.BaseClass
,
1409 ClassStrings
.SubClass
,
1410 ClassStrings
.PIFClass
1415 // Print base class, sub class, and programming inferface name
1419 PCI_CLASS_STRING_LIMIT
* sizeof (CHAR16
),
1421 ClassStrings
.BaseClass
,
1422 ClassStrings
.SubClass
1425 OutputString
[PCI_CLASS_STRING_LIMIT
] = 0;
1426 ShellPrintEx(-1,-1, L
"%s", OutputString
);
1431 This function finds out the protocol which is in charge of the given
1432 segment, and its bus range covers the current bus number. It lookes
1433 each instances of RootBridgeIoProtocol handle, until the one meets the
1436 @param[in] HandleBuf Buffer which holds all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.
1437 @param[in] HandleCount Count of all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.
1438 @param[in] Segment Segment number of device we are dealing with.
1439 @param[in] Bus Bus number of device we are dealing with.
1440 @param[out] IoDev Handle used to access configuration space of PCI device.
1442 @retval EFI_SUCCESS The command completed successfully.
1443 @retval EFI_INVALID_PARAMETER Invalid parameter.
1447 PciFindProtocolInterface (
1448 IN EFI_HANDLE
*HandleBuf
,
1449 IN UINTN HandleCount
,
1452 OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
**IoDev
1456 This function gets the protocol interface from the given handle, and
1457 obtains its address space descriptors.
1459 @param[in] Handle The PCI_ROOT_BRIDIGE_IO_PROTOCOL handle.
1460 @param[out] IoDev Handle used to access configuration space of PCI device.
1461 @param[out] Descriptors Points to the address space descriptors.
1463 @retval EFI_SUCCESS The command completed successfully
1466 PciGetProtocolAndResource (
1467 IN EFI_HANDLE Handle
,
1468 OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
**IoDev
,
1469 OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
**Descriptors
1473 This function get the next bus range of given address space descriptors.
1474 It also moves the pointer backward a node, to get prepared to be called
1477 @param[in, out] Descriptors Points to current position of a serial of address space
1479 @param[out] MinBus The lower range of bus number.
1480 @param[out] MaxBus The upper range of bus number.
1481 @param[out] IsEnd Meet end of the serial of descriptors.
1483 @retval EFI_SUCCESS The command completed successfully.
1486 PciGetNextBusRange (
1487 IN OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
**Descriptors
,
1494 Explain the data in PCI configuration space. The part which is common for
1495 PCI device and bridge is interpreted in this function. It calls other
1496 functions to interpret data unique for device or bridge.
1498 @param[in] ConfigSpace Data in PCI configuration space.
1499 @param[in] Address Address used to access configuration space of this PCI device.
1500 @param[in] IoDev Handle used to access configuration space of PCI device.
1502 @retval EFI_SUCCESS The command completed successfully.
1506 IN PCI_CONFIG_SPACE
*ConfigSpace
,
1508 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
1512 Explain the device specific part of data in PCI configuration space.
1514 @param[in] Device Data in PCI configuration space.
1515 @param[in] Address Address used to access configuration space of this PCI device.
1516 @param[in] IoDev Handle used to access configuration space of PCI device.
1518 @retval EFI_SUCCESS The command completed successfully.
1521 PciExplainDeviceData (
1522 IN PCI_DEVICE_HEADER
*Device
,
1524 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
1528 Explain the bridge specific part of data in PCI configuration space.
1530 @param[in] Bridge Bridge specific data region in PCI configuration space.
1531 @param[in] Address Address used to access configuration space of this PCI device.
1532 @param[in] IoDev Handle used to access configuration space of PCI device.
1534 @retval EFI_SUCCESS The command completed successfully.
1537 PciExplainBridgeData (
1538 IN PCI_BRIDGE_HEADER
*Bridge
,
1540 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
1544 Explain the Base Address Register(Bar) in PCI configuration space.
1546 @param[in] Bar Points to the Base Address Register intended to interpret.
1547 @param[in] Command Points to the register Command.
1548 @param[in] Address Address used to access configuration space of this PCI device.
1549 @param[in] IoDev Handle used to access configuration space of PCI device.
1550 @param[in, out] Index The Index.
1552 @retval EFI_SUCCESS The command completed successfully.
1559 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
,
1564 Explain the cardbus specific part of data in PCI configuration space.
1566 @param[in] CardBus CardBus specific region of PCI configuration space.
1567 @param[in] Address Address used to access configuration space of this PCI device.
1568 @param[in] IoDev Handle used to access configuration space of PCI device.
1570 @retval EFI_SUCCESS The command completed successfully.
1573 PciExplainCardBusData (
1574 IN PCI_CARDBUS_HEADER
*CardBus
,
1576 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
1580 Explain each meaningful bit of register Status. The definition of Status is
1581 slightly different depending on the PCI header type.
1583 @param[in] Status Points to the content of register Status.
1584 @param[in] MainStatus Indicates if this register is main status(not secondary
1586 @param[in] HeaderType Header type of this PCI device.
1588 @retval EFI_SUCCESS The command completed successfully.
1593 IN BOOLEAN MainStatus
,
1594 IN PCI_HEADER_TYPE HeaderType
1598 Explain each meaningful bit of register Command.
1600 @param[in] Command Points to the content of register Command.
1602 @retval EFI_SUCCESS The command completed successfully.
1610 Explain each meaningful bit of register Bridge Control.
1612 @param[in] BridgeControl Points to the content of register Bridge Control.
1613 @param[in] HeaderType The headertype.
1615 @retval EFI_SUCCESS The command completed successfully.
1618 PciExplainBridgeControl (
1619 IN UINT16
*BridgeControl
,
1620 IN PCI_HEADER_TYPE HeaderType
1624 Print each capability structure.
1626 @param[in] IoDev The pointer to the deivce.
1627 @param[in] Address The address to start at.
1628 @param[in] CapPtr The offset from the address.
1630 @retval EFI_SUCCESS The operation was successful.
1633 PciExplainCapabilityStruct (
1634 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
,
1640 Display Pcie device structure.
1642 @param[in] IoDev The pointer to the root pci protocol.
1643 @param[in] Address The Address to start at.
1644 @param[in] CapabilityPtr The offset from the address to start.
1647 PciExplainPciExpress (
1648 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
,
1650 IN UINT8 CapabilityPtr
1654 Print out information of the capability information.
1656 @param[in] PciExpressCap The pointer to the structure about the device.
1658 @retval EFI_SUCCESS The operation was successful.
1662 IN PCIE_CAP_STURCTURE
*PciExpressCap
1666 Print out information of the device capability information.
1668 @param[in] PciExpressCap The pointer to the structure about the device.
1670 @retval EFI_SUCCESS The operation was successful.
1673 ExplainPcieDeviceCap (
1674 IN PCIE_CAP_STURCTURE
*PciExpressCap
1678 Print out information of the device control information.
1680 @param[in] PciExpressCap The pointer to the structure about the device.
1682 @retval EFI_SUCCESS The operation was successful.
1685 ExplainPcieDeviceControl (
1686 IN PCIE_CAP_STURCTURE
*PciExpressCap
1690 Print out information of the device status information.
1692 @param[in] PciExpressCap The pointer to the structure about the device.
1694 @retval EFI_SUCCESS The operation was successful.
1697 ExplainPcieDeviceStatus (
1698 IN PCIE_CAP_STURCTURE
*PciExpressCap
1702 Print out information of the device link information.
1704 @param[in] PciExpressCap The pointer to the structure about the device.
1706 @retval EFI_SUCCESS The operation was successful.
1709 ExplainPcieLinkCap (
1710 IN PCIE_CAP_STURCTURE
*PciExpressCap
1714 Print out information of the device link control information.
1716 @param[in] PciExpressCap The pointer to the structure about the device.
1718 @retval EFI_SUCCESS The operation was successful.
1721 ExplainPcieLinkControl (
1722 IN PCIE_CAP_STURCTURE
*PciExpressCap
1726 Print out information of the device link status information.
1728 @param[in] PciExpressCap The pointer to the structure about the device.
1730 @retval EFI_SUCCESS The operation was successful.
1733 ExplainPcieLinkStatus (
1734 IN PCIE_CAP_STURCTURE
*PciExpressCap
1738 Print out information of the device slot information.
1740 @param[in] PciExpressCap The pointer to the structure about the device.
1742 @retval EFI_SUCCESS The operation was successful.
1745 ExplainPcieSlotCap (
1746 IN PCIE_CAP_STURCTURE
*PciExpressCap
1750 Print out information of the device slot control information.
1752 @param[in] PciExpressCap The pointer to the structure about the device.
1754 @retval EFI_SUCCESS The operation was successful.
1757 ExplainPcieSlotControl (
1758 IN PCIE_CAP_STURCTURE
*PciExpressCap
1762 Print out information of the device slot status information.
1764 @param[in] PciExpressCap The pointer to the structure about the device.
1766 @retval EFI_SUCCESS The operation was successful.
1769 ExplainPcieSlotStatus (
1770 IN PCIE_CAP_STURCTURE
*PciExpressCap
1774 Print out information of the device root information.
1776 @param[in] PciExpressCap The pointer to the structure about the device.
1778 @retval EFI_SUCCESS The operation was successful.
1781 ExplainPcieRootControl (
1782 IN PCIE_CAP_STURCTURE
*PciExpressCap
1786 Print out information of the device root capability information.
1788 @param[in] PciExpressCap The pointer to the structure about the device.
1790 @retval EFI_SUCCESS The operation was successful.
1793 ExplainPcieRootCap (
1794 IN PCIE_CAP_STURCTURE
*PciExpressCap
1798 Print out information of the device root status information.
1800 @param[in] PciExpressCap The pointer to the structure about the device.
1802 @retval EFI_SUCCESS The operation was successful.
1805 ExplainPcieRootStatus (
1806 IN PCIE_CAP_STURCTURE
*PciExpressCap
1809 typedef EFI_STATUS (*PCIE_EXPLAIN_FUNCTION
) (IN PCIE_CAP_STURCTURE
*PciExpressCap
);
1815 } PCIE_CAPREG_FIELD_WIDTH
;
1818 PcieExplainTypeCommon
,
1819 PcieExplainTypeDevice
,
1820 PcieExplainTypeLink
,
1821 PcieExplainTypeSlot
,
1822 PcieExplainTypeRoot
,
1824 } PCIE_EXPLAIN_TYPE
;
1830 PCIE_CAPREG_FIELD_WIDTH Width
;
1831 PCIE_EXPLAIN_FUNCTION Func
;
1832 PCIE_EXPLAIN_TYPE Type
;
1833 } PCIE_EXPLAIN_STRUCT
;
1835 PCIE_EXPLAIN_STRUCT PcieExplainList
[] = {
1837 STRING_TOKEN (STR_PCIEX_CAPABILITY_CAPID
),
1841 PcieExplainTypeCommon
1844 STRING_TOKEN (STR_PCIEX_NEXTCAP_PTR
),
1848 PcieExplainTypeCommon
1851 STRING_TOKEN (STR_PCIEX_CAP_REGISTER
),
1855 PcieExplainTypeCommon
1858 STRING_TOKEN (STR_PCIEX_DEVICE_CAP
),
1861 ExplainPcieDeviceCap
,
1862 PcieExplainTypeDevice
1865 STRING_TOKEN (STR_PCIEX_DEVICE_CONTROL
),
1868 ExplainPcieDeviceControl
,
1869 PcieExplainTypeDevice
1872 STRING_TOKEN (STR_PCIEX_DEVICE_STATUS
),
1875 ExplainPcieDeviceStatus
,
1876 PcieExplainTypeDevice
1879 STRING_TOKEN (STR_PCIEX_LINK_CAPABILITIES
),
1886 STRING_TOKEN (STR_PCIEX_LINK_CONTROL
),
1889 ExplainPcieLinkControl
,
1893 STRING_TOKEN (STR_PCIEX_LINK_STATUS
),
1896 ExplainPcieLinkStatus
,
1900 STRING_TOKEN (STR_PCIEX_SLOT_CAPABILITIES
),
1907 STRING_TOKEN (STR_PCIEX_SLOT_CONTROL
),
1910 ExplainPcieSlotControl
,
1914 STRING_TOKEN (STR_PCIEX_SLOT_STATUS
),
1917 ExplainPcieSlotStatus
,
1921 STRING_TOKEN (STR_PCIEX_ROOT_CONTROL
),
1924 ExplainPcieRootControl
,
1928 STRING_TOKEN (STR_PCIEX_RSVDP
),
1935 STRING_TOKEN (STR_PCIEX_ROOT_STATUS
),
1938 ExplainPcieRootStatus
,
1944 (PCIE_CAPREG_FIELD_WIDTH
)0,
1953 PCI_CONFIG_SPACE
*mConfigSpace
= NULL
;
1954 STATIC CONST SHELL_PARAM_ITEM ParamList
[] = {
1960 CHAR16
*DevicePortTypeTable
[] = {
1961 L
"PCI Express Endpoint",
1962 L
"Legacy PCI Express Endpoint",
1965 L
"Root Port of PCI Express Root Complex",
1966 L
"Upstream Port of PCI Express Switch",
1967 L
"Downstream Port of PCI Express Switch",
1968 L
"PCI Express to PCI/PCI-X Bridge",
1969 L
"PCI/PCI-X to PCI Express Bridge",
1970 L
"Root Complex Integrated Endpoint",
1971 L
"Root Complex Event Collector"
1974 CHAR16
*L0sLatencyStrTable
[] = {
1976 L
"64ns to less than 128ns",
1977 L
"128ns to less than 256ns",
1978 L
"256ns to less than 512ns",
1979 L
"512ns to less than 1us",
1980 L
"1us to less than 2us",
1985 CHAR16
*L1LatencyStrTable
[] = {
1987 L
"1us to less than 2us",
1988 L
"2us to less than 4us",
1989 L
"4us to less than 8us",
1990 L
"8us to less than 16us",
1991 L
"16us to less than 32us",
1996 CHAR16
*ASPMCtrlStrTable
[] = {
1998 L
"L0s Entry Enabled",
1999 L
"L1 Entry Enabled",
2000 L
"L0s and L1 Entry Enabled"
2003 CHAR16
*SlotPwrLmtScaleTable
[] = {
2010 CHAR16
*IndicatorTable
[] = {
2019 Function for 'pci' command.
2021 @param[in] ImageHandle Handle to the Image (NULL if Internal).
2022 @param[in] SystemTable Pointer to the System Table (NULL if Internal).
2026 ShellCommandRunPci (
2027 IN EFI_HANDLE ImageHandle
,
2028 IN EFI_SYSTEM_TABLE
*SystemTable
2036 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
;
2038 PCI_COMMON_HEADER PciHeader
;
2039 PCI_CONFIG_SPACE ConfigSpace
;
2043 BOOLEAN ExplainData
;
2047 UINTN HandleBufSize
;
2048 EFI_HANDLE
*HandleBuf
;
2050 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
*Descriptors
;
2054 LIST_ENTRY
*Package
;
2055 CHAR16
*ProblemParam
;
2056 SHELL_STATUS ShellStatus
;
2059 ShellStatus
= SHELL_SUCCESS
;
2060 Status
= EFI_SUCCESS
;
2067 // initialize the shell lib (we must be in non-auto-init...)
2069 Status
= ShellInitialize();
2070 ASSERT_EFI_ERROR(Status
);
2072 Status
= CommandInit();
2073 ASSERT_EFI_ERROR(Status
);
2076 // parse the command line
2078 Status
= ShellCommandLineParse (ParamList
, &Package
, &ProblemParam
, TRUE
);
2079 if (EFI_ERROR(Status
)) {
2080 if (Status
== EFI_VOLUME_CORRUPTED
&& ProblemParam
!= NULL
) {
2081 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_GEN_PROBLEM
), gShellDebug1HiiHandle
, ProblemParam
);
2082 FreePool(ProblemParam
);
2083 ShellStatus
= SHELL_INVALID_PARAMETER
;
2089 if (ShellCommandLineGetCount(Package
) == 2) {
2090 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_GEN_TOO_FEW
), gShellDebug1HiiHandle
);
2091 ShellStatus
= SHELL_INVALID_PARAMETER
;
2095 if (ShellCommandLineGetCount(Package
) > 4) {
2096 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_GEN_TOO_MANY
), gShellDebug1HiiHandle
);
2097 ShellStatus
= SHELL_INVALID_PARAMETER
;
2100 if (ShellCommandLineGetFlag(Package
, L
"-s") && ShellCommandLineGetValue(Package
, L
"-s") == NULL
) {
2101 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_GEN_NO_VALUE
), gShellDebug1HiiHandle
, L
"-s");
2102 ShellStatus
= SHELL_INVALID_PARAMETER
;
2106 // Get all instances of PciRootBridgeIo. Allocate space for 1 EFI_HANDLE and
2107 // call LibLocateHandle(), if EFI_BUFFER_TOO_SMALL is returned, allocate enough
2108 // space for handles and call it again.
2110 HandleBufSize
= sizeof (EFI_HANDLE
);
2111 HandleBuf
= (EFI_HANDLE
*) AllocateZeroPool (HandleBufSize
);
2112 if (HandleBuf
== NULL
) {
2113 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_GEN_OUT_MEM
), gShellDebug1HiiHandle
);
2114 ShellStatus
= SHELL_OUT_OF_RESOURCES
;
2118 Status
= gBS
->LocateHandle (
2120 &gEfiPciRootBridgeIoProtocolGuid
,
2126 if (Status
== EFI_BUFFER_TOO_SMALL
) {
2127 HandleBuf
= ReallocatePool (sizeof (EFI_HANDLE
), HandleBufSize
, HandleBuf
);
2128 if (HandleBuf
== NULL
) {
2129 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_GEN_OUT_MEM
), gShellDebug1HiiHandle
);
2130 ShellStatus
= SHELL_OUT_OF_RESOURCES
;
2134 Status
= gBS
->LocateHandle (
2136 &gEfiPciRootBridgeIoProtocolGuid
,
2143 if (EFI_ERROR (Status
)) {
2144 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_GEN_PCIRBIO_NF
), gShellDebug1HiiHandle
);
2145 ShellStatus
= SHELL_NOT_FOUND
;
2149 HandleCount
= HandleBufSize
/ sizeof (EFI_HANDLE
);
2151 // Argument Count == 1(no other argument): enumerate all pci functions
2153 if (ShellCommandLineGetCount(Package
) == 1) {
2154 gST
->ConOut
->QueryMode (
2156 gST
->ConOut
->Mode
->Mode
,
2163 if ((ScreenSize
& 1) == 1) {
2170 // For each handle, which decides a segment and a bus number range,
2171 // enumerate all devices on it.
2173 for (Index
= 0; Index
< HandleCount
; Index
++) {
2174 Status
= PciGetProtocolAndResource (
2179 if (EFI_ERROR (Status
)) {
2180 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_PCI_HANDLE_CFG_ERR
), gShellDebug1HiiHandle
, Status
);
2181 ShellStatus
= SHELL_NOT_FOUND
;
2185 // No document say it's impossible for a RootBridgeIo protocol handle
2186 // to have more than one address space descriptors, so find out every
2187 // bus range and for each of them do device enumeration.
2190 Status
= PciGetNextBusRange (&Descriptors
, &MinBus
, &MaxBus
, &IsEnd
);
2192 if (EFI_ERROR (Status
)) {
2193 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_PCI_BUS_RANGE_ERR
), gShellDebug1HiiHandle
, Status
);
2194 ShellStatus
= SHELL_NOT_FOUND
;
2202 for (Bus
= MinBus
; Bus
<= MaxBus
; Bus
++) {
2204 // For each devices, enumerate all functions it contains
2206 for (Device
= 0; Device
<= PCI_MAX_DEVICE
; Device
++) {
2208 // For each function, read its configuration space and print summary
2210 for (Func
= 0; Func
<= PCI_MAX_FUNC
; Func
++) {
2211 if (ShellGetExecutionBreakFlag ()) {
2212 ShellStatus
= SHELL_ABORTED
;
2215 Address
= CALC_EFI_PCI_ADDRESS (Bus
, Device
, Func
, 0);
2225 // If VendorId = 0xffff, there does not exist a device at this
2226 // location. For each device, if there is any function on it,
2227 // there must be 1 function at Function 0. So if Func = 0, there
2228 // will be no more functions in the same device, so we can break
2229 // loop to deal with the next device.
2231 if (PciHeader
.VendorId
== 0xffff && Func
== 0) {
2235 if (PciHeader
.VendorId
!= 0xffff) {
2238 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_PCI_TITLE
), gShellDebug1HiiHandle
);
2246 sizeof (PciHeader
) / sizeof (UINT32
),
2251 -1, -1, NULL
, STRING_TOKEN (STR_PCI_LINE_P1
), gShellDebug1HiiHandle
,
2252 IoDev
->SegmentNumber
,
2258 PciPrintClassCode (PciHeader
.ClassCode
, FALSE
);
2260 -1, -1, NULL
, STRING_TOKEN (STR_PCI_LINE_P2
), gShellDebug1HiiHandle
,
2263 PciHeader
.ClassCode
[0]
2267 if (ScreenCount
>= ScreenSize
&& ScreenSize
!= 0) {
2269 // If ScreenSize == 0 we have the console redirected so don't
2275 // If this is not a multi-function device, we can leave the loop
2276 // to deal with the next device.
2278 if (Func
== 0 && ((PciHeader
.HeaderType
& HEADER_TYPE_MULTI_FUNCTION
) == 0x00)) {
2286 // If Descriptor is NULL, Configuration() returns EFI_UNSUPPRORED,
2287 // we assume the bus range is 0~PCI_MAX_BUS. After enumerated all
2288 // devices on all bus, we can leave loop.
2290 if (Descriptors
== NULL
) {
2296 Status
= EFI_SUCCESS
;
2300 ExplainData
= FALSE
;
2305 if (ShellCommandLineGetFlag(Package
, L
"-i")) {
2309 Temp
= ShellCommandLineGetValue(Package
, L
"-s");
2311 Segment
= (UINT16
) ShellStrToUintn (Temp
);
2315 // The first Argument(except "-i") is assumed to be Bus number, second
2316 // to be Device number, and third to be Func number.
2318 Temp
= ShellCommandLineGetRawValue(Package
, 1);
2320 Bus
= (UINT16
)ShellStrToUintn(Temp
);
2321 if (Bus
> MAX_BUS_NUMBER
) {
2322 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_GEN_PROBLEM
), gShellDebug1HiiHandle
, Temp
);
2323 ShellStatus
= SHELL_INVALID_PARAMETER
;
2327 Temp
= ShellCommandLineGetRawValue(Package
, 2);
2329 Device
= (UINT16
) ShellStrToUintn(Temp
);
2330 if (Device
> MAX_DEVICE_NUMBER
){
2331 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_GEN_PROBLEM
), gShellDebug1HiiHandle
, Temp
);
2332 ShellStatus
= SHELL_INVALID_PARAMETER
;
2337 Temp
= ShellCommandLineGetRawValue(Package
, 3);
2339 Func
= (UINT16
) ShellStrToUintn(Temp
);
2340 if (Func
> MAX_FUNCTION_NUMBER
){
2341 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_GEN_PROBLEM
), gShellDebug1HiiHandle
, Temp
);
2342 ShellStatus
= SHELL_INVALID_PARAMETER
;
2348 // Find the protocol interface who's in charge of current segment, and its
2349 // bus range covers the current bus
2351 Status
= PciFindProtocolInterface (
2359 if (EFI_ERROR (Status
)) {
2361 -1, -1, NULL
, STRING_TOKEN (STR_PCI_NO_FIND
), gShellDebug1HiiHandle
,
2362 gShellDebug1HiiHandle
,
2366 ShellStatus
= SHELL_NOT_FOUND
;
2370 Address
= CALC_EFI_PCI_ADDRESS (Bus
, Device
, Func
, 0);
2371 Status
= IoDev
->Pci
.Read (
2375 sizeof (ConfigSpace
),
2379 if (EFI_ERROR (Status
)) {
2380 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_PCI_NO_CFG
), gShellDebug1HiiHandle
, Status
);
2381 ShellStatus
= SHELL_ACCESS_DENIED
;
2385 mConfigSpace
= &ConfigSpace
;
2390 STRING_TOKEN (STR_PCI_INFO
),
2391 gShellDebug1HiiHandle
,
2403 // Dump standard header of configuration space
2405 SizeOfHeader
= sizeof (ConfigSpace
.Common
) + sizeof (ConfigSpace
.NonCommon
);
2407 DumpHex (2, 0, SizeOfHeader
, &ConfigSpace
);
2408 ShellPrintEx(-1,-1, L
"\r\n");
2411 // Dump device dependent Part of configuration space
2416 sizeof (ConfigSpace
) - SizeOfHeader
,
2421 // If "-i" appears in command line, interpret data in configuration space
2424 Status
= PciExplainData (&ConfigSpace
, Address
, IoDev
);
2428 if (HandleBuf
!= NULL
) {
2429 FreePool (HandleBuf
);
2431 if (Package
!= NULL
) {
2432 ShellCommandLineFreeVarList (Package
);
2434 mConfigSpace
= NULL
;
2439 This function finds out the protocol which is in charge of the given
2440 segment, and its bus range covers the current bus number. It lookes
2441 each instances of RootBridgeIoProtocol handle, until the one meets the
2444 @param[in] HandleBuf Buffer which holds all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.
2445 @param[in] HandleCount Count of all PCI_ROOT_BRIDIGE_IO_PROTOCOL handles.
2446 @param[in] Segment Segment number of device we are dealing with.
2447 @param[in] Bus Bus number of device we are dealing with.
2448 @param[out] IoDev Handle used to access configuration space of PCI device.
2450 @retval EFI_SUCCESS The command completed successfully.
2451 @retval EFI_INVALID_PARAMETER Invalid parameter.
2455 PciFindProtocolInterface (
2456 IN EFI_HANDLE
*HandleBuf
,
2457 IN UINTN HandleCount
,
2460 OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
**IoDev
2465 EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
*Descriptors
;
2471 // Go through all handles, until the one meets the criteria is found
2473 for (Index
= 0; Index
< HandleCount
; Index
++) {
2474 Status
= PciGetProtocolAndResource (HandleBuf
[Index
], IoDev
, &Descriptors
);
2475 if (EFI_ERROR (Status
)) {
2479 // When Descriptors == NULL, the Configuration() is not implemented,
2480 // so we only check the Segment number
2482 if (Descriptors
== NULL
&& Segment
== (*IoDev
)->SegmentNumber
) {
2486 if ((*IoDev
)->SegmentNumber
!= Segment
) {
2491 Status
= PciGetNextBusRange (&Descriptors
, &MinBus
, &MaxBus
, &IsEnd
);
2492 if (EFI_ERROR (Status
)) {
2500 if (MinBus
<= Bus
&& MaxBus
>= Bus
) {
2506 return EFI_NOT_FOUND
;
2510 This function gets the protocol interface from the given handle, and
2511 obtains its address space descriptors.
2513 @param[in] Handle The PCI_ROOT_BRIDIGE_IO_PROTOCOL handle.
2514 @param[out] IoDev Handle used to access configuration space of PCI device.
2515 @param[out] Descriptors Points to the address space descriptors.
2517 @retval EFI_SUCCESS The command completed successfully
2520 PciGetProtocolAndResource (
2521 IN EFI_HANDLE Handle
,
2522 OUT EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
**IoDev
,
2523 OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
**Descriptors
2529 // Get inferface from protocol
2531 Status
= gBS
->HandleProtocol (
2533 &gEfiPciRootBridgeIoProtocolGuid
,
2537 if (EFI_ERROR (Status
)) {
2541 // Call Configuration() to get address space descriptors
2543 Status
= (*IoDev
)->Configuration (*IoDev
, (VOID
**)Descriptors
);
2544 if (Status
== EFI_UNSUPPORTED
) {
2545 *Descriptors
= NULL
;
2554 This function get the next bus range of given address space descriptors.
2555 It also moves the pointer backward a node, to get prepared to be called
2558 @param[in, out] Descriptors Points to current position of a serial of address space
2560 @param[out] MinBus The lower range of bus number.
2561 @param[out] MaxBus The upper range of bus number.
2562 @param[out] IsEnd Meet end of the serial of descriptors.
2564 @retval EFI_SUCCESS The command completed successfully.
2567 PciGetNextBusRange (
2568 IN OUT EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR
**Descriptors
,
2577 // When *Descriptors is NULL, Configuration() is not implemented, so assume
2578 // range is 0~PCI_MAX_BUS
2580 if ((*Descriptors
) == NULL
) {
2582 *MaxBus
= PCI_MAX_BUS
;
2586 // *Descriptors points to one or more address space descriptors, which
2587 // ends with a end tagged descriptor. Examine each of the descriptors,
2588 // if a bus typed one is found and its bus range covers bus, this handle
2589 // is the handle we are looking for.
2592 while ((*Descriptors
)->Desc
!= ACPI_END_TAG_DESCRIPTOR
) {
2593 if ((*Descriptors
)->ResType
== ACPI_ADDRESS_SPACE_TYPE_BUS
) {
2594 *MinBus
= (UINT16
) (*Descriptors
)->AddrRangeMin
;
2595 *MaxBus
= (UINT16
) (*Descriptors
)->AddrRangeMax
;
2597 return (EFI_SUCCESS
);
2603 if ((*Descriptors
)->Desc
== ACPI_END_TAG_DESCRIPTOR
) {
2611 Explain the data in PCI configuration space. The part which is common for
2612 PCI device and bridge is interpreted in this function. It calls other
2613 functions to interpret data unique for device or bridge.
2615 @param[in] ConfigSpace Data in PCI configuration space.
2616 @param[in] Address Address used to access configuration space of this PCI device.
2617 @param[in] IoDev Handle used to access configuration space of PCI device.
2619 @retval EFI_SUCCESS The command completed successfully.
2623 IN PCI_CONFIG_SPACE
*ConfigSpace
,
2625 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
2628 PCI_COMMON_HEADER
*Common
;
2629 PCI_HEADER_TYPE HeaderType
;
2633 Common
= &(ConfigSpace
->Common
);
2638 // Print Vendor Id and Device Id
2640 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_PCI_LINE_VID_DID
), gShellDebug1HiiHandle
,
2641 INDEX_OF (&(Common
->VendorId
)),
2643 INDEX_OF (&(Common
->DeviceId
)),
2648 // Print register Command
2650 PciExplainCommand (&(Common
->Command
));
2653 // Print register Status
2655 PciExplainStatus (&(Common
->Status
), TRUE
, PciUndefined
);
2658 // Print register Revision ID
2660 ShellPrintEx(-1, -1, L
"/r/n");
2661 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_PCI_LINE_RID
), gShellDebug1HiiHandle
,
2662 INDEX_OF (&(Common
->RevisionId
)),
2667 // Print register BIST
2669 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_PCI_LINE_BIST
), gShellDebug1HiiHandle
, INDEX_OF (&(Common
->Bist
)));
2670 if ((Common
->Bist
& PCI_BIT_7
) != 0) {
2671 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_PCI_LINE_CAP
), gShellDebug1HiiHandle
, 0x0f & Common
->Bist
);
2673 ShellPrintHiiEx(-1, -1, NULL
, STRING_TOKEN (STR_PCI_LINE_CAP_NO
), gShellDebug1HiiHandle
);
2676 // Print register Cache Line Size
2678 ShellPrintHiiEx(-1, -1, NULL
,
2679 STRING_TOKEN (STR_PCI2_CACHE_LINE_SIZE
),
2680 gShellDebug1HiiHandle
,
2681 INDEX_OF (&(Common
->CacheLineSize
)),
2682 Common
->CacheLineSize
2686 // Print register Latency Timer
2688 ShellPrintHiiEx(-1, -1, NULL
,
2689 STRING_TOKEN (STR_PCI2_LATENCY_TIMER
),
2690 gShellDebug1HiiHandle
,
2691 INDEX_OF (&(Common
->PrimaryLatencyTimer
)),
2692 Common
->PrimaryLatencyTimer
2696 // Print register Header Type
2698 ShellPrintHiiEx(-1, -1, NULL
,
2699 STRING_TOKEN (STR_PCI2_HEADER_TYPE
),
2700 gShellDebug1HiiHandle
,
2701 INDEX_OF (&(Common
->HeaderType
)),
2705 if ((Common
->HeaderType
& PCI_BIT_7
) != 0) {
2706 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_MULTI_FUNCTION
), gShellDebug1HiiHandle
);
2709 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_SINGLE_FUNCTION
), gShellDebug1HiiHandle
);
2712 HeaderType
= (PCI_HEADER_TYPE
)(UINT8
) (Common
->HeaderType
& 0x7f);
2713 switch (HeaderType
) {
2715 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_PCI_DEVICE
), gShellDebug1HiiHandle
);
2719 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_P2P_BRIDGE
), gShellDebug1HiiHandle
);
2722 case PciCardBusBridge
:
2723 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_CARDBUS_BRIDGE
), gShellDebug1HiiHandle
);
2727 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_RESERVED
), gShellDebug1HiiHandle
);
2728 HeaderType
= PciUndefined
;
2732 // Print register Class Code
2734 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_CLASS
), gShellDebug1HiiHandle
);
2735 PciPrintClassCode ((UINT8
*) Common
->ClassCode
, TRUE
);
2738 if (ShellGetExecutionBreakFlag()) {
2743 // Interpret remaining part of PCI configuration header depending on
2747 Status
= EFI_SUCCESS
;
2748 switch (HeaderType
) {
2750 Status
= PciExplainDeviceData (
2751 &(ConfigSpace
->NonCommon
.Device
),
2755 CapPtr
= ConfigSpace
->NonCommon
.Device
.CapabilitiesPtr
;
2759 Status
= PciExplainBridgeData (
2760 &(ConfigSpace
->NonCommon
.Bridge
),
2764 CapPtr
= ConfigSpace
->NonCommon
.Bridge
.CapabilitiesPtr
;
2767 case PciCardBusBridge
:
2768 Status
= PciExplainCardBusData (
2769 &(ConfigSpace
->NonCommon
.CardBus
),
2773 CapPtr
= ConfigSpace
->NonCommon
.CardBus
.CapabilitiesPtr
;
2780 // If Status bit4 is 1, dump or explain capability structure
2782 if ((Common
->Status
) & EFI_PCI_STATUS_CAPABILITY
) {
2783 PciExplainCapabilityStruct (IoDev
, Address
, CapPtr
);
2790 Explain the device specific part of data in PCI configuration space.
2792 @param[in] Device Data in PCI configuration space.
2793 @param[in] Address Address used to access configuration space of this PCI device.
2794 @param[in] IoDev Handle used to access configuration space of PCI device.
2796 @retval EFI_SUCCESS The command completed successfully.
2799 PciExplainDeviceData (
2800 IN PCI_DEVICE_HEADER
*Device
,
2802 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
2811 // Print Base Address Registers(Bar). When Bar = 0, this Bar does not
2812 // exist. If these no Bar for this function, print "none", otherwise
2813 // list detail information about this Bar.
2815 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_BASE_ADDR
), gShellDebug1HiiHandle
, INDEX_OF (Device
->Bar
));
2818 BarCount
= sizeof (Device
->Bar
) / sizeof (Device
->Bar
[0]);
2819 for (Index
= 0; Index
< BarCount
; Index
++) {
2820 if (Device
->Bar
[Index
] == 0) {
2826 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_START_TYPE
), gShellDebug1HiiHandle
);
2827 Print (L
" --------------------------------------------------------------------------");
2830 Status
= PciExplainBar (
2831 &(Device
->Bar
[Index
]),
2832 &(mConfigSpace
->Common
.Command
),
2838 if (EFI_ERROR (Status
)) {
2844 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_NONE
), gShellDebug1HiiHandle
);
2847 Print (L
"\n --------------------------------------------------------------------------");
2851 // Print register Expansion ROM Base Address
2853 if ((Device
->ROMBar
& PCI_BIT_0
) == 0) {
2854 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_EXPANSION_ROM_DISABLED
), gShellDebug1HiiHandle
, INDEX_OF (&(Device
->ROMBar
)));
2857 ShellPrintHiiEx(-1, -1, NULL
,
2858 STRING_TOKEN (STR_PCI2_EXPANSION_ROM_BASE
),
2859 gShellDebug1HiiHandle
,
2860 INDEX_OF (&(Device
->ROMBar
)),
2865 // Print register Cardbus CIS ptr
2867 ShellPrintHiiEx(-1, -1, NULL
,
2868 STRING_TOKEN (STR_PCI2_CARDBUS_CIS
),
2869 gShellDebug1HiiHandle
,
2870 INDEX_OF (&(Device
->CardBusCISPtr
)),
2871 Device
->CardBusCISPtr
2875 // Print register Sub-vendor ID and subsystem ID
2877 ShellPrintHiiEx(-1, -1, NULL
,
2878 STRING_TOKEN (STR_PCI2_SUB_VENDOR_ID
),
2879 gShellDebug1HiiHandle
,
2880 INDEX_OF (&(Device
->SubVendorId
)),
2884 ShellPrintHiiEx(-1, -1, NULL
,
2885 STRING_TOKEN (STR_PCI2_SUBSYSTEM_ID
),
2886 gShellDebug1HiiHandle
,
2887 INDEX_OF (&(Device
->SubSystemId
)),
2892 // Print register Capabilities Ptr
2894 ShellPrintHiiEx(-1, -1, NULL
,
2895 STRING_TOKEN (STR_PCI2_CAPABILITIES_PTR
),
2896 gShellDebug1HiiHandle
,
2897 INDEX_OF (&(Device
->CapabilitiesPtr
)),
2898 Device
->CapabilitiesPtr
2902 // Print register Interrupt Line and interrupt pin
2904 ShellPrintHiiEx(-1, -1, NULL
,
2905 STRING_TOKEN (STR_PCI2_INTERRUPT_LINE
),
2906 gShellDebug1HiiHandle
,
2907 INDEX_OF (&(Device
->InterruptLine
)),
2908 Device
->InterruptLine
2911 ShellPrintHiiEx(-1, -1, NULL
,
2912 STRING_TOKEN (STR_PCI2_INTERRUPT_PIN
),
2913 gShellDebug1HiiHandle
,
2914 INDEX_OF (&(Device
->InterruptPin
)),
2915 Device
->InterruptPin
2919 // Print register Min_Gnt and Max_Lat
2921 ShellPrintHiiEx(-1, -1, NULL
,
2922 STRING_TOKEN (STR_PCI2_MIN_GNT
),
2923 gShellDebug1HiiHandle
,
2924 INDEX_OF (&(Device
->MinGnt
)),
2928 ShellPrintHiiEx(-1, -1, NULL
,
2929 STRING_TOKEN (STR_PCI2_MAX_LAT
),
2930 gShellDebug1HiiHandle
,
2931 INDEX_OF (&(Device
->MaxLat
)),
2939 Explain the bridge specific part of data in PCI configuration space.
2941 @param[in] Bridge Bridge specific data region in PCI configuration space.
2942 @param[in] Address Address used to access configuration space of this PCI device.
2943 @param[in] IoDev Handle used to access configuration space of PCI device.
2945 @retval EFI_SUCCESS The command completed successfully.
2948 PciExplainBridgeData (
2949 IN PCI_BRIDGE_HEADER
*Bridge
,
2951 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
2961 // Print Base Address Registers. When Bar = 0, this Bar does not
2962 // exist. If these no Bar for this function, print "none", otherwise
2963 // list detail information about this Bar.
2965 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_BASE_ADDRESS
), gShellDebug1HiiHandle
, INDEX_OF (&(Bridge
->Bar
)));
2968 BarCount
= sizeof (Bridge
->Bar
) / sizeof (Bridge
->Bar
[0]);
2970 for (Index
= 0; Index
< BarCount
; Index
++) {
2971 if (Bridge
->Bar
[Index
] == 0) {
2977 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_START_TYPE_2
), gShellDebug1HiiHandle
);
2978 Print (L
" --------------------------------------------------------------------------");
2981 Status
= PciExplainBar (
2982 &(Bridge
->Bar
[Index
]),
2983 &(mConfigSpace
->Common
.Command
),
2989 if (EFI_ERROR (Status
)) {
2995 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_NONE
), gShellDebug1HiiHandle
);
2997 Print (L
"\n --------------------------------------------------------------------------");
3001 // Expansion register ROM Base Address
3003 if ((Bridge
->ROMBar
& PCI_BIT_0
) == 0) {
3004 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_NO_EXPANSION_ROM
), gShellDebug1HiiHandle
, INDEX_OF (&(Bridge
->ROMBar
)));
3007 ShellPrintHiiEx(-1, -1, NULL
,
3008 STRING_TOKEN (STR_PCI2_EXPANSION_ROM_BASE_2
),
3009 gShellDebug1HiiHandle
,
3010 INDEX_OF (&(Bridge
->ROMBar
)),
3015 // Print Bus Numbers(Primary, Secondary, and Subordinate
3017 ShellPrintHiiEx(-1, -1, NULL
,
3018 STRING_TOKEN (STR_PCI2_BUS_NUMBERS
),
3019 gShellDebug1HiiHandle
,
3020 INDEX_OF (&(Bridge
->PrimaryBus
)),
3021 INDEX_OF (&(Bridge
->SecondaryBus
)),
3022 INDEX_OF (&(Bridge
->SubordinateBus
))
3025 Print (L
" ------------------------------------------------------\n");
3027 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_BRIDGE
), gShellDebug1HiiHandle
, Bridge
->PrimaryBus
);
3028 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_BRIDGE
), gShellDebug1HiiHandle
, Bridge
->SecondaryBus
);
3029 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_BRIDGE
), gShellDebug1HiiHandle
, Bridge
->SubordinateBus
);
3032 // Print register Secondary Latency Timer
3034 ShellPrintHiiEx(-1, -1, NULL
,
3035 STRING_TOKEN (STR_PCI2_SECONDARY_TIMER
),
3036 gShellDebug1HiiHandle
,
3037 INDEX_OF (&(Bridge
->SecondaryLatencyTimer
)),
3038 Bridge
->SecondaryLatencyTimer
3042 // Print register Secondary Status
3044 PciExplainStatus (&(Bridge
->SecondaryStatus
), FALSE
, PciP2pBridge
);
3047 // Print I/O and memory ranges this bridge forwards. There are 3 resource
3048 // types: I/O, memory, and pre-fetchable memory. For each resource type,
3049 // base and limit address are listed.
3051 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_RESOURCE_TYPE
), gShellDebug1HiiHandle
);
3052 Print (L
"----------------------------------------------------------------------\n");
3057 IoAddress32
= (Bridge
->IoBaseUpper
<< 16 | Bridge
->IoBase
<< 8);
3058 IoAddress32
&= 0xfffff000;
3059 ShellPrintHiiEx(-1, -1, NULL
,
3060 STRING_TOKEN (STR_PCI2_TWO_VARS
),
3061 gShellDebug1HiiHandle
,
3062 INDEX_OF (&(Bridge
->IoBase
)),
3066 IoAddress32
= (Bridge
->IoLimitUpper
<< 16 | Bridge
->IoLimit
<< 8);
3067 IoAddress32
|= 0x00000fff;
3068 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_ONE_VAR
), gShellDebug1HiiHandle
, IoAddress32
);
3071 // Memory Base & Limit
3073 ShellPrintHiiEx(-1, -1, NULL
,
3074 STRING_TOKEN (STR_PCI2_MEMORY
),
3075 gShellDebug1HiiHandle
,
3076 INDEX_OF (&(Bridge
->MemoryBase
)),
3077 (Bridge
->MemoryBase
<< 16) & 0xfff00000
3080 ShellPrintHiiEx(-1, -1, NULL
,
3081 STRING_TOKEN (STR_PCI2_ONE_VAR
),
3082 gShellDebug1HiiHandle
,
3083 (Bridge
->MemoryLimit
<< 16) | 0x000fffff
3087 // Pre-fetch-able Memory Base & Limit
3089 ShellPrintHiiEx(-1, -1, NULL
,
3090 STRING_TOKEN (STR_PCI2_PREFETCHABLE
),
3091 gShellDebug1HiiHandle
,
3092 INDEX_OF (&(Bridge
->PrefetchableMemBase
)),
3093 Bridge
->PrefetchableBaseUpper
,
3094 (Bridge
->PrefetchableMemBase
<< 16) & 0xfff00000
3097 ShellPrintHiiEx(-1, -1, NULL
,
3098 STRING_TOKEN (STR_PCI2_TWO_VARS_2
),
3099 gShellDebug1HiiHandle
,
3100 Bridge
->PrefetchableLimitUpper
,
3101 (Bridge
->PrefetchableMemLimit
<< 16) | 0x000fffff
3105 // Print register Capabilities Pointer
3107 ShellPrintHiiEx(-1, -1, NULL
,
3108 STRING_TOKEN (STR_PCI2_CAPABILITIES_PTR_2
),
3109 gShellDebug1HiiHandle
,
3110 INDEX_OF (&(Bridge
->CapabilitiesPtr
)),
3111 Bridge
->CapabilitiesPtr
3115 // Print register Bridge Control
3117 PciExplainBridgeControl (&(Bridge
->BridgeControl
), PciP2pBridge
);
3120 // Print register Interrupt Line & PIN
3122 ShellPrintHiiEx(-1, -1, NULL
,
3123 STRING_TOKEN (STR_PCI2_INTERRUPT_LINE_2
),
3124 gShellDebug1HiiHandle
,
3125 INDEX_OF (&(Bridge
->InterruptLine
)),
3126 Bridge
->InterruptLine
3129 ShellPrintHiiEx(-1, -1, NULL
,
3130 STRING_TOKEN (STR_PCI2_INTERRUPT_PIN
),
3131 gShellDebug1HiiHandle
,
3132 INDEX_OF (&(Bridge
->InterruptPin
)),
3133 Bridge
->InterruptPin
3140 Explain the Base Address Register(Bar) in PCI configuration space.
3142 @param[in] Bar Points to the Base Address Register intended to interpret.
3143 @param[in] Command Points to the register Command.
3144 @param[in] Address Address used to access configuration space of this PCI device.
3145 @param[in] IoDev Handle used to access configuration space of PCI device.
3146 @param[in, out] Index The Index.
3148 @retval EFI_SUCCESS The command completed successfully.
3155 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
,
3176 // According the bar type, list detail about this bar, for example: 32 or
3177 // 64 bits; pre-fetchable or not.
3179 if ((*Bar
& PCI_BIT_0
) == 0) {
3181 // This bar is of memory type
3185 if ((*Bar
& PCI_BIT_1
) == 0 && (*Bar
& PCI_BIT_2
) == 0) {
3186 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_BAR
), gShellDebug1HiiHandle
, *Bar
& 0xfffffff0);
3187 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_MEM
), gShellDebug1HiiHandle
);
3188 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_32_BITS
), gShellDebug1HiiHandle
);
3190 } else if ((*Bar
& PCI_BIT_1
) == 0 && (*Bar
& PCI_BIT_2
) != 0) {
3192 CopyMem (&Bar64
, Bar
, sizeof (UINT64
));
3193 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_ONE_VAR_2
), gShellDebug1HiiHandle
, (UINT32
) RShiftU64 ((Bar64
& 0xfffffffffffffff0ULL
), 32));
3194 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_ONE_VAR_3
), gShellDebug1HiiHandle
, (UINT32
) (Bar64
& 0xfffffffffffffff0ULL
));
3195 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_MEM
), gShellDebug1HiiHandle
);
3196 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_64_BITS
), gShellDebug1HiiHandle
);
3204 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_BAR
), gShellDebug1HiiHandle
, *Bar
& 0xfffffff0);
3205 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_MEM_2
), gShellDebug1HiiHandle
);
3208 if ((*Bar
& PCI_BIT_3
) == 0) {
3209 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_NO
), gShellDebug1HiiHandle
);
3212 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_YES
), gShellDebug1HiiHandle
);
3217 // This bar is of io type
3220 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_ONE_VAR_4
), gShellDebug1HiiHandle
, *Bar
& 0xfffffffc);
3225 // Get BAR length(or the amount of resource this bar demands for). To get
3226 // Bar length, first we should temporarily disable I/O and memory access
3227 // of this function(by set bits in the register Command), then write all
3228 // "1"s to this bar. The bar value read back is the amount of resource
3229 // this bar demands for.
3232 // Disable io & mem access
3234 OldCommand
= *Command
;
3235 NewCommand
= (UINT16
) (OldCommand
& 0xfffc);
3236 RegAddress
= Address
| INDEX_OF (Command
);
3237 IoDev
->Pci
.Write (IoDev
, EfiPciWidthUint16
, RegAddress
, 1, &NewCommand
);
3239 RegAddress
= Address
| INDEX_OF (Bar
);
3242 // Read after write the BAR to get the size
3246 NewBar32
= 0xffffffff;
3248 IoDev
->Pci
.Write (IoDev
, EfiPciWidthUint32
, RegAddress
, 1, &NewBar32
);
3249 IoDev
->Pci
.Read (IoDev
, EfiPciWidthUint32
, RegAddress
, 1, &NewBar32
);
3250 IoDev
->Pci
.Write (IoDev
, EfiPciWidthUint32
, RegAddress
, 1, &OldBar32
);
3253 NewBar32
= NewBar32
& 0xfffffff0;
3254 NewBar32
= (~NewBar32
) + 1;
3257 NewBar32
= NewBar32
& 0xfffffffc;
3258 NewBar32
= (~NewBar32
) + 1;
3259 NewBar32
= NewBar32
& 0x0000ffff;
3264 CopyMem (&OldBar64
, Bar
, sizeof (UINT64
));
3265 NewBar64
= 0xffffffffffffffffULL
;
3267 IoDev
->Pci
.Write (IoDev
, EfiPciWidthUint32
, RegAddress
, 2, &NewBar64
);
3268 IoDev
->Pci
.Read (IoDev
, EfiPciWidthUint32
, RegAddress
, 2, &NewBar64
);
3269 IoDev
->Pci
.Write (IoDev
, EfiPciWidthUint32
, RegAddress
, 2, &OldBar64
);
3272 NewBar64
= NewBar64
& 0xfffffffffffffff0ULL
;
3273 NewBar64
= (~NewBar64
) + 1;
3276 NewBar64
= NewBar64
& 0xfffffffffffffffcULL
;
3277 NewBar64
= (~NewBar64
) + 1;
3278 NewBar64
= NewBar64
& 0x000000000000ffff;
3282 // Enable io & mem access
3284 RegAddress
= Address
| INDEX_OF (Command
);
3285 IoDev
->Pci
.Write (IoDev
, EfiPciWidthUint16
, RegAddress
, 1, &OldCommand
);
3289 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_NEWBAR_32
), gShellDebug1HiiHandle
, NewBar32
);
3290 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_NEWBAR_32_2
), gShellDebug1HiiHandle
, NewBar32
+ (*Bar
& 0xfffffff0) - 1);
3293 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_RSHIFT
), gShellDebug1HiiHandle
, (UINT32
) RShiftU64 (NewBar64
, 32));
3294 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_RSHIFT
), gShellDebug1HiiHandle
, (UINT32
) NewBar64
);
3296 ShellPrintHiiEx(-1, -1, NULL
,
3297 STRING_TOKEN (STR_PCI2_RSHIFT
),
3298 gShellDebug1HiiHandle
,
3299 (UINT32
) RShiftU64 ((NewBar64
+ (Bar64
& 0xfffffffffffffff0ULL
) - 1), 32)
3301 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_RSHIFT
), gShellDebug1HiiHandle
, (UINT32
) (NewBar64
+ (Bar64
& 0xfffffffffffffff0ULL
) - 1));
3305 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_NEWBAR_32_3
), gShellDebug1HiiHandle
, NewBar32
);
3306 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_NEWBAR_32_4
), gShellDebug1HiiHandle
, NewBar32
+ (*Bar
& 0xfffffffc) - 1);
3313 Explain the cardbus specific part of data in PCI configuration space.
3315 @param[in] CardBus CardBus specific region of PCI configuration space.
3316 @param[in] Address Address used to access configuration space of this PCI device.
3317 @param[in] IoDev Handle used to access configuration space of PCI device.
3319 @retval EFI_SUCCESS The command completed successfully.
3322 PciExplainCardBusData (
3323 IN PCI_CARDBUS_HEADER
*CardBus
,
3325 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
3329 PCI_CARDBUS_DATA
*CardBusData
;
3331 ShellPrintHiiEx(-1, -1, NULL
,
3332 STRING_TOKEN (STR_PCI2_CARDBUS_SOCKET
),
3333 gShellDebug1HiiHandle
,
3334 INDEX_OF (&(CardBus
->CardBusSocketReg
)),
3335 CardBus
->CardBusSocketReg
3339 // Print Secondary Status
3341 PciExplainStatus (&(CardBus
->SecondaryStatus
), FALSE
, PciCardBusBridge
);
3344 // Print Bus Numbers(Primary bus number, CardBus bus number, and
3345 // Subordinate bus number
3347 ShellPrintHiiEx(-1, -1, NULL
,
3348 STRING_TOKEN (STR_PCI2_BUS_NUMBERS_2
),
3349 gShellDebug1HiiHandle
,
3350 INDEX_OF (&(CardBus
->PciBusNumber
)),
3351 INDEX_OF (&(CardBus
->CardBusBusNumber
)),
3352 INDEX_OF (&(CardBus
->SubordinateBusNumber
))
3355 Print (L
" ------------------------------------------------------\n");
3357 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_CARDBUS
), gShellDebug1HiiHandle
, CardBus
->PciBusNumber
);
3358 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_CARDBUS_2
), gShellDebug1HiiHandle
, CardBus
->CardBusBusNumber
);
3359 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_CARDBUS_3
), gShellDebug1HiiHandle
, CardBus
->SubordinateBusNumber
);
3362 // Print CardBus Latency Timer
3364 ShellPrintHiiEx(-1, -1, NULL
,
3365 STRING_TOKEN (STR_PCI2_CARDBUS_LATENCY
),
3366 gShellDebug1HiiHandle
,
3367 INDEX_OF (&(CardBus
->CardBusLatencyTimer
)),
3368 CardBus
->CardBusLatencyTimer
3372 // Print Memory/Io ranges this cardbus bridge forwards
3374 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_RESOURCE_TYPE_2
), gShellDebug1HiiHandle
);
3375 Print (L
"----------------------------------------------------------------------\n");
3377 ShellPrintHiiEx(-1, -1, NULL
,
3378 STRING_TOKEN (STR_PCI2_MEM_3
),
3379 gShellDebug1HiiHandle
,
3380 INDEX_OF (&(CardBus
->MemoryBase0
)),
3381 CardBus
->BridgeControl
& PCI_BIT_8
? L
" Prefetchable" : L
"Non-Prefetchable",
3382 CardBus
->MemoryBase0
& 0xfffff000,
3383 CardBus
->MemoryLimit0
| 0x00000fff
3386 ShellPrintHiiEx(-1, -1, NULL
,
3387 STRING_TOKEN (STR_PCI2_MEM_3
),
3388 gShellDebug1HiiHandle
,
3389 INDEX_OF (&(CardBus
->MemoryBase1
)),
3390 CardBus
->BridgeControl
& PCI_BIT_9
? L
" Prefetchable" : L
"Non-Prefetchable",
3391 CardBus
->MemoryBase1
& 0xfffff000,
3392 CardBus
->MemoryLimit1
| 0x00000fff
3395 Io32Bit
= (BOOLEAN
) (CardBus
->IoBase0
& PCI_BIT_0
);
3396 ShellPrintHiiEx(-1, -1, NULL
,
3397 STRING_TOKEN (STR_PCI2_IO_2
),
3398 gShellDebug1HiiHandle
,
3399 INDEX_OF (&(CardBus
->IoBase0
)),
3400 Io32Bit
? L
" 32 bit" : L
" 16 bit",
3401 CardBus
->IoBase0
& (Io32Bit
? 0xfffffffc : 0x0000fffc),
3402 (CardBus
->IoLimit0
& (Io32Bit
? 0xffffffff : 0x0000ffff)) | 0x00000003
3405 Io32Bit
= (BOOLEAN
) (CardBus
->IoBase1
& PCI_BIT_0
);
3406 ShellPrintHiiEx(-1, -1, NULL
,
3407 STRING_TOKEN (STR_PCI2_IO_2
),
3408 gShellDebug1HiiHandle
,
3409 INDEX_OF (&(CardBus
->IoBase1
)),
3410 Io32Bit
? L
" 32 bit" : L
" 16 bit",
3411 CardBus
->IoBase1
& (Io32Bit
? 0xfffffffc : 0x0000fffc),
3412 (CardBus
->IoLimit1
& (Io32Bit
? 0xffffffff : 0x0000ffff)) | 0x00000003
3416 // Print register Interrupt Line & PIN
3418 ShellPrintHiiEx(-1, -1, NULL
,
3419 STRING_TOKEN (STR_PCI2_INTERRUPT_LINE_3
),
3420 gShellDebug1HiiHandle
,
3421 INDEX_OF (&(CardBus
->InterruptLine
)),
3422 CardBus
->InterruptLine
,
3423 INDEX_OF (&(CardBus
->InterruptPin
)),
3424 CardBus
->InterruptPin
3428 // Print register Bridge Control
3430 PciExplainBridgeControl (&(CardBus
->BridgeControl
), PciCardBusBridge
);
3433 // Print some registers in data region of PCI configuration space for cardbus
3434 // bridge. Fields include: Sub VendorId, Subsystem ID, and Legacy Mode Base
3437 CardBusData
= (PCI_CARDBUS_DATA
*) ((UINT8
*) CardBus
+ sizeof (PCI_CARDBUS_HEADER
));
3439 ShellPrintHiiEx(-1, -1, NULL
,
3440 STRING_TOKEN (STR_PCI2_SUB_VENDOR_ID_2
),
3441 gShellDebug1HiiHandle
,
3442 INDEX_OF (&(CardBusData
->SubVendorId
)),
3443 CardBusData
->SubVendorId
,
3444 INDEX_OF (&(CardBusData
->SubSystemId
)),
3445 CardBusData
->SubSystemId
3448 ShellPrintHiiEx(-1, -1, NULL
,
3449 STRING_TOKEN (STR_PCI2_OPTIONAL
),
3450 gShellDebug1HiiHandle
,
3451 INDEX_OF (&(CardBusData
->LegacyBase
)),
3452 CardBusData
->LegacyBase
3459 Explain each meaningful bit of register Status. The definition of Status is
3460 slightly different depending on the PCI header type.
3462 @param[in] Status Points to the content of register Status.
3463 @param[in] MainStatus Indicates if this register is main status(not secondary
3465 @param[in] HeaderType Header type of this PCI device.
3467 @retval EFI_SUCCESS The command completed successfully.
3472 IN BOOLEAN MainStatus
,
3473 IN PCI_HEADER_TYPE HeaderType
3477 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_STATUS
), gShellDebug1HiiHandle
, INDEX_OF (Status
), *Status
);
3480 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_SECONDARY_STATUS
), gShellDebug1HiiHandle
, INDEX_OF (Status
), *Status
);
3483 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_NEW_CAPABILITIES
), gShellDebug1HiiHandle
, (*Status
& PCI_BIT_4
) != 0);
3486 // Bit 5 is meaningless for CardBus Bridge
3488 if (HeaderType
== PciCardBusBridge
) {
3489 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_66_CAPABLE
), gShellDebug1HiiHandle
, (*Status
& PCI_BIT_5
) != 0);
3492 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_66_CAPABLE_2
), gShellDebug1HiiHandle
, (*Status
& PCI_BIT_5
) != 0);
3495 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_FAST_BACK
), gShellDebug1HiiHandle
, (*Status
& PCI_BIT_7
) != 0);
3497 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_MASTER_DATA
), gShellDebug1HiiHandle
, (*Status
& PCI_BIT_8
) != 0);
3499 // Bit 9 and bit 10 together decides the DEVSEL timing
3501 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_DEVSEL_TIMING
), gShellDebug1HiiHandle
);
3502 if ((*Status
& PCI_BIT_9
) == 0 && (*Status
& PCI_BIT_10
) == 0) {
3503 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_FAST
), gShellDebug1HiiHandle
);
3505 } else if ((*Status
& PCI_BIT_9
) != 0 && (*Status
& PCI_BIT_10
) == 0) {
3506 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_MEDIUM
), gShellDebug1HiiHandle
);
3508 } else if ((*Status
& PCI_BIT_9
) == 0 && (*Status
& PCI_BIT_10
) != 0) {
3509 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_SLOW
), gShellDebug1HiiHandle
);
3512 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_RESERVED_2
), gShellDebug1HiiHandle
);
3515 ShellPrintHiiEx(-1, -1, NULL
,
3516 STRING_TOKEN (STR_PCI2_SIGNALED_TARGET
),
3517 gShellDebug1HiiHandle
,
3518 (*Status
& PCI_BIT_11
) != 0
3521 ShellPrintHiiEx(-1, -1, NULL
,
3522 STRING_TOKEN (STR_PCI2_RECEIVED_TARGET
),
3523 gShellDebug1HiiHandle
,
3524 (*Status
& PCI_BIT_12
) != 0
3527 ShellPrintHiiEx(-1, -1, NULL
,
3528 STRING_TOKEN (STR_PCI2_RECEIVED_MASTER
),
3529 gShellDebug1HiiHandle
,
3530 (*Status
& PCI_BIT_13
) != 0
3534 ShellPrintHiiEx(-1, -1, NULL
,
3535 STRING_TOKEN (STR_PCI2_SIGNALED_ERROR
),
3536 gShellDebug1HiiHandle
,
3537 (*Status
& PCI_BIT_14
) != 0
3541 ShellPrintHiiEx(-1, -1, NULL
,
3542 STRING_TOKEN (STR_PCI2_RECEIVED_ERROR
),
3543 gShellDebug1HiiHandle
,
3544 (*Status
& PCI_BIT_14
) != 0
3548 ShellPrintHiiEx(-1, -1, NULL
,
3549 STRING_TOKEN (STR_PCI2_DETECTED_ERROR
),
3550 gShellDebug1HiiHandle
,
3551 (*Status
& PCI_BIT_15
) != 0
3558 Explain each meaningful bit of register Command.
3560 @param[in] Command Points to the content of register Command.
3562 @retval EFI_SUCCESS The command completed successfully.
3570 // Print the binary value of register Command
3572 ShellPrintHiiEx(-1, -1, NULL
,STRING_TOKEN (STR_PCI2_COMMAND
), gShellDebug1HiiHandle
, INDEX_OF (Command
), *Command
);
3575 // Explain register Command bit by bit
3577 ShellPrintHiiEx(-1, -1, NULL
,
3578 STRING_TOKEN (STR_PCI2_SPACE_ACCESS_DENIED
),
3579 gShellDebug1HiiHandle
,
3580 (*Command
& PCI_BIT_0
) != 0
3583 ShellPrintHiiEx(-1, -1, NULL
,
3584 STRING_TOKEN (STR_PCI2_MEMORY_SPACE
),
3585 gShellDebug1HiiHandle
,
3586 (*Command
& PCI_BIT_1
) != 0
3589 ShellPrintHiiEx(-1, -1, NULL
,
3590 STRING_TOKEN (STR_PCI2_BEHAVE_BUS_MASTER
),
3591 gShellDebug1HiiHandle
,
3592 (*Command
& PCI_BIT_2
) != 0
3595 ShellPrintHiiEx(-1, -1, NULL
,
3596 STRING_TOKEN (STR_PCI2_MONITOR_SPECIAL_CYCLE
),
3597 gShellDebug1HiiHandle
,
3598 (*Command
& PCI_BIT_3
) != 0
3601 ShellPrintHiiEx(-1, -1, NULL
,
3602 STRING_TOKEN (STR_PCI2_MEM_WRITE_INVALIDATE
),
3603 gShellDebug1HiiHandle
,
3604 (*Command
& PCI_BIT_4
) != 0
3607 ShellPrintHiiEx(-1, -1, NULL
,
3608 STRING_TOKEN (STR_PCI2_PALETTE_SNOOPING
),
3609 gShellDebug1HiiHandle
,
3610 (*Command
& PCI_BIT_5
) != 0
3613 ShellPrintHiiEx(-1, -1, NULL
,
3614 STRING_TOKEN (STR_PCI2_ASSERT_PERR
),
3615 gShellDebug1HiiHandle
,
3616 (*Command
& PCI_BIT_6
) != 0
3619 ShellPrintHiiEx(-1, -1, NULL
,
3620 STRING_TOKEN (STR_PCI2_DO_ADDR_STEPPING
),
3621 gShellDebug1HiiHandle
,
3622 (*Command
& PCI_BIT_7
) != 0
3625 ShellPrintHiiEx(-1, -1, NULL
,
3626 STRING_TOKEN (STR_PCI2_SERR_DRIVER
),
3627 gShellDebug1HiiHandle
,
3628 (*Command
& PCI_BIT_8
) != 0
3631 ShellPrintHiiEx(-1, -1, NULL
,
3632 STRING_TOKEN (STR_PCI2_FAST_BACK_2
),
3633 gShellDebug1HiiHandle
,
3634 (*Command
& PCI_BIT_9
) != 0
3641 Explain each meaningful bit of register Bridge Control.
3643 @param[in] BridgeControl Points to the content of register Bridge Control.
3644 @param[in] HeaderType The headertype.
3646 @retval EFI_SUCCESS The command completed successfully.
3649 PciExplainBridgeControl (
3650 IN UINT16
*BridgeControl
,
3651 IN PCI_HEADER_TYPE HeaderType
3654 ShellPrintHiiEx(-1, -1, NULL
,
3655 STRING_TOKEN (STR_PCI2_BRIDGE_CONTROL
),
3656 gShellDebug1HiiHandle
,
3657 INDEX_OF (BridgeControl
),
3661 ShellPrintHiiEx(-1, -1, NULL
,
3662 STRING_TOKEN (STR_PCI2_PARITY_ERROR
),
3663 gShellDebug1HiiHandle
,
3664 (*BridgeControl
& PCI_BIT_0
) != 0
3666 ShellPrintHiiEx(-1, -1, NULL
,
3667 STRING_TOKEN (STR_PCI2_SERR_ENABLE
),
3668 gShellDebug1HiiHandle
,
3669 (*BridgeControl
& PCI_BIT_1
) != 0
3671 ShellPrintHiiEx(-1, -1, NULL
,
3672 STRING_TOKEN (STR_PCI2_ISA_ENABLE
),
3673 gShellDebug1HiiHandle
,
3674 (*BridgeControl
& PCI_BIT_2
) != 0
3676 ShellPrintHiiEx(-1, -1, NULL
,
3677 STRING_TOKEN (STR_PCI2_VGA_ENABLE
),
3678 gShellDebug1HiiHandle
,
3679 (*BridgeControl
& PCI_BIT_3
) != 0
3681 ShellPrintHiiEx(-1, -1, NULL
,
3682 STRING_TOKEN (STR_PCI2_MASTER_ABORT
),
3683 gShellDebug1HiiHandle
,
3684 (*BridgeControl
& PCI_BIT_5
) != 0
3688 // Register Bridge Control has some slight differences between P2P bridge
3689 // and Cardbus bridge from bit 6 to bit 11.
3691 if (HeaderType
== PciP2pBridge
) {
3692 ShellPrintHiiEx(-1, -1, NULL
,
3693 STRING_TOKEN (STR_PCI2_SECONDARY_BUS_RESET
),
3694 gShellDebug1HiiHandle
,
3695 (*BridgeControl
& PCI_BIT_6
) != 0
3697 ShellPrintHiiEx(-1, -1, NULL
,
3698 STRING_TOKEN (STR_PCI2_FAST_ENABLE
),
3699 gShellDebug1HiiHandle
,
3700 (*BridgeControl
& PCI_BIT_7
) != 0
3702 ShellPrintHiiEx(-1, -1, NULL
,
3703 STRING_TOKEN (STR_PCI2_PRIMARY_DISCARD_TIMER
),
3704 gShellDebug1HiiHandle
,
3705 (*BridgeControl
& PCI_BIT_8
)!=0 ? L
"2^10" : L
"2^15"
3707 ShellPrintHiiEx(-1, -1, NULL
,
3708 STRING_TOKEN (STR_PCI2_SECONDARY_DISCARD_TIMER
),
3709 gShellDebug1HiiHandle
,
3710 (*BridgeControl
& PCI_BIT_9
)!=0 ? L
"2^10" : L
"2^15"
3712 ShellPrintHiiEx(-1, -1, NULL
,
3713 STRING_TOKEN (STR_PCI2_DISCARD_TIMER_STATUS
),
3714 gShellDebug1HiiHandle
,
3715 (*BridgeControl
& PCI_BIT_10
) != 0
3717 ShellPrintHiiEx(-1, -1, NULL
,
3718 STRING_TOKEN (STR_PCI2_DISCARD_TIMER_SERR
),
3719 gShellDebug1HiiHandle
,
3720 (*BridgeControl
& PCI_BIT_11
) != 0
3724 ShellPrintHiiEx(-1, -1, NULL
,
3725 STRING_TOKEN (STR_PCI2_CARDBUS_RESET
),
3726 gShellDebug1HiiHandle
,
3727 (*BridgeControl
& PCI_BIT_6
) != 0
3729 ShellPrintHiiEx(-1, -1, NULL
,
3730 STRING_TOKEN (STR_PCI2_IREQ_ENABLE
),
3731 gShellDebug1HiiHandle
,
3732 (*BridgeControl
& PCI_BIT_7
) != 0
3734 ShellPrintHiiEx(-1, -1, NULL
,
3735 STRING_TOKEN (STR_PCI2_WRITE_POSTING_ENABLE
),
3736 gShellDebug1HiiHandle
,
3737 (*BridgeControl
& PCI_BIT_10
) != 0
3745 Print each capability structure.
3747 @param[in] IoDev The pointer to the deivce.
3748 @param[in] Address The address to start at.
3749 @param[in] CapPtr The offset from the address.
3751 @retval EFI_SUCCESS The operation was successful.
3754 PciExplainCapabilityStruct (
3755 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
,
3760 UINT8 CapabilityPtr
;
3761 UINT16 CapabilityEntry
;
3765 CapabilityPtr
= CapPtr
;
3768 // Go through the Capability list
3770 while ((CapabilityPtr
>= 0x40) && ((CapabilityPtr
& 0x03) == 0x00)) {
3771 RegAddress
= Address
+ CapabilityPtr
;
3772 IoDev
->Pci
.Read (IoDev
, EfiPciWidthUint16
, RegAddress
, 1, &CapabilityEntry
);
3774 CapabilityID
= (UINT8
) CapabilityEntry
;
3777 // Explain PciExpress data
3779 if (EFI_PCI_CAPABILITY_ID_PCIEXP
== CapabilityID
) {
3780 PciExplainPciExpress (IoDev
, Address
, CapabilityPtr
);
3784 // Explain other capabilities here
3786 CapabilityPtr
= (UINT8
) (CapabilityEntry
>> 8);
3793 Print out information of the capability information.
3795 @param[in] PciExpressCap The pointer to the structure about the device.
3797 @retval EFI_SUCCESS The operation was successful.
3801 IN PCIE_CAP_STURCTURE
*PciExpressCap
3805 CHAR16
*DevicePortType
;
3807 PcieCapReg
= PciExpressCap
->PcieCapReg
;
3809 L
" Capability Version(3:0): %E0x%04x%N\n",
3810 PCIE_CAP_VERSION (PcieCapReg
)
3812 if ((UINT8
) PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg
) < PCIE_DEVICE_PORT_TYPE_MAX
) {
3813 DevicePortType
= DevicePortTypeTable
[PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg
)];
3815 DevicePortType
= L
"Unknown Type";
3818 L
" Device/PortType(7:4): %E%s%N\n",
3822 // 'Slot Implemented' is only valid for:
3823 // a) Root Port of PCI Express Root Complex, or
3824 // b) Downstream Port of PCI Express Switch
3826 if (PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg
) == PCIE_ROOT_COMPLEX_ROOT_PORT
||
3827 PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg
) == PCIE_SWITCH_DOWNSTREAM_PORT
) {
3829 L
" Slot Implemented(8): %E%d%N\n",
3830 PCIE_CAP_SLOT_IMPLEMENTED (PcieCapReg
)
3834 L
" Interrupt Message Number(13:9): %E0x%05x%N\n",
3835 PCIE_CAP_INT_MSG_NUM (PcieCapReg
)
3841 Print out information of the device capability information.
3843 @param[in] PciExpressCap The pointer to the structure about the device.
3845 @retval EFI_SUCCESS The operation was successful.
3848 ExplainPcieDeviceCap (
3849 IN PCIE_CAP_STURCTURE
*PciExpressCap
3853 UINT32 PcieDeviceCap
;
3854 UINT8 DevicePortType
;
3858 PcieCapReg
= PciExpressCap
->PcieCapReg
;
3859 PcieDeviceCap
= PciExpressCap
->PcieDeviceCap
;
3860 DevicePortType
= (UINT8
) PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg
);
3861 Print (L
" Max_Payload_Size Supported(2:0): ");
3862 if (PCIE_CAP_MAX_PAYLOAD (PcieDeviceCap
) < 6) {
3863 Print (L
"%E%d bytes%N\n", 1 << (PCIE_CAP_MAX_PAYLOAD (PcieDeviceCap
) + 7));
3865 Print (L
"%EUnknown%N\n");
3868 L
" Phantom Functions Supported(4:3): %E%d%N\n",
3869 PCIE_CAP_PHANTOM_FUNC (PcieDeviceCap
)
3872 L
" Extended Tag Field Supported(5): %E%d-bit Tag field supported%N\n",
3873 PCIE_CAP_EXTENDED_TAG (PcieDeviceCap
) ? 8 : 5
3876 // Endpoint L0s and L1 Acceptable Latency is only valid for Endpoint
3878 if (IS_PCIE_ENDPOINT (DevicePortType
)) {
3879 L0sLatency
= (UINT8
) PCIE_CAP_L0SLATENCY (PcieDeviceCap
);
3880 L1Latency
= (UINT8
) PCIE_CAP_L1LATENCY (PcieDeviceCap
);
3881 Print (L
" Endpoint L0s Acceptable Latency(8:6): ");
3882 if (L0sLatency
< 4) {
3883 Print (L
"%EMaximum of %d ns%N\n", 1 << (L0sLatency
+ 6));
3885 if (L0sLatency
< 7) {
3886 Print (L
"%EMaximum of %d us%N\n", 1 << (L0sLatency
- 3));
3888 Print (L
"%ENo limit%N\n");
3891 Print (L
" Endpoint L1 Acceptable Latency(11:9): ");
3892 if (L1Latency
< 7) {
3893 Print (L
"%EMaximum of %d us%N\n", 1 << (L1Latency
+ 1));
3895 Print (L
"%ENo limit%N\n");
3899 L
" Role-based Error Reporting(15): %E%d%N\n",
3900 PCIE_CAP_ERR_REPORTING (PcieDeviceCap
)
3903 // Only valid for Upstream Port:
3904 // a) Captured Slot Power Limit Value
3905 // b) Captured Slot Power Scale
3907 if (DevicePortType
== PCIE_SWITCH_UPSTREAM_PORT
) {
3909 L
" Captured Slot Power Limit Value(25:18): %E0x%02x%N\n",
3910 PCIE_CAP_SLOT_POWER_VALUE (PcieDeviceCap
)
3913 L
" Captured Slot Power Limit Scale(27:26): %E%s%N\n",
3914 SlotPwrLmtScaleTable
[PCIE_CAP_SLOT_POWER_SCALE (PcieDeviceCap
)]
3918 // Function Level Reset Capability is only valid for Endpoint
3920 if (IS_PCIE_ENDPOINT (DevicePortType
)) {
3922 L
" Function Level Reset Capability(28): %E%d%N\n",
3923 PCIE_CAP_FUNC_LEVEL_RESET (PcieDeviceCap
)
3930 Print out information of the device control information.
3932 @param[in] PciExpressCap The pointer to the structure about the device.
3934 @retval EFI_SUCCESS The operation was successful.
3937 ExplainPcieDeviceControl (
3938 IN PCIE_CAP_STURCTURE
*PciExpressCap
3942 UINT16 PcieDeviceControl
;
3944 PcieCapReg
= PciExpressCap
->PcieCapReg
;
3945 PcieDeviceControl
= PciExpressCap
->DeviceControl
;
3947 L
" Correctable Error Reporting Enable(0): %E%d%N\n",
3948 PCIE_CAP_COR_ERR_REPORTING_ENABLE (PcieDeviceControl
)
3951 L
" Non-Fatal Error Reporting Enable(1): %E%d%N\n",
3952 PCIE_CAP_NONFAT_ERR_REPORTING_ENABLE (PcieDeviceControl
)
3955 L
" Fatal Error Reporting Enable(2): %E%d%N\n",
3956 PCIE_CAP_FATAL_ERR_REPORTING_ENABLE (PcieDeviceControl
)
3959 L
" Unsupported Request Reporting Enable(3): %E%d%N\n",
3960 PCIE_CAP_UNSUP_REQ_REPORTING_ENABLE (PcieDeviceControl
)
3963 L
" Enable Relaxed Ordering(4): %E%d%N\n",
3964 PCIE_CAP_RELAXED_ORDERING_ENABLE (PcieDeviceControl
)
3966 Print (L
" Max_Payload_Size(7:5): ");
3967 if (PCIE_CAP_MAX_PAYLOAD_SIZE (PcieDeviceControl
) < 6) {
3968 Print (L
"%E%d bytes%N\n", 1 << (PCIE_CAP_MAX_PAYLOAD_SIZE (PcieDeviceControl
) + 7));
3970 Print (L
"%EUnknown%N\n");
3973 L
" Extended Tag Field Enable(8): %E%d%N\n",
3974 PCIE_CAP_EXTENDED_TAG_ENABLE (PcieDeviceControl
)
3977 L
" Phantom Functions Enable(9): %E%d%N\n",
3978 PCIE_CAP_PHANTOM_FUNC_ENABLE (PcieDeviceControl
)
3981 L
" Auxiliary (AUX) Power PM Enable(10): %E%d%N\n",
3982 PCIE_CAP_AUX_PM_ENABLE (PcieDeviceControl
)
3985 L
" Enable No Snoop(11): %E%d%N\n",
3986 PCIE_CAP_NO_SNOOP_ENABLE (PcieDeviceControl
)
3988 Print (L
" Max_Read_Request_Size(14:12): ");
3989 if (PCIE_CAP_MAX_READ_REQ_SIZE (PcieDeviceControl
) < 6) {
3990 Print (L
"%E%d bytes%N\n", 1 << (PCIE_CAP_MAX_READ_REQ_SIZE (PcieDeviceControl
) + 7));
3992 Print (L
"%EUnknown%N\n");
3995 // Read operation is only valid for PCI Express to PCI/PCI-X Bridges
3997 if (PCIE_CAP_DEVICEPORT_TYPE (PcieCapReg
) == PCIE_PCIE_TO_PCIX_BRIDGE
) {
3999 L
" Bridge Configuration Retry Enable(15): %E%d%N\n",
4000 PCIE_CAP_BRG_CONF_RETRY (PcieDeviceControl
)
4007 Print out information of the device status information.
4009 @param[in] PciExpressCap The pointer to the structure about the device.
4011 @retval EFI_SUCCESS The operation was successful.
4014 ExplainPcieDeviceStatus (
4015 IN PCIE_CAP_STURCTURE
*PciExpressCap
4018 UINT16 PcieDeviceStatus
;
4020 PcieDeviceStatus
= PciExpressCap
->DeviceStatus
;
4022 L
" Correctable Error Detected(0): %E%d%N\n",
4023 PCIE_CAP_COR_ERR_DETECTED (PcieDeviceStatus
)
4026 L
" Non-Fatal Error Detected(1): %E%d%N\n",
4027 PCIE_CAP_NONFAT_ERR_DETECTED (PcieDeviceStatus
)
4030 L
" Fatal Error Detected(2): %E%d%N\n",
4031 PCIE_CAP_FATAL_ERR_DETECTED (PcieDeviceStatus
)
4034 L
" Unsupported Request Detected(3): %E%d%N\n",
4035 PCIE_CAP_UNSUP_REQ_DETECTED (PcieDeviceStatus
)
4038 L
" AUX Power Detected(4): %E%d%N\n",
4039 PCIE_CAP_AUX_POWER_DETECTED (PcieDeviceStatus
)
4042 L
" Transactions Pending(5): %E%d%N\n",
4043 PCIE_CAP_TRANSACTION_PENDING (PcieDeviceStatus
)
4049 Print out information of the device link information.
4051 @param[in] PciExpressCap The pointer to the structure about the device.
4053 @retval EFI_SUCCESS The operation was successful.
4056 ExplainPcieLinkCap (
4057 IN PCIE_CAP_STURCTURE
*PciExpressCap
4061 CHAR16
*SupLinkSpeeds
;
4064 PcieLinkCap
= PciExpressCap
->LinkCap
;
4065 switch (PCIE_CAP_SUP_LINK_SPEEDS (PcieLinkCap
)) {
4067 SupLinkSpeeds
= L
"2.5 GT/s";
4070 SupLinkSpeeds
= L
"5.0 GT/s and 2.5 GT/s";
4073 SupLinkSpeeds
= L
"Unknown";
4077 L
" Supported Link Speeds(3:0): %E%s supported%N\n",
4081 L
" Maximum Link Width(9:4): %Ex%d%N\n",
4082 PCIE_CAP_MAX_LINK_WIDTH (PcieLinkCap
)
4084 switch (PCIE_CAP_ASPM_SUPPORT (PcieLinkCap
)) {
4086 AspmValue
= L
"L0s Entry";
4089 AspmValue
= L
"L0s and L1";
4092 AspmValue
= L
"Reserved";
4096 L
" Active State Power Management Support(11:10): %E%s Supported%N\n",
4100 L
" L0s Exit Latency(14:12): %E%s%N\n",
4101 L0sLatencyStrTable
[PCIE_CAP_L0S_LATENCY (PcieLinkCap
)]
4104 L
" L1 Exit Latency(17:15): %E%s%N\n",
4105 L1LatencyStrTable
[PCIE_CAP_L0S_LATENCY (PcieLinkCap
)]
4108 L
" Clock Power Management(18): %E%d%N\n",
4109 PCIE_CAP_CLOCK_PM (PcieLinkCap
)
4112 L
" Surprise Down Error Reporting Capable(19): %E%d%N\n",
4113 PCIE_CAP_SUP_DOWN_ERR_REPORTING (PcieLinkCap
)
4116 L
" Data Link Layer Link Active Reporting Capable(20): %E%d%N\n",
4117 PCIE_CAP_LINK_ACTIVE_REPORTING (PcieLinkCap
)
4120 L
" Link Bandwidth Notification Capability(21): %E%d%N\n",
4121 PCIE_CAP_LINK_BWD_NOTIF_CAP (PcieLinkCap
)
4124 L
" Port Number(31:24): %E0x%02x%N\n",
4125 PCIE_CAP_PORT_NUMBER (PcieLinkCap
)
4131 Print out information of the device link control information.
4133 @param[in] PciExpressCap The pointer to the structure about the device.
4135 @retval EFI_SUCCESS The operation was successful.
4138 ExplainPcieLinkControl (
4139 IN PCIE_CAP_STURCTURE
*PciExpressCap
4142 UINT16 PcieLinkControl
;
4143 UINT8 DevicePortType
;
4145 PcieLinkControl
= PciExpressCap
->LinkControl
;
4146 DevicePortType
= (UINT8
) PCIE_CAP_DEVICEPORT_TYPE (PciExpressCap
->PcieCapReg
);
4148 L
" Active State Power Management Control(1:0): %E%s%N\n",
4149 ASPMCtrlStrTable
[PCIE_CAP_ASPM_CONTROL (PcieLinkControl
)]
4152 // RCB is not applicable to switches
4154 if (!IS_PCIE_SWITCH(DevicePortType
)) {
4156 L
" Read Completion Boundary (RCB)(3): %E%d byte%N\n",
4157 1 << (PCIE_CAP_RCB (PcieLinkControl
) + 6)
4161 // Link Disable is reserved on
4163 // b) PCI Express to PCI/PCI-X bridges
4164 // c) Upstream Ports of Switches
4166 if (!IS_PCIE_ENDPOINT (DevicePortType
) &&
4167 DevicePortType
!= PCIE_SWITCH_UPSTREAM_PORT
&&
4168 DevicePortType
!= PCIE_PCIE_TO_PCIX_BRIDGE
) {
4170 L
" Link Disable(4): %E%d%N\n",
4171 PCIE_CAP_LINK_DISABLE (PcieLinkControl
)
4175 L
" Common Clock Configuration(6): %E%d%N\n",
4176 PCIE_CAP_COMMON_CLK_CONF (PcieLinkControl
)
4179 L
" Extended Synch(7): %E%d%N\n",
4180 PCIE_CAP_EXT_SYNC (PcieLinkControl
)
4183 L
" Enable Clock Power Management(8): %E%d%N\n",
4184 PCIE_CAP_CLK_PWR_MNG (PcieLinkControl
)
4187 L
" Hardware Autonomous Width Disable(9): %E%d%N\n",
4188 PCIE_CAP_HW_AUTO_WIDTH_DISABLE (PcieLinkControl
)
4191 L
" Link Bandwidth Management Interrupt Enable(10): %E%d%N\n",
4192 PCIE_CAP_LINK_BDW_MNG_INT_EN (PcieLinkControl
)
4195 L
" Link Autonomous Bandwidth Interrupt Enable(11): %E%d%N\n",
4196 PCIE_CAP_LINK_AUTO_BDW_INT_EN (PcieLinkControl
)
4202 Print out information of the device link status information.
4204 @param[in] PciExpressCap The pointer to the structure about the device.
4206 @retval EFI_SUCCESS The operation was successful.
4209 ExplainPcieLinkStatus (
4210 IN PCIE_CAP_STURCTURE
*PciExpressCap
4213 UINT16 PcieLinkStatus
;
4214 CHAR16
*SupLinkSpeeds
;
4216 PcieLinkStatus
= PciExpressCap
->LinkStatus
;
4217 switch (PCIE_CAP_CUR_LINK_SPEED (PcieLinkStatus
)) {
4219 SupLinkSpeeds
= L
"2.5 GT/s";
4222 SupLinkSpeeds
= L
"5.0 GT/s";
4225 SupLinkSpeeds
= L
"Reserved";
4229 L
" Current Link Speed(3:0): %E%s%N\n",
4233 L
" Negotiated Link Width(9:4): %Ex%d%N\n",
4234 PCIE_CAP_NEGO_LINK_WIDTH (PcieLinkStatus
)
4237 L
" Link Training(11): %E%d%N\n",
4238 PCIE_CAP_LINK_TRAINING (PcieLinkStatus
)
4241 L
" Slot Clock Configuration(12): %E%d%N\n",
4242 PCIE_CAP_SLOT_CLK_CONF (PcieLinkStatus
)
4245 L
" Data Link Layer Link Active(13): %E%d%N\n",
4246 PCIE_CAP_DATA_LINK_ACTIVE (PcieLinkStatus
)
4249 L
" Link Bandwidth Management Status(14): %E%d%N\n",
4250 PCIE_CAP_LINK_BDW_MNG_STAT (PcieLinkStatus
)
4253 L
" Link Autonomous Bandwidth Status(15): %E%d%N\n",
4254 PCIE_CAP_LINK_AUTO_BDW_STAT (PcieLinkStatus
)
4260 Print out information of the device slot information.
4262 @param[in] PciExpressCap The pointer to the structure about the device.
4264 @retval EFI_SUCCESS The operation was successful.
4267 ExplainPcieSlotCap (
4268 IN PCIE_CAP_STURCTURE
*PciExpressCap
4273 PcieSlotCap
= PciExpressCap
->SlotCap
;
4276 L
" Attention Button Present(0): %E%d%N\n",
4277 PCIE_CAP_ATT_BUT_PRESENT (PcieSlotCap
)
4280 L
" Power Controller Present(1): %E%d%N\n",
4281 PCIE_CAP_PWR_CTRLLER_PRESENT (PcieSlotCap
)
4284 L
" MRL Sensor Present(2): %E%d%N\n",
4285 PCIE_CAP_MRL_SENSOR_PRESENT (PcieSlotCap
)
4288 L
" Attention Indicator Present(3): %E%d%N\n",
4289 PCIE_CAP_ATT_IND_PRESENT (PcieSlotCap
)
4292 L
" Power Indicator Present(4): %E%d%N\n",
4293 PCIE_CAP_PWD_IND_PRESENT (PcieSlotCap
)
4296 L
" Hot-Plug Surprise(5): %E%d%N\n",
4297 PCIE_CAP_HOTPLUG_SUPPRISE (PcieSlotCap
)
4300 L
" Hot-Plug Capable(6): %E%d%N\n",
4301 PCIE_CAP_HOTPLUG_CAPABLE (PcieSlotCap
)
4304 L
" Slot Power Limit Value(14:7): %E0x%02x%N\n",
4305 PCIE_CAP_SLOT_PWR_LIMIT_VALUE (PcieSlotCap
)
4308 L
" Slot Power Limit Scale(16:15): %E%s%N\n",
4309 SlotPwrLmtScaleTable
[PCIE_CAP_SLOT_PWR_LIMIT_SCALE (PcieSlotCap
)]
4312 L
" Electromechanical Interlock Present(17): %E%d%N\n",
4313 PCIE_CAP_ELEC_INTERLOCK_PRESENT (PcieSlotCap
)
4316 L
" No Command Completed Support(18): %E%d%N\n",
4317 PCIE_CAP_NO_COMM_COMPLETED_SUP (PcieSlotCap
)
4320 L
" Physical Slot Number(31:19): %E%d%N\n",
4321 PCIE_CAP_PHY_SLOT_NUM (PcieSlotCap
)
4328 Print out information of the device slot control information.
4330 @param[in] PciExpressCap The pointer to the structure about the device.
4332 @retval EFI_SUCCESS The operation was successful.
4335 ExplainPcieSlotControl (
4336 IN PCIE_CAP_STURCTURE
*PciExpressCap
4339 UINT16 PcieSlotControl
;
4341 PcieSlotControl
= PciExpressCap
->SlotControl
;
4343 L
" Attention Button Pressed Enable(0): %E%d%N\n",
4344 PCIE_CAP_ATT_BUT_ENABLE (PcieSlotControl
)
4347 L
" Power Fault Detected Enable(1): %E%d%N\n",
4348 PCIE_CAP_PWR_FLT_DETECT_ENABLE (PcieSlotControl
)
4351 L
" MRL Sensor Changed Enable(2): %E%d%N\n",
4352 PCIE_CAP_MRL_SENSOR_CHANGE_ENABLE (PcieSlotControl
)
4355 L
" Presence Detect Changed Enable(3): %E%d%N\n",
4356 PCIE_CAP_PRES_DETECT_CHANGE_ENABLE (PcieSlotControl
)
4359 L
" Command Completed Interrupt Enable(4): %E%d%N\n",
4360 PCIE_CAP_COMM_CMPL_INT_ENABLE (PcieSlotControl
)
4363 L
" Hot-Plug Interrupt Enable(5): %E%d%N\n",
4364 PCIE_CAP_HOTPLUG_INT_ENABLE (PcieSlotControl
)
4367 L
" Attention Indicator Control(7:6): %E%s%N\n",
4368 IndicatorTable
[PCIE_CAP_ATT_IND_CTRL (PcieSlotControl
)]
4371 L
" Power Indicator Control(9:8): %E%s%N\n",
4372 IndicatorTable
[PCIE_CAP_PWR_IND_CTRL (PcieSlotControl
)]
4374 Print (L
" Power Controller Control(10): %EPower ");
4375 if (PCIE_CAP_PWR_CTRLLER_CTRL (PcieSlotControl
)) {
4381 L
" Electromechanical Interlock Control(11): %E%d%N\n",
4382 PCIE_CAP_ELEC_INTERLOCK_CTRL (PcieSlotControl
)
4385 L
" Data Link Layer State Changed Enable(12): %E%d%N\n",
4386 PCIE_CAP_DLINK_STAT_CHANGE_ENABLE (PcieSlotControl
)
4392 Print out information of the device slot status information.
4394 @param[in] PciExpressCap The pointer to the structure about the device.
4396 @retval EFI_SUCCESS The operation was successful.
4399 ExplainPcieSlotStatus (
4400 IN PCIE_CAP_STURCTURE
*PciExpressCap
4403 UINT16 PcieSlotStatus
;
4405 PcieSlotStatus
= PciExpressCap
->SlotStatus
;
4408 L
" Attention Button Pressed(0): %E%d%N\n",
4409 PCIE_CAP_ATT_BUT_PRESSED (PcieSlotStatus
)
4412 L
" Power Fault Detected(1): %E%d%N\n",
4413 PCIE_CAP_PWR_FLT_DETECTED (PcieSlotStatus
)
4416 L
" MRL Sensor Changed(2): %E%d%N\n",
4417 PCIE_CAP_MRL_SENSOR_CHANGED (PcieSlotStatus
)
4420 L
" Presence Detect Changed(3): %E%d%N\n",
4421 PCIE_CAP_PRES_DETECT_CHANGED (PcieSlotStatus
)
4424 L
" Command Completed(4): %E%d%N\n",
4425 PCIE_CAP_COMM_COMPLETED (PcieSlotStatus
)
4427 Print (L
" MRL Sensor State(5): %EMRL ");
4428 if (PCIE_CAP_MRL_SENSOR_STATE (PcieSlotStatus
)) {
4429 Print (L
" Opened%N\n");
4431 Print (L
" Closed%N\n");
4433 Print (L
" Presence Detect State(6): ");
4434 if (PCIE_CAP_PRES_DETECT_STATE (PcieSlotStatus
)) {
4435 Print (L
"%ECard Present in slot%N\n");
4437 Print (L
"%ESlot Empty%N\n");
4439 Print (L
" Electromechanical Interlock Status(7): %EElectromechanical Interlock ");
4440 if (PCIE_CAP_ELEC_INTERLOCK_STATE (PcieSlotStatus
)) {
4441 Print (L
"Engaged%N\n");
4443 Print (L
"Disengaged%N\n");
4446 L
" Data Link Layer State Changed(8): %E%d%N\n",
4447 PCIE_CAP_DLINK_STAT_CHANGED (PcieSlotStatus
)
4453 Print out information of the device root information.
4455 @param[in] PciExpressCap The pointer to the structure about the device.
4457 @retval EFI_SUCCESS The operation was successful.
4460 ExplainPcieRootControl (
4461 IN PCIE_CAP_STURCTURE
*PciExpressCap
4464 UINT16 PcieRootControl
;
4466 PcieRootControl
= PciExpressCap
->RootControl
;
4469 L
" System Error on Correctable Error Enable(0): %E%d%N\n",
4470 PCIE_CAP_SYSERR_ON_CORERR_EN (PcieRootControl
)
4473 L
" System Error on Non-Fatal Error Enable(1): %E%d%N\n",
4474 PCIE_CAP_SYSERR_ON_NONFATERR_EN (PcieRootControl
)
4477 L
" System Error on Fatal Error Enable(2): %E%d%N\n",
4478 PCIE_CAP_SYSERR_ON_FATERR_EN (PcieRootControl
)
4481 L
" PME Interrupt Enable(3): %E%d%N\n",
4482 PCIE_CAP_PME_INT_ENABLE (PcieRootControl
)
4485 L
" CRS Software Visibility Enable(4): %E%d%N\n",
4486 PCIE_CAP_CRS_SW_VIS_ENABLE (PcieRootControl
)
4493 Print out information of the device root capability information.
4495 @param[in] PciExpressCap The pointer to the structure about the device.
4497 @retval EFI_SUCCESS The operation was successful.
4500 ExplainPcieRootCap (
4501 IN PCIE_CAP_STURCTURE
*PciExpressCap
4506 PcieRootCap
= PciExpressCap
->RsvdP
;
4509 L
" CRS Software Visibility(0): %E%d%N\n",
4510 PCIE_CAP_CRS_SW_VIS (PcieRootCap
)
4517 Print out information of the device root status information.
4519 @param[in] PciExpressCap The pointer to the structure about the device.
4521 @retval EFI_SUCCESS The operation was successful.
4524 ExplainPcieRootStatus (
4525 IN PCIE_CAP_STURCTURE
*PciExpressCap
4528 UINT32 PcieRootStatus
;
4530 PcieRootStatus
= PciExpressCap
->RootStatus
;
4533 L
" PME Requester ID(15:0): %E0x%04x%N\n",
4534 PCIE_CAP_PME_REQ_ID (PcieRootStatus
)
4537 L
" PME Status(16): %E%d%N\n",
4538 PCIE_CAP_PME_STATUS (PcieRootStatus
)
4541 L
" PME Pending(17): %E%d%N\n",
4542 PCIE_CAP_PME_PENDING (PcieRootStatus
)
4548 Display Pcie device structure.
4550 @param[in] IoDev The pointer to the root pci protocol.
4551 @param[in] Address The Address to start at.
4552 @param[in] CapabilityPtr The offset from the address to start.
4555 PciExplainPciExpress (
4556 IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
*IoDev
,
4558 IN UINT8 CapabilityPtr
4562 PCIE_CAP_STURCTURE PciExpressCap
;
4564 UINT64 CapRegAddress
;
4569 UINTN ExtendRegSize
;
4570 UINT64 Pciex_Address
;
4571 UINT8 DevicePortType
;
4576 CapRegAddress
= Address
+ CapabilityPtr
;
4581 sizeof (PciExpressCap
) / sizeof (UINT32
),
4585 DevicePortType
= (UINT8
) PCIE_CAP_DEVICEPORT_TYPE (PciExpressCap
.PcieCapReg
);
4587 Print (L
"\nPci Express device capability structure:\n");
4589 for (Index
= 0; PcieExplainList
[Index
].Type
< PcieExplainTypeMax
; Index
++) {
4590 if (ShellGetExecutionBreakFlag()) {
4593 RegAddr
= ((UINT8
*) &PciExpressCap
) + PcieExplainList
[Index
].Offset
;
4594 switch (PcieExplainList
[Index
].Width
) {
4595 case FieldWidthUINT8
:
4596 RegValue
= *(UINT8
*) RegAddr
;
4598 case FieldWidthUINT16
:
4599 RegValue
= *(UINT16
*) RegAddr
;
4601 case FieldWidthUINT32
:
4602 RegValue
= *(UINT32
*) RegAddr
;
4608 ShellPrintHiiEx(-1, -1, NULL
,
4609 PcieExplainList
[Index
].Token
,
4610 gShellDebug1HiiHandle
,
4611 PcieExplainList
[Index
].Offset
,
4614 if (PcieExplainList
[Index
].Func
== NULL
) {
4617 switch (PcieExplainList
[Index
].Type
) {
4618 case PcieExplainTypeLink
:
4620 // Link registers should not be used by
4621 // a) Root Complex Integrated Endpoint
4622 // b) Root Complex Event Collector
4624 if (DevicePortType
== PCIE_ROOT_COMPLEX_INTEGRATED_PORT
||
4625 DevicePortType
== PCIE_ROOT_COMPLEX_EVENT_COLLECTOR
) {
4629 case PcieExplainTypeSlot
:
4631 // Slot registers are only valid for
4632 // a) Root Port of PCI Express Root Complex
4633 // b) Downstream Port of PCI Express Switch
4634 // and when SlotImplemented bit is set in PCIE cap register.
4636 if ((DevicePortType
!= PCIE_ROOT_COMPLEX_ROOT_PORT
&&
4637 DevicePortType
!= PCIE_SWITCH_DOWNSTREAM_PORT
) ||
4638 !PCIE_CAP_SLOT_IMPLEMENTED (PciExpressCap
.PcieCapReg
)) {
4642 case PcieExplainTypeRoot
:
4644 // Root registers are only valid for
4645 // Root Port of PCI Express Root Complex
4647 if (DevicePortType
!= PCIE_ROOT_COMPLEX_ROOT_PORT
) {
4654 PcieExplainList
[Index
].Func (&PciExpressCap
);
4657 Bus
= (UINT8
) (RShiftU64 (Address
, 24));
4658 Dev
= (UINT8
) (RShiftU64 (Address
, 16));
4659 Func
= (UINT8
) (RShiftU64 (Address
, 8));
4661 Pciex_Address
= CALC_EFI_PCIEX_ADDRESS (Bus
, Dev
, Func
, 0x100);
4663 ExtendRegSize
= 0x1000 - 0x100;
4665 ExRegBuffer
= (UINT8
*) AllocateZeroPool (ExtendRegSize
);
4668 // PciRootBridgeIo protocol should support pci express extend space IO
4669 // (Begins at offset 0x100)
4671 Status
= IoDev
->Pci
.Read (
4675 (ExtendRegSize
) / sizeof (UINT32
),
4676 (VOID
*) (ExRegBuffer
)
4678 if (EFI_ERROR (Status
)) {
4679 FreePool ((VOID
*) ExRegBuffer
);
4680 return EFI_UNSUPPORTED
;
4683 // Start outputing PciEx extend space( 0xFF-0xFFF)
4685 Print (L
"\n%HStart dumping PCIex extended configuration space (0x100 - 0xFFF).%N\n\n");
4687 if (ExRegBuffer
!= NULL
) {
4692 (VOID
*) (ExRegBuffer
)
4695 FreePool ((VOID
*) ExRegBuffer
);