UefiCpuPkg/CpuMpPei/CpuPaging.c

   1 /** @file
   2   Basic paging support for the CPU to enable Stack Guard.
   3
   4 Copyright (c) 2018 - 2019, Intel Corporation. All rights reserved.<BR>
   5
   6 SPDX-License-Identifier: BSD-2-Clause-Patent
   7
   8 **/
   9
  10 #include <Register/Intel/Cpuid.h>
  11 #include <Register/Intel/Msr.h>
  12 #include <Library/MemoryAllocationLib.h>
  13 #include <Library/CpuLib.h>
  14 #include <Library/BaseLib.h>
  15 #include <Guid/MigratedFvInfo.h>
  16
  17 #include "CpuMpPei.h"
  18
  19 #define IA32_PG_P   BIT0
  20 #define IA32_PG_RW  BIT1
  21 #define IA32_PG_U   BIT2
  22 #define IA32_PG_A   BIT5
  23 #define IA32_PG_D   BIT6
  24 #define IA32_PG_PS  BIT7
  25 #define IA32_PG_NX  BIT63
  26
  27 #define PAGE_ATTRIBUTE_BITS  (IA32_PG_RW | IA32_PG_P)
  28 #define PAGE_PROGATE_BITS    (IA32_PG_D | IA32_PG_A | IA32_PG_NX | IA32_PG_U | \
  29                                PAGE_ATTRIBUTE_BITS)
  30
  31 #define PAGING_PAE_INDEX_MASK        0x1FF
  32 #define PAGING_4K_ADDRESS_MASK_64    0x000FFFFFFFFFF000ull
  33 #define PAGING_2M_ADDRESS_MASK_64    0x000FFFFFFFE00000ull
  34 #define PAGING_1G_ADDRESS_MASK_64    0x000FFFFFC0000000ull
  35 #define PAGING_512G_ADDRESS_MASK_64  0x000FFF8000000000ull
  36
  37 typedef enum {
  38   PageNone = 0,
  39   PageMin  = 1,
  40   Page4K   = PageMin,
  41   Page2M   = 2,
  42   Page1G   = 3,
  43   Page512G = 4,
  44   PageMax  = Page512G
  45 } PAGE_ATTRIBUTE;
  46
  47 typedef struct {
  48   PAGE_ATTRIBUTE    Attribute;
  49   UINT64            Length;
  50   UINT64            AddressMask;
  51   UINTN             AddressBitOffset;
  52   UINTN             AddressBitLength;
  53 } PAGE_ATTRIBUTE_TABLE;
  54
  55 PAGE_ATTRIBUTE_TABLE  mPageAttributeTable[] = {
  56   { PageNone, 0,          0,                           0,  0 },
  57   { Page4K,   SIZE_4KB,   PAGING_4K_ADDRESS_MASK_64,   12, 9 },
  58   { Page2M,   SIZE_2MB,   PAGING_2M_ADDRESS_MASK_64,   21, 9 },
  59   { Page1G,   SIZE_1GB,   PAGING_1G_ADDRESS_MASK_64,   30, 9 },
  60   { Page512G, SIZE_512GB, PAGING_512G_ADDRESS_MASK_64, 39, 9 },
  61 };
  62
  63 EFI_PEI_NOTIFY_DESCRIPTOR  mPostMemNotifyList[] = {
  64   {
  65     (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
  66     &gEfiPeiMemoryDiscoveredPpiGuid,
  67     MemoryDiscoveredPpiNotifyCallback
  68   }
  69 };
  70
  71 /**
  72   The function will check if IA32 PAE is supported.
  73
  74   @retval TRUE      IA32 PAE is supported.
  75   @retval FALSE     IA32 PAE is not supported.
  76
  77 **/
  78 BOOLEAN
  79 IsIa32PaeSupported (
  80   VOID
  81   )
  82 {
  83   UINT32                  RegEax;
  84   CPUID_VERSION_INFO_EDX  RegEdx;
  85
  86   AsmCpuid (CPUID_SIGNATURE, &RegEax, NULL, NULL, NULL);
  87   if (RegEax >= CPUID_VERSION_INFO) {
  88     AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, &RegEdx.Uint32);
  89     if (RegEdx.Bits.PAE != 0) {
  90       return TRUE;
  91     }
  92   }
  93
  94   return FALSE;
  95 }
  96
  97 /**
  98   This API provides a way to allocate memory for page table.
  99
 100   @param  Pages                 The number of 4 KB pages to allocate.
 101
 102   @return A pointer to the allocated buffer or NULL if allocation fails.
 103
 104 **/
 105 VOID *
 106 AllocatePageTableMemory (
 107   IN UINTN  Pages
 108   )
 109 {
 110   VOID  *Address;
 111
 112   Address = AllocatePages (Pages);
 113   if (Address != NULL) {
 114     ZeroMem (Address, EFI_PAGES_TO_SIZE (Pages));
 115   }
 116
 117   return Address;
 118 }
 119
 120 /**
 121   Get the address width supported by current processor.
 122
 123   @retval 32      If processor is in 32-bit mode.
 124   @retval 36-48   If processor is in 64-bit mode.
 125
 126 **/
 127 UINTN
 128 GetPhysicalAddressWidth (
 129   VOID
 130   )
 131 {
 132   UINT32  RegEax;
 133
 134   if (sizeof (UINTN) == 4) {
 135     return 32;
 136   }
 137
 138   AsmCpuid (CPUID_EXTENDED_FUNCTION, &RegEax, NULL, NULL, NULL);
 139   if (RegEax >= CPUID_VIR_PHY_ADDRESS_SIZE) {
 140     AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, &RegEax, NULL, NULL, NULL);
 141     RegEax &= 0xFF;
 142     if (RegEax > 48) {
 143       return 48;
 144     }
 145
 146     return (UINTN)RegEax;
 147   }
 148
 149   return 36;
 150 }
 151
 152 /**
 153   Get the type of top level page table.
 154
 155   @retval Page512G  PML4 paging.
 156   @retval Page1G    PAE paging.
 157
 158 **/
 159 PAGE_ATTRIBUTE
 160 GetPageTableTopLevelType (
 161   VOID
 162   )
 163 {
 164   MSR_IA32_EFER_REGISTER  MsrEfer;
 165
 166   MsrEfer.Uint64 = AsmReadMsr64 (MSR_CORE_IA32_EFER);
 167
 168   return (MsrEfer.Bits.LMA == 1) ? Page512G : Page1G;
 169 }
 170
 171 /**
 172   Return page table entry matching the address.
 173
 174   @param[in]   Address          The address to be checked.
 175   @param[out]  PageAttributes   The page attribute of the page entry.
 176
 177   @return The page entry.
 178 **/
 179 VOID *
 180 GetPageTableEntry (
 181   IN  PHYSICAL_ADDRESS  Address,
 182   OUT PAGE_ATTRIBUTE    *PageAttribute
 183   )
 184 {
 185   INTN    Level;
 186   UINTN   Index;
 187   UINT64  *PageTable;
 188   UINT64  AddressEncMask;
 189
 190   AddressEncMask = PcdGet64 (PcdPteMemoryEncryptionAddressOrMask);
 191   PageTable      = (UINT64 *)(UINTN)(AsmReadCr3 () & PAGING_4K_ADDRESS_MASK_64);
 192   for (Level = (INTN)GetPageTableTopLevelType (); Level > 0; --Level) {
 193     Index  = (UINTN)RShiftU64 (Address, mPageAttributeTable[Level].AddressBitOffset);
 194     Index &= PAGING_PAE_INDEX_MASK;
 195
 196     //
 197     // No mapping?
 198     //
 199     if (PageTable[Index] == 0) {
 200       *PageAttribute = PageNone;
 201       return NULL;
 202     }
 203
 204     //
 205     // Page memory?
 206     //
 207     if (((PageTable[Index] & IA32_PG_PS) != 0) || (Level == PageMin)) {
 208       *PageAttribute = (PAGE_ATTRIBUTE)Level;
 209       return &PageTable[Index];
 210     }
 211
 212     //
 213     // Page directory or table
 214     //
 215     PageTable = (UINT64 *)(UINTN)(PageTable[Index] &
 216                                   ~AddressEncMask &
 217                                   PAGING_4K_ADDRESS_MASK_64);
 218   }
 219
 220   *PageAttribute = PageNone;
 221   return NULL;
 222 }
 223
 224 /**
 225   This function splits one page entry to smaller page entries.
 226
 227   @param[in]  PageEntry        The page entry to be splitted.
 228   @param[in]  PageAttribute    The page attribute of the page entry.
 229   @param[in]  SplitAttribute   How to split the page entry.
 230   @param[in]  Recursively      Do the split recursively or not.
 231
 232   @retval RETURN_SUCCESS            The page entry is splitted.
 233   @retval RETURN_INVALID_PARAMETER  If target page attribute is invalid
 234   @retval RETURN_OUT_OF_RESOURCES   No resource to split page entry.
 235 **/
 236 RETURN_STATUS
 237 SplitPage (
 238   IN  UINT64          *PageEntry,
 239   IN  PAGE_ATTRIBUTE  PageAttribute,
 240   IN  PAGE_ATTRIBUTE  SplitAttribute,
 241   IN  BOOLEAN         Recursively
 242   )
 243 {
 244   UINT64          BaseAddress;
 245   UINT64          *NewPageEntry;
 246   UINTN           Index;
 247   UINT64          AddressEncMask;
 248   PAGE_ATTRIBUTE  SplitTo;
 249
 250   if ((SplitAttribute == PageNone) || (SplitAttribute >= PageAttribute)) {
 251     ASSERT (SplitAttribute != PageNone);
 252     ASSERT (SplitAttribute < PageAttribute);
 253     return RETURN_INVALID_PARAMETER;
 254   }
 255
 256   NewPageEntry = AllocatePageTableMemory (1);
 257   if (NewPageEntry == NULL) {
 258     ASSERT (NewPageEntry != NULL);
 259     return RETURN_OUT_OF_RESOURCES;
 260   }
 261
 262   //
 263   // One level down each step to achieve more compact page table.
 264   //
 265   SplitTo        = PageAttribute - 1;
 266   AddressEncMask = PcdGet64 (PcdPteMemoryEncryptionAddressOrMask) &
 267                    mPageAttributeTable[SplitTo].AddressMask;
 268   BaseAddress = *PageEntry &
 269                 ~PcdGet64 (PcdPteMemoryEncryptionAddressOrMask) &
 270                 mPageAttributeTable[PageAttribute].AddressMask;
 271   for (Index = 0; Index < SIZE_4KB / sizeof (UINT64); Index++) {
 272     NewPageEntry[Index] = BaseAddress | AddressEncMask |
 273                           ((*PageEntry) & PAGE_PROGATE_BITS);
 274
 275     if (SplitTo != PageMin) {
 276       NewPageEntry[Index] |= IA32_PG_PS;
 277     }
 278
 279     if (Recursively && (SplitTo > SplitAttribute)) {
 280       SplitPage (&NewPageEntry[Index], SplitTo, SplitAttribute, Recursively);
 281     }
 282
 283     BaseAddress += mPageAttributeTable[SplitTo].Length;
 284   }
 285
 286   (*PageEntry) = (UINT64)(UINTN)NewPageEntry | AddressEncMask | PAGE_ATTRIBUTE_BITS;
 287
 288   return RETURN_SUCCESS;
 289 }
 290
 291 /**
 292   This function modifies the page attributes for the memory region specified
 293   by BaseAddress and Length from their current attributes to the attributes
 294   specified by Attributes.
 295
 296   Caller should make sure BaseAddress and Length is at page boundary.
 297
 298   @param[in]   BaseAddress      Start address of a memory region.
 299   @param[in]   Length           Size in bytes of the memory region.
 300   @param[in]   Attributes       Bit mask of attributes to modify.
 301
 302   @retval RETURN_SUCCESS            The attributes were modified for the memory
 303                                     region.
 304   @retval RETURN_INVALID_PARAMETER  Length is zero; or,
 305                                     Attributes specified an illegal combination
 306                                     of attributes that cannot be set together; or
 307                                     Addressis not 4KB aligned.
 308   @retval RETURN_OUT_OF_RESOURCES   There are not enough system resources to modify
 309                                     the attributes.
 310   @retval RETURN_UNSUPPORTED        Cannot modify the attributes of given memory.
 311
 312 **/
 313 RETURN_STATUS
 314 EFIAPI
 315 ConvertMemoryPageAttributes (
 316   IN  PHYSICAL_ADDRESS  BaseAddress,
 317   IN  UINT64            Length,
 318   IN  UINT64            Attributes
 319   )
 320 {
 321   UINT64                *PageEntry;
 322   PAGE_ATTRIBUTE        PageAttribute;
 323   RETURN_STATUS         Status;
 324   EFI_PHYSICAL_ADDRESS  MaximumAddress;
 325
 326   if ((Length == 0) ||
 327       ((BaseAddress & (SIZE_4KB - 1)) != 0) ||
 328       ((Length & (SIZE_4KB - 1)) != 0))
 329   {
 330     ASSERT (Length > 0);
 331     ASSERT ((BaseAddress & (SIZE_4KB - 1)) == 0);
 332     ASSERT ((Length & (SIZE_4KB - 1)) == 0);
 333
 334     return RETURN_INVALID_PARAMETER;
 335   }
 336
 337   MaximumAddress = (EFI_PHYSICAL_ADDRESS)MAX_UINT32;
 338   if ((BaseAddress > MaximumAddress) ||
 339       (Length > MaximumAddress) ||
 340       (BaseAddress > MaximumAddress - (Length - 1)))
 341   {
 342     return RETURN_UNSUPPORTED;
 343   }
 344
 345   //
 346   // Below logic is to check 2M/4K page to make sure we do not waste memory.
 347   //
 348   while (Length != 0) {
 349     PageEntry = GetPageTableEntry (BaseAddress, &PageAttribute);
 350     if (PageEntry == NULL) {
 351       return RETURN_UNSUPPORTED;
 352     }
 353
 354     if (PageAttribute != Page4K) {
 355       Status = SplitPage (PageEntry, PageAttribute, Page4K, FALSE);
 356       if (RETURN_ERROR (Status)) {
 357         return Status;
 358       }
 359
 360       //
 361       // Do it again until the page is 4K.
 362       //
 363       continue;
 364     }
 365
 366     //
 367     // Just take care of 'present' bit for Stack Guard.
 368     //
 369     if ((Attributes & IA32_PG_P) != 0) {
 370       *PageEntry |= (UINT64)IA32_PG_P;
 371     } else {
 372       *PageEntry &= ~((UINT64)IA32_PG_P);
 373     }
 374
 375     //
 376     // Convert success, move to next
 377     //
 378     BaseAddress += SIZE_4KB;
 379     Length      -= SIZE_4KB;
 380   }
 381
 382   return RETURN_SUCCESS;
 383 }
 384
 385 /**
 386   Get maximum size of page memory supported by current processor.
 387
 388   @param[in]   TopLevelType     The type of top level page entry.
 389
 390   @retval Page1G     If processor supports 1G page and PML4.
 391   @retval Page2M     For all other situations.
 392
 393 **/
 394 PAGE_ATTRIBUTE
 395 GetMaxMemoryPage (
 396   IN  PAGE_ATTRIBUTE  TopLevelType
 397   )
 398 {
 399   UINT32  RegEax;
 400   UINT32  RegEdx;
 401
 402   if (TopLevelType == Page512G) {
 403     AsmCpuid (CPUID_EXTENDED_FUNCTION, &RegEax, NULL, NULL, NULL);
 404     if (RegEax >= CPUID_EXTENDED_CPU_SIG) {
 405       AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, NULL, &RegEdx);
 406       if ((RegEdx & BIT26) != 0) {
 407         return Page1G;
 408       }
 409     }
 410   }
 411
 412   return Page2M;
 413 }
 414
 415 /**
 416   Create PML4 or PAE page table.
 417
 418   @return The address of page table.
 419
 420 **/
 421 UINTN
 422 CreatePageTable (
 423   VOID
 424   )
 425 {
 426   RETURN_STATUS         Status;
 427   UINTN                 PhysicalAddressBits;
 428   UINTN                 NumberOfEntries;
 429   PAGE_ATTRIBUTE        TopLevelPageAttr;
 430   UINTN                 PageTable;
 431   PAGE_ATTRIBUTE        MaxMemoryPage;
 432   UINTN                 Index;
 433   UINT64                AddressEncMask;
 434   UINT64                *PageEntry;
 435   EFI_PHYSICAL_ADDRESS  PhysicalAddress;
 436
 437   TopLevelPageAttr    = (PAGE_ATTRIBUTE)GetPageTableTopLevelType ();
 438   PhysicalAddressBits = GetPhysicalAddressWidth ();
 439   NumberOfEntries     = (UINTN)1 << (PhysicalAddressBits -
 440                                      mPageAttributeTable[TopLevelPageAttr].AddressBitOffset);
 441
 442   PageTable = (UINTN)AllocatePageTableMemory (1);
 443   if (PageTable == 0) {
 444     return 0;
 445   }
 446
 447   AddressEncMask  = PcdGet64 (PcdPteMemoryEncryptionAddressOrMask);
 448   AddressEncMask &= mPageAttributeTable[TopLevelPageAttr].AddressMask;
 449   MaxMemoryPage   = GetMaxMemoryPage (TopLevelPageAttr);
 450   PageEntry       = (UINT64 *)PageTable;
 451
 452   PhysicalAddress = 0;
 453   for (Index = 0; Index < NumberOfEntries; ++Index) {
 454     *PageEntry = PhysicalAddress | AddressEncMask | PAGE_ATTRIBUTE_BITS;
 455
 456     //
 457     // Split the top page table down to the maximum page size supported
 458     //
 459     if (MaxMemoryPage < TopLevelPageAttr) {
 460       Status = SplitPage (PageEntry, TopLevelPageAttr, MaxMemoryPage, TRUE);
 461       ASSERT_EFI_ERROR (Status);
 462     }
 463
 464     if (TopLevelPageAttr == Page1G) {
 465       //
 466       // PDPTE[2:1] (PAE Paging) must be 0. SplitPage() might change them to 1.
 467       //
 468       *PageEntry &= ~(UINT64)(IA32_PG_RW | IA32_PG_U);
 469     }
 470
 471     PageEntry       += 1;
 472     PhysicalAddress += mPageAttributeTable[TopLevelPageAttr].Length;
 473   }
 474
 475   return PageTable;
 476 }
 477
 478 /**
 479   Setup page tables and make them work.
 480
 481 **/
 482 VOID
 483 EnablePaging (
 484   VOID
 485   )
 486 {
 487   UINTN  PageTable;
 488
 489   PageTable = CreatePageTable ();
 490   ASSERT (PageTable != 0);
 491   if (PageTable != 0) {
 492     AsmWriteCr3 (PageTable);
 493     AsmWriteCr4 (AsmReadCr4 () | BIT5);   // CR4.PAE
 494     AsmWriteCr0 (AsmReadCr0 () | BIT31);  // CR0.PG
 495   }
 496 }
 497
 498 /**
 499   Get the base address of current AP's stack.
 500
 501   This function is called in AP's context and assumes that whole calling stacks
 502   (till this function) consumed by AP's wakeup procedure will not exceed 4KB.
 503
 504   PcdCpuApStackSize must be configured with value taking the Guard page into
 505   account.
 506
 507   @param[in,out] Buffer  The pointer to private data buffer.
 508
 509 **/
 510 VOID
 511 EFIAPI
 512 GetStackBase (
 513   IN OUT VOID  *Buffer
 514   )
 515 {
 516   EFI_PHYSICAL_ADDRESS  StackBase;
 517
 518   StackBase  = (EFI_PHYSICAL_ADDRESS)(UINTN)&StackBase;
 519   StackBase += BASE_4KB;
 520   StackBase &= ~((EFI_PHYSICAL_ADDRESS)BASE_4KB - 1);
 521   StackBase -= PcdGet32 (PcdCpuApStackSize);
 522
 523   *(EFI_PHYSICAL_ADDRESS *)Buffer = StackBase;
 524 }
 525
 526 /**
 527   Setup stack Guard page at the stack base of each processor. BSP and APs have
 528   different way to get stack base address.
 529
 530 **/
 531 VOID
 532 SetupStackGuardPage (
 533   VOID
 534   )
 535 {
 536   EFI_PEI_HOB_POINTERS  Hob;
 537   EFI_PHYSICAL_ADDRESS  StackBase;
 538   UINTN                 NumberOfProcessors;
 539   UINTN                 Bsp;
 540   UINTN                 Index;
 541
 542   //
 543   // One extra page at the bottom of the stack is needed for Guard page.
 544   //
 545   if (PcdGet32 (PcdCpuApStackSize) <= EFI_PAGE_SIZE) {
 546     DEBUG ((DEBUG_ERROR, "PcdCpuApStackSize is not big enough for Stack Guard!\n"));
 547     ASSERT (FALSE);
 548   }
 549
 550   MpInitLibGetNumberOfProcessors (&NumberOfProcessors, NULL);
 551   MpInitLibWhoAmI (&Bsp);
 552   for (Index = 0; Index < NumberOfProcessors; ++Index) {
 553     StackBase = 0;
 554
 555     if (Index == Bsp) {
 556       Hob.Raw = GetHobList ();
 557       while ((Hob.Raw = GetNextHob (EFI_HOB_TYPE_MEMORY_ALLOCATION, Hob.Raw)) != NULL) {
 558         if (CompareGuid (
 559               &gEfiHobMemoryAllocStackGuid,
 560               &(Hob.MemoryAllocationStack->AllocDescriptor.Name)
 561               ))
 562         {
 563           StackBase = Hob.MemoryAllocationStack->AllocDescriptor.MemoryBaseAddress;
 564           break;
 565         }
 566
 567         Hob.Raw = GET_NEXT_HOB (Hob);
 568       }
 569     } else {
 570       //
 571       // Ask AP to return is stack base address.
 572       //
 573       MpInitLibStartupThisAP (GetStackBase, Index, NULL, 0, (VOID *)&StackBase, NULL);
 574     }
 575
 576     ASSERT (StackBase != 0);
 577     //
 578     // Set Guard page at stack base address.
 579     //
 580     ConvertMemoryPageAttributes (StackBase, EFI_PAGE_SIZE, 0);
 581     DEBUG ((
 582       DEBUG_INFO,
 583       "Stack Guard set at %lx [cpu%lu]!\n",
 584       (UINT64)StackBase,
 585       (UINT64)Index
 586       ));
 587   }
 588
 589   //
 590   // Publish the changes of page table.
 591   //
 592   CpuFlushTlb ();
 593 }
 594
 595 /**
 596   Enable/setup stack guard for each processor if PcdCpuStackGuard is set to TRUE.
 597
 598   Doing this in the memory-discovered callback is to make sure the Stack Guard
 599   feature to cover as most PEI code as possible.
 600
 601   @param[in] PeiServices          General purpose services available to every PEIM.
 602   @param[in] NotifyDescriptor     The notification structure this PEIM registered on install.
 603   @param[in] Ppi                  The memory discovered PPI.  Not used.
 604
 605   @retval EFI_SUCCESS             The function completed successfully.
 606   @retval others                  There's error in MP initialization.
 607 **/
 608 EFI_STATUS
 609 EFIAPI
 610 MemoryDiscoveredPpiNotifyCallback (
 611   IN EFI_PEI_SERVICES           **PeiServices,
 612   IN EFI_PEI_NOTIFY_DESCRIPTOR  *NotifyDescriptor,
 613   IN VOID                       *Ppi
 614   )
 615 {
 616   EFI_STATUS              Status;
 617   BOOLEAN                 InitStackGuard;
 618   EDKII_MIGRATED_FV_INFO  *MigratedFvInfo;
 619   EFI_PEI_HOB_POINTERS    Hob;
 620
 621   //
 622   // Paging must be setup first. Otherwise the exception TSS setup during MP
 623   // initialization later will not contain paging information and then fail
 624   // the task switch (for the sake of stack switch).
 625   //
 626   InitStackGuard = FALSE;
 627   Hob.Raw        = NULL;
 628   if (IsIa32PaeSupported ()) {
 629     Hob.Raw        = GetFirstGuidHob (&gEdkiiMigratedFvInfoGuid);
 630     InitStackGuard = PcdGetBool (PcdCpuStackGuard);
 631   }
 632
 633   if (InitStackGuard || (Hob.Raw != NULL)) {
 634     EnablePaging ();
 635   }
 636
 637   Status = InitializeCpuMpWorker ((CONST EFI_PEI_SERVICES **)PeiServices);
 638   ASSERT_EFI_ERROR (Status);
 639
 640   if (InitStackGuard) {
 641     SetupStackGuardPage ();
 642   }
 643
 644   while (Hob.Raw != NULL) {
 645     MigratedFvInfo = GET_GUID_HOB_DATA (Hob);
 646
 647     //
 648     // Enable #PF exception, so if the code access SPI after disable NEM, it will generate
 649     // the exception to avoid potential vulnerability.
 650     //
 651     ConvertMemoryPageAttributes (MigratedFvInfo->FvOrgBase, MigratedFvInfo->FvLength, 0);
 652
 653     Hob.Raw = GET_NEXT_HOB (Hob);
 654     Hob.Raw = GetNextGuidHob (&gEdkiiMigratedFvInfoGuid, Hob.Raw);
 655   }
 656
 657   CpuFlushTlb ();
 658
 659   return Status;
 660 }