UefiCpuPkg: Apply uncrustify changes

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3737

Apply uncrustify changes to .c/.h files in the UefiCpuPkg package

Cc: Andrew Fish <afish@apple.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>

diff --git a/UefiCpuPkg/Application/Cpuid/Cpuid.c b/UefiCpuPkg/Application/Cpuid/Cpuid.c
index cee64f2fb5fc17388341f91ff9f5b7d8d470acd9..372c6ef87d36e70c20541f55c837128e84f3204d 100644 (file)
--- a/UefiCpuPkg/Application/Cpuid/Cpuid.c
+++ b/UefiCpuPkg/Application/Cpuid/Cpuid.c
@@ -27,134 +27,134 @@
 /// Structure for cache description lookup table\r
 ///\r
 typedef struct {\r
-  UINT8  CacheDescriptor;\r
-  CHAR8  *Type;\r
-  CHAR8  *Description;\r
+  UINT8    CacheDescriptor;\r
+  CHAR8    *Type;\r
+  CHAR8    *Description;\r
 } CPUID_CACHE_INFO_DESCRIPTION;\r
 \r
 ///\r
 /// Cache description lookup table\r
 ///\r
 CPUID_CACHE_INFO_DESCRIPTION  mCpuidCacheInfoDescription[] = {\r
-  { 0x00 , "General"  , "Null descriptor, this byte contains no information" },\r
-  { 0x01 , "TLB"      , "Instruction TLB: 4 KByte pages, 4-way set associative, 32 entries" },\r
-  { 0x02 , "TLB"      , "Instruction TLB: 4 MByte pages, fully associative, 2 entries" },\r
-  { 0x03 , "TLB"      , "Data TLB: 4 KByte pages, 4-way set associative, 64 entries" },\r
-  { 0x04 , "TLB"      , "Data TLB: 4 MByte pages, 4-way set associative, 8 entries" },\r
-  { 0x05 , "TLB"      , "Data TLB1: 4 MByte pages, 4-way set associative, 32 entries" },\r
-  { 0x06 , "Cache"    , "1st-level instruction cache: 8 KBytes, 4-way set associative, 32 byte line size" },\r
-  { 0x08 , "Cache"    , "1st-level instruction cache: 16 KBytes, 4-way set associative, 32 byte line size" },\r
-  { 0x09 , "Cache"    , "1st-level instruction cache: 32KBytes, 4-way set associative, 64 byte line size" },\r
-  { 0x0A , "Cache"    , "1st-level data cache: 8 KBytes, 2-way set associative, 32 byte line size" },\r
-  { 0x0B , "TLB"      , "Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries" },\r
-  { 0x0C , "Cache"    , "1st-level data cache: 16 KBytes, 4-way set associative, 32 byte line size" },\r
-  { 0x0D , "Cache"    , "1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size" },\r
-  { 0x0E , "Cache"    , "1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size" },\r
-  { 0x1D , "Cache"    , "2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size" },\r
-  { 0x21 , "Cache"    , "2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size" },\r
-  { 0x22 , "Cache"    , "3rd-level cache: 512 KBytes, 4-way set associative, 64 byte line size, 2 lines per sector" },\r
-  { 0x23 , "Cache"    , "3rd-level cache: 1 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector" },\r
-  { 0x24 , "Cache"    , "2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size" },\r
-  { 0x25 , "Cache"    , "3rd-level cache: 2 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector" },\r
-  { 0x29 , "Cache"    , "3rd-level cache: 4 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector" },\r
-  { 0x2C , "Cache"    , "1st-level data cache: 32 KBytes, 8-way set associative, 64 byte line size" },\r
-  { 0x30 , "Cache"    , "1st-level instruction cache: 32 KBytes, 8-way set associative, 64 byte line size" },\r
-  { 0x40 , "Cache"    , "No 2nd-level cache or, if processor contains a valid 2nd-level cache, no 3rd-level cache" },\r
-  { 0x41 , "Cache"    , "2nd-level cache: 128 KBytes, 4-way set associative, 32 byte line size" },\r
-  { 0x42 , "Cache"    , "2nd-level cache: 256 KBytes, 4-way set associative, 32 byte line size" },\r
-  { 0x43 , "Cache"    , "2nd-level cache: 512 KBytes, 4-way set associative, 32 byte line size" },\r
-  { 0x44 , "Cache"    , "2nd-level cache: 1 MByte, 4-way set associative, 32 byte line size" },\r
-  { 0x45 , "Cache"    , "2nd-level cache: 2 MByte, 4-way set associative, 32 byte line size" },\r
-  { 0x46 , "Cache"    , "3rd-level cache: 4 MByte, 4-way set associative, 64 byte line size" },\r
-  { 0x47 , "Cache"    , "3rd-level cache: 8 MByte, 8-way set associative, 64 byte line size" },\r
-  { 0x48 , "Cache"    , "2nd-level cache: 3MByte, 12-way set associative, 64 byte line size" },\r
-  { 0x49 , "Cache"    , "3rd-level cache: 4MB, 16-way set associative, 64-byte line size (Intel Xeon processor MP, Family 0FH, Model 06H). 2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size" },\r
-  { 0x4A , "Cache"    , "3rd-level cache: 6MByte, 12-way set associative, 64 byte line size" },\r
-  { 0x4B , "Cache"    , "3rd-level cache: 8MByte, 16-way set associative, 64 byte line size" },\r
-  { 0x4C , "Cache"    , "3rd-level cache: 12MByte, 12-way set associative, 64 byte line size" },\r
-  { 0x4D , "Cache"    , "3rd-level cache: 16MByte, 16-way set associative, 64 byte line size" },\r
-  { 0x4E , "Cache"    , "2nd-level cache: 6MByte, 24-way set associative, 64 byte line size" },\r
-  { 0x4F , "TLB"      , "Instruction TLB: 4 KByte pages, 32 entries" },\r
-  { 0x50 , "TLB"      , "Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 64 entries" },\r
-  { 0x51 , "TLB"      , "Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 128 entries" },\r
-  { 0x52 , "TLB"      , "Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 256 entries" },\r
-  { 0x55 , "TLB"      , "Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries" },\r
-  { 0x56 , "TLB"      , "Data TLB0: 4 MByte pages, 4-way set associative, 16 entries" },\r
-  { 0x57 , "TLB"      , "Data TLB0: 4 KByte pages, 4-way associative, 16 entries" },\r
-  { 0x59 , "TLB"      , "Data TLB0: 4 KByte pages, fully associative, 16 entries" },\r
-  { 0x5A , "TLB"      , "Data TLB0: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries" },\r
-  { 0x5B , "TLB"      , "Data TLB: 4 KByte and 4 MByte pages, 64 entries" },\r
-  { 0x5C , "TLB"      , "Data TLB: 4 KByte and 4 MByte pages,128 entries" },\r
-  { 0x5D , "TLB"      , "Data TLB: 4 KByte and 4 MByte pages,256 entries" },\r
-  { 0x60 , "Cache"    , "1st-level data cache: 16 KByte, 8-way set associative, 64 byte line size" },\r
-  { 0x61 , "TLB"      , "Instruction TLB: 4 KByte pages, fully associative, 48 entries" },\r
-  { 0x63 , "TLB"      , "Data TLB: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries and a separate array with 1 GByte pages, 4-way set associative, 4 entries" },\r
-  { 0x64 , "TLB"      , "Data TLB: 4 KByte pages, 4-way set associative, 512 entries" },\r
-  { 0x66 , "Cache"    , "1st-level data cache: 8 KByte, 4-way set associative, 64 byte line size" },\r
-  { 0x67 , "Cache"    , "1st-level data cache: 16 KByte, 4-way set associative, 64 byte line size" },\r
-  { 0x68 , "Cache"    , "1st-level data cache: 32 KByte, 4-way set associative, 64 byte line size" },\r
-  { 0x6A , "Cache"    , "uTLB: 4 KByte pages, 8-way set associative, 64 entries" },\r
-  { 0x6B , "Cache"    , "DTLB: 4 KByte pages, 8-way set associative, 256 entries" },\r
-  { 0x6C , "Cache"    , "DTLB: 2M/4M pages, 8-way set associative, 128 entries" },\r
-  { 0x6D , "Cache"    , "DTLB: 1 GByte pages, fully associative, 16 entries" },\r
-  { 0x70 , "Cache"    , "Trace cache: 12 K-uop, 8-way set associative" },\r
-  { 0x71 , "Cache"    , "Trace cache: 16 K-uop, 8-way set associative" },\r
-  { 0x72 , "Cache"    , "Trace cache: 32 K-uop, 8-way set associative" },\r
-  { 0x76 , "TLB"      , "Instruction TLB: 2M/4M pages, fully associative, 8 entries" },\r
-  { 0x78 , "Cache"    , "2nd-level cache: 1 MByte, 4-way set associative, 64byte line size" },\r
-  { 0x79 , "Cache"    , "2nd-level cache: 128 KByte, 8-way set associative, 64 byte line size, 2 lines per sector" },\r
-  { 0x7A , "Cache"    , "2nd-level cache: 256 KByte, 8-way set associative, 64 byte line size, 2 lines per sector" },\r
-  { 0x7B , "Cache"    , "2nd-level cache: 512 KByte, 8-way set associative, 64 byte line size, 2 lines per sector" },\r
-  { 0x7C , "Cache"    , "2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size, 2 lines per sector" },\r
-  { 0x7D , "Cache"    , "2nd-level cache: 2 MByte, 8-way set associative, 64byte line size" },\r
-  { 0x7F , "Cache"    , "2nd-level cache: 512 KByte, 2-way set associative, 64-byte line size" },\r
-  { 0x80 , "Cache"    , "2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size" },\r
-  { 0x82 , "Cache"    , "2nd-level cache: 256 KByte, 8-way set associative, 32 byte line size" },\r
-  { 0x83 , "Cache"    , "2nd-level cache: 512 KByte, 8-way set associative, 32 byte line size" },\r
-  { 0x84 , "Cache"    , "2nd-level cache: 1 MByte, 8-way set associative, 32 byte line size" },\r
-  { 0x85 , "Cache"    , "2nd-level cache: 2 MByte, 8-way set associative, 32 byte line size" },\r
-  { 0x86 , "Cache"    , "2nd-level cache: 512 KByte, 4-way set associative, 64 byte line size" },\r
-  { 0x87 , "Cache"    , "2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size" },\r
-  { 0xA0 , "DTLB"     , "DTLB: 4k pages, fully associative, 32 entries" },\r
-  { 0xB0 , "TLB"      , "Instruction TLB: 4 KByte pages, 4-way set associative, 128 entries" },\r
-  { 0xB1 , "TLB"      , "Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries" },\r
-  { 0xB2 , "TLB"      , "Instruction TLB: 4KByte pages, 4-way set associative, 64 entries" },\r
-  { 0xB3 , "TLB"      , "Data TLB: 4 KByte pages, 4-way set associative, 128 entries" },\r
-  { 0xB4 , "TLB"      , "Data TLB1: 4 KByte pages, 4-way associative, 256 entries" },\r
-  { 0xB5 , "TLB"      , "Instruction TLB: 4KByte pages, 8-way set associative, 64 entries" },\r
-  { 0xB6 , "TLB"      , "Instruction TLB: 4KByte pages, 8-way set associative, 128 entries" },\r
-  { 0xBA , "TLB"      , "Data TLB1: 4 KByte pages, 4-way associative, 64 entries" },\r
-  { 0xC0 , "TLB"      , "Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries" },\r
-  { 0xC1 , "STLB"     , "Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, 1024 entries" },\r
-  { 0xC2 , "DTLB"     , "DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries" },\r
-  { 0xC3 , "STLB"     , "Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative, 1536 entries. Also 1GBbyte pages, 4-way, 16 entries." },\r
-  { 0xC4 , "DTLB"     , "DTLB: 2M/4M Byte pages, 4-way associative, 32 entries" },\r
-  { 0xCA , "STLB"     , "Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries" },\r
-  { 0xD0 , "Cache"    , "3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size" },\r
-  { 0xD1 , "Cache"    , "3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size" },\r
-  { 0xD2 , "Cache"    , "3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size" },\r
-  { 0xD6 , "Cache"    , "3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size" },\r
-  { 0xD7 , "Cache"    , "3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size" },\r
-  { 0xD8 , "Cache"    , "3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size" },\r
-  { 0xDC , "Cache"    , "3rd-level cache: 1.5 MByte, 12-way set associative, 64 byte line size" },\r
-  { 0xDD , "Cache"    , "3rd-level cache: 3 MByte, 12-way set associative, 64 byte line size" },\r
-  { 0xDE , "Cache"    , "3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size" },\r
-  { 0xE2 , "Cache"    , "3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size" },\r
-  { 0xE3 , "Cache"    , "3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size" },\r
-  { 0xE4 , "Cache"    , "3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size" },\r
-  { 0xEA , "Cache"    , "3rd-level cache: 12MByte, 24-way set associative, 64 byte line size" },\r
-  { 0xEB , "Cache"    , "3rd-level cache: 18MByte, 24-way set associative, 64 byte line size" },\r
-  { 0xEC , "Cache"    , "3rd-level cache: 24MByte, 24-way set associative, 64 byte line size" },\r
-  { 0xF0 , "Prefetch" , "64-Byte prefetching" },\r
-  { 0xF1 , "Prefetch" , "128-Byte prefetching" },\r
-  { 0xFE , "General"  , "CPUID leaf 2 does not report TLB descriptor information; use CPUID leaf 18H to query TLB and other address translation parameters." },\r
-  { 0xFF , "General"  , "CPUID leaf 2 does not report cache descriptor information, use CPUID leaf 4 to query cache parameters" }\r
+  { 0x00, "General",  "Null descriptor, this byte contains no information"                                                                                                                                    },\r
+  { 0x01, "TLB",      "Instruction TLB: 4 KByte pages, 4-way set associative, 32 entries"                                                                                                                     },\r
+  { 0x02, "TLB",      "Instruction TLB: 4 MByte pages, fully associative, 2 entries"                                                                                                                          },\r
+  { 0x03, "TLB",      "Data TLB: 4 KByte pages, 4-way set associative, 64 entries"                                                                                                                            },\r
+  { 0x04, "TLB",      "Data TLB: 4 MByte pages, 4-way set associative, 8 entries"                                                                                                                             },\r
+  { 0x05, "TLB",      "Data TLB1: 4 MByte pages, 4-way set associative, 32 entries"                                                                                                                           },\r
+  { 0x06, "Cache",    "1st-level instruction cache: 8 KBytes, 4-way set associative, 32 byte line size"                                                                                                       },\r
+  { 0x08, "Cache",    "1st-level instruction cache: 16 KBytes, 4-way set associative, 32 byte line size"                                                                                                      },\r
+  { 0x09, "Cache",    "1st-level instruction cache: 32KBytes, 4-way set associative, 64 byte line size"                                                                                                       },\r
+  { 0x0A, "Cache",    "1st-level data cache: 8 KBytes, 2-way set associative, 32 byte line size"                                                                                                              },\r
+  { 0x0B, "TLB",      "Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries"                                                                                                                      },\r
+  { 0x0C, "Cache",    "1st-level data cache: 16 KBytes, 4-way set associative, 32 byte line size"                                                                                                             },\r
+  { 0x0D, "Cache",    "1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size"                                                                                                             },\r
+  { 0x0E, "Cache",    "1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size"                                                                                                             },\r
+  { 0x1D, "Cache",    "2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size"                                                                                                                 },\r
+  { 0x21, "Cache",    "2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size"                                                                                                                 },\r
+  { 0x22, "Cache",    "3rd-level cache: 512 KBytes, 4-way set associative, 64 byte line size, 2 lines per sector"                                                                                             },\r
+  { 0x23, "Cache",    "3rd-level cache: 1 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector"                                                                                               },\r
+  { 0x24, "Cache",    "2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size"                                                                                                                  },\r
+  { 0x25, "Cache",    "3rd-level cache: 2 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector"                                                                                               },\r
+  { 0x29, "Cache",    "3rd-level cache: 4 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector"                                                                                               },\r
+  { 0x2C, "Cache",    "1st-level data cache: 32 KBytes, 8-way set associative, 64 byte line size"                                                                                                             },\r
+  { 0x30, "Cache",    "1st-level instruction cache: 32 KBytes, 8-way set associative, 64 byte line size"                                                                                                      },\r
+  { 0x40, "Cache",    "No 2nd-level cache or, if processor contains a valid 2nd-level cache, no 3rd-level cache"                                                                                              },\r
+  { 0x41, "Cache",    "2nd-level cache: 128 KBytes, 4-way set associative, 32 byte line size"                                                                                                                 },\r
+  { 0x42, "Cache",    "2nd-level cache: 256 KBytes, 4-way set associative, 32 byte line size"                                                                                                                 },\r
+  { 0x43, "Cache",    "2nd-level cache: 512 KBytes, 4-way set associative, 32 byte line size"                                                                                                                 },\r
+  { 0x44, "Cache",    "2nd-level cache: 1 MByte, 4-way set associative, 32 byte line size"                                                                                                                    },\r
+  { 0x45, "Cache",    "2nd-level cache: 2 MByte, 4-way set associative, 32 byte line size"                                                                                                                    },\r
+  { 0x46, "Cache",    "3rd-level cache: 4 MByte, 4-way set associative, 64 byte line size"                                                                                                                    },\r
+  { 0x47, "Cache",    "3rd-level cache: 8 MByte, 8-way set associative, 64 byte line size"                                                                                                                    },\r
+  { 0x48, "Cache",    "2nd-level cache: 3MByte, 12-way set associative, 64 byte line size"                                                                                                                    },\r
+  { 0x49, "Cache",    "3rd-level cache: 4MB, 16-way set associative, 64-byte line size (Intel Xeon processor MP, Family 0FH, Model 06H). 2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size" },\r
+  { 0x4A, "Cache",    "3rd-level cache: 6MByte, 12-way set associative, 64 byte line size"                                                                                                                    },\r
+  { 0x4B, "Cache",    "3rd-level cache: 8MByte, 16-way set associative, 64 byte line size"                                                                                                                    },\r
+  { 0x4C, "Cache",    "3rd-level cache: 12MByte, 12-way set associative, 64 byte line size"                                                                                                                   },\r
+  { 0x4D, "Cache",    "3rd-level cache: 16MByte, 16-way set associative, 64 byte line size"                                                                                                                   },\r
+  { 0x4E, "Cache",    "2nd-level cache: 6MByte, 24-way set associative, 64 byte line size"                                                                                                                    },\r
+  { 0x4F, "TLB",      "Instruction TLB: 4 KByte pages, 32 entries"                                                                                                                                            },\r
+  { 0x50, "TLB",      "Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 64 entries"                                                                                                                     },\r
+  { 0x51, "TLB",      "Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 128 entries"                                                                                                                    },\r
+  { 0x52, "TLB",      "Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 256 entries"                                                                                                                    },\r
+  { 0x55, "TLB",      "Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries"                                                                                                               },\r
+  { 0x56, "TLB",      "Data TLB0: 4 MByte pages, 4-way set associative, 16 entries"                                                                                                                           },\r
+  { 0x57, "TLB",      "Data TLB0: 4 KByte pages, 4-way associative, 16 entries"                                                                                                                               },\r
+  { 0x59, "TLB",      "Data TLB0: 4 KByte pages, fully associative, 16 entries"                                                                                                                               },\r
+  { 0x5A, "TLB",      "Data TLB0: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries"                                                                                                                },\r
+  { 0x5B, "TLB",      "Data TLB: 4 KByte and 4 MByte pages, 64 entries"                                                                                                                                       },\r
+  { 0x5C, "TLB",      "Data TLB: 4 KByte and 4 MByte pages,128 entries"                                                                                                                                       },\r
+  { 0x5D, "TLB",      "Data TLB: 4 KByte and 4 MByte pages,256 entries"                                                                                                                                       },\r
+  { 0x60, "Cache",    "1st-level data cache: 16 KByte, 8-way set associative, 64 byte line size"                                                                                                              },\r
+  { 0x61, "TLB",      "Instruction TLB: 4 KByte pages, fully associative, 48 entries"                                                                                                                         },\r
+  { 0x63, "TLB",      "Data TLB: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries and a separate array with 1 GByte pages, 4-way set associative, 4 entries"                                       },\r
+  { 0x64, "TLB",      "Data TLB: 4 KByte pages, 4-way set associative, 512 entries"                                                                                                                           },\r
+  { 0x66, "Cache",    "1st-level data cache: 8 KByte, 4-way set associative, 64 byte line size"                                                                                                               },\r
+  { 0x67, "Cache",    "1st-level data cache: 16 KByte, 4-way set associative, 64 byte line size"                                                                                                              },\r
+  { 0x68, "Cache",    "1st-level data cache: 32 KByte, 4-way set associative, 64 byte line size"                                                                                                              },\r
+  { 0x6A, "Cache",    "uTLB: 4 KByte pages, 8-way set associative, 64 entries"                                                                                                                                },\r
+  { 0x6B, "Cache",    "DTLB: 4 KByte pages, 8-way set associative, 256 entries"                                                                                                                               },\r
+  { 0x6C, "Cache",    "DTLB: 2M/4M pages, 8-way set associative, 128 entries"                                                                                                                                 },\r
+  { 0x6D, "Cache",    "DTLB: 1 GByte pages, fully associative, 16 entries"                                                                                                                                    },\r
+  { 0x70, "Cache",    "Trace cache: 12 K-uop, 8-way set associative"                                                                                                                                          },\r
+  { 0x71, "Cache",    "Trace cache: 16 K-uop, 8-way set associative"                                                                                                                                          },\r
+  { 0x72, "Cache",    "Trace cache: 32 K-uop, 8-way set associative"                                                                                                                                          },\r
+  { 0x76, "TLB",      "Instruction TLB: 2M/4M pages, fully associative, 8 entries"                                                                                                                            },\r
+  { 0x78, "Cache",    "2nd-level cache: 1 MByte, 4-way set associative, 64byte line size"                                                                                                                     },\r
+  { 0x79, "Cache",    "2nd-level cache: 128 KByte, 8-way set associative, 64 byte line size, 2 lines per sector"                                                                                              },\r
+  { 0x7A, "Cache",    "2nd-level cache: 256 KByte, 8-way set associative, 64 byte line size, 2 lines per sector"                                                                                              },\r
+  { 0x7B, "Cache",    "2nd-level cache: 512 KByte, 8-way set associative, 64 byte line size, 2 lines per sector"                                                                                              },\r
+  { 0x7C, "Cache",    "2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size, 2 lines per sector"                                                                                                },\r
+  { 0x7D, "Cache",    "2nd-level cache: 2 MByte, 8-way set associative, 64byte line size"                                                                                                                     },\r
+  { 0x7F, "Cache",    "2nd-level cache: 512 KByte, 2-way set associative, 64-byte line size"                                                                                                                  },\r
+  { 0x80, "Cache",    "2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size"                                                                                                                  },\r
+  { 0x82, "Cache",    "2nd-level cache: 256 KByte, 8-way set associative, 32 byte line size"                                                                                                                  },\r
+  { 0x83, "Cache",    "2nd-level cache: 512 KByte, 8-way set associative, 32 byte line size"                                                                                                                  },\r
+  { 0x84, "Cache",    "2nd-level cache: 1 MByte, 8-way set associative, 32 byte line size"                                                                                                                    },\r
+  { 0x85, "Cache",    "2nd-level cache: 2 MByte, 8-way set associative, 32 byte line size"                                                                                                                    },\r
+  { 0x86, "Cache",    "2nd-level cache: 512 KByte, 4-way set associative, 64 byte line size"                                                                                                                  },\r
+  { 0x87, "Cache",    "2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size"                                                                                                                    },\r
+  { 0xA0, "DTLB",     "DTLB: 4k pages, fully associative, 32 entries"                                                                                                                                         },\r
+  { 0xB0, "TLB",      "Instruction TLB: 4 KByte pages, 4-way set associative, 128 entries"                                                                                                                    },\r
+  { 0xB1, "TLB",      "Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries"                                                                                                             },\r
+  { 0xB2, "TLB",      "Instruction TLB: 4KByte pages, 4-way set associative, 64 entries"                                                                                                                      },\r
+  { 0xB3, "TLB",      "Data TLB: 4 KByte pages, 4-way set associative, 128 entries"                                                                                                                           },\r
+  { 0xB4, "TLB",      "Data TLB1: 4 KByte pages, 4-way associative, 256 entries"                                                                                                                              },\r
+  { 0xB5, "TLB",      "Instruction TLB: 4KByte pages, 8-way set associative, 64 entries"                                                                                                                      },\r
+  { 0xB6, "TLB",      "Instruction TLB: 4KByte pages, 8-way set associative, 128 entries"                                                                                                                     },\r
+  { 0xBA, "TLB",      "Data TLB1: 4 KByte pages, 4-way associative, 64 entries"                                                                                                                               },\r
+  { 0xC0, "TLB",      "Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries"                                                                                                                     },\r
+  { 0xC1, "STLB",     "Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, 1024 entries"                                                                                                           },\r
+  { 0xC2, "DTLB",     "DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries"                                                                                                                            },\r
+  { 0xC3, "STLB",     "Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative, 1536 entries. Also 1GBbyte pages, 4-way, 16 entries."                                                                 },\r
+  { 0xC4, "DTLB",     "DTLB: 2M/4M Byte pages, 4-way associative, 32 entries"                                                                                                                                 },\r
+  { 0xCA, "STLB",     "Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries"                                                                                                                   },\r
+  { 0xD0, "Cache",    "3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size"                                                                                                                  },\r
+  { 0xD1, "Cache",    "3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size"                                                                                                                    },\r
+  { 0xD2, "Cache",    "3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size"                                                                                                                    },\r
+  { 0xD6, "Cache",    "3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size"                                                                                                                    },\r
+  { 0xD7, "Cache",    "3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size"                                                                                                                    },\r
+  { 0xD8, "Cache",    "3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size"                                                                                                                    },\r
+  { 0xDC, "Cache",    "3rd-level cache: 1.5 MByte, 12-way set associative, 64 byte line size"                                                                                                                 },\r
+  { 0xDD, "Cache",    "3rd-level cache: 3 MByte, 12-way set associative, 64 byte line size"                                                                                                                   },\r
+  { 0xDE, "Cache",    "3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size"                                                                                                                   },\r
+  { 0xE2, "Cache",    "3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size"                                                                                                                   },\r
+  { 0xE3, "Cache",    "3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size"                                                                                                                   },\r
+  { 0xE4, "Cache",    "3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size"                                                                                                                   },\r
+  { 0xEA, "Cache",    "3rd-level cache: 12MByte, 24-way set associative, 64 byte line size"                                                                                                                   },\r
+  { 0xEB, "Cache",    "3rd-level cache: 18MByte, 24-way set associative, 64 byte line size"                                                                                                                   },\r
+  { 0xEC, "Cache",    "3rd-level cache: 24MByte, 24-way set associative, 64 byte line size"                                                                                                                   },\r
+  { 0xF0, "Prefetch", "64-Byte prefetching"                                                                                                                                                                   },\r
+  { 0xF1, "Prefetch", "128-Byte prefetching"                                                                                                                                                                  },\r
+  { 0xFE, "General",  "CPUID leaf 2 does not report TLB descriptor information; use CPUID leaf 18H to query TLB and other address translation parameters."                                                    },\r
+  { 0xFF, "General",  "CPUID leaf 2 does not report cache descriptor information, use CPUID leaf 4 to query cache parameters"                                                                                 }\r
 };\r
 \r
 ///\r
 /// The maximum supported CPUID leaf index starting from leaf 0x00000000.\r
 ///\r
-UINT32  gMaximumBasicFunction    = CPUID_SIGNATURE;\r
+UINT32  gMaximumBasicFunction = CPUID_SIGNATURE;\r
 \r
 ///\r
 /// The maximum supported CPUID leaf index starting from leaf 0x80000000.\r
@@ -170,11 +170,11 @@ CpuidSignature (
   VOID\r
   )\r
 {\r
-  UINT32 Eax;\r
-  UINT32 Ebx;\r
-  UINT32 Ecx;\r
-  UINT32 Edx;\r
-  CHAR8  Signature[13];\r
+  UINT32  Eax;\r
+  UINT32  Ebx;\r
+  UINT32  Ecx;\r
+  UINT32  Edx;\r
+  CHAR8   Signature[13];\r
 \r
   AsmCpuid (CPUID_SIGNATURE, &Eax, &Ebx, &Ecx, &Edx);\r
 \r
@@ -184,7 +184,7 @@ CpuidSignature (
   *(UINT32 *)(Signature + 0) = Ebx;\r
   *(UINT32 *)(Signature + 4) = Edx;\r
   *(UINT32 *)(Signature + 8) = Ecx;\r
-  Signature [12] = 0;\r
+  Signature[12]              = 0;\r
   Print (L"  Signature = %a\n", Signature);\r
 \r
   gMaximumBasicFunction = Eax;\r
@@ -221,7 +221,7 @@ CpuidVersionInfo (
   }\r
 \r
   DisplayModel = Eax.Bits.Model;\r
-  if (Eax.Bits.FamilyId == 0x06 || Eax.Bits.FamilyId == 0x0f) {\r
+  if ((Eax.Bits.FamilyId == 0x06) || (Eax.Bits.FamilyId == 0x0f)) {\r
     DisplayModel |= (Eax.Bits.ExtendedModelId << 4);\r
   }\r
 \r
@@ -314,12 +314,14 @@ LookupCacheDescription (
   if (CacheDescriptor == 0x00) {\r
     return NULL;\r
   }\r
+\r
   NumDescriptors = sizeof (mCpuidCacheInfoDescription)/sizeof (mCpuidCacheInfoDescription[0]);\r
   for (Descriptor = 0; Descriptor < NumDescriptors; Descriptor++) {\r
     if (CacheDescriptor == mCpuidCacheInfoDescription[Descriptor].CacheDescriptor) {\r
       return &mCpuidCacheInfoDescription[Descriptor];\r
     }\r
   }\r
+\r
   return NULL;\r
 }\r
 \r
@@ -354,13 +356,15 @@ CpuidCacheInfo (
     for (Index = 1; Index < 4; Index++) {\r
       CacheDescription = LookupCacheDescription (Eax.CacheDescriptor[Index]);\r
       if (CacheDescription != NULL) {\r
-        Print (L"  %-8a %a\n",\r
+        Print (\r
+          L"  %-8a %a\n",\r
           CacheDescription->Type,\r
           CacheDescription->Description\r
           );\r
       }\r
     }\r
   }\r
+\r
   if (Ebx.Bits.NotValid == 0) {\r
     //\r
     // Process Ebx.CacheDescriptor[0..3]\r
@@ -368,13 +372,15 @@ CpuidCacheInfo (
     for (Index = 0; Index < 4; Index++) {\r
       CacheDescription = LookupCacheDescription (Ebx.CacheDescriptor[Index]);\r
       if (CacheDescription != NULL) {\r
-        Print (L"  %-8a %a\n",\r
+        Print (\r
+          L"  %-8a %a\n",\r
           CacheDescription->Type,\r
           CacheDescription->Description\r
           );\r
       }\r
     }\r
   }\r
+\r
   if (Ecx.Bits.NotValid == 0) {\r
     //\r
     // Process Ecx.CacheDescriptor[0..3]\r
@@ -382,13 +388,15 @@ CpuidCacheInfo (
     for (Index = 0; Index < 4; Index++) {\r
       CacheDescription = LookupCacheDescription (Ecx.CacheDescriptor[Index]);\r
       if (CacheDescription != NULL) {\r
-        Print (L"  %-8a %a\n",\r
+        Print (\r
+          L"  %-8a %a\n",\r
           CacheDescription->Type,\r
           CacheDescription->Description\r
           );\r
       }\r
     }\r
   }\r
+\r
   if (Edx.Bits.NotValid == 0) {\r
     //\r
     // Process Edx.CacheDescriptor[0..3]\r
@@ -396,7 +404,8 @@ CpuidCacheInfo (
     for (Index = 0; Index < 4; Index++) {\r
       CacheDescription = LookupCacheDescription (Edx.CacheDescriptor[Index]);\r
       if (CacheDescription != NULL) {\r
-        Print (L"  %-8a %a\n",\r
+        Print (\r
+          L"  %-8a %a\n",\r
           CacheDescription->Type,\r
           CacheDescription->Description\r
           );\r
@@ -457,8 +466,12 @@ CpuidCacheParams (
   CacheLevel = 0;\r
   do {\r
     AsmCpuidEx (\r
-      CPUID_CACHE_PARAMS, CacheLevel,\r
-      &Eax.Uint32, &Ebx.Uint32, &Ecx, &Edx.Uint32\r
+      CPUID_CACHE_PARAMS,\r
+      CacheLevel,\r
+      &Eax.Uint32,\r
+      &Ebx.Uint32,\r
+      &Ecx,\r
+      &Edx.Uint32\r
       );\r
     if (Eax.Bits.CacheType != CPUID_CACHE_PARAMS_CACHE_TYPE_NULL) {\r
       Print (L"CPUID_CACHE_PARAMS (Leaf %08x, Sub-Leaf %08x)\n", CPUID_CACHE_PARAMS, CacheLevel);\r
@@ -472,11 +485,12 @@ CpuidCacheParams (
       PRINT_BIT_FIELD (Ebx, LineSize);\r
       PRINT_BIT_FIELD (Ebx, LinePartitions);\r
       PRINT_BIT_FIELD (Ebx, Ways);\r
-      PRINT_VALUE     (Ecx, NumberOfSets);\r
+      PRINT_VALUE (Ecx, NumberOfSets);\r
       PRINT_BIT_FIELD (Edx, Invalidate);\r
       PRINT_BIT_FIELD (Edx, CacheInclusiveness);\r
       PRINT_BIT_FIELD (Edx, ComplexCacheIndexing);\r
     }\r
+\r
     CacheLevel++;\r
   } while (Eax.Bits.CacheType != CPUID_CACHE_PARAMS_CACHE_TYPE_NULL);\r
 }\r
@@ -585,15 +599,21 @@ CpuidStructuredExtendedFeatureFlags (
   AsmCpuidEx (\r
     CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS,\r
     CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO,\r
-    &Eax, NULL, NULL, NULL\r
+    &Eax,\r
+    NULL,\r
+    NULL,\r
+    NULL\r
     );\r
   for (SubLeaf = 0; SubLeaf <= Eax; SubLeaf++) {\r
     AsmCpuidEx (\r
       CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS,\r
       SubLeaf,\r
-      NULL, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32\r
+      NULL,\r
+      &Ebx.Uint32,\r
+      &Ecx.Uint32,\r
+      &Edx.Uint32\r
       );\r
-    if (Ebx.Uint32 != 0 || Ecx.Uint32 != 0 || Edx.Uint32 != 0) {\r
+    if ((Ebx.Uint32 != 0) || (Ecx.Uint32 != 0) || (Edx.Uint32 != 0)) {\r
       Print (L"CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS (Leaf %08x, Sub-Leaf %08x)\n", CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS, SubLeaf);\r
       Print (L"  EAX:%08x  EBX:%08x  ECX:%08x  EDX:%08x\n", Eax, Ebx.Uint32, Ecx.Uint32, Edx.Uint32);\r
       PRINT_BIT_FIELD (Ebx, FSGSBASE);\r
@@ -713,7 +733,7 @@ CpuidArchitecturalPerformanceMonitoring (
 **/\r
 VOID\r
 CpuidExtendedTopology (\r
-  UINT32                       LeafFunction\r
+  UINT32  LeafFunction\r
   )\r
 {\r
   CPUID_EXTENDED_TOPOLOGY_EAX  Eax;\r
@@ -725,6 +745,7 @@ CpuidExtendedTopology (
   if (LeafFunction > gMaximumBasicFunction) {\r
     return;\r
   }\r
+\r
   if ((LeafFunction != CPUID_EXTENDED_TOPOLOGY) && (LeafFunction != CPUID_V2_EXTENDED_TOPOLOGY)) {\r
     return;\r
   }\r
@@ -732,23 +753,29 @@ CpuidExtendedTopology (
   LevelNumber = 0;\r
   for (LevelNumber = 0; ; LevelNumber++) {\r
     AsmCpuidEx (\r
-      LeafFunction, LevelNumber,\r
-      &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx\r
+      LeafFunction,\r
+      LevelNumber,\r
+      &Eax.Uint32,\r
+      &Ebx.Uint32,\r
+      &Ecx.Uint32,\r
+      &Edx\r
       );\r
     if (Ecx.Bits.LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID) {\r
       break;\r
     }\r
+\r
     Print (\r
       L"%a (Leaf %08x, Sub-Leaf %08x)\n",\r
       LeafFunction == CPUID_EXTENDED_TOPOLOGY ? "CPUID_EXTENDED_TOPOLOGY" : "CPUID_V2_EXTENDED_TOPOLOGY",\r
-      LeafFunction, LevelNumber\r
+      LeafFunction,\r
+      LevelNumber\r
       );\r
     Print (L"  EAX:%08x  EBX:%08x  ECX:%08x  EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx);\r
     PRINT_BIT_FIELD (Eax, ApicIdShift);\r
     PRINT_BIT_FIELD (Ebx, LogicalProcessors);\r
     PRINT_BIT_FIELD (Ecx, LevelNumber);\r
     PRINT_BIT_FIELD (Ecx, LevelType);\r
-    PRINT_VALUE     (Edx, x2APIC_ID);\r
+    PRINT_VALUE (Edx, x2APIC_ID);\r
   }\r
 }\r
 \r
@@ -767,8 +794,12 @@ CpuidExtendedStateSubLeaf (
   UINT32                             Edx;\r
 \r
   AsmCpuidEx (\r
-    CPUID_EXTENDED_STATE, CPUID_EXTENDED_STATE_SUB_LEAF,\r
-    &Eax.Uint32, &Ebx, &Ecx.Uint32, &Edx\r
+    CPUID_EXTENDED_STATE,\r
+    CPUID_EXTENDED_STATE_SUB_LEAF,\r
+    &Eax.Uint32,\r
+    &Ebx,\r
+    &Ecx.Uint32,\r
+    &Edx\r
     );\r
   Print (L"CPUID_EXTENDED_STATE (Leaf %08x, Sub-Leaf %08x)\n", CPUID_EXTENDED_STATE, CPUID_EXTENDED_STATE_SUB_LEAF);\r
   Print (L"  EAX:%08x  EBX:%08x  ECX:%08x  EDX:%08x\n", Eax.Uint32, Ebx, Ecx.Uint32, Edx);\r
@@ -776,12 +807,12 @@ CpuidExtendedStateSubLeaf (
   PRINT_BIT_FIELD (Eax, XSAVEC);\r
   PRINT_BIT_FIELD (Eax, XGETBV);\r
   PRINT_BIT_FIELD (Eax, XSAVES);\r
-  PRINT_VALUE     (Ebx, EnabledSaveStateSize_XCR0_IA32_XSS);\r
+  PRINT_VALUE (Ebx, EnabledSaveStateSize_XCR0_IA32_XSS);\r
   PRINT_BIT_FIELD (Ecx, XCR0);\r
   PRINT_BIT_FIELD (Ecx, HWPState);\r
   PRINT_BIT_FIELD (Ecx, PT);\r
   PRINT_BIT_FIELD (Ecx, XCR0_1);\r
-  PRINT_VALUE     (Edx, IA32_XSS_Supported_32_63);\r
+  PRINT_VALUE (Edx, IA32_XSS_Supported_32_63);\r
 }\r
 \r
 /**\r
@@ -801,14 +832,18 @@ CpuidExtendedStateSizeOffset (
 \r
   for (SubLeaf = CPUID_EXTENDED_STATE_SIZE_OFFSET; SubLeaf < 32; SubLeaf++) {\r
     AsmCpuidEx (\r
-      CPUID_EXTENDED_STATE, SubLeaf,\r
-      &Eax, &Ebx, &Ecx.Uint32, &Edx\r
+      CPUID_EXTENDED_STATE,\r
+      SubLeaf,\r
+      &Eax,\r
+      &Ebx,\r
+      &Ecx.Uint32,\r
+      &Edx\r
       );\r
     if (Edx != 0) {\r
       Print (L"CPUID_EXTENDED_STATE (Leaf %08x, Sub-Leaf %08x)\n", CPUID_EXTENDED_STATE, SubLeaf);\r
       Print (L"  EAX:%08x  EBX:%08x  ECX:%08x  EDX:%08x\n", Eax, Ebx, Ecx.Uint32, Edx);\r
-      PRINT_VALUE     (Eax, FeatureSaveStateSize);\r
-      PRINT_VALUE     (Ebx, FeatureSaveStateOffset);\r
+      PRINT_VALUE (Eax, FeatureSaveStateSize);\r
+      PRINT_VALUE (Ebx, FeatureSaveStateOffset);\r
       PRINT_BIT_FIELD (Ecx, XSS);\r
       PRINT_BIT_FIELD (Ecx, Compacted);\r
     }\r
@@ -834,8 +869,12 @@ CpuidExtendedStateMainLeaf (
   }\r
 \r
   AsmCpuidEx (\r
-    CPUID_EXTENDED_STATE, CPUID_EXTENDED_STATE_MAIN_LEAF,\r
-    &Eax.Uint32, &Ebx, &Ecx, &Edx\r
+    CPUID_EXTENDED_STATE,\r
+    CPUID_EXTENDED_STATE_MAIN_LEAF,\r
+    &Eax.Uint32,\r
+    &Ebx,\r
+    &Ecx,\r
+    &Edx\r
     );\r
   Print (L"CPUID_EXTENDED_STATE (Leaf %08x, Sub-Leaf %08x)\n", CPUID_EXTENDED_STATE, CPUID_EXTENDED_STATE_MAIN_LEAF);\r
   Print (L"  EAX:%08x  EBX:%08x  ECX:%08x  EDX:%08x\n", Eax.Uint32, Ebx, Ecx, Edx);\r
@@ -847,9 +886,9 @@ CpuidExtendedStateMainLeaf (
   PRINT_BIT_FIELD (Eax, IA32_XSS);\r
   PRINT_BIT_FIELD (Eax, PKRU);\r
   PRINT_BIT_FIELD (Eax, IA32_XSS_2);\r
-  PRINT_VALUE     (Ebx, EnabledSaveStateSize);\r
-  PRINT_VALUE     (Ecx, SupportedSaveStateSize);\r
-  PRINT_VALUE     (Edx, XCR0_Supported_32_63);\r
+  PRINT_VALUE (Ebx, EnabledSaveStateSize);\r
+  PRINT_VALUE (Ecx, SupportedSaveStateSize);\r
+  PRINT_VALUE (Edx, XCR0_Supported_32_63);\r
 \r
   CpuidExtendedStateSubLeaf ();\r
   CpuidExtendedStateSizeOffset ();\r
@@ -864,20 +903,24 @@ CpuidIntelRdtMonitoringEnumerationSubLeaf (
   VOID\r
   )\r
 {\r
-  UINT32                                                  Ebx;\r
-  CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF_EDX     Edx;\r
+  UINT32                                               Ebx;\r
+  CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF_EDX  Edx;\r
 \r
   if (CPUID_INTEL_RDT_MONITORING > gMaximumBasicFunction) {\r
     return;\r
   }\r
 \r
   AsmCpuidEx (\r
-    CPUID_INTEL_RDT_MONITORING, CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF,\r
-    NULL, &Ebx, NULL, &Edx.Uint32\r
+    CPUID_INTEL_RDT_MONITORING,\r
+    CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF,\r
+    NULL,\r
+    &Ebx,\r
+    NULL,\r
+    &Edx.Uint32\r
     );\r
   Print (L"CPUID_INTEL_RDT_MONITORING (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_RDT_MONITORING, CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF);\r
   Print (L"  EAX:%08x  EBX:%08x  ECX:%08x  EDX:%08x\n", 0, Ebx, 0, Edx.Uint32);\r
-  PRINT_VALUE     (Ebx, Maximum_RMID_Range);\r
+  PRINT_VALUE (Ebx, Maximum_RMID_Range);\r
   PRINT_BIT_FIELD (Edx, L3CacheRDT_M);\r
 }\r
 \r
@@ -890,22 +933,26 @@ CpuidIntelRdtMonitoringL3CacheCapabilitySubLeaf (
   VOID\r
   )\r
 {\r
-  UINT32                                                 Ebx;\r
-  UINT32                                                 Ecx;\r
-  CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF_EDX       Edx;\r
+  UINT32                                            Ebx;\r
+  UINT32                                            Ecx;\r
+  CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF_EDX  Edx;\r
 \r
   if (CPUID_INTEL_RDT_MONITORING > gMaximumBasicFunction) {\r
     return;\r
   }\r
 \r
   AsmCpuidEx (\r
-    CPUID_INTEL_RDT_MONITORING, CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF,\r
-    NULL, &Ebx, &Ecx, &Edx.Uint32\r
+    CPUID_INTEL_RDT_MONITORING,\r
+    CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF,\r
+    NULL,\r
+    &Ebx,\r
+    &Ecx,\r
+    &Edx.Uint32\r
     );\r
   Print (L"CPUID_INTEL_RDT_MONITORING (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_RDT_MONITORING, CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF);\r
   Print (L"  EAX:%08x  EBX:%08x  ECX:%08x  EDX:%08x\n", 0, Ebx, Ecx, Edx.Uint32);\r
-  PRINT_VALUE     (Ebx, OccupancyConversionFactor);\r
-  PRINT_VALUE     (Ecx, Maximum_RMID_Range);\r
+  PRINT_VALUE (Ebx, OccupancyConversionFactor);\r
+  PRINT_VALUE (Ecx, Maximum_RMID_Range);\r
   PRINT_BIT_FIELD (Edx, L3CacheOccupancyMonitoring);\r
   PRINT_BIT_FIELD (Edx, L3CacheTotalBandwidthMonitoring);\r
   PRINT_BIT_FIELD (Edx, L3CacheLocalBandwidthMonitoring);\r
@@ -927,13 +974,17 @@ CpuidIntelRdtAllocationMemoryBandwidthSubLeaf (
   CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_EDX  Edx;\r
 \r
   AsmCpuidEx (\r
-    CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF,\r
-    &Eax.Uint32, &Ebx, &Ecx.Uint32, &Edx.Uint32\r
+    CPUID_INTEL_RDT_ALLOCATION,\r
+    CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF,\r
+    &Eax.Uint32,\r
+    &Ebx,\r
+    &Ecx.Uint32,\r
+    &Edx.Uint32\r
     );\r
   Print (L"CPUID_INTEL_RDT_ALLOCATION (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF);\r
   Print (L"  EAX:%08x  EBX:%08x  ECX:%08x  EDX:%08x\n", Eax.Uint32, Ebx, Ecx.Uint32, Edx.Uint32);\r
   PRINT_BIT_FIELD (Eax, MaximumMBAThrottling);\r
-  PRINT_VALUE     (Ebx, AllocationUnitBitMap);\r
+  PRINT_VALUE (Ebx, AllocationUnitBitMap);\r
   PRINT_BIT_FIELD (Ecx, Liner);\r
   PRINT_BIT_FIELD (Edx, HighestCosNumber);\r
 }\r
@@ -954,13 +1005,17 @@ CpuidIntelRdtAllocationL3CacheSubLeaf (
   CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EDX  Edx;\r
 \r
   AsmCpuidEx (\r
-    CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF,\r
-    &Eax.Uint32, &Ebx, &Ecx.Uint32, &Edx.Uint32\r
+    CPUID_INTEL_RDT_ALLOCATION,\r
+    CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF,\r
+    &Eax.Uint32,\r
+    &Ebx,\r
+    &Ecx.Uint32,\r
+    &Edx.Uint32\r
     );\r
   Print (L"CPUID_INTEL_RDT_ALLOCATION (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF);\r
   Print (L"  EAX:%08x  EBX:%08x  ECX:%08x  EDX:%08x\n", Eax.Uint32, Ebx, Ecx.Uint32, Edx.Uint32);\r
   PRINT_BIT_FIELD (Eax, CapacityLength);\r
-  PRINT_VALUE     (Ebx, AllocationUnitBitMap);\r
+  PRINT_VALUE (Ebx, AllocationUnitBitMap);\r
   PRINT_BIT_FIELD (Ecx, CodeDataPrioritization);\r
   PRINT_BIT_FIELD (Edx, HighestCosNumber);\r
 }\r
@@ -980,13 +1035,17 @@ CpuidIntelRdtAllocationL2CacheSubLeaf (
   CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EDX  Edx;\r
 \r
   AsmCpuidEx (\r
-    CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF,\r
-    &Eax.Uint32, &Ebx, NULL, &Edx.Uint32\r
+    CPUID_INTEL_RDT_ALLOCATION,\r
+    CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF,\r
+    &Eax.Uint32,\r
+    &Ebx,\r
+    NULL,\r
+    &Edx.Uint32\r
     );\r
   Print (L"CPUID_INTEL_RDT_ALLOCATION (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF);\r
   Print (L"  EAX:%08x  EBX:%08x  ECX:%08x  EDX:%08x\n", Eax.Uint32, Ebx, 0, Edx.Uint32);\r
   PRINT_BIT_FIELD (Eax, CapacityLength);\r
-  PRINT_VALUE     (Ebx, AllocationUnitBitMap);\r
+  PRINT_VALUE (Ebx, AllocationUnitBitMap);\r
   PRINT_BIT_FIELD (Edx, HighestCosNumber);\r
 }\r
 \r
@@ -1006,8 +1065,12 @@ CpuidIntelRdtAllocationMainLeaf (
   }\r
 \r
   AsmCpuidEx (\r
-    CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF,\r
-    NULL, &Ebx.Uint32, NULL, NULL\r
+    CPUID_INTEL_RDT_ALLOCATION,\r
+    CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF,\r
+    NULL,\r
+    &Ebx.Uint32,\r
+    NULL,\r
+    NULL\r
     );\r
   Print (L"CPUID_INTEL_RDT_ALLOCATION (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF);\r
   Print (L"  EAX:%08x  EBX:%08x  ECX:%08x  EDX:%08x\n", 0, Ebx.Uint32, 0, 0);\r
@@ -1033,8 +1096,12 @@ CpuidEnumerationOfIntelSgxCapabilities0SubLeaf (
   CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EDX  Edx;\r
 \r
   AsmCpuidEx (\r
-    CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF,\r
-    &Eax.Uint32, &Ebx, NULL, &Edx.Uint32\r
+    CPUID_INTEL_SGX,\r
+    CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF,\r
+    &Eax.Uint32,\r
+    &Ebx,\r
+    NULL,\r
+    &Edx.Uint32\r
     );\r
   Print (L"CPUID_INTEL_SGX (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF);\r
   Print (L"  EAX:%08x  EBX:%08x  ECX:%08x  EDX:%08x\n", Eax.Uint32, Ebx, 0, Edx.Uint32);\r
@@ -1055,14 +1122,18 @@ CpuidEnumerationOfIntelSgxCapabilities1SubLeaf (
   VOID\r
   )\r
 {\r
-  UINT32                                       Eax;\r
-  UINT32                                       Ebx;\r
-  UINT32                                       Ecx;\r
-  UINT32                                       Edx;\r
+  UINT32  Eax;\r
+  UINT32  Ebx;\r
+  UINT32  Ecx;\r
+  UINT32  Edx;\r
 \r
   AsmCpuidEx (\r
-    CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF,\r
-    &Eax, &Ebx, &Ecx, &Edx\r
+    CPUID_INTEL_SGX,\r
+    CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF,\r
+    &Eax,\r
+    &Ebx,\r
+    &Ecx,\r
+    &Edx\r
     );\r
   Print (L"CPUID_INTEL_SGX (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF);\r
   Print (L"  EAX:%08x  EBX:%08x  ECX:%08x  EDX:%08x\n", Eax, Ebx, Ecx, Edx);\r
@@ -1086,8 +1157,12 @@ CpuidEnumerationOfIntelSgxResourcesSubLeaf (
   SubLeaf = CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF;\r
   do {\r
     AsmCpuidEx (\r
-      CPUID_INTEL_SGX, SubLeaf,\r
-      &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32\r
+      CPUID_INTEL_SGX,\r
+      SubLeaf,\r
+      &Eax.Uint32,\r
+      &Ebx.Uint32,\r
+      &Ecx.Uint32,\r
+      &Edx.Uint32\r
       );\r
     if (Eax.Bits.SubLeafType == 0x1) {\r
       Print (L"CPUID_INTEL_SGX (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_SGX, SubLeaf);\r
@@ -1099,6 +1174,7 @@ CpuidEnumerationOfIntelSgxResourcesSubLeaf (
       PRINT_BIT_FIELD (Ecx, LowSizeOfEpcSection);\r
       PRINT_BIT_FIELD (Edx, HighSizeOfEpcSection);\r
     }\r
+\r
     SubLeaf++;\r
   } while (Eax.Bits.SubLeafType == 0x1);\r
 }\r
@@ -1121,7 +1197,10 @@ CpuidEnumerationOfIntelSgx (
   AsmCpuidEx (\r
     CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS,\r
     CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO,\r
-    NULL, &Ebx.Uint32, NULL, NULL\r
+    NULL,\r
+    &Ebx.Uint32,\r
+    NULL,\r
+    NULL\r
     );\r
   if (Ebx.Bits.SGX != 1) {\r
     //\r
@@ -1153,8 +1232,12 @@ CpuidIntelProcessorTraceSubLeaf (
 \r
   for (SubLeaf = CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF; SubLeaf <= MaximumSubLeaf; SubLeaf++) {\r
     AsmCpuidEx (\r
-      CPUID_INTEL_PROCESSOR_TRACE, SubLeaf,\r
-      &Eax.Uint32, &Ebx.Uint32, NULL, NULL\r
+      CPUID_INTEL_PROCESSOR_TRACE,\r
+      SubLeaf,\r
+      &Eax.Uint32,\r
+      &Ebx.Uint32,\r
+      NULL,\r
+      NULL\r
       );\r
     Print (L"CPUID_INTEL_PROCESSOR_TRACE (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_PROCESSOR_TRACE, SubLeaf);\r
     Print (L"  EAX:%08x  EBX:%08x  ECX:%08x  EDX:%08x\n", Eax.Uint32, Ebx.Uint32, 0, 0);\r
@@ -1183,12 +1266,16 @@ CpuidIntelProcessorTraceMainLeaf (
   }\r
 \r
   AsmCpuidEx (\r
-    CPUID_INTEL_PROCESSOR_TRACE, CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF,\r
-    &Eax, &Ebx.Uint32, &Ecx.Uint32, NULL\r
+    CPUID_INTEL_PROCESSOR_TRACE,\r
+    CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF,\r
+    &Eax,\r
+    &Ebx.Uint32,\r
+    &Ecx.Uint32,\r
+    NULL\r
     );\r
   Print (L"CPUID_INTEL_PROCESSOR_TRACE (Leaf %08x, Sub-Leaf %08x)\n", CPUID_INTEL_PROCESSOR_TRACE, CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF);\r
   Print (L"  EAX:%08x  EBX:%08x  ECX:%08x  EDX:%08x\n", Eax, Ebx.Uint32, Ecx.Uint32, 0);\r
-  PRINT_VALUE     (Eax, MaximumSubLeaf);\r
+  PRINT_VALUE (Eax, MaximumSubLeaf);\r
   PRINT_BIT_FIELD (Ebx, Cr3Filter);\r
   PRINT_BIT_FIELD (Ebx, ConfigurablePsb);\r
   PRINT_BIT_FIELD (Ebx, IpTraceStopFiltering);\r
@@ -1270,11 +1357,15 @@ CpuidSocVendorBrandString (
   // 4 32-bit brand string values per leaf and an extra value to\r
   // null terminate the string.\r
   //\r
-  UINT32                              BrandString[3 * 4 + 1];\r
+  UINT32  BrandString[3 * 4 + 1];\r
 \r
   AsmCpuidEx (\r
-    CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING1,\r
-    &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32\r
+    CPUID_SOC_VENDOR,\r
+    CPUID_SOC_VENDOR_BRAND_STRING1,\r
+    &Eax.Uint32,\r
+    &Ebx.Uint32,\r
+    &Ecx.Uint32,\r
+    &Edx.Uint32\r
     );\r
   Print (L"CPUID_SOC_VENDOR (Leaf %08x, Sub-Leaf %08x)\n", CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING1);\r
   Print (L"  EAX:%08x  EBX:%08x  ECX:%08x  EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx.Uint32);\r
@@ -1284,8 +1375,12 @@ CpuidSocVendorBrandString (
   BrandString[3] = Edx.Uint32;\r
 \r
   AsmCpuidEx (\r
-    CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING2,\r
-    &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32\r
+    CPUID_SOC_VENDOR,\r
+    CPUID_SOC_VENDOR_BRAND_STRING2,\r
+    &Eax.Uint32,\r
+    &Ebx.Uint32,\r
+    &Ecx.Uint32,\r
+    &Edx.Uint32\r
     );\r
   Print (L"CPUID_SOC_VENDOR (Leaf %08x, Sub-Leaf %08x)\n", CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING2);\r
   Print (L"  EAX:%08x  EBX:%08x  ECX:%08x  EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx.Uint32);\r
@@ -1295,8 +1390,12 @@ CpuidSocVendorBrandString (
   BrandString[7] = Edx.Uint32;\r
 \r
   AsmCpuidEx (\r
-    CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING3,\r
-    &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32\r
+    CPUID_SOC_VENDOR,\r
+    CPUID_SOC_VENDOR_BRAND_STRING3,\r
+    &Eax.Uint32,\r
+    &Ebx.Uint32,\r
+    &Ecx.Uint32,\r
+    &Edx.Uint32\r
     );\r
   Print (L"CPUID_SOC_VENDOR (Leaf %08x, Sub-Leaf %08x)\n", CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING3);\r
   Print (L"  EAX:%08x  EBX:%08x  ECX:%08x  EDX:%08x\n", Eax.Uint32, Ebx.Uint32, Ecx.Uint32, Edx.Uint32);\r
@@ -1329,8 +1428,12 @@ CpuidSocVendor (
   }\r
 \r
   AsmCpuidEx (\r
-    CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_MAIN_LEAF,\r
-    &Eax, &Ebx.Uint32, &Ecx, &Edx\r
+    CPUID_SOC_VENDOR,\r
+    CPUID_SOC_VENDOR_MAIN_LEAF,\r
+    &Eax,\r
+    &Ebx.Uint32,\r
+    &Ecx,\r
+    &Edx\r
     );\r
   Print (L"CPUID_SOC_VENDOR (Leaf %08x, Sub-Leaf %08x)\n", CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_MAIN_LEAF);\r
   Print (L"  EAX:%08x  EBX:%08x  ECX:%08x  EDX:%08x\n", Eax, Ebx.Uint32, Ecx, Edx);\r
@@ -1338,11 +1441,12 @@ CpuidSocVendor (
     Print (L"  Not Supported\n");\r
     return;\r
   }\r
-  PRINT_VALUE     (Eax, MaxSOCID_Index);\r
+\r
+  PRINT_VALUE (Eax, MaxSOCID_Index);\r
   PRINT_BIT_FIELD (Ebx, SocVendorId);\r
   PRINT_BIT_FIELD (Ebx, IsVendorScheme);\r
-  PRINT_VALUE     (Ecx, ProjectID);\r
-  PRINT_VALUE     (Edx, SteppingID);\r
+  PRINT_VALUE (Ecx, ProjectID);\r
+  PRINT_VALUE (Edx, SteppingID);\r
   CpuidSocVendorBrandString ();\r
 }\r
 \r
@@ -1367,12 +1471,15 @@ CpuidDeterministicAddressTranslationParameters (
   AsmCpuidEx (\r
     CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS,\r
     CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_MAIN_LEAF,\r
-    &Eax, &Ebx.Uint32, &Ecx, &Edx.Uint32\r
+    &Eax,\r
+    &Ebx.Uint32,\r
+    &Ecx,\r
+    &Edx.Uint32\r
     );\r
   Print (L"CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS (Leaf %08x, Sub-Leaf %08x)\n", CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS, CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_MAIN_LEAF);\r
   Print (L"  EAX:%08x  EBX:%08x  ECX:%08x  EDX:%08x\n", Eax, Ebx.Uint32, Ecx, Edx.Uint32);\r
 \r
-  PRINT_VALUE     (Eax, MaxID_Index);\r
+  PRINT_VALUE (Eax, MaxID_Index);\r
   PRINT_BIT_FIELD (Ebx, Page4K);\r
   PRINT_BIT_FIELD (Ebx, Page2M);\r
   PRINT_BIT_FIELD (Ebx, Page4M);\r
@@ -1380,7 +1487,7 @@ CpuidDeterministicAddressTranslationParameters (
   PRINT_BIT_FIELD (Ebx, Partitioning);\r
   PRINT_BIT_FIELD (Ebx, Way);\r
 \r
-  PRINT_VALUE     (Ecx, NumberOfSets);\r
+  PRINT_VALUE (Ecx, NumberOfSets);\r
 \r
   PRINT_BIT_FIELD (Edx, TranslationCacheType);\r
   PRINT_BIT_FIELD (Edx, TranslationCacheLevel);\r
@@ -1402,7 +1509,7 @@ CpuidExtendedFunction (
   AsmCpuid (CPUID_EXTENDED_FUNCTION, &Eax, NULL, NULL, NULL);\r
   Print (L"CPUID_EXTENDED_FUNCTION (Leaf %08x)\n", CPUID_EXTENDED_FUNCTION);\r
   Print (L"  EAX:%08x  EBX:%08x  ECX:%08x  EDX:%08x\n", Eax, 0, 0, 0);\r
-  PRINT_VALUE     (Eax, MaximumExtendedFunction);\r
+  PRINT_VALUE (Eax, MaximumExtendedFunction);\r
 \r
   gMaximumExtendedFunction = Eax;\r
 }\r
@@ -1456,7 +1563,7 @@ CpuidProcessorBrandString (
   // 4 32-bit brand string values per leaf and an extra value to\r
   // null terminate the string.\r
   //\r
-  UINT32                   BrandString[3 * 4 + 1];\r
+  UINT32  BrandString[3 * 4 + 1];\r
 \r
   if (CPUID_BRAND_STRING1 <= gMaximumExtendedFunction) {\r
     AsmCpuid (CPUID_BRAND_STRING1, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);\r
@@ -1583,11 +1690,11 @@ UefiMain (
   CpuidVersionInfo ();\r
   CpuidCacheInfo ();\r
   CpuidSerialNumber ();\r
-  CpuidCacheParams();\r
+  CpuidCacheParams ();\r
   CpuidMonitorMwait ();\r
   CpuidThermalPowerManagement ();\r
   CpuidStructuredExtendedFeatureFlags ();\r
-  CpuidDirectCacheAccessInfo();\r
+  CpuidDirectCacheAccessInfo ();\r
   CpuidArchitecturalPerformanceMonitoring ();\r
   CpuidExtendedTopology (CPUID_EXTENDED_TOPOLOGY);\r
   CpuidExtendedStateMainLeaf ();\r

diff --git a/UefiCpuPkg/CpuDxe/CpuDxe.c b/UefiCpuPkg/CpuDxe/CpuDxe.c
index efa0bc33084e62ff6cf082b93b75d828e3726e81..00f3cb09572cfcb2308d0fef50ab269b74fe90cb 100644 (file)
--- a/UefiCpuPkg/CpuDxe/CpuDxe.c
+++ b/UefiCpuPkg/CpuDxe/CpuDxe.c
@@ -13,15 +13,15 @@
 //\r
 // Global Variables\r
 //\r
-BOOLEAN                   InterruptState = FALSE;\r
-EFI_HANDLE                mCpuHandle = NULL;\r
-BOOLEAN                   mIsFlushingGCD;\r
-BOOLEAN                   mIsAllocatingPageTable = FALSE;\r
-UINT64                    mValidMtrrAddressMask;\r
-UINT64                    mValidMtrrBitsMask;\r
-UINT64                    mTimerPeriod = 0;\r
-\r
-FIXED_MTRR    mFixedMtrrTable[] = {\r
+BOOLEAN     InterruptState = FALSE;\r
+EFI_HANDLE  mCpuHandle     = NULL;\r
+BOOLEAN     mIsFlushingGCD;\r
+BOOLEAN     mIsAllocatingPageTable = FALSE;\r
+UINT64      mValidMtrrAddressMask;\r
+UINT64      mValidMtrrBitsMask;\r
+UINT64      mTimerPeriod = 0;\r
+\r
+FIXED_MTRR  mFixedMtrrTable[] = {\r
   {\r
     MSR_IA32_MTRR_FIX64K_00000,\r
     0,\r
@@ -79,7 +79,6 @@ FIXED_MTRR    mFixedMtrrTable[] = {
   },\r
 };\r
 \r
-\r
 EFI_CPU_ARCH_PROTOCOL  gCpu = {\r
   CpuFlushCpuDataCache,\r
   CpuEnableInterrupt,\r
@@ -115,10 +114,10 @@ EFI_CPU_ARCH_PROTOCOL  gCpu = {
 EFI_STATUS\r
 EFIAPI\r
 CpuFlushCpuDataCache (\r
-  IN EFI_CPU_ARCH_PROTOCOL     *This,\r
-  IN EFI_PHYSICAL_ADDRESS      Start,\r
-  IN UINT64                    Length,\r
-  IN EFI_CPU_FLUSH_TYPE        FlushType\r
+  IN EFI_CPU_ARCH_PROTOCOL  *This,\r
+  IN EFI_PHYSICAL_ADDRESS   Start,\r
+  IN UINT64                 Length,\r
+  IN EFI_CPU_FLUSH_TYPE     FlushType\r
   )\r
 {\r
   if (FlushType == EfiCpuFlushTypeWriteBackInvalidate) {\r
@@ -132,7 +131,6 @@ CpuFlushCpuDataCache (
   }\r
 }\r
 \r
-\r
 /**\r
   Enables CPU interrupts.\r
 \r
@@ -145,7 +143,7 @@ CpuFlushCpuDataCache (
 EFI_STATUS\r
 EFIAPI\r
 CpuEnableInterrupt (\r
-  IN EFI_CPU_ARCH_PROTOCOL          *This\r
+  IN EFI_CPU_ARCH_PROTOCOL  *This\r
   )\r
 {\r
   EnableInterrupts ();\r
@@ -154,7 +152,6 @@ CpuEnableInterrupt (
   return EFI_SUCCESS;\r
 }\r
 \r
-\r
 /**\r
   Disables CPU interrupts.\r
 \r
@@ -167,7 +164,7 @@ CpuEnableInterrupt (
 EFI_STATUS\r
 EFIAPI\r
 CpuDisableInterrupt (\r
-  IN EFI_CPU_ARCH_PROTOCOL     *This\r
+  IN EFI_CPU_ARCH_PROTOCOL  *This\r
   )\r
 {\r
   DisableInterrupts ();\r
@@ -176,7 +173,6 @@ CpuDisableInterrupt (
   return EFI_SUCCESS;\r
 }\r
 \r
-\r
 /**\r
   Return the state of interrupts.\r
 \r
@@ -190,8 +186,8 @@ CpuDisableInterrupt (
 EFI_STATUS\r
 EFIAPI\r
 CpuGetInterruptState (\r
-  IN  EFI_CPU_ARCH_PROTOCOL     *This,\r
-  OUT BOOLEAN                   *State\r
+  IN  EFI_CPU_ARCH_PROTOCOL  *This,\r
+  OUT BOOLEAN                *State\r
   )\r
 {\r
   if (State == NULL) {\r
@@ -202,7 +198,6 @@ CpuGetInterruptState (
   return EFI_SUCCESS;\r
 }\r
 \r
-\r
 /**\r
   Generates an INIT to the CPU.\r
 \r
@@ -218,14 +213,13 @@ CpuGetInterruptState (
 EFI_STATUS\r
 EFIAPI\r
 CpuInit (\r
-  IN EFI_CPU_ARCH_PROTOCOL      *This,\r
-  IN EFI_CPU_INIT_TYPE          InitType\r
+  IN EFI_CPU_ARCH_PROTOCOL  *This,\r
+  IN EFI_CPU_INIT_TYPE      InitType\r
   )\r
 {\r
   return EFI_UNSUPPORTED;\r
 }\r
 \r
-\r
 /**\r
   Registers a function to be called from the CPU interrupt handler.\r
 \r
@@ -249,15 +243,14 @@ CpuInit (
 EFI_STATUS\r
 EFIAPI\r
 CpuRegisterInterruptHandler (\r
-  IN EFI_CPU_ARCH_PROTOCOL         *This,\r
-  IN EFI_EXCEPTION_TYPE            InterruptType,\r
-  IN EFI_CPU_INTERRUPT_HANDLER     InterruptHandler\r
+  IN EFI_CPU_ARCH_PROTOCOL      *This,\r
+  IN EFI_EXCEPTION_TYPE         InterruptType,\r
+  IN EFI_CPU_INTERRUPT_HANDLER  InterruptHandler\r
   )\r
 {\r
   return RegisterCpuInterruptHandler (InterruptType, InterruptHandler);\r
 }\r
 \r
-\r
 /**\r
   Returns a timer value from one of the CPU's internal timers. There is no\r
   inherent time interval between ticks but is a function of the CPU frequency.\r
@@ -284,14 +277,14 @@ CpuRegisterInterruptHandler (
 EFI_STATUS\r
 EFIAPI\r
 CpuGetTimerValue (\r
-  IN  EFI_CPU_ARCH_PROTOCOL     *This,\r
-  IN  UINT32                    TimerIndex,\r
-  OUT UINT64                    *TimerValue,\r
-  OUT UINT64                    *TimerPeriod OPTIONAL\r
+  IN  EFI_CPU_ARCH_PROTOCOL  *This,\r
+  IN  UINT32                 TimerIndex,\r
+  OUT UINT64                 *TimerValue,\r
+  OUT UINT64                 *TimerPeriod OPTIONAL\r
   )\r
 {\r
-  UINT64          BeginValue;\r
-  UINT64          EndValue;\r
+  UINT64  BeginValue;\r
+  UINT64  EndValue;\r
 \r
   if (TimerValue == NULL) {\r
     return EFI_INVALID_PARAMETER;\r
@@ -310,7 +303,7 @@ CpuGetTimerValue (
       //\r
       BeginValue = AsmReadTsc ();\r
       MicroSecondDelay (100);\r
-      EndValue   = AsmReadTsc ();\r
+      EndValue = AsmReadTsc ();\r
       //\r
       // Calculate the actual frequency\r
       //\r
@@ -323,6 +316,7 @@ CpuGetTimerValue (
                        NULL\r
                        );\r
     }\r
+\r
     *TimerPeriod = mTimerPeriod;\r
   }\r
 \r
@@ -339,7 +333,7 @@ CpuGetTimerValue (
 VOID\r
 EFIAPI\r
 SetMtrrsFromBuffer (\r
-  IN VOID *Buffer\r
+  IN VOID  *Buffer\r
   )\r
 {\r
   MtrrSetAllMtrrs (Buffer);\r
@@ -373,10 +367,10 @@ SetMtrrsFromBuffer (
 EFI_STATUS\r
 EFIAPI\r
 CpuSetMemoryAttributes (\r
-  IN EFI_CPU_ARCH_PROTOCOL     *This,\r
-  IN EFI_PHYSICAL_ADDRESS      BaseAddress,\r
-  IN UINT64                    Length,\r
-  IN UINT64                    Attributes\r
+  IN EFI_CPU_ARCH_PROTOCOL  *This,\r
+  IN EFI_PHYSICAL_ADDRESS   BaseAddress,\r
+  IN UINT64                 Length,\r
+  IN UINT64                 Attributes\r
   )\r
 {\r
   RETURN_STATUS             Status;\r
@@ -395,7 +389,7 @@ CpuSetMemoryAttributes (
   // to avoid unnecessary computing.\r
   //\r
   if (mIsFlushingGCD) {\r
-    DEBUG((DEBUG_VERBOSE, "  Flushing GCD\n"));\r
+    DEBUG ((DEBUG_VERBOSE, "  Flushing GCD\n"));\r
     return EFI_SUCCESS;\r
   }\r
 \r
@@ -410,11 +404,11 @@ CpuSetMemoryAttributes (
   // by page table memory allocation.\r
   //\r
   if (mIsAllocatingPageTable) {\r
-    DEBUG((DEBUG_VERBOSE, "  Allocating page table memory\n"));\r
+    DEBUG ((DEBUG_VERBOSE, "  Allocating page table memory\n"));\r
     return EFI_SUCCESS;\r
   }\r
 \r
-  CacheAttributes = Attributes & EFI_CACHE_ATTRIBUTE_MASK;\r
+  CacheAttributes  = Attributes & EFI_CACHE_ATTRIBUTE_MASK;\r
   MemoryAttributes = Attributes & EFI_MEMORY_ATTRIBUTE_MASK;\r
 \r
   if (Attributes != (CacheAttributes | MemoryAttributes)) {\r
@@ -427,30 +421,31 @@ CpuSetMemoryAttributes (
     }\r
 \r
     switch (CacheAttributes) {\r
-    case EFI_MEMORY_UC:\r
-      CacheType = CacheUncacheable;\r
-      break;\r
+      case EFI_MEMORY_UC:\r
+        CacheType = CacheUncacheable;\r
+        break;\r
 \r
-    case EFI_MEMORY_WC:\r
-      CacheType = CacheWriteCombining;\r
-      break;\r
+      case EFI_MEMORY_WC:\r
+        CacheType = CacheWriteCombining;\r
+        break;\r
 \r
-    case EFI_MEMORY_WT:\r
-      CacheType = CacheWriteThrough;\r
-      break;\r
+      case EFI_MEMORY_WT:\r
+        CacheType = CacheWriteThrough;\r
+        break;\r
 \r
-    case EFI_MEMORY_WP:\r
-      CacheType = CacheWriteProtected;\r
-      break;\r
+      case EFI_MEMORY_WP:\r
+        CacheType = CacheWriteProtected;\r
+        break;\r
 \r
-    case EFI_MEMORY_WB:\r
-      CacheType = CacheWriteBack;\r
-      break;\r
+      case EFI_MEMORY_WB:\r
+        CacheType = CacheWriteBack;\r
+        break;\r
 \r
-    default:\r
-      return EFI_INVALID_PARAMETER;\r
+      default:\r
+        return EFI_INVALID_PARAMETER;\r
     }\r
-    CurrentCacheType = MtrrGetMemoryAttribute(BaseAddress);\r
+\r
+    CurrentCacheType = MtrrGetMemoryAttribute (BaseAddress);\r
     if (CurrentCacheType != CacheType) {\r
       //\r
       // call MTRR library function\r
@@ -484,7 +479,8 @@ CpuSetMemoryAttributes (
           ASSERT (MpStatus == EFI_SUCCESS || MpStatus == EFI_NOT_STARTED);\r
         }\r
       }\r
-      if (EFI_ERROR(Status)) {\r
+\r
+      if (EFI_ERROR (Status)) {\r
         return Status;\r
       }\r
     }\r
@@ -507,15 +503,15 @@ InitializeMtrrMask (
   VOID\r
   )\r
 {\r
-  UINT32                              RegEax;\r
-  UINT8                               PhysicalAddressBits;\r
+  UINT32  RegEax;\r
+  UINT8   PhysicalAddressBits;\r
 \r
   AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);\r
 \r
   if (RegEax >= 0x80000008) {\r
     AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);\r
 \r
-    PhysicalAddressBits = (UINT8) RegEax;\r
+    PhysicalAddressBits = (UINT8)RegEax;\r
   } else {\r
     PhysicalAddressBits = 36;\r
   }\r
@@ -536,22 +532,22 @@ InitializeMtrrMask (
 **/\r
 UINT64\r
 GetMemorySpaceAttributeFromMtrrType (\r
-  IN UINT8                MtrrAttributes\r
+  IN UINT8  MtrrAttributes\r
   )\r
 {\r
   switch (MtrrAttributes) {\r
-  case MTRR_CACHE_UNCACHEABLE:\r
-    return EFI_MEMORY_UC;\r
-  case MTRR_CACHE_WRITE_COMBINING:\r
-    return EFI_MEMORY_WC;\r
-  case MTRR_CACHE_WRITE_THROUGH:\r
-    return EFI_MEMORY_WT;\r
-  case MTRR_CACHE_WRITE_PROTECTED:\r
-    return EFI_MEMORY_WP;\r
-  case MTRR_CACHE_WRITE_BACK:\r
-    return EFI_MEMORY_WB;\r
-  default:\r
-    return 0;\r
+    case MTRR_CACHE_UNCACHEABLE:\r
+      return EFI_MEMORY_UC;\r
+    case MTRR_CACHE_WRITE_COMBINING:\r
+      return EFI_MEMORY_WC;\r
+    case MTRR_CACHE_WRITE_THROUGH:\r
+      return EFI_MEMORY_WT;\r
+    case MTRR_CACHE_WRITE_PROTECTED:\r
+      return EFI_MEMORY_WP;\r
+    case MTRR_CACHE_WRITE_BACK:\r
+      return EFI_MEMORY_WB;\r
+    default:\r
+      return 0;\r
   }\r
 }\r
 \r
@@ -575,29 +571,33 @@ GetMemorySpaceAttributeFromMtrrType (
 **/\r
 EFI_STATUS\r
 SearchGcdMemorySpaces (\r
-  IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR     *MemorySpaceMap,\r
-  IN UINTN                               NumberOfDescriptors,\r
-  IN EFI_PHYSICAL_ADDRESS                BaseAddress,\r
-  IN UINT64                              Length,\r
-  OUT UINTN                              *StartIndex,\r
-  OUT UINTN                              *EndIndex\r
+  IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR  *MemorySpaceMap,\r
+  IN UINTN                            NumberOfDescriptors,\r
+  IN EFI_PHYSICAL_ADDRESS             BaseAddress,\r
+  IN UINT64                           Length,\r
+  OUT UINTN                           *StartIndex,\r
+  OUT UINTN                           *EndIndex\r
   )\r
 {\r
-  UINTN           Index;\r
+  UINTN  Index;\r
 \r
   *StartIndex = 0;\r
   *EndIndex   = 0;\r
   for (Index = 0; Index < NumberOfDescriptors; Index++) {\r
-    if (BaseAddress >= MemorySpaceMap[Index].BaseAddress &&\r
-        BaseAddress < MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length) {\r
+    if ((BaseAddress >= MemorySpaceMap[Index].BaseAddress) &&\r
+        (BaseAddress < MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length))\r
+    {\r
       *StartIndex = Index;\r
     }\r
-    if (BaseAddress + Length - 1 >= MemorySpaceMap[Index].BaseAddress &&\r
-        BaseAddress + Length - 1 < MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length) {\r
+\r
+    if ((BaseAddress + Length - 1 >= MemorySpaceMap[Index].BaseAddress) &&\r
+        (BaseAddress + Length - 1 < MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length))\r
+    {\r
       *EndIndex = Index;\r
       return EFI_SUCCESS;\r
     }\r
   }\r
+\r
   return EFI_NOT_FOUND;\r
 }\r
 \r
@@ -619,11 +619,11 @@ SearchGcdMemorySpaces (
 **/\r
 EFI_STATUS\r
 SetGcdMemorySpaceAttributes (\r
-  IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR     *MemorySpaceMap,\r
-  IN UINTN                               NumberOfDescriptors,\r
-  IN EFI_PHYSICAL_ADDRESS                BaseAddress,\r
-  IN UINT64                              Length,\r
-  IN UINT64                              Attributes\r
+  IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR  *MemorySpaceMap,\r
+  IN UINTN                            NumberOfDescriptors,\r
+  IN EFI_PHYSICAL_ADDRESS             BaseAddress,\r
+  IN UINT64                           Length,\r
+  IN UINT64                           Attributes\r
   )\r
 {\r
   EFI_STATUS            Status;\r
@@ -655,6 +655,7 @@ SetGcdMemorySpaceAttributes (
     if (MemorySpaceMap[Index].GcdMemoryType == EfiGcdMemoryTypeNonExistent) {\r
       continue;\r
     }\r
+\r
     //\r
     // Calculate the start and end address of the overlapping range\r
     //\r
@@ -663,11 +664,13 @@ SetGcdMemorySpaceAttributes (
     } else {\r
       RegionStart = MemorySpaceMap[Index].BaseAddress;\r
     }\r
+\r
     if (BaseAddress + Length - 1 < MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length) {\r
       RegionLength = BaseAddress + Length - RegionStart;\r
     } else {\r
       RegionLength = MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length - RegionStart;\r
     }\r
+\r
     //\r
     // Set memory attributes according to MTRR attribute and the original attribute of descriptor\r
     //\r
@@ -681,7 +684,6 @@ SetGcdMemorySpaceAttributes (
   return EFI_SUCCESS;\r
 }\r
 \r
-\r
 /**\r
   Refreshes the GCD Memory Space attributes according to MTRRs.\r
 \r
@@ -693,22 +695,22 @@ RefreshMemoryAttributesFromMtrr (
   VOID\r
   )\r
 {\r
-  EFI_STATUS                          Status;\r
-  UINTN                               Index;\r
-  UINTN                               SubIndex;\r
-  UINT64                              RegValue;\r
-  EFI_PHYSICAL_ADDRESS                BaseAddress;\r
-  UINT64                              Length;\r
-  UINT64                              Attributes;\r
-  UINT64                              CurrentAttributes;\r
-  UINT8                               MtrrType;\r
-  UINTN                               NumberOfDescriptors;\r
-  EFI_GCD_MEMORY_SPACE_DESCRIPTOR     *MemorySpaceMap;\r
-  UINT64                              DefaultAttributes;\r
-  VARIABLE_MTRR                       VariableMtrr[MTRR_NUMBER_OF_VARIABLE_MTRR];\r
-  MTRR_FIXED_SETTINGS                 MtrrFixedSettings;\r
-  UINT32                              FirmwareVariableMtrrCount;\r
-  UINT8                               DefaultMemoryType;\r
+  EFI_STATUS                       Status;\r
+  UINTN                            Index;\r
+  UINTN                            SubIndex;\r
+  UINT64                           RegValue;\r
+  EFI_PHYSICAL_ADDRESS             BaseAddress;\r
+  UINT64                           Length;\r
+  UINT64                           Attributes;\r
+  UINT64                           CurrentAttributes;\r
+  UINT8                            MtrrType;\r
+  UINTN                            NumberOfDescriptors;\r
+  EFI_GCD_MEMORY_SPACE_DESCRIPTOR  *MemorySpaceMap;\r
+  UINT64                           DefaultAttributes;\r
+  VARIABLE_MTRR                    VariableMtrr[MTRR_NUMBER_OF_VARIABLE_MTRR];\r
+  MTRR_FIXED_SETTINGS              MtrrFixedSettings;\r
+  UINT32                           FirmwareVariableMtrrCount;\r
+  UINT8                            DefaultMemoryType;\r
 \r
   FirmwareVariableMtrrCount = GetFirmwareVariableMtrrCount ();\r
   ASSERT (FirmwareVariableMtrrCount <= MTRR_NUMBER_OF_VARIABLE_MTRR);\r
@@ -738,7 +740,7 @@ RefreshMemoryAttributesFromMtrr (
                   );\r
   ASSERT_EFI_ERROR (Status);\r
 \r
-  DefaultMemoryType = (UINT8) MtrrGetDefaultMemoryType ();\r
+  DefaultMemoryType = (UINT8)MtrrGetDefaultMemoryType ();\r
   DefaultAttributes = GetMemorySpaceAttributeFromMtrrType (DefaultMemoryType);\r
 \r
   //\r
@@ -748,6 +750,7 @@ RefreshMemoryAttributesFromMtrr (
     if (MemorySpaceMap[Index].GcdMemoryType == EfiGcdMemoryTypeNonExistent) {\r
       continue;\r
     }\r
+\r
     gDS->SetMemorySpaceAttributes (\r
            MemorySpaceMap[Index].BaseAddress,\r
            MemorySpaceMap[Index].Length,\r
@@ -761,7 +764,8 @@ RefreshMemoryAttributesFromMtrr (
   //\r
   for (Index = 0; Index < FirmwareVariableMtrrCount; Index++) {\r
     if (VariableMtrr[Index].Valid &&\r
-        VariableMtrr[Index].Type == MTRR_CACHE_WRITE_BACK) {\r
+        (VariableMtrr[Index].Type == MTRR_CACHE_WRITE_BACK))\r
+    {\r
       SetGcdMemorySpaceAttributes (\r
         MemorySpaceMap,\r
         NumberOfDescriptors,\r
@@ -777,9 +781,10 @@ RefreshMemoryAttributesFromMtrr (
   //\r
   for (Index = 0; Index < FirmwareVariableMtrrCount; Index++) {\r
     if (VariableMtrr[Index].Valid &&\r
-        VariableMtrr[Index].Type != MTRR_CACHE_WRITE_BACK &&\r
-        VariableMtrr[Index].Type != MTRR_CACHE_UNCACHEABLE) {\r
-      Attributes = GetMemorySpaceAttributeFromMtrrType ((UINT8) VariableMtrr[Index].Type);\r
+        (VariableMtrr[Index].Type != MTRR_CACHE_WRITE_BACK) &&\r
+        (VariableMtrr[Index].Type != MTRR_CACHE_UNCACHEABLE))\r
+    {\r
+      Attributes = GetMemorySpaceAttributeFromMtrrType ((UINT8)VariableMtrr[Index].Type);\r
       SetGcdMemorySpaceAttributes (\r
         MemorySpaceMap,\r
         NumberOfDescriptors,\r
@@ -795,7 +800,8 @@ RefreshMemoryAttributesFromMtrr (
   //\r
   for (Index = 0; Index < FirmwareVariableMtrrCount; Index++) {\r
     if (VariableMtrr[Index].Valid &&\r
-        VariableMtrr[Index].Type == MTRR_CACHE_UNCACHEABLE) {\r
+        (VariableMtrr[Index].Type == MTRR_CACHE_UNCACHEABLE))\r
+    {\r
       SetGcdMemorySpaceAttributes (\r
         MemorySpaceMap,\r
         NumberOfDescriptors,\r
@@ -819,7 +825,7 @@ RefreshMemoryAttributesFromMtrr (
     // Check for continuous fixed MTRR sections\r
     //\r
     for (SubIndex = 0; SubIndex < 8; SubIndex++) {\r
-      MtrrType = (UINT8) RShiftU64 (RegValue, SubIndex * 8);\r
+      MtrrType          = (UINT8)RShiftU64 (RegValue, SubIndex * 8);\r
       CurrentAttributes = GetMemorySpaceAttributeFromMtrrType (MtrrType);\r
       if (Length == 0) {\r
         //\r
@@ -839,13 +845,15 @@ RefreshMemoryAttributesFromMtrr (
             Attributes\r
             );\r
           BaseAddress = mFixedMtrrTable[Index].BaseAddress + mFixedMtrrTable[Index].Length * SubIndex;\r
-          Length = 0;\r
-          Attributes = CurrentAttributes;\r
+          Length      = 0;\r
+          Attributes  = CurrentAttributes;\r
         }\r
       }\r
+\r
       Length += mFixedMtrrTable[Index].Length;\r
     }\r
   }\r
+\r
   //\r
   // Handle the last fixed MTRR region\r
   //\r
@@ -916,20 +924,20 @@ InitInterruptDescriptorTable (
   VOID\r
   )\r
 {\r
-  EFI_STATUS                     Status;\r
-  EFI_VECTOR_HANDOFF_INFO        *VectorInfoList;\r
-  EFI_VECTOR_HANDOFF_INFO        *VectorInfo;\r
+  EFI_STATUS               Status;\r
+  EFI_VECTOR_HANDOFF_INFO  *VectorInfoList;\r
+  EFI_VECTOR_HANDOFF_INFO  *VectorInfo;\r
 \r
   VectorInfo = NULL;\r
-  Status = EfiGetSystemConfigurationTable (&gEfiVectorHandoffTableGuid, (VOID **) &VectorInfoList);\r
-  if (Status == EFI_SUCCESS && VectorInfoList != NULL) {\r
+  Status     = EfiGetSystemConfigurationTable (&gEfiVectorHandoffTableGuid, (VOID **)&VectorInfoList);\r
+  if ((Status == EFI_SUCCESS) && (VectorInfoList != NULL)) {\r
     VectorInfo = VectorInfoList;\r
   }\r
+\r
   Status = InitializeCpuInterruptHandlers (VectorInfo);\r
   ASSERT_EFI_ERROR (Status);\r
 }\r
 \r
-\r
 /**\r
   Callback function for idle events.\r
 \r
@@ -941,8 +949,8 @@ InitInterruptDescriptorTable (
 VOID\r
 EFIAPI\r
 IdleLoopEventCallback (\r
-  IN EFI_EVENT                Event,\r
-  IN VOID                     *Context\r
+  IN EFI_EVENT  Event,\r
+  IN VOID       *Context\r
   )\r
 {\r
   CpuSleep ();\r
@@ -989,24 +997,27 @@ IdleLoopEventCallback (
 **/\r
 EFI_STATUS\r
 IntersectMemoryDescriptor (\r
-  IN  UINT64                                Base,\r
-  IN  UINT64                                Length,\r
-  IN  UINT64                                Capabilities,\r
-  IN  CONST EFI_GCD_MEMORY_SPACE_DESCRIPTOR *Descriptor\r
+  IN  UINT64                                 Base,\r
+  IN  UINT64                                 Length,\r
+  IN  UINT64                                 Capabilities,\r
+  IN  CONST EFI_GCD_MEMORY_SPACE_DESCRIPTOR  *Descriptor\r
   )\r
 {\r
-  UINT64                                    IntersectionBase;\r
-  UINT64                                    IntersectionEnd;\r
-  EFI_STATUS                                Status;\r
+  UINT64      IntersectionBase;\r
+  UINT64      IntersectionEnd;\r
+  EFI_STATUS  Status;\r
 \r
-  if (Descriptor->GcdMemoryType == EfiGcdMemoryTypeMemoryMappedIo &&\r
-      (Descriptor->Capabilities & Capabilities) == Capabilities) {\r
+  if ((Descriptor->GcdMemoryType == EfiGcdMemoryTypeMemoryMappedIo) &&\r
+      ((Descriptor->Capabilities & Capabilities) == Capabilities))\r
+  {\r
     return EFI_SUCCESS;\r
   }\r
 \r
   IntersectionBase = MAX (Base, Descriptor->BaseAddress);\r
-  IntersectionEnd = MIN (Base + Length,\r
-                      Descriptor->BaseAddress + Descriptor->Length);\r
+  IntersectionEnd  = MIN (\r
+                       Base + Length,\r
+                       Descriptor->BaseAddress + Descriptor->Length\r
+                       );\r
   if (IntersectionBase >= IntersectionEnd) {\r
     //\r
     // The descriptor and the aperture don't overlap.\r
@@ -1015,21 +1026,39 @@ IntersectMemoryDescriptor (
   }\r
 \r
   if (Descriptor->GcdMemoryType == EfiGcdMemoryTypeNonExistent) {\r
-    Status = gDS->AddMemorySpace (EfiGcdMemoryTypeMemoryMappedIo,\r
-                    IntersectionBase, IntersectionEnd - IntersectionBase,\r
-                    Capabilities);\r
-\r
-    DEBUG ((EFI_ERROR (Status) ? DEBUG_ERROR : DEBUG_VERBOSE,\r
-      "%a: %a: add [%Lx, %Lx): %r\n", gEfiCallerBaseName, __FUNCTION__,\r
-      IntersectionBase, IntersectionEnd, Status));\r
+    Status = gDS->AddMemorySpace (\r
+                    EfiGcdMemoryTypeMemoryMappedIo,\r
+                    IntersectionBase,\r
+                    IntersectionEnd - IntersectionBase,\r
+                    Capabilities\r
+                    );\r
+\r
+    DEBUG ((\r
+      EFI_ERROR (Status) ? DEBUG_ERROR : DEBUG_VERBOSE,\r
+      "%a: %a: add [%Lx, %Lx): %r\n",\r
+      gEfiCallerBaseName,\r
+      __FUNCTION__,\r
+      IntersectionBase,\r
+      IntersectionEnd,\r
+      Status\r
+      ));\r
     return Status;\r
   }\r
 \r
-  DEBUG ((DEBUG_ERROR, "%a: %a: desc [%Lx, %Lx) type %u cap %Lx conflicts "\r
-    "with aperture [%Lx, %Lx) cap %Lx\n", gEfiCallerBaseName, __FUNCTION__,\r
-    Descriptor->BaseAddress, Descriptor->BaseAddress + Descriptor->Length,\r
-    (UINT32)Descriptor->GcdMemoryType, Descriptor->Capabilities,\r
-    Base, Base + Length, Capabilities));\r
+  DEBUG ((\r
+    DEBUG_ERROR,\r
+    "%a: %a: desc [%Lx, %Lx) type %u cap %Lx conflicts "\r
+    "with aperture [%Lx, %Lx) cap %Lx\n",\r
+    gEfiCallerBaseName,\r
+    __FUNCTION__,\r
+    Descriptor->BaseAddress,\r
+    Descriptor->BaseAddress + Descriptor->Length,\r
+    (UINT32)Descriptor->GcdMemoryType,\r
+    Descriptor->Capabilities,\r
+    Base,\r
+    Base + Length,\r
+    Capabilities\r
+    ));\r
   return EFI_INVALID_PARAMETER;\r
 }\r
 \r
@@ -1046,49 +1075,60 @@ IntersectMemoryDescriptor (
 **/\r
 EFI_STATUS\r
 AddMemoryMappedIoSpace (\r
-  IN  UINT64                            Base,\r
-  IN  UINT64                            Length,\r
-  IN  UINT64                            Capabilities\r
+  IN  UINT64  Base,\r
+  IN  UINT64  Length,\r
+  IN  UINT64  Capabilities\r
   )\r
 {\r
-  EFI_STATUS                            Status;\r
-  UINTN                                 Index;\r
-  UINTN                                 NumberOfDescriptors;\r
-  EFI_GCD_MEMORY_SPACE_DESCRIPTOR       *MemorySpaceMap;\r
+  EFI_STATUS                       Status;\r
+  UINTN                            Index;\r
+  UINTN                            NumberOfDescriptors;\r
+  EFI_GCD_MEMORY_SPACE_DESCRIPTOR  *MemorySpaceMap;\r
 \r
   Status = gDS->GetMemorySpaceMap (&NumberOfDescriptors, &MemorySpaceMap);\r
   if (EFI_ERROR (Status)) {\r
-    DEBUG ((DEBUG_ERROR, "%a: %a: GetMemorySpaceMap(): %r\n",\r
-      gEfiCallerBaseName, __FUNCTION__, Status));\r
+    DEBUG ((\r
+      DEBUG_ERROR,\r
+      "%a: %a: GetMemorySpaceMap(): %r\n",\r
+      gEfiCallerBaseName,\r
+      __FUNCTION__,\r
+      Status\r
+      ));\r
     return Status;\r
   }\r
 \r
   for (Index = 0; Index < NumberOfDescriptors; Index++) {\r
-    Status = IntersectMemoryDescriptor (Base, Length, Capabilities,\r
-               &MemorySpaceMap[Index]);\r
+    Status = IntersectMemoryDescriptor (\r
+               Base,\r
+               Length,\r
+               Capabilities,\r
+               &MemorySpaceMap[Index]\r
+               );\r
     if (EFI_ERROR (Status)) {\r
       goto FreeMemorySpaceMap;\r
     }\r
   }\r
 \r
   DEBUG_CODE_BEGIN ();\r
-    //\r
-    // Make sure there are adjacent descriptors covering [Base, Base + Length).\r
-    // It is possible that they have not been merged; merging can be prevented\r
-    // by allocation and different capabilities.\r
-    //\r
-    UINT64                          CheckBase;\r
-    EFI_STATUS                      CheckStatus;\r
-    EFI_GCD_MEMORY_SPACE_DESCRIPTOR Descriptor;\r
-\r
-    for (CheckBase = Base;\r
-         CheckBase < Base + Length;\r
-         CheckBase = Descriptor.BaseAddress + Descriptor.Length) {\r
-      CheckStatus = gDS->GetMemorySpaceDescriptor (CheckBase, &Descriptor);\r
-      ASSERT_EFI_ERROR (CheckStatus);\r
-      ASSERT (Descriptor.GcdMemoryType == EfiGcdMemoryTypeMemoryMappedIo);\r
-      ASSERT ((Descriptor.Capabilities & Capabilities) == Capabilities);\r
-    }\r
+  //\r
+  // Make sure there are adjacent descriptors covering [Base, Base + Length).\r
+  // It is possible that they have not been merged; merging can be prevented\r
+  // by allocation and different capabilities.\r
+  //\r
+  UINT64                           CheckBase;\r
+  EFI_STATUS                       CheckStatus;\r
+  EFI_GCD_MEMORY_SPACE_DESCRIPTOR  Descriptor;\r
+\r
+  for (CheckBase = Base;\r
+       CheckBase < Base + Length;\r
+       CheckBase = Descriptor.BaseAddress + Descriptor.Length)\r
+  {\r
+    CheckStatus = gDS->GetMemorySpaceDescriptor (CheckBase, &Descriptor);\r
+    ASSERT_EFI_ERROR (CheckStatus);\r
+    ASSERT (Descriptor.GcdMemoryType == EfiGcdMemoryTypeMemoryMappedIo);\r
+    ASSERT ((Descriptor.Capabilities & Capabilities) == Capabilities);\r
+  }\r
+\r
   DEBUG_CODE_END ();\r
 \r
 FreeMemorySpaceMap:\r
@@ -1105,14 +1145,14 @@ FreeMemorySpaceMap:
 **/\r
 VOID\r
 AddLocalApicMemorySpace (\r
-  IN EFI_HANDLE               ImageHandle\r
+  IN EFI_HANDLE  ImageHandle\r
   )\r
 {\r
-  EFI_STATUS              Status;\r
-  EFI_PHYSICAL_ADDRESS    BaseAddress;\r
+  EFI_STATUS            Status;\r
+  EFI_PHYSICAL_ADDRESS  BaseAddress;\r
 \r
-  BaseAddress = (EFI_PHYSICAL_ADDRESS) GetLocalApicBaseAddress();\r
-  Status = AddMemoryMappedIoSpace (BaseAddress, SIZE_4KB, EFI_MEMORY_UC);\r
+  BaseAddress = (EFI_PHYSICAL_ADDRESS)GetLocalApicBaseAddress ();\r
+  Status      = AddMemoryMappedIoSpace (BaseAddress, SIZE_4KB, EFI_MEMORY_UC);\r
   ASSERT_EFI_ERROR (Status);\r
 \r
   //\r
@@ -1130,8 +1170,13 @@ AddLocalApicMemorySpace (
                   NULL\r
                   );\r
   if (EFI_ERROR (Status)) {\r
-    DEBUG ((DEBUG_INFO, "%a: %a: AllocateMemorySpace() Status - %r\n",\r
-                         gEfiCallerBaseName, __FUNCTION__, Status));\r
+    DEBUG ((\r
+      DEBUG_INFO,\r
+      "%a: %a: AllocateMemorySpace() Status - %r\n",\r
+      gEfiCallerBaseName,\r
+      __FUNCTION__,\r
+      Status\r
+      ));\r
   }\r
 }\r
 \r
@@ -1149,14 +1194,14 @@ AddLocalApicMemorySpace (
 EFI_STATUS\r
 EFIAPI\r
 InitializeCpu (\r
-  IN EFI_HANDLE                            ImageHandle,\r
-  IN EFI_SYSTEM_TABLE                      *SystemTable\r
+  IN EFI_HANDLE        ImageHandle,\r
+  IN EFI_SYSTEM_TABLE  *SystemTable\r
   )\r
 {\r
   EFI_STATUS  Status;\r
   EFI_EVENT   IdleLoopEvent;\r
 \r
-  InitializePageTableLib();\r
+  InitializePageTableLib ();\r
 \r
   InitializeFloatingPointUnits ();\r
 \r
@@ -1180,7 +1225,8 @@ InitializeCpu (
   //\r
   Status = gBS->InstallMultipleProtocolInterfaces (\r
                   &mCpuHandle,\r
-                  &gEfiCpuArchProtocolGuid, &gCpu,\r
+                  &gEfiCpuArchProtocolGuid,\r
+                  &gCpu,\r
                   NULL\r
                   );\r
   ASSERT_EFI_ERROR (Status);\r

diff --git a/UefiCpuPkg/CpuDxe/CpuDxe.h b/UefiCpuPkg/CpuDxe/CpuDxe.h
index 9771ec8336fcbd9d5f872491aee9a76fe0334d11..2208671cb93275f3ab1daf81b0ecb2c1f313454c 100644 (file)
--- a/UefiCpuPkg/CpuDxe/CpuDxe.h
+++ b/UefiCpuPkg/CpuDxe/CpuDxe.h
@@ -63,10 +63,10 @@
 EFI_STATUS\r
 EFIAPI\r
 CpuFlushCpuDataCache (\r
-  IN EFI_CPU_ARCH_PROTOCOL     *This,\r
-  IN EFI_PHYSICAL_ADDRESS      Start,\r
-  IN UINT64                    Length,\r
-  IN EFI_CPU_FLUSH_TYPE        FlushType\r
+  IN EFI_CPU_ARCH_PROTOCOL  *This,\r
+  IN EFI_PHYSICAL_ADDRESS   Start,\r
+  IN UINT64                 Length,\r
+  IN EFI_CPU_FLUSH_TYPE     FlushType\r
   );\r
 \r
 /**\r
@@ -81,7 +81,7 @@ CpuFlushCpuDataCache (
 EFI_STATUS\r
 EFIAPI\r
 CpuEnableInterrupt (\r
-  IN EFI_CPU_ARCH_PROTOCOL     *This\r
+  IN EFI_CPU_ARCH_PROTOCOL  *This\r
   );\r
 \r
 /**\r
@@ -96,7 +96,7 @@ CpuEnableInterrupt (
 EFI_STATUS\r
 EFIAPI\r
 CpuDisableInterrupt (\r
-  IN EFI_CPU_ARCH_PROTOCOL     *This\r
+  IN EFI_CPU_ARCH_PROTOCOL  *This\r
   );\r
 \r
 /**\r
@@ -112,8 +112,8 @@ CpuDisableInterrupt (
 EFI_STATUS\r
 EFIAPI\r
 CpuGetInterruptState (\r
-  IN  EFI_CPU_ARCH_PROTOCOL     *This,\r
-  OUT BOOLEAN                   *State\r
+  IN  EFI_CPU_ARCH_PROTOCOL  *This,\r
+  OUT BOOLEAN                *State\r
   );\r
 \r
 /**\r
@@ -131,8 +131,8 @@ CpuGetInterruptState (
 EFI_STATUS\r
 EFIAPI\r
 CpuInit (\r
-  IN EFI_CPU_ARCH_PROTOCOL     *This,\r
-  IN EFI_CPU_INIT_TYPE         InitType\r
+  IN EFI_CPU_ARCH_PROTOCOL  *This,\r
+  IN EFI_CPU_INIT_TYPE      InitType\r
   );\r
 \r
 /**\r
@@ -158,9 +158,9 @@ CpuInit (
 EFI_STATUS\r
 EFIAPI\r
 CpuRegisterInterruptHandler (\r
-  IN EFI_CPU_ARCH_PROTOCOL         *This,\r
-  IN EFI_EXCEPTION_TYPE            InterruptType,\r
-  IN EFI_CPU_INTERRUPT_HANDLER     InterruptHandler\r
+  IN EFI_CPU_ARCH_PROTOCOL      *This,\r
+  IN EFI_EXCEPTION_TYPE         InterruptType,\r
+  IN EFI_CPU_INTERRUPT_HANDLER  InterruptHandler\r
   );\r
 \r
 /**\r
@@ -189,10 +189,10 @@ CpuRegisterInterruptHandler (
 EFI_STATUS\r
 EFIAPI\r
 CpuGetTimerValue (\r
-  IN  EFI_CPU_ARCH_PROTOCOL       *This,\r
-  IN  UINT32                      TimerIndex,\r
-  OUT UINT64                      *TimerValue,\r
-  OUT UINT64                      *TimerPeriod OPTIONAL\r
+  IN  EFI_CPU_ARCH_PROTOCOL  *This,\r
+  IN  UINT32                 TimerIndex,\r
+  OUT UINT64                 *TimerValue,\r
+  OUT UINT64                 *TimerPeriod OPTIONAL\r
   );\r
 \r
 /**\r
@@ -214,10 +214,10 @@ CpuGetTimerValue (
 EFI_STATUS\r
 EFIAPI\r
 CpuSetMemoryAttributes (\r
-  IN EFI_CPU_ARCH_PROTOCOL      *This,\r
-  IN EFI_PHYSICAL_ADDRESS       BaseAddress,\r
-  IN UINT64                     Length,\r
-  IN UINT64                     Attributes\r
+  IN EFI_CPU_ARCH_PROTOCOL  *This,\r
+  IN EFI_PHYSICAL_ADDRESS   BaseAddress,\r
+  IN UINT64                 Length,\r
+  IN UINT64                 Attributes\r
   );\r
 \r
 /**\r
@@ -238,7 +238,7 @@ InitGlobalDescriptorTable (
 VOID\r
 EFIAPI\r
 SetCodeSelector (\r
-  UINT16 Selector\r
+  UINT16  Selector\r
   );\r
 \r
 /**\r
@@ -250,7 +250,7 @@ SetCodeSelector (
 VOID\r
 EFIAPI\r
 SetDataSelectors (\r
-  UINT16 Selector\r
+  UINT16  Selector\r
   );\r
 \r
 /**\r
@@ -273,8 +273,8 @@ RefreshGcdMemoryAttributesFromPaging (
 VOID\r
 EFIAPI\r
 DebugExceptionHandler (\r
-  IN EFI_EXCEPTION_TYPE   ExceptionType,\r
-  IN EFI_SYSTEM_CONTEXT   SystemContext\r
+  IN EFI_EXCEPTION_TYPE  ExceptionType,\r
+  IN EFI_SYSTEM_CONTEXT  SystemContext\r
   );\r
 \r
 /**\r
@@ -289,12 +289,11 @@ DebugExceptionHandler (
 VOID\r
 EFIAPI\r
 PageFaultExceptionHandler (\r
-  IN EFI_EXCEPTION_TYPE   ExceptionType,\r
-  IN EFI_SYSTEM_CONTEXT   SystemContext\r
+  IN EFI_EXCEPTION_TYPE  ExceptionType,\r
+  IN EFI_SYSTEM_CONTEXT  SystemContext\r
   );\r
 \r
-extern BOOLEAN mIsAllocatingPageTable;\r
-extern UINTN   mNumberOfProcessors;\r
+extern BOOLEAN  mIsAllocatingPageTable;\r
+extern UINTN    mNumberOfProcessors;\r
 \r
 #endif\r
-\r

diff --git a/UefiCpuPkg/CpuDxe/CpuGdt.c b/UefiCpuPkg/CpuDxe/CpuGdt.c
index 692402c55df4aaa77bebfde7a422989ff8936fec..cf571138e5768913b8e74b3d7492b5e50b6adbc9 100644 (file)
--- a/UefiCpuPkg/CpuDxe/CpuGdt.c
+++ b/UefiCpuPkg/CpuDxe/CpuGdt.c
@@ -13,7 +13,7 @@
 //\r
 // Global descriptor table (GDT) Template\r
 //\r
-STATIC GDT_ENTRIES mGdtTemplate = {\r
+STATIC GDT_ENTRIES  mGdtTemplate = {\r
   //\r
   // NULL_SEL\r
   //\r
@@ -143,7 +143,7 @@ InitGlobalDescriptorTable (
                   );\r
   ASSERT_EFI_ERROR (Status);\r
   ASSERT ((Memory != 0) && (Memory < SIZE_4GB));\r
-  Gdt = (GDT_ENTRIES *) (UINTN) Memory;\r
+  Gdt = (GDT_ENTRIES *)(UINTN)Memory;\r
 \r
   //\r
   // Initialize all GDT entries\r
@@ -153,8 +153,8 @@ InitGlobalDescriptorTable (
   //\r
   // Write GDT register\r
   //\r
-  Gdtr.Base  = (UINT32) (UINTN) Gdt;\r
-  Gdtr.Limit = (UINT16) (sizeof (mGdtTemplate) - 1);\r
+  Gdtr.Base  = (UINT32)(UINTN)Gdt;\r
+  Gdtr.Limit = (UINT16)(sizeof (mGdtTemplate) - 1);\r
   AsmWriteGdtr (&Gdtr);\r
 \r
   //\r

diff --git a/UefiCpuPkg/CpuDxe/CpuGdt.h b/UefiCpuPkg/CpuDxe/CpuGdt.h
index 1c94487cbee8a36986c71fc0141d0e6750f4cab9..b09f15725a5d75acfab5f9598f5f0297919482e0 100644 (file)
--- a/UefiCpuPkg/CpuDxe/CpuGdt.h
+++ b/UefiCpuPkg/CpuDxe/CpuGdt.h
@@ -21,48 +21,47 @@
 //\r
 \r
 typedef struct _GDT_ENTRY {\r
-  UINT16 Limit15_0;\r
-  UINT16 Base15_0;\r
-  UINT8  Base23_16;\r
-  UINT8  Type;\r
-  UINT8  Limit19_16_and_flags;\r
-  UINT8  Base31_24;\r
+  UINT16    Limit15_0;\r
+  UINT16    Base15_0;\r
+  UINT8     Base23_16;\r
+  UINT8     Type;\r
+  UINT8     Limit19_16_and_flags;\r
+  UINT8     Base31_24;\r
 } GDT_ENTRY;\r
 \r
 typedef\r
-struct _GDT_ENTRIES {\r
-  GDT_ENTRY Null;\r
-  GDT_ENTRY Linear;\r
-  GDT_ENTRY LinearCode;\r
-  GDT_ENTRY SysData;\r
-  GDT_ENTRY SysCode;\r
-  GDT_ENTRY SysCode16;\r
-  GDT_ENTRY LinearData64;\r
-  GDT_ENTRY LinearCode64;\r
-  GDT_ENTRY Spare5;\r
+  struct _GDT_ENTRIES {\r
+  GDT_ENTRY    Null;\r
+  GDT_ENTRY    Linear;\r
+  GDT_ENTRY    LinearCode;\r
+  GDT_ENTRY    SysData;\r
+  GDT_ENTRY    SysCode;\r
+  GDT_ENTRY    SysCode16;\r
+  GDT_ENTRY    LinearData64;\r
+  GDT_ENTRY    LinearCode64;\r
+  GDT_ENTRY    Spare5;\r
 } GDT_ENTRIES;\r
 \r
 #pragma pack ()\r
 \r
-#define NULL_SEL          OFFSET_OF (GDT_ENTRIES, Null)\r
-#define LINEAR_SEL        OFFSET_OF (GDT_ENTRIES, Linear)\r
-#define LINEAR_CODE_SEL   OFFSET_OF (GDT_ENTRIES, LinearCode)\r
-#define SYS_DATA_SEL      OFFSET_OF (GDT_ENTRIES, SysData)\r
-#define SYS_CODE_SEL      OFFSET_OF (GDT_ENTRIES, SysCode)\r
-#define SYS_CODE16_SEL    OFFSET_OF (GDT_ENTRIES, SysCode16)\r
-#define LINEAR_DATA64_SEL OFFSET_OF (GDT_ENTRIES, LinearData64)\r
-#define LINEAR_CODE64_SEL OFFSET_OF (GDT_ENTRIES, LinearCode64)\r
-#define SPARE5_SEL        OFFSET_OF (GDT_ENTRIES, Spare5)\r
+#define NULL_SEL           OFFSET_OF (GDT_ENTRIES, Null)\r
+#define LINEAR_SEL         OFFSET_OF (GDT_ENTRIES, Linear)\r
+#define LINEAR_CODE_SEL    OFFSET_OF (GDT_ENTRIES, LinearCode)\r
+#define SYS_DATA_SEL       OFFSET_OF (GDT_ENTRIES, SysData)\r
+#define SYS_CODE_SEL       OFFSET_OF (GDT_ENTRIES, SysCode)\r
+#define SYS_CODE16_SEL     OFFSET_OF (GDT_ENTRIES, SysCode16)\r
+#define LINEAR_DATA64_SEL  OFFSET_OF (GDT_ENTRIES, LinearData64)\r
+#define LINEAR_CODE64_SEL  OFFSET_OF (GDT_ENTRIES, LinearCode64)\r
+#define SPARE5_SEL         OFFSET_OF (GDT_ENTRIES, Spare5)\r
 \r
 #if defined (MDE_CPU_IA32)\r
-#define CPU_CODE_SEL LINEAR_CODE_SEL\r
-#define CPU_DATA_SEL LINEAR_SEL\r
+#define CPU_CODE_SEL  LINEAR_CODE_SEL\r
+#define CPU_DATA_SEL  LINEAR_SEL\r
 #elif defined (MDE_CPU_X64)\r
-#define CPU_CODE_SEL LINEAR_CODE64_SEL\r
-#define CPU_DATA_SEL LINEAR_DATA64_SEL\r
+#define CPU_CODE_SEL  LINEAR_CODE64_SEL\r
+#define CPU_DATA_SEL  LINEAR_DATA64_SEL\r
 #else\r
-#error CPU type not supported for CPU GDT initialization!\r
+  #error CPU type not supported for CPU GDT initialization!\r
 #endif\r
 \r
 #endif // _CPU_GDT_H_\r
-\r

diff --git a/UefiCpuPkg/CpuDxe/CpuMp.c b/UefiCpuPkg/CpuDxe/CpuMp.c
index 60ede38df4fccf377b7606d4514fea60b4e770c7..1f218367b3a155cd2a86db495c3938a42e8b26f9 100644 (file)
--- a/UefiCpuPkg/CpuDxe/CpuMp.c
+++ b/UefiCpuPkg/CpuDxe/CpuMp.c
@@ -9,8 +9,8 @@
 #include "CpuDxe.h"\r
 #include "CpuMp.h"\r
 \r
-EFI_HANDLE     mMpServiceHandle       = NULL;\r
-UINTN          mNumberOfProcessors    = 1;\r
+EFI_HANDLE  mMpServiceHandle    = NULL;\r
+UINTN       mNumberOfProcessors = 1;\r
 \r
 EFI_MP_SERVICES_PROTOCOL  mMpServicesTemplate = {\r
   GetNumberOfProcessors,\r
@@ -509,7 +509,7 @@ WhoAmI (
   OUT UINTN                    *ProcessorNumber\r
   )\r
 {\r
-  return MpInitLibWhoAmI (ProcessorNumber);;\r
+  return MpInitLibWhoAmI (ProcessorNumber);\r
 }\r
 \r
 /**\r
@@ -547,8 +547,8 @@ CollectBistDataFromHob (
     // Sec Platform Information2 PPI includes BSP/APs' BIST information\r
     //\r
     SecPlatformInformation2 = GET_GUID_HOB_DATA (GuidHob);\r
-    NumberOfData = SecPlatformInformation2->NumberOfCpus;\r
-    CpuInstance  = SecPlatformInformation2->CpuInstance;\r
+    NumberOfData            = SecPlatformInformation2->NumberOfCpus;\r
+    CpuInstance             = SecPlatformInformation2->CpuInstance;\r
   } else {\r
     //\r
     // Otherwise, get gEfiSecPlatformInformationPpiGuid Guided HOB\r
@@ -556,14 +556,14 @@ CollectBistDataFromHob (
     GuidHob = GetFirstGuidHob (&gEfiSecPlatformInformationPpiGuid);\r
     if (GuidHob != NULL) {\r
       SecPlatformInformation = GET_GUID_HOB_DATA (GuidHob);\r
-      NumberOfData = 1;\r
+      NumberOfData           = 1;\r
       //\r
       // SEC Platform Information only includes BSP's BIST information\r
       // does not have BSP's APIC ID\r
       //\r
-      BspCpuInstance.CpuLocation = GetApicId ();\r
-      BspCpuInstance.InfoRecord.IA32HealthFlags.Uint32  = SecPlatformInformation->IA32HealthFlags.Uint32;\r
-      CpuInstance = &BspCpuInstance;\r
+      BspCpuInstance.CpuLocation                       = GetApicId ();\r
+      BspCpuInstance.InfoRecord.IA32HealthFlags.Uint32 = SecPlatformInformation->IA32HealthFlags.Uint32;\r
+      CpuInstance                                      = &BspCpuInstance;\r
     } else {\r
       DEBUG ((DEBUG_INFO, "Does not find any HOB stored CPU BIST information!\n"));\r
       //\r
@@ -583,6 +583,7 @@ CollectBistDataFromHob (
         BistData = CpuInstance[CpuInstanceNumber].InfoRecord.IA32HealthFlags;\r
       }\r
     }\r
+\r
     if (BistData.Uint32 != 0) {\r
       //\r
       // Report Status Code that self test is failed\r
@@ -607,7 +608,7 @@ CollectBistDataFromHob (
 VOID\r
 EFIAPI\r
 GetGdtr (\r
-  IN OUT VOID *Buffer\r
+  IN OUT VOID  *Buffer\r
   )\r
 {\r
   AsmReadGdtr ((IA32_DESCRIPTOR *)Buffer);\r
@@ -625,12 +626,12 @@ GetGdtr (
 VOID\r
 EFIAPI\r
 InitializeExceptionStackSwitchHandlers (\r
-  IN OUT VOID *Buffer\r
+  IN OUT VOID  *Buffer\r
   )\r
 {\r
-  CPU_EXCEPTION_INIT_DATA           *EssData;\r
-  IA32_DESCRIPTOR                   Idtr;\r
-  EFI_STATUS                        Status;\r
+  CPU_EXCEPTION_INIT_DATA  *EssData;\r
+  IA32_DESCRIPTOR          Idtr;\r
+  EFI_STATUS               Status;\r
 \r
   EssData = Buffer;\r
   //\r
@@ -638,9 +639,9 @@ InitializeExceptionStackSwitchHandlers (
   // the AP's IDT is the same as BSP's IDT either.\r
   //\r
   AsmReadIdtr (&Idtr);\r
-  EssData->Ia32.IdtTable = (VOID *)Idtr.Base;\r
+  EssData->Ia32.IdtTable     = (VOID *)Idtr.Base;\r
   EssData->Ia32.IdtTableSize = Idtr.Limit + 1;\r
-  Status = InitializeCpuExceptionHandlersEx (NULL, EssData);\r
+  Status                     = InitializeCpuExceptionHandlersEx (NULL, EssData);\r
   ASSERT_EFI_ERROR (Status);\r
 }\r
 \r
@@ -656,19 +657,19 @@ InitializeMpExceptionStackSwitchHandlers (
   VOID\r
   )\r
 {\r
-  UINTN                           Index;\r
-  UINTN                           Bsp;\r
-  UINTN                           ExceptionNumber;\r
-  UINTN                           OldGdtSize;\r
-  UINTN                           NewGdtSize;\r
-  UINTN                           NewStackSize;\r
-  IA32_DESCRIPTOR                 Gdtr;\r
-  CPU_EXCEPTION_INIT_DATA         EssData;\r
-  UINT8                           *GdtBuffer;\r
-  UINT8                           *StackTop;\r
+  UINTN                    Index;\r
+  UINTN                    Bsp;\r
+  UINTN                    ExceptionNumber;\r
+  UINTN                    OldGdtSize;\r
+  UINTN                    NewGdtSize;\r
+  UINTN                    NewStackSize;\r
+  IA32_DESCRIPTOR          Gdtr;\r
+  CPU_EXCEPTION_INIT_DATA  EssData;\r
+  UINT8                    *GdtBuffer;\r
+  UINT8                    *StackTop;\r
 \r
   ExceptionNumber = FixedPcdGetSize (PcdCpuStackSwitchExceptionList);\r
-  NewStackSize = FixedPcdGet32 (PcdCpuKnownGoodStackSize) * ExceptionNumber;\r
+  NewStackSize    = FixedPcdGet32 (PcdCpuKnownGoodStackSize) * ExceptionNumber;\r
 \r
   StackTop = AllocateRuntimeZeroPool (NewStackSize * mNumberOfProcessors);\r
   ASSERT (StackTop != NULL);\r
@@ -678,17 +679,17 @@ InitializeMpExceptionStackSwitchHandlers (
   // The default exception handlers must have been initialized. Let's just skip\r
   // it in this method.\r
   //\r
-  EssData.Ia32.Revision = CPU_EXCEPTION_INIT_DATA_REV;\r
+  EssData.Ia32.Revision            = CPU_EXCEPTION_INIT_DATA_REV;\r
   EssData.Ia32.InitDefaultHandlers = FALSE;\r
 \r
-  EssData.Ia32.StackSwitchExceptions = FixedPcdGetPtr(PcdCpuStackSwitchExceptionList);\r
+  EssData.Ia32.StackSwitchExceptions      = FixedPcdGetPtr (PcdCpuStackSwitchExceptionList);\r
   EssData.Ia32.StackSwitchExceptionNumber = ExceptionNumber;\r
-  EssData.Ia32.KnownGoodStackSize = FixedPcdGet32(PcdCpuKnownGoodStackSize);\r
+  EssData.Ia32.KnownGoodStackSize         = FixedPcdGet32 (PcdCpuKnownGoodStackSize);\r
 \r
   //\r
   // Initialize Gdtr to suppress incorrect compiler/analyzer warnings.\r
   //\r
-  Gdtr.Base = 0;\r
+  Gdtr.Base  = 0;\r
   Gdtr.Limit = 0;\r
   MpInitLibWhoAmI (&Bsp);\r
   for (Index = 0; Index < mNumberOfProcessors; ++Index) {\r
@@ -733,7 +734,7 @@ InitializeMpExceptionStackSwitchHandlers (
     //    |                              |\r
     //    --------------------------------\r
     //\r
-    OldGdtSize = Gdtr.Limit + 1;\r
+    OldGdtSize                        = Gdtr.Limit + 1;\r
     EssData.Ia32.ExceptionTssDescSize = sizeof (IA32_TSS_DESCRIPTOR) *\r
                                         (ExceptionNumber + 1);\r
     EssData.Ia32.ExceptionTssSize = sizeof (IA32_TASK_STATE_SEGMENT) *\r
@@ -749,19 +750,21 @@ InitializeMpExceptionStackSwitchHandlers (
     //\r
     // Make sure GDT table alignment\r
     //\r
-    EssData.Ia32.GdtTable = ALIGN_POINTER(GdtBuffer, sizeof (IA32_TSS_DESCRIPTOR));\r
-    NewGdtSize -= ((UINT8 *)EssData.Ia32.GdtTable - GdtBuffer);\r
+    EssData.Ia32.GdtTable     = ALIGN_POINTER (GdtBuffer, sizeof (IA32_TSS_DESCRIPTOR));\r
+    NewGdtSize               -= ((UINT8 *)EssData.Ia32.GdtTable - GdtBuffer);\r
     EssData.Ia32.GdtTableSize = NewGdtSize;\r
 \r
     EssData.Ia32.ExceptionTssDesc = ((UINT8 *)EssData.Ia32.GdtTable + OldGdtSize);\r
-    EssData.Ia32.ExceptionTss = ((UINT8 *)EssData.Ia32.GdtTable + OldGdtSize +\r
-                                 EssData.Ia32.ExceptionTssDescSize);\r
+    EssData.Ia32.ExceptionTss     = ((UINT8 *)EssData.Ia32.GdtTable + OldGdtSize +\r
+                                     EssData.Ia32.ExceptionTssDescSize);\r
 \r
     EssData.Ia32.KnownGoodStackTop = (UINTN)StackTop;\r
-    DEBUG ((DEBUG_INFO,\r
-            "Exception stack top[cpu%lu]: 0x%lX\n",\r
-            (UINT64)(UINTN)Index,\r
-            (UINT64)(UINTN)StackTop));\r
+    DEBUG ((\r
+      DEBUG_INFO,\r
+      "Exception stack top[cpu%lu]: 0x%lX\n",\r
+      (UINT64)(UINTN)Index,\r
+      (UINT64)(UINTN)StackTop\r
+      ));\r
 \r
     if (Index == Bsp) {\r
       InitializeExceptionStackSwitchHandlers (&EssData);\r
@@ -776,7 +779,7 @@ InitializeMpExceptionStackSwitchHandlers (
         );\r
     }\r
 \r
-    StackTop  -= NewStackSize;\r
+    StackTop -= NewStackSize;\r
   }\r
 }\r
 \r
@@ -815,9 +818,9 @@ InitializeMpSupport (
   VOID\r
   )\r
 {\r
-  EFI_STATUS     Status;\r
-  UINTN          NumberOfProcessors;\r
-  UINTN          NumberOfEnabledProcessors;\r
+  EFI_STATUS  Status;\r
+  UINTN       NumberOfProcessors;\r
+  UINTN       NumberOfEnabledProcessors;\r
 \r
   //\r
   // Wakeup APs to do initialization\r
@@ -841,9 +844,9 @@ InitializeMpSupport (
 \r
   Status = gBS->InstallMultipleProtocolInterfaces (\r
                   &mMpServiceHandle,\r
-                  &gEfiMpServiceProtocolGuid,  &mMpServicesTemplate,\r
+                  &gEfiMpServiceProtocolGuid,\r
+                  &mMpServicesTemplate,\r
                   NULL\r
                   );\r
   ASSERT_EFI_ERROR (Status);\r
 }\r
-\r

diff --git a/UefiCpuPkg/CpuDxe/CpuMp.h b/UefiCpuPkg/CpuDxe/CpuMp.h
index 4ee171d8c49110b23f9ff3feb6d8ba87fcff19f0..b4617535105c728e562b97c7877009c54a481fd6 100644 (file)
--- a/UefiCpuPkg/CpuDxe/CpuMp.h
+++ b/UefiCpuPkg/CpuDxe/CpuMp.h
@@ -467,4 +467,3 @@ WhoAmI (
   );\r
 \r
 #endif // _CPU_MP_H_\r
-\r

diff --git a/UefiCpuPkg/CpuDxe/CpuPageTable.c b/UefiCpuPkg/CpuDxe/CpuPageTable.c
index c34059f87f0bb707660197a54cfc4c1437f5a5e8..d9e65ab4b22a626084366340fbeb7da9a7deb00a 100644 (file)
--- a/UefiCpuPkg/CpuDxe/CpuPageTable.c
+++ b/UefiCpuPkg/CpuDxe/CpuPageTable.c
@@ -24,27 +24,27 @@
 ///\r
 /// Page Table Entry\r
 ///\r
-#define IA32_PG_P                   BIT0\r
-#define IA32_PG_RW                  BIT1\r
-#define IA32_PG_U                   BIT2\r
-#define IA32_PG_WT                  BIT3\r
-#define IA32_PG_CD                  BIT4\r
-#define IA32_PG_A                   BIT5\r
-#define IA32_PG_D                   BIT6\r
-#define IA32_PG_PS                  BIT7\r
-#define IA32_PG_PAT_2M              BIT12\r
-#define IA32_PG_PAT_4K              IA32_PG_PS\r
-#define IA32_PG_PMNT                BIT62\r
-#define IA32_PG_NX                  BIT63\r
-\r
-#define PAGE_ATTRIBUTE_BITS         (IA32_PG_D | IA32_PG_A | IA32_PG_U | IA32_PG_RW | IA32_PG_P)\r
+#define IA32_PG_P       BIT0\r
+#define IA32_PG_RW      BIT1\r
+#define IA32_PG_U       BIT2\r
+#define IA32_PG_WT      BIT3\r
+#define IA32_PG_CD      BIT4\r
+#define IA32_PG_A       BIT5\r
+#define IA32_PG_D       BIT6\r
+#define IA32_PG_PS      BIT7\r
+#define IA32_PG_PAT_2M  BIT12\r
+#define IA32_PG_PAT_4K  IA32_PG_PS\r
+#define IA32_PG_PMNT    BIT62\r
+#define IA32_PG_NX      BIT63\r
+\r
+#define PAGE_ATTRIBUTE_BITS  (IA32_PG_D | IA32_PG_A | IA32_PG_U | IA32_PG_RW | IA32_PG_P)\r
 //\r
 // Bits 1, 2, 5, 6 are reserved in the IA32 PAE PDPTE\r
 // X64 PAE PDPTE does not have such restriction\r
 //\r
-#define IA32_PAE_PDPTE_ATTRIBUTE_BITS    (IA32_PG_P)\r
+#define IA32_PAE_PDPTE_ATTRIBUTE_BITS  (IA32_PG_P)\r
 \r
-#define PAGE_PROGATE_BITS           (IA32_PG_NX | PAGE_ATTRIBUTE_BITS)\r
+#define PAGE_PROGATE_BITS  (IA32_PG_NX | PAGE_ATTRIBUTE_BITS)\r
 \r
 #define PAGING_4K_MASK  0xFFF\r
 #define PAGING_2M_MASK  0x1FFFFF\r
@@ -52,9 +52,9 @@
 \r
 #define PAGING_PAE_INDEX_MASK  0x1FF\r
 \r
-#define PAGING_4K_ADDRESS_MASK_64 0x000FFFFFFFFFF000ull\r
-#define PAGING_2M_ADDRESS_MASK_64 0x000FFFFFFFE00000ull\r
-#define PAGING_1G_ADDRESS_MASK_64 0x000FFFFFC0000000ull\r
+#define PAGING_4K_ADDRESS_MASK_64  0x000FFFFFFFFFF000ull\r
+#define PAGING_2M_ADDRESS_MASK_64  0x000FFFFFFFE00000ull\r
+#define PAGING_1G_ADDRESS_MASK_64  0x000FFFFFC0000000ull\r
 \r
 #define MAX_PF_ENTRY_COUNT        10\r
 #define MAX_DEBUG_MESSAGE_LENGTH  0x100\r
@@ -68,9 +68,9 @@ typedef enum {
 } PAGE_ATTRIBUTE;\r
 \r
 typedef struct {\r
-  PAGE_ATTRIBUTE   Attribute;\r
-  UINT64           Length;\r
-  UINT64           AddressMask;\r
+  PAGE_ATTRIBUTE    Attribute;\r
+  UINT64            Length;\r
+  UINT64            AddressMask;\r
 } PAGE_ATTRIBUTE_TABLE;\r
 \r
 typedef enum {\r
@@ -79,21 +79,21 @@ typedef enum {
   PageActionClear,\r
 } PAGE_ACTION;\r
 \r
-PAGE_ATTRIBUTE_TABLE mPageAttributeTable[] = {\r
-  {Page4K,  SIZE_4KB, PAGING_4K_ADDRESS_MASK_64},\r
-  {Page2M,  SIZE_2MB, PAGING_2M_ADDRESS_MASK_64},\r
-  {Page1G,  SIZE_1GB, PAGING_1G_ADDRESS_MASK_64},\r
+PAGE_ATTRIBUTE_TABLE  mPageAttributeTable[] = {\r
+  { Page4K, SIZE_4KB, PAGING_4K_ADDRESS_MASK_64 },\r
+  { Page2M, SIZE_2MB, PAGING_2M_ADDRESS_MASK_64 },\r
+  { Page1G, SIZE_1GB, PAGING_1G_ADDRESS_MASK_64 },\r
 };\r
 \r
-PAGE_TABLE_POOL                   *mPageTablePool = NULL;\r
-BOOLEAN                           mPageTablePoolLock = FALSE;\r
-PAGE_TABLE_LIB_PAGING_CONTEXT     mPagingContext;\r
-EFI_SMM_BASE2_PROTOCOL            *mSmmBase2 = NULL;\r
+PAGE_TABLE_POOL                *mPageTablePool    = NULL;\r
+BOOLEAN                        mPageTablePoolLock = FALSE;\r
+PAGE_TABLE_LIB_PAGING_CONTEXT  mPagingContext;\r
+EFI_SMM_BASE2_PROTOCOL         *mSmmBase2 = NULL;\r
 \r
 //\r
 // Record the page fault exception count for one instruction execution.\r
 //\r
-UINTN                     *mPFEntryCount;\r
+UINTN  *mPFEntryCount;\r
 UINT64                    *(*mLastPFEntryPointer)[MAX_PF_ENTRY_COUNT];\r
 \r
 /**\r
@@ -119,7 +119,7 @@ IsInSmm (
   VOID\r
   )\r
 {\r
-  BOOLEAN                 InSmm;\r
+  BOOLEAN  InSmm;\r
 \r
   InSmm = FALSE;\r
   if (mSmmBase2 == NULL) {\r
@@ -137,7 +137,7 @@ IsInSmm (
   // load its own page table.\r
   //\r
   return (InSmm &&\r
-          mPagingContext.ContextData.X64.PageTableBase != (UINT64)AsmReadCr3());\r
+          mPagingContext.ContextData.X64.PageTableBase != (UINT64)AsmReadCr3 ());\r
 }\r
 \r
 /**\r
@@ -147,23 +147,23 @@ IsInSmm (
 **/\r
 VOID\r
 GetCurrentPagingContext (\r
-  IN OUT PAGE_TABLE_LIB_PAGING_CONTEXT     *PagingContext\r
+  IN OUT PAGE_TABLE_LIB_PAGING_CONTEXT  *PagingContext\r
   )\r
 {\r
-  UINT32                          RegEax;\r
-  CPUID_EXTENDED_CPU_SIG_EDX      RegEdx;\r
-  MSR_IA32_EFER_REGISTER          MsrEfer;\r
-  IA32_CR4                        Cr4;\r
-  IA32_CR0                        Cr0;\r
-  UINT32                          *Attributes;\r
-  UINTN                           *PageTableBase;\r
+  UINT32                      RegEax;\r
+  CPUID_EXTENDED_CPU_SIG_EDX  RegEdx;\r
+  MSR_IA32_EFER_REGISTER      MsrEfer;\r
+  IA32_CR4                    Cr4;\r
+  IA32_CR0                    Cr0;\r
+  UINT32                      *Attributes;\r
+  UINTN                       *PageTableBase;\r
 \r
   //\r
   // Don't retrieve current paging context from processor if in SMM mode.\r
   //\r
   if (!IsInSmm ()) {\r
-    ZeroMem (&mPagingContext, sizeof(mPagingContext));\r
-    if (sizeof(UINTN) == sizeof(UINT64)) {\r
+    ZeroMem (&mPagingContext, sizeof (mPagingContext));\r
+    if (sizeof (UINTN) == sizeof (UINT64)) {\r
       mPagingContext.MachineType = IMAGE_FILE_MACHINE_X64;\r
     } else {\r
       mPagingContext.MachineType = IMAGE_FILE_MACHINE_I386;\r
@@ -179,15 +179,19 @@ GetCurrentPagingContext (
     } else {\r
       *PageTableBase = 0;\r
     }\r
+\r
     if (Cr0.Bits.WP  != 0) {\r
       *Attributes |= PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_WP_ENABLE;\r
     }\r
+\r
     if (Cr4.Bits.PSE != 0) {\r
       *Attributes |= PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_PSE;\r
     }\r
+\r
     if (Cr4.Bits.PAE != 0) {\r
       *Attributes |= PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_PAE;\r
     }\r
+\r
     if (Cr4.Bits.LA57 != 0) {\r
       *Attributes |= PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_5_LEVEL;\r
     }\r
@@ -198,7 +202,7 @@ GetCurrentPagingContext (
 \r
       if (RegEdx.Bits.NX != 0) {\r
         // XD supported\r
-        MsrEfer.Uint64 = AsmReadMsr64(MSR_CORE_IA32_EFER);\r
+        MsrEfer.Uint64 = AsmReadMsr64 (MSR_CORE_IA32_EFER);\r
         if (MsrEfer.Bits.NXE != 0) {\r
           // XD activated\r
           *Attributes |= PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_XD_ACTIVATED;\r
@@ -231,11 +235,13 @@ PageAttributeToLength (
   )\r
 {\r
   UINTN  Index;\r
-  for (Index = 0; Index < sizeof(mPageAttributeTable)/sizeof(mPageAttributeTable[0]); Index++) {\r
+\r
+  for (Index = 0; Index < sizeof (mPageAttributeTable)/sizeof (mPageAttributeTable[0]); Index++) {\r
     if (PageAttribute == mPageAttributeTable[Index].Attribute) {\r
       return (UINTN)mPageAttributeTable[Index].Length;\r
     }\r
   }\r
+\r
   return 0;\r
 }\r
 \r
@@ -252,11 +258,13 @@ PageAttributeToMask (
   )\r
 {\r
   UINTN  Index;\r
-  for (Index = 0; Index < sizeof(mPageAttributeTable)/sizeof(mPageAttributeTable[0]); Index++) {\r
+\r
+  for (Index = 0; Index < sizeof (mPageAttributeTable)/sizeof (mPageAttributeTable[0]); Index++) {\r
     if (PageAttribute == mPageAttributeTable[Index].Attribute) {\r
       return (UINTN)mPageAttributeTable[Index].AddressMask;\r
     }\r
   }\r
+\r
   return 0;\r
 }\r
 \r
@@ -271,22 +279,22 @@ PageAttributeToMask (
 **/\r
 VOID *\r
 GetPageTableEntry (\r
-  IN  PAGE_TABLE_LIB_PAGING_CONTEXT     *PagingContext,\r
-  IN  PHYSICAL_ADDRESS                  Address,\r
-  OUT PAGE_ATTRIBUTE                    *PageAttribute\r
+  IN  PAGE_TABLE_LIB_PAGING_CONTEXT  *PagingContext,\r
+  IN  PHYSICAL_ADDRESS               Address,\r
+  OUT PAGE_ATTRIBUTE                 *PageAttribute\r
   )\r
 {\r
-  UINTN                 Index1;\r
-  UINTN                 Index2;\r
-  UINTN                 Index3;\r
-  UINTN                 Index4;\r
-  UINTN                 Index5;\r
-  UINT64                *L1PageTable;\r
-  UINT64                *L2PageTable;\r
-  UINT64                *L3PageTable;\r
-  UINT64                *L4PageTable;\r
-  UINT64                *L5PageTable;\r
-  UINT64                AddressEncMask;\r
+  UINTN   Index1;\r
+  UINTN   Index2;\r
+  UINTN   Index3;\r
+  UINTN   Index4;\r
+  UINTN   Index5;\r
+  UINT64  *L1PageTable;\r
+  UINT64  *L2PageTable;\r
+  UINT64  *L3PageTable;\r
+  UINT64  *L4PageTable;\r
+  UINT64  *L5PageTable;\r
+  UINT64  AddressEncMask;\r
 \r
   ASSERT (PagingContext != NULL);\r
 \r
@@ -312,6 +320,7 @@ GetPageTableEntry (
     } else {\r
       L4PageTable = (UINT64 *)(UINTN)PagingContext->ContextData.X64.PageTableBase;\r
     }\r
+\r
     if (L4PageTable[Index4] == 0) {\r
       *PageAttribute = PageNone;\r
       return NULL;\r
@@ -319,13 +328,15 @@ GetPageTableEntry (
 \r
     L3PageTable = (UINT64 *)(UINTN)(L4PageTable[Index4] & ~AddressEncMask & PAGING_4K_ADDRESS_MASK_64);\r
   } else {\r
-    ASSERT((PagingContext->ContextData.Ia32.Attributes & PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_PAE) != 0);\r
+    ASSERT ((PagingContext->ContextData.Ia32.Attributes & PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_PAE) != 0);\r
     L3PageTable = (UINT64 *)(UINTN)PagingContext->ContextData.Ia32.PageTableBase;\r
   }\r
+\r
   if (L3PageTable[Index3] == 0) {\r
     *PageAttribute = PageNone;\r
     return NULL;\r
   }\r
+\r
   if ((L3PageTable[Index3] & IA32_PG_PS) != 0) {\r
     // 1G\r
     *PageAttribute = Page1G;\r
@@ -337,6 +348,7 @@ GetPageTableEntry (
     *PageAttribute = PageNone;\r
     return NULL;\r
   }\r
+\r
   if ((L2PageTable[Index2] & IA32_PG_PS) != 0) {\r
     // 2M\r
     *PageAttribute = Page2M;\r
@@ -349,6 +361,7 @@ GetPageTableEntry (
     *PageAttribute = PageNone;\r
     return NULL;\r
   }\r
+\r
   *PageAttribute = Page4K;\r
   return &L1PageTable[Index1];\r
 }\r
@@ -362,20 +375,24 @@ GetPageTableEntry (
 **/\r
 UINT64\r
 GetAttributesFromPageEntry (\r
-  IN  UINT64                            *PageEntry\r
+  IN  UINT64  *PageEntry\r
   )\r
 {\r
   UINT64  Attributes;\r
+\r
   Attributes = 0;\r
   if ((*PageEntry & IA32_PG_P) == 0) {\r
     Attributes |= EFI_MEMORY_RP;\r
   }\r
+\r
   if ((*PageEntry & IA32_PG_RW) == 0) {\r
     Attributes |= EFI_MEMORY_RO;\r
   }\r
+\r
   if ((*PageEntry & IA32_PG_NX) != 0) {\r
     Attributes |= EFI_MEMORY_XP;\r
   }\r
+\r
   return Attributes;\r
 }\r
 \r
@@ -390,11 +407,11 @@ GetAttributesFromPageEntry (
 **/\r
 VOID\r
 ConvertPageEntryAttribute (\r
-  IN  PAGE_TABLE_LIB_PAGING_CONTEXT     *PagingContext,\r
-  IN  UINT64                            *PageEntry,\r
-  IN  UINT64                            Attributes,\r
-  IN  PAGE_ACTION                       PageAction,\r
-  OUT BOOLEAN                           *IsModified\r
+  IN  PAGE_TABLE_LIB_PAGING_CONTEXT  *PagingContext,\r
+  IN  UINT64                         *PageEntry,\r
+  IN  UINT64                         Attributes,\r
+  IN  PAGE_ACTION                    PageAction,\r
+  OUT BOOLEAN                        *IsModified\r
   )\r
 {\r
   UINT64  CurrentPageEntry;\r
@@ -402,45 +419,46 @@ ConvertPageEntryAttribute (
   UINT32  *PageAttributes;\r
 \r
   CurrentPageEntry = *PageEntry;\r
-  NewPageEntry = CurrentPageEntry;\r
+  NewPageEntry     = CurrentPageEntry;\r
   if ((Attributes & EFI_MEMORY_RP) != 0) {\r
     switch (PageAction) {\r
-    case PageActionAssign:\r
-    case PageActionSet:\r
-      NewPageEntry &= ~(UINT64)IA32_PG_P;\r
-      break;\r
-    case PageActionClear:\r
-      NewPageEntry |= IA32_PG_P;\r
-      break;\r
+      case PageActionAssign:\r
+      case PageActionSet:\r
+        NewPageEntry &= ~(UINT64)IA32_PG_P;\r
+        break;\r
+      case PageActionClear:\r
+        NewPageEntry |= IA32_PG_P;\r
+        break;\r
     }\r
   } else {\r
     switch (PageAction) {\r
-    case PageActionAssign:\r
-      NewPageEntry |= IA32_PG_P;\r
-      break;\r
-    case PageActionSet:\r
-    case PageActionClear:\r
-      break;\r
+      case PageActionAssign:\r
+        NewPageEntry |= IA32_PG_P;\r
+        break;\r
+      case PageActionSet:\r
+      case PageActionClear:\r
+        break;\r
     }\r
   }\r
+\r
   if ((Attributes & EFI_MEMORY_RO) != 0) {\r
     switch (PageAction) {\r
-    case PageActionAssign:\r
-    case PageActionSet:\r
-      NewPageEntry &= ~(UINT64)IA32_PG_RW;\r
-      break;\r
-    case PageActionClear:\r
-      NewPageEntry |= IA32_PG_RW;\r
-      break;\r
+      case PageActionAssign:\r
+      case PageActionSet:\r
+        NewPageEntry &= ~(UINT64)IA32_PG_RW;\r
+        break;\r
+      case PageActionClear:\r
+        NewPageEntry |= IA32_PG_RW;\r
+        break;\r
     }\r
   } else {\r
     switch (PageAction) {\r
-    case PageActionAssign:\r
-      NewPageEntry |= IA32_PG_RW;\r
-      break;\r
-    case PageActionSet:\r
-    case PageActionClear:\r
-      break;\r
+      case PageActionAssign:\r
+        NewPageEntry |= IA32_PG_RW;\r
+        break;\r
+      case PageActionSet:\r
+      case PageActionClear:\r
+        break;\r
     }\r
   }\r
 \r
@@ -449,25 +467,26 @@ ConvertPageEntryAttribute (
   if ((*PageAttributes & PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_XD_ACTIVATED) != 0) {\r
     if ((Attributes & EFI_MEMORY_XP) != 0) {\r
       switch (PageAction) {\r
-      case PageActionAssign:\r
-      case PageActionSet:\r
-        NewPageEntry |= IA32_PG_NX;\r
-        break;\r
-      case PageActionClear:\r
-        NewPageEntry &= ~IA32_PG_NX;\r
-        break;\r
+        case PageActionAssign:\r
+        case PageActionSet:\r
+          NewPageEntry |= IA32_PG_NX;\r
+          break;\r
+        case PageActionClear:\r
+          NewPageEntry &= ~IA32_PG_NX;\r
+          break;\r
       }\r
     } else {\r
       switch (PageAction) {\r
-      case PageActionAssign:\r
-        NewPageEntry &= ~IA32_PG_NX;\r
-        break;\r
-      case PageActionSet:\r
-      case PageActionClear:\r
-        break;\r
+        case PageActionAssign:\r
+          NewPageEntry &= ~IA32_PG_NX;\r
+          break;\r
+        case PageActionSet:\r
+        case PageActionClear:\r
+          break;\r
       }\r
     }\r
   }\r
+\r
   *PageEntry = NewPageEntry;\r
   if (CurrentPageEntry != NewPageEntry) {\r
     *IsModified = TRUE;\r
@@ -490,13 +509,13 @@ ConvertPageEntryAttribute (
 **/\r
 PAGE_ATTRIBUTE\r
 NeedSplitPage (\r
-  IN  PHYSICAL_ADDRESS                  BaseAddress,\r
-  IN  UINT64                            Length,\r
-  IN  UINT64                            *PageEntry,\r
-  IN  PAGE_ATTRIBUTE                    PageAttribute\r
+  IN  PHYSICAL_ADDRESS  BaseAddress,\r
+  IN  UINT64            Length,\r
+  IN  UINT64            *PageEntry,\r
+  IN  PAGE_ATTRIBUTE    PageAttribute\r
   )\r
 {\r
-  UINT64                PageEntryLength;\r
+  UINT64  PageEntryLength;\r
 \r
   PageEntryLength = PageAttributeToLength (PageAttribute);\r
 \r
@@ -525,16 +544,16 @@ NeedSplitPage (
 **/\r
 RETURN_STATUS\r
 SplitPage (\r
-  IN  UINT64                            *PageEntry,\r
-  IN  PAGE_ATTRIBUTE                    PageAttribute,\r
-  IN  PAGE_ATTRIBUTE                    SplitAttribute,\r
-  IN  PAGE_TABLE_LIB_ALLOCATE_PAGES     AllocatePagesFunc\r
+  IN  UINT64                         *PageEntry,\r
+  IN  PAGE_ATTRIBUTE                 PageAttribute,\r
+  IN  PAGE_ATTRIBUTE                 SplitAttribute,\r
+  IN  PAGE_TABLE_LIB_ALLOCATE_PAGES  AllocatePagesFunc\r
   )\r
 {\r
-  UINT64   BaseAddress;\r
-  UINT64   *NewPageEntry;\r
-  UINTN    Index;\r
-  UINT64   AddressEncMask;\r
+  UINT64  BaseAddress;\r
+  UINT64  *NewPageEntry;\r
+  UINTN   Index;\r
+  UINT64  AddressEncMask;\r
 \r
   ASSERT (PageAttribute == Page2M || PageAttribute == Page1G);\r
 \r
@@ -555,10 +574,12 @@ SplitPage (
       if (NewPageEntry == NULL) {\r
         return RETURN_OUT_OF_RESOURCES;\r
       }\r
+\r
       BaseAddress = *PageEntry & ~AddressEncMask & PAGING_2M_ADDRESS_MASK_64;\r
-      for (Index = 0; Index < SIZE_4KB / sizeof(UINT64); Index++) {\r
+      for (Index = 0; Index < SIZE_4KB / sizeof (UINT64); Index++) {\r
         NewPageEntry[Index] = (BaseAddress + SIZE_4KB * Index) | AddressEncMask | ((*PageEntry) & PAGE_PROGATE_BITS);\r
       }\r
+\r
       (*PageEntry) = (UINT64)(UINTN)NewPageEntry | AddressEncMask | ((*PageEntry) & PAGE_ATTRIBUTE_BITS);\r
       return RETURN_SUCCESS;\r
     } else {\r
@@ -570,16 +591,18 @@ SplitPage (
     // No need support 1G->4K directly, we should use 1G->2M, then 2M->4K to get more compact page table.\r
     //\r
     ASSERT (SplitAttribute == Page2M || SplitAttribute == Page4K);\r
-    if ((SplitAttribute == Page2M || SplitAttribute == Page4K)) {\r
+    if (((SplitAttribute == Page2M) || (SplitAttribute == Page4K))) {\r
       NewPageEntry = AllocatePagesFunc (1);\r
       DEBUG ((DEBUG_VERBOSE, "Split - 0x%x\n", NewPageEntry));\r
       if (NewPageEntry == NULL) {\r
         return RETURN_OUT_OF_RESOURCES;\r
       }\r
+\r
       BaseAddress = *PageEntry & ~AddressEncMask  & PAGING_1G_ADDRESS_MASK_64;\r
-      for (Index = 0; Index < SIZE_4KB / sizeof(UINT64); Index++) {\r
+      for (Index = 0; Index < SIZE_4KB / sizeof (UINT64); Index++) {\r
         NewPageEntry[Index] = (BaseAddress + SIZE_2MB * Index) | AddressEncMask | IA32_PG_PS | ((*PageEntry) & PAGE_PROGATE_BITS);\r
       }\r
+\r
       (*PageEntry) = (UINT64)(UINTN)NewPageEntry | AddressEncMask | ((*PageEntry) & PAGE_ATTRIBUTE_BITS);\r
       return RETURN_SUCCESS;\r
     } else {\r
@@ -603,14 +626,16 @@ IsReadOnlyPageWriteProtected (
   )\r
 {\r
   IA32_CR0  Cr0;\r
+\r
   //\r
   // To avoid unforseen consequences, don't touch paging settings in SMM mode\r
   // in this driver.\r
   //\r
   if (!IsInSmm ()) {\r
     Cr0.UintN = AsmReadCr0 ();\r
-    return (BOOLEAN) (Cr0.Bits.WP != 0);\r
+    return (BOOLEAN)(Cr0.Bits.WP != 0);\r
   }\r
+\r
   return FALSE;\r
 }\r
 \r
@@ -623,12 +648,13 @@ DisableReadOnlyPageWriteProtect (
   )\r
 {\r
   IA32_CR0  Cr0;\r
+\r
   //\r
   // To avoid unforseen consequences, don't touch paging settings in SMM mode\r
   // in this driver.\r
   //\r
   if (!IsInSmm ()) {\r
-    Cr0.UintN = AsmReadCr0 ();\r
+    Cr0.UintN   = AsmReadCr0 ();\r
     Cr0.Bits.WP = 0;\r
     AsmWriteCr0 (Cr0.UintN);\r
   }\r
@@ -643,12 +669,13 @@ EnableReadOnlyPageWriteProtect (
   )\r
 {\r
   IA32_CR0  Cr0;\r
+\r
   //\r
   // To avoid unforseen consequences, don't touch paging settings in SMM mode\r
   // in this driver.\r
   //\r
   if (!IsInSmm ()) {\r
-    Cr0.UintN = AsmReadCr0 ();\r
+    Cr0.UintN   = AsmReadCr0 ();\r
     Cr0.Bits.WP = 1;\r
     AsmWriteCr0 (Cr0.UintN);\r
   }\r
@@ -685,33 +712,35 @@ EnableReadOnlyPageWriteProtect (
 **/\r
 RETURN_STATUS\r
 ConvertMemoryPageAttributes (\r
-  IN  PAGE_TABLE_LIB_PAGING_CONTEXT     *PagingContext OPTIONAL,\r
-  IN  PHYSICAL_ADDRESS                  BaseAddress,\r
-  IN  UINT64                            Length,\r
-  IN  UINT64                            Attributes,\r
-  IN  PAGE_ACTION                       PageAction,\r
-  IN  PAGE_TABLE_LIB_ALLOCATE_PAGES     AllocatePagesFunc OPTIONAL,\r
-  OUT BOOLEAN                           *IsSplitted   OPTIONAL,\r
-  OUT BOOLEAN                           *IsModified   OPTIONAL\r
+  IN  PAGE_TABLE_LIB_PAGING_CONTEXT  *PagingContext OPTIONAL,\r
+  IN  PHYSICAL_ADDRESS               BaseAddress,\r
+  IN  UINT64                         Length,\r
+  IN  UINT64                         Attributes,\r
+  IN  PAGE_ACTION                    PageAction,\r
+  IN  PAGE_TABLE_LIB_ALLOCATE_PAGES  AllocatePagesFunc OPTIONAL,\r
+  OUT BOOLEAN                        *IsSplitted   OPTIONAL,\r
+  OUT BOOLEAN                        *IsModified   OPTIONAL\r
   )\r
 {\r
-  PAGE_TABLE_LIB_PAGING_CONTEXT     CurrentPagingContext;\r
-  UINT64                            *PageEntry;\r
-  PAGE_ATTRIBUTE                    PageAttribute;\r
-  UINTN                             PageEntryLength;\r
-  PAGE_ATTRIBUTE                    SplitAttribute;\r
-  RETURN_STATUS                     Status;\r
-  BOOLEAN                           IsEntryModified;\r
-  BOOLEAN                           IsWpEnabled;\r
+  PAGE_TABLE_LIB_PAGING_CONTEXT  CurrentPagingContext;\r
+  UINT64                         *PageEntry;\r
+  PAGE_ATTRIBUTE                 PageAttribute;\r
+  UINTN                          PageEntryLength;\r
+  PAGE_ATTRIBUTE                 SplitAttribute;\r
+  RETURN_STATUS                  Status;\r
+  BOOLEAN                        IsEntryModified;\r
+  BOOLEAN                        IsWpEnabled;\r
 \r
   if ((BaseAddress & (SIZE_4KB - 1)) != 0) {\r
     DEBUG ((DEBUG_ERROR, "BaseAddress(0x%lx) is not aligned!\n", BaseAddress));\r
     return EFI_UNSUPPORTED;\r
   }\r
+\r
   if ((Length & (SIZE_4KB - 1)) != 0) {\r
     DEBUG ((DEBUG_ERROR, "Length(0x%lx) is not aligned!\n", Length));\r
     return EFI_UNSUPPORTED;\r
   }\r
+\r
   if (Length == 0) {\r
     DEBUG ((DEBUG_ERROR, "Length is 0!\n"));\r
     return RETURN_INVALID_PARAMETER;\r
@@ -725,44 +754,50 @@ ConvertMemoryPageAttributes (
   if (PagingContext == NULL) {\r
     GetCurrentPagingContext (&CurrentPagingContext);\r
   } else {\r
-    CopyMem (&CurrentPagingContext, PagingContext, sizeof(CurrentPagingContext));\r
+    CopyMem (&CurrentPagingContext, PagingContext, sizeof (CurrentPagingContext));\r
   }\r
-  switch(CurrentPagingContext.MachineType) {\r
-  case IMAGE_FILE_MACHINE_I386:\r
-    if (CurrentPagingContext.ContextData.Ia32.PageTableBase == 0) {\r
-      if (Attributes == 0) {\r
-        return EFI_SUCCESS;\r
-      } else {\r
-        DEBUG ((DEBUG_ERROR, "PageTable is 0!\n"));\r
+\r
+  switch (CurrentPagingContext.MachineType) {\r
+    case IMAGE_FILE_MACHINE_I386:\r
+      if (CurrentPagingContext.ContextData.Ia32.PageTableBase == 0) {\r
+        if (Attributes == 0) {\r
+          return EFI_SUCCESS;\r
+        } else {\r
+          DEBUG ((DEBUG_ERROR, "PageTable is 0!\n"));\r
+          return EFI_UNSUPPORTED;\r
+        }\r
+      }\r
+\r
+      if ((CurrentPagingContext.ContextData.Ia32.Attributes & PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_PAE) == 0) {\r
+        DEBUG ((DEBUG_ERROR, "Non-PAE Paging!\n"));\r
         return EFI_UNSUPPORTED;\r
       }\r
-    }\r
-    if ((CurrentPagingContext.ContextData.Ia32.Attributes & PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_PAE) == 0) {\r
-      DEBUG ((DEBUG_ERROR, "Non-PAE Paging!\n"));\r
-      return EFI_UNSUPPORTED;\r
-    }\r
-    if ((BaseAddress + Length) > BASE_4GB) {\r
-      DEBUG ((DEBUG_ERROR, "Beyond 4GB memory in 32-bit mode!\n"));\r
+\r
+      if ((BaseAddress + Length) > BASE_4GB) {\r
+        DEBUG ((DEBUG_ERROR, "Beyond 4GB memory in 32-bit mode!\n"));\r
+        return EFI_UNSUPPORTED;\r
+      }\r
+\r
+      break;\r
+    case IMAGE_FILE_MACHINE_X64:\r
+      ASSERT (CurrentPagingContext.ContextData.X64.PageTableBase != 0);\r
+      break;\r
+    default:\r
+      ASSERT (FALSE);\r
       return EFI_UNSUPPORTED;\r
-    }\r
-    break;\r
-  case IMAGE_FILE_MACHINE_X64:\r
-    ASSERT (CurrentPagingContext.ContextData.X64.PageTableBase != 0);\r
-    break;\r
-  default:\r
-    ASSERT(FALSE);\r
-    return EFI_UNSUPPORTED;\r
-    break;\r
+      break;\r
   }\r
 \r
-//  DEBUG ((DEBUG_ERROR, "ConvertMemoryPageAttributes(%x) - %016lx, %016lx, %02lx\n", IsSet, BaseAddress, Length, Attributes));\r
+  //  DEBUG ((DEBUG_ERROR, "ConvertMemoryPageAttributes(%x) - %016lx, %016lx, %02lx\n", IsSet, BaseAddress, Length, Attributes));\r
 \r
   if (IsSplitted != NULL) {\r
     *IsSplitted = FALSE;\r
   }\r
+\r
   if (IsModified != NULL) {\r
     *IsModified = FALSE;\r
   }\r
+\r
   if (AllocatePagesFunc == NULL) {\r
     AllocatePagesFunc = AllocatePageTableMemory;\r
   }\r
@@ -785,8 +820,9 @@ ConvertMemoryPageAttributes (
       Status = RETURN_UNSUPPORTED;\r
       goto Done;\r
     }\r
+\r
     PageEntryLength = PageAttributeToLength (PageAttribute);\r
-    SplitAttribute = NeedSplitPage (BaseAddress, Length, PageEntry, PageAttribute);\r
+    SplitAttribute  = NeedSplitPage (BaseAddress, Length, PageEntry, PageAttribute);\r
     if (SplitAttribute == PageNone) {\r
       ConvertPageEntryAttribute (&CurrentPagingContext, PageEntry, Attributes, PageAction, &IsEntryModified);\r
       if (IsEntryModified) {\r
@@ -794,27 +830,32 @@ ConvertMemoryPageAttributes (
           *IsModified = TRUE;\r
         }\r
       }\r
+\r
       //\r
       // Convert success, move to next\r
       //\r
       BaseAddress += PageEntryLength;\r
-      Length -= PageEntryLength;\r
+      Length      -= PageEntryLength;\r
     } else {\r
       if (AllocatePagesFunc == NULL) {\r
         Status = RETURN_UNSUPPORTED;\r
         goto Done;\r
       }\r
+\r
       Status = SplitPage (PageEntry, PageAttribute, SplitAttribute, AllocatePagesFunc);\r
       if (RETURN_ERROR (Status)) {\r
         Status = RETURN_UNSUPPORTED;\r
         goto Done;\r
       }\r
+\r
       if (IsSplitted != NULL) {\r
         *IsSplitted = TRUE;\r
       }\r
+\r
       if (IsModified != NULL) {\r
         *IsModified = TRUE;\r
       }\r
+\r
       //\r
       // Just split current page\r
       // Convert success in next around\r
@@ -829,6 +870,7 @@ Done:
   if (IsWpEnabled) {\r
     EnableReadOnlyPageWriteProtect ();\r
   }\r
+\r
   return Status;\r
 }\r
 \r
@@ -863,20 +905,20 @@ Done:
 RETURN_STATUS\r
 EFIAPI\r
 AssignMemoryPageAttributes (\r
-  IN  PAGE_TABLE_LIB_PAGING_CONTEXT     *PagingContext OPTIONAL,\r
-  IN  PHYSICAL_ADDRESS                  BaseAddress,\r
-  IN  UINT64                            Length,\r
-  IN  UINT64                            Attributes,\r
-  IN  PAGE_TABLE_LIB_ALLOCATE_PAGES     AllocatePagesFunc OPTIONAL\r
+  IN  PAGE_TABLE_LIB_PAGING_CONTEXT  *PagingContext OPTIONAL,\r
+  IN  PHYSICAL_ADDRESS               BaseAddress,\r
+  IN  UINT64                         Length,\r
+  IN  UINT64                         Attributes,\r
+  IN  PAGE_TABLE_LIB_ALLOCATE_PAGES  AllocatePagesFunc OPTIONAL\r
   )\r
 {\r
   RETURN_STATUS  Status;\r
   BOOLEAN        IsModified;\r
   BOOLEAN        IsSplitted;\r
 \r
-//  DEBUG((DEBUG_INFO, "AssignMemoryPageAttributes: 0x%lx - 0x%lx (0x%lx)\n", BaseAddress, Length, Attributes));\r
+  //  DEBUG((DEBUG_INFO, "AssignMemoryPageAttributes: 0x%lx - 0x%lx (0x%lx)\n", BaseAddress, Length, Attributes));\r
   Status = ConvertMemoryPageAttributes (PagingContext, BaseAddress, Length, Attributes, PageActionAssign, AllocatePagesFunc, &IsSplitted, &IsModified);\r
-  if (!EFI_ERROR(Status)) {\r
+  if (!EFI_ERROR (Status)) {\r
     if ((PagingContext == NULL) && IsModified) {\r
       //\r
       // Flush TLB as last step.\r
@@ -885,7 +927,7 @@ AssignMemoryPageAttributes (
       // TLB flush in MWAIT loop mode, there's no need to flush TLB for them\r
       // here.\r
       //\r
-      CpuFlushTlb();\r
+      CpuFlushTlb ();\r
     }\r
   }\r
 \r
@@ -900,7 +942,7 @@ IsExecuteDisableEnabled (
   VOID\r
   )\r
 {\r
-  MSR_CORE_IA32_EFER_REGISTER    MsrEfer;\r
+  MSR_CORE_IA32_EFER_REGISTER  MsrEfer;\r
 \r
   MsrEfer.Uint64 = AsmReadMsr64 (MSR_IA32_EFER);\r
   return (MsrEfer.Bits.NXE == 1);\r
@@ -914,21 +956,21 @@ RefreshGcdMemoryAttributesFromPaging (
   VOID\r
   )\r
 {\r
-  EFI_STATUS                          Status;\r
-  UINTN                               NumberOfDescriptors;\r
-  EFI_GCD_MEMORY_SPACE_DESCRIPTOR     *MemorySpaceMap;\r
-  PAGE_TABLE_LIB_PAGING_CONTEXT       PagingContext;\r
-  PAGE_ATTRIBUTE                      PageAttribute;\r
-  UINT64                              *PageEntry;\r
-  UINT64                              PageLength;\r
-  UINT64                              MemorySpaceLength;\r
-  UINT64                              Length;\r
-  UINT64                              BaseAddress;\r
-  UINT64                              PageStartAddress;\r
-  UINT64                              Attributes;\r
-  UINT64                              Capabilities;\r
-  UINT64                              NewAttributes;\r
-  UINTN                               Index;\r
+  EFI_STATUS                       Status;\r
+  UINTN                            NumberOfDescriptors;\r
+  EFI_GCD_MEMORY_SPACE_DESCRIPTOR  *MemorySpaceMap;\r
+  PAGE_TABLE_LIB_PAGING_CONTEXT    PagingContext;\r
+  PAGE_ATTRIBUTE                   PageAttribute;\r
+  UINT64                           *PageEntry;\r
+  UINT64                           PageLength;\r
+  UINT64                           MemorySpaceLength;\r
+  UINT64                           Length;\r
+  UINT64                           BaseAddress;\r
+  UINT64                           PageStartAddress;\r
+  UINT64                           Attributes;\r
+  UINT64                           Capabilities;\r
+  UINT64                           NewAttributes;\r
+  UINTN                            Index;\r
 \r
   //\r
   // Assuming that memory space map returned is sorted already; otherwise sort\r
@@ -939,10 +981,10 @@ RefreshGcdMemoryAttributesFromPaging (
 \r
   GetCurrentPagingContext (&PagingContext);\r
 \r
-  Attributes      = 0;\r
-  NewAttributes   = 0;\r
-  BaseAddress     = 0;\r
-  PageLength      = 0;\r
+  Attributes    = 0;\r
+  NewAttributes = 0;\r
+  BaseAddress   = 0;\r
+  PageLength    = 0;\r
 \r
   if (IsExecuteDisableEnabled ()) {\r
     Capabilities = EFI_MEMORY_RO | EFI_MEMORY_RP | EFI_MEMORY_XP;\r
@@ -975,7 +1017,8 @@ RefreshGcdMemoryAttributesFromPaging (
       DEBUG ((\r
         DEBUG_WARN,\r
         "Failed to update capability: [%lu] %016lx - %016lx (%016lx -> %016lx)\r\n",\r
-        (UINT64)Index, MemorySpaceMap[Index].BaseAddress,\r
+        (UINT64)Index,\r
+        MemorySpaceMap[Index].BaseAddress,\r
         MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length - 1,\r
         MemorySpaceMap[Index].Capabilities,\r
         MemorySpaceMap[Index].Capabilities | Capabilities\r
@@ -1011,14 +1054,15 @@ RefreshGcdMemoryAttributesFromPaging (
         //\r
         // Note current memory space might start in the middle of a page\r
         //\r
-        PageStartAddress  = (*PageEntry) & (UINT64)PageAttributeToMask(PageAttribute);\r
-        PageLength        = PageAttributeToLength (PageAttribute) - (BaseAddress - PageStartAddress);\r
-        Attributes        = GetAttributesFromPageEntry (PageEntry);\r
+        PageStartAddress = (*PageEntry) & (UINT64)PageAttributeToMask (PageAttribute);\r
+        PageLength       = PageAttributeToLength (PageAttribute) - (BaseAddress - PageStartAddress);\r
+        Attributes       = GetAttributesFromPageEntry (PageEntry);\r
       }\r
 \r
       Length = MIN (PageLength, MemorySpaceLength);\r
       if (Attributes != (MemorySpaceMap[Index].Attributes &\r
-                         EFI_MEMORY_ATTRIBUTE_MASK)) {\r
+                         EFI_MEMORY_ATTRIBUTE_MASK))\r
+      {\r
         NewAttributes = (MemorySpaceMap[Index].Attributes &\r
                          ~EFI_MEMORY_ATTRIBUTE_MASK) | Attributes;\r
         Status = gDS->SetMemorySpaceAttributes (\r
@@ -1030,7 +1074,9 @@ RefreshGcdMemoryAttributesFromPaging (
         DEBUG ((\r
           DEBUG_VERBOSE,\r
           "Updated memory space attribute: [%lu] %016lx - %016lx (%016lx -> %016lx)\r\n",\r
-          (UINT64)Index, BaseAddress, BaseAddress + Length - 1,\r
+          (UINT64)Index,\r
+          BaseAddress,\r
+          BaseAddress + Length - 1,\r
           MemorySpaceMap[Index].Attributes,\r
           NewAttributes\r
           ));\r
@@ -1064,11 +1110,11 @@ RefreshGcdMemoryAttributesFromPaging (
 **/\r
 BOOLEAN\r
 InitializePageTablePool (\r
-  IN  UINTN                           PoolPages\r
+  IN  UINTN  PoolPages\r
   )\r
 {\r
-  VOID                      *Buffer;\r
-  BOOLEAN                   IsModified;\r
+  VOID     *Buffer;\r
+  BOOLEAN  IsModified;\r
 \r
   //\r
   // Do not allow re-entrance.\r
@@ -1078,15 +1124,15 @@ InitializePageTablePool (
   }\r
 \r
   mPageTablePoolLock = TRUE;\r
-  IsModified = FALSE;\r
+  IsModified         = FALSE;\r
 \r
   //\r
   // Always reserve at least PAGE_TABLE_POOL_UNIT_PAGES, including one page for\r
   // header.\r
   //\r
   PoolPages += 1;   // Add one page for header.\r
-  PoolPages = ((PoolPages - 1) / PAGE_TABLE_POOL_UNIT_PAGES + 1) *\r
-              PAGE_TABLE_POOL_UNIT_PAGES;\r
+  PoolPages  = ((PoolPages - 1) / PAGE_TABLE_POOL_UNIT_PAGES + 1) *\r
+               PAGE_TABLE_POOL_UNIT_PAGES;\r
   Buffer = AllocateAlignedPages (PoolPages, PAGE_TABLE_POOL_ALIGNMENT);\r
   if (Buffer == NULL) {\r
     DEBUG ((DEBUG_ERROR, "ERROR: Out of aligned pages\r\n"));\r
@@ -1103,19 +1149,19 @@ InitializePageTablePool (
   // Link all pools into a list for easier track later.\r
   //\r
   if (mPageTablePool == NULL) {\r
-    mPageTablePool = Buffer;\r
+    mPageTablePool           = Buffer;\r
     mPageTablePool->NextPool = mPageTablePool;\r
   } else {\r
     ((PAGE_TABLE_POOL *)Buffer)->NextPool = mPageTablePool->NextPool;\r
-    mPageTablePool->NextPool = Buffer;\r
-    mPageTablePool = Buffer;\r
+    mPageTablePool->NextPool              = Buffer;\r
+    mPageTablePool                        = Buffer;\r
   }\r
 \r
   //\r
   // Reserve one page for pool header.\r
   //\r
-  mPageTablePool->FreePages  = PoolPages - 1;\r
-  mPageTablePool->Offset = EFI_PAGES_TO_SIZE (1);\r
+  mPageTablePool->FreePages = PoolPages - 1;\r
+  mPageTablePool->Offset    = EFI_PAGES_TO_SIZE (1);\r
 \r
   //\r
   // Mark the whole pool pages as read-only.\r
@@ -1157,10 +1203,10 @@ Done:
 VOID *\r
 EFIAPI\r
 AllocatePageTableMemory (\r
-  IN UINTN           Pages\r
+  IN UINTN  Pages\r
   )\r
 {\r
-  VOID                            *Buffer;\r
+  VOID  *Buffer;\r
 \r
   if (Pages == 0) {\r
     return NULL;\r
@@ -1169,8 +1215,9 @@ AllocatePageTableMemory (
   //\r
   // Renew the pool if necessary.\r
   //\r
-  if (mPageTablePool == NULL ||\r
-      Pages > mPageTablePool->FreePages) {\r
+  if ((mPageTablePool == NULL) ||\r
+      (Pages > mPageTablePool->FreePages))\r
+  {\r
     if (!InitializePageTablePool (Pages)) {\r
       return NULL;\r
     }\r
@@ -1178,8 +1225,8 @@ AllocatePageTableMemory (
 \r
   Buffer = (UINT8 *)mPageTablePool + mPageTablePool->Offset;\r
 \r
-  mPageTablePool->Offset     += EFI_PAGES_TO_SIZE (Pages);\r
-  mPageTablePool->FreePages  -= Pages;\r
+  mPageTablePool->Offset    += EFI_PAGES_TO_SIZE (Pages);\r
+  mPageTablePool->FreePages -= Pages;\r
 \r
   return Buffer;\r
 }\r
@@ -1196,13 +1243,13 @@ AllocatePageTableMemory (
 VOID\r
 EFIAPI\r
 DebugExceptionHandler (\r
-  IN EFI_EXCEPTION_TYPE   ExceptionType,\r
-  IN EFI_SYSTEM_CONTEXT   SystemContext\r
+  IN EFI_EXCEPTION_TYPE  ExceptionType,\r
+  IN EFI_SYSTEM_CONTEXT  SystemContext\r
   )\r
 {\r
-  UINTN     CpuIndex;\r
-  UINTN     PFEntry;\r
-  BOOLEAN   IsWpEnabled;\r
+  UINTN    CpuIndex;\r
+  UINTN    PFEntry;\r
+  BOOLEAN  IsWpEnabled;\r
 \r
   MpInitLibWhoAmI (&CpuIndex);\r
 \r
@@ -1238,9 +1285,9 @@ DebugExceptionHandler (
   // Clear TF in EFLAGS\r
   //\r
   if (mPagingContext.MachineType == IMAGE_FILE_MACHINE_I386) {\r
-    SystemContext.SystemContextIa32->Eflags &= (UINT32)~BIT8;\r
+    SystemContext.SystemContextIa32->Eflags &= (UINT32) ~BIT8;\r
   } else {\r
-    SystemContext.SystemContextX64->Rflags &= (UINT64)~BIT8;\r
+    SystemContext.SystemContextX64->Rflags &= (UINT64) ~BIT8;\r
   }\r
 }\r
 \r
@@ -1256,20 +1303,20 @@ DebugExceptionHandler (
 VOID\r
 EFIAPI\r
 PageFaultExceptionHandler (\r
-  IN EFI_EXCEPTION_TYPE   ExceptionType,\r
-  IN EFI_SYSTEM_CONTEXT   SystemContext\r
+  IN EFI_EXCEPTION_TYPE  ExceptionType,\r
+  IN EFI_SYSTEM_CONTEXT  SystemContext\r
   )\r
 {\r
-  EFI_STATUS                      Status;\r
-  UINT64                          PFAddress;\r
-  PAGE_TABLE_LIB_PAGING_CONTEXT   PagingContext;\r
-  PAGE_ATTRIBUTE                  PageAttribute;\r
-  UINT64                          Attributes;\r
-  UINT64                          *PageEntry;\r
-  UINTN                           Index;\r
-  UINTN                           CpuIndex;\r
-  UINTN                           PageNumber;\r
-  BOOLEAN                         NonStopMode;\r
+  EFI_STATUS                     Status;\r
+  UINT64                         PFAddress;\r
+  PAGE_TABLE_LIB_PAGING_CONTEXT  PagingContext;\r
+  PAGE_ATTRIBUTE                 PageAttribute;\r
+  UINT64                         Attributes;\r
+  UINT64                         *PageEntry;\r
+  UINTN                          Index;\r
+  UINTN                          CpuIndex;\r
+  UINTN                          PageNumber;\r
+  BOOLEAN                        NonStopMode;\r
 \r
   PFAddress = AsmReadCr2 () & ~EFI_PAGE_MASK;\r
   if (PFAddress < BASE_4KB) {\r
@@ -1289,23 +1336,28 @@ PageFaultExceptionHandler (
     PageNumber = 2;\r
     while (PageNumber > 0) {\r
       PageEntry = GetPageTableEntry (&PagingContext, PFAddress, &PageAttribute);\r
-      ASSERT(PageEntry != NULL);\r
+      ASSERT (PageEntry != NULL);\r
 \r
       if (PageEntry != NULL) {\r
         Attributes = GetAttributesFromPageEntry (PageEntry);\r
         if ((Attributes & EFI_MEMORY_RP) != 0) {\r
           Attributes &= ~EFI_MEMORY_RP;\r
-          Status = AssignMemoryPageAttributes (&PagingContext, PFAddress,\r
-                                               EFI_PAGE_SIZE, Attributes, NULL);\r
-          if (!EFI_ERROR(Status)) {\r
+          Status      = AssignMemoryPageAttributes (\r
+                          &PagingContext,\r
+                          PFAddress,\r
+                          EFI_PAGE_SIZE,\r
+                          Attributes,\r
+                          NULL\r
+                          );\r
+          if (!EFI_ERROR (Status)) {\r
             Index = mPFEntryCount[CpuIndex];\r
             //\r
             // Re-retrieve page entry because above calling might update page\r
             // table due to table split.\r
             //\r
-            PageEntry = GetPageTableEntry (&PagingContext, PFAddress, &PageAttribute);\r
+            PageEntry                              = GetPageTableEntry (&PagingContext, PFAddress, &PageAttribute);\r
             mLastPFEntryPointer[CpuIndex][Index++] = PageEntry;\r
-            mPFEntryCount[CpuIndex] = Index;\r
+            mPFEntryCount[CpuIndex]                = Index;\r
           }\r
         }\r
       }\r
@@ -1345,9 +1397,9 @@ InitializePageTableLib (
   VOID\r
   )\r
 {\r
-  PAGE_TABLE_LIB_PAGING_CONTEXT     CurrentPagingContext;\r
-  UINT32                            *Attributes;\r
-  UINTN                             *PageTableBase;\r
+  PAGE_TABLE_LIB_PAGING_CONTEXT  CurrentPagingContext;\r
+  UINT32                         *Attributes;\r
+  UINTN                          *PageTableBase;\r
 \r
   GetCurrentPagingContext (&CurrentPagingContext);\r
 \r
@@ -1357,7 +1409,8 @@ InitializePageTableLib (
   // Reserve memory of page tables for future uses, if paging is enabled.\r
   //\r
   if ((*PageTableBase != 0) &&\r
-      (*Attributes & PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_PAE) != 0) {\r
+      ((*Attributes & PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_PAE) != 0))\r
+  {\r
     DisableReadOnlyPageWriteProtect ();\r
     InitializePageTablePool (1);\r
     EnableReadOnlyPageWriteProtect ();\r
@@ -1377,5 +1430,5 @@ InitializePageTableLib (
   DEBUG ((DEBUG_INFO, "  PageTableBase - 0x%Lx\n", (UINT64)*PageTableBase));\r
   DEBUG ((DEBUG_INFO, "  Attributes    - 0x%x\n", *Attributes));\r
 \r
-  return ;\r
+  return;\r
 }\r

diff --git a/UefiCpuPkg/CpuDxe/CpuPageTable.h b/UefiCpuPkg/CpuDxe/CpuPageTable.h
index 0b2a02a2be5c35629ec69c32105c92fbbb147673..607e936b8ac7b5e05b5f255ed48f5ed8e5d317cf 100644 (file)
--- a/UefiCpuPkg/CpuDxe/CpuPageTable.h
+++ b/UefiCpuPkg/CpuDxe/CpuPageTable.h
@@ -19,19 +19,19 @@
 #define PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_XD_ACTIVATED     BIT31\r
 // Other bits are reserved for future use\r
 typedef struct {\r
-  UINT32  PageTableBase;\r
-  UINT32  Reserved;\r
-  UINT32  Attributes;\r
+  UINT32    PageTableBase;\r
+  UINT32    Reserved;\r
+  UINT32    Attributes;\r
 } PAGE_TABLE_LIB_PAGING_CONTEXT_IA32;\r
 \r
 typedef struct {\r
-  UINT64  PageTableBase;\r
-  UINT32  Attributes;\r
+  UINT64    PageTableBase;\r
+  UINT32    Attributes;\r
 } PAGE_TABLE_LIB_PAGING_CONTEXT_X64;\r
 \r
 typedef union {\r
-  PAGE_TABLE_LIB_PAGING_CONTEXT_IA32  Ia32;\r
-  PAGE_TABLE_LIB_PAGING_CONTEXT_X64   X64;\r
+  PAGE_TABLE_LIB_PAGING_CONTEXT_IA32    Ia32;\r
+  PAGE_TABLE_LIB_PAGING_CONTEXT_X64     X64;\r
 } PAGE_TABLE_LIB_PAGING_CONTEXT_DATA;\r
 \r
 typedef struct {\r
@@ -41,8 +41,8 @@ typedef struct {
   // #define IMAGE_FILE_MACHINE_I386            0x014c\r
   // #define IMAGE_FILE_MACHINE_X64             0x8664\r
   //\r
-  UINT16                                 MachineType;\r
-  PAGE_TABLE_LIB_PAGING_CONTEXT_DATA     ContextData;\r
+  UINT16                                MachineType;\r
+  PAGE_TABLE_LIB_PAGING_CONTEXT_DATA    ContextData;\r
 } PAGE_TABLE_LIB_PAGING_CONTEXT;\r
 \r
 #define PAGE_TABLE_POOL_ALIGNMENT   BASE_2MB\r
@@ -52,12 +52,11 @@ typedef struct {
   (~(EFI_PHYSICAL_ADDRESS)(PAGE_TABLE_POOL_ALIGNMENT - 1))\r
 \r
 typedef struct {\r
-  VOID            *NextPool;\r
-  UINTN           Offset;\r
-  UINTN           FreePages;\r
+  VOID     *NextPool;\r
+  UINTN    Offset;\r
+  UINTN    FreePages;\r
 } PAGE_TABLE_POOL;\r
 \r
-\r
 /**\r
   Allocates one or more 4KB pages for page table.\r
 \r
@@ -68,7 +67,7 @@ typedef struct {
 **/\r
 typedef\r
 VOID *\r
-(EFIAPI *PAGE_TABLE_LIB_ALLOCATE_PAGES) (\r
+(EFIAPI *PAGE_TABLE_LIB_ALLOCATE_PAGES)(\r
   IN UINTN  Pages\r
   );\r
 \r
@@ -103,11 +102,11 @@ VOID *
 RETURN_STATUS\r
 EFIAPI\r
 AssignMemoryPageAttributes (\r
-  IN  PAGE_TABLE_LIB_PAGING_CONTEXT     *PagingContext OPTIONAL,\r
-  IN  PHYSICAL_ADDRESS                  BaseAddress,\r
-  IN  UINT64                            Length,\r
-  IN  UINT64                            Attributes,\r
-  IN  PAGE_TABLE_LIB_ALLOCATE_PAGES     AllocatePagesFunc OPTIONAL\r
+  IN  PAGE_TABLE_LIB_PAGING_CONTEXT  *PagingContext OPTIONAL,\r
+  IN  PHYSICAL_ADDRESS               BaseAddress,\r
+  IN  UINT64                         Length,\r
+  IN  UINT64                         Attributes,\r
+  IN  PAGE_TABLE_LIB_ALLOCATE_PAGES  AllocatePagesFunc OPTIONAL\r
   );\r
 \r
 /**\r
@@ -136,7 +135,7 @@ InitializePageTableLib (
 VOID *\r
 EFIAPI\r
 AllocatePageTableMemory (\r
-  IN UINTN           Pages\r
+  IN UINTN  Pages\r
   );\r
 \r
 /**\r
@@ -149,9 +148,9 @@ AllocatePageTableMemory (
 **/\r
 VOID\r
 GetPagingDetails (\r
-  IN  PAGE_TABLE_LIB_PAGING_CONTEXT_DATA *PagingContextData,\r
-  OUT UINTN                              **PageTableBase     OPTIONAL,\r
-  OUT UINT32                             **Attributes        OPTIONAL\r
+  IN  PAGE_TABLE_LIB_PAGING_CONTEXT_DATA  *PagingContextData,\r
+  OUT UINTN                               **PageTableBase     OPTIONAL,\r
+  OUT UINT32                              **Attributes        OPTIONAL\r
   );\r
 \r
 #endif\r

diff --git a/UefiCpuPkg/CpuDxe/Ia32/PagingAttribute.c b/UefiCpuPkg/CpuDxe/Ia32/PagingAttribute.c
index 3325a42dd2d49fcfe4bbbd8d7de0cca960f88d6e..9145c17ad2761c75a490d8135625ea05b5bac7bd 100644 (file)
--- a/UefiCpuPkg/CpuDxe/Ia32/PagingAttribute.c
+++ b/UefiCpuPkg/CpuDxe/Ia32/PagingAttribute.c
@@ -8,7 +8,6 @@
 \r
 #include "CpuPageTable.h"\r
 \r
-\r
 /**\r
   Get paging details.\r
 \r
@@ -19,16 +18,16 @@
 **/\r
 VOID\r
 GetPagingDetails (\r
-  IN  PAGE_TABLE_LIB_PAGING_CONTEXT_DATA *PagingContextData,\r
-  OUT UINTN                              **PageTableBase     OPTIONAL,\r
-  OUT UINT32                             **Attributes        OPTIONAL\r
+  IN  PAGE_TABLE_LIB_PAGING_CONTEXT_DATA  *PagingContextData,\r
+  OUT UINTN                               **PageTableBase     OPTIONAL,\r
+  OUT UINT32                              **Attributes        OPTIONAL\r
   )\r
 {\r
   if (PageTableBase != NULL) {\r
     *PageTableBase = &PagingContextData->Ia32.PageTableBase;\r
   }\r
+\r
   if (Attributes != NULL) {\r
     *Attributes = &PagingContextData->Ia32.Attributes;\r
   }\r
 }\r
-\r

diff --git a/UefiCpuPkg/CpuDxe/X64/PagingAttribute.c b/UefiCpuPkg/CpuDxe/X64/PagingAttribute.c
index 79679356122c057a41c8020e86901d5292cbb84d..31ec0caff82191770c4dfa33ca1a4da938b4132c 100644 (file)
--- a/UefiCpuPkg/CpuDxe/X64/PagingAttribute.c
+++ b/UefiCpuPkg/CpuDxe/X64/PagingAttribute.c
@@ -8,7 +8,6 @@
 \r
 #include "CpuPageTable.h"\r
 \r
-\r
 /**\r
   Get paging details.\r
 \r
@@ -19,16 +18,16 @@
 **/\r
 VOID\r
 GetPagingDetails (\r
-  IN  PAGE_TABLE_LIB_PAGING_CONTEXT_DATA *PagingContextData,\r
-  OUT UINTN                              **PageTableBase     OPTIONAL,\r
-  OUT UINT32                             **Attributes        OPTIONAL\r
+  IN  PAGE_TABLE_LIB_PAGING_CONTEXT_DATA  *PagingContextData,\r
+  OUT UINTN                               **PageTableBase     OPTIONAL,\r
+  OUT UINT32                              **Attributes        OPTIONAL\r
   )\r
 {\r
   if (PageTableBase != NULL) {\r
     *PageTableBase = &PagingContextData->X64.PageTableBase;\r
   }\r
+\r
   if (Attributes != NULL) {\r
     *Attributes = &PagingContextData->X64.Attributes;\r
   }\r
 }\r
-\r

diff --git a/UefiCpuPkg/CpuFeatures/CpuFeaturesDxe.c b/UefiCpuPkg/CpuFeatures/CpuFeaturesDxe.c
index 230b9fad7ed778c724a95e7ee65f91b96d1776fb..0a0e14a134303382e50bdebc72d3b2c804aa861a 100644 (file)
--- a/UefiCpuPkg/CpuFeatures/CpuFeaturesDxe.c
+++ b/UefiCpuPkg/CpuFeatures/CpuFeaturesDxe.c
@@ -18,7 +18,6 @@
 #include <Protocol/SmmConfiguration.h>\r
 #include <Guid/CpuFeaturesInitDone.h>\r
 \r
-\r
 /**\r
   Worker function to perform CPU feature initialization.\r
 \r
@@ -28,8 +27,8 @@ CpuFeaturesInitializeWorker (
   VOID\r
   )\r
 {\r
-  EFI_STATUS             Status;\r
-  EFI_HANDLE             Handle;\r
+  EFI_STATUS  Status;\r
+  EFI_HANDLE  Handle;\r
 \r
   CpuFeaturesDetect ();\r
 \r
@@ -57,12 +56,12 @@ CpuFeaturesInitializeWorker (
 VOID\r
 EFIAPI\r
 SmmConfigurationEventNotify (\r
-  IN EFI_EVENT                         Event,\r
-  IN VOID                              *Context\r
+  IN EFI_EVENT  Event,\r
+  IN VOID       *Context\r
   )\r
 {\r
-  EFI_STATUS                           Status;\r
-  EFI_SMM_CONFIGURATION_PROTOCOL       *SmmConfiguration;\r
+  EFI_STATUS                      Status;\r
+  EFI_SMM_CONFIGURATION_PROTOCOL  *SmmConfiguration;\r
 \r
   //\r
   // Make sure this notification is for this handler\r
@@ -91,8 +90,8 @@ SmmConfigurationEventNotify (
 EFI_STATUS\r
 EFIAPI\r
 CpuFeaturesDxeInitialize (\r
-  IN EFI_HANDLE                            ImageHandle,\r
-  IN EFI_SYSTEM_TABLE                      *SystemTable\r
+  IN EFI_HANDLE        ImageHandle,\r
+  IN EFI_SYSTEM_TABLE  *SystemTable\r
   )\r
 {\r
   VOID        *Registration;\r
@@ -133,4 +132,3 @@ CpuFeaturesDxeInitialize (
 \r
   return EFI_SUCCESS;\r
 }\r
-\r

diff --git a/UefiCpuPkg/CpuFeatures/CpuFeaturesPei.c b/UefiCpuPkg/CpuFeatures/CpuFeaturesPei.c
index be559a959555048dda3932f076cc06e803b01f32..8448668e5ad1bd50f2a1c879ab35272e69bc6e48 100644 (file)
--- a/UefiCpuPkg/CpuFeatures/CpuFeaturesPei.c
+++ b/UefiCpuPkg/CpuFeatures/CpuFeaturesPei.c
@@ -16,7 +16,7 @@
 \r
 #include <Guid/CpuFeaturesInitDone.h>\r
 \r
-EFI_PEI_PPI_DESCRIPTOR           mPeiCpuFeaturesInitDonePpiDesc = {\r
+EFI_PEI_PPI_DESCRIPTOR  mPeiCpuFeaturesInitDonePpiDesc = {\r
   (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),\r
   &gEdkiiCpuFeaturesInitDoneGuid,\r
   NULL\r
@@ -40,14 +40,15 @@ CpuFeaturesPeimInitialize (
   IN CONST EFI_PEI_SERVICES     **PeiServices\r
   )\r
 {\r
-  EFI_STATUS                 Status;\r
-  EFI_BOOT_MODE              BootMode;\r
+  EFI_STATUS     Status;\r
+  EFI_BOOT_MODE  BootMode;\r
 \r
   Status = PeiServicesGetBootMode (&BootMode);\r
   ASSERT_EFI_ERROR (Status);\r
 \r
-  if (BootMode == BOOT_ON_S3_RESUME &&\r
-      !PcdGetBool (PcdCpuFeaturesInitOnS3Resume)) {\r
+  if ((BootMode == BOOT_ON_S3_RESUME) &&\r
+      !PcdGetBool (PcdCpuFeaturesInitOnS3Resume))\r
+  {\r
     //\r
     // Does nothing when if PcdCpuFeaturesInitOnS3Resume is FLASE\r
     // on S3 boot mode\r
@@ -62,7 +63,7 @@ CpuFeaturesPeimInitialize (
   //\r
   // Install CPU Features Init Done PPI\r
   //\r
-  Status = PeiServicesInstallPpi(&mPeiCpuFeaturesInitDonePpiDesc);\r
+  Status = PeiServicesInstallPpi (&mPeiCpuFeaturesInitDonePpiDesc);\r
   ASSERT_EFI_ERROR (Status);\r
 \r
   //\r
@@ -72,4 +73,3 @@ CpuFeaturesPeimInitialize (
 \r
   return EFI_SUCCESS;\r
 }\r
-\r

diff --git a/UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.c b/UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.c
index ade8207288b97eedffcaa2312df7210338716f35..87f4f805caf0258251d028a425dd611d503ce01f 100644 (file)
--- a/UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.c
+++ b/UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.c
@@ -18,7 +18,7 @@ EFI_HANDLE  mHandle = NULL;
 //\r
 // CPU I/O 2 Protocol instance\r
 //\r
-EFI_CPU_IO2_PROTOCOL mCpuIo2 = {\r
+EFI_CPU_IO2_PROTOCOL  mCpuIo2 = {\r
   {\r
     CpuMemoryServiceRead,\r
     CpuMemoryServiceWrite\r
@@ -32,7 +32,7 @@ EFI_CPU_IO2_PROTOCOL mCpuIo2 = {
 //\r
 // Lookup table for increment values based on transfer widths\r
 //\r
-UINT8 mInStride[] = {\r
+UINT8  mInStride[] = {\r
   1, // EfiCpuIoWidthUint8\r
   2, // EfiCpuIoWidthUint16\r
   4, // EfiCpuIoWidthUint32\r
@@ -50,7 +50,7 @@ UINT8 mInStride[] = {
 //\r
 // Lookup table for increment values based on transfer widths\r
 //\r
-UINT8 mOutStride[] = {\r
+UINT8  mOutStride[] = {\r
   1, // EfiCpuIoWidthUint8\r
   2, // EfiCpuIoWidthUint16\r
   4, // EfiCpuIoWidthUint32\r
@@ -120,14 +120,14 @@ CpuIoCheckParameter (
   // For FIFO type, the target address won't increase during the access,\r
   // so treat Count as 1\r
   //\r
-  if (Width >= EfiCpuIoWidthFifoUint8 && Width <= EfiCpuIoWidthFifoUint64) {\r
+  if ((Width >= EfiCpuIoWidthFifoUint8) && (Width <= EfiCpuIoWidthFifoUint64)) {\r
     Count = 1;\r
   }\r
 \r
   //\r
   // Check to see if Width is in the valid range for I/O Port operations\r
   //\r
-  Width = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);\r
+  Width = (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03);\r
   if (!MmioOperation && (Width == EfiCpuIoWidthUint64)) {\r
     return EFI_INVALID_PARAMETER;\r
   }\r
@@ -164,6 +164,7 @@ CpuIoCheckParameter (
     if (MaxCount < (Count - 1)) {\r
       return EFI_UNSUPPORTED;\r
     }\r
+\r
     if (Address > LShiftU64 (MaxCount - Count + 1, Width)) {\r
       return EFI_UNSUPPORTED;\r
     }\r
@@ -243,9 +244,9 @@ CpuMemoryServiceRead (
   //\r
   // Select loop based on the width of the transfer\r
   //\r
-  InStride = mInStride[Width];\r
-  OutStride = mOutStride[Width];\r
-  OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);\r
+  InStride       = mInStride[Width];\r
+  OutStride      = mOutStride[Width];\r
+  OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03);\r
   for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {\r
     if (OperationWidth == EfiCpuIoWidthUint8) {\r
       *Uint8Buffer = MmioRead8 ((UINTN)Address);\r
@@ -257,6 +258,7 @@ CpuMemoryServiceRead (
       *((UINT64 *)Uint8Buffer) = MmioRead64 ((UINTN)Address);\r
     }\r
   }\r
+\r
   return EFI_SUCCESS;\r
 }\r
 \r
@@ -323,9 +325,9 @@ CpuMemoryServiceWrite (
   //\r
   // Select loop based on the width of the transfer\r
   //\r
-  InStride = mInStride[Width];\r
-  OutStride = mOutStride[Width];\r
-  OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);\r
+  InStride       = mInStride[Width];\r
+  OutStride      = mOutStride[Width];\r
+  OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03);\r
   for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {\r
     if (OperationWidth == EfiCpuIoWidthUint8) {\r
       MmioWrite8 ((UINTN)Address, *Uint8Buffer);\r
@@ -337,6 +339,7 @@ CpuMemoryServiceWrite (
       MmioWrite64 ((UINTN)Address, *((UINT64 *)Uint8Buffer));\r
     }\r
   }\r
+\r
   return EFI_SUCCESS;\r
 }\r
 \r
@@ -403,31 +406,31 @@ CpuIoServiceRead (
   //\r
   // Select loop based on the width of the transfer\r
   //\r
-  InStride = mInStride[Width];\r
-  OutStride = mOutStride[Width];\r
-  OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);\r
+  InStride       = mInStride[Width];\r
+  OutStride      = mOutStride[Width];\r
+  OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03);\r
 \r
   //\r
   // Fifo operations supported for (mInStride[Width] == 0)\r
   //\r
   if (InStride == 0) {\r
     switch (OperationWidth) {\r
-    case EfiCpuIoWidthUint8:\r
-      IoReadFifo8 ((UINTN)Address, Count, Buffer);\r
-      return EFI_SUCCESS;\r
-    case EfiCpuIoWidthUint16:\r
-      IoReadFifo16 ((UINTN)Address, Count, Buffer);\r
-      return EFI_SUCCESS;\r
-    case EfiCpuIoWidthUint32:\r
-      IoReadFifo32 ((UINTN)Address, Count, Buffer);\r
-      return EFI_SUCCESS;\r
-    default:\r
-      //\r
-      // The CpuIoCheckParameter call above will ensure that this\r
-      // path is not taken.\r
-      //\r
-      ASSERT (FALSE);\r
-      break;\r
+      case EfiCpuIoWidthUint8:\r
+        IoReadFifo8 ((UINTN)Address, Count, Buffer);\r
+        return EFI_SUCCESS;\r
+      case EfiCpuIoWidthUint16:\r
+        IoReadFifo16 ((UINTN)Address, Count, Buffer);\r
+        return EFI_SUCCESS;\r
+      case EfiCpuIoWidthUint32:\r
+        IoReadFifo32 ((UINTN)Address, Count, Buffer);\r
+        return EFI_SUCCESS;\r
+      default:\r
+        //\r
+        // The CpuIoCheckParameter call above will ensure that this\r
+        // path is not taken.\r
+        //\r
+        ASSERT (FALSE);\r
+        break;\r
     }\r
   }\r
 \r
@@ -510,31 +513,31 @@ CpuIoServiceWrite (
   //\r
   // Select loop based on the width of the transfer\r
   //\r
-  InStride = mInStride[Width];\r
-  OutStride = mOutStride[Width];\r
-  OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);\r
+  InStride       = mInStride[Width];\r
+  OutStride      = mOutStride[Width];\r
+  OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03);\r
 \r
   //\r
   // Fifo operations supported for (mInStride[Width] == 0)\r
   //\r
   if (InStride == 0) {\r
     switch (OperationWidth) {\r
-    case EfiCpuIoWidthUint8:\r
-      IoWriteFifo8 ((UINTN)Address, Count, Buffer);\r
-      return EFI_SUCCESS;\r
-    case EfiCpuIoWidthUint16:\r
-      IoWriteFifo16 ((UINTN)Address, Count, Buffer);\r
-      return EFI_SUCCESS;\r
-    case EfiCpuIoWidthUint32:\r
-      IoWriteFifo32 ((UINTN)Address, Count, Buffer);\r
-      return EFI_SUCCESS;\r
-    default:\r
-      //\r
-      // The CpuIoCheckParameter call above will ensure that this\r
-      // path is not taken.\r
-      //\r
-      ASSERT (FALSE);\r
-      break;\r
+      case EfiCpuIoWidthUint8:\r
+        IoWriteFifo8 ((UINTN)Address, Count, Buffer);\r
+        return EFI_SUCCESS;\r
+      case EfiCpuIoWidthUint16:\r
+        IoWriteFifo16 ((UINTN)Address, Count, Buffer);\r
+        return EFI_SUCCESS;\r
+      case EfiCpuIoWidthUint32:\r
+        IoWriteFifo32 ((UINTN)Address, Count, Buffer);\r
+        return EFI_SUCCESS;\r
+      default:\r
+        //\r
+        // The CpuIoCheckParameter call above will ensure that this\r
+        // path is not taken.\r
+        //\r
+        ASSERT (FALSE);\r
+        break;\r
     }\r
   }\r
 \r
@@ -568,12 +571,13 @@ CpuIo2Initialize (
   IN EFI_SYSTEM_TABLE  *SystemTable\r
   )\r
 {\r
-  EFI_STATUS Status;\r
+  EFI_STATUS  Status;\r
 \r
   ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gEfiCpuIo2ProtocolGuid);\r
   Status = gBS->InstallMultipleProtocolInterfaces (\r
                   &mHandle,\r
-                  &gEfiCpuIo2ProtocolGuid, &mCpuIo2,\r
+                  &gEfiCpuIo2ProtocolGuid,\r
+                  &mCpuIo2,\r
                   NULL\r
                   );\r
   ASSERT_EFI_ERROR (Status);\r

diff --git a/UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.h b/UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.h
index 3b16b205f69b44189c1a5ffe61764aee4c06dec8..7ebde0759ba9a67e077e27943a7a4bdd336d47d9 100644 (file)
--- a/UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.h
+++ b/UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.h
@@ -18,7 +18,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
 #include <Library/IoLib.h>\r
 #include <Library/UefiBootServicesTableLib.h>\r
 \r
-#define MAX_IO_PORT_ADDRESS   0xFFFF\r
+#define MAX_IO_PORT_ADDRESS  0xFFFF\r
 \r
 /**\r
   Reads memory-mapped registers.\r

diff --git a/UefiCpuPkg/CpuIo2Smm/CpuIo2Mm.c b/UefiCpuPkg/CpuIo2Smm/CpuIo2Mm.c
index 7e314eaa1558073e071d018403448094bc59b272..44e52562a89f50d7e4090088bfa81ee9dcf80c23 100644 (file)
--- a/UefiCpuPkg/CpuIo2Smm/CpuIo2Mm.c
+++ b/UefiCpuPkg/CpuIo2Smm/CpuIo2Mm.c
@@ -16,7 +16,7 @@ EFI_HANDLE  mHandle = NULL;
 //\r
 // SMM CPU I/O Protocol instance\r
 //\r
-EFI_SMM_CPU_IO2_PROTOCOL mSmmCpuIo2 = {\r
+EFI_SMM_CPU_IO2_PROTOCOL  mSmmCpuIo2 = {\r
   {\r
     CpuMemoryServiceRead,\r
     CpuMemoryServiceWrite\r
@@ -30,7 +30,7 @@ EFI_SMM_CPU_IO2_PROTOCOL mSmmCpuIo2 = {
 //\r
 // Lookup table for increment values based on transfer widths\r
 //\r
-UINT8 mStride[] = {\r
+UINT8  mStride[] = {\r
   1, // SMM_IO_UINT8\r
   2, // SMM_IO_UINT16\r
   4, // SMM_IO_UINT32\r
@@ -112,6 +112,7 @@ CpuIoCheckParameter (
     if (MaxCount < (Count - 1)) {\r
       return EFI_UNSUPPORTED;\r
     }\r
+\r
     if (Address > LShiftU64 (MaxCount - Count + 1, Width)) {\r
       return EFI_UNSUPPORTED;\r
     }\r
@@ -184,6 +185,7 @@ CpuMemoryServiceRead (
       *((UINT64 *)Uint8Buffer) = MmioRead64 ((UINTN)Address);\r
     }\r
   }\r
+\r
   return EFI_SUCCESS;\r
 }\r
 \r
@@ -244,6 +246,7 @@ CpuMemoryServiceWrite (
       MmioWrite64 ((UINTN)Address, *((UINT64 *)Uint8Buffer));\r
     }\r
   }\r
+\r
   return EFI_SUCCESS;\r
 }\r
 \r

diff --git a/UefiCpuPkg/CpuIo2Smm/CpuIo2Mm.h b/UefiCpuPkg/CpuIo2Smm/CpuIo2Mm.h
index eda9fbb090cdca98f914be9e84ecff8d48bb406e..840451355432fc25abcf62ade2e1e9b119c19273 100644 (file)
--- a/UefiCpuPkg/CpuIo2Smm/CpuIo2Mm.h
+++ b/UefiCpuPkg/CpuIo2Smm/CpuIo2Mm.h
@@ -19,7 +19,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
 #include <Library/MmServicesTableLib.h>\r
 #include <Library/BaseMemoryLib.h>\r
 \r
-#define MAX_IO_PORT_ADDRESS   0xFFFF\r
+#define MAX_IO_PORT_ADDRESS  0xFFFF\r
 \r
 /**\r
   Reads memory-mapped registers.\r

diff --git a/UefiCpuPkg/CpuIoPei/CpuIoPei.c b/UefiCpuPkg/CpuIoPei/CpuIoPei.c
index 98bae46e2970b9597e6c940d3677363dcdd5ea79..0d0fe3d4bc96a6d713bbc6e8aa1caedda484f0ba 100644 (file)
--- a/UefiCpuPkg/CpuIoPei/CpuIoPei.c
+++ b/UefiCpuPkg/CpuIoPei/CpuIoPei.c
@@ -43,7 +43,7 @@ EFI_PEI_CPU_IO_PPI  gCpuIoPpi = {
 //\r
 // PPI Descriptor used to install the CPU I/O PPI\r
 //\r
-EFI_PEI_PPI_DESCRIPTOR gPpiList = {\r
+EFI_PEI_PPI_DESCRIPTOR  gPpiList = {\r
   (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),\r
   &gEfiPeiCpuIoPpiInstalledGuid,\r
   NULL\r
@@ -52,7 +52,7 @@ EFI_PEI_PPI_DESCRIPTOR gPpiList = {
 //\r
 // Lookup table for increment values based on transfer widths\r
 //\r
-UINT8 mInStride[] = {\r
+UINT8  mInStride[] = {\r
   1, // EfiPeiCpuIoWidthUint8\r
   2, // EfiPeiCpuIoWidthUint16\r
   4, // EfiPeiCpuIoWidthUint32\r
@@ -70,7 +70,7 @@ UINT8 mInStride[] = {
 //\r
 // Lookup table for increment values based on transfer widths\r
 //\r
-UINT8 mOutStride[] = {\r
+UINT8  mOutStride[] = {\r
   1, // EfiPeiCpuIoWidthUint8\r
   2, // EfiPeiCpuIoWidthUint16\r
   4, // EfiPeiCpuIoWidthUint32\r
@@ -131,14 +131,14 @@ CpuIoCheckParameter (
   // For FIFO type, the target address won't increase during the access,\r
   // so treat Count as 1\r
   //\r
-  if (Width >= EfiPeiCpuIoWidthFifoUint8 && Width <= EfiPeiCpuIoWidthFifoUint64) {\r
+  if ((Width >= EfiPeiCpuIoWidthFifoUint8) && (Width <= EfiPeiCpuIoWidthFifoUint64)) {\r
     Count = 1;\r
   }\r
 \r
   //\r
   // Check to see if Width is in the valid range for I/O Port operations\r
   //\r
-  Width = (EFI_PEI_CPU_IO_PPI_WIDTH) (Width & 0x03);\r
+  Width = (EFI_PEI_CPU_IO_PPI_WIDTH)(Width & 0x03);\r
   if (!MmioOperation && (Width == EfiPeiCpuIoWidthUint64)) {\r
     return EFI_INVALID_PARAMETER;\r
   }\r
@@ -168,6 +168,7 @@ CpuIoCheckParameter (
     if (MaxCount < (Count - 1)) {\r
       return EFI_UNSUPPORTED;\r
     }\r
+\r
     if (Address > LShiftU64 (MaxCount - Count + 1, Width)) {\r
       return EFI_UNSUPPORTED;\r
     }\r
@@ -220,10 +221,10 @@ CpuMemoryServiceRead (
   //\r
   // Select loop based on the width of the transfer\r
   //\r
-  InStride = mInStride[Width];\r
-  OutStride = mOutStride[Width];\r
-  OperationWidth = (EFI_PEI_CPU_IO_PPI_WIDTH) (Width & 0x03);\r
-  Aligned = (BOOLEAN)(((UINTN)Buffer & (mInStride[OperationWidth] - 1)) == 0x00);\r
+  InStride       = mInStride[Width];\r
+  OutStride      = mOutStride[Width];\r
+  OperationWidth = (EFI_PEI_CPU_IO_PPI_WIDTH)(Width & 0x03);\r
+  Aligned        = (BOOLEAN)(((UINTN)Buffer & (mInStride[OperationWidth] - 1)) == 0x00);\r
   for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {\r
     if (OperationWidth == EfiPeiCpuIoWidthUint8) {\r
       *Uint8Buffer = MmioRead8 ((UINTN)Address);\r
@@ -247,6 +248,7 @@ CpuMemoryServiceRead (
       }\r
     }\r
   }\r
+\r
   return EFI_SUCCESS;\r
 }\r
 \r
@@ -294,10 +296,10 @@ CpuMemoryServiceWrite (
   //\r
   // Select loop based on the width of the transfer\r
   //\r
-  InStride = mInStride[Width];\r
-  OutStride = mOutStride[Width];\r
-  OperationWidth = (EFI_PEI_CPU_IO_PPI_WIDTH) (Width & 0x03);\r
-  Aligned = (BOOLEAN)(((UINTN)Buffer & (mInStride[OperationWidth] - 1)) == 0x00);\r
+  InStride       = mInStride[Width];\r
+  OutStride      = mOutStride[Width];\r
+  OperationWidth = (EFI_PEI_CPU_IO_PPI_WIDTH)(Width & 0x03);\r
+  Aligned        = (BOOLEAN)(((UINTN)Buffer & (mInStride[OperationWidth] - 1)) == 0x00);\r
   for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {\r
     if (OperationWidth == EfiPeiCpuIoWidthUint8) {\r
       MmioWrite8 ((UINTN)Address, *Uint8Buffer);\r
@@ -321,6 +323,7 @@ CpuMemoryServiceWrite (
       }\r
     }\r
   }\r
+\r
   return EFI_SUCCESS;\r
 }\r
 \r
@@ -368,31 +371,31 @@ CpuIoServiceRead (
   //\r
   // Select loop based on the width of the transfer\r
   //\r
-  InStride = mInStride[Width];\r
-  OutStride = mOutStride[Width];\r
-  OperationWidth = (EFI_PEI_CPU_IO_PPI_WIDTH) (Width & 0x03);\r
+  InStride       = mInStride[Width];\r
+  OutStride      = mOutStride[Width];\r
+  OperationWidth = (EFI_PEI_CPU_IO_PPI_WIDTH)(Width & 0x03);\r
 \r
   //\r
   // Fifo operations supported for (mInStride[Width] == 0)\r
   //\r
   if (InStride == 0) {\r
     switch (OperationWidth) {\r
-    case EfiPeiCpuIoWidthUint8:\r
-      IoReadFifo8 ((UINTN)Address, Count, Buffer);\r
-      return EFI_SUCCESS;\r
-    case EfiPeiCpuIoWidthUint16:\r
-      IoReadFifo16 ((UINTN)Address, Count, Buffer);\r
-      return EFI_SUCCESS;\r
-    case EfiPeiCpuIoWidthUint32:\r
-      IoReadFifo32 ((UINTN)Address, Count, Buffer);\r
-      return EFI_SUCCESS;\r
-    default:\r
-      //\r
-      // The CpuIoCheckParameter call above will ensure that this\r
-      // path is not taken.\r
-      //\r
-      ASSERT (FALSE);\r
-      break;\r
+      case EfiPeiCpuIoWidthUint8:\r
+        IoReadFifo8 ((UINTN)Address, Count, Buffer);\r
+        return EFI_SUCCESS;\r
+      case EfiPeiCpuIoWidthUint16:\r
+        IoReadFifo16 ((UINTN)Address, Count, Buffer);\r
+        return EFI_SUCCESS;\r
+      case EfiPeiCpuIoWidthUint32:\r
+        IoReadFifo32 ((UINTN)Address, Count, Buffer);\r
+        return EFI_SUCCESS;\r
+      default:\r
+        //\r
+        // The CpuIoCheckParameter call above will ensure that this\r
+        // path is not taken.\r
+        //\r
+        ASSERT (FALSE);\r
+        break;\r
     }\r
   }\r
 \r
@@ -465,31 +468,31 @@ CpuIoServiceWrite (
   //\r
   // Select loop based on the width of the transfer\r
   //\r
-  InStride = mInStride[Width];\r
-  OutStride = mOutStride[Width];\r
-  OperationWidth = (EFI_PEI_CPU_IO_PPI_WIDTH) (Width & 0x03);\r
+  InStride       = mInStride[Width];\r
+  OutStride      = mOutStride[Width];\r
+  OperationWidth = (EFI_PEI_CPU_IO_PPI_WIDTH)(Width & 0x03);\r
 \r
   //\r
   // Fifo operations supported for (mInStride[Width] == 0)\r
   //\r
   if (InStride == 0) {\r
     switch (OperationWidth) {\r
-    case EfiPeiCpuIoWidthUint8:\r
-      IoWriteFifo8 ((UINTN)Address, Count, Buffer);\r
-      return EFI_SUCCESS;\r
-    case EfiPeiCpuIoWidthUint16:\r
-      IoWriteFifo16 ((UINTN)Address, Count, Buffer);\r
-      return EFI_SUCCESS;\r
-    case EfiPeiCpuIoWidthUint32:\r
-      IoWriteFifo32 ((UINTN)Address, Count, Buffer);\r
-      return EFI_SUCCESS;\r
-    default:\r
-      //\r
-      // The CpuIoCheckParameter call above will ensure that this\r
-      // path is not taken.\r
-      //\r
-      ASSERT (FALSE);\r
-      break;\r
+      case EfiPeiCpuIoWidthUint8:\r
+        IoWriteFifo8 ((UINTN)Address, Count, Buffer);\r
+        return EFI_SUCCESS;\r
+      case EfiPeiCpuIoWidthUint16:\r
+        IoWriteFifo16 ((UINTN)Address, Count, Buffer);\r
+        return EFI_SUCCESS;\r
+      case EfiPeiCpuIoWidthUint32:\r
+        IoWriteFifo32 ((UINTN)Address, Count, Buffer);\r
+        return EFI_SUCCESS;\r
+      default:\r
+        //\r
+        // The CpuIoCheckParameter call above will ensure that this\r
+        // path is not taken.\r
+        //\r
+        ASSERT (FALSE);\r
+        break;\r
     }\r
   }\r
 \r
@@ -572,9 +575,9 @@ CpuIoRead16 (
 UINT32\r
 EFIAPI\r
 CpuIoRead32 (\r
-  IN CONST EFI_PEI_SERVICES     **PeiServices,\r
-  IN CONST EFI_PEI_CPU_IO_PPI   *This,\r
-  IN UINT64                     Address\r
+  IN CONST EFI_PEI_SERVICES    **PeiServices,\r
+  IN CONST EFI_PEI_CPU_IO_PPI  *This,\r
+  IN UINT64                    Address\r
   )\r
 {\r
   return IoRead32 ((UINTN)Address);\r

diff --git a/UefiCpuPkg/CpuIoPei/CpuIoPei.h b/UefiCpuPkg/CpuIoPei/CpuIoPei.h
index e8676df906c259d9753ced3f86b872249fbf9031..eb1982f9470bd8efdbd56d69240698a6aeabfc3d 100644 (file)
--- a/UefiCpuPkg/CpuIoPei/CpuIoPei.h
+++ b/UefiCpuPkg/CpuIoPei/CpuIoPei.h
@@ -18,7 +18,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
 #include <Library/IoLib.h>\r
 #include <Library/PeiServicesLib.h>\r
 \r
-#define MAX_IO_PORT_ADDRESS   0xFFFF\r
+#define MAX_IO_PORT_ADDRESS  0xFFFF\r
 \r
 /**\r
   Reads memory-mapped registers.\r
@@ -149,9 +149,9 @@ CpuIoServiceWrite (
 UINT8\r
 EFIAPI\r
 CpuIoRead8 (\r
-  IN  CONST EFI_PEI_SERVICES      **PeiServices,\r
-  IN  CONST EFI_PEI_CPU_IO_PPI    *This,\r
-  IN  UINT64                      Address\r
+  IN  CONST EFI_PEI_SERVICES    **PeiServices,\r
+  IN  CONST EFI_PEI_CPU_IO_PPI  *This,\r
+  IN  UINT64                    Address\r
   );\r
 \r
 /**\r
@@ -168,9 +168,9 @@ CpuIoRead8 (
 UINT16\r
 EFIAPI\r
 CpuIoRead16 (\r
-  IN  CONST EFI_PEI_SERVICES      **PeiServices,\r
-  IN  CONST EFI_PEI_CPU_IO_PPI    *This,\r
-  IN  UINT64                      Address\r
+  IN  CONST EFI_PEI_SERVICES    **PeiServices,\r
+  IN  CONST EFI_PEI_CPU_IO_PPI  *This,\r
+  IN  UINT64                    Address\r
   );\r
 \r
 /**\r
@@ -187,9 +187,9 @@ CpuIoRead16 (
 UINT32\r
 EFIAPI\r
 CpuIoRead32 (\r
-  IN  CONST EFI_PEI_SERVICES      **PeiServices,\r
-  IN  CONST EFI_PEI_CPU_IO_PPI    *This,\r
-  IN  UINT64                      Address\r
+  IN  CONST EFI_PEI_SERVICES    **PeiServices,\r
+  IN  CONST EFI_PEI_CPU_IO_PPI  *This,\r
+  IN  UINT64                    Address\r
   );\r
 \r
 /**\r
@@ -206,9 +206,9 @@ CpuIoRead32 (
 UINT64\r
 EFIAPI\r
 CpuIoRead64 (\r
-  IN  CONST EFI_PEI_SERVICES      **PeiServices,\r
-  IN  CONST EFI_PEI_CPU_IO_PPI    *This,\r
-  IN  UINT64                      Address\r
+  IN  CONST EFI_PEI_SERVICES    **PeiServices,\r
+  IN  CONST EFI_PEI_CPU_IO_PPI  *This,\r
+  IN  UINT64                    Address\r
   );\r
 \r
 /**\r
@@ -224,10 +224,10 @@ CpuIoRead64 (
 VOID\r
 EFIAPI\r
 CpuIoWrite8 (\r
-  IN  CONST EFI_PEI_SERVICES      **PeiServices,\r
-  IN  CONST EFI_PEI_CPU_IO_PPI    *This,\r
-  IN  UINT64                      Address,\r
-  IN  UINT8                       Data\r
+  IN  CONST EFI_PEI_SERVICES    **PeiServices,\r
+  IN  CONST EFI_PEI_CPU_IO_PPI  *This,\r
+  IN  UINT64                    Address,\r
+  IN  UINT8                     Data\r
   );\r
 \r
 /**\r
@@ -243,10 +243,10 @@ CpuIoWrite8 (
 VOID\r
 EFIAPI\r
 CpuIoWrite16 (\r
-  IN  CONST EFI_PEI_SERVICES      **PeiServices,\r
-  IN  CONST EFI_PEI_CPU_IO_PPI    *This,\r
-  IN  UINT64                      Address,\r
-  IN  UINT16                      Data\r
+  IN  CONST EFI_PEI_SERVICES    **PeiServices,\r
+  IN  CONST EFI_PEI_CPU_IO_PPI  *This,\r
+  IN  UINT64                    Address,\r
+  IN  UINT16                    Data\r
   );\r
 \r
 /**\r
@@ -262,10 +262,10 @@ CpuIoWrite16 (
 VOID\r
 EFIAPI\r
 CpuIoWrite32 (\r
-  IN  CONST EFI_PEI_SERVICES      **PeiServices,\r
-  IN  CONST EFI_PEI_CPU_IO_PPI    *This,\r
-  IN  UINT64                      Address,\r
-  IN  UINT32                      Data\r
+  IN  CONST EFI_PEI_SERVICES    **PeiServices,\r
+  IN  CONST EFI_PEI_CPU_IO_PPI  *This,\r
+  IN  UINT64                    Address,\r
+  IN  UINT32                    Data\r
   );\r
 \r
 /**\r
@@ -281,10 +281,10 @@ CpuIoWrite32 (
 VOID\r
 EFIAPI\r
 CpuIoWrite64 (\r
-  IN  CONST EFI_PEI_SERVICES      **PeiServices,\r
-  IN  CONST EFI_PEI_CPU_IO_PPI    *This,\r
-  IN  UINT64                      Address,\r
-  IN  UINT64                      Data\r
+  IN  CONST EFI_PEI_SERVICES    **PeiServices,\r
+  IN  CONST EFI_PEI_CPU_IO_PPI  *This,\r
+  IN  UINT64                    Address,\r
+  IN  UINT64                    Data\r
   );\r
 \r
 /**\r
@@ -301,9 +301,9 @@ CpuIoWrite64 (
 UINT8\r
 EFIAPI\r
 CpuMemRead8 (\r
-  IN  CONST EFI_PEI_SERVICES      **PeiServices,\r
-  IN  CONST EFI_PEI_CPU_IO_PPI    *This,\r
-  IN  UINT64                      Address\r
+  IN  CONST EFI_PEI_SERVICES    **PeiServices,\r
+  IN  CONST EFI_PEI_CPU_IO_PPI  *This,\r
+  IN  UINT64                    Address\r
   );\r
 \r
 /**\r
@@ -320,9 +320,9 @@ CpuMemRead8 (
 UINT16\r
 EFIAPI\r
 CpuMemRead16 (\r
-  IN  CONST EFI_PEI_SERVICES      **PeiServices,\r
-  IN  CONST EFI_PEI_CPU_IO_PPI    *This,\r
-  IN  UINT64                      Address\r
+  IN  CONST EFI_PEI_SERVICES    **PeiServices,\r
+  IN  CONST EFI_PEI_CPU_IO_PPI  *This,\r
+  IN  UINT64                    Address\r
   );\r
 \r
 /**\r
@@ -339,9 +339,9 @@ CpuMemRead16 (
 UINT32\r
 EFIAPI\r
 CpuMemRead32 (\r
-  IN  CONST EFI_PEI_SERVICES      **PeiServices,\r
-  IN  CONST EFI_PEI_CPU_IO_PPI    *This,\r
-  IN  UINT64                      Address\r
+  IN  CONST EFI_PEI_SERVICES    **PeiServices,\r
+  IN  CONST EFI_PEI_CPU_IO_PPI  *This,\r
+  IN  UINT64                    Address\r
   );\r
 \r
 /**\r
@@ -358,9 +358,9 @@ CpuMemRead32 (
 UINT64\r
 EFIAPI\r
 CpuMemRead64 (\r
-  IN  CONST EFI_PEI_SERVICES      **PeiServices,\r
-  IN  CONST EFI_PEI_CPU_IO_PPI    *This,\r
-  IN  UINT64                      Address\r
+  IN  CONST EFI_PEI_SERVICES    **PeiServices,\r
+  IN  CONST EFI_PEI_CPU_IO_PPI  *This,\r
+  IN  UINT64                    Address\r
   );\r
 \r
 /**\r
@@ -376,10 +376,10 @@ CpuMemRead64 (
 VOID\r
 EFIAPI\r
 CpuMemWrite8 (\r
-  IN  CONST EFI_PEI_SERVICES      **PeiServices,\r
-  IN  CONST EFI_PEI_CPU_IO_PPI    *This,\r
-  IN  UINT64                      Address,\r
-  IN  UINT8                       Data\r
+  IN  CONST EFI_PEI_SERVICES    **PeiServices,\r
+  IN  CONST EFI_PEI_CPU_IO_PPI  *This,\r
+  IN  UINT64                    Address,\r
+  IN  UINT8                     Data\r
   );\r
 \r
 /**\r
@@ -395,10 +395,10 @@ CpuMemWrite8 (
 VOID\r
 EFIAPI\r
 CpuMemWrite16 (\r
-  IN  CONST EFI_PEI_SERVICES      **PeiServices,\r
-  IN  CONST EFI_PEI_CPU_IO_PPI    *This,\r
-  IN  UINT64                      Address,\r
-  IN  UINT16                      Data\r
+  IN  CONST EFI_PEI_SERVICES    **PeiServices,\r
+  IN  CONST EFI_PEI_CPU_IO_PPI  *This,\r
+  IN  UINT64                    Address,\r
+  IN  UINT16                    Data\r
   );\r
 \r
 /**\r
@@ -414,10 +414,10 @@ CpuMemWrite16 (
 VOID\r
 EFIAPI\r
 CpuMemWrite32 (\r
-  IN  CONST EFI_PEI_SERVICES      **PeiServices,\r
-  IN  CONST EFI_PEI_CPU_IO_PPI    *This,\r
-  IN  UINT64                      Address,\r
-  IN  UINT32                      Data\r
+  IN  CONST EFI_PEI_SERVICES    **PeiServices,\r
+  IN  CONST EFI_PEI_CPU_IO_PPI  *This,\r
+  IN  UINT64                    Address,\r
+  IN  UINT32                    Data\r
   );\r
 \r
 /**\r
@@ -433,10 +433,10 @@ CpuMemWrite32 (
 VOID\r
 EFIAPI\r
 CpuMemWrite64 (\r
-  IN  CONST EFI_PEI_SERVICES      **PeiServices,\r
-  IN  CONST EFI_PEI_CPU_IO_PPI    *This,\r
-  IN  UINT64                      Address,\r
-  IN  UINT64                      Data\r
+  IN  CONST EFI_PEI_SERVICES    **PeiServices,\r
+  IN  CONST EFI_PEI_CPU_IO_PPI  *This,\r
+  IN  UINT64                    Address,\r
+  IN  UINT64                    Data\r
   );\r
 \r
 #endif\r

diff --git a/UefiCpuPkg/CpuMpPei/CpuBist.c b/UefiCpuPkg/CpuMpPei/CpuBist.c
index bb35bb434728bd97af9af5537eadb122f88f0ef5..7dc93cd784d4ae01774ad3b252fc8292a6a329f1 100644 (file)
--- a/UefiCpuPkg/CpuMpPei/CpuBist.c
+++ b/UefiCpuPkg/CpuMpPei/CpuBist.c
@@ -8,11 +8,11 @@
 \r
 #include "CpuMpPei.h"\r
 \r
-EFI_SEC_PLATFORM_INFORMATION2_PPI mSecPlatformInformation2Ppi = {\r
+EFI_SEC_PLATFORM_INFORMATION2_PPI  mSecPlatformInformation2Ppi = {\r
   SecPlatformInformation2\r
 };\r
 \r
-EFI_PEI_PPI_DESCRIPTOR mPeiSecPlatformInformation2Ppi = {\r
+EFI_PEI_PPI_DESCRIPTOR  mPeiSecPlatformInformation2Ppi = {\r
   (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),\r
   &gEfiSecPlatformInformation2PpiGuid,\r
   &mSecPlatformInformation2Ppi\r
@@ -33,14 +33,14 @@ EFI_PEI_PPI_DESCRIPTOR mPeiSecPlatformInformation2Ppi = {
 EFI_STATUS\r
 EFIAPI\r
 SecPlatformInformation2 (\r
-  IN CONST EFI_PEI_SERVICES                   **PeiServices,\r
-  IN OUT UINT64                               *StructureSize,\r
-     OUT EFI_SEC_PLATFORM_INFORMATION_RECORD2 *PlatformInformationRecord2\r
+  IN CONST EFI_PEI_SERVICES                 **PeiServices,\r
+  IN OUT UINT64                             *StructureSize,\r
+  OUT EFI_SEC_PLATFORM_INFORMATION_RECORD2  *PlatformInformationRecord2\r
   )\r
 {\r
-  EFI_HOB_GUID_TYPE       *GuidHob;\r
-  VOID                    *DataInHob;\r
-  UINTN                   DataSize;\r
+  EFI_HOB_GUID_TYPE  *GuidHob;\r
+  VOID               *DataInHob;\r
+  UINTN              DataSize;\r
 \r
   GuidHob = GetFirstGuidHob (&gEfiSecPlatformInformation2PpiGuid);\r
   if (GuidHob == NULL) {\r
@@ -54,12 +54,12 @@ SecPlatformInformation2 (
   //\r
   // return the information from BistHob\r
   //\r
-  if ((*StructureSize) < (UINT64) DataSize) {\r
-    *StructureSize = (UINT64) DataSize;\r
+  if ((*StructureSize) < (UINT64)DataSize) {\r
+    *StructureSize = (UINT64)DataSize;\r
     return EFI_BUFFER_TOO_SMALL;\r
   }\r
 \r
-  *StructureSize = (UINT64) DataSize;\r
+  *StructureSize = (UINT64)DataSize;\r
   CopyMem (PlatformInformationRecord2, DataInHob, DataSize);\r
   return EFI_SUCCESS;\r
 }\r
@@ -82,11 +82,11 @@ SecPlatformInformation2 (
 **/\r
 EFI_STATUS\r
 GetBistInfoFromPpi (\r
-  IN CONST EFI_PEI_SERVICES     **PeiServices,\r
-  IN CONST EFI_GUID             *Guid,\r
-     OUT EFI_PEI_PPI_DESCRIPTOR **PpiDescriptor,\r
-     OUT VOID                   **BistInformationData,\r
-     OUT UINT64                 *BistInformationSize OPTIONAL\r
+  IN CONST EFI_PEI_SERVICES   **PeiServices,\r
+  IN CONST EFI_GUID           *Guid,\r
+  OUT EFI_PEI_PPI_DESCRIPTOR  **PpiDescriptor,\r
+  OUT VOID                    **BistInformationData,\r
+  OUT UINT64                  *BistInformationSize OPTIONAL\r
   )\r
 {\r
   EFI_STATUS                            Status;\r
@@ -110,15 +110,15 @@ GetBistInfoFromPpi (
     //\r
     InformationSize         = 0;\r
     SecPlatformInformation2 = NULL;\r
-    Status = SecPlatformInformation2Ppi->PlatformInformation2 (\r
-                                           PeiServices,\r
-                                           &InformationSize,\r
-                                           SecPlatformInformation2\r
-                                           );\r
+    Status                  = SecPlatformInformation2Ppi->PlatformInformation2 (\r
+                                                            PeiServices,\r
+                                                            &InformationSize,\r
+                                                            SecPlatformInformation2\r
+                                                            );\r
     if (Status == EFI_BUFFER_TOO_SMALL) {\r
       Status = PeiServicesAllocatePool (\r
-                 (UINTN) InformationSize,\r
-                 (VOID **) &SecPlatformInformation2\r
+                 (UINTN)InformationSize,\r
+                 (VOID **)&SecPlatformInformation2\r
                  );\r
       if (Status == EFI_SUCCESS) {\r
         //\r
@@ -134,6 +134,7 @@ GetBistInfoFromPpi (
           if (BistInformationSize != NULL) {\r
             *BistInformationSize = InformationSize;\r
           }\r
+\r
           return EFI_SUCCESS;\r
         }\r
       }\r
@@ -154,7 +155,7 @@ GetBistInfoFromPpi (
 **/\r
 VOID\r
 CollectBistDataFromPpi (\r
-  IN CONST EFI_PEI_SERVICES             **PeiServices\r
+  IN CONST EFI_PEI_SERVICES  **PeiServices\r
   )\r
 {\r
   EFI_STATUS                            Status;\r
@@ -174,14 +175,13 @@ CollectBistDataFromPpi (
   EFI_SEC_PLATFORM_INFORMATION_RECORD2  *PlatformInformationRecord2;\r
   EFI_SEC_PLATFORM_INFORMATION_CPU      *CpuInstanceInHob;\r
 \r
-\r
-  MpInitLibGetNumberOfProcessors(&NumberOfProcessors, &NumberOfEnabledProcessors);\r
+  MpInitLibGetNumberOfProcessors (&NumberOfProcessors, &NumberOfEnabledProcessors);\r
 \r
   BistInformationSize = sizeof (EFI_SEC_PLATFORM_INFORMATION_RECORD2) +\r
                         sizeof (EFI_SEC_PLATFORM_INFORMATION_CPU) * NumberOfProcessors;\r
   Status = PeiServicesAllocatePool (\r
-             (UINTN) BistInformationSize,\r
-             (VOID **) &PlatformInformationRecord2\r
+             (UINTN)BistInformationSize,\r
+             (VOID **)&PlatformInformationRecord2\r
              );\r
   ASSERT_EFI_ERROR (Status);\r
   PlatformInformationRecord2->NumberOfCpus = (UINT32)NumberOfProcessors;\r
@@ -197,7 +197,7 @@ CollectBistDataFromPpi (
              PeiServices,\r
              &gEfiSecPlatformInformation2PpiGuid,\r
              &SecInformationDescriptor,\r
-             (VOID *) &SecPlatformInformation2,\r
+             (VOID *)&SecPlatformInformation2,\r
              NULL\r
              );\r
   if (Status == EFI_SUCCESS) {\r
@@ -214,7 +214,7 @@ CollectBistDataFromPpi (
                PeiServices,\r
                &gEfiSecPlatformInformationPpiGuid,\r
                &SecInformationDescriptor,\r
-               (VOID *) &SecPlatformInformation,\r
+               (VOID *)&SecPlatformInformation,\r
                NULL\r
                );\r
     if (Status == EFI_SUCCESS) {\r
@@ -223,16 +223,17 @@ CollectBistDataFromPpi (
       // SEC Platform Information only includes BSP's BIST information\r
       // and does not have BSP's APIC ID\r
       //\r
-      BspCpuInstance.CpuLocation = GetInitialApicId ();\r
-      BspCpuInstance.InfoRecord.IA32HealthFlags.Uint32  = SecPlatformInformation->IA32HealthFlags.Uint32;\r
-      CpuInstance = &BspCpuInstance;\r
+      BspCpuInstance.CpuLocation                       = GetInitialApicId ();\r
+      BspCpuInstance.InfoRecord.IA32HealthFlags.Uint32 = SecPlatformInformation->IA32HealthFlags.Uint32;\r
+      CpuInstance                                      = &BspCpuInstance;\r
     } else {\r
       DEBUG ((DEBUG_INFO, "Does not find any stored CPU BIST information from PPI!\n"));\r
     }\r
   }\r
-  for (ProcessorNumber = 0; ProcessorNumber < NumberOfProcessors; ProcessorNumber ++) {\r
+\r
+  for (ProcessorNumber = 0; ProcessorNumber < NumberOfProcessors; ProcessorNumber++) {\r
     MpInitLibGetProcessorInfo (ProcessorNumber, &ProcessorInfo, &BistData);\r
-    for (CpuIndex = 0; CpuIndex < NumberOfData; CpuIndex ++) {\r
+    for (CpuIndex = 0; CpuIndex < NumberOfData; CpuIndex++) {\r
       ASSERT (CpuInstance != NULL);\r
       if (ProcessorInfo.ProcessorId == CpuInstance[CpuIndex].CpuLocation) {\r
         //\r
@@ -241,6 +242,7 @@ CollectBistDataFromPpi (
         BistData = CpuInstance[CpuIndex].InfoRecord.IA32HealthFlags;\r
       }\r
     }\r
+\r
     if (BistData.Uint32 != 0) {\r
       //\r
       // Report Status Code that self test is failed\r
@@ -250,12 +252,15 @@ CollectBistDataFromPpi (
         (EFI_COMPUTING_UNIT_HOST_PROCESSOR | EFI_CU_HP_EC_SELF_TEST)\r
         );\r
     }\r
-    DEBUG ((DEBUG_INFO, "  APICID - 0x%08x, BIST - 0x%08x\n",\r
-            (UINT32) ProcessorInfo.ProcessorId,\r
-            BistData\r
-            ));\r
-    CpuInstanceInHob = PlatformInformationRecord2->CpuInstance;\r
-    CpuInstanceInHob[ProcessorNumber].CpuLocation = (UINT32) ProcessorInfo.ProcessorId;\r
+\r
+    DEBUG ((\r
+      DEBUG_INFO,\r
+      "  APICID - 0x%08x, BIST - 0x%08x\n",\r
+      (UINT32)ProcessorInfo.ProcessorId,\r
+      BistData\r
+      ));\r
+    CpuInstanceInHob                                             = PlatformInformationRecord2->CpuInstance;\r
+    CpuInstanceInHob[ProcessorNumber].CpuLocation                = (UINT32)ProcessorInfo.ProcessorId;\r
     CpuInstanceInHob[ProcessorNumber].InfoRecord.IA32HealthFlags = BistData;\r
   }\r
 \r
@@ -266,7 +271,7 @@ CollectBistDataFromPpi (
   BuildGuidDataHob (\r
     &gEfiSecPlatformInformation2PpiGuid,\r
     PlatformInformationRecord2,\r
-    (UINTN) BistInformationSize\r
+    (UINTN)BistInformationSize\r
     );\r
 \r
   if (SecPlatformInformation2 != NULL) {\r
@@ -285,6 +290,6 @@ CollectBistDataFromPpi (
     // Install SecPlatformInformation2 PPI\r
     //\r
     Status = PeiServicesInstallPpi (&mPeiSecPlatformInformation2Ppi);\r
-    ASSERT_EFI_ERROR(Status);\r
+    ASSERT_EFI_ERROR (Status);\r
   }\r
 }\r

diff --git a/UefiCpuPkg/CpuMpPei/CpuMp2Pei.c b/UefiCpuPkg/CpuMpPei/CpuMp2Pei.c
index c1116a5b7736c07d8da1a71a34e552f6e0d9d4bd..9c55eadb18828ef7c6f5042b0c5411494c411e97 100644 (file)
--- a/UefiCpuPkg/CpuMpPei/CpuMp2Pei.c
+++ b/UefiCpuPkg/CpuMpPei/CpuMp2Pei.c
@@ -43,9 +43,9 @@
 EFI_STATUS\r
 EFIAPI\r
 EdkiiPeiGetNumberOfProcessors (\r
-  IN  EDKII_PEI_MP_SERVICES2_PPI   *This,\r
-  OUT UINTN                     *NumberOfProcessors,\r
-  OUT UINTN                     *NumberOfEnabledProcessors\r
+  IN  EDKII_PEI_MP_SERVICES2_PPI  *This,\r
+  OUT UINTN                       *NumberOfProcessors,\r
+  OUT UINTN                       *NumberOfEnabledProcessors\r
   )\r
 {\r
   if ((NumberOfProcessors == NULL) || (NumberOfEnabledProcessors == NULL)) {\r
@@ -85,9 +85,9 @@ EdkiiPeiGetNumberOfProcessors (
 EFI_STATUS\r
 EFIAPI\r
 EdkiiPeiGetProcessorInfo (\r
-  IN  EDKII_PEI_MP_SERVICES2_PPI    *This,\r
-  IN  UINTN                         ProcessorNumber,\r
-  OUT EFI_PROCESSOR_INFORMATION     *ProcessorInfoBuffer\r
+  IN  EDKII_PEI_MP_SERVICES2_PPI  *This,\r
+  IN  UINTN                       ProcessorNumber,\r
+  OUT EFI_PROCESSOR_INFORMATION   *ProcessorInfoBuffer\r
   )\r
 {\r
   return MpInitLibGetProcessorInfo (ProcessorNumber, ProcessorInfoBuffer, NULL);\r
@@ -157,11 +157,11 @@ EdkiiPeiGetProcessorInfo (
 EFI_STATUS\r
 EFIAPI\r
 EdkiiPeiStartupAllAPs (\r
-  IN  EDKII_PEI_MP_SERVICES2_PPI   *This,\r
-  IN  EFI_AP_PROCEDURE             Procedure,\r
-  IN  BOOLEAN                      SingleThread,\r
-  IN  UINTN                        TimeoutInMicroSeconds,\r
-  IN  VOID                         *ProcedureArgument      OPTIONAL\r
+  IN  EDKII_PEI_MP_SERVICES2_PPI  *This,\r
+  IN  EFI_AP_PROCEDURE            Procedure,\r
+  IN  BOOLEAN                     SingleThread,\r
+  IN  UINTN                       TimeoutInMicroSeconds,\r
+  IN  VOID                        *ProcedureArgument      OPTIONAL\r
   )\r
 {\r
   return MpInitLibStartupAllAPs (\r
@@ -221,11 +221,11 @@ EdkiiPeiStartupAllAPs (
 EFI_STATUS\r
 EFIAPI\r
 EdkiiPeiStartupThisAP (\r
-  IN  EDKII_PEI_MP_SERVICES2_PPI   *This,\r
-  IN  EFI_AP_PROCEDURE             Procedure,\r
-  IN  UINTN                        ProcessorNumber,\r
-  IN  UINTN                        TimeoutInMicroseconds,\r
-  IN  VOID                         *ProcedureArgument      OPTIONAL\r
+  IN  EDKII_PEI_MP_SERVICES2_PPI  *This,\r
+  IN  EFI_AP_PROCEDURE            Procedure,\r
+  IN  UINTN                       ProcessorNumber,\r
+  IN  UINTN                       TimeoutInMicroseconds,\r
+  IN  VOID                        *ProcedureArgument      OPTIONAL\r
   )\r
 {\r
   return MpInitLibStartupThisAP (\r
@@ -321,10 +321,10 @@ EdkiiPeiSwitchBSP (
 EFI_STATUS\r
 EFIAPI\r
 EdkiiPeiEnableDisableAP (\r
-  IN  EDKII_PEI_MP_SERVICES2_PPI   *This,\r
-  IN  UINTN                        ProcessorNumber,\r
-  IN  BOOLEAN                      EnableAP,\r
-  IN  UINT32                       *HealthFlag OPTIONAL\r
+  IN  EDKII_PEI_MP_SERVICES2_PPI  *This,\r
+  IN  UINTN                       ProcessorNumber,\r
+  IN  BOOLEAN                     EnableAP,\r
+  IN  UINT32                      *HealthFlag OPTIONAL\r
   )\r
 {\r
   return MpInitLibEnableDisableAP (ProcessorNumber, EnableAP, HealthFlag);\r
@@ -388,10 +388,10 @@ EdkiiPeiWhoAmI (
 EFI_STATUS\r
 EFIAPI\r
 EdkiiPeiStartupAllCPUs (\r
-  IN  EDKII_PEI_MP_SERVICES2_PPI   *This,\r
-  IN  EFI_AP_PROCEDURE             Procedure,\r
-  IN  UINTN                        TimeoutInMicroSeconds,\r
-  IN  VOID                         *ProcedureArgument      OPTIONAL\r
+  IN  EDKII_PEI_MP_SERVICES2_PPI  *This,\r
+  IN  EFI_AP_PROCEDURE            Procedure,\r
+  IN  UINTN                       TimeoutInMicroSeconds,\r
+  IN  VOID                        *ProcedureArgument      OPTIONAL\r
   )\r
 {\r
   return MpInitLibStartupAllCPUs (\r
@@ -404,7 +404,7 @@ EdkiiPeiStartupAllCPUs (
 //\r
 // CPU MP2 PPI to be installed\r
 //\r
-EDKII_PEI_MP_SERVICES2_PPI            mMpServices2Ppi = {\r
+EDKII_PEI_MP_SERVICES2_PPI  mMpServices2Ppi = {\r
   EdkiiPeiGetNumberOfProcessors,\r
   EdkiiPeiGetProcessorInfo,\r
   EdkiiPeiStartupAllAPs,\r
@@ -414,4 +414,3 @@ EDKII_PEI_MP_SERVICES2_PPI            mMpServices2Ppi = {
   EdkiiPeiWhoAmI,\r
   EdkiiPeiStartupAllCPUs\r
 };\r
-\r

diff --git a/UefiCpuPkg/CpuMpPei/CpuMpPei.c b/UefiCpuPkg/CpuMpPei/CpuMpPei.c
index 3c1bad64701d43c601936b37c6b0556fd959c87f..1e68c91d95f31c579d5d5e86d58259cf70077599 100644 (file)
--- a/UefiCpuPkg/CpuMpPei/CpuMpPei.c
+++ b/UefiCpuPkg/CpuMpPei/CpuMpPei.c
@@ -8,12 +8,12 @@
 \r
 #include "CpuMpPei.h"\r
 \r
-extern EDKII_PEI_MP_SERVICES2_PPI            mMpServices2Ppi;\r
+extern EDKII_PEI_MP_SERVICES2_PPI  mMpServices2Ppi;\r
 \r
 //\r
 // CPU MP PPI to be installed\r
 //\r
-EFI_PEI_MP_SERVICES_PPI                mMpServicesPpi = {\r
+EFI_PEI_MP_SERVICES_PPI  mMpServicesPpi = {\r
   PeiGetNumberOfProcessors,\r
   PeiGetProcessorInfo,\r
   PeiStartupAllAPs,\r
@@ -23,7 +23,7 @@ EFI_PEI_MP_SERVICES_PPI                mMpServicesPpi = {
   PeiWhoAmI,\r
 };\r
 \r
-EFI_PEI_PPI_DESCRIPTOR           mPeiCpuMpPpiList[] = {\r
+EFI_PEI_PPI_DESCRIPTOR  mPeiCpuMpPpiList[] = {\r
   {\r
     EFI_PEI_PPI_DESCRIPTOR_PPI,\r
     &gEdkiiPeiMpServices2PpiGuid,\r
@@ -73,10 +73,10 @@ EFI_PEI_PPI_DESCRIPTOR           mPeiCpuMpPpiList[] = {
 EFI_STATUS\r
 EFIAPI\r
 PeiGetNumberOfProcessors (\r
-  IN  CONST EFI_PEI_SERVICES    **PeiServices,\r
-  IN  EFI_PEI_MP_SERVICES_PPI   *This,\r
-  OUT UINTN                     *NumberOfProcessors,\r
-  OUT UINTN                     *NumberOfEnabledProcessors\r
+  IN  CONST EFI_PEI_SERVICES   **PeiServices,\r
+  IN  EFI_PEI_MP_SERVICES_PPI  *This,\r
+  OUT UINTN                    *NumberOfProcessors,\r
+  OUT UINTN                    *NumberOfEnabledProcessors\r
   )\r
 {\r
   if ((NumberOfProcessors == NULL) || (NumberOfEnabledProcessors == NULL)) {\r
@@ -193,12 +193,12 @@ PeiGetProcessorInfo (
 EFI_STATUS\r
 EFIAPI\r
 PeiStartupAllAPs (\r
-  IN  CONST EFI_PEI_SERVICES    **PeiServices,\r
-  IN  EFI_PEI_MP_SERVICES_PPI   *This,\r
-  IN  EFI_AP_PROCEDURE          Procedure,\r
-  IN  BOOLEAN                   SingleThread,\r
-  IN  UINTN                     TimeoutInMicroSeconds,\r
-  IN  VOID                      *ProcedureArgument      OPTIONAL\r
+  IN  CONST EFI_PEI_SERVICES   **PeiServices,\r
+  IN  EFI_PEI_MP_SERVICES_PPI  *This,\r
+  IN  EFI_AP_PROCEDURE         Procedure,\r
+  IN  BOOLEAN                  SingleThread,\r
+  IN  UINTN                    TimeoutInMicroSeconds,\r
+  IN  VOID                     *ProcedureArgument      OPTIONAL\r
   )\r
 {\r
   return MpInitLibStartupAllAPs (\r
@@ -260,12 +260,12 @@ PeiStartupAllAPs (
 EFI_STATUS\r
 EFIAPI\r
 PeiStartupThisAP (\r
-  IN  CONST EFI_PEI_SERVICES    **PeiServices,\r
-  IN  EFI_PEI_MP_SERVICES_PPI   *This,\r
-  IN  EFI_AP_PROCEDURE          Procedure,\r
-  IN  UINTN                     ProcessorNumber,\r
-  IN  UINTN                     TimeoutInMicroseconds,\r
-  IN  VOID                      *ProcedureArgument      OPTIONAL\r
+  IN  CONST EFI_PEI_SERVICES   **PeiServices,\r
+  IN  EFI_PEI_MP_SERVICES_PPI  *This,\r
+  IN  EFI_AP_PROCEDURE         Procedure,\r
+  IN  UINTN                    ProcessorNumber,\r
+  IN  UINTN                    TimeoutInMicroseconds,\r
+  IN  VOID                     *ProcedureArgument      OPTIONAL\r
   )\r
 {\r
   return MpInitLibStartupThisAP (\r
@@ -366,11 +366,11 @@ PeiSwitchBSP (
 EFI_STATUS\r
 EFIAPI\r
 PeiEnableDisableAP (\r
-  IN  CONST EFI_PEI_SERVICES    **PeiServices,\r
-  IN  EFI_PEI_MP_SERVICES_PPI   *This,\r
-  IN  UINTN                     ProcessorNumber,\r
-  IN  BOOLEAN                   EnableAP,\r
-  IN  UINT32                    *HealthFlag OPTIONAL\r
+  IN  CONST EFI_PEI_SERVICES   **PeiServices,\r
+  IN  EFI_PEI_MP_SERVICES_PPI  *This,\r
+  IN  UINTN                    ProcessorNumber,\r
+  IN  BOOLEAN                  EnableAP,\r
+  IN  UINT32                   *HealthFlag OPTIONAL\r
   )\r
 {\r
   return MpInitLibEnableDisableAP (ProcessorNumber, EnableAP, HealthFlag);\r
@@ -423,7 +423,7 @@ PeiWhoAmI (
 VOID\r
 EFIAPI\r
 GetGdtr (\r
-  IN OUT VOID *Buffer\r
+  IN OUT VOID  *Buffer\r
   )\r
 {\r
   AsmReadGdtr ((IA32_DESCRIPTOR *)Buffer);\r
@@ -441,12 +441,12 @@ GetGdtr (
 VOID\r
 EFIAPI\r
 InitializeExceptionStackSwitchHandlers (\r
-  IN OUT VOID *Buffer\r
+  IN OUT VOID  *Buffer\r
   )\r
 {\r
-  CPU_EXCEPTION_INIT_DATA           *EssData;\r
-  IA32_DESCRIPTOR                   Idtr;\r
-  EFI_STATUS                        Status;\r
+  CPU_EXCEPTION_INIT_DATA  *EssData;\r
+  IA32_DESCRIPTOR          Idtr;\r
+  EFI_STATUS               Status;\r
 \r
   EssData = Buffer;\r
   //\r
@@ -454,9 +454,9 @@ InitializeExceptionStackSwitchHandlers (
   // the AP's IDT is the same as BSP's IDT either.\r
   //\r
   AsmReadIdtr (&Idtr);\r
-  EssData->Ia32.IdtTable = (VOID *)Idtr.Base;\r
+  EssData->Ia32.IdtTable     = (VOID *)Idtr.Base;\r
   EssData->Ia32.IdtTableSize = Idtr.Limit + 1;\r
-  Status = InitializeCpuExceptionHandlersEx (NULL, EssData);\r
+  Status                     = InitializeCpuExceptionHandlersEx (NULL, EssData);\r
   ASSERT_EFI_ERROR (Status);\r
 }\r
 \r
@@ -472,58 +472,59 @@ InitializeMpExceptionStackSwitchHandlers (
   VOID\r
   )\r
 {\r
-  EFI_STATUS                      Status;\r
-  UINTN                           Index;\r
-  UINTN                           Bsp;\r
-  UINTN                           ExceptionNumber;\r
-  UINTN                           OldGdtSize;\r
-  UINTN                           NewGdtSize;\r
-  UINTN                           NewStackSize;\r
-  IA32_DESCRIPTOR                 Gdtr;\r
-  CPU_EXCEPTION_INIT_DATA         EssData;\r
-  UINT8                           *GdtBuffer;\r
-  UINT8                           *StackTop;\r
-  UINTN                           NumberOfProcessors;\r
+  EFI_STATUS               Status;\r
+  UINTN                    Index;\r
+  UINTN                    Bsp;\r
+  UINTN                    ExceptionNumber;\r
+  UINTN                    OldGdtSize;\r
+  UINTN                    NewGdtSize;\r
+  UINTN                    NewStackSize;\r
+  IA32_DESCRIPTOR          Gdtr;\r
+  CPU_EXCEPTION_INIT_DATA  EssData;\r
+  UINT8                    *GdtBuffer;\r
+  UINT8                    *StackTop;\r
+  UINTN                    NumberOfProcessors;\r
 \r
   if (!PcdGetBool (PcdCpuStackGuard)) {\r
     return;\r
   }\r
 \r
-  MpInitLibGetNumberOfProcessors(&NumberOfProcessors, NULL);\r
+  MpInitLibGetNumberOfProcessors (&NumberOfProcessors, NULL);\r
   MpInitLibWhoAmI (&Bsp);\r
 \r
   ExceptionNumber = FixedPcdGetSize (PcdCpuStackSwitchExceptionList);\r
-  NewStackSize = FixedPcdGet32 (PcdCpuKnownGoodStackSize) * ExceptionNumber;\r
+  NewStackSize    = FixedPcdGet32 (PcdCpuKnownGoodStackSize) * ExceptionNumber;\r
 \r
   StackTop = AllocatePages (EFI_SIZE_TO_PAGES (NewStackSize * NumberOfProcessors));\r
-  ASSERT(StackTop != NULL);\r
+  ASSERT (StackTop != NULL);\r
   if (StackTop == NULL) {\r
     return;\r
   }\r
+\r
   StackTop += NewStackSize  * NumberOfProcessors;\r
 \r
   //\r
   // The default exception handlers must have been initialized. Let's just skip\r
   // it in this method.\r
   //\r
-  EssData.Ia32.Revision = CPU_EXCEPTION_INIT_DATA_REV;\r
+  EssData.Ia32.Revision            = CPU_EXCEPTION_INIT_DATA_REV;\r
   EssData.Ia32.InitDefaultHandlers = FALSE;\r
 \r
-  EssData.Ia32.StackSwitchExceptions = FixedPcdGetPtr(PcdCpuStackSwitchExceptionList);\r
+  EssData.Ia32.StackSwitchExceptions      = FixedPcdGetPtr (PcdCpuStackSwitchExceptionList);\r
   EssData.Ia32.StackSwitchExceptionNumber = ExceptionNumber;\r
-  EssData.Ia32.KnownGoodStackSize = FixedPcdGet32(PcdCpuKnownGoodStackSize);\r
+  EssData.Ia32.KnownGoodStackSize         = FixedPcdGet32 (PcdCpuKnownGoodStackSize);\r
 \r
   //\r
   // Initialize Gdtr to suppress incorrect compiler/analyzer warnings.\r
   //\r
-  Gdtr.Base = 0;\r
+  Gdtr.Base  = 0;\r
   Gdtr.Limit = 0;\r
   for (Index = 0; Index < NumberOfProcessors; ++Index) {\r
     //\r
     // To support stack switch, we need to re-construct GDT but not IDT.\r
     //\r
     if (Index == Bsp) {\r
-      GetGdtr(&Gdtr);\r
+      GetGdtr (&Gdtr);\r
     } else {\r
       //\r
       // AP might have different size of GDT from BSP.\r
@@ -560,7 +561,7 @@ InitializeMpExceptionStackSwitchHandlers (
     //    |                              |\r
     //    --------------------------------\r
     //\r
-    OldGdtSize = Gdtr.Limit + 1;\r
+    OldGdtSize                        = Gdtr.Limit + 1;\r
     EssData.Ia32.ExceptionTssDescSize = sizeof (IA32_TSS_DESCRIPTOR) *\r
                                         (ExceptionNumber + 1);\r
     EssData.Ia32.ExceptionTssSize = sizeof (IA32_TASK_STATE_SEGMENT) *\r
@@ -583,19 +584,21 @@ InitializeMpExceptionStackSwitchHandlers (
     //\r
     // Make sure GDT table alignment\r
     //\r
-    EssData.Ia32.GdtTable = ALIGN_POINTER(GdtBuffer, sizeof (IA32_TSS_DESCRIPTOR));\r
-    NewGdtSize -= ((UINT8 *)EssData.Ia32.GdtTable - GdtBuffer);\r
+    EssData.Ia32.GdtTable     = ALIGN_POINTER (GdtBuffer, sizeof (IA32_TSS_DESCRIPTOR));\r
+    NewGdtSize               -= ((UINT8 *)EssData.Ia32.GdtTable - GdtBuffer);\r
     EssData.Ia32.GdtTableSize = NewGdtSize;\r
 \r
     EssData.Ia32.ExceptionTssDesc = ((UINT8 *)EssData.Ia32.GdtTable + OldGdtSize);\r
-    EssData.Ia32.ExceptionTss = ((UINT8 *)EssData.Ia32.GdtTable + OldGdtSize +\r
-                                 EssData.Ia32.ExceptionTssDescSize);\r
+    EssData.Ia32.ExceptionTss     = ((UINT8 *)EssData.Ia32.GdtTable + OldGdtSize +\r
+                                     EssData.Ia32.ExceptionTssDescSize);\r
 \r
     EssData.Ia32.KnownGoodStackTop = (UINTN)StackTop;\r
-    DEBUG ((DEBUG_INFO,\r
-            "Exception stack top[cpu%lu]: 0x%lX\n",\r
-            (UINT64)(UINTN)Index,\r
-            (UINT64)(UINTN)StackTop));\r
+    DEBUG ((\r
+      DEBUG_INFO,\r
+      "Exception stack top[cpu%lu]: 0x%lX\n",\r
+      (UINT64)(UINTN)Index,\r
+      (UINT64)(UINTN)StackTop\r
+      ));\r
 \r
     if (Index == Bsp) {\r
       InitializeExceptionStackSwitchHandlers (&EssData);\r
@@ -610,7 +613,7 @@ InitializeMpExceptionStackSwitchHandlers (
         );\r
     }\r
 \r
-    StackTop  -= NewStackSize;\r
+    StackTop -= NewStackSize;\r
   }\r
 }\r
 \r
@@ -625,23 +628,23 @@ InitializeMpExceptionStackSwitchHandlers (
 **/\r
 EFI_STATUS\r
 InitializeCpuMpWorker (\r
-  IN CONST EFI_PEI_SERVICES     **PeiServices\r
+  IN CONST EFI_PEI_SERVICES  **PeiServices\r
   )\r
 {\r
-  EFI_STATUS                      Status;\r
-  EFI_VECTOR_HANDOFF_INFO         *VectorInfo;\r
-  EFI_PEI_VECTOR_HANDOFF_INFO_PPI *VectorHandoffInfoPpi;\r
+  EFI_STATUS                       Status;\r
+  EFI_VECTOR_HANDOFF_INFO          *VectorInfo;\r
+  EFI_PEI_VECTOR_HANDOFF_INFO_PPI  *VectorHandoffInfoPpi;\r
 \r
   //\r
   // Get Vector Hand-off Info PPI\r
   //\r
   VectorInfo = NULL;\r
-  Status = PeiServicesLocatePpi (\r
-             &gEfiVectorHandoffInfoPpiGuid,\r
-             0,\r
-             NULL,\r
-             (VOID **)&VectorHandoffInfoPpi\r
-             );\r
+  Status     = PeiServicesLocatePpi (\r
+                 &gEfiVectorHandoffInfoPpiGuid,\r
+                 0,\r
+                 NULL,\r
+                 (VOID **)&VectorHandoffInfoPpi\r
+                 );\r
   if (Status == EFI_SUCCESS) {\r
     VectorInfo = VectorHandoffInfoPpi->Info;\r
   }\r
@@ -672,7 +675,7 @@ InitializeCpuMpWorker (
   //\r
   // Install CPU MP PPI\r
   //\r
-  Status = PeiServicesInstallPpi(mPeiCpuMpPpiList);\r
+  Status = PeiServicesInstallPpi (mPeiCpuMpPpiList);\r
   ASSERT_EFI_ERROR (Status);\r
 \r
   return Status;\r
@@ -697,7 +700,7 @@ CpuMpPeimInit (
   IN CONST EFI_PEI_SERVICES     **PeiServices\r
   )\r
 {\r
-  EFI_STATUS           Status;\r
+  EFI_STATUS  Status;\r
 \r
   //\r
   // For the sake of special initialization needing to be done right after\r

diff --git a/UefiCpuPkg/CpuMpPei/CpuMpPei.h b/UefiCpuPkg/CpuMpPei/CpuMpPei.h
index c6870656ca645117b29478c82b9de76fab23c9d1..0649c48d14f099b9f76800e3df6956c07788fe96 100644 (file)
--- a/UefiCpuPkg/CpuMpPei/CpuMpPei.h
+++ b/UefiCpuPkg/CpuMpPei/CpuMpPei.h
@@ -29,7 +29,7 @@
 #include <Library/BaseMemoryLib.h>\r
 #include <Library/MemoryAllocationLib.h>\r
 \r
-extern EFI_PEI_PPI_DESCRIPTOR   mPeiCpuMpPpiDesc;\r
+extern EFI_PEI_PPI_DESCRIPTOR  mPeiCpuMpPpiDesc;\r
 \r
 /**\r
   This service retrieves the number of logical processor in the platform\r
@@ -68,10 +68,10 @@ extern EFI_PEI_PPI_DESCRIPTOR   mPeiCpuMpPpiDesc;
 EFI_STATUS\r
 EFIAPI\r
 PeiGetNumberOfProcessors (\r
-  IN  CONST EFI_PEI_SERVICES    **PeiServices,\r
-  IN  EFI_PEI_MP_SERVICES_PPI   *This,\r
-  OUT UINTN                     *NumberOfProcessors,\r
-  OUT UINTN                     *NumberOfEnabledProcessors\r
+  IN  CONST EFI_PEI_SERVICES   **PeiServices,\r
+  IN  EFI_PEI_MP_SERVICES_PPI  *This,\r
+  OUT UINTN                    *NumberOfProcessors,\r
+  OUT UINTN                    *NumberOfEnabledProcessors\r
   );\r
 \r
 /**\r
@@ -175,12 +175,12 @@ PeiGetProcessorInfo (
 EFI_STATUS\r
 EFIAPI\r
 PeiStartupAllAPs (\r
-  IN  CONST EFI_PEI_SERVICES    **PeiServices,\r
-  IN  EFI_PEI_MP_SERVICES_PPI   *This,\r
-  IN  EFI_AP_PROCEDURE          Procedure,\r
-  IN  BOOLEAN                   SingleThread,\r
-  IN  UINTN                     TimeoutInMicroSeconds,\r
-  IN  VOID                      *ProcedureArgument      OPTIONAL\r
+  IN  CONST EFI_PEI_SERVICES   **PeiServices,\r
+  IN  EFI_PEI_MP_SERVICES_PPI  *This,\r
+  IN  EFI_AP_PROCEDURE         Procedure,\r
+  IN  BOOLEAN                  SingleThread,\r
+  IN  UINTN                    TimeoutInMicroSeconds,\r
+  IN  VOID                     *ProcedureArgument      OPTIONAL\r
   );\r
 \r
 /**\r
@@ -232,12 +232,12 @@ PeiStartupAllAPs (
 EFI_STATUS\r
 EFIAPI\r
 PeiStartupThisAP (\r
-  IN  CONST EFI_PEI_SERVICES    **PeiServices,\r
-  IN  EFI_PEI_MP_SERVICES_PPI   *This,\r
-  IN  EFI_AP_PROCEDURE          Procedure,\r
-  IN  UINTN                     ProcessorNumber,\r
-  IN  UINTN                     TimeoutInMicroseconds,\r
-  IN  VOID                      *ProcedureArgument      OPTIONAL\r
+  IN  CONST EFI_PEI_SERVICES   **PeiServices,\r
+  IN  EFI_PEI_MP_SERVICES_PPI  *This,\r
+  IN  EFI_AP_PROCEDURE         Procedure,\r
+  IN  UINTN                    ProcessorNumber,\r
+  IN  UINTN                    TimeoutInMicroseconds,\r
+  IN  VOID                     *ProcedureArgument      OPTIONAL\r
   );\r
 \r
 /**\r
@@ -325,11 +325,11 @@ PeiSwitchBSP (
 EFI_STATUS\r
 EFIAPI\r
 PeiEnableDisableAP (\r
-  IN  CONST EFI_PEI_SERVICES    **PeiServices,\r
-  IN  EFI_PEI_MP_SERVICES_PPI   *This,\r
-  IN  UINTN                     ProcessorNumber,\r
-  IN  BOOLEAN                   EnableAP,\r
-  IN  UINT32                    *HealthFlag OPTIONAL\r
+  IN  CONST EFI_PEI_SERVICES   **PeiServices,\r
+  IN  EFI_PEI_MP_SERVICES_PPI  *This,\r
+  IN  UINTN                    ProcessorNumber,\r
+  IN  BOOLEAN                  EnableAP,\r
+  IN  UINT32                   *HealthFlag OPTIONAL\r
   );\r
 \r
 /**\r
@@ -375,7 +375,7 @@ PeiWhoAmI (
 **/\r
 VOID\r
 CollectBistDataFromPpi (\r
-  IN CONST EFI_PEI_SERVICES             **PeiServices\r
+  IN CONST EFI_PEI_SERVICES  **PeiServices\r
   );\r
 \r
 /**\r
@@ -393,9 +393,9 @@ CollectBistDataFromPpi (
 EFI_STATUS\r
 EFIAPI\r
 SecPlatformInformation2 (\r
-  IN CONST EFI_PEI_SERVICES                   **PeiServices,\r
-  IN OUT UINT64                               *StructureSize,\r
-     OUT EFI_SEC_PLATFORM_INFORMATION_RECORD2 *PlatformInformationRecord2\r
+  IN CONST EFI_PEI_SERVICES                 **PeiServices,\r
+  IN OUT UINT64                             *StructureSize,\r
+  OUT EFI_SEC_PLATFORM_INFORMATION_RECORD2  *PlatformInformationRecord2\r
   );\r
 \r
 /**\r
@@ -421,7 +421,7 @@ MigrateGdt (
 **/\r
 EFI_STATUS\r
 InitializeCpuMpWorker (\r
-  IN CONST EFI_PEI_SERVICES     **PeiServices\r
+  IN CONST EFI_PEI_SERVICES  **PeiServices\r
   );\r
 \r
 /**\r

diff --git a/UefiCpuPkg/CpuMpPei/CpuPaging.c b/UefiCpuPkg/CpuMpPei/CpuPaging.c
index 3e261d6657b305619534b3c9fd3df77d54e583ab..1354222253400c80d4678a0a065697c8c923f9cf 100644 (file)
--- a/UefiCpuPkg/CpuMpPei/CpuPaging.c
+++ b/UefiCpuPkg/CpuMpPei/CpuPaging.c
@@ -16,23 +16,23 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
 \r
 #include "CpuMpPei.h"\r
 \r
-#define IA32_PG_P             BIT0\r
-#define IA32_PG_RW            BIT1\r
-#define IA32_PG_U             BIT2\r
-#define IA32_PG_A             BIT5\r
-#define IA32_PG_D             BIT6\r
-#define IA32_PG_PS            BIT7\r
-#define IA32_PG_NX            BIT63\r
-\r
-#define PAGE_ATTRIBUTE_BITS   (IA32_PG_RW | IA32_PG_P)\r
-#define PAGE_PROGATE_BITS     (IA32_PG_D | IA32_PG_A | IA32_PG_NX | IA32_PG_U |\\r
+#define IA32_PG_P   BIT0\r
+#define IA32_PG_RW  BIT1\r
+#define IA32_PG_U   BIT2\r
+#define IA32_PG_A   BIT5\r
+#define IA32_PG_D   BIT6\r
+#define IA32_PG_PS  BIT7\r
+#define IA32_PG_NX  BIT63\r
+\r
+#define PAGE_ATTRIBUTE_BITS  (IA32_PG_RW | IA32_PG_P)\r
+#define PAGE_PROGATE_BITS    (IA32_PG_D | IA32_PG_A | IA32_PG_NX | IA32_PG_U | \\r
                                PAGE_ATTRIBUTE_BITS)\r
 \r
-#define PAGING_PAE_INDEX_MASK       0x1FF\r
-#define PAGING_4K_ADDRESS_MASK_64   0x000FFFFFFFFFF000ull\r
-#define PAGING_2M_ADDRESS_MASK_64   0x000FFFFFFFE00000ull\r
-#define PAGING_1G_ADDRESS_MASK_64   0x000FFFFFC0000000ull\r
-#define PAGING_512G_ADDRESS_MASK_64 0x000FFF8000000000ull\r
+#define PAGING_PAE_INDEX_MASK        0x1FF\r
+#define PAGING_4K_ADDRESS_MASK_64    0x000FFFFFFFFFF000ull\r
+#define PAGING_2M_ADDRESS_MASK_64    0x000FFFFFFFE00000ull\r
+#define PAGING_1G_ADDRESS_MASK_64    0x000FFFFFC0000000ull\r
+#define PAGING_512G_ADDRESS_MASK_64  0x000FFF8000000000ull\r
 \r
 typedef enum {\r
   PageNone = 0,\r
@@ -45,19 +45,19 @@ typedef enum {
 } PAGE_ATTRIBUTE;\r
 \r
 typedef struct {\r
-  PAGE_ATTRIBUTE   Attribute;\r
-  UINT64           Length;\r
-  UINT64           AddressMask;\r
-  UINTN            AddressBitOffset;\r
-  UINTN            AddressBitLength;\r
+  PAGE_ATTRIBUTE    Attribute;\r
+  UINT64            Length;\r
+  UINT64            AddressMask;\r
+  UINTN             AddressBitOffset;\r
+  UINTN             AddressBitLength;\r
 } PAGE_ATTRIBUTE_TABLE;\r
 \r
-PAGE_ATTRIBUTE_TABLE mPageAttributeTable[] = {\r
-  {PageNone,          0,                           0,  0, 0},\r
-  {Page4K,     SIZE_4KB,   PAGING_4K_ADDRESS_MASK_64, 12, 9},\r
-  {Page2M,     SIZE_2MB,   PAGING_2M_ADDRESS_MASK_64, 21, 9},\r
-  {Page1G,     SIZE_1GB,   PAGING_1G_ADDRESS_MASK_64, 30, 9},\r
-  {Page512G, SIZE_512GB, PAGING_512G_ADDRESS_MASK_64, 39, 9},\r
+PAGE_ATTRIBUTE_TABLE  mPageAttributeTable[] = {\r
+  { PageNone, 0,          0,                           0,  0 },\r
+  { Page4K,   SIZE_4KB,   PAGING_4K_ADDRESS_MASK_64,   12, 9 },\r
+  { Page2M,   SIZE_2MB,   PAGING_2M_ADDRESS_MASK_64,   21, 9 },\r
+  { Page1G,   SIZE_1GB,   PAGING_1G_ADDRESS_MASK_64,   30, 9 },\r
+  { Page512G, SIZE_512GB, PAGING_512G_ADDRESS_MASK_64, 39, 9 },\r
 };\r
 \r
 EFI_PEI_NOTIFY_DESCRIPTOR  mPostMemNotifyList[] = {\r
@@ -80,8 +80,8 @@ IsIa32PaeSupported (
   VOID\r
   )\r
 {\r
-  UINT32                    RegEax;\r
-  CPUID_VERSION_INFO_EDX    RegEdx;\r
+  UINT32                  RegEax;\r
+  CPUID_VERSION_INFO_EDX  RegEdx;\r
 \r
   AsmCpuid (CPUID_SIGNATURE, &RegEax, NULL, NULL, NULL);\r
   if (RegEax >= CPUID_VERSION_INFO) {\r
@@ -104,14 +104,14 @@ IsIa32PaeSupported (
 **/\r
 VOID *\r
 AllocatePageTableMemory (\r
-  IN UINTN           Pages\r
+  IN UINTN  Pages\r
   )\r
 {\r
-  VOID      *Address;\r
+  VOID  *Address;\r
 \r
-  Address = AllocatePages(Pages);\r
+  Address = AllocatePages (Pages);\r
   if (Address != NULL) {\r
-    ZeroMem(Address, EFI_PAGES_TO_SIZE (Pages));\r
+    ZeroMem (Address, EFI_PAGES_TO_SIZE (Pages));\r
   }\r
 \r
   return Address;\r
@@ -129,13 +129,13 @@ GetPhysicalAddressWidth (
   VOID\r
   )\r
 {\r
-  UINT32          RegEax;\r
+  UINT32  RegEax;\r
 \r
-  if (sizeof(UINTN) == 4) {\r
+  if (sizeof (UINTN) == 4) {\r
     return 32;\r
   }\r
 \r
-  AsmCpuid(CPUID_EXTENDED_FUNCTION, &RegEax, NULL, NULL, NULL);\r
+  AsmCpuid (CPUID_EXTENDED_FUNCTION, &RegEax, NULL, NULL, NULL);\r
   if (RegEax >= CPUID_VIR_PHY_ADDRESS_SIZE) {\r
     AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, &RegEax, NULL, NULL, NULL);\r
     RegEax &= 0xFF;\r
@@ -161,7 +161,7 @@ GetPageTableTopLevelType (
   VOID\r
   )\r
 {\r
-  MSR_IA32_EFER_REGISTER      MsrEfer;\r
+  MSR_IA32_EFER_REGISTER  MsrEfer;\r
 \r
   MsrEfer.Uint64 = AsmReadMsr64 (MSR_CORE_IA32_EFER);\r
 \r
@@ -178,19 +178,19 @@ GetPageTableTopLevelType (
 **/\r
 VOID *\r
 GetPageTableEntry (\r
-  IN  PHYSICAL_ADDRESS                  Address,\r
-  OUT PAGE_ATTRIBUTE                    *PageAttribute\r
+  IN  PHYSICAL_ADDRESS  Address,\r
+  OUT PAGE_ATTRIBUTE    *PageAttribute\r
   )\r
 {\r
-  INTN                  Level;\r
-  UINTN                 Index;\r
-  UINT64                *PageTable;\r
-  UINT64                AddressEncMask;\r
+  INTN    Level;\r
+  UINTN   Index;\r
+  UINT64  *PageTable;\r
+  UINT64  AddressEncMask;\r
 \r
   AddressEncMask = PcdGet64 (PcdPteMemoryEncryptionAddressOrMask);\r
-  PageTable = (UINT64 *)(UINTN)(AsmReadCr3 () & PAGING_4K_ADDRESS_MASK_64);\r
+  PageTable      = (UINT64 *)(UINTN)(AsmReadCr3 () & PAGING_4K_ADDRESS_MASK_64);\r
   for (Level = (INTN)GetPageTableTopLevelType (); Level > 0; --Level) {\r
-    Index = (UINTN)RShiftU64 (Address, mPageAttributeTable[Level].AddressBitOffset);\r
+    Index  = (UINTN)RShiftU64 (Address, mPageAttributeTable[Level].AddressBitOffset);\r
     Index &= PAGING_PAE_INDEX_MASK;\r
 \r
     //\r
@@ -204,7 +204,7 @@ GetPageTableEntry (
     //\r
     // Page memory?\r
     //\r
-    if ((PageTable[Index] & IA32_PG_PS) != 0 || Level == PageMin) {\r
+    if (((PageTable[Index] & IA32_PG_PS) != 0) || (Level == PageMin)) {\r
       *PageAttribute = (PAGE_ATTRIBUTE)Level;\r
       return &PageTable[Index];\r
     }\r
@@ -235,19 +235,19 @@ GetPageTableEntry (
 **/\r
 RETURN_STATUS\r
 SplitPage (\r
-  IN  UINT64                            *PageEntry,\r
-  IN  PAGE_ATTRIBUTE                    PageAttribute,\r
-  IN  PAGE_ATTRIBUTE                    SplitAttribute,\r
-  IN  BOOLEAN                           Recursively\r
+  IN  UINT64          *PageEntry,\r
+  IN  PAGE_ATTRIBUTE  PageAttribute,\r
+  IN  PAGE_ATTRIBUTE  SplitAttribute,\r
+  IN  BOOLEAN         Recursively\r
   )\r
 {\r
-  UINT64            BaseAddress;\r
-  UINT64            *NewPageEntry;\r
-  UINTN             Index;\r
-  UINT64            AddressEncMask;\r
-  PAGE_ATTRIBUTE    SplitTo;\r
+  UINT64          BaseAddress;\r
+  UINT64          *NewPageEntry;\r
+  UINTN           Index;\r
+  UINT64          AddressEncMask;\r
+  PAGE_ATTRIBUTE  SplitTo;\r
 \r
-  if (SplitAttribute == PageNone || SplitAttribute >= PageAttribute) {\r
+  if ((SplitAttribute == PageNone) || (SplitAttribute >= PageAttribute)) {\r
     ASSERT (SplitAttribute != PageNone);\r
     ASSERT (SplitAttribute < PageAttribute);\r
     return RETURN_INVALID_PARAMETER;\r
@@ -262,13 +262,13 @@ SplitPage (
   //\r
   // One level down each step to achieve more compact page table.\r
   //\r
-  SplitTo = PageAttribute - 1;\r
+  SplitTo        = PageAttribute - 1;\r
   AddressEncMask = PcdGet64 (PcdPteMemoryEncryptionAddressOrMask) &\r
                    mPageAttributeTable[SplitTo].AddressMask;\r
-  BaseAddress    = *PageEntry &\r
-                   ~PcdGet64 (PcdPteMemoryEncryptionAddressOrMask) &\r
-                   mPageAttributeTable[PageAttribute].AddressMask;\r
-  for (Index = 0; Index < SIZE_4KB / sizeof(UINT64); Index++) {\r
+  BaseAddress = *PageEntry &\r
+                ~PcdGet64 (PcdPteMemoryEncryptionAddressOrMask) &\r
+                mPageAttributeTable[PageAttribute].AddressMask;\r
+  for (Index = 0; Index < SIZE_4KB / sizeof (UINT64); Index++) {\r
     NewPageEntry[Index] = BaseAddress | AddressEncMask |\r
                           ((*PageEntry) & PAGE_PROGATE_BITS);\r
 \r
@@ -276,7 +276,7 @@ SplitPage (
       NewPageEntry[Index] |= IA32_PG_PS;\r
     }\r
 \r
-    if (Recursively && SplitTo > SplitAttribute) {\r
+    if (Recursively && (SplitTo > SplitAttribute)) {\r
       SplitPage (&NewPageEntry[Index], SplitTo, SplitAttribute, Recursively);\r
     }\r
 \r
@@ -313,20 +313,20 @@ SplitPage (
 RETURN_STATUS\r
 EFIAPI\r
 ConvertMemoryPageAttributes (\r
-  IN  PHYSICAL_ADDRESS                  BaseAddress,\r
-  IN  UINT64                            Length,\r
-  IN  UINT64                            Attributes\r
+  IN  PHYSICAL_ADDRESS  BaseAddress,\r
+  IN  UINT64            Length,\r
+  IN  UINT64            Attributes\r
   )\r
 {\r
-  UINT64                            *PageEntry;\r
-  PAGE_ATTRIBUTE                    PageAttribute;\r
-  RETURN_STATUS                     Status;\r
-  EFI_PHYSICAL_ADDRESS              MaximumAddress;\r
-\r
-  if (Length == 0 ||\r
-      (BaseAddress & (SIZE_4KB - 1)) != 0 ||\r
-      (Length & (SIZE_4KB - 1)) != 0) {\r
-\r
+  UINT64                *PageEntry;\r
+  PAGE_ATTRIBUTE        PageAttribute;\r
+  RETURN_STATUS         Status;\r
+  EFI_PHYSICAL_ADDRESS  MaximumAddress;\r
+\r
+  if ((Length == 0) ||\r
+      ((BaseAddress & (SIZE_4KB - 1)) != 0) ||\r
+      ((Length & (SIZE_4KB - 1)) != 0))\r
+  {\r
     ASSERT (Length > 0);\r
     ASSERT ((BaseAddress & (SIZE_4KB - 1)) == 0);\r
     ASSERT ((Length & (SIZE_4KB - 1)) == 0);\r
@@ -335,9 +335,10 @@ ConvertMemoryPageAttributes (
   }\r
 \r
   MaximumAddress = (EFI_PHYSICAL_ADDRESS)MAX_UINT32;\r
-  if (BaseAddress > MaximumAddress ||\r
-      Length > MaximumAddress ||\r
-      (BaseAddress > MaximumAddress - (Length - 1))) {\r
+  if ((BaseAddress > MaximumAddress) ||\r
+      (Length > MaximumAddress) ||\r
+      (BaseAddress > MaximumAddress - (Length - 1)))\r
+  {\r
     return RETURN_UNSUPPORTED;\r
   }\r
 \r
@@ -355,6 +356,7 @@ ConvertMemoryPageAttributes (
       if (RETURN_ERROR (Status)) {\r
         return Status;\r
       }\r
+\r
       //\r
       // Do it again until the page is 4K.\r
       //\r
@@ -374,7 +376,7 @@ ConvertMemoryPageAttributes (
     // Convert success, move to next\r
     //\r
     BaseAddress += SIZE_4KB;\r
-    Length -= SIZE_4KB;\r
+    Length      -= SIZE_4KB;\r
   }\r
 \r
   return RETURN_SUCCESS;\r
@@ -394,8 +396,8 @@ GetMaxMemoryPage (
   IN  PAGE_ATTRIBUTE  TopLevelType\r
   )\r
 {\r
-  UINT32          RegEax;\r
-  UINT32          RegEdx;\r
+  UINT32  RegEax;\r
+  UINT32  RegEdx;\r
 \r
   if (TopLevelType == Page512G) {\r
     AsmCpuid (CPUID_EXTENDED_FUNCTION, &RegEax, NULL, NULL, NULL);\r
@@ -421,31 +423,31 @@ CreatePageTable (
   VOID\r
   )\r
 {\r
-  RETURN_STATUS           Status;\r
-  UINTN                   PhysicalAddressBits;\r
-  UINTN                   NumberOfEntries;\r
-  PAGE_ATTRIBUTE          TopLevelPageAttr;\r
-  UINTN                   PageTable;\r
-  PAGE_ATTRIBUTE          MaxMemoryPage;\r
-  UINTN                   Index;\r
-  UINT64                  AddressEncMask;\r
-  UINT64                  *PageEntry;\r
-  EFI_PHYSICAL_ADDRESS    PhysicalAddress;\r
-\r
-  TopLevelPageAttr = (PAGE_ATTRIBUTE)GetPageTableTopLevelType ();\r
+  RETURN_STATUS         Status;\r
+  UINTN                 PhysicalAddressBits;\r
+  UINTN                 NumberOfEntries;\r
+  PAGE_ATTRIBUTE        TopLevelPageAttr;\r
+  UINTN                 PageTable;\r
+  PAGE_ATTRIBUTE        MaxMemoryPage;\r
+  UINTN                 Index;\r
+  UINT64                AddressEncMask;\r
+  UINT64                *PageEntry;\r
+  EFI_PHYSICAL_ADDRESS  PhysicalAddress;\r
+\r
+  TopLevelPageAttr    = (PAGE_ATTRIBUTE)GetPageTableTopLevelType ();\r
   PhysicalAddressBits = GetPhysicalAddressWidth ();\r
-  NumberOfEntries = (UINTN)1 << (PhysicalAddressBits -\r
-                                 mPageAttributeTable[TopLevelPageAttr].AddressBitOffset);\r
+  NumberOfEntries     = (UINTN)1 << (PhysicalAddressBits -\r
+                                     mPageAttributeTable[TopLevelPageAttr].AddressBitOffset);\r
 \r
-  PageTable = (UINTN) AllocatePageTableMemory (1);\r
+  PageTable = (UINTN)AllocatePageTableMemory (1);\r
   if (PageTable == 0) {\r
     return 0;\r
   }\r
 \r
-  AddressEncMask = PcdGet64 (PcdPteMemoryEncryptionAddressOrMask);\r
+  AddressEncMask  = PcdGet64 (PcdPteMemoryEncryptionAddressOrMask);\r
   AddressEncMask &= mPageAttributeTable[TopLevelPageAttr].AddressMask;\r
-  MaxMemoryPage = GetMaxMemoryPage (TopLevelPageAttr);\r
-  PageEntry = (UINT64 *)PageTable;\r
+  MaxMemoryPage   = GetMaxMemoryPage (TopLevelPageAttr);\r
+  PageEntry       = (UINT64 *)PageTable;\r
 \r
   PhysicalAddress = 0;\r
   for (Index = 0; Index < NumberOfEntries; ++Index) {\r
@@ -455,7 +457,7 @@ CreatePageTable (
     // Split the top page table down to the maximum page size supported\r
     //\r
     if (MaxMemoryPage < TopLevelPageAttr) {\r
-      Status = SplitPage(PageEntry, TopLevelPageAttr, MaxMemoryPage, TRUE);\r
+      Status = SplitPage (PageEntry, TopLevelPageAttr, MaxMemoryPage, TRUE);\r
       ASSERT_EFI_ERROR (Status);\r
     }\r
 \r
@@ -466,11 +468,10 @@ CreatePageTable (
       *PageEntry &= ~(UINT64)(IA32_PG_RW | IA32_PG_U);\r
     }\r
 \r
-    PageEntry += 1;\r
+    PageEntry       += 1;\r
     PhysicalAddress += mPageAttributeTable[TopLevelPageAttr].Length;\r
   }\r
 \r
-\r
   return PageTable;\r
 }\r
 \r
@@ -483,12 +484,12 @@ EnablePaging (
   VOID\r
   )\r
 {\r
-  UINTN                       PageTable;\r
+  UINTN  PageTable;\r
 \r
   PageTable = CreatePageTable ();\r
   ASSERT (PageTable != 0);\r
   if (PageTable != 0) {\r
-    AsmWriteCr3(PageTable);\r
+    AsmWriteCr3 (PageTable);\r
     AsmWriteCr4 (AsmReadCr4 () | BIT5);   // CR4.PAE\r
     AsmWriteCr0 (AsmReadCr0 () | BIT31);  // CR0.PG\r
   }\r
@@ -509,15 +510,15 @@ EnablePaging (
 VOID\r
 EFIAPI\r
 GetStackBase (\r
-  IN OUT VOID *Buffer\r
+  IN OUT VOID  *Buffer\r
   )\r
 {\r
-  EFI_PHYSICAL_ADDRESS    StackBase;\r
+  EFI_PHYSICAL_ADDRESS  StackBase;\r
 \r
-  StackBase = (EFI_PHYSICAL_ADDRESS)(UINTN)&StackBase;\r
+  StackBase  = (EFI_PHYSICAL_ADDRESS)(UINTN)&StackBase;\r
   StackBase += BASE_4KB;\r
   StackBase &= ~((EFI_PHYSICAL_ADDRESS)BASE_4KB - 1);\r
-  StackBase -= PcdGet32(PcdCpuApStackSize);\r
+  StackBase -= PcdGet32 (PcdCpuApStackSize);\r
 \r
   *(EFI_PHYSICAL_ADDRESS *)Buffer = StackBase;\r
 }\r
@@ -532,21 +533,21 @@ SetupStackGuardPage (
   VOID\r
   )\r
 {\r
-  EFI_PEI_HOB_POINTERS        Hob;\r
-  EFI_PHYSICAL_ADDRESS        StackBase;\r
-  UINTN                       NumberOfProcessors;\r
-  UINTN                       Bsp;\r
-  UINTN                       Index;\r
+  EFI_PEI_HOB_POINTERS  Hob;\r
+  EFI_PHYSICAL_ADDRESS  StackBase;\r
+  UINTN                 NumberOfProcessors;\r
+  UINTN                 Bsp;\r
+  UINTN                 Index;\r
 \r
   //\r
   // One extra page at the bottom of the stack is needed for Guard page.\r
   //\r
-  if (PcdGet32(PcdCpuApStackSize) <= EFI_PAGE_SIZE) {\r
+  if (PcdGet32 (PcdCpuApStackSize) <= EFI_PAGE_SIZE) {\r
     DEBUG ((DEBUG_ERROR, "PcdCpuApStackSize is not big enough for Stack Guard!\n"));\r
     ASSERT (FALSE);\r
   }\r
 \r
-  MpInitLibGetNumberOfProcessors(&NumberOfProcessors, NULL);\r
+  MpInitLibGetNumberOfProcessors (&NumberOfProcessors, NULL);\r
   MpInitLibWhoAmI (&Bsp);\r
   for (Index = 0; Index < NumberOfProcessors; ++Index) {\r
     StackBase = 0;\r
@@ -554,26 +555,35 @@ SetupStackGuardPage (
     if (Index == Bsp) {\r
       Hob.Raw = GetHobList ();\r
       while ((Hob.Raw = GetNextHob (EFI_HOB_TYPE_MEMORY_ALLOCATION, Hob.Raw)) != NULL) {\r
-        if (CompareGuid (&gEfiHobMemoryAllocStackGuid,\r
-                         &(Hob.MemoryAllocationStack->AllocDescriptor.Name))) {\r
+        if (CompareGuid (\r
+              &gEfiHobMemoryAllocStackGuid,\r
+              &(Hob.MemoryAllocationStack->AllocDescriptor.Name)\r
+              ))\r
+        {\r
           StackBase = Hob.MemoryAllocationStack->AllocDescriptor.MemoryBaseAddress;\r
           break;\r
         }\r
+\r
         Hob.Raw = GET_NEXT_HOB (Hob);\r
       }\r
     } else {\r
       //\r
       // Ask AP to return is stack base address.\r
       //\r
-      MpInitLibStartupThisAP(GetStackBase, Index, NULL, 0, (VOID *)&StackBase, NULL);\r
+      MpInitLibStartupThisAP (GetStackBase, Index, NULL, 0, (VOID *)&StackBase, NULL);\r
     }\r
+\r
     ASSERT (StackBase != 0);\r
     //\r
     // Set Guard page at stack base address.\r
     //\r
-    ConvertMemoryPageAttributes(StackBase, EFI_PAGE_SIZE, 0);\r
-    DEBUG ((DEBUG_INFO, "Stack Guard set at %lx [cpu%lu]!\n",\r
-            (UINT64)StackBase, (UINT64)Index));\r
+    ConvertMemoryPageAttributes (StackBase, EFI_PAGE_SIZE, 0);\r
+    DEBUG ((\r
+      DEBUG_INFO,\r
+      "Stack Guard set at %lx [cpu%lu]!\n",\r
+      (UINT64)StackBase,\r
+      (UINT64)Index\r
+      ));\r
   }\r
 \r
   //\r
@@ -614,13 +624,13 @@ MemoryDiscoveredPpiNotifyCallback (
   // the task switch (for the sake of stack switch).\r
   //\r
   InitStackGuard = FALSE;\r
-  Hob.Raw = NULL;\r
+  Hob.Raw        = NULL;\r
   if (IsIa32PaeSupported ()) {\r
-    Hob.Raw  = GetFirstGuidHob (&gEdkiiMigratedFvInfoGuid);\r
+    Hob.Raw        = GetFirstGuidHob (&gEdkiiMigratedFvInfoGuid);\r
     InitStackGuard = PcdGetBool (PcdCpuStackGuard);\r
   }\r
 \r
-  if (InitStackGuard || Hob.Raw != NULL) {\r
+  if (InitStackGuard || (Hob.Raw != NULL)) {\r
     EnablePaging ();\r
   }\r
 \r
@@ -643,8 +653,8 @@ MemoryDiscoveredPpiNotifyCallback (
     Hob.Raw = GET_NEXT_HOB (Hob);\r
     Hob.Raw = GetNextGuidHob (&gEdkiiMigratedFvInfoGuid, Hob.Raw);\r
   }\r
+\r
   CpuFlushTlb ();\r
 \r
   return Status;\r
 }\r
-\r

diff --git a/UefiCpuPkg/CpuS3DataDxe/CpuS3Data.c b/UefiCpuPkg/CpuS3DataDxe/CpuS3Data.c
index 6100799a79160bed7040a314e93dfa3a1d3d6b6b..59a5d932eee203b255cb627c75845033274e004c 100644 (file)
--- a/UefiCpuPkg/CpuS3DataDxe/CpuS3Data.c
+++ b/UefiCpuPkg/CpuS3DataDxe/CpuS3Data.c
@@ -34,10 +34,10 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
 // Data structure used to allocate ACPI_CPU_DATA and its supporting structures\r
 //\r
 typedef struct {\r
-  ACPI_CPU_DATA             AcpiCpuData;\r
-  MTRR_SETTINGS             MtrrTable;\r
-  IA32_DESCRIPTOR           GdtrProfile;\r
-  IA32_DESCRIPTOR           IdtrProfile;\r
+  ACPI_CPU_DATA      AcpiCpuData;\r
+  MTRR_SETTINGS      MtrrTable;\r
+  IA32_DESCRIPTOR    GdtrProfile;\r
+  IA32_DESCRIPTOR    IdtrProfile;\r
 } ACPI_CPU_DATA_EX;\r
 \r
 /**\r
@@ -57,12 +57,12 @@ AllocateAcpiNvsMemory (
   EFI_STATUS            Status;\r
   VOID                  *Buffer;\r
 \r
-  Status  = gBS->AllocatePages (\r
-                   AllocateAnyPages,\r
-                   EfiACPIMemoryNVS,\r
-                   EFI_SIZE_TO_PAGES (Size),\r
-                   &Address\r
-                   );\r
+  Status = gBS->AllocatePages (\r
+                  AllocateAnyPages,\r
+                  EfiACPIMemoryNVS,\r
+                  EFI_SIZE_TO_PAGES (Size),\r
+                  &Address\r
+                  );\r
   if (EFI_ERROR (Status)) {\r
     return NULL;\r
   }\r
@@ -86,7 +86,7 @@ AllocateZeroPages (
   IN UINTN  Size\r
   )\r
 {\r
-  VOID                  *Buffer;\r
+  VOID  *Buffer;\r
 \r
   Buffer = AllocatePages (EFI_SIZE_TO_PAGES (Size));\r
   if (Buffer != NULL) {\r
@@ -95,6 +95,7 @@ AllocateZeroPages (
 \r
   return Buffer;\r
 }\r
+\r
 /**\r
   Callback function executed when the EndOfDxe event group is signaled.\r
 \r
@@ -110,20 +111,20 @@ CpuS3DataOnEndOfDxe (
   OUT VOID       *Context\r
   )\r
 {\r
-  EFI_STATUS         Status;\r
-  ACPI_CPU_DATA_EX   *AcpiCpuDataEx;\r
+  EFI_STATUS        Status;\r
+  ACPI_CPU_DATA_EX  *AcpiCpuDataEx;\r
 \r
-  AcpiCpuDataEx = (ACPI_CPU_DATA_EX *) Context;\r
+  AcpiCpuDataEx = (ACPI_CPU_DATA_EX *)Context;\r
   //\r
   // Allocate a 4KB reserved page below 1MB\r
   //\r
   AcpiCpuDataEx->AcpiCpuData.StartupVector = BASE_1MB - 1;\r
-  Status = gBS->AllocatePages (\r
-                  AllocateMaxAddress,\r
-                  EfiReservedMemoryType,\r
-                  1,\r
-                  &AcpiCpuDataEx->AcpiCpuData.StartupVector\r
-                  );\r
+  Status                                   = gBS->AllocatePages (\r
+                                                    AllocateMaxAddress,\r
+                                                    EfiReservedMemoryType,\r
+                                                    1,\r
+                                                    &AcpiCpuDataEx->AcpiCpuData.StartupVector\r
+                                                    );\r
   ASSERT_EFI_ERROR (Status);\r
 \r
   DEBUG ((DEBUG_VERBOSE, "%a\n", __FUNCTION__));\r
@@ -158,19 +159,19 @@ CpuS3DataInitialize (
   IN EFI_SYSTEM_TABLE  *SystemTable\r
   )\r
 {\r
-  EFI_STATUS                 Status;\r
-  ACPI_CPU_DATA_EX           *AcpiCpuDataEx;\r
-  ACPI_CPU_DATA              *AcpiCpuData;\r
-  EFI_MP_SERVICES_PROTOCOL   *MpServices;\r
-  UINTN                      NumberOfCpus;\r
-  UINTN                      NumberOfEnabledProcessors;\r
-  VOID                       *Stack;\r
-  UINTN                      GdtSize;\r
-  UINTN                      IdtSize;\r
-  VOID                       *Gdt;\r
-  VOID                       *Idt;\r
-  EFI_EVENT                  Event;\r
-  ACPI_CPU_DATA              *OldAcpiCpuData;\r
+  EFI_STATUS                Status;\r
+  ACPI_CPU_DATA_EX          *AcpiCpuDataEx;\r
+  ACPI_CPU_DATA             *AcpiCpuData;\r
+  EFI_MP_SERVICES_PROTOCOL  *MpServices;\r
+  UINTN                     NumberOfCpus;\r
+  UINTN                     NumberOfEnabledProcessors;\r
+  VOID                      *Stack;\r
+  UINTN                     GdtSize;\r
+  UINTN                     IdtSize;\r
+  VOID                      *Gdt;\r
+  VOID                      *Idt;\r
+  EFI_EVENT                 Event;\r
+  ACPI_CPU_DATA             *OldAcpiCpuData;\r
 \r
   if (!PcdGetBool (PcdAcpiS3Enable)) {\r
     return EFI_UNSUPPORTED;\r
@@ -179,7 +180,7 @@ CpuS3DataInitialize (
   //\r
   // Set PcdCpuS3DataAddress to the base address of the ACPI_CPU_DATA structure\r
   //\r
-  OldAcpiCpuData = (ACPI_CPU_DATA *) (UINTN) PcdGet64 (PcdCpuS3DataAddress);\r
+  OldAcpiCpuData = (ACPI_CPU_DATA *)(UINTN)PcdGet64 (PcdCpuS3DataAddress);\r
 \r
   AcpiCpuDataEx = AllocateZeroPages (sizeof (ACPI_CPU_DATA_EX));\r
   ASSERT (AcpiCpuDataEx != NULL);\r
@@ -212,9 +213,9 @@ CpuS3DataInitialize (
   AcpiCpuData->StackSize                 = PcdGet32 (PcdCpuApStackSize);\r
   AcpiCpuData->ApMachineCheckHandlerBase = 0;\r
   AcpiCpuData->ApMachineCheckHandlerSize = 0;\r
-  AcpiCpuData->GdtrProfile  = (EFI_PHYSICAL_ADDRESS)(UINTN)&AcpiCpuDataEx->GdtrProfile;\r
-  AcpiCpuData->IdtrProfile  = (EFI_PHYSICAL_ADDRESS)(UINTN)&AcpiCpuDataEx->IdtrProfile;\r
-  AcpiCpuData->MtrrTable    = (EFI_PHYSICAL_ADDRESS)(UINTN)&AcpiCpuDataEx->MtrrTable;\r
+  AcpiCpuData->GdtrProfile               = (EFI_PHYSICAL_ADDRESS)(UINTN)&AcpiCpuDataEx->GdtrProfile;\r
+  AcpiCpuData->IdtrProfile               = (EFI_PHYSICAL_ADDRESS)(UINTN)&AcpiCpuDataEx->IdtrProfile;\r
+  AcpiCpuData->MtrrTable                 = (EFI_PHYSICAL_ADDRESS)(UINTN)&AcpiCpuDataEx->MtrrTable;\r
 \r
   //\r
   // Allocate stack space for all CPUs.\r
@@ -238,7 +239,7 @@ CpuS3DataInitialize (
   //\r
   GdtSize = AcpiCpuDataEx->GdtrProfile.Limit + 1;\r
   IdtSize = AcpiCpuDataEx->IdtrProfile.Limit + 1;\r
-  Gdt = AllocateZeroPages (GdtSize + IdtSize);\r
+  Gdt     = AllocateZeroPages (GdtSize + IdtSize);\r
   ASSERT (Gdt != NULL);\r
   Idt = (VOID *)((UINTN)Gdt + GdtSize);\r
   CopyMem (Gdt, (VOID *)AcpiCpuDataEx->GdtrProfile.Base, GdtSize);\r

diff --git a/UefiCpuPkg/Include/AcpiCpuData.h b/UefiCpuPkg/Include/AcpiCpuData.h
index 659821072d0d74cdddfc180fd684c32aadb0f2bc..161a43c27835b6fd8e861ef1d4d269916c42b423 100644 (file)
--- a/UefiCpuPkg/Include/AcpiCpuData.h
+++ b/UefiCpuPkg/Include/AcpiCpuData.h
@@ -52,19 +52,19 @@ typedef struct {
   //\r
   // Record the package count in this CPU.\r
   //\r
-  UINT32                      PackageCount;\r
+  UINT32    PackageCount;\r
   //\r
   // Record the max core count in this CPU.\r
   // Different packages may have different core count, this value\r
   // save the max core count in all the packages.\r
   //\r
-  UINT32                      MaxCoreCount;\r
+  UINT32    MaxCoreCount;\r
   //\r
   // Record the max thread count in this CPU.\r
   // Different cores may have different thread count, this value\r
   // save the max thread count in all the cores.\r
   //\r
-  UINT32                      MaxThreadCount;\r
+  UINT32    MaxThreadCount;\r
   //\r
   // This field points to an array.\r
   // This array saves thread count (type UINT32) of each package.\r
@@ -74,7 +74,7 @@ typedef struct {
   // therefore it doesn't need the dependency semaphores, it should set\r
   // this field to 0.\r
   //\r
-  EFI_PHYSICAL_ADDRESS        ThreadCountPerPackage;\r
+  EFI_PHYSICAL_ADDRESS    ThreadCountPerPackage;\r
   //\r
   // This field points to an array.\r
   // This array saves thread count (type UINT8) of each core.\r
@@ -84,21 +84,21 @@ typedef struct {
   // therefore it doesn't need the dependency semaphores, it should set\r
   // this field to 0.\r
   //\r
-  EFI_PHYSICAL_ADDRESS        ThreadCountPerCore;\r
+  EFI_PHYSICAL_ADDRESS    ThreadCountPerCore;\r
 } CPU_STATUS_INFORMATION;\r
 \r
 //\r
 // Element of register table entry\r
 //\r
 typedef struct {\r
-  REGISTER_TYPE  RegisterType;          // offset 0 - 3\r
-  UINT32         Index;                 // offset 4 - 7\r
-  UINT8          ValidBitStart;         // offset 8\r
-  UINT8          ValidBitLength;        // offset 9\r
-  BOOLEAN        TestThenWrite;         // offset 10\r
-  UINT8          Reserved1;             // offset 11\r
-  UINT32         HighIndex;             // offset 12-15, only valid for MemoryMapped\r
-  UINT64         Value;                 // offset 16-23\r
+  REGISTER_TYPE    RegisterType;        // offset 0 - 3\r
+  UINT32           Index;               // offset 4 - 7\r
+  UINT8            ValidBitStart;       // offset 8\r
+  UINT8            ValidBitLength;      // offset 9\r
+  BOOLEAN          TestThenWrite;       // offset 10\r
+  UINT8            Reserved1;           // offset 11\r
+  UINT32           HighIndex;           // offset 12-15, only valid for MemoryMapped\r
+  UINT64           Value;               // offset 16-23\r
 } CPU_REGISTER_TABLE_ENTRY;\r
 \r
 //\r
@@ -109,20 +109,20 @@ typedef struct {
   //\r
   // The number of valid entries in the RegisterTableEntry buffer\r
   //\r
-  UINT32                    TableLength;\r
-  UINT32                    NumberBeforeReset;\r
+  UINT32                  TableLength;\r
+  UINT32                  NumberBeforeReset;\r
   //\r
   // The size, in bytes, of the RegisterTableEntry buffer\r
   //\r
-  UINT32                    AllocatedSize;\r
+  UINT32                  AllocatedSize;\r
   //\r
   // The initial APIC ID of the CPU this register table applies to\r
   //\r
-  UINT32                    InitialApicId;\r
+  UINT32                  InitialApicId;\r
   //\r
   // Physical address of CPU_REGISTER_TABLE_ENTRY structures.\r
   //\r
-  EFI_PHYSICAL_ADDRESS      RegisterTableEntry;\r
+  EFI_PHYSICAL_ADDRESS    RegisterTableEntry;\r
 } CPU_REGISTER_TABLE;\r
 \r
 //\r
@@ -151,11 +151,11 @@ typedef struct {
   // If a register table is not required for any one of the CPUs, then\r
   // RegisterTable may be set to 0.\r
   //\r
-  EFI_PHYSICAL_ADDRESS    RegisterTable;\r
+  EFI_PHYSICAL_ADDRESS      RegisterTable;\r
   //\r
   // CPU information which is required when set the register table.\r
   //\r
-  CPU_STATUS_INFORMATION  CpuStatus;\r
+  CPU_STATUS_INFORMATION    CpuStatus;\r
   //\r
   // Location info for each AP.\r
   // It points to an array which saves all APs location info.\r
@@ -180,7 +180,7 @@ typedef struct {
   // it is recommended that the buffer be zero-filled.  This buffer is used to\r
   // wake APs during an ACPI S3 resume.\r
   //\r
-  EFI_PHYSICAL_ADDRESS  StartupVector;\r
+  EFI_PHYSICAL_ADDRESS     StartupVector;\r
   //\r
   // Physical address of structure of type IA32_DESCRIPTOR. The\r
   // IA32_DESCRIPTOR structure provides the base address and length of a GDT\r
@@ -188,7 +188,7 @@ typedef struct {
   // used during an ACPI S3 resume.  This is typically the contents of the GDT\r
   // used by the boot processor when the platform is booted.\r
   //\r
-  EFI_PHYSICAL_ADDRESS  GdtrProfile;\r
+  EFI_PHYSICAL_ADDRESS     GdtrProfile;\r
   //\r
   // Physical address of structure of type IA32_DESCRIPTOR.  The\r
   // IA32_DESCRIPTOR structure provides the base address and length of an IDT.\r
@@ -196,31 +196,31 @@ typedef struct {
   // used during an ACPI S3 resume.  This is typically the contents of the IDT\r
   // used by the boot processor when the platform is booted.\r
   //\r
-  EFI_PHYSICAL_ADDRESS  IdtrProfile;\r
+  EFI_PHYSICAL_ADDRESS     IdtrProfile;\r
   //\r
   // Physical address of a buffer that is used as stacks during ACPI S3 resume.\r
   // The total size of this buffer, in bytes, is NumberOfCpus * StackSize.  This\r
   // structure must be allocated from memory of type EfiACPIMemoryNVS.\r
   //\r
-  EFI_PHYSICAL_ADDRESS  StackAddress;\r
+  EFI_PHYSICAL_ADDRESS     StackAddress;\r
   //\r
   // The size, in bytes, of the stack provided to each CPU during ACPI S3 resume.\r
   //\r
-  UINT32                StackSize;\r
+  UINT32                   StackSize;\r
   //\r
   // The number of CPUs.  If a platform does not support hot plug CPUs, then\r
   // this is the number of CPUs detected when the platform is booted, regardless\r
   // of being enabled or disabled.  If a platform does support hot plug CPUs,\r
   // then this is the maximum number of CPUs that the platform supports.\r
   //\r
-  UINT32                NumberOfCpus;\r
+  UINT32                   NumberOfCpus;\r
   //\r
   // Physical address of structure of type MTRR_SETTINGS that contains a copy\r
   // of the MTRR settings that are compatible with the MTRR settings used by\r
   // the boot processor when the platform was booted.  These MTRR settings are\r
   // used during an ACPI S3 resume.\r
   //\r
-  EFI_PHYSICAL_ADDRESS  MtrrTable;\r
+  EFI_PHYSICAL_ADDRESS     MtrrTable;\r
   //\r
   // Physical address of a buffer that contains the machine check handler that\r
   // is used during an ACPI S3 Resume.  In order for this machine check\r
@@ -228,18 +228,18 @@ typedef struct {
   // vector in the IDT provided by IdtrProfile must be initialized to transfer\r
   // control to this physical address.\r
   //\r
-  EFI_PHYSICAL_ADDRESS  ApMachineCheckHandlerBase;\r
+  EFI_PHYSICAL_ADDRESS     ApMachineCheckHandlerBase;\r
   //\r
   // The size, in bytes, of the machine check handler that is used during an\r
   // ACPI S3 Resume.  If this field is 0, then a machine check handler is not\r
   // provided.\r
   //\r
-  UINT32                ApMachineCheckHandlerSize;\r
+  UINT32                   ApMachineCheckHandlerSize;\r
   //\r
   // Data structure that is used for CPU feature initialization during ACPI S3\r
   // resume.\r
   //\r
-  CPU_FEATURE_INIT_DATA CpuFeatureInitData;\r
+  CPU_FEATURE_INIT_DATA    CpuFeatureInitData;\r
 } ACPI_CPU_DATA;\r
 \r
 #endif\r

diff --git a/UefiCpuPkg/Include/CpuHotPlugData.h b/UefiCpuPkg/Include/CpuHotPlugData.h
index 6321a149fa52484da114a72de865c645b6cb8d56..dd0d7b9f3e9d1672f1ea5fa1c54a27148a82ff02 100644 (file)
--- a/UefiCpuPkg/Include/CpuHotPlugData.h
+++ b/UefiCpuPkg/Include/CpuHotPlugData.h
@@ -9,7 +9,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
 #ifndef _CPU_HOT_PLUG_DATA_H_\r
 #define _CPU_HOT_PLUG_DATA_H_\r
 \r
-#define  CPU_HOT_PLUG_DATA_REVISION_1      0x00000001\r
+#define  CPU_HOT_PLUG_DATA_REVISION_1  0x00000001\r
 \r
 typedef struct {\r
   UINT32    Revision;          // Used for version identification for this structure\r

diff --git a/UefiCpuPkg/Include/Guid/CpuFeaturesInitDone.h b/UefiCpuPkg/Include/Guid/CpuFeaturesInitDone.h
index 81c8ff63d48bceb830eec5aba5e7c56d62d5e0e8..b23580f1dafdbb507e855d63820a7902ab82e757 100644 (file)
--- a/UefiCpuPkg/Include/Guid/CpuFeaturesInitDone.h
+++ b/UefiCpuPkg/Include/Guid/CpuFeaturesInitDone.h
@@ -15,6 +15,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
     { 0xc77c3a41, 0x61ab, 0x4143, { 0x98, 0x3e, 0x33, 0x39, 0x28, 0x6, 0x28, 0xe5 } \\r
   }\r
 \r
-extern EFI_GUID gEdkiiCpuFeaturesInitDoneGuid;\r
+extern EFI_GUID  gEdkiiCpuFeaturesInitDoneGuid;\r
 \r
 #endif\r

diff --git a/UefiCpuPkg/Include/Guid/CpuFeaturesSetDone.h b/UefiCpuPkg/Include/Guid/CpuFeaturesSetDone.h
index a005a51fd6565a868d41f5b849586f55f18982b7..28eb5c7076db8cb6788890a16feeabf7ee740d72 100644 (file)
--- a/UefiCpuPkg/Include/Guid/CpuFeaturesSetDone.h
+++ b/UefiCpuPkg/Include/Guid/CpuFeaturesSetDone.h
@@ -15,6 +15,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
     { 0xa82485ce, 0xad6b, 0x4101, { 0x99, 0xd3, 0xe1, 0x35, 0x8c, 0x9e, 0x7e, 0x37 } \\r
   }\r
 \r
-extern EFI_GUID gEdkiiCpuFeaturesSetDoneGuid;\r
+extern EFI_GUID  gEdkiiCpuFeaturesSetDoneGuid;\r
 \r
 #endif\r

diff --git a/UefiCpuPkg/Include/Guid/MicrocodePatchHob.h b/UefiCpuPkg/Include/Guid/MicrocodePatchHob.h
index 2d307fbffbf1d8711166103800df36ae25be9c06..2772c41a16a40673bc73e9376ad48224b314d61f 100644 (file)
--- a/UefiCpuPkg/Include/Guid/MicrocodePatchHob.h
+++ b/UefiCpuPkg/Include/Guid/MicrocodePatchHob.h
@@ -11,7 +11,7 @@
 #ifndef _MICROCODE_PATCH_HOB_H_\r
 #define _MICROCODE_PATCH_HOB_H_\r
 \r
-extern EFI_GUID gEdkiiMicrocodePatchHobGuid;\r
+extern EFI_GUID  gEdkiiMicrocodePatchHobGuid;\r
 \r
 //\r
 // The EDKII microcode patch HOB will be produced by MpInitLib and it can be\r

diff --git a/UefiCpuPkg/Include/Guid/MsegSmram.h b/UefiCpuPkg/Include/Guid/MsegSmram.h
index 01001c4730d8f3f5a67bc7f8a79ea471edfa6ef6..77dd3eda054f58211bd549e69a326a8967c6942e 100644 (file)
--- a/UefiCpuPkg/Include/Guid/MsegSmram.h
+++ b/UefiCpuPkg/Include/Guid/MsegSmram.h
@@ -15,7 +15,7 @@
     0x5802bce4, 0xeeee, 0x4e33, { 0xa1, 0x30, 0xeb, 0xad, 0x27, 0xf0, 0xe4, 0x39 } \\r
   }\r
 \r
-extern EFI_GUID gMsegSmramGuid;\r
+extern EFI_GUID  gMsegSmramGuid;\r
 \r
 //\r
 // The data portion of this HOB is type EFI_SMRAM_DESCRIPTOR\r

diff --git a/UefiCpuPkg/Include/Library/CpuCacheInfoLib.h b/UefiCpuPkg/Include/Library/CpuCacheInfoLib.h
index 3422997f54fcb87c0be2e03c0d2bf1d05e4408e4..022d9f2ca8c2c3785dc6e06e7c85599f7e05dda8 100644 (file)
--- a/UefiCpuPkg/Include/Library/CpuCacheInfoLib.h
+++ b/UefiCpuPkg/Include/Library/CpuCacheInfoLib.h
@@ -13,49 +13,49 @@ typedef struct {
   //\r
   // Package number.\r
   //\r
-  UINT32        Package;\r
+  UINT32    Package;\r
   //\r
   // Core type of logical processor.\r
   // Value = CPUID.1Ah:EAX[31:24]\r
   //\r
-  UINT8         CoreType;\r
+  UINT8     CoreType;\r
   //\r
   // Level of the cache that this package's this type of logical processor corresponds to.\r
   // Value = CPUID.04h:EAX[07:05]\r
   //\r
-  UINT8         CacheLevel : 3;\r
+  UINT8     CacheLevel            : 3;\r
   //\r
   // Type of the cache that this package's this type of logical processor corresponds to.\r
   // Value = CPUID.04h:EAX[04:00]\r
   //\r
-  UINT8         CacheType : 5;\r
+  UINT8     CacheType             : 5;\r
   //\r
   // Ways of associativity.\r
   // Value = CPUID.04h:EBX[31:22]\r
   //\r
-  UINT16        CacheWays : 10;\r
+  UINT16    CacheWays             : 10;\r
   //\r
   // Fully associative cache.\r
   // Value = CPUID.04h:EAX[09]\r
   //\r
-  UINT16        FullyAssociativeCache : 1;\r
+  UINT16    FullyAssociativeCache : 1;\r
   //\r
   // Direct mapped cache.\r
   // Value = CPUID.04h:EDX[02]\r
   //\r
-  UINT16        DirectMappedCache : 1;\r
-  UINT16        Reserved : 4;\r
+  UINT16    DirectMappedCache     : 1;\r
+  UINT16    Reserved              : 4;\r
   //\r
   // Size of single cache that this package's this type of logical processor corresponds to.\r
   // Value = (CPUID.04h:EBX[31:22] + 1) * (CPUID.04h:EBX[21:12] + 1) *\r
   //         (CPUID.04h:EBX[11:00] + 1) * (CPUID.04h:ECX[31:00] + 1)\r
   //\r
-  UINT32        CacheSizeinKB;\r
+  UINT32    CacheSizeinKB;\r
   //\r
   // Number of the cache that this package's this type of logical processor corresponds to.\r
   // Have subtracted the number of caches that are shared.\r
   //\r
-  UINT16        CacheCount;\r
+  UINT16    CacheCount;\r
 } CPU_CACHE_INFO;\r
 \r
 /**\r
@@ -78,8 +78,8 @@ typedef struct {
 EFI_STATUS\r
 EFIAPI\r
 GetCpuCacheInfo (\r
-  IN OUT CPU_CACHE_INFO     *CpuCacheInfo,\r
-  IN OUT UINTN              *CpuCacheInfoCount\r
+  IN OUT CPU_CACHE_INFO  *CpuCacheInfo,\r
+  IN OUT UINTN           *CpuCacheInfoCount\r
   );\r
 \r
 #endif\r

diff --git a/UefiCpuPkg/Include/Library/LocalApicLib.h b/UefiCpuPkg/Include/Library/LocalApicLib.h
index 96b93aa347ace4a2d6ec3e684ce5d732523b30ff..b55d88b0f52c874117ec5c61fce24ff22da5f1d4 100644 (file)
--- a/UefiCpuPkg/Include/Library/LocalApicLib.h
+++ b/UefiCpuPkg/Include/Library/LocalApicLib.h
@@ -38,7 +38,7 @@ GetLocalApicBaseAddress (
 VOID\r
 EFIAPI\r
 SetLocalApicBaseAddress (\r
-  IN UINTN                BaseAddress\r
+  IN UINTN  BaseAddress\r
   );\r
 \r
 /**\r
@@ -120,8 +120,8 @@ GetApicVersion (
 VOID\r
 EFIAPI\r
 SendFixedIpi (\r
-  IN UINT32          ApicId,\r
-  IN UINT8           Vector\r
+  IN UINT32  ApicId,\r
+  IN UINT8   Vector\r
   );\r
 \r
 /**\r
@@ -134,7 +134,7 @@ SendFixedIpi (
 VOID\r
 EFIAPI\r
 SendFixedIpiAllExcludingSelf (\r
-  IN UINT8           Vector\r
+  IN UINT8  Vector\r
   );\r
 \r
 /**\r
@@ -147,7 +147,7 @@ SendFixedIpiAllExcludingSelf (
 VOID\r
 EFIAPI\r
 SendSmiIpi (\r
-  IN UINT32          ApicId\r
+  IN UINT32  ApicId\r
   );\r
 \r
 /**\r
@@ -171,7 +171,7 @@ SendSmiIpiAllExcludingSelf (
 VOID\r
 EFIAPI\r
 SendInitIpi (\r
-  IN UINT32          ApicId\r
+  IN UINT32  ApicId\r
   );\r
 \r
 /**\r
@@ -200,8 +200,8 @@ SendInitIpiAllExcludingSelf (
 VOID\r
 EFIAPI\r
 SendInitSipiSipi (\r
-  IN UINT32          ApicId,\r
-  IN UINT32          StartupRoutine\r
+  IN UINT32  ApicId,\r
+  IN UINT32  StartupRoutine\r
   );\r
 \r
 /**\r
@@ -218,7 +218,7 @@ SendInitSipiSipi (
 VOID\r
 EFIAPI\r
 SendInitSipiSipiAllExcludingSelf (\r
-  IN UINT32          StartupRoutine\r
+  IN UINT32  StartupRoutine\r
   );\r
 \r
 /**\r
@@ -296,10 +296,10 @@ GetApicTimerCurrentCount (
 VOID\r
 EFIAPI\r
 InitializeApicTimer (\r
-  IN UINTN   DivideValue,\r
-  IN UINT32  InitCount,\r
-  IN BOOLEAN PeriodicMode,\r
-  IN UINT8   Vector\r
+  IN UINTN    DivideValue,\r
+  IN UINT32   InitCount,\r
+  IN BOOLEAN  PeriodicMode,\r
+  IN UINT8    Vector\r
   );\r
 \r
 /**\r
@@ -453,5 +453,5 @@ GetProcessorLocation2ByApicId (
   OUT UINT32  *Core     OPTIONAL,\r
   OUT UINT32  *Thread   OPTIONAL\r
   );\r
-#endif\r
 \r
+#endif\r

diff --git a/UefiCpuPkg/Include/Library/MicrocodeLib.h b/UefiCpuPkg/Include/Library/MicrocodeLib.h
index f14d56ba5f7ab617f3d86e57092c8a7925e2e227..1890b5084023329a01295f11e9b79edf20c761d9 100644 (file)
--- a/UefiCpuPkg/Include/Library/MicrocodeLib.h
+++ b/UefiCpuPkg/Include/Library/MicrocodeLib.h
@@ -52,7 +52,7 @@ GetProcessorMicrocodeCpuId (
 UINT32\r
 EFIAPI\r
 GetMicrocodeLength (\r
-  IN CPU_MICROCODE_HEADER *Microcode\r
+  IN CPU_MICROCODE_HEADER  *Microcode\r
   );\r
 \r
 /**\r
@@ -65,7 +65,7 @@ GetMicrocodeLength (
 VOID\r
 EFIAPI\r
 LoadMicrocode (\r
-  IN CPU_MICROCODE_HEADER *Microcode\r
+  IN CPU_MICROCODE_HEADER  *Microcode\r
   );\r
 \r
 /**\r
@@ -109,12 +109,12 @@ LoadMicrocode (
 BOOLEAN\r
 EFIAPI\r
 IsValidMicrocode (\r
-  IN CPU_MICROCODE_HEADER       *Microcode,\r
-  IN UINTN                      MicrocodeLength,\r
-  IN UINT32                     MinimumRevision,\r
-  IN EDKII_PEI_MICROCODE_CPU_ID *MicrocodeCpuIds,\r
-  IN UINTN                      MicrocodeCpuIdCount,\r
-  IN BOOLEAN                    VerifyChecksum\r
+  IN CPU_MICROCODE_HEADER        *Microcode,\r
+  IN UINTN                       MicrocodeLength,\r
+  IN UINT32                      MinimumRevision,\r
+  IN EDKII_PEI_MICROCODE_CPU_ID  *MicrocodeCpuIds,\r
+  IN UINTN                       MicrocodeCpuIdCount,\r
+  IN BOOLEAN                     VerifyChecksum\r
   );\r
 \r
 #endif\r

diff --git a/UefiCpuPkg/Include/Library/MpInitLib.h b/UefiCpuPkg/Include/Library/MpInitLib.h
index d6a1e6c067f2f349115bf3157815f3fa17b7c3fd..1853c464154cbeafff5a8387681ff0ebd3784457 100644 (file)
--- a/UefiCpuPkg/Include/Library/MpInitLib.h
+++ b/UefiCpuPkg/Include/Library/MpInitLib.h
@@ -54,8 +54,8 @@ MpInitLibInitialize (
 EFI_STATUS\r
 EFIAPI\r
 MpInitLibGetNumberOfProcessors (\r
-  OUT UINTN                     *NumberOfProcessors        OPTIONAL,\r
-  OUT UINTN                     *NumberOfEnabledProcessors OPTIONAL\r
+  OUT UINTN  *NumberOfProcessors        OPTIONAL,\r
+  OUT UINTN  *NumberOfEnabledProcessors OPTIONAL\r
   );\r
 \r
 /**\r
@@ -161,12 +161,12 @@ MpInitLibGetProcessorInfo (
 EFI_STATUS\r
 EFIAPI\r
 MpInitLibStartupAllAPs (\r
-  IN  EFI_AP_PROCEDURE          Procedure,\r
-  IN  BOOLEAN                   SingleThread,\r
-  IN  EFI_EVENT                 WaitEvent               OPTIONAL,\r
-  IN  UINTN                     TimeoutInMicroseconds,\r
-  IN  VOID                      *ProcedureArgument      OPTIONAL,\r
-  OUT UINTN                     **FailedCpuList         OPTIONAL\r
+  IN  EFI_AP_PROCEDURE  Procedure,\r
+  IN  BOOLEAN           SingleThread,\r
+  IN  EFI_EVENT         WaitEvent               OPTIONAL,\r
+  IN  UINTN             TimeoutInMicroseconds,\r
+  IN  VOID              *ProcedureArgument      OPTIONAL,\r
+  OUT UINTN             **FailedCpuList         OPTIONAL\r
   );\r
 \r
 /**\r
@@ -243,12 +243,12 @@ MpInitLibStartupAllAPs (
 EFI_STATUS\r
 EFIAPI\r
 MpInitLibStartupThisAP (\r
-  IN  EFI_AP_PROCEDURE          Procedure,\r
-  IN  UINTN                     ProcessorNumber,\r
-  IN  EFI_EVENT                 WaitEvent               OPTIONAL,\r
-  IN  UINTN                     TimeoutInMicroseconds,\r
-  IN  VOID                      *ProcedureArgument      OPTIONAL,\r
-  OUT BOOLEAN                   *Finished               OPTIONAL\r
+  IN  EFI_AP_PROCEDURE  Procedure,\r
+  IN  UINTN             ProcessorNumber,\r
+  IN  EFI_EVENT         WaitEvent               OPTIONAL,\r
+  IN  UINTN             TimeoutInMicroseconds,\r
+  IN  VOID              *ProcedureArgument      OPTIONAL,\r
+  OUT BOOLEAN           *Finished               OPTIONAL\r
   );\r
 \r
 /**\r
@@ -280,8 +280,8 @@ MpInitLibStartupThisAP (
 EFI_STATUS\r
 EFIAPI\r
 MpInitLibSwitchBSP (\r
-  IN UINTN                     ProcessorNumber,\r
-  IN BOOLEAN                   EnableOldBSP\r
+  IN UINTN    ProcessorNumber,\r
+  IN BOOLEAN  EnableOldBSP\r
   );\r
 \r
 /**\r
@@ -317,9 +317,9 @@ MpInitLibSwitchBSP (
 EFI_STATUS\r
 EFIAPI\r
 MpInitLibEnableDisableAP (\r
-  IN  UINTN                     ProcessorNumber,\r
-  IN  BOOLEAN                   EnableAP,\r
-  IN  UINT32                    *HealthFlag OPTIONAL\r
+  IN  UINTN    ProcessorNumber,\r
+  IN  BOOLEAN  EnableAP,\r
+  IN  UINT32   *HealthFlag OPTIONAL\r
   );\r
 \r
 /**\r
@@ -341,7 +341,7 @@ MpInitLibEnableDisableAP (
 EFI_STATUS\r
 EFIAPI\r
 MpInitLibWhoAmI (\r
-  OUT UINTN                    *ProcessorNumber\r
+  OUT UINTN  *ProcessorNumber\r
   );\r
 \r
 /**\r
@@ -373,9 +373,9 @@ MpInitLibWhoAmI (
 EFI_STATUS\r
 EFIAPI\r
 MpInitLibStartupAllCPUs (\r
-  IN  EFI_AP_PROCEDURE          Procedure,\r
-  IN  UINTN                     TimeoutInMicroseconds,\r
-  IN  VOID                      *ProcedureArgument      OPTIONAL\r
+  IN  EFI_AP_PROCEDURE  Procedure,\r
+  IN  UINTN             TimeoutInMicroseconds,\r
+  IN  VOID              *ProcedureArgument      OPTIONAL\r
   );\r
 \r
 #endif\r

diff --git a/UefiCpuPkg/Include/Library/MtrrLib.h b/UefiCpuPkg/Include/Library/MtrrLib.h
index 9110787067b531b4bd41cdb0616509ba6570ca9c..683d9f2c14470d1e387eb14ebc3a881a012c379a 100644 (file)
--- a/UefiCpuPkg/Include/Library/MtrrLib.h
+++ b/UefiCpuPkg/Include/Library/MtrrLib.h
@@ -24,27 +24,27 @@
 //\r
 #define  RESERVED_FIRMWARE_VARIABLE_MTRR_NUMBER  2\r
 \r
-#define  MTRR_NUMBER_OF_FIXED_MTRR      11\r
+#define  MTRR_NUMBER_OF_FIXED_MTRR  11\r
 \r
 //\r
 // Structure to describe a fixed MTRR\r
 //\r
 typedef struct {\r
-  UINT32  Msr;\r
-  UINT32  BaseAddress;\r
-  UINT32  Length;\r
+  UINT32    Msr;\r
+  UINT32    BaseAddress;\r
+  UINT32    Length;\r
 } FIXED_MTRR;\r
 \r
 //\r
 // Structure to describe a variable MTRR\r
 //\r
 typedef struct {\r
-  UINT64  BaseAddress;\r
-  UINT64  Length;\r
-  UINT64  Type;\r
-  UINT32  Msr;\r
-  BOOLEAN Valid;\r
-  BOOLEAN Used;\r
+  UINT64     BaseAddress;\r
+  UINT64     Length;\r
+  UINT64     Type;\r
+  UINT32     Msr;\r
+  BOOLEAN    Valid;\r
+  BOOLEAN    Used;\r
 } VARIABLE_MTRR;\r
 \r
 //\r
@@ -59,14 +59,14 @@ typedef struct _MTRR_VARIABLE_SETTING_ {
 // Array for variable MTRRs\r
 //\r
 typedef struct _MTRR_VARIABLE_SETTINGS_ {\r
-  MTRR_VARIABLE_SETTING   Mtrr[MTRR_NUMBER_OF_VARIABLE_MTRR];\r
+  MTRR_VARIABLE_SETTING    Mtrr[MTRR_NUMBER_OF_VARIABLE_MTRR];\r
 } MTRR_VARIABLE_SETTINGS;\r
 \r
 //\r
 // Array for fixed MTRRs\r
 //\r
 typedef  struct  _MTRR_FIXED_SETTINGS_ {\r
-  UINT64       Mtrr[MTRR_NUMBER_OF_FIXED_MTRR];\r
+  UINT64    Mtrr[MTRR_NUMBER_OF_FIXED_MTRR];\r
 } MTRR_FIXED_SETTINGS;\r
 \r
 //\r
@@ -98,9 +98,9 @@ typedef enum {
 #define  MTRR_CACHE_INVALID_TYPE     7\r
 \r
 typedef struct {\r
-  UINT64                 BaseAddress;\r
-  UINT64                 Length;\r
-  MTRR_MEMORY_CACHE_TYPE Type;\r
+  UINT64                    BaseAddress;\r
+  UINT64                    Length;\r
+  MTRR_MEMORY_CACHE_TYPE    Type;\r
 } MTRR_MEMORY_RANGE;\r
 \r
 /**\r
@@ -168,7 +168,6 @@ MtrrSetMemoryAttribute (
   IN MTRR_MEMORY_CACHE_TYPE  Attribute\r
   );\r
 \r
-\r
 /**\r
   This function will get the memory cache type of the specific address.\r
   This function is mainly for debugging purposes.\r
@@ -181,10 +180,9 @@ MtrrSetMemoryAttribute (
 MTRR_MEMORY_CACHE_TYPE\r
 EFIAPI\r
 MtrrGetMemoryAttribute (\r
-  IN PHYSICAL_ADDRESS   Address\r
+  IN PHYSICAL_ADDRESS  Address\r
   );\r
 \r
-\r
 /**\r
   This function gets the content in fixed MTRRs\r
 \r
@@ -193,13 +191,12 @@ MtrrGetMemoryAttribute (
   @return The pointer of FixedSettings\r
 \r
 **/\r
-MTRR_FIXED_SETTINGS*\r
+MTRR_FIXED_SETTINGS *\r
 EFIAPI\r
 MtrrGetFixedMtrr (\r
-  OUT MTRR_FIXED_SETTINGS         *FixedSettings\r
+  OUT MTRR_FIXED_SETTINGS  *FixedSettings\r
   );\r
 \r
-\r
 /**\r
   This function gets the content in all MTRRs (variable and fixed)\r
 \r
@@ -211,10 +208,9 @@ MtrrGetFixedMtrr (
 MTRR_SETTINGS *\r
 EFIAPI\r
 MtrrGetAllMtrrs (\r
-  OUT MTRR_SETTINGS                *MtrrSetting\r
+  OUT MTRR_SETTINGS  *MtrrSetting\r
   );\r
 \r
-\r
 /**\r
   This function sets all MTRRs (variable and fixed)\r
 \r
@@ -226,10 +222,9 @@ MtrrGetAllMtrrs (
 MTRR_SETTINGS *\r
 EFIAPI\r
 MtrrSetAllMtrrs (\r
-  IN MTRR_SETTINGS                *MtrrSetting\r
+  IN MTRR_SETTINGS  *MtrrSetting\r
   );\r
 \r
-\r
 /**\r
   Get the attribute of variable MTRRs.\r
 \r
@@ -248,12 +243,11 @@ MtrrSetAllMtrrs (
 UINT32\r
 EFIAPI\r
 MtrrGetMemoryAttributeInVariableMtrr (\r
-  IN  UINT64                    MtrrValidBitsMask,\r
-  IN  UINT64                    MtrrValidAddressMask,\r
-  OUT VARIABLE_MTRR             *VariableMtrr\r
+  IN  UINT64         MtrrValidBitsMask,\r
+  IN  UINT64         MtrrValidAddressMask,\r
+  OUT VARIABLE_MTRR  *VariableMtrr\r
   );\r
 \r
-\r
 /**\r
   This function prints all MTRRs for debugging.\r
 **/\r
@@ -355,10 +349,11 @@ MtrrSetMemoryAttributeInMtrrSettings (
 RETURN_STATUS\r
 EFIAPI\r
 MtrrSetMemoryAttributesInMtrrSettings (\r
-  IN OUT MTRR_SETTINGS           *MtrrSetting,\r
-  IN     VOID                    *Scratch,\r
-  IN OUT UINTN                   *ScratchSize,\r
-  IN     CONST MTRR_MEMORY_RANGE *Ranges,\r
-  IN     UINTN                   RangeCount\r
+  IN OUT MTRR_SETTINGS            *MtrrSetting,\r
+  IN     VOID                     *Scratch,\r
+  IN OUT UINTN                    *ScratchSize,\r
+  IN     CONST MTRR_MEMORY_RANGE  *Ranges,\r
+  IN     UINTN                    RangeCount\r
   );\r
+\r
 #endif // _MTRR_LIB_H_\r

diff --git a/UefiCpuPkg/Include/Library/PlatformSecLib.h b/UefiCpuPkg/Include/Library/PlatformSecLib.h
index c27ecfaf94b2def6c1e8866f5e4a1e53e08a13ec..564fc31542435ea0ef4b0b504e8c65fad4307d75 100644 (file)
--- a/UefiCpuPkg/Include/Library/PlatformSecLib.h
+++ b/UefiCpuPkg/Include/Library/PlatformSecLib.h
@@ -30,7 +30,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
 EFI_PEI_PPI_DESCRIPTOR *\r
 EFIAPI\r
 SecPlatformMain (\r
-  IN OUT   EFI_SEC_PEI_HAND_OFF        *SecCoreData\r
+  IN OUT   EFI_SEC_PEI_HAND_OFF  *SecCoreData\r
   );\r
 \r
 /**\r
@@ -47,9 +47,9 @@ SecPlatformMain (
 EFI_STATUS\r
 EFIAPI\r
 SecPlatformInformation (\r
-  IN CONST EFI_PEI_SERVICES                     **PeiServices,\r
-  IN OUT   UINT64                               *StructureSize,\r
-     OUT   EFI_SEC_PLATFORM_INFORMATION_RECORD  *PlatformInformationRecord\r
+  IN CONST EFI_PEI_SERVICES                  **PeiServices,\r
+  IN OUT   UINT64                            *StructureSize,\r
+  OUT   EFI_SEC_PLATFORM_INFORMATION_RECORD  *PlatformInformationRecord\r
   );\r
 \r
 /**\r

diff --git a/UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h b/UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h
index 60caf313bf4f2366c6fff6af023ac2271fe2c0e2..36459afc5e242dfec9c358574d605b99561a3197 100644 (file)
--- a/UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h
+++ b/UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h
@@ -20,62 +20,62 @@
 /// modifiers of a CPU feature.  When used in a list, the define value\r
 /// CPU_FEATURE_END is used to terminate a list of CPU feature values.\r
 /// @{\r
-#define CPU_FEATURE_AESNI                           0\r
-#define CPU_FEATURE_TURBO_MODE                      1\r
-#define CPU_FEATURE_MWAIT                           2\r
-#define CPU_FEATURE_ACPI                            3\r
-#define CPU_FEATURE_EIST                            4\r
-#define CPU_FEATURE_RESERVED_5                      5\r
-#define CPU_FEATURE_FASTSTRINGS                     6\r
-#define CPU_FEATURE_VMX                             7\r
-#define CPU_FEATURE_SMX                             8\r
-#define CPU_FEATURE_LMCE                            9\r
-#define CPU_FEATURE_LOCK_FEATURE_CONTROL_REGISTER   10\r
-#define CPU_FEATURE_LIMIT_CPUID_MAX_VAL             11\r
-#define CPU_FEATURE_MCE                             12\r
-#define CPU_FEATURE_MCA                             13\r
-#define CPU_FEATURE_MCG_CTL                         14\r
-#define CPU_FEATURE_PENDING_BREAK                   15\r
-#define CPU_FEATURE_C1E                             16\r
-#define CPU_FEATURE_C1_AUTO_DEMOTION                17\r
-#define CPU_FEATURE_C3_AUTO_DEMOTION                18\r
-#define CPU_FEATURE_C1_UNDEMOTION                   19\r
-#define CPU_FEATURE_C3_UNDEMOTION                   20\r
-#define CPU_FEATURE_C_STATE                         21\r
-#define CPU_FEATURE_TM                              22\r
-#define CPU_FEATURE_TM2                             23\r
-#define CPU_FEATURE_X2APIC                          24\r
-#define CPU_FEATURE_RESERVED_25                     25\r
-#define CPU_FEATURE_RESERVED_26                     26\r
-#define CPU_FEATURE_RESERVED_27                     27\r
-#define CPU_FEATURE_RESERVED_28                     28\r
-#define CPU_FEATURE_RESERVED_29                     29\r
-#define CPU_FEATURE_RESERVED_30                     30\r
-#define CPU_FEATURE_RESERVED_31                     31\r
-\r
-#define CPU_FEATURE_L2_PREFETCHER                   (32+0)\r
-#define CPU_FEATURE_L1_DATA_PREFETCHER              (32+1)\r
-#define CPU_FEATURE_HARDWARE_PREFETCHER             (32+2)\r
-#define CPU_FEATURE_ADJACENT_CACHE_LINE_PREFETCH    (32+3)\r
-#define CPU_FEATURE_DCU_PREFETCHER                  (32+4)\r
-#define CPU_FEATURE_IP_PREFETCHER                   (32+5)\r
-#define CPU_FEATURE_MLC_STREAMER_PREFETCHER         (32+6)\r
-#define CPU_FEATURE_MLC_SPATIAL_PREFETCHER          (32+7)\r
-#define CPU_FEATURE_THREE_STRIKE_COUNTER            (32+8)\r
-#define CPU_FEATURE_APIC_TPR_UPDATE_MESSAGE         (32+9)\r
-#define CPU_FEATURE_ENERGY_PERFORMANCE_BIAS         (32+10)\r
-#define CPU_FEATURE_PPIN                            (32+11)\r
-#define CPU_FEATURE_PROC_TRACE                      (32+12)\r
-\r
-#define CPU_FEATURE_BEFORE_ALL                      BIT23\r
-#define CPU_FEATURE_AFTER_ALL                       BIT24\r
-#define CPU_FEATURE_THREAD_BEFORE                   BIT25\r
-#define CPU_FEATURE_THREAD_AFTER                    BIT26\r
-#define CPU_FEATURE_CORE_BEFORE                     BIT27\r
-#define CPU_FEATURE_CORE_AFTER                      BIT28\r
-#define CPU_FEATURE_PACKAGE_BEFORE                  BIT29\r
-#define CPU_FEATURE_PACKAGE_AFTER                   BIT30\r
-#define CPU_FEATURE_END                             MAX_UINT32\r
+#define CPU_FEATURE_AESNI                          0\r
+#define CPU_FEATURE_TURBO_MODE                     1\r
+#define CPU_FEATURE_MWAIT                          2\r
+#define CPU_FEATURE_ACPI                           3\r
+#define CPU_FEATURE_EIST                           4\r
+#define CPU_FEATURE_RESERVED_5                     5\r
+#define CPU_FEATURE_FASTSTRINGS                    6\r
+#define CPU_FEATURE_VMX                            7\r
+#define CPU_FEATURE_SMX                            8\r
+#define CPU_FEATURE_LMCE                           9\r
+#define CPU_FEATURE_LOCK_FEATURE_CONTROL_REGISTER  10\r
+#define CPU_FEATURE_LIMIT_CPUID_MAX_VAL            11\r
+#define CPU_FEATURE_MCE                            12\r
+#define CPU_FEATURE_MCA                            13\r
+#define CPU_FEATURE_MCG_CTL                        14\r
+#define CPU_FEATURE_PENDING_BREAK                  15\r
+#define CPU_FEATURE_C1E                            16\r
+#define CPU_FEATURE_C1_AUTO_DEMOTION               17\r
+#define CPU_FEATURE_C3_AUTO_DEMOTION               18\r
+#define CPU_FEATURE_C1_UNDEMOTION                  19\r
+#define CPU_FEATURE_C3_UNDEMOTION                  20\r
+#define CPU_FEATURE_C_STATE                        21\r
+#define CPU_FEATURE_TM                             22\r
+#define CPU_FEATURE_TM2                            23\r
+#define CPU_FEATURE_X2APIC                         24\r
+#define CPU_FEATURE_RESERVED_25                    25\r
+#define CPU_FEATURE_RESERVED_26                    26\r
+#define CPU_FEATURE_RESERVED_27                    27\r
+#define CPU_FEATURE_RESERVED_28                    28\r
+#define CPU_FEATURE_RESERVED_29                    29\r
+#define CPU_FEATURE_RESERVED_30                    30\r
+#define CPU_FEATURE_RESERVED_31                    31\r
+\r
+#define CPU_FEATURE_L2_PREFETCHER                 (32+0)\r
+#define CPU_FEATURE_L1_DATA_PREFETCHER            (32+1)\r
+#define CPU_FEATURE_HARDWARE_PREFETCHER           (32+2)\r
+#define CPU_FEATURE_ADJACENT_CACHE_LINE_PREFETCH  (32+3)\r
+#define CPU_FEATURE_DCU_PREFETCHER                (32+4)\r
+#define CPU_FEATURE_IP_PREFETCHER                 (32+5)\r
+#define CPU_FEATURE_MLC_STREAMER_PREFETCHER       (32+6)\r
+#define CPU_FEATURE_MLC_SPATIAL_PREFETCHER        (32+7)\r
+#define CPU_FEATURE_THREE_STRIKE_COUNTER          (32+8)\r
+#define CPU_FEATURE_APIC_TPR_UPDATE_MESSAGE       (32+9)\r
+#define CPU_FEATURE_ENERGY_PERFORMANCE_BIAS       (32+10)\r
+#define CPU_FEATURE_PPIN                          (32+11)\r
+#define CPU_FEATURE_PROC_TRACE                    (32+12)\r
+\r
+#define CPU_FEATURE_BEFORE_ALL      BIT23\r
+#define CPU_FEATURE_AFTER_ALL       BIT24\r
+#define CPU_FEATURE_THREAD_BEFORE   BIT25\r
+#define CPU_FEATURE_THREAD_AFTER    BIT26\r
+#define CPU_FEATURE_CORE_BEFORE     BIT27\r
+#define CPU_FEATURE_CORE_AFTER      BIT28\r
+#define CPU_FEATURE_PACKAGE_BEFORE  BIT29\r
+#define CPU_FEATURE_PACKAGE_AFTER   BIT30\r
+#define CPU_FEATURE_END             MAX_UINT32\r
 /// @}\r
 \r
 ///\r
@@ -85,28 +85,28 @@ typedef struct {
   //\r
   // Set to 1 when current processor is the first thread in the core it resides in.\r
   //\r
-  UINT32 Thread   : 1;\r
+  UINT32    Thread   : 1;\r
   //\r
   // Set to 1 when current processor is a thread of the first core in the module it resides in.\r
   //\r
-  UINT32 Core     : 1;\r
+  UINT32    Core     : 1;\r
   //\r
   // Set to 1 when current processor is a thread of the first module in the tile it resides in.\r
   //\r
-  UINT32 Module   : 1;\r
+  UINT32    Module   : 1;\r
   //\r
   // Set to 1 when current processor is a thread of the first tile in the die it resides in.\r
   //\r
-  UINT32 Tile     : 1;\r
+  UINT32    Tile     : 1;\r
   //\r
   // Set to 1 when current processor is a thread of the first die in the package it resides in.\r
   //\r
-  UINT32 Die      : 1;\r
+  UINT32    Die      : 1;\r
   //\r
   // Set to 1 when current processor is a thread of the first package in the system.\r
   //\r
-  UINT32 Package  : 1;\r
-  UINT32 Reserved : 26;\r
+  UINT32    Package  : 1;\r
+  UINT32    Reserved : 26;\r
 } REGISTER_CPU_FEATURE_FIRST_PROCESSOR;\r
 \r
 ///\r
@@ -118,36 +118,36 @@ typedef struct {
   ///\r
   /// The package that the CPU resides\r
   ///\r
-  EFI_PROCESSOR_INFORMATION            ProcessorInfo;\r
+  EFI_PROCESSOR_INFORMATION               ProcessorInfo;\r
 \r
   ///\r
   /// The bit flag indicating whether the CPU is the first Thread/Core/Module/Tile/Die/Package in its parent scope.\r
   ///\r
-  REGISTER_CPU_FEATURE_FIRST_PROCESSOR First;\r
+  REGISTER_CPU_FEATURE_FIRST_PROCESSOR    First;\r
   ///\r
   /// The Display Family of the CPU computed from CPUID leaf CPUID_VERSION_INFO\r
   ///\r
-  UINT32                               DisplayFamily;\r
+  UINT32                                  DisplayFamily;\r
   ///\r
   /// The Display Model of the CPU computed from CPUID leaf CPUID_VERSION_INFO\r
   ///\r
-  UINT32                               DisplayModel;\r
+  UINT32                                  DisplayModel;\r
   ///\r
   /// The Stepping ID of the CPU computed from CPUID leaf CPUID_VERSION_INFO\r
   ///\r
-  UINT32                               SteppingId;\r
+  UINT32                                  SteppingId;\r
   ///\r
   /// The Processor Type of the CPU computed from CPUID leaf CPUID_VERSION_INFO\r
   ///\r
-  UINT32                               ProcessorType;\r
+  UINT32                                  ProcessorType;\r
   ///\r
   /// Bit field structured returned in ECX from CPUID leaf CPUID_VERSION_INFO\r
   ///\r
-  CPUID_VERSION_INFO_ECX               CpuIdVersionInfoEcx;\r
+  CPUID_VERSION_INFO_ECX                  CpuIdVersionInfoEcx;\r
   ///\r
   /// Bit field structured returned in EDX from CPUID leaf CPUID_VERSION_INFO\r
   ///\r
-  CPUID_VERSION_INFO_EDX               CpuIdVersionInfoEdx;\r
+  CPUID_VERSION_INFO_EDX                  CpuIdVersionInfoEdx;\r
 } REGISTER_CPU_FEATURE_INFORMATION;\r
 \r
 /**\r
@@ -167,7 +167,7 @@ typedef struct {
 BOOLEAN\r
 EFIAPI\r
 IsCpuFeatureSupported (\r
-  IN UINT32              Feature\r
+  IN UINT32  Feature\r
   );\r
 \r
 /**\r
@@ -184,7 +184,7 @@ IsCpuFeatureSupported (
 BOOLEAN\r
 EFIAPI\r
 IsCpuFeatureInSetting (\r
-  IN UINT32              Feature\r
+  IN UINT32  Feature\r
   );\r
 \r
 /**\r
@@ -303,10 +303,10 @@ RETURN_STATUS
 RETURN_STATUS\r
 EFIAPI\r
 RegisterCpuFeature (\r
-  IN CHAR8                             *FeatureName        OPTIONAL,\r
-  IN CPU_FEATURE_GET_CONFIG_DATA       GetConfigDataFunc   OPTIONAL,\r
-  IN CPU_FEATURE_SUPPORT               SupportFunc         OPTIONAL,\r
-  IN CPU_FEATURE_INITIALIZE            InitializeFunc      OPTIONAL,\r
+  IN CHAR8                        *FeatureName        OPTIONAL,\r
+  IN CPU_FEATURE_GET_CONFIG_DATA  GetConfigDataFunc   OPTIONAL,\r
+  IN CPU_FEATURE_SUPPORT          SupportFunc         OPTIONAL,\r
+  IN CPU_FEATURE_INITIALIZE       InitializeFunc      OPTIONAL,\r
   ...\r
   );\r
 \r
@@ -348,7 +348,7 @@ CpuFeaturesInitialize (
 VOID\r
 EFIAPI\r
 SwitchBspAfterFeaturesInitialize (\r
-  IN UINTN               ProcessorNumber\r
+  IN UINTN  ProcessorNumber\r
   );\r
 \r
 /**\r
@@ -368,11 +368,11 @@ SwitchBspAfterFeaturesInitialize (
 VOID\r
 EFIAPI\r
 CpuRegisterTableWrite (\r
-  IN UINTN               ProcessorNumber,\r
-  IN REGISTER_TYPE       RegisterType,\r
-  IN UINT64              Index,\r
-  IN UINT64              ValueMask,\r
-  IN UINT64              Value\r
+  IN UINTN          ProcessorNumber,\r
+  IN REGISTER_TYPE  RegisterType,\r
+  IN UINT64         Index,\r
+  IN UINT64         ValueMask,\r
+  IN UINT64         Value\r
   );\r
 \r
 /**\r
@@ -394,11 +394,11 @@ CpuRegisterTableWrite (
 VOID\r
 EFIAPI\r
 CpuRegisterTableTestThenWrite (\r
-  IN UINTN               ProcessorNumber,\r
-  IN REGISTER_TYPE       RegisterType,\r
-  IN UINT64              Index,\r
-  IN UINT64              ValueMask,\r
-  IN UINT64              Value\r
+  IN UINTN          ProcessorNumber,\r
+  IN REGISTER_TYPE  RegisterType,\r
+  IN UINT64         Index,\r
+  IN UINT64         ValueMask,\r
+  IN UINT64         Value\r
   );\r
 \r
 /**\r
@@ -418,11 +418,11 @@ CpuRegisterTableTestThenWrite (
 VOID\r
 EFIAPI\r
 PreSmmCpuRegisterTableWrite (\r
-  IN UINTN               ProcessorNumber,\r
-  IN REGISTER_TYPE       RegisterType,\r
-  IN UINT64              Index,\r
-  IN UINT64              ValueMask,\r
-  IN UINT64              Value\r
+  IN UINTN          ProcessorNumber,\r
+  IN REGISTER_TYPE  RegisterType,\r
+  IN UINT64         Index,\r
+  IN UINT64         ValueMask,\r
+  IN UINT64         Value\r
   );\r
 \r
 /**\r

diff --git a/UefiCpuPkg/Include/Library/SmmCpuFeaturesLib.h b/UefiCpuPkg/Include/Library/SmmCpuFeaturesLib.h
index dbcd57e0ad42dc0758407dcd57d4ddc143db8b6c..54cae865a28ea686c1ac46949986535e4129e03f 100644 (file)
--- a/UefiCpuPkg/Include/Library/SmmCpuFeaturesLib.h
+++ b/UefiCpuPkg/Include/Library/SmmCpuFeaturesLib.h
@@ -408,7 +408,7 @@ SmmCpuFeaturesCompleteSmmReadyToLock (
 VOID *\r
 EFIAPI\r
 SmmCpuFeaturesAllocatePageTableMemory (\r
-  IN UINTN           Pages\r
+  IN UINTN  Pages\r
   );\r
 \r
 #endif\r

diff --git a/UefiCpuPkg/Include/Library/SmmCpuPlatformHookLib.h b/UefiCpuPkg/Include/Library/SmmCpuPlatformHookLib.h
index fdb756de9db7e90a29384f3203611be2d7390be8..f9cc3f7249e8490269a41eb38d10ad58e0c34d05 100644 (file)
--- a/UefiCpuPkg/Include/Library/SmmCpuPlatformHookLib.h
+++ b/UefiCpuPkg/Include/Library/SmmCpuPlatformHookLib.h
@@ -13,10 +13,10 @@
 /// SMM Page Size Type\r
 ///\r
 typedef enum {\r
-    SmmPageSize4K,\r
-    SmmPageSize2M,\r
-    SmmPageSize1G,\r
-    MaxSmmPageSizeType\r
+  SmmPageSize4K,\r
+  SmmPageSize2M,\r
+  SmmPageSize1G,\r
+  MaxSmmPageSizeType\r
 } SMM_PAGE_SIZE_TYPE;\r
 \r
 /**\r
@@ -74,7 +74,7 @@ ClearTopLevelSmiStatus (
 EFI_STATUS\r
 EFIAPI\r
 PlatformSmmBspElection (\r
-  OUT BOOLEAN     *IsBsp\r
+  OUT BOOLEAN  *IsBsp\r
   );\r
 \r
 /**\r
@@ -94,10 +94,10 @@ PlatformSmmBspElection (
 EFI_STATUS\r
 EFIAPI\r
 GetPlatformPageTableAttribute (\r
-  IN  UINT64                Address,\r
-  OUT SMM_PAGE_SIZE_TYPE    *PageSize,\r
-  OUT UINTN                 *NumOfPages,\r
-  OUT UINTN                 *PageAttribute\r
+  IN  UINT64              Address,\r
+  OUT SMM_PAGE_SIZE_TYPE  *PageSize,\r
+  OUT UINTN               *NumOfPages,\r
+  OUT UINTN               *PageAttribute\r
   );\r
 \r
 #endif\r

diff --git a/UefiCpuPkg/Include/Library/UefiCpuLib.h b/UefiCpuPkg/Include/Library/UefiCpuLib.h
index 092c1d2116c3bbf54c88447d016acc37d543b449..0ff4a35774c15ce7ddc72b248eca4f1f2fb7e68b 100644 (file)
--- a/UefiCpuPkg/Include/Library/UefiCpuLib.h
+++ b/UefiCpuPkg/Include/Library/UefiCpuLib.h
@@ -13,8 +13,6 @@
 #ifndef __UEFI_CPU_LIB_H__\r
 #define __UEFI_CPU_LIB_H__\r
 \r
-\r
-\r
 /**\r
   Initializes floating point units for requirement of UEFI specification.\r
 \r

diff --git a/UefiCpuPkg/Include/Library/VmgExitLib.h b/UefiCpuPkg/Include/Library/VmgExitLib.h
index 061948cf840df0b88beeafe8c90bc34238db7544..ebda1c3d907c9028165f8a529ca7fd9edde9625e 100644 (file)
--- a/UefiCpuPkg/Include/Library/VmgExitLib.h
+++ b/UefiCpuPkg/Include/Library/VmgExitLib.h
@@ -15,7 +15,6 @@
 #include <Protocol/DebugSupport.h>\r
 #include <Register/Amd/Ghcb.h>\r
 \r
-\r
 /**\r
   Perform VMGEXIT.\r
 \r
@@ -38,10 +37,10 @@
 UINT64\r
 EFIAPI\r
 VmgExit (\r
-  IN OUT GHCB                *Ghcb,\r
-  IN     UINT64              ExitCode,\r
-  IN     UINT64              ExitInfo1,\r
-  IN     UINT64              ExitInfo2\r
+  IN OUT GHCB    *Ghcb,\r
+  IN     UINT64  ExitCode,\r
+  IN     UINT64  ExitInfo1,\r
+  IN     UINT64  ExitInfo2\r
   );\r
 \r
 /**\r
@@ -58,8 +57,8 @@ VmgExit (
 VOID\r
 EFIAPI\r
 VmgInit (\r
-  IN OUT GHCB                *Ghcb,\r
-  IN OUT BOOLEAN             *InterruptState\r
+  IN OUT GHCB     *Ghcb,\r
+  IN OUT BOOLEAN  *InterruptState\r
   );\r
 \r
 /**\r
@@ -76,8 +75,8 @@ VmgInit (
 VOID\r
 EFIAPI\r
 VmgDone (\r
-  IN OUT GHCB                *Ghcb,\r
-  IN     BOOLEAN             InterruptState\r
+  IN OUT GHCB     *Ghcb,\r
+  IN     BOOLEAN  InterruptState\r
   );\r
 \r
 /**\r
@@ -93,8 +92,8 @@ VmgDone (
 VOID\r
 EFIAPI\r
 VmgSetOffsetValid (\r
-  IN OUT GHCB                *Ghcb,\r
-  IN     GHCB_REGISTER       Offset\r
+  IN OUT GHCB           *Ghcb,\r
+  IN     GHCB_REGISTER  Offset\r
   );\r
 \r
 /**\r
@@ -113,8 +112,8 @@ VmgSetOffsetValid (
 BOOLEAN\r
 EFIAPI\r
 VmgIsOffsetValid (\r
-  IN GHCB                    *Ghcb,\r
-  IN GHCB_REGISTER           Offset\r
+  IN GHCB           *Ghcb,\r
+  IN GHCB_REGISTER  Offset\r
   );\r
 \r
 /**\r

diff --git a/UefiCpuPkg/Include/Ppi/MpServices2.h b/UefiCpuPkg/Include/Ppi/MpServices2.h
index 3e224ed99521d7daf5a2b50033b4e95ef7fd60a0..36feac5237e3793cf169934af0967042a1dfa409 100644 (file)
--- a/UefiCpuPkg/Include/Ppi/MpServices2.h
+++ b/UefiCpuPkg/Include/Ppi/MpServices2.h
@@ -16,7 +16,7 @@
     0x5cb9cb3d, 0x31a4, 0x480c, { 0x94, 0x98, 0x29, 0xd2, 0x69, 0xba, 0xcf, 0xba} \\r
   }\r
 \r
-typedef struct _EDKII_PEI_MP_SERVICES2_PPI  EDKII_PEI_MP_SERVICES2_PPI;\r
+typedef struct _EDKII_PEI_MP_SERVICES2_PPI EDKII_PEI_MP_SERVICES2_PPI;\r
 \r
 /**\r
   Get the number of CPU's.\r
@@ -35,7 +35,7 @@ typedef struct _EDKII_PEI_MP_SERVICES2_PPI  EDKII_PEI_MP_SERVICES2_PPI;
 **/\r
 typedef\r
 EFI_STATUS\r
-(EFIAPI *EDKII_PEI_MP_SERVICES_GET_NUMBER_OF_PROCESSORS) (\r
+(EFIAPI *EDKII_PEI_MP_SERVICES_GET_NUMBER_OF_PROCESSORS)(\r
   IN  EDKII_PEI_MP_SERVICES2_PPI     *This,\r
   OUT UINTN                          *NumberOfProcessors,\r
   OUT UINTN                          *NumberOfEnabledProcessors\r
@@ -57,7 +57,7 @@ EFI_STATUS
 **/\r
 typedef\r
 EFI_STATUS\r
-(EFIAPI *EDKII_PEI_MP_SERVICES_GET_PROCESSOR_INFO) (\r
+(EFIAPI *EDKII_PEI_MP_SERVICES_GET_PROCESSOR_INFO)(\r
   IN  EDKII_PEI_MP_SERVICES2_PPI     *This,\r
   IN  UINTN                          ProcessorNumber,\r
   OUT EFI_PROCESSOR_INFORMATION     *ProcessorInfoBuffer\r
@@ -97,7 +97,7 @@ EFI_STATUS
 **/\r
 typedef\r
 EFI_STATUS\r
-(EFIAPI *EDKII_PEI_MP_SERVICES_STARTUP_ALL_APS) (\r
+(EFIAPI *EDKII_PEI_MP_SERVICES_STARTUP_ALL_APS)(\r
   IN  EDKII_PEI_MP_SERVICES2_PPI     *This,\r
   IN  EFI_AP_PROCEDURE               Procedure,\r
   IN  BOOLEAN                        SingleThread,\r
@@ -139,7 +139,7 @@ EFI_STATUS
 **/\r
 typedef\r
 EFI_STATUS\r
-(EFIAPI *EDKII_PEI_MP_SERVICES_STARTUP_THIS_AP) (\r
+(EFIAPI *EDKII_PEI_MP_SERVICES_STARTUP_THIS_AP)(\r
   IN  EDKII_PEI_MP_SERVICES2_PPI     *This,\r
   IN  EFI_AP_PROCEDURE               Procedure,\r
   IN  UINTN                          ProcessorNumber,\r
@@ -171,7 +171,7 @@ EFI_STATUS
 **/\r
 typedef\r
 EFI_STATUS\r
-(EFIAPI *EDKII_PEI_MP_SERVICES_SWITCH_BSP) (\r
+(EFIAPI *EDKII_PEI_MP_SERVICES_SWITCH_BSP)(\r
   IN  EDKII_PEI_MP_SERVICES2_PPI     *This,\r
   IN  UINTN                          ProcessorNumber,\r
   IN  BOOLEAN                        EnableOldBSP\r
@@ -205,7 +205,7 @@ EFI_STATUS
 **/\r
 typedef\r
 EFI_STATUS\r
-(EFIAPI *EDKII_PEI_MP_SERVICES_ENABLEDISABLEAP) (\r
+(EFIAPI *EDKII_PEI_MP_SERVICES_ENABLEDISABLEAP)(\r
   IN  EDKII_PEI_MP_SERVICES2_PPI     *This,\r
   IN  UINTN                          ProcessorNumber,\r
   IN  BOOLEAN                        EnableAP,\r
@@ -227,12 +227,11 @@ EFI_STATUS
 **/\r
 typedef\r
 EFI_STATUS\r
-(EFIAPI *EDKII_PEI_MP_SERVICES_WHOAMI) (\r
+(EFIAPI *EDKII_PEI_MP_SERVICES_WHOAMI)(\r
   IN  EDKII_PEI_MP_SERVICES2_PPI     *This,\r
   OUT UINTN                          *ProcessorNumber\r
   );\r
 \r
-\r
 /**\r
   Activate all of the application proessors.\r
 \r
@@ -256,7 +255,7 @@ EFI_STATUS
 **/\r
 typedef\r
 EFI_STATUS\r
-(EFIAPI *EDKII_PEI_MP_SERVICES_STARTUP_ALL_CPUS) (\r
+(EFIAPI *EDKII_PEI_MP_SERVICES_STARTUP_ALL_CPUS)(\r
   IN  EDKII_PEI_MP_SERVICES2_PPI     *This,\r
   IN  EFI_AP_PROCEDURE               Procedure,\r
   IN  UINTN                          TimeoutInMicroSeconds,\r
@@ -264,16 +263,16 @@ EFI_STATUS
   );\r
 \r
 struct _EDKII_PEI_MP_SERVICES2_PPI {\r
-  EDKII_PEI_MP_SERVICES_GET_NUMBER_OF_PROCESSORS  GetNumberOfProcessors;\r
-  EDKII_PEI_MP_SERVICES_GET_PROCESSOR_INFO        GetProcessorInfo;\r
-  EDKII_PEI_MP_SERVICES_STARTUP_ALL_APS           StartupAllAPs;\r
-  EDKII_PEI_MP_SERVICES_STARTUP_THIS_AP           StartupThisAP;\r
-  EDKII_PEI_MP_SERVICES_SWITCH_BSP                SwitchBSP;\r
-  EDKII_PEI_MP_SERVICES_ENABLEDISABLEAP           EnableDisableAP;\r
-  EDKII_PEI_MP_SERVICES_WHOAMI                    WhoAmI;\r
-  EDKII_PEI_MP_SERVICES_STARTUP_ALL_CPUS          StartupAllCPUs;\r
+  EDKII_PEI_MP_SERVICES_GET_NUMBER_OF_PROCESSORS    GetNumberOfProcessors;\r
+  EDKII_PEI_MP_SERVICES_GET_PROCESSOR_INFO          GetProcessorInfo;\r
+  EDKII_PEI_MP_SERVICES_STARTUP_ALL_APS             StartupAllAPs;\r
+  EDKII_PEI_MP_SERVICES_STARTUP_THIS_AP             StartupThisAP;\r
+  EDKII_PEI_MP_SERVICES_SWITCH_BSP                  SwitchBSP;\r
+  EDKII_PEI_MP_SERVICES_ENABLEDISABLEAP             EnableDisableAP;\r
+  EDKII_PEI_MP_SERVICES_WHOAMI                      WhoAmI;\r
+  EDKII_PEI_MP_SERVICES_STARTUP_ALL_CPUS            StartupAllCPUs;\r
 };\r
 \r
-extern EFI_GUID gEdkiiPeiMpServices2PpiGuid;\r
+extern EFI_GUID  gEdkiiPeiMpServices2PpiGuid;\r
 \r
 #endif\r

diff --git a/UefiCpuPkg/Include/Ppi/RepublishSecPpi.h b/UefiCpuPkg/Include/Ppi/RepublishSecPpi.h
index ea865acbb5c846b13d91f17a2d577aa50671f497..2ea99394a9b1dfae97dea680bf74fe32d398007b 100644 (file)
--- a/UefiCpuPkg/Include/Ppi/RepublishSecPpi.h
+++ b/UefiCpuPkg/Include/Ppi/RepublishSecPpi.h
@@ -46,9 +46,9 @@ EFI_STATUS
 /// Republish SEC PPIs\r
 ///\r
 struct _REPUBLISH_SEC_PPI_PPI {\r
-  REPUBLISH_SEC_PPI_REPUBLISH_SEC_PPIS  RepublishSecPpis;\r
+  REPUBLISH_SEC_PPI_REPUBLISH_SEC_PPIS    RepublishSecPpis;\r
 };\r
 \r
-extern EFI_GUID gRepublishSecPpiPpiGuid;\r
+extern EFI_GUID  gRepublishSecPpiPpiGuid;\r
 \r
 #endif\r

diff --git a/UefiCpuPkg/Include/Ppi/ShadowMicrocode.h b/UefiCpuPkg/Include/Ppi/ShadowMicrocode.h
index be48965422d9fde32a508581a5a3e43dc6b0d164..ee20e30414b384c5749c0f672de3e7c58ccfb87e 100644 (file)
--- a/UefiCpuPkg/Include/Ppi/ShadowMicrocode.h
+++ b/UefiCpuPkg/Include/Ppi/ShadowMicrocode.h
@@ -14,11 +14,11 @@
     0x430f6965, 0x9a69, 0x41c5, { 0x93, 0xed, 0x8b, 0xf0, 0x64, 0x35, 0xc1, 0xc6 } \\r
   }\r
 \r
-typedef struct _EDKII_PEI_SHADOW_MICROCODE_PPI  EDKII_PEI_SHADOW_MICROCODE_PPI;\r
+typedef struct _EDKII_PEI_SHADOW_MICROCODE_PPI EDKII_PEI_SHADOW_MICROCODE_PPI;\r
 \r
 typedef struct {\r
-  UINT32         ProcessorSignature;\r
-  UINT8          PlatformId;\r
+  UINT32    ProcessorSignature;\r
+  UINT8     PlatformId;\r
 } EDKII_PEI_MICROCODE_CPU_ID;\r
 \r
 /**\r
@@ -44,7 +44,7 @@ typedef struct {
 **/\r
 typedef\r
 EFI_STATUS\r
-(EFIAPI *EDKII_PEI_SHADOW_MICROCODE) (\r
+(EFIAPI *EDKII_PEI_SHADOW_MICROCODE)(\r
   IN  EDKII_PEI_SHADOW_MICROCODE_PPI        *This,\r
   IN  UINTN                                 CpuIdCount,\r
   IN  EDKII_PEI_MICROCODE_CPU_ID            *MicrocodeCpuId,\r
@@ -57,10 +57,9 @@ EFI_STATUS
 /// abstracts handling microcode shadow support.\r
 ///\r
 struct _EDKII_PEI_SHADOW_MICROCODE_PPI {\r
-  EDKII_PEI_SHADOW_MICROCODE          ShadowMicrocode;\r
+  EDKII_PEI_SHADOW_MICROCODE    ShadowMicrocode;\r
 };\r
 \r
-extern EFI_GUID gEdkiiPeiShadowMicrocodePpiGuid;\r
+extern EFI_GUID  gEdkiiPeiShadowMicrocodePpiGuid;\r
 \r
 #endif\r
-\r

diff --git a/UefiCpuPkg/Include/Protocol/SmMonitorInit.h b/UefiCpuPkg/Include/Protocol/SmMonitorInit.h
index db2ce11f1e093d59f041e697cec06178f4ab3d7f..0f77897e03ff04d8e5b371dcfd972b0804c86831 100644 (file)
--- a/UefiCpuPkg/Include/Protocol/SmMonitorInit.h
+++ b/UefiCpuPkg/Include/Protocol/SmMonitorInit.h
@@ -34,7 +34,7 @@
 **/\r
 typedef\r
 EFI_STATUS\r
-(EFIAPI *EFI_SM_MONITOR_LOAD_MONITOR) (\r
+(EFIAPI *EFI_SM_MONITOR_LOAD_MONITOR)(\r
   IN EFI_PHYSICAL_ADDRESS StmImage,\r
   IN UINTN                StmImageSize\r
   );\r
@@ -54,7 +54,7 @@ EFI_STATUS
 **/\r
 typedef\r
 EFI_STATUS\r
-(EFIAPI *EFI_SM_MONITOR_ADD_PI_RESOURCE) (\r
+(EFIAPI *EFI_SM_MONITOR_ADD_PI_RESOURCE)(\r
   IN STM_RSC *ResourceList,\r
   IN UINT32   NumEntries OPTIONAL\r
   );\r
@@ -74,7 +74,7 @@ EFI_STATUS
 **/\r
 typedef\r
 EFI_STATUS\r
-(EFIAPI *EFI_SM_MONITOR_DELETE_PI_RESOURCE) (\r
+(EFIAPI *EFI_SM_MONITOR_DELETE_PI_RESOURCE)(\r
   IN STM_RSC *ResourceList OPTIONAL,\r
   IN UINT32   NumEntries OPTIONAL\r
   );\r
@@ -94,14 +94,14 @@ EFI_STATUS
 **/\r
 typedef\r
 EFI_STATUS\r
-(EFIAPI *EFI_SM_MONITOR_GET_PI_RESOURCE) (\r
+(EFIAPI *EFI_SM_MONITOR_GET_PI_RESOURCE)(\r
   OUT    STM_RSC *ResourceList,\r
   IN OUT UINT32  *ResourceSize\r
   );\r
 \r
 typedef UINT32 EFI_SM_MONITOR_STATE;\r
-#define EFI_SM_MONITOR_STATE_ENABLED     0x1\r
-#define EFI_SM_MONITOR_STATE_ACTIVATED   0x2\r
+#define EFI_SM_MONITOR_STATE_ENABLED    0x1\r
+#define EFI_SM_MONITOR_STATE_ACTIVATED  0x2\r
 \r
 /**\r
 \r
@@ -112,7 +112,7 @@ typedef UINT32 EFI_SM_MONITOR_STATE;
 **/\r
 typedef\r
 EFI_SM_MONITOR_STATE\r
-(EFIAPI *EFI_SM_MONITOR_GET_MONITOR_STATE) (\r
+(EFIAPI *EFI_SM_MONITOR_GET_MONITOR_STATE)(\r
   VOID\r
   );\r
 \r
@@ -120,16 +120,16 @@ typedef struct _EFI_SM_MONITOR_INIT_PROTOCOL {
   //\r
   // Valid at boot-time only\r
   //\r
-  EFI_SM_MONITOR_LOAD_MONITOR                      LoadMonitor;\r
-  EFI_SM_MONITOR_ADD_PI_RESOURCE                   AddPiResource;\r
-  EFI_SM_MONITOR_DELETE_PI_RESOURCE                DeletePiResource;\r
-  EFI_SM_MONITOR_GET_PI_RESOURCE                   GetPiResource;\r
+  EFI_SM_MONITOR_LOAD_MONITOR          LoadMonitor;\r
+  EFI_SM_MONITOR_ADD_PI_RESOURCE       AddPiResource;\r
+  EFI_SM_MONITOR_DELETE_PI_RESOURCE    DeletePiResource;\r
+  EFI_SM_MONITOR_GET_PI_RESOURCE       GetPiResource;\r
   //\r
   // Valid at runtime\r
   //\r
-  EFI_SM_MONITOR_GET_MONITOR_STATE                 GetMonitorState;\r
+  EFI_SM_MONITOR_GET_MONITOR_STATE     GetMonitorState;\r
 } EFI_SM_MONITOR_INIT_PROTOCOL;\r
 \r
-extern EFI_GUID gEfiSmMonitorInitProtocolGuid;\r
+extern EFI_GUID  gEfiSmMonitorInitProtocolGuid;\r
 \r
 #endif\r

diff --git a/UefiCpuPkg/Include/Protocol/SmmCpuService.h b/UefiCpuPkg/Include/Protocol/SmmCpuService.h
index 13ba1feeba6b92687ba77e6ba7f9c05badb9d9f9..952767afce755ddfa22906ec443052b94b38d5a7 100644 (file)
--- a/UefiCpuPkg/Include/Protocol/SmmCpuService.h
+++ b/UefiCpuPkg/Include/Protocol/SmmCpuService.h
@@ -44,7 +44,7 @@ typedef struct _EFI_SMM_CPU_SERVICE_PROTOCOL EFI_SMM_CPU_SERVICE_PROTOCOL;
 **/\r
 typedef\r
 EFI_STATUS\r
-(EFIAPI * EFI_SMM_GET_PROCESSOR_INFO) (\r
+(EFIAPI *EFI_SMM_GET_PROCESSOR_INFO)(\r
   IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL *This,\r
   IN       UINTN                        ProcessorNumber,\r
   OUT      EFI_PROCESSOR_INFORMATION    *ProcessorInfoBuffer\r
@@ -82,7 +82,7 @@ EFI_STATUS
 **/\r
 typedef\r
 EFI_STATUS\r
-(EFIAPI * EFI_SMM_SWITCH_BSP) (\r
+(EFIAPI *EFI_SMM_SWITCH_BSP)(\r
   IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL *This,\r
   IN       UINTN                        ProcessorNumber\r
   );\r
@@ -106,7 +106,7 @@ EFI_STATUS
 **/\r
 typedef\r
 EFI_STATUS\r
-(EFIAPI *EFI_SMM_ADD_PROCESSOR) (\r
+(EFIAPI *EFI_SMM_ADD_PROCESSOR)(\r
   IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL  *This,\r
   IN       UINT64                        ProcessorId,\r
   OUT      UINTN                         *ProcessorNumber\r
@@ -128,7 +128,7 @@ EFI_STATUS
 **/\r
 typedef\r
 EFI_STATUS\r
-(EFIAPI *EFI_SMM_REMOVE_PROCESSOR) (\r
+(EFIAPI *EFI_SMM_REMOVE_PROCESSOR)(\r
   IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL  *This,\r
   IN       UINTN                         ProcessorNumber\r
   );\r
@@ -156,7 +156,7 @@ EFI_STATUS
 **/\r
 typedef\r
 EFI_STATUS\r
-(EFIAPI * EFI_SMM_WHOAMI) (\r
+(EFIAPI *EFI_SMM_WHOAMI)(\r
   IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL *This,\r
   OUT      UINTN                        *ProcessorNumber\r
   );\r
@@ -180,7 +180,7 @@ EFI_STATUS
 **/\r
 typedef\r
 EFI_STATUS\r
-(EFIAPI *EFI_SMM_REGISTER_EXCEPTION_HANDLER) (\r
+(EFIAPI *EFI_SMM_REGISTER_EXCEPTION_HANDLER)(\r
   IN EFI_SMM_CPU_SERVICE_PROTOCOL  *This,\r
   IN EFI_EXCEPTION_TYPE            ExceptionType,\r
   IN EFI_CPU_INTERRUPT_HANDLER     InterruptHandler\r
@@ -190,14 +190,14 @@ EFI_STATUS
 //  This protocol provides CPU services from SMM.\r
 //\r
 struct _EFI_SMM_CPU_SERVICE_PROTOCOL {\r
-  EFI_SMM_GET_PROCESSOR_INFO          GetProcessorInfo;\r
-  EFI_SMM_SWITCH_BSP                  SwitchBsp;\r
-  EFI_SMM_ADD_PROCESSOR               AddProcessor;\r
-  EFI_SMM_REMOVE_PROCESSOR            RemoveProcessor;\r
-  EFI_SMM_WHOAMI                      WhoAmI;\r
-  EFI_SMM_REGISTER_EXCEPTION_HANDLER  RegisterExceptionHandler;\r
+  EFI_SMM_GET_PROCESSOR_INFO            GetProcessorInfo;\r
+  EFI_SMM_SWITCH_BSP                    SwitchBsp;\r
+  EFI_SMM_ADD_PROCESSOR                 AddProcessor;\r
+  EFI_SMM_REMOVE_PROCESSOR              RemoveProcessor;\r
+  EFI_SMM_WHOAMI                        WhoAmI;\r
+  EFI_SMM_REGISTER_EXCEPTION_HANDLER    RegisterExceptionHandler;\r
 };\r
 \r
-extern EFI_GUID gEfiSmmCpuServiceProtocolGuid;\r
+extern EFI_GUID  gEfiSmmCpuServiceProtocolGuid;\r
 \r
 #endif\r

diff --git a/UefiCpuPkg/Include/Register/LocalApic.h b/UefiCpuPkg/Include/Register/LocalApic.h
index 689c8257772394a008b4c9521f5562062dd5089b..55498ce3ea10d208e66f1938f798be3d3df3693b 100644 (file)
--- a/UefiCpuPkg/Include/Register/LocalApic.h
+++ b/UefiCpuPkg/Include/Register/LocalApic.h
@@ -11,4 +11,3 @@
 #include <Register/Intel/LocalApic.h>\r
 \r
 #endif\r
-\r

diff --git a/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.c b/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.c
index 50891618c458b3ca8c651577e817ac89aa3fcbb9..5d925bc273f8f6c1ff0d989143a84a34fcd86518 100644 (file)
--- a/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.c
+++ b/UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.c
@@ -77,5 +77,5 @@ GetCpuSteppingId (
 \r
   AsmCpuid (CPUID_VERSION_INFO, &Eax.Uint32, NULL, NULL, NULL);\r
 \r
-  return (UINT8) Eax.Bits.SteppingId;\r
+  return (UINT8)Eax.Bits.SteppingId;\r
 }\r

diff --git a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
index 7b4e730f984f443c2efd043df62174e925c80451..f9e06b2fca4588c11808a8e85f5c9f2772f5d32b 100644 (file)
--- a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
+++ b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
@@ -44,13 +44,14 @@ LocalApicBaseAddressMsrSupported (
 \r
   AsmCpuid (1, &RegEax, NULL, NULL, NULL);\r
   FamilyId = BitFieldRead32 (RegEax, 8, 11);\r
-  if (FamilyId == 0x04 || FamilyId == 0x05) {\r
+  if ((FamilyId == 0x04) || (FamilyId == 0x05)) {\r
     //\r
     // CPUs with a FamilyId of 0x04 or 0x05 do not support the\r
     // Local APIC Base Address MSR\r
     //\r
     return FALSE;\r
   }\r
+\r
   return TRUE;\r
 }\r
 \r
@@ -78,8 +79,8 @@ GetLocalApicBaseAddress (
 \r
   ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);\r
 \r
-  return (UINTN)(LShiftU64 ((UINT64) ApicBaseMsr.Bits.ApicBaseHi, 32)) +\r
-           (((UINTN)ApicBaseMsr.Bits.ApicBase) << 12);\r
+  return (UINTN)(LShiftU64 ((UINT64)ApicBaseMsr.Bits.ApicBaseHi, 32)) +\r
+         (((UINTN)ApicBaseMsr.Bits.ApicBase) << 12);\r
 }\r
 \r
 /**\r
@@ -93,7 +94,7 @@ GetLocalApicBaseAddress (
 VOID\r
 EFIAPI\r
 SetLocalApicBaseAddress (\r
-  IN UINTN                BaseAddress\r
+  IN UINTN  BaseAddress\r
   )\r
 {\r
   MSR_IA32_APIC_BASE_REGISTER  ApicBaseMsr;\r
@@ -109,8 +110,8 @@ SetLocalApicBaseAddress (
 \r
   ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);\r
 \r
-  ApicBaseMsr.Bits.ApicBase   = (UINT32) (BaseAddress >> 12);\r
-  ApicBaseMsr.Bits.ApicBaseHi = (UINT32) (RShiftU64((UINT64) BaseAddress, 32));\r
+  ApicBaseMsr.Bits.ApicBase   = (UINT32)(BaseAddress >> 12);\r
+  ApicBaseMsr.Bits.ApicBaseHi = (UINT32)(RShiftU64 ((UINT64)BaseAddress, 32));\r
 \r
   AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64);\r
 }\r
@@ -137,7 +138,7 @@ ReadLocalApicReg (
   ASSERT ((MmioOffset & 0xf) == 0);\r
   ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);\r
 \r
-  return MmioRead32 (GetLocalApicBaseAddress() + MmioOffset);\r
+  return MmioRead32 (GetLocalApicBaseAddress () + MmioOffset);\r
 }\r
 \r
 /**\r
@@ -157,14 +158,14 @@ ReadLocalApicReg (
 VOID\r
 EFIAPI\r
 WriteLocalApicReg (\r
-  IN UINTN  MmioOffset,\r
-  IN UINT32 Value\r
+  IN UINTN   MmioOffset,\r
+  IN UINT32  Value\r
   )\r
 {\r
   ASSERT ((MmioOffset & 0xf) == 0);\r
   ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);\r
 \r
-  MmioWrite32 (GetLocalApicBaseAddress() + MmioOffset, Value);\r
+  MmioWrite32 (GetLocalApicBaseAddress () + MmioOffset, Value);\r
 }\r
 \r
 /**\r
@@ -177,13 +178,13 @@ WriteLocalApicReg (
 **/\r
 VOID\r
 SendIpi (\r
-  IN UINT32          IcrLow,\r
-  IN UINT32          ApicId\r
+  IN UINT32  IcrLow,\r
+  IN UINT32  ApicId\r
   )\r
 {\r
-  LOCAL_APIC_ICR_LOW IcrLowReg;\r
-  UINT32             IcrHigh;\r
-  BOOLEAN            InterruptState;\r
+  LOCAL_APIC_ICR_LOW  IcrLowReg;\r
+  UINT32              IcrHigh;\r
+  BOOLEAN             InterruptState;\r
 \r
   ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);\r
   ASSERT (ApicId <= 0xff);\r
@@ -222,7 +223,6 @@ SendIpi (
   WriteLocalApicReg (XAPIC_ICR_HIGH_OFFSET, IcrHigh);\r
 \r
   SetInterruptState (InterruptState);\r
-\r
 }\r
 \r
 //\r
@@ -244,21 +244,21 @@ GetApicMode (
   )\r
 {\r
   DEBUG_CODE_BEGIN ();\r
-    {\r
-      MSR_IA32_APIC_BASE_REGISTER  ApicBaseMsr;\r
+  {\r
+    MSR_IA32_APIC_BASE_REGISTER  ApicBaseMsr;\r
 \r
+    //\r
+    // Check to see if the CPU supports the APIC Base Address MSR\r
+    //\r
+    if (LocalApicBaseAddressMsrSupported ()) {\r
+      ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);\r
       //\r
-      // Check to see if the CPU supports the APIC Base Address MSR\r
+      // Local APIC should have been enabled\r
       //\r
-      if (LocalApicBaseAddressMsrSupported ()) {\r
-        ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);\r
-        //\r
-        // Local APIC should have been enabled\r
-        //\r
-        ASSERT (ApicBaseMsr.Bits.EN != 0);\r
-        ASSERT (ApicBaseMsr.Bits.EXTD == 0);\r
-      }\r
+      ASSERT (ApicBaseMsr.Bits.EN != 0);\r
+      ASSERT (ApicBaseMsr.Bits.EXTD == 0);\r
     }\r
+  }\r
   DEBUG_CODE_END ();\r
   return LOCAL_APIC_MODE_XAPIC;\r
 }\r
@@ -299,9 +299,9 @@ GetInitialApicId (
   VOID\r
   )\r
 {\r
-  UINT32 ApicId;\r
-  UINT32 MaxCpuIdIndex;\r
-  UINT32 RegEbx;\r
+  UINT32  ApicId;\r
+  UINT32  MaxCpuIdIndex;\r
+  UINT32  RegEbx;\r
 \r
   ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);\r
 \r
@@ -338,7 +338,7 @@ GetApicId (
   VOID\r
   )\r
 {\r
-  UINT32 ApicId;\r
+  UINT32  ApicId;\r
 \r
   ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);\r
 \r
@@ -347,9 +347,10 @@ GetApicId (
     // If the initial local APIC ID is less 0x100, read APIC ID from\r
     // XAPIC_ID_OFFSET, otherwise return the initial local APIC ID.\r
     //\r
-    ApicId = ReadLocalApicReg (XAPIC_ID_OFFSET);\r
+    ApicId   = ReadLocalApicReg (XAPIC_ID_OFFSET);\r
     ApicId >>= 24;\r
   }\r
+\r
   return ApicId;\r
 }\r
 \r
@@ -378,16 +379,16 @@ GetApicVersion (
 VOID\r
 EFIAPI\r
 SendFixedIpi (\r
-  IN UINT32          ApicId,\r
-  IN UINT8           Vector\r
+  IN UINT32  ApicId,\r
+  IN UINT8   Vector\r
   )\r
 {\r
-  LOCAL_APIC_ICR_LOW IcrLow;\r
+  LOCAL_APIC_ICR_LOW  IcrLow;\r
 \r
-  IcrLow.Uint32 = 0;\r
+  IcrLow.Uint32            = 0;\r
   IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_FIXED;\r
-  IcrLow.Bits.Level = 1;\r
-  IcrLow.Bits.Vector = Vector;\r
+  IcrLow.Bits.Level        = 1;\r
+  IcrLow.Bits.Vector       = Vector;\r
   SendIpi (IcrLow.Uint32, ApicId);\r
 }\r
 \r
@@ -401,16 +402,16 @@ SendFixedIpi (
 VOID\r
 EFIAPI\r
 SendFixedIpiAllExcludingSelf (\r
-  IN UINT8           Vector\r
+  IN UINT8  Vector\r
   )\r
 {\r
-  LOCAL_APIC_ICR_LOW IcrLow;\r
+  LOCAL_APIC_ICR_LOW  IcrLow;\r
 \r
-  IcrLow.Uint32 = 0;\r
-  IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_FIXED;\r
-  IcrLow.Bits.Level = 1;\r
+  IcrLow.Uint32                    = 0;\r
+  IcrLow.Bits.DeliveryMode         = LOCAL_APIC_DELIVERY_MODE_FIXED;\r
+  IcrLow.Bits.Level                = 1;\r
   IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;\r
-  IcrLow.Bits.Vector = Vector;\r
+  IcrLow.Bits.Vector               = Vector;\r
   SendIpi (IcrLow.Uint32, 0);\r
 }\r
 \r
@@ -424,14 +425,14 @@ SendFixedIpiAllExcludingSelf (
 VOID\r
 EFIAPI\r
 SendSmiIpi (\r
-  IN UINT32          ApicId\r
+  IN UINT32  ApicId\r
   )\r
 {\r
-  LOCAL_APIC_ICR_LOW IcrLow;\r
+  LOCAL_APIC_ICR_LOW  IcrLow;\r
 \r
-  IcrLow.Uint32 = 0;\r
+  IcrLow.Uint32            = 0;\r
   IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_SMI;\r
-  IcrLow.Bits.Level = 1;\r
+  IcrLow.Bits.Level        = 1;\r
   SendIpi (IcrLow.Uint32, ApicId);\r
 }\r
 \r
@@ -446,11 +447,11 @@ SendSmiIpiAllExcludingSelf (
   VOID\r
   )\r
 {\r
-  LOCAL_APIC_ICR_LOW IcrLow;\r
+  LOCAL_APIC_ICR_LOW  IcrLow;\r
 \r
-  IcrLow.Uint32 = 0;\r
-  IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_SMI;\r
-  IcrLow.Bits.Level = 1;\r
+  IcrLow.Uint32                    = 0;\r
+  IcrLow.Bits.DeliveryMode         = LOCAL_APIC_DELIVERY_MODE_SMI;\r
+  IcrLow.Bits.Level                = 1;\r
   IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;\r
   SendIpi (IcrLow.Uint32, 0);\r
 }\r
@@ -465,14 +466,14 @@ SendSmiIpiAllExcludingSelf (
 VOID\r
 EFIAPI\r
 SendInitIpi (\r
-  IN UINT32          ApicId\r
+  IN UINT32  ApicId\r
   )\r
 {\r
-  LOCAL_APIC_ICR_LOW IcrLow;\r
+  LOCAL_APIC_ICR_LOW  IcrLow;\r
 \r
-  IcrLow.Uint32 = 0;\r
+  IcrLow.Uint32            = 0;\r
   IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_INIT;\r
-  IcrLow.Bits.Level = 1;\r
+  IcrLow.Bits.Level        = 1;\r
   SendIpi (IcrLow.Uint32, ApicId);\r
 }\r
 \r
@@ -487,11 +488,11 @@ SendInitIpiAllExcludingSelf (
   VOID\r
   )\r
 {\r
-  LOCAL_APIC_ICR_LOW IcrLow;\r
+  LOCAL_APIC_ICR_LOW  IcrLow;\r
 \r
-  IcrLow.Uint32 = 0;\r
-  IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_INIT;\r
-  IcrLow.Bits.Level = 1;\r
+  IcrLow.Uint32                    = 0;\r
+  IcrLow.Bits.DeliveryMode         = LOCAL_APIC_DELIVERY_MODE_INIT;\r
+  IcrLow.Bits.Level                = 1;\r
   IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;\r
   SendIpi (IcrLow.Uint32, 0);\r
 }\r
@@ -511,21 +512,21 @@ SendInitIpiAllExcludingSelf (
 VOID\r
 EFIAPI\r
 SendInitSipiSipi (\r
-  IN UINT32          ApicId,\r
-  IN UINT32          StartupRoutine\r
+  IN UINT32  ApicId,\r
+  IN UINT32  StartupRoutine\r
   )\r
 {\r
-  LOCAL_APIC_ICR_LOW IcrLow;\r
+  LOCAL_APIC_ICR_LOW  IcrLow;\r
 \r
   ASSERT (StartupRoutine < 0x100000);\r
   ASSERT ((StartupRoutine & 0xfff) == 0);\r
 \r
   SendInitIpi (ApicId);\r
-  MicroSecondDelay (PcdGet32(PcdCpuInitIpiDelayInMicroSeconds));\r
-  IcrLow.Uint32 = 0;\r
-  IcrLow.Bits.Vector = (StartupRoutine >> 12);\r
+  MicroSecondDelay (PcdGet32 (PcdCpuInitIpiDelayInMicroSeconds));\r
+  IcrLow.Uint32            = 0;\r
+  IcrLow.Bits.Vector       = (StartupRoutine >> 12);\r
   IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP;\r
-  IcrLow.Bits.Level = 1;\r
+  IcrLow.Bits.Level        = 1;\r
   SendIpi (IcrLow.Uint32, ApicId);\r
   if (!StandardSignatureIsAuthenticAMD ()) {\r
     MicroSecondDelay (200);\r
@@ -547,20 +548,20 @@ SendInitSipiSipi (
 VOID\r
 EFIAPI\r
 SendInitSipiSipiAllExcludingSelf (\r
-  IN UINT32          StartupRoutine\r
+  IN UINT32  StartupRoutine\r
   )\r
 {\r
-  LOCAL_APIC_ICR_LOW IcrLow;\r
+  LOCAL_APIC_ICR_LOW  IcrLow;\r
 \r
   ASSERT (StartupRoutine < 0x100000);\r
   ASSERT ((StartupRoutine & 0xfff) == 0);\r
 \r
   SendInitIpiAllExcludingSelf ();\r
-  MicroSecondDelay (PcdGet32(PcdCpuInitIpiDelayInMicroSeconds));\r
-  IcrLow.Uint32 = 0;\r
-  IcrLow.Bits.Vector = (StartupRoutine >> 12);\r
-  IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP;\r
-  IcrLow.Bits.Level = 1;\r
+  MicroSecondDelay (PcdGet32 (PcdCpuInitIpiDelayInMicroSeconds));\r
+  IcrLow.Uint32                    = 0;\r
+  IcrLow.Bits.Vector               = (StartupRoutine >> 12);\r
+  IcrLow.Bits.DeliveryMode         = LOCAL_APIC_DELIVERY_MODE_STARTUP;\r
+  IcrLow.Bits.Level                = 1;\r
   IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;\r
   SendIpi (IcrLow.Uint32, 0);\r
   if (!StandardSignatureIsAuthenticAMD ()) {\r
@@ -616,13 +617,13 @@ ProgramVirtualWireMode (
   VOID\r
   )\r
 {\r
-  LOCAL_APIC_SVR      Svr;\r
-  LOCAL_APIC_LVT_LINT Lint;\r
+  LOCAL_APIC_SVR       Svr;\r
+  LOCAL_APIC_LVT_LINT  Lint;\r
 \r
   //\r
   // Enable the APIC via SVR and set the spurious interrupt to use Int 00F.\r
   //\r
-  Svr.Uint32 = ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET);\r
+  Svr.Uint32              = ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET);\r
   Svr.Bits.SpuriousVector = 0xf;\r
   Svr.Bits.SoftwareEnable = 1;\r
   WriteLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET, Svr.Uint32);\r
@@ -630,21 +631,21 @@ ProgramVirtualWireMode (
   //\r
   // Program the LINT0 vector entry as ExtInt. Not masked, edge, active high.\r
   //\r
-  Lint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET);\r
-  Lint.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_EXTINT;\r
+  Lint.Uint32                = ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET);\r
+  Lint.Bits.DeliveryMode     = LOCAL_APIC_DELIVERY_MODE_EXTINT;\r
   Lint.Bits.InputPinPolarity = 0;\r
-  Lint.Bits.TriggerMode = 0;\r
-  Lint.Bits.Mask = 0;\r
+  Lint.Bits.TriggerMode      = 0;\r
+  Lint.Bits.Mask             = 0;\r
   WriteLocalApicReg (XAPIC_LVT_LINT0_OFFSET, Lint.Uint32);\r
 \r
   //\r
   // Program the LINT0 vector entry as NMI. Not masked, edge, active high.\r
   //\r
-  Lint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET);\r
-  Lint.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_NMI;\r
+  Lint.Uint32                = ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET);\r
+  Lint.Bits.DeliveryMode     = LOCAL_APIC_DELIVERY_MODE_NMI;\r
   Lint.Bits.InputPinPolarity = 0;\r
-  Lint.Bits.TriggerMode = 0;\r
-  Lint.Bits.Mask = 0;\r
+  Lint.Bits.TriggerMode      = 0;\r
+  Lint.Bits.Mask             = 0;\r
   WriteLocalApicReg (XAPIC_LVT_LINT1_OFFSET, Lint.Uint32);\r
 }\r
 \r
@@ -659,13 +660,13 @@ DisableLvtInterrupts (
   VOID\r
   )\r
 {\r
-  LOCAL_APIC_LVT_LINT LvtLint;\r
+  LOCAL_APIC_LVT_LINT  LvtLint;\r
 \r
-  LvtLint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET);\r
+  LvtLint.Uint32    = ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET);\r
   LvtLint.Bits.Mask = 1;\r
   WriteLocalApicReg (XAPIC_LVT_LINT0_OFFSET, LvtLint.Uint32);\r
 \r
-  LvtLint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET);\r
+  LvtLint.Uint32    = ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET);\r
   LvtLint.Bits.Mask = 1;\r
   WriteLocalApicReg (XAPIC_LVT_LINT1_OFFSET, LvtLint.Uint32);\r
 }\r
@@ -712,15 +713,15 @@ GetApicTimerCurrentCount (
 VOID\r
 EFIAPI\r
 InitializeApicTimer (\r
-  IN UINTN   DivideValue,\r
-  IN UINT32  InitCount,\r
-  IN BOOLEAN PeriodicMode,\r
-  IN UINT8   Vector\r
+  IN UINTN    DivideValue,\r
+  IN UINT32   InitCount,\r
+  IN BOOLEAN  PeriodicMode,\r
+  IN UINT8    Vector\r
   )\r
 {\r
-  LOCAL_APIC_DCR       Dcr;\r
-  LOCAL_APIC_LVT_TIMER LvtTimer;\r
-  UINT32               Divisor;\r
+  LOCAL_APIC_DCR        Dcr;\r
+  LOCAL_APIC_LVT_TIMER  LvtTimer;\r
+  UINT32                Divisor;\r
 \r
   //\r
   // Ensure local APIC is in software-enabled state.\r
@@ -734,10 +735,10 @@ InitializeApicTimer (
 \r
   if (DivideValue != 0) {\r
     ASSERT (DivideValue <= 128);\r
-    ASSERT (DivideValue == GetPowerOfTwo32((UINT32)DivideValue));\r
+    ASSERT (DivideValue == GetPowerOfTwo32 ((UINT32)DivideValue));\r
     Divisor = (UINT32)((HighBitSet32 ((UINT32)DivideValue) - 1) & 0x7);\r
 \r
-    Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET);\r
+    Dcr.Uint32            = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET);\r
     Dcr.Bits.DivideValue1 = (Divisor & 0x3);\r
     Dcr.Bits.DivideValue2 = (Divisor >> 2);\r
     WriteLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET, Dcr.Uint32);\r
@@ -752,7 +753,8 @@ InitializeApicTimer (
   } else {\r
     LvtTimer.Bits.TimerMode = 0;\r
   }\r
-  LvtTimer.Bits.Mask = 0;\r
+\r
+  LvtTimer.Bits.Mask   = 0;\r
   LvtTimer.Bits.Vector = Vector;\r
   WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);\r
 }\r
@@ -774,25 +776,25 @@ GetApicTimerState (
   OUT UINT8    *Vector  OPTIONAL\r
   )\r
 {\r
-  UINT32 Divisor;\r
-  LOCAL_APIC_DCR Dcr;\r
-  LOCAL_APIC_LVT_TIMER LvtTimer;\r
+  UINT32                Divisor;\r
+  LOCAL_APIC_DCR        Dcr;\r
+  LOCAL_APIC_LVT_TIMER  LvtTimer;\r
 \r
   //\r
   // Check the APIC Software Enable/Disable bit (bit 8) in Spurious-Interrupt\r
   // Vector Register.\r
   // This bit will be 1, if local APIC is software enabled.\r
   //\r
-  ASSERT ((ReadLocalApicReg(XAPIC_SPURIOUS_VECTOR_OFFSET) & BIT8) != 0);\r
+  ASSERT ((ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET) & BIT8) != 0);\r
 \r
   if (DivideValue != NULL) {\r
-    Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET);\r
-    Divisor = Dcr.Bits.DivideValue1 | (Dcr.Bits.DivideValue2 << 2);\r
-    Divisor = (Divisor + 1) & 0x7;\r
+    Dcr.Uint32   = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET);\r
+    Divisor      = Dcr.Bits.DivideValue1 | (Dcr.Bits.DivideValue2 << 2);\r
+    Divisor      = (Divisor + 1) & 0x7;\r
     *DivideValue = ((UINTN)1) << Divisor;\r
   }\r
 \r
-  if (PeriodicMode != NULL || Vector != NULL) {\r
+  if ((PeriodicMode != NULL) || (Vector != NULL)) {\r
     LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);\r
     if (PeriodicMode != NULL) {\r
       if (LvtTimer.Bits.TimerMode == 1) {\r
@@ -801,8 +803,9 @@ GetApicTimerState (
         *PeriodicMode = FALSE;\r
       }\r
     }\r
+\r
     if (Vector != NULL) {\r
-      *Vector = (UINT8) LvtTimer.Bits.Vector;\r
+      *Vector = (UINT8)LvtTimer.Bits.Vector;\r
     }\r
   }\r
 }\r
@@ -816,9 +819,9 @@ EnableApicTimerInterrupt (
   VOID\r
   )\r
 {\r
-  LOCAL_APIC_LVT_TIMER LvtTimer;\r
+  LOCAL_APIC_LVT_TIMER  LvtTimer;\r
 \r
-  LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);\r
+  LvtTimer.Uint32    = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);\r
   LvtTimer.Bits.Mask = 0;\r
   WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);\r
 }\r
@@ -832,9 +835,9 @@ DisableApicTimerInterrupt (
   VOID\r
   )\r
 {\r
-  LOCAL_APIC_LVT_TIMER LvtTimer;\r
+  LOCAL_APIC_LVT_TIMER  LvtTimer;\r
 \r
-  LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);\r
+  LvtTimer.Uint32    = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);\r
   LvtTimer.Bits.Mask = 1;\r
   WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);\r
 }\r
@@ -851,7 +854,7 @@ GetApicTimerInterruptState (
   VOID\r
   )\r
 {\r
-  LOCAL_APIC_LVT_TIMER LvtTimer;\r
+  LOCAL_APIC_LVT_TIMER  LvtTimer;\r
 \r
   LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);\r
   return (BOOLEAN)(LvtTimer.Bits.Mask == 0);\r
@@ -944,6 +947,7 @@ GetApicMsiValue (
       MsiData.Bits.Level = 1;\r
     }\r
   }\r
+\r
   return MsiData.Uint64;\r
 }\r
 \r
@@ -995,12 +999,15 @@ GetProcessorLocationByApicId (
     if (Thread != NULL) {\r
       *Thread = 0;\r
     }\r
+\r
     if (Core != NULL) {\r
       *Core = 0;\r
     }\r
+\r
     if (Package != NULL) {\r
       *Package = 0;\r
     }\r
+\r
     return;\r
   }\r
 \r
@@ -1008,7 +1015,7 @@ GetProcessorLocationByApicId (
   // Assume three-level mapping of APIC ID: Package|Core|Thread.\r
   //\r
   ThreadBits = 0;\r
-  CoreBits = 0;\r
+  CoreBits   = 0;\r
 \r
   //\r
   // Get max index of CPUID\r
@@ -1022,7 +1029,7 @@ GetProcessorLocationByApicId (
   //\r
   TopologyLeafSupported = FALSE;\r
   if (MaxStandardCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {\r
-    AsmCpuidEx(\r
+    AsmCpuidEx (\r
       CPUID_EXTENDED_TOPOLOGY,\r
       0,\r
       &ExtendedTopologyEax.Uint32,\r
@@ -1065,6 +1072,7 @@ GetProcessorLocationByApicId (
           CoreBits = ExtendedTopologyEax.Bits.ApicIdShift - ThreadBits;\r
           break;\r
         }\r
+\r
         SubIndex++;\r
       } while (LevelType != CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);\r
     }\r
@@ -1085,7 +1093,7 @@ GetProcessorLocationByApicId (
     //\r
     // Check for topology extensions on AMD processor\r
     //\r
-    if (StandardSignatureIsAuthenticAMD()) {\r
+    if (StandardSignatureIsAuthenticAMD ()) {\r
       if (MaxExtendedCpuIdIndex >= CPUID_AMD_PROCESSOR_TOPOLOGY) {\r
         AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, &AmdExtendedCpuSigEcx.Uint32, NULL);\r
         if (AmdExtendedCpuSigEcx.Bits.TopologyExtensions != 0) {\r
@@ -1102,8 +1110,7 @@ GetProcessorLocationByApicId (
           MaxCoresPerPackage = MaxLogicProcessorsPerPackage / (AmdProcessorTopologyEbx.Bits.ThreadsPerCore + 1);\r
         }\r
       }\r
-    }\r
-    else {\r
+    } else {\r
       //\r
       // Extract core count based on CACHE information\r
       //\r
@@ -1115,16 +1122,18 @@ GetProcessorLocationByApicId (
       }\r
     }\r
 \r
-    ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1);\r
-    CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1);\r
+    ThreadBits = (UINTN)(HighBitSet32 (MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1);\r
+    CoreBits   = (UINTN)(HighBitSet32 (MaxCoresPerPackage - 1) + 1);\r
   }\r
 \r
   if (Thread != NULL) {\r
     *Thread = InitialApicId & ((1 << ThreadBits) - 1);\r
   }\r
+\r
   if (Core != NULL) {\r
     *Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);\r
   }\r
+\r
   if (Package != NULL) {\r
     *Package = (InitialApicId >> (ThreadBits + CoreBits));\r
   }\r
@@ -1158,13 +1167,13 @@ GetProcessorLocation2ByApicId (
   OUT UINT32  *Thread   OPTIONAL\r
   )\r
 {\r
-  CPUID_EXTENDED_TOPOLOGY_EAX         ExtendedTopologyEax;\r
-  CPUID_EXTENDED_TOPOLOGY_ECX         ExtendedTopologyEcx;\r
-  UINT32                              MaxStandardCpuIdIndex;\r
-  UINT32                              Index;\r
-  UINTN                               LevelType;\r
-  UINT32                              Bits[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 2];\r
-  UINT32                              *Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 2];\r
+  CPUID_EXTENDED_TOPOLOGY_EAX  ExtendedTopologyEax;\r
+  CPUID_EXTENDED_TOPOLOGY_ECX  ExtendedTopologyEcx;\r
+  UINT32                       MaxStandardCpuIdIndex;\r
+  UINT32                       Index;\r
+  UINTN                        LevelType;\r
+  UINT32                       Bits[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 2];\r
+  UINT32                       *Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 2];\r
 \r
   for (LevelType = 0; LevelType < ARRAY_SIZE (Bits); LevelType++) {\r
     Bits[LevelType] = 0;\r
@@ -1178,12 +1187,15 @@ GetProcessorLocation2ByApicId (
     if (Die != NULL) {\r
       *Die = 0;\r
     }\r
+\r
     if (Tile != NULL) {\r
       *Tile = 0;\r
     }\r
+\r
     if (Module != NULL) {\r
       *Module = 0;\r
     }\r
+\r
     GetProcessorLocationByApicId (InitialApicId, Package, Core, Thread);\r
     return;\r
   }\r
@@ -1193,7 +1205,7 @@ GetProcessorLocation2ByApicId (
   // is the preferred mechanism for enumerating topology.\r
   //\r
   for (Index = 0; ; Index++) {\r
-    AsmCpuidEx(\r
+    AsmCpuidEx (\r
       CPUID_V2_EXTENDED_TOPOLOGY,\r
       Index,\r
       &ExtendedTopologyEax.Uint32,\r
@@ -1211,6 +1223,7 @@ GetProcessorLocation2ByApicId (
     if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID) {\r
       break;\r
     }\r
+\r
     ASSERT (LevelType < ARRAY_SIZE (Bits));\r
     Bits[LevelType] = ExtendedTopologyEax.Bits.ApicIdShift;\r
   }\r
@@ -1226,18 +1239,19 @@ GetProcessorLocation2ByApicId (
   }\r
 \r
   Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 1] = Package;\r
-  Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE    ] = Die;\r
-  Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_TILE   ] = Tile;\r
-  Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_MODULE ] = Module;\r
-  Location[CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE   ]    = Core;\r
-  Location[CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT    ]    = Thread;\r
+  Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE]     = Die;\r
+  Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_TILE]    = Tile;\r
+  Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_MODULE]  = Module;\r
+  Location[CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE]       = Core;\r
+  Location[CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT]        = Thread;\r
 \r
   Bits[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 1] = 32;\r
 \r
   for ( LevelType = CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT\r
-      ; LevelType <= CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 1\r
-      ; LevelType ++\r
-      ) {\r
+        ; LevelType <= CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 1\r
+        ; LevelType++\r
+        )\r
+  {\r
     if (Location[LevelType] != NULL) {\r
       //\r
       // Bits[i] holds the number of bits to shift right on x2APIC ID to get a unique\r

diff --git a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
index cdcbca04619119a2b0012e347647acd1ec65f6cd..aaa42ff8450b575e541a30ed373007aae9169196 100644 (file)
--- a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
+++ b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
@@ -45,13 +45,14 @@ LocalApicBaseAddressMsrSupported (
 \r
   AsmCpuid (1, &RegEax, NULL, NULL, NULL);\r
   FamilyId = BitFieldRead32 (RegEax, 8, 11);\r
-  if (FamilyId == 0x04 || FamilyId == 0x05) {\r
+  if ((FamilyId == 0x04) || (FamilyId == 0x05)) {\r
     //\r
     // CPUs with a FamilyId of 0x04 or 0x05 do not support the\r
     // Local APIC Base Address MSR\r
     //\r
     return FALSE;\r
   }\r
+\r
   return TRUE;\r
 }\r
 \r
@@ -79,8 +80,8 @@ GetLocalApicBaseAddress (
 \r
   ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);\r
 \r
-  return (UINTN)(LShiftU64 ((UINT64) ApicBaseMsr.Bits.ApicBaseHi, 32)) +\r
-           (((UINTN)ApicBaseMsr.Bits.ApicBase) << 12);\r
+  return (UINTN)(LShiftU64 ((UINT64)ApicBaseMsr.Bits.ApicBaseHi, 32)) +\r
+         (((UINTN)ApicBaseMsr.Bits.ApicBase) << 12);\r
 }\r
 \r
 /**\r
@@ -94,7 +95,7 @@ GetLocalApicBaseAddress (
 VOID\r
 EFIAPI\r
 SetLocalApicBaseAddress (\r
-  IN UINTN                BaseAddress\r
+  IN UINTN  BaseAddress\r
   )\r
 {\r
   MSR_IA32_APIC_BASE_REGISTER  ApicBaseMsr;\r
@@ -110,8 +111,8 @@ SetLocalApicBaseAddress (
 \r
   ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);\r
 \r
-  ApicBaseMsr.Bits.ApicBase   = (UINT32) (BaseAddress >> 12);\r
-  ApicBaseMsr.Bits.ApicBaseHi = (UINT32) (RShiftU64((UINT64) BaseAddress, 32));\r
+  ApicBaseMsr.Bits.ApicBase   = (UINT32)(BaseAddress >> 12);\r
+  ApicBaseMsr.Bits.ApicBaseHi = (UINT32)(RShiftU64 ((UINT64)BaseAddress, 32));\r
 \r
   AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64);\r
 }\r
@@ -135,12 +136,12 @@ ReadLocalApicReg (
   IN UINTN  MmioOffset\r
   )\r
 {\r
-  UINT32 MsrIndex;\r
+  UINT32  MsrIndex;\r
 \r
   ASSERT ((MmioOffset & 0xf) == 0);\r
 \r
   if (GetApicMode () == LOCAL_APIC_MODE_XAPIC) {\r
-    return MmioRead32 (GetLocalApicBaseAddress() + MmioOffset);\r
+    return MmioRead32 (GetLocalApicBaseAddress () + MmioOffset);\r
   } else {\r
     //\r
     // DFR is not supported in x2APIC mode.\r
@@ -174,16 +175,16 @@ ReadLocalApicReg (
 VOID\r
 EFIAPI\r
 WriteLocalApicReg (\r
-  IN UINTN  MmioOffset,\r
-  IN UINT32 Value\r
+  IN UINTN   MmioOffset,\r
+  IN UINT32  Value\r
   )\r
 {\r
-  UINT32 MsrIndex;\r
+  UINT32  MsrIndex;\r
 \r
   ASSERT ((MmioOffset & 0xf) == 0);\r
 \r
   if (GetApicMode () == LOCAL_APIC_MODE_XAPIC) {\r
-    MmioWrite32 (GetLocalApicBaseAddress() + MmioOffset, Value);\r
+    MmioWrite32 (GetLocalApicBaseAddress () + MmioOffset, Value);\r
   } else {\r
     //\r
     // DFR is not supported in x2APIC mode.\r
@@ -216,15 +217,15 @@ WriteLocalApicReg (
 **/\r
 VOID\r
 SendIpi (\r
-  IN UINT32          IcrLow,\r
-  IN UINT32          ApicId\r
+  IN UINT32  IcrLow,\r
+  IN UINT32  ApicId\r
   )\r
 {\r
-  UINT64             MsrValue;\r
-  LOCAL_APIC_ICR_LOW IcrLowReg;\r
-  UINTN              LocalApciBaseAddress;\r
-  UINT32             IcrHigh;\r
-  BOOLEAN            InterruptState;\r
+  UINT64              MsrValue;\r
+  LOCAL_APIC_ICR_LOW  IcrLowReg;\r
+  UINTN               LocalApciBaseAddress;\r
+  UINT32              IcrHigh;\r
+  BOOLEAN             InterruptState;\r
 \r
   //\r
   // Legacy APIC or X2APIC?\r
@@ -237,7 +238,7 @@ SendIpi (
     //\r
     // Get base address of this LAPIC\r
     //\r
-    LocalApciBaseAddress = GetLocalApicBaseAddress();\r
+    LocalApciBaseAddress = GetLocalApicBaseAddress ();\r
 \r
     //\r
     // Save existing contents of ICR high 32 bits\r
@@ -271,13 +272,12 @@ SendIpi (
     MmioWrite32 (LocalApciBaseAddress + XAPIC_ICR_HIGH_OFFSET, IcrHigh);\r
 \r
     SetInterruptState (InterruptState);\r
-\r
   } else {\r
     //\r
     // For x2APIC, A single MSR write to the Interrupt Command Register is required for dispatching an\r
     // interrupt in x2APIC mode.\r
     //\r
-    MsrValue = LShiftU64 ((UINT64) ApicId, 32) | IcrLow;\r
+    MsrValue = LShiftU64 ((UINT64)ApicId, 32) | IcrLow;\r
     AsmWriteMsr64 (X2APIC_MSR_ICR_ADDRESS, MsrValue);\r
   }\r
 }\r
@@ -354,7 +354,7 @@ SetApicMode (
       case LOCAL_APIC_MODE_XAPIC:\r
         break;\r
       case LOCAL_APIC_MODE_X2APIC:\r
-        ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);\r
+        ApicBaseMsr.Uint64    = AsmReadMsr64 (MSR_IA32_APIC_BASE);\r
         ApicBaseMsr.Bits.EXTD = 1;\r
         AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64);\r
         break;\r
@@ -368,9 +368,9 @@ SetApicMode (
         //  Transition from x2APIC mode to xAPIC mode is a two-step process:\r
         //    x2APIC -> Local APIC disabled -> xAPIC\r
         //\r
-        ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);\r
+        ApicBaseMsr.Uint64    = AsmReadMsr64 (MSR_IA32_APIC_BASE);\r
         ApicBaseMsr.Bits.EXTD = 0;\r
-        ApicBaseMsr.Bits.EN = 0;\r
+        ApicBaseMsr.Bits.EN   = 0;\r
         AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64);\r
         ApicBaseMsr.Bits.EN = 1;\r
         AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64);\r
@@ -398,9 +398,9 @@ GetInitialApicId (
   VOID\r
   )\r
 {\r
-  UINT32 ApicId;\r
-  UINT32 MaxCpuIdIndex;\r
-  UINT32 RegEbx;\r
+  UINT32  ApicId;\r
+  UINT32  MaxCpuIdIndex;\r
+  UINT32  RegEbx;\r
 \r
   if (GetApicMode () == LOCAL_APIC_MODE_XAPIC) {\r
     //\r
@@ -419,6 +419,7 @@ GetInitialApicId (
         return ApicId;\r
       }\r
     }\r
+\r
     AsmCpuid (CPUID_VERSION_INFO, NULL, &RegEbx, NULL, NULL);\r
     return RegEbx >> 24;\r
   } else {\r
@@ -437,8 +438,8 @@ GetApicId (
   VOID\r
   )\r
 {\r
-  UINT32 ApicId;\r
-  UINT32 InitApicId;\r
+  UINT32  ApicId;\r
+  UINT32  InitApicId;\r
 \r
   ApicId = ReadLocalApicReg (XAPIC_ID_OFFSET);\r
   if (GetApicMode () == LOCAL_APIC_MODE_XAPIC) {\r
@@ -473,16 +474,16 @@ GetApicVersion (
 VOID\r
 EFIAPI\r
 SendFixedIpi (\r
-  IN UINT32          ApicId,\r
-  IN UINT8           Vector\r
+  IN UINT32  ApicId,\r
+  IN UINT8   Vector\r
   )\r
 {\r
-  LOCAL_APIC_ICR_LOW IcrLow;\r
+  LOCAL_APIC_ICR_LOW  IcrLow;\r
 \r
-  IcrLow.Uint32 = 0;\r
+  IcrLow.Uint32            = 0;\r
   IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_FIXED;\r
-  IcrLow.Bits.Level = 1;\r
-  IcrLow.Bits.Vector = Vector;\r
+  IcrLow.Bits.Level        = 1;\r
+  IcrLow.Bits.Vector       = Vector;\r
   SendIpi (IcrLow.Uint32, ApicId);\r
 }\r
 \r
@@ -496,16 +497,16 @@ SendFixedIpi (
 VOID\r
 EFIAPI\r
 SendFixedIpiAllExcludingSelf (\r
-  IN UINT8           Vector\r
+  IN UINT8  Vector\r
   )\r
 {\r
-  LOCAL_APIC_ICR_LOW IcrLow;\r
+  LOCAL_APIC_ICR_LOW  IcrLow;\r
 \r
-  IcrLow.Uint32 = 0;\r
-  IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_FIXED;\r
-  IcrLow.Bits.Level = 1;\r
+  IcrLow.Uint32                    = 0;\r
+  IcrLow.Bits.DeliveryMode         = LOCAL_APIC_DELIVERY_MODE_FIXED;\r
+  IcrLow.Bits.Level                = 1;\r
   IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;\r
-  IcrLow.Bits.Vector = Vector;\r
+  IcrLow.Bits.Vector               = Vector;\r
   SendIpi (IcrLow.Uint32, 0);\r
 }\r
 \r
@@ -519,14 +520,14 @@ SendFixedIpiAllExcludingSelf (
 VOID\r
 EFIAPI\r
 SendSmiIpi (\r
-  IN UINT32          ApicId\r
+  IN UINT32  ApicId\r
   )\r
 {\r
-  LOCAL_APIC_ICR_LOW IcrLow;\r
+  LOCAL_APIC_ICR_LOW  IcrLow;\r
 \r
-  IcrLow.Uint32 = 0;\r
+  IcrLow.Uint32            = 0;\r
   IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_SMI;\r
-  IcrLow.Bits.Level = 1;\r
+  IcrLow.Bits.Level        = 1;\r
   SendIpi (IcrLow.Uint32, ApicId);\r
 }\r
 \r
@@ -541,11 +542,11 @@ SendSmiIpiAllExcludingSelf (
   VOID\r
   )\r
 {\r
-  LOCAL_APIC_ICR_LOW IcrLow;\r
+  LOCAL_APIC_ICR_LOW  IcrLow;\r
 \r
-  IcrLow.Uint32 = 0;\r
-  IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_SMI;\r
-  IcrLow.Bits.Level = 1;\r
+  IcrLow.Uint32                    = 0;\r
+  IcrLow.Bits.DeliveryMode         = LOCAL_APIC_DELIVERY_MODE_SMI;\r
+  IcrLow.Bits.Level                = 1;\r
   IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;\r
   SendIpi (IcrLow.Uint32, 0);\r
 }\r
@@ -560,14 +561,14 @@ SendSmiIpiAllExcludingSelf (
 VOID\r
 EFIAPI\r
 SendInitIpi (\r
-  IN UINT32          ApicId\r
+  IN UINT32  ApicId\r
   )\r
 {\r
-  LOCAL_APIC_ICR_LOW IcrLow;\r
+  LOCAL_APIC_ICR_LOW  IcrLow;\r
 \r
-  IcrLow.Uint32 = 0;\r
+  IcrLow.Uint32            = 0;\r
   IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_INIT;\r
-  IcrLow.Bits.Level = 1;\r
+  IcrLow.Bits.Level        = 1;\r
   SendIpi (IcrLow.Uint32, ApicId);\r
 }\r
 \r
@@ -582,11 +583,11 @@ SendInitIpiAllExcludingSelf (
   VOID\r
   )\r
 {\r
-  LOCAL_APIC_ICR_LOW IcrLow;\r
+  LOCAL_APIC_ICR_LOW  IcrLow;\r
 \r
-  IcrLow.Uint32 = 0;\r
-  IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_INIT;\r
-  IcrLow.Bits.Level = 1;\r
+  IcrLow.Uint32                    = 0;\r
+  IcrLow.Bits.DeliveryMode         = LOCAL_APIC_DELIVERY_MODE_INIT;\r
+  IcrLow.Bits.Level                = 1;\r
   IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;\r
   SendIpi (IcrLow.Uint32, 0);\r
 }\r
@@ -606,21 +607,21 @@ SendInitIpiAllExcludingSelf (
 VOID\r
 EFIAPI\r
 SendInitSipiSipi (\r
-  IN UINT32          ApicId,\r
-  IN UINT32          StartupRoutine\r
+  IN UINT32  ApicId,\r
+  IN UINT32  StartupRoutine\r
   )\r
 {\r
-  LOCAL_APIC_ICR_LOW IcrLow;\r
+  LOCAL_APIC_ICR_LOW  IcrLow;\r
 \r
   ASSERT (StartupRoutine < 0x100000);\r
   ASSERT ((StartupRoutine & 0xfff) == 0);\r
 \r
   SendInitIpi (ApicId);\r
-  MicroSecondDelay (PcdGet32(PcdCpuInitIpiDelayInMicroSeconds));\r
-  IcrLow.Uint32 = 0;\r
-  IcrLow.Bits.Vector = (StartupRoutine >> 12);\r
+  MicroSecondDelay (PcdGet32 (PcdCpuInitIpiDelayInMicroSeconds));\r
+  IcrLow.Uint32            = 0;\r
+  IcrLow.Bits.Vector       = (StartupRoutine >> 12);\r
   IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP;\r
-  IcrLow.Bits.Level = 1;\r
+  IcrLow.Bits.Level        = 1;\r
   SendIpi (IcrLow.Uint32, ApicId);\r
   if (!StandardSignatureIsAuthenticAMD ()) {\r
     MicroSecondDelay (200);\r
@@ -642,20 +643,20 @@ SendInitSipiSipi (
 VOID\r
 EFIAPI\r
 SendInitSipiSipiAllExcludingSelf (\r
-  IN UINT32          StartupRoutine\r
+  IN UINT32  StartupRoutine\r
   )\r
 {\r
-  LOCAL_APIC_ICR_LOW IcrLow;\r
+  LOCAL_APIC_ICR_LOW  IcrLow;\r
 \r
   ASSERT (StartupRoutine < 0x100000);\r
   ASSERT ((StartupRoutine & 0xfff) == 0);\r
 \r
   SendInitIpiAllExcludingSelf ();\r
-  MicroSecondDelay (PcdGet32(PcdCpuInitIpiDelayInMicroSeconds));\r
-  IcrLow.Uint32 = 0;\r
-  IcrLow.Bits.Vector = (StartupRoutine >> 12);\r
-  IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP;\r
-  IcrLow.Bits.Level = 1;\r
+  MicroSecondDelay (PcdGet32 (PcdCpuInitIpiDelayInMicroSeconds));\r
+  IcrLow.Uint32                    = 0;\r
+  IcrLow.Bits.Vector               = (StartupRoutine >> 12);\r
+  IcrLow.Bits.DeliveryMode         = LOCAL_APIC_DELIVERY_MODE_STARTUP;\r
+  IcrLow.Bits.Level                = 1;\r
   IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;\r
   SendIpi (IcrLow.Uint32, 0);\r
   if (!StandardSignatureIsAuthenticAMD ()) {\r
@@ -711,13 +712,13 @@ ProgramVirtualWireMode (
   VOID\r
   )\r
 {\r
-  LOCAL_APIC_SVR      Svr;\r
-  LOCAL_APIC_LVT_LINT Lint;\r
+  LOCAL_APIC_SVR       Svr;\r
+  LOCAL_APIC_LVT_LINT  Lint;\r
 \r
   //\r
   // Enable the APIC via SVR and set the spurious interrupt to use Int 00F.\r
   //\r
-  Svr.Uint32 = ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET);\r
+  Svr.Uint32              = ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET);\r
   Svr.Bits.SpuriousVector = 0xf;\r
   Svr.Bits.SoftwareEnable = 1;\r
   WriteLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET, Svr.Uint32);\r
@@ -725,21 +726,21 @@ ProgramVirtualWireMode (
   //\r
   // Program the LINT0 vector entry as ExtInt. Not masked, edge, active high.\r
   //\r
-  Lint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET);\r
-  Lint.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_EXTINT;\r
+  Lint.Uint32                = ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET);\r
+  Lint.Bits.DeliveryMode     = LOCAL_APIC_DELIVERY_MODE_EXTINT;\r
   Lint.Bits.InputPinPolarity = 0;\r
-  Lint.Bits.TriggerMode = 0;\r
-  Lint.Bits.Mask = 0;\r
+  Lint.Bits.TriggerMode      = 0;\r
+  Lint.Bits.Mask             = 0;\r
   WriteLocalApicReg (XAPIC_LVT_LINT0_OFFSET, Lint.Uint32);\r
 \r
   //\r
   // Program the LINT0 vector entry as NMI. Not masked, edge, active high.\r
   //\r
-  Lint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET);\r
-  Lint.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_NMI;\r
+  Lint.Uint32                = ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET);\r
+  Lint.Bits.DeliveryMode     = LOCAL_APIC_DELIVERY_MODE_NMI;\r
   Lint.Bits.InputPinPolarity = 0;\r
-  Lint.Bits.TriggerMode = 0;\r
-  Lint.Bits.Mask = 0;\r
+  Lint.Bits.TriggerMode      = 0;\r
+  Lint.Bits.Mask             = 0;\r
   WriteLocalApicReg (XAPIC_LVT_LINT1_OFFSET, Lint.Uint32);\r
 }\r
 \r
@@ -754,13 +755,13 @@ DisableLvtInterrupts (
   VOID\r
   )\r
 {\r
-  LOCAL_APIC_LVT_LINT LvtLint;\r
+  LOCAL_APIC_LVT_LINT  LvtLint;\r
 \r
-  LvtLint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET);\r
+  LvtLint.Uint32    = ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET);\r
   LvtLint.Bits.Mask = 1;\r
   WriteLocalApicReg (XAPIC_LVT_LINT0_OFFSET, LvtLint.Uint32);\r
 \r
-  LvtLint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET);\r
+  LvtLint.Uint32    = ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET);\r
   LvtLint.Bits.Mask = 1;\r
   WriteLocalApicReg (XAPIC_LVT_LINT1_OFFSET, LvtLint.Uint32);\r
 }\r
@@ -807,15 +808,15 @@ GetApicTimerCurrentCount (
 VOID\r
 EFIAPI\r
 InitializeApicTimer (\r
-  IN UINTN   DivideValue,\r
-  IN UINT32  InitCount,\r
-  IN BOOLEAN PeriodicMode,\r
-  IN UINT8   Vector\r
+  IN UINTN    DivideValue,\r
+  IN UINT32   InitCount,\r
+  IN BOOLEAN  PeriodicMode,\r
+  IN UINT8    Vector\r
   )\r
 {\r
-  LOCAL_APIC_DCR       Dcr;\r
-  LOCAL_APIC_LVT_TIMER LvtTimer;\r
-  UINT32               Divisor;\r
+  LOCAL_APIC_DCR        Dcr;\r
+  LOCAL_APIC_LVT_TIMER  LvtTimer;\r
+  UINT32                Divisor;\r
 \r
   //\r
   // Ensure local APIC is in software-enabled state.\r
@@ -829,10 +830,10 @@ InitializeApicTimer (
 \r
   if (DivideValue != 0) {\r
     ASSERT (DivideValue <= 128);\r
-    ASSERT (DivideValue == GetPowerOfTwo32((UINT32)DivideValue));\r
+    ASSERT (DivideValue == GetPowerOfTwo32 ((UINT32)DivideValue));\r
     Divisor = (UINT32)((HighBitSet32 ((UINT32)DivideValue) - 1) & 0x7);\r
 \r
-    Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET);\r
+    Dcr.Uint32            = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET);\r
     Dcr.Bits.DivideValue1 = (Divisor & 0x3);\r
     Dcr.Bits.DivideValue2 = (Divisor >> 2);\r
     WriteLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET, Dcr.Uint32);\r
@@ -847,7 +848,8 @@ InitializeApicTimer (
   } else {\r
     LvtTimer.Bits.TimerMode = 0;\r
   }\r
-  LvtTimer.Bits.Mask = 0;\r
+\r
+  LvtTimer.Bits.Mask   = 0;\r
   LvtTimer.Bits.Vector = Vector;\r
   WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);\r
 }\r
@@ -869,25 +871,25 @@ GetApicTimerState (
   OUT UINT8    *Vector  OPTIONAL\r
   )\r
 {\r
-  UINT32 Divisor;\r
-  LOCAL_APIC_DCR Dcr;\r
-  LOCAL_APIC_LVT_TIMER LvtTimer;\r
+  UINT32                Divisor;\r
+  LOCAL_APIC_DCR        Dcr;\r
+  LOCAL_APIC_LVT_TIMER  LvtTimer;\r
 \r
   //\r
   // Check the APIC Software Enable/Disable bit (bit 8) in Spurious-Interrupt\r
   // Vector Register.\r
   // This bit will be 1, if local APIC is software enabled.\r
   //\r
-  ASSERT ((ReadLocalApicReg(XAPIC_SPURIOUS_VECTOR_OFFSET) & BIT8) != 0);\r
+  ASSERT ((ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET) & BIT8) != 0);\r
 \r
   if (DivideValue != NULL) {\r
-    Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET);\r
-    Divisor = Dcr.Bits.DivideValue1 | (Dcr.Bits.DivideValue2 << 2);\r
-    Divisor = (Divisor + 1) & 0x7;\r
+    Dcr.Uint32   = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET);\r
+    Divisor      = Dcr.Bits.DivideValue1 | (Dcr.Bits.DivideValue2 << 2);\r
+    Divisor      = (Divisor + 1) & 0x7;\r
     *DivideValue = ((UINTN)1) << Divisor;\r
   }\r
 \r
-  if (PeriodicMode != NULL || Vector != NULL) {\r
+  if ((PeriodicMode != NULL) || (Vector != NULL)) {\r
     LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);\r
     if (PeriodicMode != NULL) {\r
       if (LvtTimer.Bits.TimerMode == 1) {\r
@@ -896,8 +898,9 @@ GetApicTimerState (
         *PeriodicMode = FALSE;\r
       }\r
     }\r
+\r
     if (Vector != NULL) {\r
-      *Vector = (UINT8) LvtTimer.Bits.Vector;\r
+      *Vector = (UINT8)LvtTimer.Bits.Vector;\r
     }\r
   }\r
 }\r
@@ -911,9 +914,9 @@ EnableApicTimerInterrupt (
   VOID\r
   )\r
 {\r
-  LOCAL_APIC_LVT_TIMER LvtTimer;\r
+  LOCAL_APIC_LVT_TIMER  LvtTimer;\r
 \r
-  LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);\r
+  LvtTimer.Uint32    = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);\r
   LvtTimer.Bits.Mask = 0;\r
   WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);\r
 }\r
@@ -927,9 +930,9 @@ DisableApicTimerInterrupt (
   VOID\r
   )\r
 {\r
-  LOCAL_APIC_LVT_TIMER LvtTimer;\r
+  LOCAL_APIC_LVT_TIMER  LvtTimer;\r
 \r
-  LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);\r
+  LvtTimer.Uint32    = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);\r
   LvtTimer.Bits.Mask = 1;\r
   WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);\r
 }\r
@@ -946,7 +949,7 @@ GetApicTimerInterruptState (
   VOID\r
   )\r
 {\r
-  LOCAL_APIC_LVT_TIMER LvtTimer;\r
+  LOCAL_APIC_LVT_TIMER  LvtTimer;\r
 \r
   LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);\r
   return (BOOLEAN)(LvtTimer.Bits.Mask == 0);\r
@@ -1039,6 +1042,7 @@ GetApicMsiValue (
       MsiData.Bits.Level = 1;\r
     }\r
   }\r
+\r
   return MsiData.Uint64;\r
 }\r
 \r
@@ -1090,12 +1094,15 @@ GetProcessorLocationByApicId (
     if (Thread != NULL) {\r
       *Thread = 0;\r
     }\r
+\r
     if (Core != NULL) {\r
       *Core = 0;\r
     }\r
+\r
     if (Package != NULL) {\r
       *Package = 0;\r
     }\r
+\r
     return;\r
   }\r
 \r
@@ -1103,7 +1110,7 @@ GetProcessorLocationByApicId (
   // Assume three-level mapping of APIC ID: Package|Core|Thread.\r
   //\r
   ThreadBits = 0;\r
-  CoreBits = 0;\r
+  CoreBits   = 0;\r
 \r
   //\r
   // Get max index of CPUID\r
@@ -1117,7 +1124,7 @@ GetProcessorLocationByApicId (
   //\r
   TopologyLeafSupported = FALSE;\r
   if (MaxStandardCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {\r
-    AsmCpuidEx(\r
+    AsmCpuidEx (\r
       CPUID_EXTENDED_TOPOLOGY,\r
       0,\r
       &ExtendedTopologyEax.Uint32,\r
@@ -1160,6 +1167,7 @@ GetProcessorLocationByApicId (
           CoreBits = ExtendedTopologyEax.Bits.ApicIdShift - ThreadBits;\r
           break;\r
         }\r
+\r
         SubIndex++;\r
       } while (LevelType != CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);\r
     }\r
@@ -1180,7 +1188,7 @@ GetProcessorLocationByApicId (
     //\r
     // Check for topology extensions on AMD processor\r
     //\r
-    if (StandardSignatureIsAuthenticAMD()) {\r
+    if (StandardSignatureIsAuthenticAMD ()) {\r
       if (MaxExtendedCpuIdIndex >= CPUID_AMD_PROCESSOR_TOPOLOGY) {\r
         AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, &AmdExtendedCpuSigEcx.Uint32, NULL);\r
         if (AmdExtendedCpuSigEcx.Bits.TopologyExtensions != 0) {\r
@@ -1197,8 +1205,7 @@ GetProcessorLocationByApicId (
           MaxCoresPerPackage = MaxLogicProcessorsPerPackage / (AmdProcessorTopologyEbx.Bits.ThreadsPerCore + 1);\r
         }\r
       }\r
-    }\r
-    else {\r
+    } else {\r
       //\r
       // Extract core count based on CACHE information\r
       //\r
@@ -1210,16 +1217,18 @@ GetProcessorLocationByApicId (
       }\r
     }\r
 \r
-    ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1);\r
-    CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1);\r
+    ThreadBits = (UINTN)(HighBitSet32 (MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1);\r
+    CoreBits   = (UINTN)(HighBitSet32 (MaxCoresPerPackage - 1) + 1);\r
   }\r
 \r
   if (Thread != NULL) {\r
     *Thread = InitialApicId & ((1 << ThreadBits) - 1);\r
   }\r
+\r
   if (Core != NULL) {\r
     *Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);\r
   }\r
+\r
   if (Package != NULL) {\r
     *Package = (InitialApicId >> (ThreadBits + CoreBits));\r
   }\r
@@ -1253,13 +1262,13 @@ GetProcessorLocation2ByApicId (
   OUT UINT32  *Thread   OPTIONAL\r
   )\r
 {\r
-  CPUID_EXTENDED_TOPOLOGY_EAX         ExtendedTopologyEax;\r
-  CPUID_EXTENDED_TOPOLOGY_ECX         ExtendedTopologyEcx;\r
-  UINT32                              MaxStandardCpuIdIndex;\r
-  UINT32                              Index;\r
-  UINTN                               LevelType;\r
-  UINT32                              Bits[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 2];\r
-  UINT32                              *Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 2];\r
+  CPUID_EXTENDED_TOPOLOGY_EAX  ExtendedTopologyEax;\r
+  CPUID_EXTENDED_TOPOLOGY_ECX  ExtendedTopologyEcx;\r
+  UINT32                       MaxStandardCpuIdIndex;\r
+  UINT32                       Index;\r
+  UINTN                        LevelType;\r
+  UINT32                       Bits[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 2];\r
+  UINT32                       *Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 2];\r
 \r
   for (LevelType = 0; LevelType < ARRAY_SIZE (Bits); LevelType++) {\r
     Bits[LevelType] = 0;\r
@@ -1273,12 +1282,15 @@ GetProcessorLocation2ByApicId (
     if (Die != NULL) {\r
       *Die = 0;\r
     }\r
+\r
     if (Tile != NULL) {\r
       *Tile = 0;\r
     }\r
+\r
     if (Module != NULL) {\r
       *Module = 0;\r
     }\r
+\r
     GetProcessorLocationByApicId (InitialApicId, Package, Core, Thread);\r
     return;\r
   }\r
@@ -1288,7 +1300,7 @@ GetProcessorLocation2ByApicId (
   // is the preferred mechanism for enumerating topology.\r
   //\r
   for (Index = 0; ; Index++) {\r
-    AsmCpuidEx(\r
+    AsmCpuidEx (\r
       CPUID_V2_EXTENDED_TOPOLOGY,\r
       Index,\r
       &ExtendedTopologyEax.Uint32,\r
@@ -1306,6 +1318,7 @@ GetProcessorLocation2ByApicId (
     if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID) {\r
       break;\r
     }\r
+\r
     ASSERT (LevelType < ARRAY_SIZE (Bits));\r
     Bits[LevelType] = ExtendedTopologyEax.Bits.ApicIdShift;\r
   }\r
@@ -1321,18 +1334,19 @@ GetProcessorLocation2ByApicId (
   }\r
 \r
   Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 1] = Package;\r
-  Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE    ] = Die;\r
-  Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_TILE   ] = Tile;\r
-  Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_MODULE ] = Module;\r
-  Location[CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE   ]    = Core;\r
-  Location[CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT    ]    = Thread;\r
+  Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE]     = Die;\r
+  Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_TILE]    = Tile;\r
+  Location[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_MODULE]  = Module;\r
+  Location[CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE]       = Core;\r
+  Location[CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT]        = Thread;\r
 \r
   Bits[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 1] = 32;\r
 \r
   for ( LevelType = CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT\r
-      ; LevelType <= CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 1\r
-      ; LevelType ++\r
-      ) {\r
+        ; LevelType <= CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE + 1\r
+        ; LevelType++\r
+        )\r
+  {\r
     if (Location[LevelType] != NULL) {\r
       //\r
       // Bits[i] holds the number of bits to shift right on x2APIC ID to get a unique\r

diff --git a/UefiCpuPkg/Library/CpuCacheInfoLib/CpuCacheInfoLib.c b/UefiCpuPkg/Library/CpuCacheInfoLib/CpuCacheInfoLib.c
index f4fcee39e97ddc17d6b69c12d0dc1e9a9b3929a3..c7973735e15d41ed9dcd71c1809a8ce0e3dcb54f 100644 (file)
--- a/UefiCpuPkg/Library/CpuCacheInfoLib/CpuCacheInfoLib.c
+++ b/UefiCpuPkg/Library/CpuCacheInfoLib/CpuCacheInfoLib.c
@@ -17,21 +17,31 @@
 **/\r
 VOID\r
 CpuCacheInfoPrintCpuCacheInfoTable (\r
-  IN CPU_CACHE_INFO         *CpuCacheInfo,\r
-  IN UINTN                  CpuCacheInfoCount\r
+  IN CPU_CACHE_INFO  *CpuCacheInfo,\r
+  IN UINTN           CpuCacheInfoCount\r
   )\r
 {\r
-  UINTN                     Index;\r
+  UINTN  Index;\r
 \r
   DEBUG ((DEBUG_INFO, "+-------+--------------------------------------------------------------------------------------+\n"));\r
   DEBUG ((DEBUG_INFO, "| Index | Packge  CoreType  CacheLevel  CacheType  CacheWays (FA|DM) CacheSizeinKB  CacheCount |\n"));\r
   DEBUG ((DEBUG_INFO, "+-------+--------------------------------------------------------------------------------------+\n"));\r
 \r
   for (Index = 0; Index < CpuCacheInfoCount; Index++) {\r
-    DEBUG ((DEBUG_INFO, "| %4x  | %4x       %2x        %2x          %2x       %4x     ( %x| %x) %8x         %4x     |\n",\r
-        Index, CpuCacheInfo[Index].Package, CpuCacheInfo[Index].CoreType, CpuCacheInfo[Index].CacheLevel,\r
-        CpuCacheInfo[Index].CacheType, CpuCacheInfo[Index].CacheWays, CpuCacheInfo[Index].FullyAssociativeCache,\r
-        CpuCacheInfo[Index].DirectMappedCache, CpuCacheInfo[Index].CacheSizeinKB, CpuCacheInfo[Index].CacheCount));\r
+    DEBUG ((\r
+      DEBUG_INFO,\r
+      "| %4x  | %4x       %2x        %2x          %2x       %4x     ( %x| %x) %8x         %4x     |\n",\r
+      Index,\r
+      CpuCacheInfo[Index].Package,\r
+      CpuCacheInfo[Index].CoreType,\r
+      CpuCacheInfo[Index].CacheLevel,\r
+      CpuCacheInfo[Index].CacheType,\r
+      CpuCacheInfo[Index].CacheWays,\r
+      CpuCacheInfo[Index].FullyAssociativeCache,\r
+      CpuCacheInfo[Index].DirectMappedCache,\r
+      CpuCacheInfo[Index].CacheSizeinKB,\r
+      CpuCacheInfo[Index].CacheCount\r
+      ));\r
   }\r
 \r
   DEBUG ((DEBUG_INFO, "+-------+--------------------------------------------------------------------------------------+\n"));\r
@@ -50,24 +60,24 @@ CpuCacheInfoPrintCpuCacheInfoTable (
 INTN\r
 EFIAPI\r
 CpuCacheInfoCompare (\r
-  IN CONST VOID             *Buffer1,\r
-  IN CONST VOID             *Buffer2\r
+  IN CONST VOID  *Buffer1,\r
+  IN CONST VOID  *Buffer2\r
   )\r
 {\r
-  CPU_CACHE_INFO_COMPARATOR Comparator1, Comparator2;\r
+  CPU_CACHE_INFO_COMPARATOR  Comparator1, Comparator2;\r
 \r
   ZeroMem (&Comparator1, sizeof (Comparator1));\r
   ZeroMem (&Comparator2, sizeof (Comparator2));\r
 \r
-  Comparator1.Bits.Package    = ((CPU_CACHE_INFO*)Buffer1)->Package;\r
-  Comparator1.Bits.CoreType   = ((CPU_CACHE_INFO*)Buffer1)->CoreType;\r
-  Comparator1.Bits.CacheLevel = ((CPU_CACHE_INFO*)Buffer1)->CacheLevel;\r
-  Comparator1.Bits.CacheType  = ((CPU_CACHE_INFO*)Buffer1)->CacheType;\r
+  Comparator1.Bits.Package    = ((CPU_CACHE_INFO *)Buffer1)->Package;\r
+  Comparator1.Bits.CoreType   = ((CPU_CACHE_INFO *)Buffer1)->CoreType;\r
+  Comparator1.Bits.CacheLevel = ((CPU_CACHE_INFO *)Buffer1)->CacheLevel;\r
+  Comparator1.Bits.CacheType  = ((CPU_CACHE_INFO *)Buffer1)->CacheType;\r
 \r
-  Comparator2.Bits.Package    = ((CPU_CACHE_INFO*)Buffer2)->Package;\r
-  Comparator2.Bits.CoreType   = ((CPU_CACHE_INFO*)Buffer2)->CoreType;\r
-  Comparator2.Bits.CacheLevel = ((CPU_CACHE_INFO*)Buffer2)->CacheLevel;\r
-  Comparator2.Bits.CacheType  = ((CPU_CACHE_INFO*)Buffer2)->CacheType;\r
+  Comparator2.Bits.Package    = ((CPU_CACHE_INFO *)Buffer2)->Package;\r
+  Comparator2.Bits.CoreType   = ((CPU_CACHE_INFO *)Buffer2)->CoreType;\r
+  Comparator2.Bits.CacheLevel = ((CPU_CACHE_INFO *)Buffer2)->CacheLevel;\r
+  Comparator2.Bits.CacheType  = ((CPU_CACHE_INFO *)Buffer2)->CacheType;\r
 \r
   if (Comparator1.Uint64 == Comparator2.Uint64) {\r
     return 0;\r
@@ -89,15 +99,15 @@ CpuCacheInfoCompare (
 **/\r
 UINT32\r
 CpuCacheInfoGetNumberOfPackages (\r
-  IN CPUID_PROCESSOR_INFO   *ProcessorInfo,\r
-  IN UINTN                  NumberOfProcessors,\r
-  IN OUT UINT32             *Package\r
+  IN CPUID_PROCESSOR_INFO  *ProcessorInfo,\r
+  IN UINTN                 NumberOfProcessors,\r
+  IN OUT UINT32            *Package\r
   )\r
 {\r
-  UINTN                     ProcessorIndex;\r
-  UINT32                    PackageIndex;\r
-  UINT32                    PackageCount;\r
-  UINT32                    CurrentPackage;\r
+  UINTN   ProcessorIndex;\r
+  UINT32  PackageIndex;\r
+  UINT32  PackageCount;\r
+  UINT32  CurrentPackage;\r
 \r
   PackageCount = 0;\r
 \r
@@ -135,21 +145,21 @@ CpuCacheInfoGetNumberOfPackages (
   @retval  Return the number of CoreType of requested package.\r
 **/\r
 UINTN\r
-CpuCacheInfoGetNumberOfCoreTypePerPackage(\r
-  IN CPUID_PROCESSOR_INFO   *ProcessorInfo,\r
-  IN UINTN                  NumberOfProcessors,\r
-  IN UINTN                  Package\r
+CpuCacheInfoGetNumberOfCoreTypePerPackage (\r
+  IN CPUID_PROCESSOR_INFO  *ProcessorInfo,\r
+  IN UINTN                 NumberOfProcessors,\r
+  IN UINTN                 Package\r
   )\r
 {\r
-  UINTN                     ProcessorIndex;\r
+  UINTN  ProcessorIndex;\r
   //\r
   // Core Type value comes from CPUID.1Ah.EAX[31:24].\r
   // So max number of core types should be MAX_UINT8.\r
   //\r
-  UINT8                     CoreType[MAX_UINT8];\r
-  UINTN                     CoreTypeIndex;\r
-  UINTN                     CoreTypeCount;\r
-  UINT8                     CurrentCoreType;\r
+  UINT8  CoreType[MAX_UINT8];\r
+  UINTN  CoreTypeIndex;\r
+  UINTN  CoreTypeCount;\r
+  UINT8  CurrentCoreType;\r
 \r
   //\r
   // CoreType array is empty.\r
@@ -192,23 +202,23 @@ CpuCacheInfoGetNumberOfCoreTypePerPackage(
 VOID\r
 EFIAPI\r
 CpuCacheInfoCollectCoreAndCacheData (\r
-  IN OUT VOID               *Buffer\r
+  IN OUT VOID  *Buffer\r
   )\r
 {\r
-  UINTN                     ProcessorIndex;\r
-  UINT32                    CpuidMaxInput;\r
-  UINT8                     CacheParamLeafIndex;\r
-  CPUID_CACHE_PARAMS_EAX    CacheParamEax;\r
-  CPUID_CACHE_PARAMS_EBX    CacheParamEbx;\r
-  UINT32                    CacheParamEcx;\r
-  CPUID_CACHE_PARAMS_EDX    CacheParamEdx;\r
-  CPUID_NATIVE_MODEL_ID_AND_CORE_TYPE_EAX   NativeModelIdAndCoreTypeEax;\r
-  COLLECT_CPUID_CACHE_DATA_CONTEXT  *Context;\r
-  CPUID_CACHE_DATA          *CacheData;\r
-\r
-  Context = (COLLECT_CPUID_CACHE_DATA_CONTEXT *)Buffer;\r
+  UINTN                                    ProcessorIndex;\r
+  UINT32                                   CpuidMaxInput;\r
+  UINT8                                    CacheParamLeafIndex;\r
+  CPUID_CACHE_PARAMS_EAX                   CacheParamEax;\r
+  CPUID_CACHE_PARAMS_EBX                   CacheParamEbx;\r
+  UINT32                                   CacheParamEcx;\r
+  CPUID_CACHE_PARAMS_EDX                   CacheParamEdx;\r
+  CPUID_NATIVE_MODEL_ID_AND_CORE_TYPE_EAX  NativeModelIdAndCoreTypeEax;\r
+  COLLECT_CPUID_CACHE_DATA_CONTEXT         *Context;\r
+  CPUID_CACHE_DATA                         *CacheData;\r
+\r
+  Context        = (COLLECT_CPUID_CACHE_DATA_CONTEXT *)Buffer;\r
   ProcessorIndex = CpuCacheInfoWhoAmI (Context->MpServices);\r
-  CacheData = &Context->CacheData[MAX_NUM_OF_CACHE_PARAMS_LEAF * ProcessorIndex];\r
+  CacheData      = &Context->CacheData[MAX_NUM_OF_CACHE_PARAMS_LEAF * ProcessorIndex];\r
 \r
   AsmCpuid (CPUID_SIGNATURE, &CpuidMaxInput, NULL, NULL, NULL);\r
 \r
@@ -218,7 +228,7 @@ CpuCacheInfoCollectCoreAndCacheData (
   Context->ProcessorInfo[ProcessorIndex].CoreType = 0;\r
   if (CpuidMaxInput >= CPUID_HYBRID_INFORMATION) {\r
     AsmCpuidEx (CPUID_HYBRID_INFORMATION, CPUID_HYBRID_INFORMATION_MAIN_LEAF, &NativeModelIdAndCoreTypeEax.Uint32, NULL, NULL, NULL);\r
-    Context->ProcessorInfo[ProcessorIndex].CoreType = (UINT8) NativeModelIdAndCoreTypeEax.Bits.CoreType;\r
+    Context->ProcessorInfo[ProcessorIndex].CoreType = (UINT8)NativeModelIdAndCoreTypeEax.Bits.CoreType;\r
   }\r
 \r
   //\r
@@ -240,7 +250,7 @@ CpuCacheInfoCollectCoreAndCacheData (
     CacheData[CacheParamLeafIndex].DirectMappedCache     = (UINT8)(CacheParamEdx.Bits.ComplexCacheIndexing == 0);\r
     CacheData[CacheParamLeafIndex].CacheShareBits        = (UINT16)CacheParamEax.Bits.MaximumAddressableIdsForLogicalProcessors;\r
     CacheData[CacheParamLeafIndex].CacheSizeinKB         = (CacheParamEbx.Bits.Ways + 1) *\r
-        (CacheParamEbx.Bits.LinePartitions + 1) * (CacheParamEbx.Bits.LineSize + 1) * (CacheParamEcx + 1) / SIZE_1KB;\r
+                                                           (CacheParamEbx.Bits.LinePartitions + 1) * (CacheParamEbx.Bits.LineSize + 1) * (CacheParamEcx + 1) / SIZE_1KB;\r
 \r
     CacheParamLeafIndex++;\r
   }\r
@@ -264,25 +274,25 @@ CpuCacheInfoCollectCoreAndCacheData (
 **/\r
 EFI_STATUS\r
 CpuCacheInfoCollectCpuCacheInfoData (\r
-  IN CPUID_CACHE_DATA       *CacheData,\r
-  IN CPUID_PROCESSOR_INFO   *ProcessorInfo,\r
-  IN UINTN                  NumberOfProcessors,\r
-  IN OUT CPU_CACHE_INFO     *CacheInfo,\r
-  IN OUT UINTN              *CacheInfoCount\r
+  IN CPUID_CACHE_DATA      *CacheData,\r
+  IN CPUID_PROCESSOR_INFO  *ProcessorInfo,\r
+  IN UINTN                 NumberOfProcessors,\r
+  IN OUT CPU_CACHE_INFO    *CacheInfo,\r
+  IN OUT UINTN             *CacheInfoCount\r
   )\r
 {\r
-  EFI_STATUS                Status;\r
-  UINT32                    NumberOfPackage;\r
-  UINT32                    Package[MAX_NUM_OF_PACKAGE];\r
-  UINTN                     PackageIndex;\r
-  UINTN                     TotalNumberOfCoreType;\r
-  UINTN                     MaxCacheInfoCount;\r
-  CPU_CACHE_INFO            *LocalCacheInfo;\r
-  UINTN                     CacheInfoIndex;\r
-  UINTN                     LocalCacheInfoCount;\r
-  UINTN                     Index;\r
-  UINTN                     NextIndex;\r
-  CPU_CACHE_INFO            SortBuffer;\r
+  EFI_STATUS      Status;\r
+  UINT32          NumberOfPackage;\r
+  UINT32          Package[MAX_NUM_OF_PACKAGE];\r
+  UINTN           PackageIndex;\r
+  UINTN           TotalNumberOfCoreType;\r
+  UINTN           MaxCacheInfoCount;\r
+  CPU_CACHE_INFO  *LocalCacheInfo;\r
+  UINTN           CacheInfoIndex;\r
+  UINTN           LocalCacheInfoCount;\r
+  UINTN           Index;\r
+  UINTN           NextIndex;\r
+  CPU_CACHE_INFO  SortBuffer;\r
 \r
   //\r
   // Get number of Packages and Package ID.\r
@@ -299,7 +309,7 @@ CpuCacheInfoCollectCpuCacheInfoData (
   }\r
 \r
   MaxCacheInfoCount = TotalNumberOfCoreType * MAX_NUM_OF_CACHE_PARAMS_LEAF;\r
-  LocalCacheInfo = AllocatePages (EFI_SIZE_TO_PAGES (MaxCacheInfoCount * sizeof (*LocalCacheInfo)));\r
+  LocalCacheInfo    = AllocatePages (EFI_SIZE_TO_PAGES (MaxCacheInfoCount * sizeof (*LocalCacheInfo)));\r
   ASSERT (LocalCacheInfo != NULL);\r
   if (LocalCacheInfo == NULL) {\r
     return EFI_OUT_OF_RESOURCES;\r
@@ -320,12 +330,13 @@ CpuCacheInfoCollectCpuCacheInfoData (
         continue;\r
       }\r
 \r
-      if (CacheData[Index].CacheLevel == CacheData[NextIndex].CacheLevel &&\r
-          CacheData[Index].CacheType == CacheData[NextIndex].CacheType &&\r
-          ProcessorInfo[Index / MAX_NUM_OF_CACHE_PARAMS_LEAF].Package == ProcessorInfo[NextIndex / MAX_NUM_OF_CACHE_PARAMS_LEAF].Package &&\r
-          ProcessorInfo[Index / MAX_NUM_OF_CACHE_PARAMS_LEAF].CoreType == ProcessorInfo[NextIndex / MAX_NUM_OF_CACHE_PARAMS_LEAF].CoreType &&\r
-          (ProcessorInfo[Index / MAX_NUM_OF_CACHE_PARAMS_LEAF].ApicId & ~CacheData[Index].CacheShareBits) ==\r
-          (ProcessorInfo[NextIndex / MAX_NUM_OF_CACHE_PARAMS_LEAF].ApicId & ~CacheData[NextIndex].CacheShareBits)) {\r
+      if ((CacheData[Index].CacheLevel == CacheData[NextIndex].CacheLevel) &&\r
+          (CacheData[Index].CacheType == CacheData[NextIndex].CacheType) &&\r
+          (ProcessorInfo[Index / MAX_NUM_OF_CACHE_PARAMS_LEAF].Package == ProcessorInfo[NextIndex / MAX_NUM_OF_CACHE_PARAMS_LEAF].Package) &&\r
+          (ProcessorInfo[Index / MAX_NUM_OF_CACHE_PARAMS_LEAF].CoreType == ProcessorInfo[NextIndex / MAX_NUM_OF_CACHE_PARAMS_LEAF].CoreType) &&\r
+          ((ProcessorInfo[Index / MAX_NUM_OF_CACHE_PARAMS_LEAF].ApicId & ~CacheData[Index].CacheShareBits) ==\r
+           (ProcessorInfo[NextIndex / MAX_NUM_OF_CACHE_PARAMS_LEAF].ApicId & ~CacheData[NextIndex].CacheShareBits)))\r
+      {\r
         CacheData[NextIndex].CacheSizeinKB = 0; // uses the sharing cache\r
       }\r
     }\r
@@ -334,10 +345,11 @@ CpuCacheInfoCollectCpuCacheInfoData (
     // For the cache that already exists in LocalCacheInfo, increase its CacheCount.\r
     //\r
     for (CacheInfoIndex = 0; CacheInfoIndex < LocalCacheInfoCount; CacheInfoIndex++) {\r
-      if (LocalCacheInfo[CacheInfoIndex].Package    == ProcessorInfo[Index / MAX_NUM_OF_CACHE_PARAMS_LEAF].Package &&\r
-          LocalCacheInfo[CacheInfoIndex].CoreType   == ProcessorInfo[Index / MAX_NUM_OF_CACHE_PARAMS_LEAF].CoreType &&\r
-          LocalCacheInfo[CacheInfoIndex].CacheLevel == CacheData[Index].CacheLevel &&\r
-          LocalCacheInfo[CacheInfoIndex].CacheType  == CacheData[Index].CacheType) {\r
+      if ((LocalCacheInfo[CacheInfoIndex].Package    == ProcessorInfo[Index / MAX_NUM_OF_CACHE_PARAMS_LEAF].Package) &&\r
+          (LocalCacheInfo[CacheInfoIndex].CoreType   == ProcessorInfo[Index / MAX_NUM_OF_CACHE_PARAMS_LEAF].CoreType) &&\r
+          (LocalCacheInfo[CacheInfoIndex].CacheLevel == CacheData[Index].CacheLevel) &&\r
+          (LocalCacheInfo[CacheInfoIndex].CacheType  == CacheData[Index].CacheType))\r
+      {\r
         LocalCacheInfo[CacheInfoIndex].CacheCount++;\r
         break;\r
       }\r
@@ -370,11 +382,11 @@ CpuCacheInfoCollectCpuCacheInfoData (
     //\r
     // Sort LocalCacheInfo array by CPU package ID, core type, cache level and cache type.\r
     //\r
-    QuickSort (LocalCacheInfo, LocalCacheInfoCount, sizeof (*LocalCacheInfo), CpuCacheInfoCompare, (VOID*) &SortBuffer);\r
+    QuickSort (LocalCacheInfo, LocalCacheInfoCount, sizeof (*LocalCacheInfo), CpuCacheInfoCompare, (VOID *)&SortBuffer);\r
     CopyMem (CacheInfo, LocalCacheInfo, sizeof (*CacheInfo) * LocalCacheInfoCount);\r
     DEBUG_CODE (\r
       CpuCacheInfoPrintCpuCacheInfoTable (CacheInfo, LocalCacheInfoCount);\r
-    );\r
+      );\r
     Status = EFI_SUCCESS;\r
   }\r
 \r
@@ -405,23 +417,23 @@ CpuCacheInfoCollectCpuCacheInfoData (
 EFI_STATUS\r
 EFIAPI\r
 GetCpuCacheInfo (\r
-  IN OUT CPU_CACHE_INFO     *CpuCacheInfo,\r
-  IN OUT UINTN              *CpuCacheInfoCount\r
+  IN OUT CPU_CACHE_INFO  *CpuCacheInfo,\r
+  IN OUT UINTN           *CpuCacheInfoCount\r
   )\r
 {\r
-  EFI_STATUS                Status;\r
-  UINT32                    CpuidMaxInput;\r
-  UINT32                    NumberOfProcessors;\r
-  UINTN                     CacheDataCount;\r
-  UINTN                     ProcessorIndex;\r
-  EFI_PROCESSOR_INFORMATION ProcessorInfo;\r
+  EFI_STATUS                        Status;\r
+  UINT32                            CpuidMaxInput;\r
+  UINT32                            NumberOfProcessors;\r
+  UINTN                             CacheDataCount;\r
+  UINTN                             ProcessorIndex;\r
+  EFI_PROCESSOR_INFORMATION         ProcessorInfo;\r
   COLLECT_CPUID_CACHE_DATA_CONTEXT  Context;\r
 \r
   if (CpuCacheInfoCount == NULL) {\r
     return EFI_INVALID_PARAMETER;\r
   }\r
 \r
-  if (*CpuCacheInfoCount != 0 && CpuCacheInfo == NULL) {\r
+  if ((*CpuCacheInfoCount != 0) && (CpuCacheInfo == NULL)) {\r
     return EFI_INVALID_PARAMETER;\r
   }\r
 \r
@@ -445,13 +457,14 @@ GetCpuCacheInfo (
   if (Context.ProcessorInfo == NULL) {\r
     return EFI_OUT_OF_RESOURCES;\r
   }\r
+\r
   //\r
   // Initialize COLLECT_CPUID_CACHE_DATA_CONTEXT.CacheData.\r
   // CacheData array consists of CPUID_CACHE_DATA data structure for each Cpuid Cache Parameter Leaf\r
   // per logical processor. The array begin with data of each Cache Parameter Leaf of processor 0, followed\r
   // by data of each Cache Parameter Leaf of processor 1 ...\r
   //\r
-  CacheDataCount = NumberOfProcessors * MAX_NUM_OF_CACHE_PARAMS_LEAF;\r
+  CacheDataCount    = NumberOfProcessors * MAX_NUM_OF_CACHE_PARAMS_LEAF;\r
   Context.CacheData = AllocatePages (EFI_SIZE_TO_PAGES (CacheDataCount * sizeof (*Context.CacheData)));\r
   ASSERT (Context.CacheData != NULL);\r
   if (Context.CacheData == NULL) {\r
@@ -467,7 +480,7 @@ GetCpuCacheInfo (
   for (ProcessorIndex = 0; ProcessorIndex < NumberOfProcessors; ProcessorIndex++) {\r
     CpuCacheInfoGetProcessorInfo (Context.MpServices, ProcessorIndex, &ProcessorInfo);\r
     Context.ProcessorInfo[ProcessorIndex].Package = ProcessorInfo.Location.Package;\r
-    Context.ProcessorInfo[ProcessorIndex].ApicId  = (UINT32) ProcessorInfo.ProcessorId;\r
+    Context.ProcessorInfo[ProcessorIndex].ApicId  = (UINT32)ProcessorInfo.ProcessorId;\r
   }\r
 \r
   //\r

diff --git a/UefiCpuPkg/Library/CpuCacheInfoLib/DxeCpuCacheInfoLib.c b/UefiCpuPkg/Library/CpuCacheInfoLib/DxeCpuCacheInfoLib.c
index d810294e2120c4e7ca1e52441a1a80a4cd0420ad..ebf2db86ba1e8a909e30000397c86bf6fe251ad8 100644 (file)
--- a/UefiCpuPkg/Library/CpuCacheInfoLib/DxeCpuCacheInfoLib.c
+++ b/UefiCpuPkg/Library/CpuCacheInfoLib/DxeCpuCacheInfoLib.c
@@ -23,10 +23,10 @@
 **/\r
 EFI_STATUS\r
 CpuCacheInfoGetMpServices (\r
-  OUT MP_SERVICES           *MpServices\r
+  OUT MP_SERVICES  *MpServices\r
   )\r
 {\r
-  EFI_STATUS                Status;\r
+  EFI_STATUS  Status;\r
 \r
   Status = gBS->LocateProtocol (&gEfiMpServiceProtocolGuid, NULL, (VOID **)&MpServices->Protocol);\r
   ASSERT_EFI_ERROR (Status);\r
@@ -43,12 +43,12 @@ CpuCacheInfoGetMpServices (
 **/\r
 VOID\r
 CpuCacheInfoStartupAllCPUs (\r
-  IN MP_SERVICES            MpServices,\r
-  IN EFI_AP_PROCEDURE       Procedure,\r
-  IN VOID                   *ProcedureArgument\r
+  IN MP_SERVICES       MpServices,\r
+  IN EFI_AP_PROCEDURE  Procedure,\r
+  IN VOID              *ProcedureArgument\r
   )\r
 {\r
-  EFI_STATUS                Status;\r
+  EFI_STATUS  Status;\r
 \r
   Status = MpServices.Protocol->StartupAllAPs (MpServices.Protocol, Procedure, FALSE, NULL, 0, ProcedureArgument, NULL);\r
   if (Status == EFI_NOT_STARTED) {\r
@@ -58,6 +58,7 @@ CpuCacheInfoStartupAllCPUs (
     //\r
     Status = EFI_SUCCESS;\r
   }\r
+\r
   ASSERT_EFI_ERROR (Status);\r
 \r
   Procedure (ProcedureArgument);\r
@@ -72,12 +73,12 @@ CpuCacheInfoStartupAllCPUs (
 **/\r
 VOID\r
 CpuCacheInfoGetProcessorInfo (\r
-  IN MP_SERVICES                MpServices,\r
-  IN UINTN                      ProcessorNum,\r
-  OUT EFI_PROCESSOR_INFORMATION *ProcessorInfo\r
+  IN MP_SERVICES                 MpServices,\r
+  IN UINTN                       ProcessorNum,\r
+  OUT EFI_PROCESSOR_INFORMATION  *ProcessorInfo\r
   )\r
 {\r
-  EFI_STATUS                Status;\r
+  EFI_STATUS  Status;\r
 \r
   Status = MpServices.Protocol->GetProcessorInfo (MpServices.Protocol, ProcessorNum, ProcessorInfo);\r
   ASSERT_EFI_ERROR (Status);\r
@@ -92,11 +93,11 @@ CpuCacheInfoGetProcessorInfo (
 **/\r
 UINT32\r
 CpuCacheInfoWhoAmI (\r
-  IN MP_SERVICES            MpServices\r
+  IN MP_SERVICES  MpServices\r
   )\r
 {\r
-  EFI_STATUS                Status;\r
-  UINTN                     ProcessorNum;\r
+  EFI_STATUS  Status;\r
+  UINTN       ProcessorNum;\r
 \r
   Status = MpServices.Protocol->WhoAmI (MpServices.Protocol, &ProcessorNum);\r
   ASSERT_EFI_ERROR (Status);\r
@@ -113,12 +114,12 @@ CpuCacheInfoWhoAmI (
 **/\r
 UINT32\r
 CpuCacheInfoGetNumberOfProcessors (\r
-  IN MP_SERVICES            MpServices\r
+  IN MP_SERVICES  MpServices\r
   )\r
 {\r
-  EFI_STATUS                Status;\r
-  UINTN                     NumberOfProcessor;\r
-  UINTN                     NumberOfEnabledProcessor;\r
+  EFI_STATUS  Status;\r
+  UINTN       NumberOfProcessor;\r
+  UINTN       NumberOfEnabledProcessor;\r
 \r
   Status = MpServices.Protocol->GetNumberOfProcessors (MpServices.Protocol, &NumberOfProcessor, &NumberOfEnabledProcessor);\r
   ASSERT_EFI_ERROR (Status);\r

diff --git a/UefiCpuPkg/Library/CpuCacheInfoLib/InternalCpuCacheInfoLib.h b/UefiCpuPkg/Library/CpuCacheInfoLib/InternalCpuCacheInfoLib.h
index 829a9f43ce49da4ff662148e12f0cd9311244917..953b3d66b1bf5e56e5d9ed41fb7a6aba24c1747f 100644 (file)
--- a/UefiCpuPkg/Library/CpuCacheInfoLib/InternalCpuCacheInfoLib.h
+++ b/UefiCpuPkg/Library/CpuCacheInfoLib/InternalCpuCacheInfoLib.h
@@ -25,24 +25,24 @@ typedef union {
     // Type of the cache that this package's this type of logical processor corresponds to.\r
     // Value = CPUID.04h:EAX[04:00]\r
     //\r
-    UINT32        CacheType : 5;\r
+    UINT32    CacheType  : 5;\r
     //\r
     // Level of the cache that this package's this type of logical processor corresponds to.\r
     // Value = CPUID.04h:EAX[07:05]\r
     //\r
-    UINT32        CacheLevel : 3;\r
+    UINT32    CacheLevel : 3;\r
     //\r
     // Core type of logical processor.\r
     // Value = CPUID.1Ah:EAX[31:24]\r
     //\r
-    UINT32        CoreType : 8;\r
-    UINT32        Reserved : 16;\r
+    UINT32    CoreType   : 8;\r
+    UINT32    Reserved   : 16;\r
     //\r
     // Package number.\r
     //\r
-    UINT32        Package;\r
+    UINT32    Package;\r
   } Bits;\r
-  UINT64        Uint64;\r
+  UINT64    Uint64;\r
 } CPU_CACHE_INFO_COMPARATOR;\r
 \r
 typedef struct {\r
@@ -50,17 +50,17 @@ typedef struct {
   // Package ID, the information comes from\r
   // EFI_CPU_PHYSICAL_LOCATION.Package\r
   //\r
-  UINT32                    Package;\r
+  UINT32    Package;\r
   //\r
   // APIC ID, the information comes from\r
   // EFI_PROCESSOR_INFORMATION.ProcessorId\r
   //\r
-  UINT32                    ApicId;\r
+  UINT32    ApicId;\r
   //\r
   // Core type of logical processor.\r
   // Value = CPUID.1Ah:EAX[31:24]\r
   //\r
-  UINT8                     CoreType;\r
+  UINT8     CoreType;\r
 } CPUID_PROCESSOR_INFO;\r
 \r
 typedef struct {\r
@@ -68,39 +68,39 @@ typedef struct {
   // Level of the cache.\r
   // Value = CPUID.04h:EAX[07:05]\r
   //\r
-  UINT8                     CacheLevel : 3;\r
+  UINT8     CacheLevel            : 3;\r
   //\r
   // Type of the cache.\r
   // Value = CPUID.04h:EAX[04:00]\r
   //\r
-  UINT8                     CacheType : 5;\r
+  UINT8     CacheType             : 5;\r
   //\r
   // Ways of associativity.\r
   // Value = CPUID.04h:EBX[31:22]\r
   //\r
-  UINT16                    CacheWays : 10;\r
+  UINT16    CacheWays             : 10;\r
   //\r
   // Fully associative cache.\r
   // Value = CPUID.04h:EAX[09]\r
   //\r
-  UINT16                    FullyAssociativeCache : 1;\r
+  UINT16    FullyAssociativeCache : 1;\r
   //\r
   // Direct mapped cache.\r
   // Value = CPUID.04h:EDX[02]\r
   //\r
-  UINT16                    DirectMappedCache : 1;\r
-  UINT16                    Reserved : 4;\r
+  UINT16    DirectMappedCache     : 1;\r
+  UINT16    Reserved              : 4;\r
   //\r
   // Cache share bits.\r
   // Value = CPUID.04h:EAX[25:14]\r
   //\r
-  UINT16                    CacheShareBits;\r
+  UINT16    CacheShareBits;\r
   //\r
   // Size of single cache.\r
   // Value = (CPUID.04h:EBX[31:22] + 1) * (CPUID.04h:EBX[21:12] + 1) *\r
   //         (CPUID.04h:EBX[11:00] + 1) * (CPUID.04h:ECX[31:00] + 1)\r
   //\r
-  UINT32                    CacheSizeinKB;\r
+  UINT32    CacheSizeinKB;\r
 } CPUID_CACHE_DATA;\r
 \r
 typedef union {\r
@@ -109,24 +109,23 @@ typedef union {
 } MP_SERVICES;\r
 \r
 typedef struct {\r
-  MP_SERVICES               MpServices;\r
-  CPUID_PROCESSOR_INFO      *ProcessorInfo;\r
-  CPUID_CACHE_DATA          *CacheData;\r
+  MP_SERVICES             MpServices;\r
+  CPUID_PROCESSOR_INFO    *ProcessorInfo;\r
+  CPUID_CACHE_DATA        *CacheData;\r
 } COLLECT_CPUID_CACHE_DATA_CONTEXT;\r
 \r
-\r
 /*\r
   Defines the maximum count of Deterministic Cache Parameters Leaf of all APs and BSP.\r
   To save boot time, skip starting up all APs to calculate each AP's count of Deterministic\r
   Cache Parameters Leaf, so use a definition instead.\r
   Anyway, definition value will be checked in CpuCacheInfoCollectCoreAndCacheData function.\r
 */\r
-#define MAX_NUM_OF_CACHE_PARAMS_LEAF    6\r
+#define MAX_NUM_OF_CACHE_PARAMS_LEAF  6\r
 \r
 /*\r
   Defines the maximum count of packages.\r
 */\r
-#define MAX_NUM_OF_PACKAGE              100\r
+#define MAX_NUM_OF_PACKAGE  100\r
 \r
 /**\r
   Get EDKII_PEI_MP_SERVICES2_PPI or EFI_MP_SERVICES_PROTOCOL pointer.\r
@@ -139,7 +138,7 @@ typedef struct {
 **/\r
 EFI_STATUS\r
 CpuCacheInfoGetMpServices (\r
-  OUT MP_SERVICES           *MpServices\r
+  OUT MP_SERVICES  *MpServices\r
   );\r
 \r
 /**\r
@@ -151,9 +150,9 @@ CpuCacheInfoGetMpServices (
 **/\r
 VOID\r
 CpuCacheInfoStartupAllCPUs (\r
-  IN MP_SERVICES            MpServices,\r
-  IN EFI_AP_PROCEDURE       Procedure,\r
-  IN VOID                   *ProcedureArgument\r
+  IN MP_SERVICES       MpServices,\r
+  IN EFI_AP_PROCEDURE  Procedure,\r
+  IN VOID              *ProcedureArgument\r
   );\r
 \r
 /**\r
@@ -165,9 +164,9 @@ CpuCacheInfoStartupAllCPUs (
 **/\r
 VOID\r
 CpuCacheInfoGetProcessorInfo (\r
-  IN MP_SERVICES                MpServices,\r
-  IN UINTN                      ProcessorNum,\r
-  OUT EFI_PROCESSOR_INFORMATION *ProcessorInfo\r
+  IN MP_SERVICES                 MpServices,\r
+  IN UINTN                       ProcessorNum,\r
+  OUT EFI_PROCESSOR_INFORMATION  *ProcessorInfo\r
   );\r
 \r
 /**\r
@@ -179,7 +178,7 @@ CpuCacheInfoGetProcessorInfo (
 **/\r
 UINT32\r
 CpuCacheInfoWhoAmI (\r
-  IN MP_SERVICES            MpServices\r
+  IN MP_SERVICES  MpServices\r
   );\r
 \r
 /**\r
@@ -191,6 +190,7 @@ CpuCacheInfoWhoAmI (
 **/\r
 UINT32\r
 CpuCacheInfoGetNumberOfProcessors (\r
-  IN MP_SERVICES            MpServices\r
+  IN MP_SERVICES  MpServices\r
   );\r
+\r
 #endif\r

diff --git a/UefiCpuPkg/Library/CpuCacheInfoLib/PeiCpuCacheInfoLib.c b/UefiCpuPkg/Library/CpuCacheInfoLib/PeiCpuCacheInfoLib.c
index 06c160421b00935810e268c721c4aebbba8e4cd7..ea262d8f0216d00e60f05924e1f09de9d4ae3745 100644 (file)
--- a/UefiCpuPkg/Library/CpuCacheInfoLib/PeiCpuCacheInfoLib.c
+++ b/UefiCpuPkg/Library/CpuCacheInfoLib/PeiCpuCacheInfoLib.c
@@ -24,10 +24,10 @@
 **/\r
 EFI_STATUS\r
 CpuCacheInfoGetMpServices (\r
-  OUT MP_SERVICES           *MpServices\r
+  OUT MP_SERVICES  *MpServices\r
   )\r
 {\r
-  EFI_STATUS                Status;\r
+  EFI_STATUS  Status;\r
 \r
   Status = PeiServicesLocatePpi (&gEdkiiPeiMpServices2PpiGuid, 0, NULL, (VOID **)&MpServices->Ppi);\r
   ASSERT_EFI_ERROR (Status);\r
@@ -44,12 +44,12 @@ CpuCacheInfoGetMpServices (
 **/\r
 VOID\r
 CpuCacheInfoStartupAllCPUs (\r
-  IN MP_SERVICES            MpServices,\r
-  IN EFI_AP_PROCEDURE       Procedure,\r
-  IN VOID                   *ProcedureArgument\r
+  IN MP_SERVICES       MpServices,\r
+  IN EFI_AP_PROCEDURE  Procedure,\r
+  IN VOID              *ProcedureArgument\r
   )\r
 {\r
-  EFI_STATUS                Status;\r
+  EFI_STATUS  Status;\r
 \r
   Status = MpServices.Ppi->StartupAllCPUs (MpServices.Ppi, Procedure, 0, ProcedureArgument);\r
   ASSERT_EFI_ERROR (Status);\r
@@ -64,12 +64,12 @@ CpuCacheInfoStartupAllCPUs (
 **/\r
 VOID\r
 CpuCacheInfoGetProcessorInfo (\r
-  IN MP_SERVICES                MpServices,\r
-  IN UINTN                      ProcessorNum,\r
-  OUT EFI_PROCESSOR_INFORMATION *ProcessorInfo\r
+  IN MP_SERVICES                 MpServices,\r
+  IN UINTN                       ProcessorNum,\r
+  OUT EFI_PROCESSOR_INFORMATION  *ProcessorInfo\r
   )\r
 {\r
-  EFI_STATUS                Status;\r
+  EFI_STATUS  Status;\r
 \r
   Status = MpServices.Ppi->GetProcessorInfo (MpServices.Ppi, ProcessorNum, ProcessorInfo);\r
   ASSERT_EFI_ERROR (Status);\r
@@ -84,11 +84,11 @@ CpuCacheInfoGetProcessorInfo (
 **/\r
 UINT32\r
 CpuCacheInfoWhoAmI (\r
-  IN MP_SERVICES            MpServices\r
+  IN MP_SERVICES  MpServices\r
   )\r
 {\r
-  EFI_STATUS                Status;\r
-  UINTN                     ProcessorNum;\r
+  EFI_STATUS  Status;\r
+  UINTN       ProcessorNum;\r
 \r
   Status = MpServices.Ppi->WhoAmI (MpServices.Ppi, &ProcessorNum);\r
   ASSERT_EFI_ERROR (Status);\r
@@ -105,12 +105,12 @@ CpuCacheInfoWhoAmI (
 **/\r
 UINT32\r
 CpuCacheInfoGetNumberOfProcessors (\r
-  IN MP_SERVICES            MpServices\r
+  IN MP_SERVICES  MpServices\r
   )\r
 {\r
-  EFI_STATUS                Status;\r
-  UINTN                     NumberOfProcessor;\r
-  UINTN                     NumberOfEnabledProcessor;\r
+  EFI_STATUS  Status;\r
+  UINTN       NumberOfProcessor;\r
+  UINTN       NumberOfEnabledProcessor;\r
 \r
   Status = MpServices.Ppi->GetNumberOfProcessors (MpServices.Ppi, &NumberOfProcessor, &NumberOfEnabledProcessor);\r
   ASSERT_EFI_ERROR (Status);\r

diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/Aesni.c b/UefiCpuPkg/Library/CpuCommonFeaturesLib/Aesni.c
index 80a7df2957af3c952c096153d092877dffa01058..beda97e238009ae5635f6d67a0001a021bd7f6ec 100644 (file)
--- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/Aesni.c
+++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/Aesni.c
@@ -23,7 +23,7 @@ AesniGetConfigData (
   IN UINTN  NumberOfProcessors\r
   )\r
 {\r
-  UINT64                            *ConfigData;\r
+  UINT64  *ConfigData;\r
 \r
   ConfigData = AllocateZeroPool (sizeof (UINT64) * NumberOfProcessors);\r
   ASSERT (ConfigData != NULL);\r
@@ -54,14 +54,15 @@ AesniSupport (
   IN VOID                              *ConfigData  OPTIONAL\r
   )\r
 {\r
-  MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER   *MsrFeatureConfig;\r
+  MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER  *MsrFeatureConfig;\r
 \r
   if (CpuInfo->CpuIdVersionInfoEcx.Bits.AESNI == 1) {\r
-    MsrFeatureConfig = (MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER *) ConfigData;\r
+    MsrFeatureConfig = (MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER *)ConfigData;\r
     ASSERT (MsrFeatureConfig != NULL);\r
     MsrFeatureConfig[ProcessorNumber].Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_FEATURE_CONFIG);\r
     return TRUE;\r
   }\r
+\r
   return FALSE;\r
 }\r
 \r
@@ -91,7 +92,7 @@ AesniInitialize (
   IN BOOLEAN                           State\r
   )\r
 {\r
-  MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER   *MsrFeatureConfig;\r
+  MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER  *MsrFeatureConfig;\r
 \r
   //\r
   // SANDY_BRIDGE, SILVERMONT, XEON_5600, XEON_7, and XEON_PHI have the same MSR index,\r
@@ -102,7 +103,7 @@ AesniInitialize (
   // programming it.\r
   //\r
   if (CpuInfo->ProcessorInfo.Location.Thread == 0) {\r
-    MsrFeatureConfig = (MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER *) ConfigData;\r
+    MsrFeatureConfig = (MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER *)ConfigData;\r
     ASSERT (MsrFeatureConfig != NULL);\r
     if ((MsrFeatureConfig[ProcessorNumber].Bits.AESConfiguration & BIT0) == 0) {\r
       CPU_REGISTER_TABLE_WRITE_FIELD (\r
@@ -115,5 +116,6 @@ AesniInitialize (
         );\r
     }\r
   }\r
+\r
   return RETURN_SUCCESS;\r
 }\r

diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/C1e.c b/UefiCpuPkg/Library/CpuCommonFeaturesLib/C1e.c
index 98a34083701b98f96fb9be91beaf4a0910eafa78..bc09f8bc6242b13ba2981aa2060f6588092b1178 100644 (file)
--- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/C1e.c
+++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/C1e.c
@@ -66,7 +66,7 @@ C1eInitialize (
   // MSR_NEHALEM_POWER_CTL once for each package.\r
   //\r
   if ((CpuInfo->First.Thread == 0) || (CpuInfo->First.Core == 0)) {\r
-  return RETURN_SUCCESS;\r
+    return RETURN_SUCCESS;\r
   }\r
 \r
   CPU_REGISTER_TABLE_WRITE_FIELD (\r

diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/ClockModulation.c b/UefiCpuPkg/Library/CpuCommonFeaturesLib/ClockModulation.c
index 94d596605bf72c9c8df72f389b8c28edf822b06a..5874a99570ef37cb98c3e9f97814f8696174e5b1 100644 (file)
--- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/ClockModulation.c
+++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/ClockModulation.c
@@ -9,8 +9,8 @@
 #include "CpuCommonFeatures.h"\r
 \r
 typedef struct  {\r
-  CPUID_THERMAL_POWER_MANAGEMENT_EAX  ThermalPowerManagementEax;\r
-  MSR_IA32_CLOCK_MODULATION_REGISTER  ClockModulation;\r
+  CPUID_THERMAL_POWER_MANAGEMENT_EAX    ThermalPowerManagementEax;\r
+  MSR_IA32_CLOCK_MODULATION_REGISTER    ClockModulation;\r
 } CLOCK_MODULATION_CONFIG_DATA;\r
 \r
 /**\r
@@ -28,7 +28,7 @@ ClockModulationGetConfigData (
   IN UINTN  NumberOfProcessors\r
   )\r
 {\r
-  UINT32    *ConfigData;\r
+  UINT32  *ConfigData;\r
 \r
   ConfigData = AllocateZeroPool (sizeof (CLOCK_MODULATION_CONFIG_DATA) * NumberOfProcessors);\r
   ASSERT (ConfigData != NULL);\r
@@ -59,10 +59,10 @@ ClockModulationSupport (
   IN VOID                              *ConfigData  OPTIONAL\r
   )\r
 {\r
-  CLOCK_MODULATION_CONFIG_DATA         *CmConfigData;\r
+  CLOCK_MODULATION_CONFIG_DATA  *CmConfigData;\r
 \r
   if (CpuInfo->CpuIdVersionInfoEdx.Bits.ACPI == 1) {\r
-    CmConfigData = (CLOCK_MODULATION_CONFIG_DATA *) ConfigData;\r
+    CmConfigData = (CLOCK_MODULATION_CONFIG_DATA *)ConfigData;\r
     ASSERT (CmConfigData != NULL);\r
     AsmCpuid (\r
       CPUID_THERMAL_POWER_MANAGEMENT,\r
@@ -74,6 +74,7 @@ ClockModulationSupport (
     CmConfigData[ProcessorNumber].ClockModulation.Uint64 = AsmReadMsr64 (MSR_IA32_CLOCK_MODULATION);\r
     return TRUE;\r
   }\r
+\r
   return FALSE;\r
 }\r
 \r
@@ -103,15 +104,15 @@ ClockModulationInitialize (
   IN BOOLEAN                           State\r
   )\r
 {\r
-  CLOCK_MODULATION_CONFIG_DATA         *CmConfigData;\r
-  MSR_IA32_CLOCK_MODULATION_REGISTER   *ClockModulation;\r
+  CLOCK_MODULATION_CONFIG_DATA        *CmConfigData;\r
+  MSR_IA32_CLOCK_MODULATION_REGISTER  *ClockModulation;\r
 \r
-  CmConfigData = (CLOCK_MODULATION_CONFIG_DATA *) ConfigData;\r
+  CmConfigData = (CLOCK_MODULATION_CONFIG_DATA *)ConfigData;\r
   ASSERT (CmConfigData != NULL);\r
   ClockModulation = &CmConfigData[ProcessorNumber].ClockModulation;\r
 \r
   if (State) {\r
-    ClockModulation->Bits.OnDemandClockModulationEnable = 1;\r
+    ClockModulation->Bits.OnDemandClockModulationEnable    = 1;\r
     ClockModulation->Bits.OnDemandClockModulationDutyCycle = PcdGet8 (PcdCpuClockModulationDutyCycle) >> 1;\r
     if (CmConfigData[ProcessorNumber].ThermalPowerManagementEax.Bits.ECMD == 1) {\r
       ClockModulation->Bits.ExtendedOnDemandClockModulationDutyCycle = PcdGet8 (PcdCpuClockModulationDutyCycle) & BIT0;\r

diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeatures.h b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeatures.h
index 74f27dcc445d05353ec056835c4ea8d8de574a8a..5434a45f6a84be6314f88656b21bf0a0c8e48150 100644 (file)
--- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeatures.h
+++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeatures.h
@@ -860,7 +860,7 @@ X2ApicInitialize (
 VOID *\r
 EFIAPI\r
 PpinGetConfigData (\r
-  IN UINTN               NumberOfProcessors\r
+  IN UINTN  NumberOfProcessors\r
   );\r
 \r
 /**\r

diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c
index 725ef7bd438601eab528c0e149338e018431487d..7f0e1004b9e63ecb7380e01450a511b4b8368316 100644 (file)
--- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c
+++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c
@@ -20,7 +20,7 @@ CpuCommonFeaturesLibConstructor (
   VOID\r
   )\r
 {\r
-  RETURN_STATUS         Status;\r
+  RETURN_STATUS  Status;\r
 \r
   if (IsCpuFeatureSupported (CPU_FEATURE_AESNI)) {\r
     Status = RegisterCpuFeature (\r
@@ -33,6 +33,7 @@ CpuCommonFeaturesLibConstructor (
                );\r
     ASSERT_EFI_ERROR (Status);\r
   }\r
+\r
   if (IsCpuFeatureSupported (CPU_FEATURE_MWAIT)) {\r
     Status = RegisterCpuFeature (\r
                "MWAIT",\r
@@ -44,6 +45,7 @@ CpuCommonFeaturesLibConstructor (
                );\r
     ASSERT_EFI_ERROR (Status);\r
   }\r
+\r
   if (IsCpuFeatureSupported (CPU_FEATURE_ACPI)) {\r
     Status = RegisterCpuFeature (\r
                "ACPI",\r
@@ -55,6 +57,7 @@ CpuCommonFeaturesLibConstructor (
                );\r
     ASSERT_EFI_ERROR (Status);\r
   }\r
+\r
   if (IsCpuFeatureSupported (CPU_FEATURE_EIST)) {\r
     Status = RegisterCpuFeature (\r
                "EIST",\r
@@ -66,6 +69,7 @@ CpuCommonFeaturesLibConstructor (
                );\r
     ASSERT_EFI_ERROR (Status);\r
   }\r
+\r
   if (IsCpuFeatureSupported (CPU_FEATURE_FASTSTRINGS)) {\r
     Status = RegisterCpuFeature (\r
                "FastStrings",\r
@@ -77,6 +81,7 @@ CpuCommonFeaturesLibConstructor (
                );\r
     ASSERT_EFI_ERROR (Status);\r
   }\r
+\r
   if (IsCpuFeatureSupported (CPU_FEATURE_LOCK_FEATURE_CONTROL_REGISTER)) {\r
     Status = RegisterCpuFeature (\r
                "Lock Feature Control Register",\r
@@ -88,6 +93,7 @@ CpuCommonFeaturesLibConstructor (
                );\r
     ASSERT_EFI_ERROR (Status);\r
   }\r
+\r
   if (IsCpuFeatureSupported (CPU_FEATURE_SMX)) {\r
     Status = RegisterCpuFeature (\r
                "SMX",\r
@@ -100,6 +106,7 @@ CpuCommonFeaturesLibConstructor (
                );\r
     ASSERT_EFI_ERROR (Status);\r
   }\r
+\r
   if (IsCpuFeatureSupported (CPU_FEATURE_VMX)) {\r
     Status = RegisterCpuFeature (\r
                "VMX",\r
@@ -112,6 +119,7 @@ CpuCommonFeaturesLibConstructor (
                );\r
     ASSERT_EFI_ERROR (Status);\r
   }\r
+\r
   if (IsCpuFeatureSupported (CPU_FEATURE_LIMIT_CPUID_MAX_VAL)) {\r
     Status = RegisterCpuFeature (\r
                "Limit CpuId Maximum Value",\r
@@ -123,6 +131,7 @@ CpuCommonFeaturesLibConstructor (
                );\r
     ASSERT_EFI_ERROR (Status);\r
   }\r
+\r
   if (IsCpuFeatureSupported (CPU_FEATURE_MCE)) {\r
     Status = RegisterCpuFeature (\r
                "Machine Check Enable",\r
@@ -134,6 +143,7 @@ CpuCommonFeaturesLibConstructor (
                );\r
     ASSERT_EFI_ERROR (Status);\r
   }\r
+\r
   if (IsCpuFeatureSupported (CPU_FEATURE_MCA)) {\r
     Status = RegisterCpuFeature (\r
                "Machine Check Architect",\r
@@ -145,6 +155,7 @@ CpuCommonFeaturesLibConstructor (
                );\r
     ASSERT_EFI_ERROR (Status);\r
   }\r
+\r
   if (IsCpuFeatureSupported (CPU_FEATURE_MCG_CTL)) {\r
     Status = RegisterCpuFeature (\r
                "MCG_CTL",\r
@@ -156,6 +167,7 @@ CpuCommonFeaturesLibConstructor (
                );\r
     ASSERT_EFI_ERROR (Status);\r
   }\r
+\r
   if (IsCpuFeatureSupported (CPU_FEATURE_PENDING_BREAK)) {\r
     Status = RegisterCpuFeature (\r
                "Pending Break",\r
@@ -167,6 +179,7 @@ CpuCommonFeaturesLibConstructor (
                );\r
     ASSERT_EFI_ERROR (Status);\r
   }\r
+\r
   if (IsCpuFeatureSupported (CPU_FEATURE_C1E)) {\r
     Status = RegisterCpuFeature (\r
                "C1E",\r
@@ -178,6 +191,7 @@ CpuCommonFeaturesLibConstructor (
                );\r
     ASSERT_EFI_ERROR (Status);\r
   }\r
+\r
   if (IsCpuFeatureSupported (CPU_FEATURE_X2APIC)) {\r
     Status = RegisterCpuFeature (\r
                "X2Apic",\r
@@ -189,6 +203,7 @@ CpuCommonFeaturesLibConstructor (
                );\r
     ASSERT_EFI_ERROR (Status);\r
   }\r
+\r
   if (IsCpuFeatureSupported (CPU_FEATURE_PPIN)) {\r
     Status = RegisterCpuFeature (\r
                "PPIN",\r
@@ -200,6 +215,7 @@ CpuCommonFeaturesLibConstructor (
                );\r
     ASSERT_EFI_ERROR (Status);\r
   }\r
+\r
   if (IsCpuFeatureSupported (CPU_FEATURE_LMCE)) {\r
     Status = RegisterCpuFeature (\r
                "LMCE",\r
@@ -212,6 +228,7 @@ CpuCommonFeaturesLibConstructor (
                );\r
     ASSERT_EFI_ERROR (Status);\r
   }\r
+\r
   if (IsCpuFeatureSupported (CPU_FEATURE_PROC_TRACE)) {\r
     Status = RegisterCpuFeature (\r
                "Proc Trace",\r
@@ -226,6 +243,3 @@ CpuCommonFeaturesLibConstructor (
 \r
   return RETURN_SUCCESS;\r
 }\r
-\r
-\r
-\r

diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/Eist.c b/UefiCpuPkg/Library/CpuCommonFeaturesLib/Eist.c
index ed42afe289c2c09950ee4a7918d7bbb167e463a0..aedf3e6f2c82f9daf0acf5fd4928ac5f31ed5f5d 100644 (file)
--- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/Eist.c
+++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/Eist.c
@@ -69,7 +69,8 @@ EistInitialize (
   //\r
   if (IS_ATOM_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||\r
       IS_CORE_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||\r
-      IS_CORE2_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) {\r
+      IS_CORE2_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel))\r
+  {\r
     if (CpuInfo->ProcessorInfo.Location.Thread != 0) {\r
       return RETURN_SUCCESS;\r
     }\r

diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/FastStrings.c b/UefiCpuPkg/Library/CpuCommonFeaturesLib/FastStrings.c
index 9ae5216555f13def4a098e7a836e9569c00f6fcb..63c3bf9d1077ed847daad71771339c97ae8822d6 100644 (file)
--- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/FastStrings.c
+++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/FastStrings.c
@@ -40,7 +40,8 @@ FastStringsInitialize (
   //\r
   if (IS_SILVERMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||\r
       IS_GOLDMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||\r
-      IS_PENTIUM_4_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) {\r
+      IS_PENTIUM_4_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel))\r
+  {\r
     if (CpuInfo->ProcessorInfo.Location.Thread != 0) {\r
       return RETURN_SUCCESS;\r
     }\r

diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/FeatureControl.c b/UefiCpuPkg/Library/CpuCommonFeaturesLib/FeatureControl.c
index 8ad81a6e8731354bdffe5ea0019e8206dde8e6f7..63ec27a1a6f24639f783940744946c17f3c0853d 100644 (file)
--- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/FeatureControl.c
+++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/FeatureControl.c
@@ -68,7 +68,8 @@ VmxInitialize (
   //\r
   if (IS_SILVERMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||\r
       IS_GOLDMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||\r
-      IS_GOLDMONT_PLUS_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) {\r
+      IS_GOLDMONT_PLUS_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel))\r
+  {\r
     if (CpuInfo->ProcessorInfo.Location.Thread != 0) {\r
       return RETURN_SUCCESS;\r
     }\r
@@ -146,7 +147,8 @@ LockFeatureControlRegisterInitialize (
   //\r
   if (IS_SILVERMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||\r
       IS_GOLDMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||\r
-      IS_GOLDMONT_PLUS_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) {\r
+      IS_GOLDMONT_PLUS_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel))\r
+  {\r
     if (CpuInfo->ProcessorInfo.Location.Thread != 0) {\r
       return RETURN_SUCCESS;\r
     }\r
@@ -218,7 +220,7 @@ SmxInitialize (
   IN BOOLEAN                           State\r
   )\r
 {\r
-  RETURN_STATUS                        Status;\r
+  RETURN_STATUS  Status;\r
 \r
   //\r
   // The scope of Lock bit in the MSR_IA32_FEATURE_CONTROL is core for\r
@@ -226,7 +228,8 @@ SmxInitialize (
   // core.\r
   //\r
   if (IS_GOLDMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||\r
-      IS_GOLDMONT_PLUS_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) {\r
+      IS_GOLDMONT_PLUS_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel))\r
+  {\r
     if (CpuInfo->ProcessorInfo.Location.Thread != 0) {\r
       return RETURN_SUCCESS;\r
     }\r
@@ -236,7 +239,7 @@ SmxInitialize (
 \r
   if (State && (!IsCpuFeatureInSetting (CPU_FEATURE_VMX))) {\r
     DEBUG ((DEBUG_WARN, "Warning :: Can't enable SMX feature when VMX feature not enabled, disable it.\n"));\r
-    State = FALSE;\r
+    State  = FALSE;\r
     Status = RETURN_UNSUPPORTED;\r
   }\r
 \r
@@ -247,7 +250,7 @@ SmxInitialize (
     IA32_CR4,\r
     Bits.SMXE,\r
     (State) ? 1 : 0\r
-  )\r
+    )\r
 \r
   CPU_REGISTER_TABLE_TEST_THEN_WRITE_FIELD (\r
     ProcessorNumber,\r

diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/LimitCpuIdMaxval.c b/UefiCpuPkg/Library/CpuCommonFeaturesLib/LimitCpuIdMaxval.c
index 71d82eab8dcc24526b3eadcc4e1b6fef6c426420..bf495f96bb938841531cd1adc298dedbb352c522 100644 (file)
--- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/LimitCpuIdMaxval.c
+++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/LimitCpuIdMaxval.c
@@ -72,7 +72,8 @@ LimitCpuidMaxvalInitialize (
       IS_SILVERMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||\r
       IS_GOLDMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||\r
       IS_CORE_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||\r
-      IS_CORE2_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) {\r
+      IS_CORE2_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel))\r
+  {\r
     if (CpuInfo->ProcessorInfo.Location.Thread != 0) {\r
       return RETURN_SUCCESS;\r
     }\r

diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c b/UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c
index 0e78a0ce2689802a227a2d2a420b65cf5a454283..d8b070d9f10a0942603a6b415f0a2b091313d329 100644 (file)
--- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c
+++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c
@@ -102,6 +102,7 @@ McaSupport (
   if (!MceSupport (ProcessorNumber, CpuInfo, ConfigData)) {\r
     return FALSE;\r
   }\r
+\r
   return (CpuInfo->CpuIdVersionInfoEdx.Bits.MCA == 1);\r
 }\r
 \r
@@ -144,7 +145,8 @@ McaInitialize (
       IS_SKYLAKE_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||\r
       IS_XEON_PHI_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||\r
       IS_PENTIUM_4_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||\r
-      IS_CORE_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) {\r
+      IS_CORE_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel))\r
+  {\r
     if (CpuInfo->ProcessorInfo.Location.Thread != 0) {\r
       return RETURN_SUCCESS;\r
     }\r
@@ -162,7 +164,7 @@ McaInitialize (
 \r
   if (State) {\r
     McgCap.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_CAP);\r
-    for (BankIndex = 0; BankIndex < (UINT32) McgCap.Bits.Count; BankIndex++) {\r
+    for (BankIndex = 0; BankIndex < (UINT32)McgCap.Bits.Count; BankIndex++) {\r
       CPU_REGISTER_TABLE_WRITE64 (\r
         ProcessorNumber,\r
         Msr,\r
@@ -172,7 +174,7 @@ McaInitialize (
     }\r
 \r
     if (PcdGetBool (PcdIsPowerOnReset)) {\r
-      for (BankIndex = 0; BankIndex < (UINTN) McgCap.Bits.Count; BankIndex++) {\r
+      for (BankIndex = 0; BankIndex < (UINTN)McgCap.Bits.Count; BankIndex++) {\r
         CPU_REGISTER_TABLE_WRITE64 (\r
           ProcessorNumber,\r
           Msr,\r
@@ -215,6 +217,7 @@ McgCtlSupport (
   if (!McaSupport (ProcessorNumber, CpuInfo, ConfigData)) {\r
     return FALSE;\r
   }\r
+\r
   McgCap.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_CAP);\r
   return (McgCap.Bits.MCG_CTL_P == 1);\r
 }\r
@@ -249,7 +252,7 @@ McgCtlInitialize (
     ProcessorNumber,\r
     Msr,\r
     MSR_IA32_MCG_CTL,\r
-    (State)? MAX_UINT64 : 0\r
+    (State) ? MAX_UINT64 : 0\r
     );\r
   return RETURN_SUCCESS;\r
 }\r
@@ -279,7 +282,7 @@ LmceSupport (
   IN VOID                              *ConfigData  OPTIONAL\r
   )\r
 {\r
-  MSR_IA32_MCG_CAP_REGISTER    McgCap;\r
+  MSR_IA32_MCG_CAP_REGISTER  McgCap;\r
 \r
   if (!McaSupport (ProcessorNumber, CpuInfo, ConfigData)) {\r
     return FALSE;\r
@@ -287,9 +290,10 @@ LmceSupport (
 \r
   McgCap.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_CAP);\r
   if (ProcessorNumber == 0) {\r
-    DEBUG ((DEBUG_INFO, "LMCE enable = %x\n", (BOOLEAN) (McgCap.Bits.MCG_LMCE_P != 0)));\r
+    DEBUG ((DEBUG_INFO, "LMCE enable = %x\n", (BOOLEAN)(McgCap.Bits.MCG_LMCE_P != 0)));\r
   }\r
-  return (BOOLEAN) (McgCap.Bits.MCG_LMCE_P != 0);\r
+\r
+  return (BOOLEAN)(McgCap.Bits.MCG_LMCE_P != 0);\r
 }\r
 \r
 /**\r
@@ -325,7 +329,8 @@ LmceInitialize (
   //\r
   if (IS_SILVERMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||\r
       IS_GOLDMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||\r
-      IS_PENTIUM_4_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) {\r
+      IS_PENTIUM_4_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel))\r
+  {\r
     if (CpuInfo->ProcessorInfo.Location.Thread != 0) {\r
       return RETURN_SUCCESS;\r
     }\r

diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/MonitorMwait.c b/UefiCpuPkg/Library/CpuCommonFeaturesLib/MonitorMwait.c
index 9fcbaf8d5d539a293051b59f9f228eee62b6c3d4..d55cf6c6f28d8e5411caece59e768aeec04f563d 100644 (file)
--- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/MonitorMwait.c
+++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/MonitorMwait.c
@@ -70,7 +70,8 @@ MonitorMwaitInitialize (
       IS_GOLDMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||\r
       IS_SILVERMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||\r
       IS_PENTIUM_4_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||\r
-      IS_CORE_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) {\r
+      IS_CORE_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel))\r
+  {\r
     if (CpuInfo->ProcessorInfo.Location.Thread != 0) {\r
       return RETURN_SUCCESS;\r
     }\r

diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/PendingBreak.c b/UefiCpuPkg/Library/CpuCommonFeaturesLib/PendingBreak.c
index 3d7030d6093d8ada784b2a315f82a6ca9d97f1e5..6095dbde05991b5d9dc46ce586c8646a94945b4c 100644 (file)
--- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/PendingBreak.c
+++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/PendingBreak.c
@@ -36,9 +36,11 @@ PendingBreakSupport (
       IS_CORE2_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||\r
       IS_CORE_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||\r
       IS_PENTIUM_4_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||\r
-      IS_PENTIUM_M_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) {\r
+      IS_PENTIUM_M_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel))\r
+  {\r
     return (CpuInfo->CpuIdVersionInfoEdx.Bits.PBE == 1);\r
   }\r
+\r
   return FALSE;\r
 }\r
 \r

diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/Ppin.c b/UefiCpuPkg/Library/CpuCommonFeaturesLib/Ppin.c
index 468e425a0bfeba9fa616ed15af5c01f1101f8390..a7c2c12a51f490caf4ddbed21378c07decd4ad76 100644 (file)
--- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/Ppin.c
+++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/Ppin.c
@@ -20,10 +20,10 @@
 VOID *\r
 EFIAPI\r
 PpinGetConfigData (\r
-  IN UINTN               NumberOfProcessors\r
+  IN UINTN  NumberOfProcessors\r
   )\r
 {\r
-  VOID          *ConfigData;\r
+  VOID  *ConfigData;\r
 \r
   ConfigData = AllocateZeroPool (sizeof (MSR_IVY_BRIDGE_PPIN_CTL_REGISTER) * NumberOfProcessors);\r
   ASSERT (ConfigData != NULL);\r
@@ -55,8 +55,8 @@ PpinSupport (
   IN VOID                              *ConfigData  OPTIONAL\r
   )\r
 {\r
-  MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER    PlatformInfo;\r
-  MSR_IVY_BRIDGE_PPIN_CTL_REGISTER           *MsrPpinCtrl;\r
+  MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER  PlatformInfo;\r
+  MSR_IVY_BRIDGE_PPIN_CTL_REGISTER         *MsrPpinCtrl;\r
 \r
   if ((CpuInfo->DisplayFamily == 0x06) &&\r
       ((CpuInfo->DisplayModel == 0x3E) ||      // Xeon E5 V2\r
@@ -65,13 +65,14 @@ PpinSupport (
        (CpuInfo->DisplayModel == 0x55) ||      // Xeon Processor Scalable\r
        (CpuInfo->DisplayModel == 0x57) ||      // Xeon Phi processor 3200, 5200, 7200 series.\r
        (CpuInfo->DisplayModel == 0x85)         // Future Xeon phi processor\r
-     )) {\r
+      ))\r
+  {\r
     //\r
     // Check whether platform support this feature.\r
     //\r
     PlatformInfo.Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PLATFORM_INFO_1);\r
     if (PlatformInfo.Bits.PPIN_CAP != 0) {\r
-      MsrPpinCtrl = (MSR_IVY_BRIDGE_PPIN_CTL_REGISTER *) ConfigData;\r
+      MsrPpinCtrl = (MSR_IVY_BRIDGE_PPIN_CTL_REGISTER *)ConfigData;\r
       ASSERT (MsrPpinCtrl != NULL);\r
       MsrPpinCtrl[ProcessorNumber].Uint64 = AsmReadMsr64 (MSR_IVY_BRIDGE_PPIN_CTL);\r
       return TRUE;\r
@@ -112,9 +113,9 @@ PpinInitialize (
   IN BOOLEAN                           State\r
   )\r
 {\r
-  MSR_IVY_BRIDGE_PPIN_CTL_REGISTER     *MsrPpinCtrl;\r
+  MSR_IVY_BRIDGE_PPIN_CTL_REGISTER  *MsrPpinCtrl;\r
 \r
-  MsrPpinCtrl = (MSR_IVY_BRIDGE_PPIN_CTL_REGISTER *) ConfigData;\r
+  MsrPpinCtrl = (MSR_IVY_BRIDGE_PPIN_CTL_REGISTER *)ConfigData;\r
   ASSERT (MsrPpinCtrl != NULL);\r
 \r
   //\r
@@ -143,14 +144,14 @@ PpinInitialize (
     // According to SDM, once Enable_PPIN is set, attempt to write 1 to LockOut will cause #GP.\r
     //\r
     MsrPpinCtrl[ProcessorNumber].Bits.Enable_PPIN = 1;\r
-    MsrPpinCtrl[ProcessorNumber].Bits.LockOut = 0;\r
+    MsrPpinCtrl[ProcessorNumber].Bits.LockOut     = 0;\r
   } else {\r
     //\r
     // Disable and Lock.\r
     // According to SDM, writing 1 to LockOut is permitted only if Enable_PPIN is clear.\r
     //\r
     MsrPpinCtrl[ProcessorNumber].Bits.Enable_PPIN = 0;\r
-    MsrPpinCtrl[ProcessorNumber].Bits.LockOut = 1;\r
+    MsrPpinCtrl[ProcessorNumber].Bits.LockOut     = 1;\r
   }\r
 \r
   CPU_REGISTER_TABLE_WRITE64 (\r

diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/ProcTrace.c b/UefiCpuPkg/Library/CpuCommonFeaturesLib/ProcTrace.c
index e567ed54e73042b932ae607845ce4337e493ba94..04e6a607280b28e0ccd7f2e0b6f7f1fe5d101bd1 100644 (file)
--- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/ProcTrace.c
+++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/ProcTrace.c
@@ -17,8 +17,7 @@
 /// be terminated by an entry with the END bit set to 1, so 2\r
 /// entries are required to use a single valid entry.\r
 ///\r
-#define MAX_TOPA_ENTRY_COUNT         2\r
-\r
+#define MAX_TOPA_ENTRY_COUNT  2\r
 \r
 ///\r
 /// Processor trace output scheme selection.\r
@@ -29,25 +28,25 @@ typedef enum {
 } RTIT_OUTPUT_SCHEME;\r
 \r
 typedef struct  {\r
-  BOOLEAN                                   TopaSupported;\r
-  BOOLEAN                                   SingleRangeSupported;\r
-  MSR_IA32_RTIT_CTL_REGISTER                RtitCtrl;\r
-  MSR_IA32_RTIT_OUTPUT_BASE_REGISTER        RtitOutputBase;\r
-  MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER   RtitOutputMaskPtrs;\r
+  BOOLEAN                                    TopaSupported;\r
+  BOOLEAN                                    SingleRangeSupported;\r
+  MSR_IA32_RTIT_CTL_REGISTER                 RtitCtrl;\r
+  MSR_IA32_RTIT_OUTPUT_BASE_REGISTER         RtitOutputBase;\r
+  MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER    RtitOutputMaskPtrs;\r
 } PROC_TRACE_PROCESSOR_DATA;\r
 \r
 typedef struct  {\r
-  UINT32                      NumberOfProcessors;\r
+  UINT32                       NumberOfProcessors;\r
 \r
-  UINT8                       ProcTraceOutputScheme;\r
-  UINT32                      ProcTraceMemSize;\r
+  UINT8                        ProcTraceOutputScheme;\r
+  UINT32                       ProcTraceMemSize;\r
 \r
-  UINTN                       *ThreadMemRegionTable;\r
-  UINTN                       AllocatedThreads;\r
+  UINTN                        *ThreadMemRegionTable;\r
+  UINTN                        AllocatedThreads;\r
 \r
-  UINTN                       *TopaMemArray;\r
+  UINTN                        *TopaMemArray;\r
 \r
-  PROC_TRACE_PROCESSOR_DATA   *ProcessorData;\r
+  PROC_TRACE_PROCESSOR_DATA    *ProcessorData;\r
 } PROC_TRACE_DATA;\r
 \r
 typedef struct {\r
@@ -73,10 +72,10 @@ ProcTraceGetConfigData (
 \r
   ConfigData = AllocateZeroPool (sizeof (PROC_TRACE_DATA) + sizeof (PROC_TRACE_PROCESSOR_DATA) * NumberOfProcessors);\r
   ASSERT (ConfigData != NULL);\r
-  ConfigData->ProcessorData = (PROC_TRACE_PROCESSOR_DATA *) ((UINT8*) ConfigData + sizeof (PROC_TRACE_DATA));\r
+  ConfigData->ProcessorData = (PROC_TRACE_PROCESSOR_DATA *)((UINT8 *)ConfigData + sizeof (PROC_TRACE_DATA));\r
 \r
-  ConfigData->NumberOfProcessors = (UINT32) NumberOfProcessors;\r
-  ConfigData->ProcTraceMemSize = PcdGet32 (PcdCpuProcTraceMemSize);\r
+  ConfigData->NumberOfProcessors    = (UINT32)NumberOfProcessors;\r
+  ConfigData->ProcTraceMemSize      = PcdGet32 (PcdCpuProcTraceMemSize);\r
   ConfigData->ProcTraceOutputScheme = PcdGet8 (PcdCpuProcTraceOutputScheme);\r
 \r
   return ConfigData;\r
@@ -107,17 +106,18 @@ ProcTraceSupport (
   IN VOID                              *ConfigData  OPTIONAL\r
   )\r
 {\r
-  PROC_TRACE_DATA                             *ProcTraceData;\r
-  CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX Ebx;\r
-  CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX   Ecx;\r
+  PROC_TRACE_DATA                              *ProcTraceData;\r
+  CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX  Ebx;\r
+  CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX    Ecx;\r
 \r
   //\r
   // Check if ProcTraceMemorySize option is enabled (0xFF means disable by user)\r
   //\r
-  ProcTraceData = (PROC_TRACE_DATA *) ConfigData;\r
+  ProcTraceData = (PROC_TRACE_DATA *)ConfigData;\r
   ASSERT (ProcTraceData != NULL);\r
   if ((ProcTraceData->ProcTraceMemSize > RtitTopaMemorySize128M) ||\r
-      (ProcTraceData->ProcTraceOutputScheme > RtitOutputSchemeToPA)) {\r
+      (ProcTraceData->ProcTraceOutputScheme > RtitOutputSchemeToPA))\r
+  {\r
     return FALSE;\r
   }\r
 \r
@@ -130,12 +130,13 @@ ProcTraceSupport (
   }\r
 \r
   AsmCpuidEx (CPUID_INTEL_PROCESSOR_TRACE, CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF, NULL, NULL, &Ecx.Uint32, NULL);\r
-  ProcTraceData->ProcessorData[ProcessorNumber].TopaSupported = (BOOLEAN) (Ecx.Bits.RTIT == 1);\r
-  ProcTraceData->ProcessorData[ProcessorNumber].SingleRangeSupported = (BOOLEAN) (Ecx.Bits.SingleRangeOutput == 1);\r
+  ProcTraceData->ProcessorData[ProcessorNumber].TopaSupported        = (BOOLEAN)(Ecx.Bits.RTIT == 1);\r
+  ProcTraceData->ProcessorData[ProcessorNumber].SingleRangeSupported = (BOOLEAN)(Ecx.Bits.SingleRangeOutput == 1);\r
   if ((ProcTraceData->ProcessorData[ProcessorNumber].TopaSupported && (ProcTraceData->ProcTraceOutputScheme == RtitOutputSchemeToPA)) ||\r
-      (ProcTraceData->ProcessorData[ProcessorNumber].SingleRangeSupported && (ProcTraceData->ProcTraceOutputScheme == RtitOutputSchemeSingleRange))) {\r
-    ProcTraceData->ProcessorData[ProcessorNumber].RtitCtrl.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_CTL);\r
-    ProcTraceData->ProcessorData[ProcessorNumber].RtitOutputBase.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_OUTPUT_BASE);\r
+      (ProcTraceData->ProcessorData[ProcessorNumber].SingleRangeSupported && (ProcTraceData->ProcTraceOutputScheme == RtitOutputSchemeSingleRange)))\r
+  {\r
+    ProcTraceData->ProcessorData[ProcessorNumber].RtitCtrl.Uint64           = AsmReadMsr64 (MSR_IA32_RTIT_CTL);\r
+    ProcTraceData->ProcessorData[ProcessorNumber].RtitOutputBase.Uint64     = AsmReadMsr64 (MSR_IA32_RTIT_OUTPUT_BASE);\r
     ProcTraceData->ProcessorData[ProcessorNumber].RtitOutputMaskPtrs.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_OUTPUT_MASK_PTRS);\r
     return TRUE;\r
   }\r
@@ -170,36 +171,37 @@ ProcTraceInitialize (
   IN BOOLEAN                           State\r
   )\r
 {\r
-  UINT32                               MemRegionSize;\r
-  UINTN                                Pages;\r
-  UINTN                                Alignment;\r
-  UINTN                                MemRegionBaseAddr;\r
-  UINTN                                *ThreadMemRegionTable;\r
-  UINTN                                Index;\r
-  UINTN                                TopaTableBaseAddr;\r
-  UINTN                                AlignedAddress;\r
-  UINTN                                *TopaMemArray;\r
-  PROC_TRACE_TOPA_TABLE                *TopaTable;\r
-  PROC_TRACE_DATA                      *ProcTraceData;\r
-  BOOLEAN                              FirstIn;\r
-  MSR_IA32_RTIT_CTL_REGISTER           CtrlReg;\r
-  MSR_IA32_RTIT_STATUS_REGISTER        StatusReg;\r
-  MSR_IA32_RTIT_OUTPUT_BASE_REGISTER   OutputBaseReg;\r
+  UINT32                                   MemRegionSize;\r
+  UINTN                                    Pages;\r
+  UINTN                                    Alignment;\r
+  UINTN                                    MemRegionBaseAddr;\r
+  UINTN                                    *ThreadMemRegionTable;\r
+  UINTN                                    Index;\r
+  UINTN                                    TopaTableBaseAddr;\r
+  UINTN                                    AlignedAddress;\r
+  UINTN                                    *TopaMemArray;\r
+  PROC_TRACE_TOPA_TABLE                    *TopaTable;\r
+  PROC_TRACE_DATA                          *ProcTraceData;\r
+  BOOLEAN                                  FirstIn;\r
+  MSR_IA32_RTIT_CTL_REGISTER               CtrlReg;\r
+  MSR_IA32_RTIT_STATUS_REGISTER            StatusReg;\r
+  MSR_IA32_RTIT_OUTPUT_BASE_REGISTER       OutputBaseReg;\r
   MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER  OutputMaskPtrsReg;\r
-  RTIT_TOPA_TABLE_ENTRY                *TopaEntryPtr;\r
+  RTIT_TOPA_TABLE_ENTRY                    *TopaEntryPtr;\r
 \r
   //\r
   // The scope of the MSR_IA32_RTIT_* is core for below processor type, only program\r
   // MSR_IA32_RTIT_* for thread 0 in each core.\r
   //\r
   if (IS_GOLDMONT_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel) ||\r
-      IS_GOLDMONT_PLUS_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) {\r
+      IS_GOLDMONT_PLUS_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel))\r
+  {\r
     if (CpuInfo->ProcessorInfo.Location.Thread != 0) {\r
       return RETURN_SUCCESS;\r
     }\r
   }\r
 \r
-  ProcTraceData = (PROC_TRACE_DATA *) ConfigData;\r
+  ProcTraceData = (PROC_TRACE_DATA *)ConfigData;\r
   ASSERT (ProcTraceData != NULL);\r
 \r
   //\r
@@ -235,7 +237,7 @@ ProcTraceInitialize (
   }\r
 \r
   MemRegionBaseAddr = 0;\r
-  FirstIn = FALSE;\r
+  FirstIn           = FALSE;\r
 \r
   if (ProcTraceData->ThreadMemRegionTable == NULL) {\r
     FirstIn = TRUE;\r
@@ -245,7 +247,7 @@ ProcTraceInitialize (
   ///\r
   /// Refer to PROC_TRACE_MEM_SIZE Table for Size Encoding\r
   ///\r
-  MemRegionSize = (UINT32) (1 << (ProcTraceData->ProcTraceMemSize + 12));\r
+  MemRegionSize = (UINT32)(1 << (ProcTraceData->ProcTraceMemSize + 12));\r
   if (FirstIn) {\r
     DEBUG ((DEBUG_INFO, "ProcTrace: MemSize requested: 0x%X \n", MemRegionSize));\r
   }\r
@@ -258,32 +260,34 @@ ProcTraceInitialize (
     //   address base in MSR, IA32_RTIT_OUTPUT_BASE (560h) bits 47:12. Note that all regions must be\r
     //   aligned based on their size, not just 4K. Thus a 2M region must have bits 20:12 cleared.\r
     //\r
-    ThreadMemRegionTable = (UINTN *) AllocatePool (ProcTraceData->NumberOfProcessors * sizeof (UINTN *));\r
+    ThreadMemRegionTable = (UINTN *)AllocatePool (ProcTraceData->NumberOfProcessors * sizeof (UINTN *));\r
     if (ThreadMemRegionTable == NULL) {\r
       DEBUG ((DEBUG_ERROR, "Allocate ProcTrace ThreadMemRegionTable Failed\n"));\r
       return RETURN_OUT_OF_RESOURCES;\r
     }\r
+\r
     ProcTraceData->ThreadMemRegionTable = ThreadMemRegionTable;\r
 \r
     for (Index = 0; Index < ProcTraceData->NumberOfProcessors; Index++, ProcTraceData->AllocatedThreads++) {\r
-      Pages = EFI_SIZE_TO_PAGES (MemRegionSize);\r
-      Alignment = MemRegionSize;\r
-      AlignedAddress = (UINTN) AllocateAlignedReservedPages (Pages, Alignment);\r
+      Pages          = EFI_SIZE_TO_PAGES (MemRegionSize);\r
+      Alignment      = MemRegionSize;\r
+      AlignedAddress = (UINTN)AllocateAlignedReservedPages (Pages, Alignment);\r
       if (AlignedAddress == 0) {\r
         DEBUG ((DEBUG_ERROR, "ProcTrace: Out of mem, allocated only for %d threads\n", ProcTraceData->AllocatedThreads));\r
         if (Index == 0) {\r
           //\r
           // Could not allocate for BSP even\r
           //\r
-          FreePool ((VOID *) ThreadMemRegionTable);\r
+          FreePool ((VOID *)ThreadMemRegionTable);\r
           ThreadMemRegionTable = NULL;\r
           return RETURN_OUT_OF_RESOURCES;\r
         }\r
+\r
         break;\r
       }\r
 \r
       ThreadMemRegionTable[Index] = AlignedAddress;\r
-      DEBUG ((DEBUG_INFO, "ProcTrace: PT MemRegionBaseAddr(aligned) for thread %d: 0x%llX \n", Index, (UINT64) ThreadMemRegionTable[Index]));\r
+      DEBUG ((DEBUG_INFO, "ProcTrace: PT MemRegionBaseAddr(aligned) for thread %d: 0x%llX \n", Index, (UINT64)ThreadMemRegionTable[Index]));\r
     }\r
 \r
     DEBUG ((DEBUG_INFO, "ProcTrace: Allocated PT mem for %d thread \n", ProcTraceData->AllocatedThreads));\r
@@ -303,7 +307,8 @@ ProcTraceInitialize (
   //  Single Range output scheme\r
   //\r
   if (ProcTraceData->ProcessorData[ProcessorNumber].SingleRangeSupported &&\r
-      (ProcTraceData->ProcTraceOutputScheme == RtitOutputSchemeSingleRange)) {\r
+      (ProcTraceData->ProcTraceOutputScheme == RtitOutputSchemeSingleRange))\r
+  {\r
     if (FirstIn) {\r
       DEBUG ((DEBUG_INFO, "ProcTrace: Enabling Single Range Output scheme \n"));\r
     }\r
@@ -322,9 +327,9 @@ ProcTraceInitialize (
     //\r
     // Program MSR IA32_RTIT_OUTPUT_BASE (0x560) bits[63:7] with the allocated Memory Region\r
     //\r
-    OutputBaseReg.Uint64 = ProcTraceData->ProcessorData[ProcessorNumber].RtitOutputBase.Uint64;\r
-    OutputBaseReg.Bits.Base = (MemRegionBaseAddr >> 7) & 0x01FFFFFF;\r
-    OutputBaseReg.Bits.BaseHi = RShiftU64 ((UINT64) MemRegionBaseAddr, 32) & 0xFFFFFFFF;\r
+    OutputBaseReg.Uint64      = ProcTraceData->ProcessorData[ProcessorNumber].RtitOutputBase.Uint64;\r
+    OutputBaseReg.Bits.Base   = (MemRegionBaseAddr >> 7) & 0x01FFFFFF;\r
+    OutputBaseReg.Bits.BaseHi = RShiftU64 ((UINT64)MemRegionBaseAddr, 32) & 0xFFFFFFFF;\r
     CPU_REGISTER_TABLE_WRITE64 (\r
       ProcessorNumber,\r
       Msr,\r
@@ -335,9 +340,9 @@ ProcTraceInitialize (
     //\r
     // Program the Mask bits for the Memory Region to MSR IA32_RTIT_OUTPUT_MASK_PTRS (561h)\r
     //\r
-    OutputMaskPtrsReg.Uint64 = ProcTraceData->ProcessorData[ProcessorNumber].RtitOutputMaskPtrs.Uint64;\r
+    OutputMaskPtrsReg.Uint64                 = ProcTraceData->ProcessorData[ProcessorNumber].RtitOutputMaskPtrs.Uint64;\r
     OutputMaskPtrsReg.Bits.MaskOrTableOffset = ((MemRegionSize - 1) >> 7) & 0x01FFFFFF;\r
-    OutputMaskPtrsReg.Bits.OutputOffset = RShiftU64 (MemRegionSize - 1, 32) & 0xFFFFFFFF;\r
+    OutputMaskPtrsReg.Bits.OutputOffset      = RShiftU64 (MemRegionSize - 1, 32) & 0xFFFFFFFF;\r
     CPU_REGISTER_TABLE_WRITE64 (\r
       ProcessorNumber,\r
       Msr,\r
@@ -350,7 +355,8 @@ ProcTraceInitialize (
   //  ToPA(Table of physical address) scheme\r
   //\r
   if (ProcTraceData->ProcessorData[ProcessorNumber].TopaSupported &&\r
-      (ProcTraceData->ProcTraceOutputScheme == RtitOutputSchemeToPA)) {\r
+      (ProcTraceData->ProcTraceOutputScheme == RtitOutputSchemeToPA))\r
+  {\r
     //\r
     //  Create ToPA structure aligned at 4KB for each logical thread\r
     //  with at least 2 entries by 8 bytes size each. The first entry\r
@@ -364,35 +370,38 @@ ProcTraceInitialize (
       //\r
       // Let BSP allocate ToPA table mem for all threads\r
       //\r
-      TopaMemArray = (UINTN *) AllocatePool (ProcTraceData->AllocatedThreads * sizeof (UINTN *));\r
+      TopaMemArray = (UINTN *)AllocatePool (ProcTraceData->AllocatedThreads * sizeof (UINTN *));\r
       if (TopaMemArray == NULL) {\r
         DEBUG ((DEBUG_ERROR, "ProcTrace: Allocate mem for ToPA Failed\n"));\r
         return RETURN_OUT_OF_RESOURCES;\r
       }\r
+\r
       ProcTraceData->TopaMemArray = TopaMemArray;\r
 \r
       for (Index = 0; Index < ProcTraceData->AllocatedThreads; Index++) {\r
-        Pages = EFI_SIZE_TO_PAGES (sizeof (PROC_TRACE_TOPA_TABLE));\r
-        Alignment = 0x1000;\r
-        AlignedAddress = (UINTN) AllocateAlignedReservedPages (Pages, Alignment);\r
+        Pages          = EFI_SIZE_TO_PAGES (sizeof (PROC_TRACE_TOPA_TABLE));\r
+        Alignment      = 0x1000;\r
+        AlignedAddress = (UINTN)AllocateAlignedReservedPages (Pages, Alignment);\r
         if (AlignedAddress == 0) {\r
           if (Index < ProcTraceData->AllocatedThreads) {\r
             ProcTraceData->AllocatedThreads = Index;\r
           }\r
+\r
           DEBUG ((DEBUG_ERROR, "ProcTrace:  Out of mem, allocated ToPA mem only for %d threads\n", ProcTraceData->AllocatedThreads));\r
           if (Index == 0) {\r
             //\r
             // Could not allocate for BSP even\r
             //\r
-            FreePool ((VOID *) TopaMemArray);\r
+            FreePool ((VOID *)TopaMemArray);\r
             TopaMemArray = NULL;\r
             return RETURN_OUT_OF_RESOURCES;\r
           }\r
+\r
           break;\r
         }\r
 \r
         TopaMemArray[Index] = AlignedAddress;\r
-        DEBUG ((DEBUG_INFO, "ProcTrace: Topa table address(aligned) for thread %d is 0x%llX \n", Index,  (UINT64) TopaMemArray[Index]));\r
+        DEBUG ((DEBUG_INFO, "ProcTrace: Topa table address(aligned) for thread %d is 0x%llX \n", Index, (UINT64)TopaMemArray[Index]));\r
       }\r
 \r
       DEBUG ((DEBUG_INFO, "ProcTrace: Allocated ToPA mem for %d thread \n", ProcTraceData->AllocatedThreads));\r
@@ -404,26 +413,26 @@ ProcTraceInitialize (
       return RETURN_SUCCESS;\r
     }\r
 \r
-    TopaTable = (PROC_TRACE_TOPA_TABLE *) TopaTableBaseAddr;\r
-    TopaEntryPtr = &TopaTable->TopaEntry[0];\r
-    TopaEntryPtr->Uint64 = 0;\r
-    TopaEntryPtr->Bits.Base = (MemRegionBaseAddr >> 12) & 0x000FFFFF;\r
-    TopaEntryPtr->Bits.BaseHi = RShiftU64 ((UINT64) MemRegionBaseAddr, 32) & 0xFFFFFFFF;\r
-    TopaEntryPtr->Bits.Size = ProcTraceData->ProcTraceMemSize;\r
-    TopaEntryPtr->Bits.END = 0;\r
+    TopaTable                 = (PROC_TRACE_TOPA_TABLE *)TopaTableBaseAddr;\r
+    TopaEntryPtr              = &TopaTable->TopaEntry[0];\r
+    TopaEntryPtr->Uint64      = 0;\r
+    TopaEntryPtr->Bits.Base   = (MemRegionBaseAddr >> 12) & 0x000FFFFF;\r
+    TopaEntryPtr->Bits.BaseHi = RShiftU64 ((UINT64)MemRegionBaseAddr, 32) & 0xFFFFFFFF;\r
+    TopaEntryPtr->Bits.Size   = ProcTraceData->ProcTraceMemSize;\r
+    TopaEntryPtr->Bits.END    = 0;\r
 \r
-    TopaEntryPtr = &TopaTable->TopaEntry[1];\r
-    TopaEntryPtr->Uint64 = 0;\r
-    TopaEntryPtr->Bits.Base = (TopaTableBaseAddr >> 12) & 0x000FFFFF;\r
-    TopaEntryPtr->Bits.BaseHi = RShiftU64 ((UINT64) TopaTableBaseAddr, 32) & 0xFFFFFFFF;\r
-    TopaEntryPtr->Bits.END = 1;\r
+    TopaEntryPtr              = &TopaTable->TopaEntry[1];\r
+    TopaEntryPtr->Uint64      = 0;\r
+    TopaEntryPtr->Bits.Base   = (TopaTableBaseAddr >> 12) & 0x000FFFFF;\r
+    TopaEntryPtr->Bits.BaseHi = RShiftU64 ((UINT64)TopaTableBaseAddr, 32) & 0xFFFFFFFF;\r
+    TopaEntryPtr->Bits.END    = 1;\r
 \r
     //\r
     // Program the MSR IA32_RTIT_OUTPUT_BASE (0x560) bits[63:7] with ToPA base\r
     //\r
-    OutputBaseReg.Uint64 = ProcTraceData->ProcessorData[ProcessorNumber].RtitOutputBase.Uint64;\r
-    OutputBaseReg.Bits.Base = (TopaTableBaseAddr >> 7) & 0x01FFFFFF;\r
-    OutputBaseReg.Bits.BaseHi = RShiftU64 ((UINT64) TopaTableBaseAddr, 32) & 0xFFFFFFFF;\r
+    OutputBaseReg.Uint64      = ProcTraceData->ProcessorData[ProcessorNumber].RtitOutputBase.Uint64;\r
+    OutputBaseReg.Bits.Base   = (TopaTableBaseAddr >> 7) & 0x01FFFFFF;\r
+    OutputBaseReg.Bits.BaseHi = RShiftU64 ((UINT64)TopaTableBaseAddr, 32) & 0xFFFFFFFF;\r
     CPU_REGISTER_TABLE_WRITE64 (\r
       ProcessorNumber,\r
       Msr,\r
@@ -434,9 +443,9 @@ ProcTraceInitialize (
     //\r
     // Set the MSR IA32_RTIT_OUTPUT_MASK (0x561) bits[63:7] to 0\r
     //\r
-    OutputMaskPtrsReg.Uint64 = ProcTraceData->ProcessorData[ProcessorNumber].RtitOutputMaskPtrs.Uint64;\r
+    OutputMaskPtrsReg.Uint64                 = ProcTraceData->ProcessorData[ProcessorNumber].RtitOutputMaskPtrs.Uint64;\r
     OutputMaskPtrsReg.Bits.MaskOrTableOffset = 0;\r
-    OutputMaskPtrsReg.Bits.OutputOffset = 0;\r
+    OutputMaskPtrsReg.Bits.OutputOffset      = 0;\r
     CPU_REGISTER_TABLE_WRITE64 (\r
       ProcessorNumber,\r
       Msr,\r
@@ -458,10 +467,10 @@ ProcTraceInitialize (
   ///\r
   /// Enable the Processor Trace feature from MSR IA32_RTIT_CTL (570h)\r
   ///\r
-  CtrlReg.Bits.OS = 1;\r
-  CtrlReg.Bits.User = 1;\r
+  CtrlReg.Bits.OS       = 1;\r
+  CtrlReg.Bits.User     = 1;\r
   CtrlReg.Bits.BranchEn = 1;\r
-  CtrlReg.Bits.TraceEn = 1;\r
+  CtrlReg.Bits.TraceEn  = 1;\r
   CPU_REGISTER_TABLE_WRITE64 (\r
     ProcessorNumber,\r
     Msr,\r

diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/X2Apic.c b/UefiCpuPkg/Library/CpuCommonFeaturesLib/X2Apic.c
index 181dcae21cab22ddd493ba1c35b4d0c6106d79c6..220f307e5a6df01bf072e742febdd2c6f5178cc7 100644 (file)
--- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/X2Apic.c
+++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/X2Apic.c
@@ -23,7 +23,7 @@ X2ApicGetConfigData (
   IN UINTN  NumberOfProcessors\r
   )\r
 {\r
-  BOOLEAN                            *ConfigData;\r
+  BOOLEAN  *ConfigData;\r
 \r
   ConfigData = AllocateZeroPool (sizeof (BOOLEAN) * NumberOfProcessors);\r
   ASSERT (ConfigData != NULL);\r
@@ -56,10 +56,10 @@ X2ApicSupport (
   IN VOID                              *ConfigData  OPTIONAL\r
   )\r
 {\r
-  BOOLEAN                            *X2ApicEnabled;\r
+  BOOLEAN  *X2ApicEnabled;\r
 \r
   ASSERT (ConfigData != NULL);\r
-  X2ApicEnabled = (BOOLEAN *) ConfigData;\r
+  X2ApicEnabled = (BOOLEAN *)ConfigData;\r
   //\r
   // *ConfigData indicates if X2APIC enabled on current processor\r
   //\r
@@ -94,7 +94,7 @@ X2ApicInitialize (
   IN BOOLEAN                           State\r
   )\r
 {\r
-  BOOLEAN                            *X2ApicEnabled;\r
+  BOOLEAN  *X2ApicEnabled;\r
 \r
   //\r
   // The scope of the MSR_IA32_APIC_BASE is core for below processor type, only program\r
@@ -107,7 +107,7 @@ X2ApicInitialize (
   }\r
 \r
   ASSERT (ConfigData != NULL);\r
-  X2ApicEnabled = (BOOLEAN *) ConfigData;\r
+  X2ApicEnabled = (BOOLEAN *)ConfigData;\r
   if (X2ApicEnabled[ProcessorNumber]) {\r
     PRE_SMM_CPU_REGISTER_TABLE_WRITE_FIELD (\r
       ProcessorNumber,\r
@@ -133,5 +133,6 @@ X2ApicInitialize (
         );\r
     }\r
   }\r
+\r
   return RETURN_SUCCESS;\r
 }\r

diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.c
index 49d0041e2ff3230f238b26dff4d7f658563ba6a5..903fac927e3e8a99f9bce9772c6abf30c93dc4f9 100644 (file)
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.c
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.c
@@ -14,15 +14,15 @@
 //\r
 // 1 means an error code will be pushed, otherwise 0\r
 //\r
-CONST UINT32 mErrorCodeFlag = 0x20227d00;\r
+CONST UINT32  mErrorCodeFlag = 0x20227d00;\r
 \r
 //\r
 // Define the maximum message length\r
 //\r
 #define MAX_DEBUG_MESSAGE_LENGTH  0x100\r
 \r
-CONST CHAR8 mExceptionReservedStr[] = "Reserved";\r
-CONST CHAR8 *mExceptionNameStr[] = {\r
+CONST CHAR8  mExceptionReservedStr[] = "Reserved";\r
+CONST CHAR8  *mExceptionNameStr[]    = {\r
   "#DE - Divide Error",\r
   "#DB - Debug",\r
   "NMI Interrupt",\r
@@ -66,10 +66,10 @@ CONST CHAR8 *mExceptionNameStr[] = {
 **/\r
 CONST CHAR8 *\r
 GetExceptionNameStr (\r
-  IN EFI_EXCEPTION_TYPE          ExceptionType\r
+  IN EFI_EXCEPTION_TYPE  ExceptionType\r
   )\r
 {\r
-  if ((UINTN) ExceptionType < EXCEPTION_KNOWN_NAME_NUM) {\r
+  if ((UINTN)ExceptionType < EXCEPTION_KNOWN_NAME_NUM) {\r
     return mExceptionNameStr[ExceptionType];\r
   } else {\r
     return mExceptionReservedStr;\r
@@ -115,13 +115,13 @@ InternalPrintMessage (
 **/\r
 VOID\r
 DumpModuleImageInfo (\r
-  IN  UINTN              CurrentEip\r
+  IN  UINTN  CurrentEip\r
   )\r
 {\r
-  EFI_STATUS                           Status;\r
-  UINTN                                Pe32Data;\r
-  VOID                                 *PdbPointer;\r
-  VOID                                 *EntryPoint;\r
+  EFI_STATUS  Status;\r
+  UINTN       Pe32Data;\r
+  VOID        *PdbPointer;\r
+  VOID        *EntryPoint;\r
 \r
   Pe32Data = PeCoffSearchImageBase (CurrentEip);\r
   if (Pe32Data == 0) {\r
@@ -130,20 +130,22 @@ DumpModuleImageInfo (
     //\r
     // Find Image Base entry point\r
     //\r
-    Status = PeCoffLoaderGetEntryPoint ((VOID *) Pe32Data, &EntryPoint);\r
+    Status = PeCoffLoaderGetEntryPoint ((VOID *)Pe32Data, &EntryPoint);\r
     if (EFI_ERROR (Status)) {\r
       EntryPoint = NULL;\r
     }\r
+\r
     InternalPrintMessage ("!!!! Find image based on IP(0x%x) ", CurrentEip);\r
-    PdbPointer = PeCoffLoaderGetPdbPointer ((VOID *) Pe32Data);\r
+    PdbPointer = PeCoffLoaderGetPdbPointer ((VOID *)Pe32Data);\r
     if (PdbPointer != NULL) {\r
       InternalPrintMessage ("%a", PdbPointer);\r
     } else {\r
-      InternalPrintMessage ("(No PDB) " );\r
+      InternalPrintMessage ("(No PDB) ");\r
     }\r
+\r
     InternalPrintMessage (\r
       " (ImageBase=%016lp, EntryPoint=%016p) !!!!\n",\r
-      (VOID *) Pe32Data,\r
+      (VOID *)Pe32Data,\r
       EntryPoint\r
       );\r
   }\r
@@ -162,9 +164,9 @@ DumpModuleImageInfo (
 **/\r
 EFI_STATUS\r
 ReadAndVerifyVectorInfo (\r
-  IN  EFI_VECTOR_HANDOFF_INFO       *VectorInfo,\r
-  OUT RESERVED_VECTORS_DATA         *ReservedVector,\r
-  IN  UINTN                         VectorCount\r
+  IN  EFI_VECTOR_HANDOFF_INFO  *VectorInfo,\r
+  OUT RESERVED_VECTORS_DATA    *ReservedVector,\r
+  IN  UINTN                    VectorCount\r
   )\r
 {\r
   while (VectorInfo->Attribute != EFI_VECTOR_HANDOFF_LAST_ENTRY) {\r
@@ -174,10 +176,13 @@ ReadAndVerifyVectorInfo (
       //\r
       return EFI_INVALID_PARAMETER;\r
     }\r
+\r
     if (VectorInfo->VectorNumber < VectorCount) {\r
       ReservedVector[VectorInfo->VectorNumber].Attribute = VectorInfo->Attribute;\r
     }\r
-    VectorInfo ++;\r
+\r
+    VectorInfo++;\r
   }\r
+\r
   return EFI_SUCCESS;\r
 }\r

diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
index 0544d6dba631784453b771b4f3ccde6daf7735f1..0f012bccde2b02c85b971ab6b76bd0dbaf98058d 100644 (file)
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
@@ -20,21 +20,21 @@
 #include <Library/SynchronizationLib.h>\r
 #include <Library/CpuExceptionHandlerLib.h>\r
 \r
-#define  CPU_EXCEPTION_NUM          32\r
-#define  CPU_INTERRUPT_NUM         256\r
-#define  HOOKAFTER_STUB_SIZE        16\r
+#define  CPU_EXCEPTION_NUM    32\r
+#define  CPU_INTERRUPT_NUM    256\r
+#define  HOOKAFTER_STUB_SIZE  16\r
 \r
 //\r
 // Exception Error Code of Page-Fault Exception\r
 //\r
-#define IA32_PF_EC_P                BIT0\r
-#define IA32_PF_EC_WR               BIT1\r
-#define IA32_PF_EC_US               BIT2\r
-#define IA32_PF_EC_RSVD             BIT3\r
-#define IA32_PF_EC_ID               BIT4\r
-#define IA32_PF_EC_PK               BIT5\r
-#define IA32_PF_EC_SS               BIT6\r
-#define IA32_PF_EC_SGX              BIT15\r
+#define IA32_PF_EC_P     BIT0\r
+#define IA32_PF_EC_WR    BIT1\r
+#define IA32_PF_EC_US    BIT2\r
+#define IA32_PF_EC_RSVD  BIT3\r
+#define IA32_PF_EC_ID    BIT4\r
+#define IA32_PF_EC_PK    BIT5\r
+#define IA32_PF_EC_SS    BIT6\r
+#define IA32_PF_EC_SGX   BIT15\r
 \r
 #include "ArchInterruptDefs.h"\r
 \r
@@ -47,26 +47,26 @@
 #define CPU_KNOWN_GOOD_STACK_SIZE \\r
   FixedPcdGet32 (PcdCpuKnownGoodStackSize)\r
 \r
-#define CPU_TSS_GDT_SIZE (SIZE_2KB + CPU_TSS_DESC_SIZE + CPU_TSS_SIZE)\r
+#define CPU_TSS_GDT_SIZE  (SIZE_2KB + CPU_TSS_DESC_SIZE + CPU_TSS_SIZE)\r
 \r
 //\r
 // Record exception handler information\r
 //\r
 typedef struct {\r
-  UINTN ExceptionStart;\r
-  UINTN ExceptionStubHeaderSize;\r
-  UINTN HookAfterStubHeaderStart;\r
+  UINTN    ExceptionStart;\r
+  UINTN    ExceptionStubHeaderSize;\r
+  UINTN    HookAfterStubHeaderStart;\r
 } EXCEPTION_HANDLER_TEMPLATE_MAP;\r
 \r
 typedef struct {\r
-  UINTN                       IdtEntryCount;\r
-  SPIN_LOCK                   DisplayMessageSpinLock;\r
-  RESERVED_VECTORS_DATA       *ReservedVectors;\r
-  EFI_CPU_INTERRUPT_HANDLER   *ExternalInterruptHandler;\r
+  UINTN                        IdtEntryCount;\r
+  SPIN_LOCK                    DisplayMessageSpinLock;\r
+  RESERVED_VECTORS_DATA        *ReservedVectors;\r
+  EFI_CPU_INTERRUPT_HANDLER    *ExternalInterruptHandler;\r
 } EXCEPTION_HANDLER_DATA;\r
 \r
-extern CONST UINT32                mErrorCodeFlag;\r
-extern CONST UINTN                 mDoFarReturnFlag;\r
+extern CONST UINT32  mErrorCodeFlag;\r
+extern CONST UINTN   mDoFarReturnFlag;\r
 \r
 /**\r
   Return address map of exception handler template so that C code can generate\r
@@ -77,7 +77,7 @@ extern CONST UINTN                 mDoFarReturnFlag;
 VOID\r
 EFIAPI\r
 AsmGetTemplateAddressMap (\r
-  OUT EXCEPTION_HANDLER_TEMPLATE_MAP *AddressMap\r
+  OUT EXCEPTION_HANDLER_TEMPLATE_MAP  *AddressMap\r
   );\r
 \r
 /**\r
@@ -90,8 +90,8 @@ AsmGetTemplateAddressMap (
 **/\r
 VOID\r
 ArchUpdateIdtEntry (\r
-  OUT IA32_IDT_GATE_DESCRIPTOR       *IdtEntry,\r
-  IN  UINTN                          InterruptHandler\r
+  OUT IA32_IDT_GATE_DESCRIPTOR  *IdtEntry,\r
+  IN  UINTN                     InterruptHandler\r
   );\r
 \r
 /**\r
@@ -102,7 +102,7 @@ ArchUpdateIdtEntry (
 **/\r
 UINTN\r
 ArchGetIdtHandler (\r
-  IN IA32_IDT_GATE_DESCRIPTOR        *IdtEntry\r
+  IN IA32_IDT_GATE_DESCRIPTOR  *IdtEntry\r
   );\r
 \r
 /**\r
@@ -128,7 +128,7 @@ InternalPrintMessage (
 **/\r
 VOID\r
 DumpModuleImageInfo (\r
-  IN  UINTN              CurrentEip\r
+  IN  UINTN  CurrentEip\r
   );\r
 \r
 /**\r
@@ -139,8 +139,8 @@ DumpModuleImageInfo (
 **/\r
 VOID\r
 DumpImageAndCpuContent (\r
-  IN EFI_EXCEPTION_TYPE   ExceptionType,\r
-  IN EFI_SYSTEM_CONTEXT   SystemContext\r
+  IN EFI_EXCEPTION_TYPE  ExceptionType,\r
+  IN EFI_SYSTEM_CONTEXT  SystemContext\r
   );\r
 \r
 /**\r
@@ -157,8 +157,8 @@ DumpImageAndCpuContent (
 **/\r
 EFI_STATUS\r
 InitializeCpuExceptionHandlersWorker (\r
-  IN EFI_VECTOR_HANDOFF_INFO       *VectorInfo OPTIONAL,\r
-  IN OUT EXCEPTION_HANDLER_DATA    *ExceptionHandlerData\r
+  IN EFI_VECTOR_HANDOFF_INFO     *VectorInfo OPTIONAL,\r
+  IN OUT EXCEPTION_HANDLER_DATA  *ExceptionHandlerData\r
   );\r
 \r
 /**\r
@@ -180,9 +180,9 @@ InitializeCpuExceptionHandlersWorker (
 **/\r
 EFI_STATUS\r
 RegisterCpuInterruptHandlerWorker (\r
-  IN EFI_EXCEPTION_TYPE            InterruptType,\r
-  IN EFI_CPU_INTERRUPT_HANDLER     InterruptHandler,\r
-  IN EXCEPTION_HANDLER_DATA        *ExceptionHandlerData\r
+  IN EFI_EXCEPTION_TYPE         InterruptType,\r
+  IN EFI_CPU_INTERRUPT_HANDLER  InterruptHandler,\r
+  IN EXCEPTION_HANDLER_DATA     *ExceptionHandlerData\r
   );\r
 \r
 /**\r
@@ -210,9 +210,9 @@ UpdateIdtTable (
 **/\r
 VOID\r
 ArchSaveExceptionContext (\r
-  IN UINTN                        ExceptionType,\r
-  IN EFI_SYSTEM_CONTEXT           SystemContext,\r
-  IN EXCEPTION_HANDLER_DATA       *ExceptionHandlerData\r
+  IN UINTN                   ExceptionType,\r
+  IN EFI_SYSTEM_CONTEXT      SystemContext,\r
+  IN EXCEPTION_HANDLER_DATA  *ExceptionHandlerData\r
   );\r
 \r
 /**\r
@@ -224,9 +224,9 @@ ArchSaveExceptionContext (
 **/\r
 VOID\r
 ArchRestoreExceptionContext (\r
-  IN UINTN                        ExceptionType,\r
-  IN EFI_SYSTEM_CONTEXT           SystemContext,\r
-  IN EXCEPTION_HANDLER_DATA       *ExceptionHandlerData\r
+  IN UINTN                   ExceptionType,\r
+  IN EFI_SYSTEM_CONTEXT      SystemContext,\r
+  IN EXCEPTION_HANDLER_DATA  *ExceptionHandlerData\r
   );\r
 \r
 /**\r
@@ -240,9 +240,9 @@ ArchRestoreExceptionContext (
 VOID\r
 EFIAPI\r
 AsmVectorNumFixup (\r
-  IN VOID    *NewVectorAddr,\r
-  IN UINT8   VectorNum,\r
-  IN VOID    *OldVectorAddr\r
+  IN VOID   *NewVectorAddr,\r
+  IN UINT8  VectorNum,\r
+  IN VOID   *OldVectorAddr\r
   );\r
 \r
 /**\r
@@ -258,9 +258,9 @@ AsmVectorNumFixup (
 **/\r
 EFI_STATUS\r
 ReadAndVerifyVectorInfo (\r
-  IN  EFI_VECTOR_HANDOFF_INFO       *VectorInfo,\r
-  OUT RESERVED_VECTORS_DATA         *ReservedVector,\r
-  IN  UINTN                         VectorCount\r
+  IN  EFI_VECTOR_HANDOFF_INFO  *VectorInfo,\r
+  OUT RESERVED_VECTORS_DATA    *ReservedVector,\r
+  IN  UINTN                    VectorCount\r
   );\r
 \r
 /**\r
@@ -272,7 +272,7 @@ ReadAndVerifyVectorInfo (
 **/\r
 CONST CHAR8 *\r
 GetExceptionNameStr (\r
-  IN EFI_EXCEPTION_TYPE          ExceptionType\r
+  IN EFI_EXCEPTION_TYPE  ExceptionType\r
   );\r
 \r
 /**\r
@@ -284,9 +284,9 @@ GetExceptionNameStr (
 **/\r
 VOID\r
 CommonExceptionHandlerWorker (\r
-  IN EFI_EXCEPTION_TYPE          ExceptionType,\r
-  IN EFI_SYSTEM_CONTEXT          SystemContext,\r
-  IN EXCEPTION_HANDLER_DATA      *ExceptionHandlerData\r
+  IN EFI_EXCEPTION_TYPE      ExceptionType,\r
+  IN EFI_SYSTEM_CONTEXT      SystemContext,\r
+  IN EXCEPTION_HANDLER_DATA  *ExceptionHandlerData\r
   );\r
 \r
 /**\r
@@ -301,7 +301,7 @@ CommonExceptionHandlerWorker (
 **/\r
 EFI_STATUS\r
 ArchSetupExceptionStack (\r
-  IN CPU_EXCEPTION_INIT_DATA        *StackSwitchData\r
+  IN CPU_EXCEPTION_INIT_DATA  *StackSwitchData\r
   );\r
 \r
 /**\r
@@ -318,4 +318,3 @@ AsmGetTssTemplateMap (
   );\r
 \r
 #endif\r
-\r

diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c
index fd59f09ecd082e21bd563b59cc9aee8bfe39fcc9..61f11e98f8dc6ecdd9561b8d506c72da28a30958 100644 (file)
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c
@@ -12,17 +12,17 @@
 #include <Library/MemoryAllocationLib.h>\r
 #include <Library/UefiBootServicesTableLib.h>\r
 \r
-CONST UINTN    mDoFarReturnFlag  = 0;\r
+CONST UINTN  mDoFarReturnFlag = 0;\r
 \r
-RESERVED_VECTORS_DATA       mReservedVectorsData[CPU_EXCEPTION_NUM];\r
-EFI_CPU_INTERRUPT_HANDLER   mExternalInterruptHandlerTable[CPU_EXCEPTION_NUM];\r
-UINTN                       mEnabledInterruptNum = 0;\r
+RESERVED_VECTORS_DATA      mReservedVectorsData[CPU_EXCEPTION_NUM];\r
+EFI_CPU_INTERRUPT_HANDLER  mExternalInterruptHandlerTable[CPU_EXCEPTION_NUM];\r
+UINTN                      mEnabledInterruptNum = 0;\r
 \r
-EXCEPTION_HANDLER_DATA      mExceptionHandlerData;\r
+EXCEPTION_HANDLER_DATA  mExceptionHandlerData;\r
 \r
-UINT8                       mNewStack[CPU_STACK_SWITCH_EXCEPTION_NUMBER *\r
-                                      CPU_KNOWN_GOOD_STACK_SIZE];\r
-UINT8                       mNewGdt[CPU_TSS_GDT_SIZE];\r
+UINT8  mNewStack[CPU_STACK_SWITCH_EXCEPTION_NUMBER *\r
+                 CPU_KNOWN_GOOD_STACK_SIZE];\r
+UINT8  mNewGdt[CPU_TSS_GDT_SIZE];\r
 \r
 /**\r
   Common exception handler.\r
@@ -33,8 +33,8 @@ UINT8                       mNewGdt[CPU_TSS_GDT_SIZE];
 VOID\r
 EFIAPI\r
 CommonExceptionHandler (\r
-  IN EFI_EXCEPTION_TYPE          ExceptionType,\r
-  IN EFI_SYSTEM_CONTEXT          SystemContext\r
+  IN EFI_EXCEPTION_TYPE  ExceptionType,\r
+  IN EFI_SYSTEM_CONTEXT  SystemContext\r
   )\r
 {\r
   CommonExceptionHandlerWorker (ExceptionType, SystemContext, &mExceptionHandlerData);\r
@@ -59,7 +59,7 @@ CommonExceptionHandler (
 EFI_STATUS\r
 EFIAPI\r
 InitializeCpuExceptionHandlers (\r
-  IN EFI_VECTOR_HANDOFF_INFO       *VectorInfo OPTIONAL\r
+  IN EFI_VECTOR_HANDOFF_INFO  *VectorInfo OPTIONAL\r
   )\r
 {\r
   mExceptionHandlerData.ReservedVectors          = mReservedVectorsData;\r
@@ -87,19 +87,19 @@ InitializeCpuExceptionHandlers (
 EFI_STATUS\r
 EFIAPI\r
 InitializeCpuInterruptHandlers (\r
-  IN EFI_VECTOR_HANDOFF_INFO       *VectorInfo OPTIONAL\r
+  IN EFI_VECTOR_HANDOFF_INFO  *VectorInfo OPTIONAL\r
   )\r
 {\r
-  EFI_STATUS                         Status;\r
-  IA32_IDT_GATE_DESCRIPTOR           *IdtTable;\r
-  IA32_DESCRIPTOR                    IdtDescriptor;\r
-  UINTN                              IdtEntryCount;\r
-  EXCEPTION_HANDLER_TEMPLATE_MAP     TemplateMap;\r
-  UINTN                              Index;\r
-  UINTN                              InterruptEntry;\r
-  UINT8                              *InterruptEntryCode;\r
-  RESERVED_VECTORS_DATA              *ReservedVectors;\r
-  EFI_CPU_INTERRUPT_HANDLER          *ExternalInterruptHandler;\r
+  EFI_STATUS                      Status;\r
+  IA32_IDT_GATE_DESCRIPTOR        *IdtTable;\r
+  IA32_DESCRIPTOR                 IdtDescriptor;\r
+  UINTN                           IdtEntryCount;\r
+  EXCEPTION_HANDLER_TEMPLATE_MAP  TemplateMap;\r
+  UINTN                           Index;\r
+  UINTN                           InterruptEntry;\r
+  UINT8                           *InterruptEntryCode;\r
+  RESERVED_VECTORS_DATA           *ReservedVectors;\r
+  EFI_CPU_INTERRUPT_HANDLER       *ExternalInterruptHandler;\r
 \r
   Status = gBS->AllocatePool (\r
                   EfiBootServicesCode,\r
@@ -107,7 +107,7 @@ InitializeCpuInterruptHandlers (
                   (VOID **)&ReservedVectors\r
                   );\r
   ASSERT (!EFI_ERROR (Status) && ReservedVectors != NULL);\r
-  SetMem ((VOID *) ReservedVectors, sizeof (RESERVED_VECTORS_DATA) * CPU_INTERRUPT_NUM, 0xff);\r
+  SetMem ((VOID *)ReservedVectors, sizeof (RESERVED_VECTORS_DATA) * CPU_INTERRUPT_NUM, 0xff);\r
   if (VectorInfo != NULL) {\r
     Status = ReadAndVerifyVectorInfo (VectorInfo, ReservedVectors, CPU_INTERRUPT_NUM);\r
     if (EFI_ERROR (Status)) {\r
@@ -127,6 +127,7 @@ InitializeCpuInterruptHandlers (
   if (IdtEntryCount > CPU_INTERRUPT_NUM) {\r
     IdtEntryCount = CPU_INTERRUPT_NUM;\r
   }\r
+\r
   //\r
   // Create Interrupt Descriptor Table and Copy the old IDT table in\r
   //\r
@@ -144,18 +145,18 @@ InitializeCpuInterruptHandlers (
                   );\r
   ASSERT (!EFI_ERROR (Status) && InterruptEntryCode != NULL);\r
 \r
-  InterruptEntry = (UINTN) InterruptEntryCode;\r
-  for (Index = 0; Index < CPU_INTERRUPT_NUM; Index ++) {\r
+  InterruptEntry = (UINTN)InterruptEntryCode;\r
+  for (Index = 0; Index < CPU_INTERRUPT_NUM; Index++) {\r
     CopyMem (\r
-      (VOID *) InterruptEntry,\r
-      (VOID *) TemplateMap.ExceptionStart,\r
+      (VOID *)InterruptEntry,\r
+      (VOID *)TemplateMap.ExceptionStart,\r
       TemplateMap.ExceptionStubHeaderSize\r
       );\r
-    AsmVectorNumFixup ((VOID *) InterruptEntry,  (UINT8) Index, (VOID *) TemplateMap.ExceptionStart);\r
+    AsmVectorNumFixup ((VOID *)InterruptEntry, (UINT8)Index, (VOID *)TemplateMap.ExceptionStart);\r
     InterruptEntry += TemplateMap.ExceptionStubHeaderSize;\r
   }\r
 \r
-  TemplateMap.ExceptionStart = (UINTN) InterruptEntryCode;\r
+  TemplateMap.ExceptionStart                     = (UINTN)InterruptEntryCode;\r
   mExceptionHandlerData.IdtEntryCount            = CPU_INTERRUPT_NUM;\r
   mExceptionHandlerData.ReservedVectors          = ReservedVectors;\r
   mExceptionHandlerData.ExternalInterruptHandler = ExternalInterruptHandler;\r
@@ -166,9 +167,9 @@ InitializeCpuInterruptHandlers (
   //\r
   // Load Interrupt Descriptor Table\r
   //\r
-  IdtDescriptor.Base  = (UINTN) IdtTable;\r
-  IdtDescriptor.Limit = (UINT16) (sizeof (IA32_IDT_GATE_DESCRIPTOR) * CPU_INTERRUPT_NUM - 1);\r
-  AsmWriteIdtr ((IA32_DESCRIPTOR *) &IdtDescriptor);\r
+  IdtDescriptor.Base  = (UINTN)IdtTable;\r
+  IdtDescriptor.Limit = (UINT16)(sizeof (IA32_IDT_GATE_DESCRIPTOR) * CPU_INTERRUPT_NUM - 1);\r
+  AsmWriteIdtr ((IA32_DESCRIPTOR *)&IdtDescriptor);\r
 \r
   return EFI_SUCCESS;\r
 }\r
@@ -199,8 +200,8 @@ InitializeCpuInterruptHandlers (
 EFI_STATUS\r
 EFIAPI\r
 RegisterCpuInterruptHandler (\r
-  IN EFI_EXCEPTION_TYPE            InterruptType,\r
-  IN EFI_CPU_INTERRUPT_HANDLER     InterruptHandler\r
+  IN EFI_EXCEPTION_TYPE         InterruptType,\r
+  IN EFI_CPU_INTERRUPT_HANDLER  InterruptHandler\r
   )\r
 {\r
   return RegisterCpuInterruptHandlerWorker (InterruptType, InterruptHandler, &mExceptionHandlerData);\r
@@ -230,14 +231,14 @@ RegisterCpuInterruptHandler (
 EFI_STATUS\r
 EFIAPI\r
 InitializeCpuExceptionHandlersEx (\r
-  IN EFI_VECTOR_HANDOFF_INFO            *VectorInfo OPTIONAL,\r
-  IN CPU_EXCEPTION_INIT_DATA            *InitData OPTIONAL\r
+  IN EFI_VECTOR_HANDOFF_INFO  *VectorInfo OPTIONAL,\r
+  IN CPU_EXCEPTION_INIT_DATA  *InitData OPTIONAL\r
   )\r
 {\r
-  EFI_STATUS                        Status;\r
-  CPU_EXCEPTION_INIT_DATA           EssData;\r
-  IA32_DESCRIPTOR                   Idtr;\r
-  IA32_DESCRIPTOR                   Gdtr;\r
+  EFI_STATUS               Status;\r
+  CPU_EXCEPTION_INIT_DATA  EssData;\r
+  IA32_DESCRIPTOR          Idtr;\r
+  IA32_DESCRIPTOR          Gdtr;\r
 \r
   //\r
   // To avoid repeat initialization of default handlers, the caller should pass\r
@@ -246,7 +247,7 @@ InitializeCpuExceptionHandlersEx (
   // version instead; or this method must be implemented as a simple wrapper of\r
   // non-ex version of it, if this version has to be called.\r
   //\r
-  if (InitData == NULL || InitData->X64.InitDefaultHandlers) {\r
+  if ((InitData == NULL) || InitData->X64.InitDefaultHandlers) {\r
     Status = InitializeCpuExceptionHandlers (VectorInfo);\r
   } else {\r
     Status = EFI_SUCCESS;\r
@@ -263,25 +264,26 @@ InitializeCpuExceptionHandlersEx (
         AsmReadIdtr (&Idtr);\r
         AsmReadGdtr (&Gdtr);\r
 \r
-        EssData.X64.Revision = CPU_EXCEPTION_INIT_DATA_REV;\r
-        EssData.X64.KnownGoodStackTop = (UINTN)mNewStack + sizeof (mNewStack);\r
-        EssData.X64.KnownGoodStackSize = CPU_KNOWN_GOOD_STACK_SIZE;\r
-        EssData.X64.StackSwitchExceptions = CPU_STACK_SWITCH_EXCEPTION_LIST;\r
+        EssData.X64.Revision                   = CPU_EXCEPTION_INIT_DATA_REV;\r
+        EssData.X64.KnownGoodStackTop          = (UINTN)mNewStack + sizeof (mNewStack);\r
+        EssData.X64.KnownGoodStackSize         = CPU_KNOWN_GOOD_STACK_SIZE;\r
+        EssData.X64.StackSwitchExceptions      = CPU_STACK_SWITCH_EXCEPTION_LIST;\r
         EssData.X64.StackSwitchExceptionNumber = CPU_STACK_SWITCH_EXCEPTION_NUMBER;\r
-        EssData.X64.IdtTable = (VOID *)Idtr.Base;\r
-        EssData.X64.IdtTableSize = Idtr.Limit + 1;\r
-        EssData.X64.GdtTable = mNewGdt;\r
-        EssData.X64.GdtTableSize = sizeof (mNewGdt);\r
-        EssData.X64.ExceptionTssDesc = mNewGdt + Gdtr.Limit + 1;\r
-        EssData.X64.ExceptionTssDescSize = CPU_TSS_DESC_SIZE;\r
-        EssData.X64.ExceptionTss = mNewGdt + Gdtr.Limit + 1 + CPU_TSS_DESC_SIZE;\r
-        EssData.X64.ExceptionTssSize = CPU_TSS_SIZE;\r
+        EssData.X64.IdtTable                   = (VOID *)Idtr.Base;\r
+        EssData.X64.IdtTableSize               = Idtr.Limit + 1;\r
+        EssData.X64.GdtTable                   = mNewGdt;\r
+        EssData.X64.GdtTableSize               = sizeof (mNewGdt);\r
+        EssData.X64.ExceptionTssDesc           = mNewGdt + Gdtr.Limit + 1;\r
+        EssData.X64.ExceptionTssDescSize       = CPU_TSS_DESC_SIZE;\r
+        EssData.X64.ExceptionTss               = mNewGdt + Gdtr.Limit + 1 + CPU_TSS_DESC_SIZE;\r
+        EssData.X64.ExceptionTssSize           = CPU_TSS_SIZE;\r
 \r
         InitData = &EssData;\r
       }\r
+\r
       Status = ArchSetupExceptionStack (InitData);\r
     }\r
   }\r
 \r
-  return  Status;\r
+  return Status;\r
 }\r

diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c
index 903449e0daa9109cdd81dc0c4ddfb1d17b4d0779..f13e8e70206ec7c9a823236c9a1c1f95934c1beb 100644 (file)
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c
@@ -18,13 +18,13 @@
 **/\r
 VOID\r
 ArchUpdateIdtEntry (\r
-  OUT IA32_IDT_GATE_DESCRIPTOR        *IdtEntry,\r
-  IN  UINTN                           InterruptHandler\r
+  OUT IA32_IDT_GATE_DESCRIPTOR  *IdtEntry,\r
+  IN  UINTN                     InterruptHandler\r
   )\r
 {\r
-  IdtEntry->Bits.OffsetLow   = (UINT16)(UINTN)InterruptHandler;\r
-  IdtEntry->Bits.OffsetHigh  = (UINT16)((UINTN)InterruptHandler >> 16);\r
-  IdtEntry->Bits.GateType    = IA32_IDT_GATE_TYPE_INTERRUPT_32;\r
+  IdtEntry->Bits.OffsetLow  = (UINT16)(UINTN)InterruptHandler;\r
+  IdtEntry->Bits.OffsetHigh = (UINT16)((UINTN)InterruptHandler >> 16);\r
+  IdtEntry->Bits.GateType   = IA32_IDT_GATE_TYPE_INTERRUPT_32;\r
 }\r
 \r
 /**\r
@@ -35,7 +35,7 @@ ArchUpdateIdtEntry (
 **/\r
 UINTN\r
 ArchGetIdtHandler (\r
-  IN IA32_IDT_GATE_DESCRIPTOR        *IdtEntry\r
+  IN IA32_IDT_GATE_DESCRIPTOR  *IdtEntry\r
   )\r
 {\r
   return (UINTN)IdtEntry->Bits.OffsetLow + (((UINTN)IdtEntry->Bits.OffsetHigh) << 16);\r
@@ -50,13 +50,13 @@ ArchGetIdtHandler (
 **/\r
 VOID\r
 ArchSaveExceptionContext (\r
-  IN UINTN                        ExceptionType,\r
-  IN EFI_SYSTEM_CONTEXT           SystemContext,\r
-  IN EXCEPTION_HANDLER_DATA       *ExceptionHandlerData\r
+  IN UINTN                   ExceptionType,\r
+  IN EFI_SYSTEM_CONTEXT      SystemContext,\r
+  IN EXCEPTION_HANDLER_DATA  *ExceptionHandlerData\r
   )\r
 {\r
-  IA32_EFLAGS32           Eflags;\r
-  RESERVED_VECTORS_DATA   *ReservedVectors;\r
+  IA32_EFLAGS32          Eflags;\r
+  RESERVED_VECTORS_DATA  *ReservedVectors;\r
 \r
   ReservedVectors = ExceptionHandlerData->ReservedVectors;\r
   //\r
@@ -71,13 +71,13 @@ ArchSaveExceptionContext (
   //\r
   // Clear IF flag to avoid old IDT handler enable interrupt by IRET\r
   //\r
-  Eflags.UintN = SystemContext.SystemContextIa32->Eflags;\r
-  Eflags.Bits.IF = 0;\r
+  Eflags.UintN                            = SystemContext.SystemContextIa32->Eflags;\r
+  Eflags.Bits.IF                          = 0;\r
   SystemContext.SystemContextIa32->Eflags = Eflags.UintN;\r
   //\r
   // Modify the EIP in stack, then old IDT handler will return to HookAfterStubBegin.\r
   //\r
-  SystemContext.SystemContextIa32->Eip    = (UINTN) ReservedVectors[ExceptionType].HookAfterStubHeaderCode;\r
+  SystemContext.SystemContextIa32->Eip = (UINTN)ReservedVectors[ExceptionType].HookAfterStubHeaderCode;\r
 }\r
 \r
 /**\r
@@ -89,14 +89,14 @@ ArchSaveExceptionContext (
 **/\r
 VOID\r
 ArchRestoreExceptionContext (\r
-  IN UINTN                        ExceptionType,\r
-  IN EFI_SYSTEM_CONTEXT           SystemContext,\r
-  IN EXCEPTION_HANDLER_DATA       *ExceptionHandlerData\r
+  IN UINTN                   ExceptionType,\r
+  IN EFI_SYSTEM_CONTEXT      SystemContext,\r
+  IN EXCEPTION_HANDLER_DATA  *ExceptionHandlerData\r
   )\r
 {\r
-  RESERVED_VECTORS_DATA   *ReservedVectors;\r
+  RESERVED_VECTORS_DATA  *ReservedVectors;\r
 \r
-  ReservedVectors = ExceptionHandlerData->ReservedVectors;\r
+  ReservedVectors                                = ExceptionHandlerData->ReservedVectors;\r
   SystemContext.SystemContextIa32->Eflags        = ReservedVectors[ExceptionType].OldFlags;\r
   SystemContext.SystemContextIa32->Cs            = ReservedVectors[ExceptionType].OldCs;\r
   SystemContext.SystemContextIa32->Eip           = ReservedVectors[ExceptionType].OldIp;\r
@@ -116,32 +116,33 @@ ArchRestoreExceptionContext (
 **/\r
 EFI_STATUS\r
 ArchSetupExceptionStack (\r
-  IN CPU_EXCEPTION_INIT_DATA      *StackSwitchData\r
+  IN CPU_EXCEPTION_INIT_DATA  *StackSwitchData\r
   )\r
 {\r
-  IA32_DESCRIPTOR                   Gdtr;\r
-  IA32_DESCRIPTOR                   Idtr;\r
-  IA32_IDT_GATE_DESCRIPTOR          *IdtTable;\r
-  IA32_TSS_DESCRIPTOR               *TssDesc;\r
-  IA32_TASK_STATE_SEGMENT           *Tss;\r
-  UINTN                             StackTop;\r
-  UINTN                             Index;\r
-  UINTN                             Vector;\r
-  UINTN                             TssBase;\r
-  UINTN                             GdtSize;\r
-  EXCEPTION_HANDLER_TEMPLATE_MAP    TemplateMap;\r
-\r
-  if (StackSwitchData == NULL ||\r
-      StackSwitchData->Ia32.Revision != CPU_EXCEPTION_INIT_DATA_REV ||\r
-      StackSwitchData->Ia32.KnownGoodStackTop == 0 ||\r
-      StackSwitchData->Ia32.KnownGoodStackSize == 0 ||\r
-      StackSwitchData->Ia32.StackSwitchExceptions == NULL ||\r
-      StackSwitchData->Ia32.StackSwitchExceptionNumber == 0 ||\r
-      StackSwitchData->Ia32.StackSwitchExceptionNumber > CPU_EXCEPTION_NUM ||\r
-      StackSwitchData->Ia32.GdtTable == NULL ||\r
-      StackSwitchData->Ia32.IdtTable == NULL ||\r
-      StackSwitchData->Ia32.ExceptionTssDesc == NULL ||\r
-      StackSwitchData->Ia32.ExceptionTss == NULL) {\r
+  IA32_DESCRIPTOR                 Gdtr;\r
+  IA32_DESCRIPTOR                 Idtr;\r
+  IA32_IDT_GATE_DESCRIPTOR        *IdtTable;\r
+  IA32_TSS_DESCRIPTOR             *TssDesc;\r
+  IA32_TASK_STATE_SEGMENT         *Tss;\r
+  UINTN                           StackTop;\r
+  UINTN                           Index;\r
+  UINTN                           Vector;\r
+  UINTN                           TssBase;\r
+  UINTN                           GdtSize;\r
+  EXCEPTION_HANDLER_TEMPLATE_MAP  TemplateMap;\r
+\r
+  if ((StackSwitchData == NULL) ||\r
+      (StackSwitchData->Ia32.Revision != CPU_EXCEPTION_INIT_DATA_REV) ||\r
+      (StackSwitchData->Ia32.KnownGoodStackTop == 0) ||\r
+      (StackSwitchData->Ia32.KnownGoodStackSize == 0) ||\r
+      (StackSwitchData->Ia32.StackSwitchExceptions == NULL) ||\r
+      (StackSwitchData->Ia32.StackSwitchExceptionNumber == 0) ||\r
+      (StackSwitchData->Ia32.StackSwitchExceptionNumber > CPU_EXCEPTION_NUM) ||\r
+      (StackSwitchData->Ia32.GdtTable == NULL) ||\r
+      (StackSwitchData->Ia32.IdtTable == NULL) ||\r
+      (StackSwitchData->Ia32.ExceptionTssDesc == NULL) ||\r
+      (StackSwitchData->Ia32.ExceptionTss == NULL))\r
+  {\r
     return EFI_INVALID_PARAMETER;\r
   }\r
 \r
@@ -159,7 +160,8 @@ ArchSetupExceptionStack (
   }\r
 \r
   if ((UINTN)StackSwitchData->Ia32.ExceptionTssDesc + StackSwitchData->Ia32.ExceptionTssDescSize >\r
-      ((UINTN)(StackSwitchData->Ia32.GdtTable) + StackSwitchData->Ia32.GdtTableSize)) {\r
+      ((UINTN)(StackSwitchData->Ia32.GdtTable) + StackSwitchData->Ia32.GdtTableSize))\r
+  {\r
     return EFI_INVALID_PARAMETER;\r
   }\r
 \r
@@ -168,11 +170,14 @@ ArchSetupExceptionStack (
   // specified.\r
   //\r
   if (StackSwitchData->Ia32.ExceptionTssDescSize <\r
-      sizeof (IA32_TSS_DESCRIPTOR) * (StackSwitchData->Ia32.StackSwitchExceptionNumber + 1)) {\r
+      sizeof (IA32_TSS_DESCRIPTOR) * (StackSwitchData->Ia32.StackSwitchExceptionNumber + 1))\r
+  {\r
     return EFI_INVALID_PARAMETER;\r
   }\r
+\r
   if (StackSwitchData->Ia32.ExceptionTssSize <\r
-      sizeof (IA32_TASK_STATE_SEGMENT) * (StackSwitchData->Ia32.StackSwitchExceptionNumber + 1)) {\r
+      sizeof (IA32_TASK_STATE_SEGMENT) * (StackSwitchData->Ia32.StackSwitchExceptionNumber + 1))\r
+  {\r
     return EFI_INVALID_PARAMETER;\r
   }\r
 \r
@@ -191,13 +196,14 @@ ArchSetupExceptionStack (
             (UINTN)(StackSwitchData->Ia32.GdtTable);\r
   if ((UINTN)StackSwitchData->Ia32.GdtTable != Gdtr.Base) {\r
     CopyMem (StackSwitchData->Ia32.GdtTable, (VOID *)Gdtr.Base, Gdtr.Limit + 1);\r
-    Gdtr.Base = (UINTN)StackSwitchData->Ia32.GdtTable;\r
+    Gdtr.Base  = (UINTN)StackSwitchData->Ia32.GdtTable;\r
     Gdtr.Limit = (UINT16)GdtSize - 1;\r
   }\r
 \r
   if ((UINTN)StackSwitchData->Ia32.IdtTable != Idtr.Base) {\r
     Idtr.Base = (UINTN)StackSwitchData->Ia32.IdtTable;\r
   }\r
+\r
   if (StackSwitchData->Ia32.IdtTableSize > 0) {\r
     Idtr.Limit = (UINT16)(StackSwitchData->Ia32.IdtTableSize - 1);\r
   }\r
@@ -208,14 +214,14 @@ ArchSetupExceptionStack (
   //\r
   TssBase = (UINTN)Tss;\r
 \r
-  TssDesc->Uint64          = 0;\r
-  TssDesc->Bits.LimitLow   = sizeof(IA32_TASK_STATE_SEGMENT) - 1;\r
-  TssDesc->Bits.BaseLow    = (UINT16)TssBase;\r
-  TssDesc->Bits.BaseMid    = (UINT8)(TssBase >> 16);\r
-  TssDesc->Bits.Type       = IA32_GDT_TYPE_TSS;\r
-  TssDesc->Bits.P          = 1;\r
-  TssDesc->Bits.LimitHigh  = 0;\r
-  TssDesc->Bits.BaseHigh   = (UINT8)(TssBase >> 24);\r
+  TssDesc->Uint64         = 0;\r
+  TssDesc->Bits.LimitLow  = sizeof (IA32_TASK_STATE_SEGMENT) - 1;\r
+  TssDesc->Bits.BaseLow   = (UINT16)TssBase;\r
+  TssDesc->Bits.BaseMid   = (UINT8)(TssBase >> 16);\r
+  TssDesc->Bits.Type      = IA32_GDT_TYPE_TSS;\r
+  TssDesc->Bits.P         = 1;\r
+  TssDesc->Bits.LimitHigh = 0;\r
+  TssDesc->Bits.BaseHigh  = (UINT8)(TssBase >> 24);\r
 \r
   //\r
   // Fixup exception task descriptor and task-state segment\r
@@ -234,7 +240,7 @@ ArchSetupExceptionStack (
     TssBase = (UINTN)Tss;\r
 \r
     TssDesc->Uint64         = 0;\r
-    TssDesc->Bits.LimitLow  = sizeof(IA32_TASK_STATE_SEGMENT) - 1;\r
+    TssDesc->Bits.LimitLow  = sizeof (IA32_TASK_STATE_SEGMENT) - 1;\r
     TssDesc->Bits.BaseLow   = (UINT16)TssBase;\r
     TssDesc->Bits.BaseMid   = (UINT8)(TssBase >> 16);\r
     TssDesc->Bits.Type      = IA32_GDT_TYPE_TSS;\r
@@ -246,14 +252,15 @@ ArchSetupExceptionStack (
     // Fixup TSS\r
     //\r
     Vector = StackSwitchData->Ia32.StackSwitchExceptions[Index];\r
-    if (Vector >= CPU_EXCEPTION_NUM ||\r
-        Vector >= (Idtr.Limit + 1) / sizeof (IA32_IDT_GATE_DESCRIPTOR)) {\r
+    if ((Vector >= CPU_EXCEPTION_NUM) ||\r
+        (Vector >= (Idtr.Limit + 1) / sizeof (IA32_IDT_GATE_DESCRIPTOR)))\r
+    {\r
       continue;\r
     }\r
 \r
     ZeroMem (Tss, sizeof (*Tss));\r
-    Tss->EIP    = (UINT32)(TemplateMap.ExceptionStart\r
-                           + Vector * TemplateMap.ExceptionStubHeaderSize);\r
+    Tss->EIP = (UINT32)(TemplateMap.ExceptionStart\r
+                        + Vector * TemplateMap.ExceptionStubHeaderSize);\r
     Tss->EFLAGS = 0x2;\r
     Tss->ESP    = StackTop;\r
     Tss->CR3    = AsmReadCr3 ();\r
@@ -264,7 +271,7 @@ ArchSetupExceptionStack (
     Tss->FS     = AsmReadFs ();\r
     Tss->GS     = AsmReadGs ();\r
 \r
-    StackTop   -= StackSwitchData->Ia32.KnownGoodStackSize;\r
+    StackTop -= StackSwitchData->Ia32.KnownGoodStackSize;\r
 \r
     //\r
     // Update IDT to use Task Gate for given exception\r
@@ -303,8 +310,8 @@ ArchSetupExceptionStack (
 VOID\r
 EFIAPI\r
 DumpCpuContext (\r
-  IN EFI_EXCEPTION_TYPE   ExceptionType,\r
-  IN EFI_SYSTEM_CONTEXT   SystemContext\r
+  IN EFI_EXCEPTION_TYPE  ExceptionType,\r
+  IN EFI_SYSTEM_CONTEXT  SystemContext\r
   )\r
 {\r
   InternalPrintMessage (\r
@@ -331,8 +338,10 @@ DumpCpuContext (
         (SystemContext.SystemContextIa32->ExceptionData & IA32_PF_EC_SGX)  != 0\r
         );\r
     }\r
+\r
     InternalPrintMessage ("\n");\r
   }\r
+\r
   InternalPrintMessage (\r
     "EIP  - %08x, CS  - %08x, EFLAGS - %08x\n",\r
     SystemContext.SystemContextIa32->Eip,\r
@@ -406,8 +415,8 @@ DumpCpuContext (
 **/\r
 VOID\r
 DumpImageAndCpuContent (\r
-  IN EFI_EXCEPTION_TYPE   ExceptionType,\r
-  IN EFI_SYSTEM_CONTEXT   SystemContext\r
+  IN EFI_EXCEPTION_TYPE  ExceptionType,\r
+  IN EFI_SYSTEM_CONTEXT  SystemContext\r
   )\r
 {\r
   DumpCpuContext (ExceptionType, SystemContext);\r
@@ -415,7 +424,8 @@ DumpImageAndCpuContent (
   // Dump module image base and module entry point by EIP\r
   //\r
   if ((ExceptionType == EXCEPT_IA32_PAGE_FAULT) &&\r
-      ((SystemContext.SystemContextIa32->ExceptionData & IA32_PF_EC_ID) != 0)) {\r
+      ((SystemContext.SystemContextIa32->ExceptionData & IA32_PF_EC_ID) != 0))\r
+  {\r
     //\r
     // The EIP in SystemContext could not be used\r
     // if it is page fault with I/D set.\r

diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchInterruptDefs.h b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchInterruptDefs.h
index fc37fbe5823fb7c52659a26b31bd0e1cf5932303..211d2abe4886c9ad5f82ebf23458f30580e3613f 100644 (file)
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchInterruptDefs.h
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchInterruptDefs.h
@@ -10,29 +10,29 @@
 #define _ARCH_CPU_INTERRUPT_DEFS_H_\r
 \r
 typedef struct {\r
-  EFI_SYSTEM_CONTEXT_IA32 SystemContext;\r
-  BOOLEAN                 ExceptionDataFlag;\r
-  UINTN                   OldIdtHandler;\r
+  EFI_SYSTEM_CONTEXT_IA32    SystemContext;\r
+  BOOLEAN                    ExceptionDataFlag;\r
+  UINTN                      OldIdtHandler;\r
 } EXCEPTION_HANDLER_CONTEXT;\r
 \r
 //\r
 // Register Structure Definitions\r
 //\r
 typedef struct {\r
-  EFI_STATUS_CODE_DATA      Header;\r
-  EFI_SYSTEM_CONTEXT_IA32   SystemContext;\r
+  EFI_STATUS_CODE_DATA       Header;\r
+  EFI_SYSTEM_CONTEXT_IA32    SystemContext;\r
 } CPU_STATUS_CODE_TEMPLATE;\r
 \r
 typedef struct {\r
-  SPIN_LOCK   SpinLock;\r
-  UINT32      ApicId;\r
-  UINT32      Attribute;\r
-  UINTN       ExceptonHandler;\r
-  UINTN       OldFlags;\r
-  UINTN       OldCs;\r
-  UINTN       OldIp;\r
-  UINTN       ExceptionData;\r
-  UINT8       HookAfterStubHeaderCode[HOOKAFTER_STUB_SIZE];\r
+  SPIN_LOCK    SpinLock;\r
+  UINT32       ApicId;\r
+  UINT32       Attribute;\r
+  UINTN        ExceptonHandler;\r
+  UINTN        OldFlags;\r
+  UINTN        OldCs;\r
+  UINTN        OldIp;\r
+  UINTN        ExceptionData;\r
+  UINT8        HookAfterStubHeaderCode[HOOKAFTER_STUB_SIZE];\r
 } RESERVED_VECTORS_DATA;\r
 \r
 #define CPU_TSS_DESC_SIZE \\r

diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuException.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuException.c
index d256643435e55ab6e25dba69a63bc78c6db1af9b..687fc4177fe131163e0a214259c4a3ab0997ffbf 100644 (file)
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuException.c
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuException.c
@@ -13,11 +13,11 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
 #include <Library/MemoryAllocationLib.h>\r
 #include <Library/PcdLib.h>\r
 \r
-CONST UINTN    mDoFarReturnFlag  = 0;\r
+CONST UINTN  mDoFarReturnFlag = 0;\r
 \r
 typedef struct {\r
-  UINT8                   ExceptionStubHeader[HOOKAFTER_STUB_SIZE];\r
-  EXCEPTION_HANDLER_DATA  *ExceptionHandlerData;\r
+  UINT8                     ExceptionStubHeader[HOOKAFTER_STUB_SIZE];\r
+  EXCEPTION_HANDLER_DATA    *ExceptionHandlerData;\r
 } EXCEPTION0_STUB_HEADER;\r
 \r
 /**\r
@@ -34,9 +34,9 @@ GetExceptionHandlerData (
   VOID\r
   )\r
 {\r
-  IA32_DESCRIPTOR                  IdtDescriptor;\r
-  IA32_IDT_GATE_DESCRIPTOR         *IdtTable;\r
-  EXCEPTION0_STUB_HEADER           *Exception0StubHeader;\r
+  IA32_DESCRIPTOR           IdtDescriptor;\r
+  IA32_IDT_GATE_DESCRIPTOR  *IdtTable;\r
+  EXCEPTION0_STUB_HEADER    *Exception0StubHeader;\r
 \r
   AsmReadIdtr (&IdtDescriptor);\r
   IdtTable = (IA32_IDT_GATE_DESCRIPTOR *)IdtDescriptor.Base;\r
@@ -56,12 +56,13 @@ GetExceptionHandlerData (
 **/\r
 VOID\r
 SetExceptionHandlerData (\r
-  IN EXCEPTION_HANDLER_DATA        *ExceptionHandlerData\r
+  IN EXCEPTION_HANDLER_DATA  *ExceptionHandlerData\r
   )\r
 {\r
-  EXCEPTION0_STUB_HEADER           *Exception0StubHeader;\r
-  IA32_DESCRIPTOR                  IdtDescriptor;\r
-  IA32_IDT_GATE_DESCRIPTOR         *IdtTable;\r
+  EXCEPTION0_STUB_HEADER    *Exception0StubHeader;\r
+  IA32_DESCRIPTOR           IdtDescriptor;\r
+  IA32_IDT_GATE_DESCRIPTOR  *IdtTable;\r
+\r
   //\r
   // Duplicate the exception #0 stub header in pool and cache the ExceptionHandlerData just after the stub header.\r
   // So AP can get the ExceptionHandlerData by reading the IDT[0].\r
@@ -89,8 +90,8 @@ SetExceptionHandlerData (
 VOID\r
 EFIAPI\r
 CommonExceptionHandler (\r
-  IN EFI_EXCEPTION_TYPE   ExceptionType,\r
-  IN EFI_SYSTEM_CONTEXT   SystemContext\r
+  IN EFI_EXCEPTION_TYPE  ExceptionType,\r
+  IN EFI_SYSTEM_CONTEXT  SystemContext\r
   )\r
 {\r
   EXCEPTION_HANDLER_DATA  *ExceptionHandlerData;\r
@@ -120,12 +121,12 @@ CommonExceptionHandler (
 EFI_STATUS\r
 EFIAPI\r
 InitializeCpuExceptionHandlers (\r
-  IN EFI_VECTOR_HANDOFF_INFO       *VectorInfo OPTIONAL\r
+  IN EFI_VECTOR_HANDOFF_INFO  *VectorInfo OPTIONAL\r
   )\r
 {\r
-  EFI_STATUS                       Status;\r
-  EXCEPTION_HANDLER_DATA           *ExceptionHandlerData;\r
-  RESERVED_VECTORS_DATA            *ReservedVectors;\r
+  EFI_STATUS              Status;\r
+  EXCEPTION_HANDLER_DATA  *ExceptionHandlerData;\r
+  RESERVED_VECTORS_DATA   *ReservedVectors;\r
 \r
   ReservedVectors = AllocatePool (sizeof (RESERVED_VECTORS_DATA) * CPU_EXCEPTION_NUM);\r
   ASSERT (ReservedVectors != NULL);\r
@@ -166,7 +167,7 @@ InitializeCpuExceptionHandlers (
 EFI_STATUS\r
 EFIAPI\r
 InitializeCpuInterruptHandlers (\r
-  IN EFI_VECTOR_HANDOFF_INFO       *VectorInfo OPTIONAL\r
+  IN EFI_VECTOR_HANDOFF_INFO  *VectorInfo OPTIONAL\r
   )\r
 {\r
   return EFI_UNSUPPORTED;\r
@@ -198,8 +199,8 @@ InitializeCpuInterruptHandlers (
 EFI_STATUS\r
 EFIAPI\r
 RegisterCpuInterruptHandler (\r
-  IN EFI_EXCEPTION_TYPE            InterruptType,\r
-  IN EFI_CPU_INTERRUPT_HANDLER     InterruptHandler\r
+  IN EFI_EXCEPTION_TYPE         InterruptType,\r
+  IN EFI_CPU_INTERRUPT_HANDLER  InterruptHandler\r
   )\r
 {\r
   return EFI_UNSUPPORTED;\r
@@ -230,11 +231,11 @@ RegisterCpuInterruptHandler (
 EFI_STATUS\r
 EFIAPI\r
 InitializeCpuExceptionHandlersEx (\r
-  IN EFI_VECTOR_HANDOFF_INFO            *VectorInfo OPTIONAL,\r
-  IN CPU_EXCEPTION_INIT_DATA            *InitData OPTIONAL\r
+  IN EFI_VECTOR_HANDOFF_INFO  *VectorInfo OPTIONAL,\r
+  IN CPU_EXCEPTION_INIT_DATA  *InitData OPTIONAL\r
   )\r
 {\r
-  EFI_STATUS                        Status;\r
+  EFI_STATUS  Status;\r
 \r
   //\r
   // To avoid repeat initialization of default handlers, the caller should pass\r
@@ -243,7 +244,7 @@ InitializeCpuExceptionHandlersEx (
   // version instead; or this method must be implemented as a simple wrapper of\r
   // non-ex version of it, if this version has to be called.\r
   //\r
-  if (InitData == NULL || InitData->Ia32.InitDefaultHandlers) {\r
+  if ((InitData == NULL) || InitData->Ia32.InitDefaultHandlers) {\r
     Status = InitializeCpuExceptionHandlers (VectorInfo);\r
   } else {\r
     Status = EFI_SUCCESS;\r
@@ -253,10 +254,10 @@ InitializeCpuExceptionHandlersEx (
     //\r
     // Initializing stack switch is only necessary for Stack Guard functionality.\r
     //\r
-    if (PcdGetBool (PcdCpuStackGuard) && InitData != NULL) {\r
+    if (PcdGetBool (PcdCpuStackGuard) && (InitData != NULL)) {\r
       Status = ArchSetupExceptionStack (InitData);\r
     }\r
   }\r
 \r
-  return  Status;\r
+  return Status;\r
 }\r

diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiDxeSmmCpuException.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiDxeSmmCpuException.c
index 892d349d4b37823125ce0524334aba0134a61b27..762ea2460f9191ebe10026e43b97fe540dfe446a 100644 (file)
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiDxeSmmCpuException.c
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiDxeSmmCpuException.c
@@ -19,14 +19,14 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
 **/\r
 VOID\r
 CommonExceptionHandlerWorker (\r
-  IN EFI_EXCEPTION_TYPE          ExceptionType,\r
-  IN EFI_SYSTEM_CONTEXT          SystemContext,\r
-  IN EXCEPTION_HANDLER_DATA      *ExceptionHandlerData\r
+  IN EFI_EXCEPTION_TYPE      ExceptionType,\r
+  IN EFI_SYSTEM_CONTEXT      SystemContext,\r
+  IN EXCEPTION_HANDLER_DATA  *ExceptionHandlerData\r
   )\r
 {\r
-  EXCEPTION_HANDLER_CONTEXT      *ExceptionHandlerContext;\r
-  RESERVED_VECTORS_DATA          *ReservedVectors;\r
-  EFI_CPU_INTERRUPT_HANDLER      *ExternalInterruptHandler;\r
+  EXCEPTION_HANDLER_CONTEXT  *ExceptionHandlerContext;\r
+  RESERVED_VECTORS_DATA      *ReservedVectors;\r
+  EFI_CPU_INTERRUPT_HANDLER  *ExternalInterruptHandler;\r
 \r
   if (ExceptionType == VC_EXCEPTION) {\r
     EFI_STATUS  Status;\r
@@ -45,68 +45,72 @@ CommonExceptionHandlerWorker (
     }\r
   }\r
 \r
-  ExceptionHandlerContext  = (EXCEPTION_HANDLER_CONTEXT *) (UINTN) (SystemContext.SystemContextIa32);\r
+  ExceptionHandlerContext  = (EXCEPTION_HANDLER_CONTEXT *)(UINTN)(SystemContext.SystemContextIa32);\r
   ReservedVectors          = ExceptionHandlerData->ReservedVectors;\r
   ExternalInterruptHandler = ExceptionHandlerData->ExternalInterruptHandler;\r
 \r
   switch (ReservedVectors[ExceptionType].Attribute) {\r
-  case EFI_VECTOR_HANDOFF_HOOK_BEFORE:\r
-    //\r
-    // The new exception handler registered by RegisterCpuInterruptHandler() is executed BEFORE original handler.\r
-    // Save the original handler to stack so the assembly code can jump to it instead of returning from handler.\r
-    //\r
-    ExceptionHandlerContext->ExceptionDataFlag = (mErrorCodeFlag & (1 << ExceptionType)) ? TRUE : FALSE;\r
-    ExceptionHandlerContext->OldIdtHandler     = ReservedVectors[ExceptionType].ExceptonHandler;\r
-    break;\r
-  case EFI_VECTOR_HANDOFF_HOOK_AFTER:\r
-    while (TRUE) {\r
-      //\r
-      // If spin-lock can be acquired, it's the first time entering here.\r
-      //\r
-      if (AcquireSpinLockOrFail (&ReservedVectors[ExceptionType].SpinLock)) {\r
-        //\r
-        // The new exception handler registered by RegisterCpuInterruptHandler() is executed AFTER original handler.\r
-        // Save the original handler to stack but skip running the new handler so the original handler is executed\r
-        // firstly.\r
-        //\r
-        ReservedVectors[ExceptionType].ApicId = GetApicId ();\r
-        ArchSaveExceptionContext (ExceptionType, SystemContext, ExceptionHandlerData);\r
-        ExceptionHandlerContext->ExceptionDataFlag = (mErrorCodeFlag & (1 << ExceptionType)) ? TRUE : FALSE;\r
-        ExceptionHandlerContext->OldIdtHandler     = ReservedVectors[ExceptionType].ExceptonHandler;\r
-        return;\r
-      }\r
+    case EFI_VECTOR_HANDOFF_HOOK_BEFORE:\r
       //\r
-      // If spin-lock cannot be acquired, it's the second time entering here.\r
-      // 'break' instead of 'return' is used so the new exception handler can be executed.\r
+      // The new exception handler registered by RegisterCpuInterruptHandler() is executed BEFORE original handler.\r
+      // Save the original handler to stack so the assembly code can jump to it instead of returning from handler.\r
       //\r
-      if (ReservedVectors[ExceptionType].ApicId == GetApicId ()) {\r
+      ExceptionHandlerContext->ExceptionDataFlag = (mErrorCodeFlag & (1 << ExceptionType)) ? TRUE : FALSE;\r
+      ExceptionHandlerContext->OldIdtHandler     = ReservedVectors[ExceptionType].ExceptonHandler;\r
+      break;\r
+    case EFI_VECTOR_HANDOFF_HOOK_AFTER:\r
+      while (TRUE) {\r
         //\r
-        // Old IDT handler has been executed, then restore CPU exception content to\r
-        // run new exception handler.\r
+        // If spin-lock can be acquired, it's the first time entering here.\r
         //\r
-        ArchRestoreExceptionContext (ExceptionType, SystemContext, ExceptionHandlerData);\r
+        if (AcquireSpinLockOrFail (&ReservedVectors[ExceptionType].SpinLock)) {\r
+          //\r
+          // The new exception handler registered by RegisterCpuInterruptHandler() is executed AFTER original handler.\r
+          // Save the original handler to stack but skip running the new handler so the original handler is executed\r
+          // firstly.\r
+          //\r
+          ReservedVectors[ExceptionType].ApicId = GetApicId ();\r
+          ArchSaveExceptionContext (ExceptionType, SystemContext, ExceptionHandlerData);\r
+          ExceptionHandlerContext->ExceptionDataFlag = (mErrorCodeFlag & (1 << ExceptionType)) ? TRUE : FALSE;\r
+          ExceptionHandlerContext->OldIdtHandler     = ReservedVectors[ExceptionType].ExceptonHandler;\r
+          return;\r
+        }\r
+\r
         //\r
-        // Release spin lock for ApicId\r
+        // If spin-lock cannot be acquired, it's the second time entering here.\r
+        // 'break' instead of 'return' is used so the new exception handler can be executed.\r
         //\r
-        ReleaseSpinLock (&ReservedVectors[ExceptionType].SpinLock);\r
-        break;\r
+        if (ReservedVectors[ExceptionType].ApicId == GetApicId ()) {\r
+          //\r
+          // Old IDT handler has been executed, then restore CPU exception content to\r
+          // run new exception handler.\r
+          //\r
+          ArchRestoreExceptionContext (ExceptionType, SystemContext, ExceptionHandlerData);\r
+          //\r
+          // Release spin lock for ApicId\r
+          //\r
+          ReleaseSpinLock (&ReservedVectors[ExceptionType].SpinLock);\r
+          break;\r
+        }\r
+\r
+        CpuPause ();\r
       }\r
-      CpuPause ();\r
-    }\r
-    break;\r
-  case 0xffffffff:\r
-    break;\r
-  default:\r
-    //\r
-    // It should never reach here\r
-    //\r
-    CpuDeadLoop ();\r
-    break;\r
+\r
+      break;\r
+    case 0xffffffff:\r
+      break;\r
+    default:\r
+      //\r
+      // It should never reach here\r
+      //\r
+      CpuDeadLoop ();\r
+      break;\r
   }\r
 \r
-  if (ExternalInterruptHandler != NULL &&\r
-      ExternalInterruptHandler[ExceptionType] != NULL) {\r
-    (ExternalInterruptHandler[ExceptionType]) (ExceptionType, SystemContext);\r
+  if ((ExternalInterruptHandler != NULL) &&\r
+      (ExternalInterruptHandler[ExceptionType] != NULL))\r
+  {\r
+    (ExternalInterruptHandler[ExceptionType])(ExceptionType, SystemContext);\r
   } else if (ExceptionType < CPU_EXCEPTION_NUM) {\r
     //\r
     // Get Spinlock to display CPU information\r
@@ -114,6 +118,7 @@ CommonExceptionHandlerWorker (
     while (!AcquireSpinLockOrFail (&ExceptionHandlerData->DisplayMessageSpinLock)) {\r
       CpuPause ();\r
     }\r
+\r
     //\r
     // Initialize the serial port before dumping.\r
     //\r
@@ -151,10 +156,10 @@ UpdateIdtTable (
   IN EXCEPTION_HANDLER_DATA          *ExceptionHandlerData\r
   )\r
 {\r
-  UINT16                             CodeSegment;\r
-  UINTN                              Index;\r
-  UINTN                              InterruptHandler;\r
-  RESERVED_VECTORS_DATA              *ReservedVectors;\r
+  UINT16                 CodeSegment;\r
+  UINTN                  Index;\r
+  UINTN                  InterruptHandler;\r
+  RESERVED_VECTORS_DATA  *ReservedVectors;\r
 \r
   ReservedVectors = ExceptionHandlerData->ReservedVectors;\r
   //\r
@@ -162,47 +167,47 @@ UpdateIdtTable (
   //\r
   CodeSegment = AsmReadCs ();\r
 \r
-  for (Index = 0; Index < ExceptionHandlerData->IdtEntryCount; Index ++) {\r
+  for (Index = 0; Index < ExceptionHandlerData->IdtEntryCount; Index++) {\r
     IdtTable[Index].Bits.Selector = CodeSegment;\r
     //\r
     // Check reserved vectors attributes\r
     //\r
     switch (ReservedVectors[Index].Attribute) {\r
-    case EFI_VECTOR_HANDOFF_DO_NOT_HOOK:\r
-      //\r
-      // Keep original IDT entry\r
-      //\r
-      continue;\r
-    case EFI_VECTOR_HANDOFF_HOOK_AFTER:\r
-      InitializeSpinLock (&ReservedVectors[Index].SpinLock);\r
-      CopyMem (\r
-        (VOID *) ReservedVectors[Index].HookAfterStubHeaderCode,\r
-        (VOID *) TemplateMap->HookAfterStubHeaderStart,\r
-        TemplateMap->ExceptionStubHeaderSize\r
-        );\r
-      AsmVectorNumFixup (\r
-        (VOID *) ReservedVectors[Index].HookAfterStubHeaderCode,\r
-        (UINT8) Index,\r
-        (VOID *) TemplateMap->HookAfterStubHeaderStart\r
-        );\r
+      case EFI_VECTOR_HANDOFF_DO_NOT_HOOK:\r
+        //\r
+        // Keep original IDT entry\r
+        //\r
+        continue;\r
+      case EFI_VECTOR_HANDOFF_HOOK_AFTER:\r
+        InitializeSpinLock (&ReservedVectors[Index].SpinLock);\r
+        CopyMem (\r
+          (VOID *)ReservedVectors[Index].HookAfterStubHeaderCode,\r
+          (VOID *)TemplateMap->HookAfterStubHeaderStart,\r
+          TemplateMap->ExceptionStubHeaderSize\r
+          );\r
+        AsmVectorNumFixup (\r
+          (VOID *)ReservedVectors[Index].HookAfterStubHeaderCode,\r
+          (UINT8)Index,\r
+          (VOID *)TemplateMap->HookAfterStubHeaderStart\r
+          );\r
       //\r
       // Go on the following code\r
       //\r
-    case EFI_VECTOR_HANDOFF_HOOK_BEFORE:\r
-      //\r
-      // Save original IDT handler address\r
-      //\r
-      ReservedVectors[Index].ExceptonHandler = ArchGetIdtHandler (&IdtTable[Index]);\r
+      case EFI_VECTOR_HANDOFF_HOOK_BEFORE:\r
+        //\r
+        // Save original IDT handler address\r
+        //\r
+        ReservedVectors[Index].ExceptonHandler = ArchGetIdtHandler (&IdtTable[Index]);\r
       //\r
       // Go on the following code\r
       //\r
-    default:\r
-      //\r
-      // Update new IDT entry\r
-      //\r
-      InterruptHandler = TemplateMap->ExceptionStart + Index * TemplateMap->ExceptionStubHeaderSize;\r
-      ArchUpdateIdtEntry (&IdtTable[Index], InterruptHandler);\r
-      break;\r
+      default:\r
+        //\r
+        // Update new IDT entry\r
+        //\r
+        InterruptHandler = TemplateMap->ExceptionStart + Index * TemplateMap->ExceptionStubHeaderSize;\r
+        ArchUpdateIdtEntry (&IdtTable[Index], InterruptHandler);\r
+        break;\r
     }\r
   }\r
 }\r
@@ -221,19 +226,19 @@ UpdateIdtTable (
 **/\r
 EFI_STATUS\r
 InitializeCpuExceptionHandlersWorker (\r
-  IN EFI_VECTOR_HANDOFF_INFO       *VectorInfo OPTIONAL,\r
-  IN OUT EXCEPTION_HANDLER_DATA    *ExceptionHandlerData\r
+  IN EFI_VECTOR_HANDOFF_INFO     *VectorInfo OPTIONAL,\r
+  IN OUT EXCEPTION_HANDLER_DATA  *ExceptionHandlerData\r
   )\r
 {\r
-  EFI_STATUS                       Status;\r
-  IA32_DESCRIPTOR                  IdtDescriptor;\r
-  UINTN                            IdtEntryCount;\r
-  EXCEPTION_HANDLER_TEMPLATE_MAP   TemplateMap;\r
-  IA32_IDT_GATE_DESCRIPTOR         *IdtTable;\r
-  RESERVED_VECTORS_DATA            *ReservedVectors;\r
+  EFI_STATUS                      Status;\r
+  IA32_DESCRIPTOR                 IdtDescriptor;\r
+  UINTN                           IdtEntryCount;\r
+  EXCEPTION_HANDLER_TEMPLATE_MAP  TemplateMap;\r
+  IA32_IDT_GATE_DESCRIPTOR        *IdtTable;\r
+  RESERVED_VECTORS_DATA           *ReservedVectors;\r
 \r
   ReservedVectors = ExceptionHandlerData->ReservedVectors;\r
-  SetMem ((VOID *) ReservedVectors, sizeof (RESERVED_VECTORS_DATA) * CPU_EXCEPTION_NUM, 0xff);\r
+  SetMem ((VOID *)ReservedVectors, sizeof (RESERVED_VECTORS_DATA) * CPU_EXCEPTION_NUM, 0xff);\r
   if (VectorInfo != NULL) {\r
     Status = ReadAndVerifyVectorInfo (VectorInfo, ReservedVectors, CPU_EXCEPTION_NUM);\r
     if (EFI_ERROR (Status)) {\r
@@ -253,7 +258,7 @@ InitializeCpuExceptionHandlersWorker (
     IdtEntryCount = CPU_EXCEPTION_NUM;\r
   }\r
 \r
-  IdtTable = (IA32_IDT_GATE_DESCRIPTOR *) IdtDescriptor.Base;\r
+  IdtTable = (IA32_IDT_GATE_DESCRIPTOR *)IdtDescriptor.Base;\r
   AsmGetTemplateAddressMap (&TemplateMap);\r
   ASSERT (TemplateMap.ExceptionStubHeaderSize <= HOOKAFTER_STUB_SIZE);\r
 \r
@@ -282,33 +287,33 @@ InitializeCpuExceptionHandlersWorker (
 **/\r
 EFI_STATUS\r
 RegisterCpuInterruptHandlerWorker (\r
-  IN EFI_EXCEPTION_TYPE            InterruptType,\r
-  IN EFI_CPU_INTERRUPT_HANDLER     InterruptHandler,\r
-  IN EXCEPTION_HANDLER_DATA        *ExceptionHandlerData\r
+  IN EFI_EXCEPTION_TYPE         InterruptType,\r
+  IN EFI_CPU_INTERRUPT_HANDLER  InterruptHandler,\r
+  IN EXCEPTION_HANDLER_DATA     *ExceptionHandlerData\r
   )\r
 {\r
-  UINTN                          EnabledInterruptNum;\r
-  RESERVED_VECTORS_DATA          *ReservedVectors;\r
-  EFI_CPU_INTERRUPT_HANDLER      *ExternalInterruptHandler;\r
+  UINTN                      EnabledInterruptNum;\r
+  RESERVED_VECTORS_DATA      *ReservedVectors;\r
+  EFI_CPU_INTERRUPT_HANDLER  *ExternalInterruptHandler;\r
 \r
   EnabledInterruptNum      = ExceptionHandlerData->IdtEntryCount;\r
   ReservedVectors          = ExceptionHandlerData->ReservedVectors;\r
   ExternalInterruptHandler = ExceptionHandlerData->ExternalInterruptHandler;\r
 \r
-  if (InterruptType < 0 || InterruptType >= (EFI_EXCEPTION_TYPE)EnabledInterruptNum ||\r
-      ReservedVectors[InterruptType].Attribute == EFI_VECTOR_HANDOFF_DO_NOT_HOOK) {\r
+  if ((InterruptType < 0) || (InterruptType >= (EFI_EXCEPTION_TYPE)EnabledInterruptNum) ||\r
+      (ReservedVectors[InterruptType].Attribute == EFI_VECTOR_HANDOFF_DO_NOT_HOOK))\r
+  {\r
     return EFI_UNSUPPORTED;\r
   }\r
 \r
-  if (InterruptHandler == NULL && ExternalInterruptHandler[InterruptType] == NULL) {\r
+  if ((InterruptHandler == NULL) && (ExternalInterruptHandler[InterruptType] == NULL)) {\r
     return EFI_INVALID_PARAMETER;\r
   }\r
 \r
-  if (InterruptHandler != NULL && ExternalInterruptHandler[InterruptType] != NULL) {\r
+  if ((InterruptHandler != NULL) && (ExternalInterruptHandler[InterruptType] != NULL)) {\r
     return EFI_ALREADY_STARTED;\r
   }\r
 \r
   ExternalInterruptHandler[InterruptType] = InterruptHandler;\r
   return EFI_SUCCESS;\r
 }\r
-\r

diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuException.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuException.c
index 01b5a2f1f4fcff4f7f93376d917f6b493044b780..c614d5b0b6f17274ea3c6ed7e77f7d1e6b5c47a4 100644 (file)
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuException.c
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuException.c
@@ -10,7 +10,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
 #include <Library/VmgExitLib.h>\r
 #include "CpuExceptionCommon.h"\r
 \r
-CONST UINTN    mDoFarReturnFlag  = 0;\r
+CONST UINTN  mDoFarReturnFlag = 0;\r
 \r
 /**\r
   Common exception handler.\r
@@ -21,8 +21,8 @@ CONST UINTN    mDoFarReturnFlag  = 0;
 VOID\r
 EFIAPI\r
 CommonExceptionHandler (\r
-  IN EFI_EXCEPTION_TYPE   ExceptionType,\r
-  IN EFI_SYSTEM_CONTEXT   SystemContext\r
+  IN EFI_EXCEPTION_TYPE  ExceptionType,\r
+  IN EFI_SYSTEM_CONTEXT  SystemContext\r
   )\r
 {\r
   if (ExceptionType == VC_EXCEPTION) {\r
@@ -79,26 +79,27 @@ CommonExceptionHandler (
 EFI_STATUS\r
 EFIAPI\r
 InitializeCpuExceptionHandlers (\r
-  IN EFI_VECTOR_HANDOFF_INFO       *VectorInfo OPTIONAL\r
+  IN EFI_VECTOR_HANDOFF_INFO  *VectorInfo OPTIONAL\r
   )\r
 {\r
-  EFI_STATUS                       Status;\r
-  RESERVED_VECTORS_DATA            ReservedVectorData[CPU_EXCEPTION_NUM];\r
-  IA32_DESCRIPTOR                  IdtDescriptor;\r
-  UINTN                            IdtEntryCount;\r
-  UINT16                           CodeSegment;\r
-  EXCEPTION_HANDLER_TEMPLATE_MAP   TemplateMap;\r
-  IA32_IDT_GATE_DESCRIPTOR         *IdtTable;\r
-  UINTN                            Index;\r
-  UINTN                            InterruptHandler;\r
+  EFI_STATUS                      Status;\r
+  RESERVED_VECTORS_DATA           ReservedVectorData[CPU_EXCEPTION_NUM];\r
+  IA32_DESCRIPTOR                 IdtDescriptor;\r
+  UINTN                           IdtEntryCount;\r
+  UINT16                          CodeSegment;\r
+  EXCEPTION_HANDLER_TEMPLATE_MAP  TemplateMap;\r
+  IA32_IDT_GATE_DESCRIPTOR        *IdtTable;\r
+  UINTN                           Index;\r
+  UINTN                           InterruptHandler;\r
 \r
   if (VectorInfo != NULL) {\r
-    SetMem ((VOID *) ReservedVectorData, sizeof (RESERVED_VECTORS_DATA) * CPU_EXCEPTION_NUM, 0xff);\r
+    SetMem ((VOID *)ReservedVectorData, sizeof (RESERVED_VECTORS_DATA) * CPU_EXCEPTION_NUM, 0xff);\r
     Status = ReadAndVerifyVectorInfo (VectorInfo, ReservedVectorData, CPU_EXCEPTION_NUM);\r
     if (EFI_ERROR (Status)) {\r
       return EFI_INVALID_PARAMETER;\r
     }\r
   }\r
+\r
   //\r
   // Read IDT descriptor and calculate IDT size\r
   //\r
@@ -110,6 +111,7 @@ InitializeCpuExceptionHandlers (
     //\r
     IdtEntryCount = CPU_EXCEPTION_NUM;\r
   }\r
+\r
   //\r
   // Use current CS as the segment selector of interrupt gate in IDT\r
   //\r
@@ -117,7 +119,7 @@ InitializeCpuExceptionHandlers (
 \r
   AsmGetTemplateAddressMap (&TemplateMap);\r
   IdtTable = (IA32_IDT_GATE_DESCRIPTOR *)IdtDescriptor.Base;\r
-  for (Index = 0; Index < IdtEntryCount; Index ++) {\r
+  for (Index = 0; Index < IdtEntryCount; Index++) {\r
     IdtTable[Index].Bits.Selector = CodeSegment;\r
     //\r
     // Check reserved vectors attributes if has, only EFI_VECTOR_HANDOFF_DO_NOT_HOOK\r
@@ -128,12 +130,14 @@ InitializeCpuExceptionHandlers (
         continue;\r
       }\r
     }\r
+\r
     //\r
     // Update IDT entry\r
     //\r
     InterruptHandler = TemplateMap.ExceptionStart + Index * TemplateMap.ExceptionStubHeaderSize;\r
     ArchUpdateIdtEntry (&IdtTable[Index], InterruptHandler);\r
   }\r
+\r
   return EFI_SUCCESS;\r
 }\r
 \r
@@ -156,7 +160,7 @@ InitializeCpuExceptionHandlers (
 EFI_STATUS\r
 EFIAPI\r
 InitializeCpuInterruptHandlers (\r
-  IN EFI_VECTOR_HANDOFF_INFO       *VectorInfo OPTIONAL\r
+  IN EFI_VECTOR_HANDOFF_INFO  *VectorInfo OPTIONAL\r
   )\r
 {\r
   return EFI_UNSUPPORTED;\r
@@ -188,8 +192,8 @@ InitializeCpuInterruptHandlers (
 EFI_STATUS\r
 EFIAPI\r
 RegisterCpuInterruptHandler (\r
-  IN EFI_EXCEPTION_TYPE            InterruptType,\r
-  IN EFI_CPU_INTERRUPT_HANDLER     InterruptHandler\r
+  IN EFI_EXCEPTION_TYPE         InterruptType,\r
+  IN EFI_CPU_INTERRUPT_HANDLER  InterruptHandler\r
   )\r
 {\r
   return EFI_UNSUPPORTED;\r
@@ -220,8 +224,8 @@ RegisterCpuInterruptHandler (
 EFI_STATUS\r
 EFIAPI\r
 InitializeCpuExceptionHandlersEx (\r
-  IN EFI_VECTOR_HANDOFF_INFO            *VectorInfo OPTIONAL,\r
-  IN CPU_EXCEPTION_INIT_DATA            *InitData OPTIONAL\r
+  IN EFI_VECTOR_HANDOFF_INFO  *VectorInfo OPTIONAL,\r
+  IN CPU_EXCEPTION_INIT_DATA  *InitData OPTIONAL\r
   )\r
 {\r
   return InitializeCpuExceptionHandlers (VectorInfo);\r

diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmException.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmException.c
index e7977d49b7719cbe3077db465ab28cef644c9c7a..77ee74579fb261e0a068f6ba4824c68811752546 100644 (file)
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmException.c
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmException.c
@@ -9,16 +9,17 @@
 #include <PiSmm.h>\r
 #include "CpuExceptionCommon.h"\r
 \r
-CONST UINTN   mDoFarReturnFlag   = 1;\r
+CONST UINTN  mDoFarReturnFlag = 1;\r
 \r
 //\r
 // Spin lock for CPU information display\r
 //\r
-SPIN_LOCK        mDisplayMessageSpinLock;\r
+SPIN_LOCK  mDisplayMessageSpinLock;\r
+\r
+RESERVED_VECTORS_DATA      mReservedVectorsData[CPU_EXCEPTION_NUM];\r
+EFI_CPU_INTERRUPT_HANDLER  mExternalInterruptHandlerTable[CPU_EXCEPTION_NUM];\r
+EXCEPTION_HANDLER_DATA     mExceptionHandlerData;\r
 \r
-RESERVED_VECTORS_DATA       mReservedVectorsData[CPU_EXCEPTION_NUM];\r
-EFI_CPU_INTERRUPT_HANDLER   mExternalInterruptHandlerTable[CPU_EXCEPTION_NUM];\r
-EXCEPTION_HANDLER_DATA      mExceptionHandlerData;\r
 /**\r
   Common exception handler.\r
 \r
@@ -28,8 +29,8 @@ EXCEPTION_HANDLER_DATA      mExceptionHandlerData;
 VOID\r
 EFIAPI\r
 CommonExceptionHandler (\r
-  IN EFI_EXCEPTION_TYPE          ExceptionType,\r
-  IN EFI_SYSTEM_CONTEXT          SystemContext\r
+  IN EFI_EXCEPTION_TYPE  ExceptionType,\r
+  IN EFI_SYSTEM_CONTEXT  SystemContext\r
   )\r
 {\r
   CommonExceptionHandlerWorker (ExceptionType, SystemContext, &mExceptionHandlerData);\r
@@ -54,7 +55,7 @@ CommonExceptionHandler (
 EFI_STATUS\r
 EFIAPI\r
 InitializeCpuExceptionHandlers (\r
-  IN EFI_VECTOR_HANDOFF_INFO       *VectorInfo OPTIONAL\r
+  IN EFI_VECTOR_HANDOFF_INFO  *VectorInfo OPTIONAL\r
   )\r
 {\r
   mExceptionHandlerData.ReservedVectors          = mReservedVectorsData;\r
@@ -82,7 +83,7 @@ InitializeCpuExceptionHandlers (
 EFI_STATUS\r
 EFIAPI\r
 InitializeCpuInterruptHandlers (\r
-  IN EFI_VECTOR_HANDOFF_INFO       *VectorInfo OPTIONAL\r
+  IN EFI_VECTOR_HANDOFF_INFO  *VectorInfo OPTIONAL\r
   )\r
 {\r
   return EFI_UNSUPPORTED;\r
@@ -114,8 +115,8 @@ InitializeCpuInterruptHandlers (
 EFI_STATUS\r
 EFIAPI\r
 RegisterCpuInterruptHandler (\r
-  IN EFI_EXCEPTION_TYPE            InterruptType,\r
-  IN EFI_CPU_INTERRUPT_HANDLER     InterruptHandler\r
+  IN EFI_EXCEPTION_TYPE         InterruptType,\r
+  IN EFI_CPU_INTERRUPT_HANDLER  InterruptHandler\r
   )\r
 {\r
   return RegisterCpuInterruptHandlerWorker (InterruptType, InterruptHandler, &mExceptionHandlerData);\r
@@ -146,8 +147,8 @@ RegisterCpuInterruptHandler (
 EFI_STATUS\r
 EFIAPI\r
 InitializeCpuExceptionHandlersEx (\r
-  IN EFI_VECTOR_HANDOFF_INFO            *VectorInfo OPTIONAL,\r
-  IN CPU_EXCEPTION_INIT_DATA            *InitData OPTIONAL\r
+  IN EFI_VECTOR_HANDOFF_INFO  *VectorInfo OPTIONAL,\r
+  IN CPU_EXCEPTION_INIT_DATA  *InitData OPTIONAL\r
   )\r
 {\r
   return InitializeCpuExceptionHandlers (VectorInfo);\r

diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
index d3da16e4dfa2958d819f85c5c19b11780098b327..cd7dccd48141025da8a1644fb0a6165b1e982f79 100644 (file)
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
@@ -17,8 +17,8 @@
 **/\r
 VOID\r
 ArchUpdateIdtEntry (\r
-  OUT IA32_IDT_GATE_DESCRIPTOR       *IdtEntry,\r
-  IN  UINTN                          InterruptHandler\r
+  OUT IA32_IDT_GATE_DESCRIPTOR  *IdtEntry,\r
+  IN  UINTN                     InterruptHandler\r
   )\r
 {\r
   IdtEntry->Bits.OffsetLow   = (UINT16)(UINTN)InterruptHandler;\r
@@ -35,11 +35,11 @@ ArchUpdateIdtEntry (
 **/\r
 UINTN\r
 ArchGetIdtHandler (\r
-  IN IA32_IDT_GATE_DESCRIPTOR        *IdtEntry\r
+  IN IA32_IDT_GATE_DESCRIPTOR  *IdtEntry\r
   )\r
 {\r
-  return IdtEntry->Bits.OffsetLow + (((UINTN) IdtEntry->Bits.OffsetHigh)  << 16) +\r
-                                    (((UINTN) IdtEntry->Bits.OffsetUpper) << 32);\r
+  return IdtEntry->Bits.OffsetLow + (((UINTN)IdtEntry->Bits.OffsetHigh)  << 16) +\r
+         (((UINTN)IdtEntry->Bits.OffsetUpper) << 32);\r
 }\r
 \r
 /**\r
@@ -51,13 +51,13 @@ ArchGetIdtHandler (
 **/\r
 VOID\r
 ArchSaveExceptionContext (\r
-  IN UINTN                        ExceptionType,\r
-  IN EFI_SYSTEM_CONTEXT           SystemContext,\r
-  IN EXCEPTION_HANDLER_DATA       *ExceptionHandlerData\r
+  IN UINTN                   ExceptionType,\r
+  IN EFI_SYSTEM_CONTEXT      SystemContext,\r
+  IN EXCEPTION_HANDLER_DATA  *ExceptionHandlerData\r
   )\r
 {\r
-  IA32_EFLAGS32           Eflags;\r
-  RESERVED_VECTORS_DATA   *ReservedVectors;\r
+  IA32_EFLAGS32          Eflags;\r
+  RESERVED_VECTORS_DATA  *ReservedVectors;\r
 \r
   ReservedVectors = ExceptionHandlerData->ReservedVectors;\r
   //\r
@@ -74,13 +74,13 @@ ArchSaveExceptionContext (
   //\r
   // Clear IF flag to avoid old IDT handler enable interrupt by IRET\r
   //\r
-  Eflags.UintN = SystemContext.SystemContextX64->Rflags;\r
-  Eflags.Bits.IF = 0;\r
+  Eflags.UintN                           = SystemContext.SystemContextX64->Rflags;\r
+  Eflags.Bits.IF                         = 0;\r
   SystemContext.SystemContextX64->Rflags = Eflags.UintN;\r
   //\r
   // Modify the EIP in stack, then old IDT handler will return to HookAfterStubBegin.\r
   //\r
-  SystemContext.SystemContextX64->Rip = (UINTN) ReservedVectors[ExceptionType].HookAfterStubHeaderCode;\r
+  SystemContext.SystemContextX64->Rip = (UINTN)ReservedVectors[ExceptionType].HookAfterStubHeaderCode;\r
 }\r
 \r
 /**\r
@@ -92,14 +92,14 @@ ArchSaveExceptionContext (
 **/\r
 VOID\r
 ArchRestoreExceptionContext (\r
-  IN UINTN                        ExceptionType,\r
-  IN EFI_SYSTEM_CONTEXT           SystemContext,\r
-  IN EXCEPTION_HANDLER_DATA       *ExceptionHandlerData\r
+  IN UINTN                   ExceptionType,\r
+  IN EFI_SYSTEM_CONTEXT      SystemContext,\r
+  IN EXCEPTION_HANDLER_DATA  *ExceptionHandlerData\r
   )\r
 {\r
-  RESERVED_VECTORS_DATA   *ReservedVectors;\r
+  RESERVED_VECTORS_DATA  *ReservedVectors;\r
 \r
-  ReservedVectors = ExceptionHandlerData->ReservedVectors;\r
+  ReservedVectors                               = ExceptionHandlerData->ReservedVectors;\r
   SystemContext.SystemContextX64->Ss            = ReservedVectors[ExceptionType].OldSs;\r
   SystemContext.SystemContextX64->Rsp           = ReservedVectors[ExceptionType].OldSp;\r
   SystemContext.SystemContextX64->Rflags        = ReservedVectors[ExceptionType].OldFlags;\r
@@ -121,31 +121,32 @@ ArchRestoreExceptionContext (
 **/\r
 EFI_STATUS\r
 ArchSetupExceptionStack (\r
-  IN CPU_EXCEPTION_INIT_DATA          *StackSwitchData\r
+  IN CPU_EXCEPTION_INIT_DATA  *StackSwitchData\r
   )\r
 {\r
-  IA32_DESCRIPTOR                   Gdtr;\r
-  IA32_DESCRIPTOR                   Idtr;\r
-  IA32_IDT_GATE_DESCRIPTOR          *IdtTable;\r
-  IA32_TSS_DESCRIPTOR               *TssDesc;\r
-  IA32_TASK_STATE_SEGMENT           *Tss;\r
-  UINTN                             StackTop;\r
-  UINTN                             Index;\r
-  UINTN                             Vector;\r
-  UINTN                             TssBase;\r
-  UINTN                             GdtSize;\r
-\r
-  if (StackSwitchData == NULL ||\r
-      StackSwitchData->Ia32.Revision != CPU_EXCEPTION_INIT_DATA_REV ||\r
-      StackSwitchData->X64.KnownGoodStackTop == 0 ||\r
-      StackSwitchData->X64.KnownGoodStackSize == 0 ||\r
-      StackSwitchData->X64.StackSwitchExceptions == NULL ||\r
-      StackSwitchData->X64.StackSwitchExceptionNumber == 0 ||\r
-      StackSwitchData->X64.StackSwitchExceptionNumber > CPU_EXCEPTION_NUM ||\r
-      StackSwitchData->X64.GdtTable == NULL ||\r
-      StackSwitchData->X64.IdtTable == NULL ||\r
-      StackSwitchData->X64.ExceptionTssDesc == NULL ||\r
-      StackSwitchData->X64.ExceptionTss == NULL) {\r
+  IA32_DESCRIPTOR           Gdtr;\r
+  IA32_DESCRIPTOR           Idtr;\r
+  IA32_IDT_GATE_DESCRIPTOR  *IdtTable;\r
+  IA32_TSS_DESCRIPTOR       *TssDesc;\r
+  IA32_TASK_STATE_SEGMENT   *Tss;\r
+  UINTN                     StackTop;\r
+  UINTN                     Index;\r
+  UINTN                     Vector;\r
+  UINTN                     TssBase;\r
+  UINTN                     GdtSize;\r
+\r
+  if ((StackSwitchData == NULL) ||\r
+      (StackSwitchData->Ia32.Revision != CPU_EXCEPTION_INIT_DATA_REV) ||\r
+      (StackSwitchData->X64.KnownGoodStackTop == 0) ||\r
+      (StackSwitchData->X64.KnownGoodStackSize == 0) ||\r
+      (StackSwitchData->X64.StackSwitchExceptions == NULL) ||\r
+      (StackSwitchData->X64.StackSwitchExceptionNumber == 0) ||\r
+      (StackSwitchData->X64.StackSwitchExceptionNumber > CPU_EXCEPTION_NUM) ||\r
+      (StackSwitchData->X64.GdtTable == NULL) ||\r
+      (StackSwitchData->X64.IdtTable == NULL) ||\r
+      (StackSwitchData->X64.ExceptionTssDesc == NULL) ||\r
+      (StackSwitchData->X64.ExceptionTss == NULL))\r
+  {\r
     return EFI_INVALID_PARAMETER;\r
   }\r
 \r
@@ -163,7 +164,8 @@ ArchSetupExceptionStack (
   }\r
 \r
   if (((UINTN)StackSwitchData->X64.ExceptionTssDesc + StackSwitchData->X64.ExceptionTssDescSize) >\r
-      ((UINTN)(StackSwitchData->X64.GdtTable) + StackSwitchData->X64.GdtTableSize)) {\r
+      ((UINTN)(StackSwitchData->X64.GdtTable) + StackSwitchData->X64.GdtTableSize))\r
+  {\r
     return EFI_INVALID_PARAMETER;\r
   }\r
 \r
@@ -173,6 +175,7 @@ ArchSetupExceptionStack (
   if (StackSwitchData->X64.ExceptionTssDescSize < sizeof (IA32_TSS_DESCRIPTOR)) {\r
     return EFI_INVALID_PARAMETER;\r
   }\r
+\r
   if (StackSwitchData->X64.ExceptionTssSize < sizeof (IA32_TASK_STATE_SEGMENT)) {\r
     return EFI_INVALID_PARAMETER;\r
   }\r
@@ -196,13 +199,14 @@ ArchSetupExceptionStack (
             (UINTN)(StackSwitchData->X64.GdtTable);\r
   if ((UINTN)StackSwitchData->X64.GdtTable != Gdtr.Base) {\r
     CopyMem (StackSwitchData->X64.GdtTable, (VOID *)Gdtr.Base, Gdtr.Limit + 1);\r
-    Gdtr.Base = (UINTN)StackSwitchData->X64.GdtTable;\r
+    Gdtr.Base  = (UINTN)StackSwitchData->X64.GdtTable;\r
     Gdtr.Limit = (UINT16)GdtSize - 1;\r
   }\r
 \r
   if ((UINTN)StackSwitchData->X64.IdtTable != Idtr.Base) {\r
     Idtr.Base = (UINTN)StackSwitchData->X64.IdtTable;\r
   }\r
+\r
   if (StackSwitchData->X64.IdtTableSize > 0) {\r
     Idtr.Limit = (UINT16)(StackSwitchData->X64.IdtTableSize - 1);\r
   }\r
@@ -213,16 +217,16 @@ ArchSetupExceptionStack (
   //\r
   TssBase = (UINTN)Tss;\r
 \r
-  TssDesc->Uint128.Uint64  = 0;\r
-  TssDesc->Uint128.Uint64_1= 0;\r
-  TssDesc->Bits.LimitLow   = sizeof(IA32_TASK_STATE_SEGMENT) - 1;\r
-  TssDesc->Bits.BaseLow    = (UINT16)TssBase;\r
-  TssDesc->Bits.BaseMidl   = (UINT8)(TssBase >> 16);\r
-  TssDesc->Bits.Type       = IA32_GDT_TYPE_TSS;\r
-  TssDesc->Bits.P          = 1;\r
-  TssDesc->Bits.LimitHigh  = 0;\r
-  TssDesc->Bits.BaseMidh   = (UINT8)(TssBase >> 24);\r
-  TssDesc->Bits.BaseHigh   = (UINT32)(TssBase >> 32);\r
+  TssDesc->Uint128.Uint64   = 0;\r
+  TssDesc->Uint128.Uint64_1 = 0;\r
+  TssDesc->Bits.LimitLow    = sizeof (IA32_TASK_STATE_SEGMENT) - 1;\r
+  TssDesc->Bits.BaseLow     = (UINT16)TssBase;\r
+  TssDesc->Bits.BaseMidl    = (UINT8)(TssBase >> 16);\r
+  TssDesc->Bits.Type        = IA32_GDT_TYPE_TSS;\r
+  TssDesc->Bits.P           = 1;\r
+  TssDesc->Bits.LimitHigh   = 0;\r
+  TssDesc->Bits.BaseMidh    = (UINT8)(TssBase >> 24);\r
+  TssDesc->Bits.BaseHigh    = (UINT32)(TssBase >> 32);\r
 \r
   //\r
   // Fixup exception task descriptor and task-state segment\r
@@ -236,16 +240,18 @@ ArchSetupExceptionStack (
     // Fixup IST\r
     //\r
     Tss->IST[Index] = StackTop;\r
-    StackTop -= StackSwitchData->X64.KnownGoodStackSize;\r
+    StackTop       -= StackSwitchData->X64.KnownGoodStackSize;\r
 \r
     //\r
     // Set the IST field to enable corresponding IST\r
     //\r
     Vector = StackSwitchData->X64.StackSwitchExceptions[Index];\r
-    if (Vector >= CPU_EXCEPTION_NUM ||\r
-        Vector >= (Idtr.Limit + 1) / sizeof (IA32_IDT_GATE_DESCRIPTOR)) {\r
+    if ((Vector >= CPU_EXCEPTION_NUM) ||\r
+        (Vector >= (Idtr.Limit + 1) / sizeof (IA32_IDT_GATE_DESCRIPTOR)))\r
+    {\r
       continue;\r
     }\r
+\r
     IdtTable[Vector].Bits.Reserved_0 = (UINT8)(Index + 1);\r
   }\r
 \r
@@ -276,8 +282,8 @@ ArchSetupExceptionStack (
 VOID\r
 EFIAPI\r
 DumpCpuContext (\r
-  IN EFI_EXCEPTION_TYPE   ExceptionType,\r
-  IN EFI_SYSTEM_CONTEXT   SystemContext\r
+  IN EFI_EXCEPTION_TYPE  ExceptionType,\r
+  IN EFI_SYSTEM_CONTEXT  SystemContext\r
   )\r
 {\r
   InternalPrintMessage (\r
@@ -304,8 +310,10 @@ DumpCpuContext (
         (SystemContext.SystemContextX64->ExceptionData & IA32_PF_EC_SGX)  != 0\r
         );\r
     }\r
+\r
     InternalPrintMessage ("\n");\r
   }\r
+\r
   InternalPrintMessage (\r
     "RIP  - %016lx, CS  - %016lx, RFLAGS - %016lx\n",\r
     SystemContext.SystemContextX64->Rip,\r
@@ -406,8 +414,8 @@ DumpCpuContext (
 **/\r
 VOID\r
 DumpImageAndCpuContent (\r
-  IN EFI_EXCEPTION_TYPE   ExceptionType,\r
-  IN EFI_SYSTEM_CONTEXT   SystemContext\r
+  IN EFI_EXCEPTION_TYPE  ExceptionType,\r
+  IN EFI_SYSTEM_CONTEXT  SystemContext\r
   )\r
 {\r
   DumpCpuContext (ExceptionType, SystemContext);\r
@@ -415,7 +423,8 @@ DumpImageAndCpuContent (
   // Dump module image base and module entry point by RIP\r
   //\r
   if ((ExceptionType == EXCEPT_IA32_PAGE_FAULT) &&\r
-      ((SystemContext.SystemContextX64->ExceptionData & IA32_PF_EC_ID) != 0)) {\r
+      ((SystemContext.SystemContextX64->ExceptionData & IA32_PF_EC_ID) != 0))\r
+  {\r
     //\r
     // The RIP in SystemContext could not be used\r
     // if it is page fault with I/D set.\r

diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchInterruptDefs.h b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchInterruptDefs.h
index c3a07862ea6daf3c9313c17554be62de6c9c0a06..008670cb0d4b63b4bba4e466d05005657278d936 100644 (file)
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchInterruptDefs.h
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchInterruptDefs.h
@@ -10,9 +10,9 @@
 #define _ARCH_CPU_INTERRUPT_DEFS_H_\r
 \r
 typedef struct {\r
-  EFI_SYSTEM_CONTEXT_X64  SystemContext;\r
-  BOOLEAN                 ExceptionDataFlag;\r
-  UINTN                   OldIdtHandler;\r
+  EFI_SYSTEM_CONTEXT_X64    SystemContext;\r
+  BOOLEAN                   ExceptionDataFlag;\r
+  UINTN                     OldIdtHandler;\r
 } EXCEPTION_HANDLER_CONTEXT;\r
 \r
 //\r
@@ -24,20 +24,20 @@ typedef struct {
 } CPU_STATUS_CODE_TEMPLATE;\r
 \r
 typedef struct {\r
-  SPIN_LOCK   SpinLock;\r
-  UINT32      ApicId;\r
-  UINT32      Attribute;\r
-  UINTN       ExceptonHandler;\r
-  UINTN       OldSs;\r
-  UINTN       OldSp;\r
-  UINTN       OldFlags;\r
-  UINTN       OldCs;\r
-  UINTN       OldIp;\r
-  UINTN       ExceptionData;\r
-  UINT8       HookAfterStubHeaderCode[HOOKAFTER_STUB_SIZE];\r
+  SPIN_LOCK    SpinLock;\r
+  UINT32       ApicId;\r
+  UINT32       Attribute;\r
+  UINTN        ExceptonHandler;\r
+  UINTN        OldSs;\r
+  UINTN        OldSp;\r
+  UINTN        OldFlags;\r
+  UINTN        OldCs;\r
+  UINTN        OldIp;\r
+  UINTN        ExceptionData;\r
+  UINT8        HookAfterStubHeaderCode[HOOKAFTER_STUB_SIZE];\r
 } RESERVED_VECTORS_DATA;\r
 \r
-#define CPU_TSS_DESC_SIZE sizeof (IA32_TSS_DESCRIPTOR)\r
-#define CPU_TSS_SIZE      sizeof (IA32_TASK_STATE_SEGMENT)\r
+#define CPU_TSS_DESC_SIZE  sizeof (IA32_TSS_DESCRIPTOR)\r
+#define CPU_TSS_SIZE       sizeof (IA32_TASK_STATE_SEGMENT)\r
 \r
 #endif\r

diff --git a/UefiCpuPkg/Library/CpuTimerLib/BaseCpuTimerLib.c b/UefiCpuPkg/Library/CpuTimerLib/BaseCpuTimerLib.c
index 6ddf917bad0fa95abac19e5069e27df8591a1c7d..98363bd8f7891cd7d67aa3a009f33ab7e7912800 100644 (file)
--- a/UefiCpuPkg/Library/CpuTimerLib/BaseCpuTimerLib.c
+++ b/UefiCpuPkg/Library/CpuTimerLib/BaseCpuTimerLib.c
@@ -38,4 +38,3 @@ InternalGetPerformanceCounterFrequency (
 {\r
   return CpuidCoreClockCalculateTscFrequency ();\r
 }\r
-\r

diff --git a/UefiCpuPkg/Library/CpuTimerLib/CpuTimerLib.c b/UefiCpuPkg/Library/CpuTimerLib/CpuTimerLib.c
index bce02eeef961644c2d27fa9c023ad7b763b69ce7..1955b90e5440f84627379a98822ea6df588c2fb4 100644 (file)
--- a/UefiCpuPkg/Library/CpuTimerLib/CpuTimerLib.c
+++ b/UefiCpuPkg/Library/CpuTimerLib/CpuTimerLib.c
@@ -13,7 +13,9 @@
 #include <Library/DebugLib.h>\r
 #include <Register/Cpuid.h>\r
 \r
-GUID mCpuCrystalFrequencyHobGuid = { 0xe1ec5ad0, 0x8569, 0x46bd, { 0x8d, 0xcd, 0x3b, 0x9f, 0x6f, 0x45, 0x82, 0x7a } };\r
+GUID  mCpuCrystalFrequencyHobGuid = {\r
+  0xe1ec5ad0, 0x8569, 0x46bd, { 0x8d, 0xcd, 0x3b, 0x9f, 0x6f, 0x45, 0x82, 0x7a }\r
+};\r
 \r
 /**\r
   Internal function to retrieves the 64-bit frequency in Hz.\r
@@ -41,11 +43,11 @@ CpuidCoreClockCalculateTscFrequency (
   VOID\r
   )\r
 {\r
-  UINT64                 TscFrequency;\r
-  UINT64                 CoreXtalFrequency;\r
-  UINT32                 RegEax;\r
-  UINT32                 RegEbx;\r
-  UINT32                 RegEcx;\r
+  UINT64  TscFrequency;\r
+  UINT64  CoreXtalFrequency;\r
+  UINT32  RegEax;\r
+  UINT32  RegEbx;\r
+  UINT32  RegEcx;\r
 \r
   //\r
   // Use CPUID leaf 0x15 Time Stamp Counter and Nominal Core Crystal Clock Information\r
@@ -57,11 +59,12 @@ CpuidCoreClockCalculateTscFrequency (
   //\r
   // If EAX or EBX returns 0, the XTAL ratio is not enumerated.\r
   //\r
-  if (RegEax == 0 || RegEbx ==0 ) {\r
+  if ((RegEax == 0) || (RegEbx == 0)) {\r
     ASSERT (RegEax != 0);\r
     ASSERT (RegEbx != 0);\r
     return 0;\r
   }\r
+\r
   //\r
   // If ECX returns 0, the XTAL frequency is not enumerated.\r
   // And PcdCpuCoreCrystalClockFrequency defined should base on processor series.\r
@@ -69,7 +72,7 @@ CpuidCoreClockCalculateTscFrequency (
   if (RegEcx == 0) {\r
     CoreXtalFrequency = PcdGet64 (PcdCpuCoreCrystalClockFrequency);\r
   } else {\r
-    CoreXtalFrequency = (UINT64) RegEcx;\r
+    CoreXtalFrequency = (UINT64)RegEcx;\r
   }\r
 \r
   //\r
@@ -99,7 +102,7 @@ InternalCpuDelay (
   //\r
   // The target timer count is calculated here\r
   //\r
-  Ticks = AsmReadTsc() + Delay;\r
+  Ticks = AsmReadTsc () + Delay;\r
 \r
   //\r
   // Wait until time out\r
@@ -107,8 +110,8 @@ InternalCpuDelay (
   // Thus, this function must be called within 10 years of reset since\r
   // Intel guarantees a minimum of 10 years before the TSC wraps.\r
   //\r
-  while (AsmReadTsc() <= Ticks) {\r
-    CpuPause();\r
+  while (AsmReadTsc () <= Ticks) {\r
+    CpuPause ();\r
   }\r
 }\r
 \r
@@ -128,7 +131,6 @@ MicroSecondDelay (
   IN UINTN  MicroSeconds\r
   )\r
 {\r
-\r
   InternalCpuDelay (\r
     DivU64x32 (\r
       MultU64x64 (\r
@@ -136,8 +138,8 @@ MicroSecondDelay (
         InternalGetPerformanceCounterFrequency ()\r
         ),\r
       1000000u\r
-    )\r
-  );\r
+      )\r
+    );\r
 \r
   return MicroSeconds;\r
 }\r
@@ -158,7 +160,6 @@ NanoSecondDelay (
   IN UINTN  NanoSeconds\r
   )\r
 {\r
-\r
   InternalCpuDelay (\r
     DivU64x32 (\r
       MultU64x64 (\r
@@ -166,8 +167,8 @@ NanoSecondDelay (
         InternalGetPerformanceCounterFrequency ()\r
         ),\r
       1000000000u\r
-    )\r
-  );\r
+      )\r
+    );\r
 \r
   return NanoSeconds;\r
 }\r
@@ -230,6 +231,7 @@ GetPerformanceCounterProperties (
   if (EndValue != NULL) {\r
     *EndValue = 0xffffffffffffffffULL;\r
   }\r
+\r
   return InternalGetPerformanceCounterFrequency ();\r
 }\r
 \r
@@ -269,9 +271,9 @@ GetTimeInNanoSecond (
   // Since 2^29 < 1,000,000,000 = 0x3B9ACA00 < 2^30, Remainder should < 2^(64-30) = 2^34,\r
   // i.e. highest bit set in Remainder should <= 33.\r
   //\r
-  Shift = MAX (0, HighBitSet64 (Remainder) - 33);\r
-  Remainder = RShiftU64 (Remainder, (UINTN) Shift);\r
-  Frequency = RShiftU64 (Frequency, (UINTN) Shift);\r
+  Shift        = MAX (0, HighBitSet64 (Remainder) - 33);\r
+  Remainder    = RShiftU64 (Remainder, (UINTN)Shift);\r
+  Frequency    = RShiftU64 (Frequency, (UINTN)Shift);\r
   NanoSeconds += DivU64x64Remainder (MultU64x32 (Remainder, 1000000000u), Frequency, NULL);\r
 \r
   return NanoSeconds;\r

diff --git a/UefiCpuPkg/Library/MicrocodeLib/MicrocodeLib.c b/UefiCpuPkg/Library/MicrocodeLib/MicrocodeLib.c
index 03a43fdae72954f17657bd3755bf6461c9c36b9b..767ec80f8af42b7c3c0d4dd4bae1837c524143bd 100644 (file)
--- a/UefiCpuPkg/Library/MicrocodeLib/MicrocodeLib.c
+++ b/UefiCpuPkg/Library/MicrocodeLib/MicrocodeLib.c
@@ -25,7 +25,7 @@ GetProcessorMicrocodeSignature (
   VOID\r
   )\r
 {\r
-  MSR_IA32_BIOS_SIGN_ID_REGISTER   BiosSignIdMsr;\r
+  MSR_IA32_BIOS_SIGN_ID_REGISTER  BiosSignIdMsr;\r
 \r
   AsmWriteMsr64 (MSR_IA32_BIOS_SIGN_ID, 0);\r
   AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, NULL);\r
@@ -44,12 +44,12 @@ GetProcessorMicrocodeCpuId (
   EDKII_PEI_MICROCODE_CPU_ID  *MicrocodeCpuId\r
   )\r
 {\r
-  MSR_IA32_PLATFORM_ID_REGISTER PlatformIdMsr;\r
+  MSR_IA32_PLATFORM_ID_REGISTER  PlatformIdMsr;\r
 \r
   ASSERT (MicrocodeCpuId != NULL);\r
 \r
-  PlatformIdMsr.Uint64 = AsmReadMsr64 (MSR_IA32_PLATFORM_ID);\r
-  MicrocodeCpuId->PlatformId = (UINT8) PlatformIdMsr.Bits.PlatformId;\r
+  PlatformIdMsr.Uint64       = AsmReadMsr64 (MSR_IA32_PLATFORM_ID);\r
+  MicrocodeCpuId->PlatformId = (UINT8)PlatformIdMsr.Bits.PlatformId;\r
   AsmCpuid (CPUID_VERSION_INFO, &MicrocodeCpuId->ProcessorSignature, NULL, NULL, NULL);\r
 }\r
 \r
@@ -71,10 +71,10 @@ GetProcessorMicrocodeCpuId (
 UINT32\r
 EFIAPI\r
 GetMicrocodeLength (\r
-  IN CPU_MICROCODE_HEADER *Microcode\r
+  IN CPU_MICROCODE_HEADER  *Microcode\r
   )\r
 {\r
-  UINT32   TotalSize;\r
+  UINT32  TotalSize;\r
 \r
   ASSERT (Microcode != NULL);\r
 \r
@@ -82,6 +82,7 @@ GetMicrocodeLength (
   if (Microcode->DataSize != 0) {\r
     TotalSize = Microcode->TotalSize;\r
   }\r
+\r
   return TotalSize;\r
 }\r
 \r
@@ -95,12 +96,12 @@ GetMicrocodeLength (
 VOID\r
 EFIAPI\r
 LoadMicrocode (\r
-  IN CPU_MICROCODE_HEADER *Microcode\r
+  IN CPU_MICROCODE_HEADER  *Microcode\r
   )\r
 {\r
   ASSERT (Microcode != NULL);\r
 \r
-  AsmWriteMsr64 (MSR_IA32_BIOS_UPDT_TRIG, (UINT64) (UINTN) (Microcode + 1));\r
+  AsmWriteMsr64 (MSR_IA32_BIOS_UPDT_TRIG, (UINT64)(UINTN)(Microcode + 1));\r
 }\r
 \r
 /**\r
@@ -119,13 +120,13 @@ LoadMicrocode (
 **/\r
 BOOLEAN\r
 IsProcessorMatchedMicrocode (\r
-  IN UINT32                           ProcessorSignature,\r
-  IN UINT32                           ProcessorFlags,\r
-  IN EDKII_PEI_MICROCODE_CPU_ID       *MicrocodeCpuId,\r
-  IN UINTN                            MicrocodeCpuIdCount\r
+  IN UINT32                      ProcessorSignature,\r
+  IN UINT32                      ProcessorFlags,\r
+  IN EDKII_PEI_MICROCODE_CPU_ID  *MicrocodeCpuId,\r
+  IN UINTN                       MicrocodeCpuIdCount\r
   )\r
 {\r
-  UINTN          Index;\r
+  UINTN  Index;\r
 \r
   if (MicrocodeCpuIdCount == 0) {\r
     return TRUE;\r
@@ -133,7 +134,8 @@ IsProcessorMatchedMicrocode (
 \r
   for (Index = 0; Index < MicrocodeCpuIdCount; Index++) {\r
     if ((ProcessorSignature == MicrocodeCpuId[Index].ProcessorSignature) &&\r
-        (ProcessorFlags & (1 << MicrocodeCpuId[Index].PlatformId)) != 0) {\r
+        ((ProcessorFlags & (1 << MicrocodeCpuId[Index].PlatformId)) != 0))\r
+    {\r
       return TRUE;\r
     }\r
   }\r
@@ -182,22 +184,22 @@ IsProcessorMatchedMicrocode (
 BOOLEAN\r
 EFIAPI\r
 IsValidMicrocode (\r
-  IN CPU_MICROCODE_HEADER       *Microcode,\r
-  IN UINTN                      MicrocodeLength,\r
-  IN UINT32                     MinimumRevision,\r
-  IN EDKII_PEI_MICROCODE_CPU_ID *MicrocodeCpuIds,\r
-  IN UINTN                      MicrocodeCpuIdCount,\r
-  IN BOOLEAN                    VerifyChecksum\r
+  IN CPU_MICROCODE_HEADER        *Microcode,\r
+  IN UINTN                       MicrocodeLength,\r
+  IN UINT32                      MinimumRevision,\r
+  IN EDKII_PEI_MICROCODE_CPU_ID  *MicrocodeCpuIds,\r
+  IN UINTN                       MicrocodeCpuIdCount,\r
+  IN BOOLEAN                     VerifyChecksum\r
   )\r
 {\r
-  UINTN                                   Index;\r
-  UINT32                                  DataSize;\r
-  UINT32                                  TotalSize;\r
-  CPU_MICROCODE_EXTENDED_TABLE            *ExtendedTable;\r
-  CPU_MICROCODE_EXTENDED_TABLE_HEADER     *ExtendedTableHeader;\r
-  UINT32                                  ExtendedTableLength;\r
-  UINT32                                  Sum32;\r
-  BOOLEAN                                 Match;\r
+  UINTN                                Index;\r
+  UINT32                               DataSize;\r
+  UINT32                               TotalSize;\r
+  CPU_MICROCODE_EXTENDED_TABLE         *ExtendedTable;\r
+  CPU_MICROCODE_EXTENDED_TABLE_HEADER  *ExtendedTableHeader;\r
+  UINT32                               ExtendedTableLength;\r
+  UINT32                               Sum32;\r
+  BOOLEAN                              Match;\r
 \r
   ASSERT (Microcode != NULL);\r
 \r
@@ -206,7 +208,7 @@ IsValidMicrocode (
   //   the input microcode buffer is so small that even cannot contain the header.\r
   //   the input microcode buffer is so large that exceeds MAX_ADDRESS.\r
   //\r
-  if ((MicrocodeLength < sizeof (CPU_MICROCODE_HEADER)) || (MicrocodeLength > (MAX_ADDRESS - (UINTN) Microcode))) {\r
+  if ((MicrocodeLength < sizeof (CPU_MICROCODE_HEADER)) || (MicrocodeLength > (MAX_ADDRESS - (UINTN)Microcode))) {\r
     return FALSE;\r
   }\r
 \r
@@ -249,7 +251,7 @@ IsValidMicrocode (
   //\r
   // The summation of all DWORDs in microcode should be zero.\r
   //\r
-  if (VerifyChecksum && (CalculateSum32 ((UINT32 *) Microcode, TotalSize) != 0)) {\r
+  if (VerifyChecksum && (CalculateSum32 ((UINT32 *)Microcode, TotalSize) != 0)) {\r
     return FALSE;\r
   }\r
 \r
@@ -272,29 +274,34 @@ IsValidMicrocode (
   if ((ExtendedTableLength < sizeof (CPU_MICROCODE_EXTENDED_TABLE_HEADER)) || ((ExtendedTableLength % 4) != 0)) {\r
     return FALSE;\r
   }\r
+\r
   //\r
   // Extended Table exist, check if the CPU in support list\r
   //\r
-  ExtendedTableHeader = (CPU_MICROCODE_EXTENDED_TABLE_HEADER *) ((UINTN) (Microcode + 1) + DataSize);\r
+  ExtendedTableHeader = (CPU_MICROCODE_EXTENDED_TABLE_HEADER *)((UINTN)(Microcode + 1) + DataSize);\r
   if (ExtendedTableHeader->ExtendedSignatureCount > MAX_UINT32 / sizeof (CPU_MICROCODE_EXTENDED_TABLE)) {\r
     return FALSE;\r
   }\r
+\r
   if (ExtendedTableHeader->ExtendedSignatureCount * sizeof (CPU_MICROCODE_EXTENDED_TABLE)\r
-      > ExtendedTableLength - sizeof (CPU_MICROCODE_EXTENDED_TABLE_HEADER)) {\r
+      > ExtendedTableLength - sizeof (CPU_MICROCODE_EXTENDED_TABLE_HEADER))\r
+  {\r
     return FALSE;\r
   }\r
+\r
   //\r
   // Check the extended table checksum\r
   //\r
-  if (VerifyChecksum && (CalculateSum32 ((UINT32 *) ExtendedTableHeader, ExtendedTableLength) != 0)) {\r
+  if (VerifyChecksum && (CalculateSum32 ((UINT32 *)ExtendedTableHeader, ExtendedTableLength) != 0)) {\r
     return FALSE;\r
   }\r
 \r
-  ExtendedTable = (CPU_MICROCODE_EXTENDED_TABLE *) (ExtendedTableHeader + 1);\r
-  for (Index = 0; Index < ExtendedTableHeader->ExtendedSignatureCount; Index ++) {\r
+  ExtendedTable = (CPU_MICROCODE_EXTENDED_TABLE *)(ExtendedTableHeader + 1);\r
+  for (Index = 0; Index < ExtendedTableHeader->ExtendedSignatureCount; Index++) {\r
     if (VerifyChecksum &&\r
         (ExtendedTable[Index].ProcessorSignature.Uint32 + ExtendedTable[Index].ProcessorFlag\r
-        + ExtendedTable[Index].Checksum != Sum32)) {\r
+         + ExtendedTable[Index].Checksum != Sum32))\r
+    {\r
       //\r
       // The extended table entry is valid when the summation of Processor Signature, Processor Flags\r
       // and Checksum equal to the coresponding summation from primary header. Because:\r
@@ -308,6 +315,7 @@ IsValidMicrocode (
       //\r
       continue;\r
     }\r
+\r
     Match = IsProcessorMatchedMicrocode (\r
               ExtendedTable[Index].ProcessorSignature.Uint32,\r
               ExtendedTable[Index].ProcessorFlag,\r
@@ -318,5 +326,6 @@ IsValidMicrocode (
       return TRUE;\r
     }\r
   }\r
+\r
   return FALSE;\r
 }\r

diff --git a/UefiCpuPkg/Library/MpInitLib/DxeMpLib.c b/UefiCpuPkg/Library/MpInitLib/DxeMpLib.c
index 93fc63bf93e3070d5e3ddffae14158d72aacc74c..9d9206d20915bc9d3d3a15b412d210cb142f24c1 100644 (file)
--- a/UefiCpuPkg/Library/MpInitLib/DxeMpLib.c
+++ b/UefiCpuPkg/Library/MpInitLib/DxeMpLib.c
@@ -18,21 +18,21 @@
 \r
 #include <Protocol/Timer.h>\r
 \r
-#define  AP_SAFE_STACK_SIZE    128\r
+#define  AP_SAFE_STACK_SIZE  128\r
 \r
-CPU_MP_DATA      *mCpuMpData = NULL;\r
-EFI_EVENT        mCheckAllApsEvent = NULL;\r
-EFI_EVENT        mMpInitExitBootServicesEvent = NULL;\r
-EFI_EVENT        mLegacyBootEvent = NULL;\r
-volatile BOOLEAN mStopCheckAllApsStatus = TRUE;\r
-VOID             *mReservedApLoopFunc = NULL;\r
-UINTN            mReservedTopOfApStack;\r
-volatile UINT32  mNumberToFinish = 0;\r
+CPU_MP_DATA       *mCpuMpData                  = NULL;\r
+EFI_EVENT         mCheckAllApsEvent            = NULL;\r
+EFI_EVENT         mMpInitExitBootServicesEvent = NULL;\r
+EFI_EVENT         mLegacyBootEvent             = NULL;\r
+volatile BOOLEAN  mStopCheckAllApsStatus       = TRUE;\r
+VOID              *mReservedApLoopFunc         = NULL;\r
+UINTN             mReservedTopOfApStack;\r
+volatile UINT32   mNumberToFinish = 0;\r
 \r
 //\r
 // Begin wakeup buffer allocation below 0x88000\r
 //\r
-STATIC EFI_PHYSICAL_ADDRESS mSevEsDxeWakeupBuffer = 0x88000;\r
+STATIC EFI_PHYSICAL_ADDRESS  mSevEsDxeWakeupBuffer = 0x88000;\r
 \r
 /**\r
   Enable Debug Agent to support source debugging on AP function.\r
@@ -70,7 +70,7 @@ GetCpuMpData (
 **/\r
 VOID\r
 SaveCpuMpData (\r
-  IN CPU_MP_DATA   *CpuMpData\r
+  IN CPU_MP_DATA  *CpuMpData\r
   )\r
 {\r
   mCpuMpData = CpuMpData;\r
@@ -86,12 +86,12 @@ SaveCpuMpData (
 **/\r
 UINTN\r
 GetWakeupBuffer (\r
-  IN UINTN                WakeupBufferSize\r
+  IN UINTN  WakeupBufferSize\r
   )\r
 {\r
-  EFI_STATUS              Status;\r
-  EFI_PHYSICAL_ADDRESS    StartAddress;\r
-  EFI_MEMORY_TYPE         MemoryType;\r
+  EFI_STATUS            Status;\r
+  EFI_PHYSICAL_ADDRESS  StartAddress;\r
+  EFI_MEMORY_TYPE       MemoryType;\r
 \r
   if (PcdGetBool (PcdSevEsIsEnabled)) {\r
     MemoryType = EfiReservedMemoryType;\r
@@ -115,6 +115,7 @@ GetWakeupBuffer (
   } else {\r
     StartAddress = 0x88000;\r
   }\r
+\r
   Status = gBS->AllocatePages (\r
                   AllocateMaxAddress,\r
                   MemoryType,\r
@@ -123,7 +124,7 @@ GetWakeupBuffer (
                   );\r
   ASSERT_EFI_ERROR (Status);\r
   if (EFI_ERROR (Status)) {\r
-    StartAddress = (EFI_PHYSICAL_ADDRESS) -1;\r
+    StartAddress = (EFI_PHYSICAL_ADDRESS)-1;\r
   } else if (PcdGetBool (PcdSevEsIsEnabled)) {\r
     //\r
     // Next SEV-ES wakeup buffer allocation must be below this allocation\r
@@ -131,10 +132,14 @@ GetWakeupBuffer (
     mSevEsDxeWakeupBuffer = StartAddress;\r
   }\r
 \r
-  DEBUG ((DEBUG_INFO, "WakeupBufferStart = %x, WakeupBufferSize = %x\n",\r
-                      (UINTN) StartAddress, WakeupBufferSize));\r
+  DEBUG ((\r
+    DEBUG_INFO,\r
+    "WakeupBufferStart = %x, WakeupBufferSize = %x\n",\r
+    (UINTN)StartAddress,\r
+    WakeupBufferSize\r
+    ));\r
 \r
-  return (UINTN) StartAddress;\r
+  return (UINTN)StartAddress;\r
 }\r
 \r
 /**\r
@@ -151,19 +156,19 @@ GetWakeupBuffer (
 **/\r
 UINTN\r
 GetModeTransitionBuffer (\r
-  IN UINTN                BufferSize\r
+  IN UINTN  BufferSize\r
   )\r
 {\r
-  EFI_STATUS              Status;\r
-  EFI_PHYSICAL_ADDRESS    StartAddress;\r
+  EFI_STATUS            Status;\r
+  EFI_PHYSICAL_ADDRESS  StartAddress;\r
 \r
   StartAddress = BASE_4GB - 1;\r
-  Status = gBS->AllocatePages (\r
-                  AllocateMaxAddress,\r
-                  EfiBootServicesCode,\r
-                  EFI_SIZE_TO_PAGES (BufferSize),\r
-                  &StartAddress\r
-                  );\r
+  Status       = gBS->AllocatePages (\r
+                        AllocateMaxAddress,\r
+                        EfiBootServicesCode,\r
+                        EFI_SIZE_TO_PAGES (BufferSize),\r
+                        &StartAddress\r
+                        );\r
   if (EFI_ERROR (Status)) {\r
     StartAddress = 0;\r
   }\r
@@ -194,27 +199,27 @@ GetSevEsAPMemory (
   // Allocate 1 page for AP jump table page\r
   //\r
   StartAddress = BASE_4GB - 1;\r
-  Status = gBS->AllocatePages (\r
-                  AllocateMaxAddress,\r
-                  EfiReservedMemoryType,\r
-                  1,\r
-                  &StartAddress\r
-                  );\r
+  Status       = gBS->AllocatePages (\r
+                        AllocateMaxAddress,\r
+                        EfiReservedMemoryType,\r
+                        1,\r
+                        &StartAddress\r
+                        );\r
   ASSERT_EFI_ERROR (Status);\r
 \r
-  DEBUG ((DEBUG_INFO, "Dxe: SevEsAPMemory = %lx\n", (UINTN) StartAddress));\r
+  DEBUG ((DEBUG_INFO, "Dxe: SevEsAPMemory = %lx\n", (UINTN)StartAddress));\r
 \r
   //\r
   // Save the SevEsAPMemory as the AP jump table.\r
   //\r
   Msr.GhcbPhysicalAddress = AsmReadMsr64 (MSR_SEV_ES_GHCB);\r
-  Ghcb = Msr.Ghcb;\r
+  Ghcb                    = Msr.Ghcb;\r
 \r
   VmgInit (Ghcb, &InterruptState);\r
-  VmgExit (Ghcb, SVM_EXIT_AP_JUMP_TABLE, 0, (UINT64) (UINTN) StartAddress);\r
+  VmgExit (Ghcb, SVM_EXIT_AP_JUMP_TABLE, 0, (UINT64)(UINTN)StartAddress);\r
   VmgDone (Ghcb, InterruptState);\r
 \r
-  return (UINTN) StartAddress;\r
+  return (UINTN)StartAddress;\r
 }\r
 \r
 /**\r
@@ -226,9 +231,9 @@ CheckAndUpdateApsStatus (
   VOID\r
   )\r
 {\r
-  UINTN                   ProcessorNumber;\r
-  EFI_STATUS              Status;\r
-  CPU_MP_DATA             *CpuMpData;\r
+  UINTN        ProcessorNumber;\r
+  EFI_STATUS   Status;\r
+  CPU_MP_DATA  *CpuMpData;\r
 \r
   CpuMpData = GetCpuMpData ();\r
 \r
@@ -236,13 +241,12 @@ CheckAndUpdateApsStatus (
   // First, check whether pending StartupAllAPs() exists.\r
   //\r
   if (CpuMpData->WaitEvent != NULL) {\r
-\r
     Status = CheckAllAPs ();\r
     //\r
     // If all APs finish for StartupAllAPs(), signal the WaitEvent for it.\r
     //\r
     if (Status != EFI_NOT_READY) {\r
-      Status = gBS->SignalEvent (CpuMpData->WaitEvent);\r
+      Status               = gBS->SignalEvent (CpuMpData->WaitEvent);\r
       CpuMpData->WaitEvent = NULL;\r
     }\r
   }\r
@@ -251,7 +255,6 @@ CheckAndUpdateApsStatus (
   // Second, check whether pending StartupThisAPs() callings exist.\r
   //\r
   for (ProcessorNumber = 0; ProcessorNumber < CpuMpData->CpuCount; ProcessorNumber++) {\r
-\r
     if (CpuMpData->CpuData[ProcessorNumber].WaitEvent == NULL) {\r
       continue;\r
     }\r
@@ -260,7 +263,7 @@ CheckAndUpdateApsStatus (
 \r
     if (Status != EFI_NOT_READY) {\r
       gBS->SignalEvent (CpuMpData->CpuData[ProcessorNumber].WaitEvent);\r
-     CpuMpData->CpuData[ProcessorNumber].WaitEvent = NULL;\r
+      CpuMpData->CpuData[ProcessorNumber].WaitEvent = NULL;\r
     }\r
   }\r
 }\r
@@ -279,8 +282,8 @@ CheckAndUpdateApsStatus (
 VOID\r
 EFIAPI\r
 CheckApsStatus (\r
-  IN  EFI_EVENT                           Event,\r
-  IN  VOID                                *Context\r
+  IN  EFI_EVENT  Event,\r
+  IN  VOID       *Context\r
   )\r
 {\r
   //\r
@@ -307,18 +310,20 @@ GetProtectedMode16CS (
   UINTN                    GdtEntryCount;\r
   UINT16                   Index;\r
 \r
-  Index = (UINT16) -1;\r
+  Index = (UINT16)-1;\r
   AsmReadGdtr (&GdtrDesc);\r
   GdtEntryCount = (GdtrDesc.Limit + 1) / sizeof (IA32_SEGMENT_DESCRIPTOR);\r
-  GdtEntry = (IA32_SEGMENT_DESCRIPTOR *) GdtrDesc.Base;\r
+  GdtEntry      = (IA32_SEGMENT_DESCRIPTOR *)GdtrDesc.Base;\r
   for (Index = 0; Index < GdtEntryCount; Index++) {\r
     if (GdtEntry->Bits.L == 0) {\r
-      if (GdtEntry->Bits.Type > 8 && GdtEntry->Bits.DB == 0) {\r
+      if ((GdtEntry->Bits.Type > 8) && (GdtEntry->Bits.DB == 0)) {\r
         break;\r
       }\r
     }\r
+\r
     GdtEntry++;\r
   }\r
+\r
   ASSERT (Index != GdtEntryCount);\r
   return Index * 8;\r
 }\r
@@ -340,15 +345,17 @@ GetProtectedModeCS (
 \r
   AsmReadGdtr (&GdtrDesc);\r
   GdtEntryCount = (GdtrDesc.Limit + 1) / sizeof (IA32_SEGMENT_DESCRIPTOR);\r
-  GdtEntry = (IA32_SEGMENT_DESCRIPTOR *) GdtrDesc.Base;\r
+  GdtEntry      = (IA32_SEGMENT_DESCRIPTOR *)GdtrDesc.Base;\r
   for (Index = 0; Index < GdtEntryCount; Index++) {\r
     if (GdtEntry->Bits.L == 0) {\r
-      if (GdtEntry->Bits.Type > 8 && GdtEntry->Bits.DB == 1) {\r
+      if ((GdtEntry->Bits.Type > 8) && (GdtEntry->Bits.DB == 1)) {\r
         break;\r
       }\r
     }\r
+\r
     GdtEntry++;\r
   }\r
+\r
   ASSERT (Index != GdtEntryCount);\r
   return Index * 8;\r
 }\r
@@ -364,11 +371,11 @@ RelocateApLoop (
   IN OUT VOID  *Buffer\r
   )\r
 {\r
-  CPU_MP_DATA            *CpuMpData;\r
-  BOOLEAN                MwaitSupport;\r
-  ASM_RELOCATE_AP_LOOP   AsmRelocateApLoopFunc;\r
-  UINTN                  ProcessorNumber;\r
-  UINTN                  StackStart;\r
+  CPU_MP_DATA           *CpuMpData;\r
+  BOOLEAN               MwaitSupport;\r
+  ASM_RELOCATE_AP_LOOP  AsmRelocateApLoopFunc;\r
+  UINTN                 ProcessorNumber;\r
+  UINTN                 StackStart;\r
 \r
   MpInitLibWhoAmI (&ProcessorNumber);\r
   CpuMpData    = GetCpuMpData ();\r
@@ -378,13 +385,14 @@ RelocateApLoop (
   } else {\r
     StackStart = mReservedTopOfApStack;\r
   }\r
-  AsmRelocateApLoopFunc = (ASM_RELOCATE_AP_LOOP) (UINTN) mReservedApLoopFunc;\r
+\r
+  AsmRelocateApLoopFunc = (ASM_RELOCATE_AP_LOOP)(UINTN)mReservedApLoopFunc;\r
   AsmRelocateApLoopFunc (\r
     MwaitSupport,\r
     CpuMpData->ApTargetCState,\r
     CpuMpData->PmCodeSegment,\r
     StackStart - ProcessorNumber * AP_SAFE_STACK_SIZE,\r
-    (UINTN) &mNumberToFinish,\r
+    (UINTN)&mNumberToFinish,\r
     CpuMpData->Pm16CodeSegment,\r
     CpuMpData->SevEsAPBuffer,\r
     CpuMpData->WakeupBuffer\r
@@ -406,32 +414,32 @@ RelocateApLoop (
 VOID\r
 EFIAPI\r
 MpInitChangeApLoopCallback (\r
-  IN EFI_EVENT                Event,\r
-  IN VOID                     *Context\r
+  IN EFI_EVENT  Event,\r
+  IN VOID       *Context\r
   )\r
 {\r
-  CPU_MP_DATA               *CpuMpData;\r
+  CPU_MP_DATA  *CpuMpData;\r
 \r
-  CpuMpData = GetCpuMpData ();\r
-  CpuMpData->PmCodeSegment = GetProtectedModeCS ();\r
+  CpuMpData                  = GetCpuMpData ();\r
+  CpuMpData->PmCodeSegment   = GetProtectedModeCS ();\r
   CpuMpData->Pm16CodeSegment = GetProtectedMode16CS ();\r
-  CpuMpData->ApLoopMode = PcdGet8 (PcdCpuApLoopMode);\r
-  mNumberToFinish = CpuMpData->CpuCount - 1;\r
+  CpuMpData->ApLoopMode      = PcdGet8 (PcdCpuApLoopMode);\r
+  mNumberToFinish            = CpuMpData->CpuCount - 1;\r
   WakeUpAP (CpuMpData, TRUE, 0, RelocateApLoop, NULL, TRUE);\r
   while (mNumberToFinish > 0) {\r
     CpuPause ();\r
   }\r
 \r
-  if (CpuMpData->SevEsIsEnabled && (CpuMpData->WakeupBuffer != (UINTN) -1)) {\r
+  if (CpuMpData->SevEsIsEnabled && (CpuMpData->WakeupBuffer != (UINTN)-1)) {\r
     //\r
     // There are APs present. Re-use reserved memory area below 1MB from\r
     // WakeupBuffer as the area to be used for transitioning to 16-bit mode\r
     // in support of booting of the AP by an OS.\r
     //\r
     CopyMem (\r
-      (VOID *) CpuMpData->WakeupBuffer,\r
-      (VOID *) (CpuMpData->AddressMap.RendezvousFunnelAddress +\r
-                  CpuMpData->AddressMap.SwitchToRealPM16ModeOffset),\r
+      (VOID *)CpuMpData->WakeupBuffer,\r
+      (VOID *)(CpuMpData->AddressMap.RendezvousFunnelAddress +\r
+               CpuMpData->AddressMap.SwitchToRealPM16ModeOffset),\r
       CpuMpData->AddressMap.SwitchToRealPM16ModeSize\r
       );\r
   }\r
@@ -446,16 +454,16 @@ MpInitChangeApLoopCallback (
 **/\r
 VOID\r
 InitMpGlobalData (\r
-  IN CPU_MP_DATA               *CpuMpData\r
+  IN CPU_MP_DATA  *CpuMpData\r
   )\r
 {\r
-  EFI_STATUS                          Status;\r
-  EFI_PHYSICAL_ADDRESS                Address;\r
-  UINTN                               ApSafeBufferSize;\r
-  UINTN                               Index;\r
-  EFI_GCD_MEMORY_SPACE_DESCRIPTOR     MemDesc;\r
-  UINTN                               StackBase;\r
-  CPU_INFO_IN_HOB                     *CpuInfoInHob;\r
+  EFI_STATUS                       Status;\r
+  EFI_PHYSICAL_ADDRESS             Address;\r
+  UINTN                            ApSafeBufferSize;\r
+  UINTN                            Index;\r
+  EFI_GCD_MEMORY_SPACE_DESCRIPTOR  MemDesc;\r
+  UINTN                            StackBase;\r
+  CPU_INFO_IN_HOB                  *CpuInfoInHob;\r
 \r
   SaveCpuMpData (CpuMpData);\r
 \r
@@ -485,7 +493,7 @@ InitMpGlobalData (
     //\r
     CpuInfoInHob = (CPU_INFO_IN_HOB *)(UINTN)CpuMpData->CpuInfoInHob;\r
     for (Index = 0; Index < CpuMpData->CpuCount; ++Index) {\r
-      if (CpuInfoInHob != NULL && CpuInfoInHob[Index].ApTopOfStack != 0) {\r
+      if ((CpuInfoInHob != NULL) && (CpuInfoInHob[Index].ApTopOfStack != 0)) {\r
         StackBase = (UINTN)CpuInfoInHob[Index].ApTopOfStack - CpuMpData->CpuApStackSize;\r
       } else {\r
         StackBase = CpuMpData->Buffer + Index * CpuMpData->CpuApStackSize;\r
@@ -501,8 +509,12 @@ InitMpGlobalData (
                       );\r
       ASSERT_EFI_ERROR (Status);\r
 \r
-      DEBUG ((DEBUG_INFO, "Stack Guard set at %lx [cpu%lu]!\n",\r
-              (UINT64)StackBase, (UINT64)Index));\r
+      DEBUG ((\r
+        DEBUG_INFO,\r
+        "Stack Guard set at %lx [cpu%lu]!\n",\r
+        (UINT64)StackBase,\r
+        (UINT64)Index\r
+        ));\r
     }\r
   }\r
 \r
@@ -514,9 +526,11 @@ InitMpGlobalData (
   // Allocating it in advance since memory services are not available in\r
   // Exit Boot Services callback function.\r
   //\r
-  ApSafeBufferSize  = EFI_PAGES_TO_SIZE (EFI_SIZE_TO_PAGES (\r
-                        CpuMpData->AddressMap.RelocateApLoopFuncSize\r
-                        ));\r
+  ApSafeBufferSize = EFI_PAGES_TO_SIZE (\r
+                       EFI_SIZE_TO_PAGES (\r
+                         CpuMpData->AddressMap.RelocateApLoopFuncSize\r
+                         )\r
+                       );\r
   Address = BASE_4GB - 1;\r
   Status  = gBS->AllocatePages (\r
                    AllocateMaxAddress,\r
@@ -526,7 +540,7 @@ InitMpGlobalData (
                    );\r
   ASSERT_EFI_ERROR (Status);\r
 \r
-  mReservedApLoopFunc = (VOID *) (UINTN) Address;\r
+  mReservedApLoopFunc = (VOID *)(UINTN)Address;\r
   ASSERT (mReservedApLoopFunc != NULL);\r
 \r
   //\r
@@ -545,9 +559,11 @@ InitMpGlobalData (
            );\r
   }\r
 \r
-  ApSafeBufferSize = EFI_PAGES_TO_SIZE (EFI_SIZE_TO_PAGES (\r
-                       CpuMpData->CpuCount * AP_SAFE_STACK_SIZE\r
-                       ));\r
+  ApSafeBufferSize = EFI_PAGES_TO_SIZE (\r
+                       EFI_SIZE_TO_PAGES (\r
+                         CpuMpData->CpuCount * AP_SAFE_STACK_SIZE\r
+                         )\r
+                       );\r
   Address = BASE_4GB - 1;\r
   Status  = gBS->AllocatePages (\r
                    AllocateMaxAddress,\r
@@ -557,7 +573,7 @@ InitMpGlobalData (
                    );\r
   ASSERT_EFI_ERROR (Status);\r
 \r
-  mReservedTopOfApStack = (UINTN) Address + ApSafeBufferSize;\r
+  mReservedTopOfApStack = (UINTN)Address + ApSafeBufferSize;\r
   ASSERT ((mReservedTopOfApStack & (UINTN)(CPU_STACK_ALIGNMENT - 1)) == 0);\r
   CopyMem (\r
     mReservedApLoopFunc,\r
@@ -684,15 +700,15 @@ InitMpGlobalData (
 EFI_STATUS\r
 EFIAPI\r
 MpInitLibStartupAllAPs (\r
-  IN  EFI_AP_PROCEDURE          Procedure,\r
-  IN  BOOLEAN                   SingleThread,\r
-  IN  EFI_EVENT                 WaitEvent               OPTIONAL,\r
-  IN  UINTN                     TimeoutInMicroseconds,\r
-  IN  VOID                      *ProcedureArgument      OPTIONAL,\r
-  OUT UINTN                     **FailedCpuList         OPTIONAL\r
+  IN  EFI_AP_PROCEDURE  Procedure,\r
+  IN  BOOLEAN           SingleThread,\r
+  IN  EFI_EVENT         WaitEvent               OPTIONAL,\r
+  IN  UINTN             TimeoutInMicroseconds,\r
+  IN  VOID              *ProcedureArgument      OPTIONAL,\r
+  OUT UINTN             **FailedCpuList         OPTIONAL\r
   )\r
 {\r
-  EFI_STATUS              Status;\r
+  EFI_STATUS  Status;\r
 \r
   //\r
   // Temporarily stop checkAllApsStatus for avoid resource dead-lock.\r
@@ -791,15 +807,15 @@ MpInitLibStartupAllAPs (
 EFI_STATUS\r
 EFIAPI\r
 MpInitLibStartupThisAP (\r
-  IN  EFI_AP_PROCEDURE          Procedure,\r
-  IN  UINTN                     ProcessorNumber,\r
-  IN  EFI_EVENT                 WaitEvent               OPTIONAL,\r
-  IN  UINTN                     TimeoutInMicroseconds,\r
-  IN  VOID                      *ProcedureArgument      OPTIONAL,\r
-  OUT BOOLEAN                   *Finished               OPTIONAL\r
+  IN  EFI_AP_PROCEDURE  Procedure,\r
+  IN  UINTN             ProcessorNumber,\r
+  IN  EFI_EVENT         WaitEvent               OPTIONAL,\r
+  IN  UINTN             TimeoutInMicroseconds,\r
+  IN  VOID              *ProcedureArgument      OPTIONAL,\r
+  OUT BOOLEAN           *Finished               OPTIONAL\r
   )\r
 {\r
-  EFI_STATUS              Status;\r
+  EFI_STATUS  Status;\r
 \r
   //\r
   // temporarily stop checkAllApsStatus for avoid resource dead-lock.\r
@@ -849,19 +865,19 @@ MpInitLibStartupThisAP (
 EFI_STATUS\r
 EFIAPI\r
 MpInitLibSwitchBSP (\r
-  IN UINTN                     ProcessorNumber,\r
-  IN BOOLEAN                   EnableOldBSP\r
+  IN UINTN    ProcessorNumber,\r
+  IN BOOLEAN  EnableOldBSP\r
   )\r
 {\r
-  EFI_STATUS                   Status;\r
-  EFI_TIMER_ARCH_PROTOCOL      *Timer;\r
-  UINT64                       TimerPeriod;\r
+  EFI_STATUS               Status;\r
+  EFI_TIMER_ARCH_PROTOCOL  *Timer;\r
+  UINT64                   TimerPeriod;\r
 \r
   TimerPeriod = 0;\r
   //\r
   // Locate Timer Arch Protocol\r
   //\r
-  Status = gBS->LocateProtocol (&gEfiTimerArchProtocolGuid, NULL, (VOID **) &Timer);\r
+  Status = gBS->LocateProtocol (&gEfiTimerArchProtocolGuid, NULL, (VOID **)&Timer);\r
   if (EFI_ERROR (Status)) {\r
     Timer = NULL;\r
   }\r
@@ -922,13 +938,13 @@ MpInitLibSwitchBSP (
 EFI_STATUS\r
 EFIAPI\r
 MpInitLibEnableDisableAP (\r
-  IN  UINTN                     ProcessorNumber,\r
-  IN  BOOLEAN                   EnableAP,\r
-  IN  UINT32                    *HealthFlag OPTIONAL\r
+  IN  UINTN    ProcessorNumber,\r
+  IN  BOOLEAN  EnableAP,\r
+  IN  UINT32   *HealthFlag OPTIONAL\r
   )\r
 {\r
-  EFI_STATUS     Status;\r
-  BOOLEAN        TempStopCheckState;\r
+  EFI_STATUS  Status;\r
+  BOOLEAN     TempStopCheckState;\r
 \r
   TempStopCheckState = FALSE;\r
   //\r
@@ -961,7 +977,7 @@ MpInitLibEnableDisableAP (
 **/\r
 EFI_STATUS\r
 PlatformShadowMicrocode (\r
-  IN OUT CPU_MP_DATA             *CpuMpData\r
+  IN OUT CPU_MP_DATA  *CpuMpData\r
   )\r
 {\r
   //\r

diff --git a/UefiCpuPkg/Library/MpInitLib/Microcode.c b/UefiCpuPkg/Library/MpInitLib/Microcode.c
index 105a9f84bf95bd0f7fc3f71747386a98ba0df547..f9f070fa8bf230e72b7643b5bd8f96212512905b 100644 (file)
--- a/UefiCpuPkg/Library/MpInitLib/Microcode.c
+++ b/UefiCpuPkg/Library/MpInitLib/Microcode.c
@@ -18,17 +18,17 @@
 **/\r
 VOID\r
 MicrocodeDetect (\r
-  IN CPU_MP_DATA             *CpuMpData,\r
-  IN UINTN                   ProcessorNumber\r
+  IN CPU_MP_DATA  *CpuMpData,\r
+  IN UINTN        ProcessorNumber\r
   )\r
 {\r
-  CPU_MICROCODE_HEADER                    *Microcode;\r
-  UINTN                                   MicrocodeEnd;\r
-  CPU_AP_DATA                             *BspData;\r
-  UINT32                                  LatestRevision;\r
-  CPU_MICROCODE_HEADER                    *LatestMicrocode;\r
-  UINT32                                  ThreadId;\r
-  EDKII_PEI_MICROCODE_CPU_ID              MicrocodeCpuId;\r
+  CPU_MICROCODE_HEADER        *Microcode;\r
+  UINTN                       MicrocodeEnd;\r
+  CPU_AP_DATA                 *BspData;\r
+  UINT32                      LatestRevision;\r
+  CPU_MICROCODE_HEADER        *LatestMicrocode;\r
+  UINT32                      ThreadId;\r
+  EDKII_PEI_MICROCODE_CPU_ID  MicrocodeCpuId;\r
 \r
   if (CpuMpData->MicrocodePatchRegionSize == 0) {\r
     //\r
@@ -47,7 +47,7 @@ MicrocodeDetect (
 \r
   GetProcessorMicrocodeCpuId (&MicrocodeCpuId);\r
 \r
-  if (ProcessorNumber != (UINTN) CpuMpData->BspNumber) {\r
+  if (ProcessorNumber != (UINTN)CpuMpData->BspNumber) {\r
     //\r
     // Direct use microcode of BSP if AP is the same as BSP.\r
     // Assume BSP calls this routine() before AP.\r
@@ -55,8 +55,9 @@ MicrocodeDetect (
     BspData = &(CpuMpData->CpuData[CpuMpData->BspNumber]);\r
     if ((BspData->ProcessorSignature == MicrocodeCpuId.ProcessorSignature) &&\r
         (BspData->PlatformId == MicrocodeCpuId.PlatformId) &&\r
-        (BspData->MicrocodeEntryAddr != 0)) {\r
-      LatestMicrocode = (CPU_MICROCODE_HEADER *)(UINTN) BspData->MicrocodeEntryAddr;\r
+        (BspData->MicrocodeEntryAddr != 0))\r
+    {\r
+      LatestMicrocode = (CPU_MICROCODE_HEADER *)(UINTN)BspData->MicrocodeEntryAddr;\r
       LatestRevision  = LatestMicrocode->UpdateRevision;\r
       goto LoadMicrocode;\r
     }\r
@@ -69,11 +70,11 @@ MicrocodeDetect (
   //\r
   LatestRevision  = 0;\r
   LatestMicrocode = NULL;\r
-  Microcode       = (CPU_MICROCODE_HEADER *) (UINTN) CpuMpData->MicrocodePatchAddress;\r
-  MicrocodeEnd    = (UINTN) Microcode + (UINTN) CpuMpData->MicrocodePatchRegionSize;\r
+  Microcode       = (CPU_MICROCODE_HEADER *)(UINTN)CpuMpData->MicrocodePatchAddress;\r
+  MicrocodeEnd    = (UINTN)Microcode + (UINTN)CpuMpData->MicrocodePatchRegionSize;\r
 \r
   do {\r
-    if (!IsValidMicrocode (Microcode, MicrocodeEnd - (UINTN) Microcode, LatestRevision, &MicrocodeCpuId, 1, TRUE)) {\r
+    if (!IsValidMicrocode (Microcode, MicrocodeEnd - (UINTN)Microcode, LatestRevision, &MicrocodeCpuId, 1, TRUE)) {\r
       //\r
       // It is the padding data between the microcode patches for microcode patches alignment.\r
       // Because the microcode patch is the multiple of 1-KByte, the padding data should not\r
@@ -81,14 +82,15 @@ MicrocodeDetect (
       // alignment value should be larger than 1-KByte. We could skip SIZE_1KB padding data to\r
       // find the next possible microcode patch header.\r
       //\r
-      Microcode = (CPU_MICROCODE_HEADER *) ((UINTN) Microcode + SIZE_1KB);\r
+      Microcode = (CPU_MICROCODE_HEADER *)((UINTN)Microcode + SIZE_1KB);\r
       continue;\r
     }\r
+\r
     LatestMicrocode = Microcode;\r
     LatestRevision  = LatestMicrocode->UpdateRevision;\r
 \r
-    Microcode = (CPU_MICROCODE_HEADER *) (((UINTN) Microcode) + GetMicrocodeLength (Microcode));\r
-  } while ((UINTN) Microcode < MicrocodeEnd);\r
+    Microcode = (CPU_MICROCODE_HEADER *)(((UINTN)Microcode) + GetMicrocodeLength (Microcode));\r
+  } while ((UINTN)Microcode < MicrocodeEnd);\r
 \r
 LoadMicrocode:\r
   if (LatestRevision != 0) {\r
@@ -97,7 +99,7 @@ LoadMicrocode:
     // patch header) for each processor even it's the same as the loaded one.\r
     // It will be used when building the microcode patch cache HOB.\r
     //\r
-    CpuMpData->CpuData[ProcessorNumber].MicrocodeEntryAddr = (UINTN) LatestMicrocode;\r
+    CpuMpData->CpuData[ProcessorNumber].MicrocodeEntryAddr = (UINTN)LatestMicrocode;\r
   }\r
 \r
   if (LatestRevision > GetProcessorMicrocodeSignature ()) {\r
@@ -109,6 +111,7 @@ LoadMicrocode:
     //\r
     LoadMicrocode (LatestMicrocode);\r
   }\r
+\r
   //\r
   // It's possible that the microcode fails to load. Just capture the CPU microcode revision after loading.\r
   //\r
@@ -129,15 +132,15 @@ LoadMicrocode:
 **/\r
 VOID\r
 ShadowMicrocodePatchWorker (\r
-  IN OUT CPU_MP_DATA             *CpuMpData,\r
-  IN     MICROCODE_PATCH_INFO    *Patches,\r
-  IN     UINTN                   PatchCount,\r
-  IN     UINTN                   TotalLoadSize\r
+  IN OUT CPU_MP_DATA           *CpuMpData,\r
+  IN     MICROCODE_PATCH_INFO  *Patches,\r
+  IN     UINTN                 PatchCount,\r
+  IN     UINTN                 TotalLoadSize\r
   )\r
 {\r
-  UINTN    Index;\r
-  VOID     *MicrocodePatchInRam;\r
-  UINT8    *Walker;\r
+  UINTN  Index;\r
+  VOID   *MicrocodePatchInRam;\r
+  UINT8  *Walker;\r
 \r
   ASSERT ((Patches != NULL) && (PatchCount != 0));\r
 \r
@@ -152,7 +155,7 @@ ShadowMicrocodePatchWorker (
   for (Walker = MicrocodePatchInRam, Index = 0; Index < PatchCount; Index++) {\r
     CopyMem (\r
       Walker,\r
-      (VOID *) Patches[Index].Address,\r
+      (VOID *)Patches[Index].Address,\r
       Patches[Index].Size\r
       );\r
     Walker += Patches[Index].Size;\r
@@ -161,13 +164,15 @@ ShadowMicrocodePatchWorker (
   //\r
   // Update the microcode patch related fields in CpuMpData\r
   //\r
-  CpuMpData->MicrocodePatchAddress    = (UINTN) MicrocodePatchInRam;\r
+  CpuMpData->MicrocodePatchAddress    = (UINTN)MicrocodePatchInRam;\r
   CpuMpData->MicrocodePatchRegionSize = TotalLoadSize;\r
 \r
   DEBUG ((\r
     DEBUG_INFO,\r
     "%a: Required microcode patches have been loaded at 0x%lx, with size 0x%lx.\n",\r
-    __FUNCTION__, CpuMpData->MicrocodePatchAddress, CpuMpData->MicrocodePatchRegionSize\r
+    __FUNCTION__,\r
+    CpuMpData->MicrocodePatchAddress,\r
+    CpuMpData->MicrocodePatchRegionSize\r
     ));\r
 \r
   return;\r
@@ -181,19 +186,19 @@ ShadowMicrocodePatchWorker (
 **/\r
 VOID\r
 ShadowMicrocodePatchByPcd (\r
-  IN OUT CPU_MP_DATA             *CpuMpData\r
+  IN OUT CPU_MP_DATA  *CpuMpData\r
   )\r
 {\r
-  UINTN                                  Index;\r
-  CPU_MICROCODE_HEADER                   *MicrocodeEntryPoint;\r
-  UINTN                                  MicrocodeEnd;\r
-  UINTN                                  TotalSize;\r
-  MICROCODE_PATCH_INFO                   *PatchInfoBuffer;\r
-  UINTN                                  MaxPatchNumber;\r
-  UINTN                                  PatchCount;\r
-  UINTN                                  TotalLoadSize;\r
-  EDKII_PEI_MICROCODE_CPU_ID             *MicrocodeCpuIds;\r
-  BOOLEAN                                Valid;\r
+  UINTN                       Index;\r
+  CPU_MICROCODE_HEADER        *MicrocodeEntryPoint;\r
+  UINTN                       MicrocodeEnd;\r
+  UINTN                       TotalSize;\r
+  MICROCODE_PATCH_INFO        *PatchInfoBuffer;\r
+  UINTN                       MaxPatchNumber;\r
+  UINTN                       PatchCount;\r
+  UINTN                       TotalLoadSize;\r
+  EDKII_PEI_MICROCODE_CPU_ID  *MicrocodeCpuIds;\r
+  BOOLEAN                     Valid;\r
 \r
   //\r
   // Initialize the microcode patch related fields in CpuMpData as the values\r
@@ -203,10 +208,10 @@ ShadowMicrocodePatchByPcd (
   CpuMpData->MicrocodePatchAddress    = PcdGet64 (PcdCpuMicrocodePatchAddress);\r
   CpuMpData->MicrocodePatchRegionSize = PcdGet64 (PcdCpuMicrocodePatchRegionSize);\r
 \r
-  MicrocodeEntryPoint    = (CPU_MICROCODE_HEADER *) (UINTN) CpuMpData->MicrocodePatchAddress;\r
-  MicrocodeEnd           = (UINTN) MicrocodeEntryPoint +\r
-                           (UINTN) CpuMpData->MicrocodePatchRegionSize;\r
-  if ((MicrocodeEntryPoint == NULL) || ((UINTN) MicrocodeEntryPoint == MicrocodeEnd)) {\r
+  MicrocodeEntryPoint = (CPU_MICROCODE_HEADER *)(UINTN)CpuMpData->MicrocodePatchAddress;\r
+  MicrocodeEnd        = (UINTN)MicrocodeEntryPoint +\r
+                        (UINTN)CpuMpData->MicrocodePatchRegionSize;\r
+  if ((MicrocodeEntryPoint == NULL) || ((UINTN)MicrocodeEntryPoint == MicrocodeEnd)) {\r
     //\r
     // There is no microcode patches\r
     //\r
@@ -242,7 +247,7 @@ ShadowMicrocodePatchByPcd (
   do {\r
     Valid = IsValidMicrocode (\r
               MicrocodeEntryPoint,\r
-              MicrocodeEnd - (UINTN) MicrocodeEntryPoint,\r
+              MicrocodeEnd - (UINTN)MicrocodeEntryPoint,\r
               0,\r
               MicrocodeCpuIds,\r
               CpuMpData->CpuCount,\r
@@ -252,7 +257,7 @@ ShadowMicrocodePatchByPcd (
       //\r
       // Padding data between the microcode patches, skip 1KB to check next entry.\r
       //\r
-      MicrocodeEntryPoint = (CPU_MICROCODE_HEADER *) (((UINTN) MicrocodeEntryPoint) + SIZE_1KB);\r
+      MicrocodeEntryPoint = (CPU_MICROCODE_HEADER *)(((UINTN)MicrocodeEntryPoint) + SIZE_1KB);\r
       continue;\r
     }\r
 \r
@@ -277,6 +282,7 @@ ShadowMicrocodePatchByPcd (
       if (PatchInfoBuffer == NULL) {\r
         goto OnExit;\r
       }\r
+\r
       MaxPatchNumber = MaxPatchNumber * 2;\r
     }\r
 \r
@@ -285,21 +291,23 @@ ShadowMicrocodePatchByPcd (
     //\r
     // Store the information of this microcode patch\r
     //\r
-    PatchInfoBuffer[PatchCount - 1].Address = (UINTN) MicrocodeEntryPoint;\r
+    PatchInfoBuffer[PatchCount - 1].Address = (UINTN)MicrocodeEntryPoint;\r
     PatchInfoBuffer[PatchCount - 1].Size    = TotalSize;\r
-    TotalLoadSize += TotalSize;\r
+    TotalLoadSize                          += TotalSize;\r
 \r
     //\r
     // Process the next microcode patch\r
     //\r
-    MicrocodeEntryPoint = (CPU_MICROCODE_HEADER *) ((UINTN) MicrocodeEntryPoint + TotalSize);\r
-  } while ((UINTN) MicrocodeEntryPoint < MicrocodeEnd);\r
+    MicrocodeEntryPoint = (CPU_MICROCODE_HEADER *)((UINTN)MicrocodeEntryPoint + TotalSize);\r
+  } while ((UINTN)MicrocodeEntryPoint < MicrocodeEnd);\r
 \r
   if (PatchCount != 0) {\r
     DEBUG ((\r
       DEBUG_INFO,\r
       "%a: 0x%x microcode patches will be loaded into memory, with size 0x%x.\n",\r
-      __FUNCTION__, PatchCount, TotalLoadSize\r
+      __FUNCTION__,\r
+      PatchCount,\r
+      TotalLoadSize\r
       ));\r
 \r
     ShadowMicrocodePatchWorker (CpuMpData, PatchInfoBuffer, PatchCount, TotalLoadSize);\r
@@ -309,6 +317,7 @@ OnExit:
   if (PatchInfoBuffer != NULL) {\r
     FreePool (PatchInfoBuffer);\r
   }\r
+\r
   FreePages (MicrocodeCpuIds, EFI_SIZE_TO_PAGES (CpuMpData->CpuCount * sizeof (EDKII_PEI_MICROCODE_CPU_ID)));\r
 }\r
 \r
@@ -319,10 +328,10 @@ OnExit:
 **/\r
 VOID\r
 ShadowMicrocodeUpdatePatch (\r
-  IN OUT CPU_MP_DATA             *CpuMpData\r
+  IN OUT CPU_MP_DATA  *CpuMpData\r
   )\r
 {\r
-  EFI_STATUS     Status;\r
+  EFI_STATUS  Status;\r
 \r
   Status = PlatformShadowMicrocode (CpuMpData);\r
   if (EFI_ERROR (Status)) {\r
@@ -347,16 +356,16 @@ ShadowMicrocodeUpdatePatch (
 **/\r
 BOOLEAN\r
 GetMicrocodePatchInfoFromHob (\r
-  UINT64                         *Address,\r
-  UINT64                         *RegionSize\r
+  UINT64  *Address,\r
+  UINT64  *RegionSize\r
   )\r
 {\r
-  EFI_HOB_GUID_TYPE            *GuidHob;\r
-  EDKII_MICROCODE_PATCH_HOB    *MicrocodePathHob;\r
+  EFI_HOB_GUID_TYPE          *GuidHob;\r
+  EDKII_MICROCODE_PATCH_HOB  *MicrocodePathHob;\r
 \r
   GuidHob = GetFirstGuidHob (&gEdkiiMicrocodePatchHobGuid);\r
   if (GuidHob == NULL) {\r
-    DEBUG((DEBUG_INFO, "%a: Microcode patch cache HOB is not found.\n", __FUNCTION__));\r
+    DEBUG ((DEBUG_INFO, "%a: Microcode patch cache HOB is not found.\n", __FUNCTION__));\r
     return FALSE;\r
   }\r
 \r
@@ -365,9 +374,12 @@ GetMicrocodePatchInfoFromHob (
   *Address    = MicrocodePathHob->MicrocodePatchAddress;\r
   *RegionSize = MicrocodePathHob->MicrocodePatchRegionSize;\r
 \r
-  DEBUG((\r
-    DEBUG_INFO, "%a: MicrocodeBase = 0x%lx, MicrocodeSize = 0x%lx\n",\r
-    __FUNCTION__, *Address, *RegionSize\r
+  DEBUG ((\r
+    DEBUG_INFO,\r
+    "%a: MicrocodeBase = 0x%lx, MicrocodeSize = 0x%lx\n",\r
+    __FUNCTION__,\r
+    *Address,\r
+    *RegionSize\r
     ));\r
 \r
   return TRUE;\r

diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c b/UefiCpuPkg/Library/MpInitLib/MpLib.c
index b390c558d4bd51f158e4a5ade038be42223af10c..2d8e9512ab98e261f8b6956aee3c98f76b6e7de8 100644 (file)
--- a/UefiCpuPkg/Library/MpInitLib/MpLib.c
+++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c
@@ -13,8 +13,7 @@
 #include <Register/Amd/Fam17Msr.h>\r
 #include <Register/Amd/Ghcb.h>\r
 \r
-EFI_GUID mCpuInitMpLibHobGuid = CPU_INIT_MP_LIB_HOB_GUID;\r
-\r
+EFI_GUID  mCpuInitMpLibHobGuid = CPU_INIT_MP_LIB_HOB_GUID;\r
 \r
 /**\r
   The function will check if BSP Execute Disable is enabled.\r
@@ -38,7 +37,7 @@ IsBspExecuteDisableEnabled (
   BOOLEAN                     Enabled;\r
   IA32_CR0                    Cr0;\r
 \r
-  Enabled = FALSE;\r
+  Enabled   = FALSE;\r
   Cr0.UintN = AsmReadCr0 ();\r
   if (Cr0.Bits.PG != 0) {\r
     //\r
@@ -78,12 +77,12 @@ IsBspExecuteDisableEnabled (
 VOID\r
 EFIAPI\r
 FutureBSPProc (\r
-  IN  VOID            *Buffer\r
+  IN  VOID  *Buffer\r
   )\r
 {\r
-  CPU_MP_DATA         *DataInHob;\r
+  CPU_MP_DATA  *DataInHob;\r
 \r
-  DataInHob = (CPU_MP_DATA *) Buffer;\r
+  DataInHob = (CPU_MP_DATA *)Buffer;\r
   AsmExchangeRole (&DataInHob->APInfo, &DataInHob->BSPInfo);\r
 }\r
 \r
@@ -96,7 +95,7 @@ FutureBSPProc (
 **/\r
 CPU_STATE\r
 GetApState (\r
-  IN  CPU_AP_DATA     *CpuData\r
+  IN  CPU_AP_DATA  *CpuData\r
   )\r
 {\r
   return CpuData->State;\r
@@ -110,8 +109,8 @@ GetApState (
 **/\r
 VOID\r
 SetApState (\r
-  IN  CPU_AP_DATA     *CpuData,\r
-  IN  CPU_STATE       State\r
+  IN  CPU_AP_DATA  *CpuData,\r
+  IN  CPU_STATE    State\r
   )\r
 {\r
   AcquireSpinLock (&CpuData->ApLock);\r
@@ -126,7 +125,7 @@ SetApState (
 **/\r
 VOID\r
 SaveLocalApicTimerSetting (\r
-  IN CPU_MP_DATA   *CpuMpData\r
+  IN CPU_MP_DATA  *CpuMpData\r
   )\r
 {\r
   //\r
@@ -148,7 +147,7 @@ SaveLocalApicTimerSetting (
 **/\r
 VOID\r
 SyncLocalApicTimerSetting (\r
-  IN CPU_MP_DATA   *CpuMpData\r
+  IN CPU_MP_DATA  *CpuMpData\r
   )\r
 {\r
   //\r
@@ -173,10 +172,10 @@ SyncLocalApicTimerSetting (
 **/\r
 VOID\r
 SaveVolatileRegisters (\r
-  OUT CPU_VOLATILE_REGISTERS    *VolatileRegisters\r
+  OUT CPU_VOLATILE_REGISTERS  *VolatileRegisters\r
   )\r
 {\r
-  CPUID_VERSION_INFO_EDX        VersionInfoEdx;\r
+  CPUID_VERSION_INFO_EDX  VersionInfoEdx;\r
 \r
   VolatileRegisters->Cr0 = AsmReadCr0 ();\r
   VolatileRegisters->Cr3 = AsmReadCr3 ();\r
@@ -210,12 +209,12 @@ SaveVolatileRegisters (
 **/\r
 VOID\r
 RestoreVolatileRegisters (\r
-  IN CPU_VOLATILE_REGISTERS    *VolatileRegisters,\r
-  IN BOOLEAN                   IsRestoreDr\r
+  IN CPU_VOLATILE_REGISTERS  *VolatileRegisters,\r
+  IN BOOLEAN                 IsRestoreDr\r
   )\r
 {\r
-  CPUID_VERSION_INFO_EDX        VersionInfoEdx;\r
-  IA32_TSS_DESCRIPTOR           *Tss;\r
+  CPUID_VERSION_INFO_EDX  VersionInfoEdx;\r
+  IA32_TSS_DESCRIPTOR     *Tss;\r
 \r
   AsmWriteCr3 (VolatileRegisters->Cr3);\r
   AsmWriteCr4 (VolatileRegisters->Cr4);\r
@@ -239,8 +238,9 @@ RestoreVolatileRegisters (
 \r
   AsmWriteGdtr (&VolatileRegisters->Gdtr);\r
   AsmWriteIdtr (&VolatileRegisters->Idtr);\r
-  if (VolatileRegisters->Tr != 0 &&\r
-      VolatileRegisters->Tr < VolatileRegisters->Gdtr.Limit) {\r
+  if ((VolatileRegisters->Tr != 0) &&\r
+      (VolatileRegisters->Tr < VolatileRegisters->Gdtr.Limit))\r
+  {\r
     Tss = (IA32_TSS_DESCRIPTOR *)(VolatileRegisters->Gdtr.Base +\r
                                   VolatileRegisters->Tr);\r
     if (Tss->Bits.P == 1) {\r
@@ -261,7 +261,7 @@ IsMwaitSupport (
   VOID\r
   )\r
 {\r
-  CPUID_VERSION_INFO_ECX        VersionInfoEcx;\r
+  CPUID_VERSION_INFO_ECX  VersionInfoEcx;\r
 \r
   AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, &VersionInfoEcx.Uint32, NULL);\r
   return (VersionInfoEcx.Bits.MONITOR == 1) ? TRUE : FALSE;\r
@@ -276,11 +276,11 @@ IsMwaitSupport (
 **/\r
 UINT8\r
 GetApLoopMode (\r
-  OUT UINT32     *MonitorFilterSize\r
+  OUT UINT32  *MonitorFilterSize\r
   )\r
 {\r
-  UINT8                         ApLoopMode;\r
-  CPUID_MONITOR_MWAIT_EBX       MonitorMwaitEbx;\r
+  UINT8                    ApLoopMode;\r
+  CPUID_MONITOR_MWAIT_EBX  MonitorMwaitEbx;\r
 \r
   ASSERT (MonitorFilterSize != NULL);\r
 \r
@@ -328,20 +328,20 @@ GetApLoopMode (
 **/\r
 VOID\r
 SortApicId (\r
-  IN CPU_MP_DATA   *CpuMpData\r
+  IN CPU_MP_DATA  *CpuMpData\r
   )\r
 {\r
-  UINTN             Index1;\r
-  UINTN             Index2;\r
-  UINTN             Index3;\r
-  UINT32            ApicId;\r
-  CPU_INFO_IN_HOB   CpuInfo;\r
-  UINT32            ApCount;\r
-  CPU_INFO_IN_HOB   *CpuInfoInHob;\r
-  volatile UINT32   *StartupApSignal;\r
-\r
-  ApCount = CpuMpData->CpuCount - 1;\r
-  CpuInfoInHob = (CPU_INFO_IN_HOB *) (UINTN) CpuMpData->CpuInfoInHob;\r
+  UINTN            Index1;\r
+  UINTN            Index2;\r
+  UINTN            Index3;\r
+  UINT32           ApicId;\r
+  CPU_INFO_IN_HOB  CpuInfo;\r
+  UINT32           ApCount;\r
+  CPU_INFO_IN_HOB  *CpuInfoInHob;\r
+  volatile UINT32  *StartupApSignal;\r
+\r
+  ApCount      = CpuMpData->CpuCount - 1;\r
+  CpuInfoInHob = (CPU_INFO_IN_HOB *)(UINTN)CpuMpData->CpuInfoInHob;\r
   if (ApCount != 0) {\r
     for (Index1 = 0; Index1 < ApCount; Index1++) {\r
       Index3 = Index1;\r
@@ -355,6 +355,7 @@ SortApicId (
           ApicId = CpuInfoInHob[Index2].ApicId;\r
         }\r
       }\r
+\r
       if (Index3 != Index1) {\r
         CopyMem (&CpuInfo, &CpuInfoInHob[Index3], sizeof (CPU_INFO_IN_HOB));\r
         CopyMem (\r
@@ -367,7 +368,7 @@ SortApicId (
         //\r
         // Also exchange the StartupApSignal.\r
         //\r
-        StartupApSignal = CpuMpData->CpuData[Index3].StartupApSignal;\r
+        StartupApSignal                            = CpuMpData->CpuData[Index3].StartupApSignal;\r
         CpuMpData->CpuData[Index3].StartupApSignal =\r
           CpuMpData->CpuData[Index1].StartupApSignal;\r
         CpuMpData->CpuData[Index1].StartupApSignal = StartupApSignal;\r
@@ -380,7 +381,7 @@ SortApicId (
     ApicId = GetInitialApicId ();\r
     for (Index1 = 0; Index1 < CpuMpData->CpuCount; Index1++) {\r
       if (CpuInfoInHob[Index1].ApicId == ApicId) {\r
-        CpuMpData->BspNumber = (UINT32) Index1;\r
+        CpuMpData->BspNumber = (UINT32)Index1;\r
         break;\r
       }\r
     }\r
@@ -416,8 +417,8 @@ ApInitializeSync (
   UINTN        ProcessorNumber;\r
   EFI_STATUS   Status;\r
 \r
-  CpuMpData = (CPU_MP_DATA *) Buffer;\r
-  Status = GetProcessorNumber (CpuMpData, &ProcessorNumber);\r
+  CpuMpData = (CPU_MP_DATA *)Buffer;\r
+  Status    = GetProcessorNumber (CpuMpData, &ProcessorNumber);\r
   ASSERT_EFI_ERROR (Status);\r
   //\r
   // Load microcode on AP\r
@@ -440,20 +441,20 @@ ApInitializeSync (
 **/\r
 EFI_STATUS\r
 GetProcessorNumber (\r
-  IN CPU_MP_DATA               *CpuMpData,\r
-  OUT UINTN                    *ProcessorNumber\r
+  IN CPU_MP_DATA  *CpuMpData,\r
+  OUT UINTN       *ProcessorNumber\r
   )\r
 {\r
-  UINTN                   TotalProcessorNumber;\r
-  UINTN                   Index;\r
-  CPU_INFO_IN_HOB         *CpuInfoInHob;\r
-  UINT32                  CurrentApicId;\r
+  UINTN            TotalProcessorNumber;\r
+  UINTN            Index;\r
+  CPU_INFO_IN_HOB  *CpuInfoInHob;\r
+  UINT32           CurrentApicId;\r
 \r
-  CpuInfoInHob = (CPU_INFO_IN_HOB *) (UINTN) CpuMpData->CpuInfoInHob;\r
+  CpuInfoInHob = (CPU_INFO_IN_HOB *)(UINTN)CpuMpData->CpuInfoInHob;\r
 \r
   TotalProcessorNumber = CpuMpData->CpuCount;\r
-  CurrentApicId = GetApicId ();\r
-  for (Index = 0; Index < TotalProcessorNumber; Index ++) {\r
+  CurrentApicId        = GetApicId ();\r
+  for (Index = 0; Index < TotalProcessorNumber; Index++) {\r
     if (CpuInfoInHob[Index].ApicId == CurrentApicId) {\r
       *ProcessorNumber = Index;\r
       return EFI_SUCCESS;\r
@@ -472,12 +473,12 @@ GetProcessorNumber (
 **/\r
 UINTN\r
 CollectProcessorCount (\r
-  IN CPU_MP_DATA         *CpuMpData\r
+  IN CPU_MP_DATA  *CpuMpData\r
   )\r
 {\r
-  UINTN                  Index;\r
-  CPU_INFO_IN_HOB        *CpuInfoInHob;\r
-  BOOLEAN                X2Apic;\r
+  UINTN            Index;\r
+  CPU_INFO_IN_HOB  *CpuInfoInHob;\r
+  BOOLEAN          X2Apic;\r
 \r
   //\r
   // Send 1st broadcast IPI to APs to wakeup APs\r
@@ -504,7 +505,7 @@ CollectProcessorCount (
     //\r
     X2Apic = TRUE;\r
   } else {\r
-    CpuInfoInHob = (CPU_INFO_IN_HOB *) (UINTN) CpuMpData->CpuInfoInHob;\r
+    CpuInfoInHob = (CPU_INFO_IN_HOB *)(UINTN)CpuMpData->CpuInfoInHob;\r
     for (Index = 0; Index < CpuMpData->CpuCount; Index++) {\r
       if (CpuInfoInHob[Index].InitialApicId >= 0xFF) {\r
         X2Apic = TRUE;\r
@@ -525,6 +526,7 @@ CollectProcessorCount (
     while (CpuMpData->FinishedCount < (CpuMpData->CpuCount - 1)) {\r
       CpuPause ();\r
     }\r
+\r
     //\r
     // Enable x2APIC on BSP\r
     //\r
@@ -536,6 +538,7 @@ CollectProcessorCount (
       SetApState (&CpuMpData->CpuData[Index], CpuStateIdle);\r
     }\r
   }\r
+\r
   DEBUG ((DEBUG_INFO, "APIC MODE is %d\n", GetApicMode ()));\r
   //\r
   // Sort BSP/Aps by CPU APIC ID in ascending order\r
@@ -558,16 +561,16 @@ CollectProcessorCount (
 **/\r
 VOID\r
 InitializeApData (\r
-  IN OUT CPU_MP_DATA      *CpuMpData,\r
-  IN     UINTN            ProcessorNumber,\r
-  IN     UINT32           BistData,\r
-  IN     UINT64           ApTopOfStack\r
+  IN OUT CPU_MP_DATA  *CpuMpData,\r
+  IN     UINTN        ProcessorNumber,\r
+  IN     UINT32       BistData,\r
+  IN     UINT64       ApTopOfStack\r
   )\r
 {\r
-  CPU_INFO_IN_HOB                  *CpuInfoInHob;\r
-  MSR_IA32_PLATFORM_ID_REGISTER    PlatformIdMsr;\r
+  CPU_INFO_IN_HOB                *CpuInfoInHob;\r
+  MSR_IA32_PLATFORM_ID_REGISTER  PlatformIdMsr;\r
 \r
-  CpuInfoInHob = (CPU_INFO_IN_HOB *) (UINTN) CpuMpData->CpuInfoInHob;\r
+  CpuInfoInHob                                = (CPU_INFO_IN_HOB *)(UINTN)CpuMpData->CpuInfoInHob;\r
   CpuInfoInHob[ProcessorNumber].InitialApicId = GetInitialApicId ();\r
   CpuInfoInHob[ProcessorNumber].ApicId        = GetApicId ();\r
   CpuInfoInHob[ProcessorNumber].Health        = BistData;\r
@@ -580,7 +583,7 @@ InitializeApData (
   // NOTE: PlatformId is not relevant on AMD platforms.\r
   //\r
   if (!StandardSignatureIsAuthenticAMD ()) {\r
-    PlatformIdMsr.Uint64 = AsmReadMsr64 (MSR_IA32_PLATFORM_ID);\r
+    PlatformIdMsr.Uint64                           = AsmReadMsr64 (MSR_IA32_PLATFORM_ID);\r
     CpuMpData->CpuData[ProcessorNumber].PlatformId = (UINT8)PlatformIdMsr.Bits.PlatformId;\r
   }\r
 \r
@@ -592,7 +595,7 @@ InitializeApData (
     NULL\r
     );\r
 \r
-  InitializeSpinLock(&CpuMpData->CpuData[ProcessorNumber].ApLock);\r
+  InitializeSpinLock (&CpuMpData->CpuData[ProcessorNumber].ApLock);\r
   SetApState (&CpuMpData->CpuData[ProcessorNumber], CpuStateIdle);\r
 }\r
 \r
@@ -613,18 +616,21 @@ GetProtectedMode16CS (
   UINTN                    GdtEntryCount;\r
   UINT16                   Index;\r
 \r
-  Index = (UINT16) -1;\r
+  Index = (UINT16)-1;\r
   AsmReadGdtr (&GdtrDesc);\r
   GdtEntryCount = (GdtrDesc.Limit + 1) / sizeof (IA32_SEGMENT_DESCRIPTOR);\r
-  GdtEntry = (IA32_SEGMENT_DESCRIPTOR *) GdtrDesc.Base;\r
+  GdtEntry      = (IA32_SEGMENT_DESCRIPTOR *)GdtrDesc.Base;\r
   for (Index = 0; Index < GdtEntryCount; Index++) {\r
-    if (GdtEntry->Bits.L == 0 &&\r
-        GdtEntry->Bits.DB == 0 &&\r
-        GdtEntry->Bits.Type > 8) {\r
+    if ((GdtEntry->Bits.L == 0) &&\r
+        (GdtEntry->Bits.DB == 0) &&\r
+        (GdtEntry->Bits.Type > 8))\r
+    {\r
       break;\r
     }\r
+\r
     GdtEntry++;\r
   }\r
+\r
   ASSERT (Index != GdtEntryCount);\r
   return Index * 8;\r
 }\r
@@ -646,18 +652,21 @@ GetProtectedMode32CS (
   UINTN                    GdtEntryCount;\r
   UINT16                   Index;\r
 \r
-  Index = (UINT16) -1;\r
+  Index = (UINT16)-1;\r
   AsmReadGdtr (&GdtrDesc);\r
   GdtEntryCount = (GdtrDesc.Limit + 1) / sizeof (IA32_SEGMENT_DESCRIPTOR);\r
-  GdtEntry = (IA32_SEGMENT_DESCRIPTOR *) GdtrDesc.Base;\r
+  GdtEntry      = (IA32_SEGMENT_DESCRIPTOR *)GdtrDesc.Base;\r
   for (Index = 0; Index < GdtEntryCount; Index++) {\r
-    if (GdtEntry->Bits.L == 0 &&\r
-        GdtEntry->Bits.DB == 1 &&\r
-        GdtEntry->Bits.Type > 8) {\r
+    if ((GdtEntry->Bits.L == 0) &&\r
+        (GdtEntry->Bits.DB == 1) &&\r
+        (GdtEntry->Bits.Type > 8))\r
+    {\r
       break;\r
     }\r
+\r
     GdtEntry++;\r
   }\r
+\r
   ASSERT (Index != GdtEntryCount);\r
   return Index * 8;\r
 }\r
@@ -674,16 +683,16 @@ GetProtectedMode32CS (
 STATIC\r
 VOID\r
 MpInitLibSevEsAPReset (\r
-  IN GHCB                         *Ghcb,\r
-  IN CPU_MP_DATA                  *CpuMpData\r
+  IN GHCB         *Ghcb,\r
+  IN CPU_MP_DATA  *CpuMpData\r
   )\r
 {\r
-  EFI_STATUS       Status;\r
-  UINTN            ProcessorNumber;\r
-  UINT16           Code16, Code32;\r
-  AP_RESET         *APResetFn;\r
-  UINTN            BufferStart;\r
-  UINTN            StackStart;\r
+  EFI_STATUS  Status;\r
+  UINTN       ProcessorNumber;\r
+  UINT16      Code16, Code32;\r
+  AP_RESET    *APResetFn;\r
+  UINTN       BufferStart;\r
+  UINTN       StackStart;\r
 \r
   Status = GetProcessorNumber (CpuMpData, &ProcessorNumber);\r
   ASSERT_EFI_ERROR (Status);\r
@@ -692,14 +701,14 @@ MpInitLibSevEsAPReset (
   Code32 = GetProtectedMode32CS ();\r
 \r
   if (CpuMpData->WakeupBufferHigh != 0) {\r
-    APResetFn = (AP_RESET *) (CpuMpData->WakeupBufferHigh + CpuMpData->AddressMap.SwitchToRealNoNxOffset);\r
+    APResetFn = (AP_RESET *)(CpuMpData->WakeupBufferHigh + CpuMpData->AddressMap.SwitchToRealNoNxOffset);\r
   } else {\r
-    APResetFn = (AP_RESET *) (CpuMpData->MpCpuExchangeInfo->BufferStart + CpuMpData->AddressMap.SwitchToRealOffset);\r
+    APResetFn = (AP_RESET *)(CpuMpData->MpCpuExchangeInfo->BufferStart + CpuMpData->AddressMap.SwitchToRealOffset);\r
   }\r
 \r
   BufferStart = CpuMpData->MpCpuExchangeInfo->BufferStart;\r
-  StackStart = CpuMpData->SevEsAPResetStackStart -\r
-                 (AP_RESET_STACK_SIZE * ProcessorNumber);\r
+  StackStart  = CpuMpData->SevEsAPResetStackStart -\r
+                (AP_RESET_STACK_SIZE * ProcessorNumber);\r
 \r
   //\r
   // This call never returns.\r
@@ -716,19 +725,19 @@ MpInitLibSevEsAPReset (
 VOID\r
 EFIAPI\r
 ApWakeupFunction (\r
-  IN MP_CPU_EXCHANGE_INFO      *ExchangeInfo,\r
-  IN UINTN                     ApIndex\r
+  IN MP_CPU_EXCHANGE_INFO  *ExchangeInfo,\r
+  IN UINTN                 ApIndex\r
   )\r
 {\r
-  CPU_MP_DATA                *CpuMpData;\r
-  UINTN                      ProcessorNumber;\r
-  EFI_AP_PROCEDURE           Procedure;\r
-  VOID                       *Parameter;\r
-  UINT32                     BistData;\r
-  volatile UINT32            *ApStartupSignalBuffer;\r
-  CPU_INFO_IN_HOB            *CpuInfoInHob;\r
-  UINT64                     ApTopOfStack;\r
-  UINTN                      CurrentApicMode;\r
+  CPU_MP_DATA       *CpuMpData;\r
+  UINTN             ProcessorNumber;\r
+  EFI_AP_PROCEDURE  Procedure;\r
+  VOID              *Parameter;\r
+  UINT32            BistData;\r
+  volatile UINT32   *ApStartupSignalBuffer;\r
+  CPU_INFO_IN_HOB   *CpuInfoInHob;\r
+  UINT64            ApTopOfStack;\r
+  UINTN             CurrentApicMode;\r
 \r
   //\r
   // AP finished assembly code and begin to execute C code\r
@@ -753,8 +762,8 @@ ApWakeupFunction (
       //\r
       // This is first time AP wakeup, get BIST information from AP stack\r
       //\r
-      ApTopOfStack  = CpuMpData->Buffer + (ProcessorNumber + 1) * CpuMpData->CpuApStackSize;\r
-      BistData = *(UINT32 *) ((UINTN) ApTopOfStack - sizeof (UINTN));\r
+      ApTopOfStack = CpuMpData->Buffer + (ProcessorNumber + 1) * CpuMpData->CpuApStackSize;\r
+      BistData     = *(UINT32 *)((UINTN)ApTopOfStack - sizeof (UINTN));\r
       //\r
       // CpuMpData->CpuData[0].VolatileRegisters is initialized based on BSP environment,\r
       //   to initialize AP in InitConfig path.\r
@@ -773,7 +782,7 @@ ApWakeupFunction (
       //\r
       ApStartupSignalBuffer = CpuMpData->CpuData[ProcessorNumber].StartupApSignal;\r
       InterlockedCompareExchange32 (\r
-        (UINT32 *) ApStartupSignalBuffer,\r
+        (UINT32 *)ApStartupSignalBuffer,\r
         WAKEUP_AP_SIGNAL,\r
         0\r
         );\r
@@ -788,7 +797,7 @@ ApWakeupFunction (
         //   different IDT shared by all APs.\r
         //\r
         RestoreVolatileRegisters (&CpuMpData->CpuData[0].VolatileRegisters, FALSE);\r
-      }  else {\r
+      } else {\r
         if (CpuMpData->ApLoopMode == ApInHltLoop) {\r
           //\r
           // Restore AP's volatile registers saved before AP is halted\r
@@ -806,7 +815,7 @@ ApWakeupFunction (
 \r
       if (GetApState (&CpuMpData->CpuData[ProcessorNumber]) == CpuStateReady) {\r
         Procedure = (EFI_AP_PROCEDURE)CpuMpData->CpuData[ProcessorNumber].ApFunction;\r
-        Parameter = (VOID *) CpuMpData->CpuData[ProcessorNumber].ApFunctionArgument;\r
+        Parameter = (VOID *)CpuMpData->CpuData[ProcessorNumber].ApFunctionArgument;\r
         if (Procedure != NULL) {\r
           SetApState (&CpuMpData->CpuData[ProcessorNumber], CpuStateBusy);\r
           //\r
@@ -817,19 +826,20 @@ ApWakeupFunction (
           // Invoke AP function here\r
           //\r
           Procedure (Parameter);\r
-          CpuInfoInHob = (CPU_INFO_IN_HOB *) (UINTN) CpuMpData->CpuInfoInHob;\r
+          CpuInfoInHob = (CPU_INFO_IN_HOB *)(UINTN)CpuMpData->CpuInfoInHob;\r
           if (CpuMpData->SwitchBspFlag) {\r
             //\r
             // Re-get the processor number due to BSP/AP maybe exchange in AP function\r
             //\r
             GetProcessorNumber (CpuMpData, &ProcessorNumber);\r
-            CpuMpData->CpuData[ProcessorNumber].ApFunction = 0;\r
+            CpuMpData->CpuData[ProcessorNumber].ApFunction         = 0;\r
             CpuMpData->CpuData[ProcessorNumber].ApFunctionArgument = 0;\r
-            ApStartupSignalBuffer = CpuMpData->CpuData[ProcessorNumber].StartupApSignal;\r
-            CpuInfoInHob[ProcessorNumber].ApTopOfStack = CpuInfoInHob[CpuMpData->NewBspNumber].ApTopOfStack;\r
+            ApStartupSignalBuffer                                  = CpuMpData->CpuData[ProcessorNumber].StartupApSignal;\r
+            CpuInfoInHob[ProcessorNumber].ApTopOfStack             = CpuInfoInHob[CpuMpData->NewBspNumber].ApTopOfStack;\r
           } else {\r
-            if (CpuInfoInHob[ProcessorNumber].ApicId != GetApicId () ||\r
-                CpuInfoInHob[ProcessorNumber].InitialApicId != GetInitialApicId ()) {\r
+            if ((CpuInfoInHob[ProcessorNumber].ApicId != GetApicId ()) ||\r
+                (CpuInfoInHob[ProcessorNumber].InitialApicId != GetInitialApicId ()))\r
+            {\r
               if (CurrentApicMode != GetApicMode ()) {\r
                 //\r
                 // If APIC mode change happened during AP function execution,\r
@@ -847,6 +857,7 @@ ApWakeupFunction (
             }\r
           }\r
         }\r
+\r
         SetApState (&CpuMpData->CpuData[ProcessorNumber], CpuStateFinished);\r
       }\r
     }\r
@@ -861,7 +872,7 @@ ApWakeupFunction (
     //\r
     // AP finished executing C code\r
     //\r
-    InterlockedIncrement ((UINT32 *) &CpuMpData->FinishedCount);\r
+    InterlockedIncrement ((UINT32 *)&CpuMpData->FinishedCount);\r
 \r
     if (CpuMpData->InitFlag == ApInitConfig) {\r
       //\r
@@ -870,7 +881,7 @@ ApWakeupFunction (
       // performs another INIT-SIPI-SIPI sequence.\r
       //\r
       if (!CpuMpData->SevEsIsEnabled) {\r
-        InterlockedDecrement ((UINT32 *) &CpuMpData->MpCpuExchangeInfo->NumApsExecuting);\r
+        InterlockedDecrement ((UINT32 *)&CpuMpData->MpCpuExchangeInfo->NumApsExecuting);\r
       }\r
     }\r
 \r
@@ -890,11 +901,11 @@ ApWakeupFunction (
           BOOLEAN                   DoDecrement;\r
           BOOLEAN                   InterruptState;\r
 \r
-          DoDecrement = (BOOLEAN) (CpuMpData->InitFlag == ApInitConfig);\r
+          DoDecrement = (BOOLEAN)(CpuMpData->InitFlag == ApInitConfig);\r
 \r
           while (TRUE) {\r
             Msr.GhcbPhysicalAddress = AsmReadMsr64 (MSR_SEV_ES_GHCB);\r
-            Ghcb = Msr.Ghcb;\r
+            Ghcb                    = Msr.Ghcb;\r
 \r
             VmgInit (Ghcb, &InterruptState);\r
 \r
@@ -905,7 +916,7 @@ ApWakeupFunction (
               // Perform the delayed decrement just before issuing the first\r
               // VMGEXIT with AP_RESET_HOLD.\r
               //\r
-              InterlockedDecrement ((UINT32 *) &CpuMpData->MpCpuExchangeInfo->NumApsExecuting);\r
+              InterlockedDecrement ((UINT32 *)&CpuMpData->MpCpuExchangeInfo->NumApsExecuting);\r
             }\r
 \r
             Status = VmgExit (Ghcb, SVM_EXIT_AP_RESET_HOLD, 0, 0);\r
@@ -928,16 +939,18 @@ ApWakeupFunction (
         } else {\r
           CpuSleep ();\r
         }\r
+\r
         CpuPause ();\r
       }\r
     }\r
+\r
     while (TRUE) {\r
       DisableInterrupts ();\r
       if (CpuMpData->ApLoopMode == ApInMwaitLoop) {\r
         //\r
         // Place AP in MWAIT-loop\r
         //\r
-        AsmMonitor ((UINTN) ApStartupSignalBuffer, 0, 0);\r
+        AsmMonitor ((UINTN)ApStartupSignalBuffer, 0, 0);\r
         if (*ApStartupSignalBuffer != WAKEUP_AP_SIGNAL) {\r
           //\r
           // Check AP start-up signal again.\r
@@ -973,7 +986,7 @@ ApWakeupFunction (
 **/\r
 VOID\r
 WaitApWakeup (\r
-  IN volatile UINT32        *ApStartupSignalBuffer\r
+  IN volatile UINT32  *ApStartupSignalBuffer\r
   )\r
 {\r
   //\r
@@ -981,10 +994,11 @@ WaitApWakeup (
   // Otherwise, write StartupApSignal again till AP waken up.\r
   //\r
   while (InterlockedCompareExchange32 (\r
-          (UINT32 *) ApStartupSignalBuffer,\r
-          WAKEUP_AP_SIGNAL,\r
-          WAKEUP_AP_SIGNAL\r
-          ) != 0) {\r
+           (UINT32 *)ApStartupSignalBuffer,\r
+           WAKEUP_AP_SIGNAL,\r
+           WAKEUP_AP_SIGNAL\r
+           ) != 0)\r
+  {\r
     CpuPause ();\r
   }\r
 }\r
@@ -997,30 +1011,30 @@ WaitApWakeup (
 **/\r
 VOID\r
 FillExchangeInfoData (\r
-  IN CPU_MP_DATA               *CpuMpData\r
+  IN CPU_MP_DATA  *CpuMpData\r
   )\r
 {\r
-  volatile MP_CPU_EXCHANGE_INFO    *ExchangeInfo;\r
-  UINTN                            Size;\r
-  IA32_SEGMENT_DESCRIPTOR          *Selector;\r
-  IA32_CR4                         Cr4;\r
+  volatile MP_CPU_EXCHANGE_INFO  *ExchangeInfo;\r
+  UINTN                          Size;\r
+  IA32_SEGMENT_DESCRIPTOR        *Selector;\r
+  IA32_CR4                       Cr4;\r
 \r
-  ExchangeInfo                  = CpuMpData->MpCpuExchangeInfo;\r
-  ExchangeInfo->StackStart      = CpuMpData->Buffer;\r
-  ExchangeInfo->StackSize       = CpuMpData->CpuApStackSize;\r
-  ExchangeInfo->BufferStart     = CpuMpData->WakeupBuffer;\r
-  ExchangeInfo->ModeOffset      = CpuMpData->AddressMap.ModeEntryOffset;\r
+  ExchangeInfo              = CpuMpData->MpCpuExchangeInfo;\r
+  ExchangeInfo->StackStart  = CpuMpData->Buffer;\r
+  ExchangeInfo->StackSize   = CpuMpData->CpuApStackSize;\r
+  ExchangeInfo->BufferStart = CpuMpData->WakeupBuffer;\r
+  ExchangeInfo->ModeOffset  = CpuMpData->AddressMap.ModeEntryOffset;\r
 \r
-  ExchangeInfo->CodeSegment     = AsmReadCs ();\r
-  ExchangeInfo->DataSegment     = AsmReadDs ();\r
+  ExchangeInfo->CodeSegment = AsmReadCs ();\r
+  ExchangeInfo->DataSegment = AsmReadDs ();\r
 \r
-  ExchangeInfo->Cr3             = AsmReadCr3 ();\r
+  ExchangeInfo->Cr3 = AsmReadCr3 ();\r
 \r
-  ExchangeInfo->CFunction       = (UINTN) ApWakeupFunction;\r
+  ExchangeInfo->CFunction       = (UINTN)ApWakeupFunction;\r
   ExchangeInfo->ApIndex         = 0;\r
   ExchangeInfo->NumApsExecuting = 0;\r
-  ExchangeInfo->InitFlag        = (UINTN) CpuMpData->InitFlag;\r
-  ExchangeInfo->CpuInfo         = (CPU_INFO_IN_HOB *) (UINTN) CpuMpData->CpuInfoInHob;\r
+  ExchangeInfo->InitFlag        = (UINTN)CpuMpData->InitFlag;\r
+  ExchangeInfo->CpuInfo         = (CPU_INFO_IN_HOB *)(UINTN)CpuMpData->CpuInfoInHob;\r
   ExchangeInfo->CpuMpData       = CpuMpData;\r
 \r
   ExchangeInfo->EnableExecuteDisable = IsBspExecuteDisableEnabled ();\r
@@ -1035,32 +1049,33 @@ FillExchangeInfoData (
   // Using latter way is simpler because it also eliminates the needs to\r
   //  check whether platform wants to enable it.\r
   //\r
-  Cr4.UintN = AsmReadCr4 ();\r
-  ExchangeInfo->Enable5LevelPaging = (BOOLEAN) (Cr4.Bits.LA57 == 1);\r
+  Cr4.UintN                        = AsmReadCr4 ();\r
+  ExchangeInfo->Enable5LevelPaging = (BOOLEAN)(Cr4.Bits.LA57 == 1);\r
   DEBUG ((DEBUG_INFO, "%a: 5-Level Paging = %d\n", gEfiCallerBaseName, ExchangeInfo->Enable5LevelPaging));\r
 \r
-  ExchangeInfo->SevEsIsEnabled  = CpuMpData->SevEsIsEnabled;\r
-  ExchangeInfo->GhcbBase        = (UINTN) CpuMpData->GhcbBase;\r
+  ExchangeInfo->SevEsIsEnabled = CpuMpData->SevEsIsEnabled;\r
+  ExchangeInfo->GhcbBase       = (UINTN)CpuMpData->GhcbBase;\r
 \r
   //\r
   // Get the BSP's data of GDT and IDT\r
   //\r
-  AsmReadGdtr ((IA32_DESCRIPTOR *) &ExchangeInfo->GdtrProfile);\r
-  AsmReadIdtr ((IA32_DESCRIPTOR *) &ExchangeInfo->IdtrProfile);\r
+  AsmReadGdtr ((IA32_DESCRIPTOR *)&ExchangeInfo->GdtrProfile);\r
+  AsmReadIdtr ((IA32_DESCRIPTOR *)&ExchangeInfo->IdtrProfile);\r
 \r
   //\r
   // Find a 32-bit code segment\r
   //\r
   Selector = (IA32_SEGMENT_DESCRIPTOR *)ExchangeInfo->GdtrProfile.Base;\r
-  Size = ExchangeInfo->GdtrProfile.Limit + 1;\r
+  Size     = ExchangeInfo->GdtrProfile.Limit + 1;\r
   while (Size > 0) {\r
-    if (Selector->Bits.L == 0 && Selector->Bits.Type >= 8) {\r
+    if ((Selector->Bits.L == 0) && (Selector->Bits.Type >= 8)) {\r
       ExchangeInfo->ModeTransitionSegment =\r
         (UINT16)((UINTN)Selector - ExchangeInfo->GdtrProfile.Base);\r
       break;\r
     }\r
+\r
     Selector += 1;\r
-    Size -= sizeof (IA32_SEGMENT_DESCRIPTOR);\r
+    Size     -= sizeof (IA32_SEGMENT_DESCRIPTOR);\r
   }\r
 \r
   //\r
@@ -1069,8 +1084,8 @@ FillExchangeInfoData (
   //\r
   if (CpuMpData->WakeupBufferHigh != 0) {\r
     Size = CpuMpData->AddressMap.RendezvousFunnelSize +\r
-             CpuMpData->AddressMap.SwitchToRealSize -\r
-             CpuMpData->AddressMap.ModeTransitionOffset;\r
+           CpuMpData->AddressMap.SwitchToRealSize -\r
+           CpuMpData->AddressMap.ModeTransitionOffset;\r
     CopyMem (\r
       (VOID *)CpuMpData->WakeupBufferHigh,\r
       CpuMpData->AddressMap.RendezvousFunnelAddress +\r
@@ -1081,12 +1096,12 @@ FillExchangeInfoData (
     ExchangeInfo->ModeTransitionMemory = (UINT32)CpuMpData->WakeupBufferHigh;\r
   } else {\r
     ExchangeInfo->ModeTransitionMemory = (UINT32)\r
-      (ExchangeInfo->BufferStart + CpuMpData->AddressMap.ModeTransitionOffset);\r
+                                         (ExchangeInfo->BufferStart + CpuMpData->AddressMap.ModeTransitionOffset);\r
   }\r
 \r
   ExchangeInfo->ModeHighMemory = ExchangeInfo->ModeTransitionMemory +\r
-                         (UINT32)ExchangeInfo->ModeOffset -\r
-                         (UINT32)CpuMpData->AddressMap.ModeTransitionOffset;\r
+                                 (UINT32)ExchangeInfo->ModeOffset -\r
+                                 (UINT32)CpuMpData->AddressMap.ModeTransitionOffset;\r
   ExchangeInfo->ModeHighSegment = (UINT16)ExchangeInfo->CodeSegment;\r
 }\r
 \r
@@ -1100,9 +1115,9 @@ FillExchangeInfoData (
 **/\r
 VOID\r
 TimedWaitForApFinish (\r
-  IN CPU_MP_DATA               *CpuMpData,\r
-  IN UINT32                    FinishedApLimit,\r
-  IN UINT32                    TimeLimit\r
+  IN CPU_MP_DATA  *CpuMpData,\r
+  IN UINT32       FinishedApLimit,\r
+  IN UINT32       TimeLimit\r
   );\r
 \r
 /**\r
@@ -1111,20 +1126,20 @@ TimedWaitForApFinish (
   @param[in]  CpuMpData  The pointer to CPU MP Data structure.\r
 **/\r
 VOID\r
-BackupAndPrepareWakeupBuffer(\r
-  IN CPU_MP_DATA              *CpuMpData\r
+BackupAndPrepareWakeupBuffer (\r
+  IN CPU_MP_DATA  *CpuMpData\r
   )\r
 {\r
   CopyMem (\r
-    (VOID *) CpuMpData->BackupBuffer,\r
-    (VOID *) CpuMpData->WakeupBuffer,\r
+    (VOID *)CpuMpData->BackupBuffer,\r
+    (VOID *)CpuMpData->WakeupBuffer,\r
     CpuMpData->BackupBufferSize\r
     );\r
   CopyMem (\r
-    (VOID *) CpuMpData->WakeupBuffer,\r
-    (VOID *) CpuMpData->AddressMap.RendezvousFunnelAddress,\r
+    (VOID *)CpuMpData->WakeupBuffer,\r
+    (VOID *)CpuMpData->AddressMap.RendezvousFunnelAddress,\r
     CpuMpData->AddressMap.RendezvousFunnelSize +\r
-      CpuMpData->AddressMap.SwitchToRealSize\r
+    CpuMpData->AddressMap.SwitchToRealSize\r
     );\r
 }\r
 \r
@@ -1134,13 +1149,13 @@ BackupAndPrepareWakeupBuffer(
   @param[in]  CpuMpData  The pointer to CPU MP Data structure.\r
 **/\r
 VOID\r
-RestoreWakeupBuffer(\r
-  IN CPU_MP_DATA              *CpuMpData\r
+RestoreWakeupBuffer (\r
+  IN CPU_MP_DATA  *CpuMpData\r
   )\r
 {\r
   CopyMem (\r
-    (VOID *) CpuMpData->WakeupBuffer,\r
-    (VOID *) CpuMpData->BackupBuffer,\r
+    (VOID *)CpuMpData->WakeupBuffer,\r
+    (VOID *)CpuMpData->BackupBuffer,\r
     CpuMpData->BackupBufferSize\r
     );\r
 }\r
@@ -1161,8 +1176,8 @@ GetApResetVectorSize (
   UINTN  Size;\r
 \r
   Size = AddressMap->RendezvousFunnelSize +\r
-           AddressMap->SwitchToRealSize +\r
-           sizeof (MP_CPU_EXCHANGE_INFO);\r
+         AddressMap->SwitchToRealSize +\r
+         sizeof (MP_CPU_EXCHANGE_INFO);\r
 \r
   return Size;\r
 }\r
@@ -1174,21 +1189,21 @@ GetApResetVectorSize (
 **/\r
 VOID\r
 AllocateResetVector (\r
-  IN OUT CPU_MP_DATA          *CpuMpData\r
+  IN OUT CPU_MP_DATA  *CpuMpData\r
   )\r
 {\r
-  UINTN           ApResetVectorSize;\r
-  UINTN           ApResetStackSize;\r
+  UINTN  ApResetVectorSize;\r
+  UINTN  ApResetStackSize;\r
 \r
-  if (CpuMpData->WakeupBuffer == (UINTN) -1) {\r
+  if (CpuMpData->WakeupBuffer == (UINTN)-1) {\r
     ApResetVectorSize = GetApResetVectorSize (&CpuMpData->AddressMap);\r
 \r
     CpuMpData->WakeupBuffer      = GetWakeupBuffer (ApResetVectorSize);\r
-    CpuMpData->MpCpuExchangeInfo = (MP_CPU_EXCHANGE_INFO *) (UINTN)\r
-                    (CpuMpData->WakeupBuffer +\r
-                       CpuMpData->AddressMap.RendezvousFunnelSize +\r
-                       CpuMpData->AddressMap.SwitchToRealSize);\r
-    CpuMpData->WakeupBufferHigh  = GetModeTransitionBuffer (\r
+    CpuMpData->MpCpuExchangeInfo = (MP_CPU_EXCHANGE_INFO *)(UINTN)\r
+                                   (CpuMpData->WakeupBuffer +\r
+                                    CpuMpData->AddressMap.RendezvousFunnelSize +\r
+                                    CpuMpData->AddressMap.SwitchToRealSize);\r
+    CpuMpData->WakeupBufferHigh = GetModeTransitionBuffer (\r
                                     CpuMpData->AddressMap.RendezvousFunnelSize +\r
                                     CpuMpData->AddressMap.SwitchToRealSize -\r
                                     CpuMpData->AddressMap.ModeTransitionOffset\r
@@ -1228,6 +1243,7 @@ AllocateResetVector (
       }\r
     }\r
   }\r
+\r
   BackupAndPrepareWakeupBuffer (CpuMpData);\r
 }\r
 \r
@@ -1238,7 +1254,7 @@ AllocateResetVector (
 **/\r
 VOID\r
 FreeResetVector (\r
-  IN CPU_MP_DATA              *CpuMpData\r
+  IN CPU_MP_DATA  *CpuMpData\r
   )\r
 {\r
   //\r
@@ -1259,10 +1275,10 @@ FreeResetVector (
 **/\r
 VOID\r
 AllocateSevEsAPMemory (\r
-  IN OUT CPU_MP_DATA          *CpuMpData\r
+  IN OUT CPU_MP_DATA  *CpuMpData\r
   )\r
 {\r
-  if (CpuMpData->SevEsAPBuffer == (UINTN) -1) {\r
+  if (CpuMpData->SevEsAPBuffer == (UINTN)-1) {\r
     CpuMpData->SevEsAPBuffer =\r
       CpuMpData->SevEsIsEnabled ? GetSevEsAPMemory () : 0;\r
   }\r
@@ -1278,11 +1294,11 @@ SetSevEsJumpTable (
   IN UINTN  SipiVector\r
   )\r
 {\r
-  SEV_ES_AP_JMP_FAR *JmpFar;\r
-  UINT32            Offset, InsnByte;\r
-  UINT8             LoNib, HiNib;\r
+  SEV_ES_AP_JMP_FAR  *JmpFar;\r
+  UINT32             Offset, InsnByte;\r
+  UINT8              LoNib, HiNib;\r
 \r
-  JmpFar = (SEV_ES_AP_JMP_FAR *) (UINTN) FixedPcdGet32 (PcdSevEsWorkAreaBase);\r
+  JmpFar = (SEV_ES_AP_JMP_FAR *)(UINTN)FixedPcdGet32 (PcdSevEsWorkAreaBase);\r
   ASSERT (JmpFar != NULL);\r
 \r
   //\r
@@ -1290,10 +1306,10 @@ SetSevEsJumpTable (
   // This will be set to a value derived from the SIPI vector and will\r
   // be the memory address used for the far jump below.\r
   //\r
-  Offset = FixedPcdGet32 (PcdSevEsWorkAreaBase);\r
+  Offset  = FixedPcdGet32 (PcdSevEsWorkAreaBase);\r
   Offset += sizeof (JmpFar->InsnBuffer);\r
-  LoNib = (UINT8) Offset;\r
-  HiNib = (UINT8) (Offset >> 8);\r
+  LoNib   = (UINT8)Offset;\r
+  HiNib   = (UINT8)(Offset >> 8);\r
 \r
   //\r
   // Program the workarea (which is the initial AP boot address) with\r
@@ -1302,7 +1318,7 @@ SetSevEsJumpTable (
   //\r
   //   JMP FAR [CS:XXYY] => 2E FF 2E YY XX\r
   //\r
-  InsnByte = 0;\r
+  InsnByte                       = 0;\r
   JmpFar->InsnBuffer[InsnByte++] = 0x2E;  // CS override prefix\r
   JmpFar->InsnBuffer[InsnByte++] = 0xFF;  // JMP (FAR)\r
   JmpFar->InsnBuffer[InsnByte++] = 0x2E;  // ModRM (JMP memory location)\r
@@ -1313,8 +1329,8 @@ SetSevEsJumpTable (
   // Program the Segment/Rip based on the SIPI vector (always at least\r
   // 16-byte aligned, so Rip is set to 0).\r
   //\r
-  JmpFar->Rip = 0;\r
-  JmpFar->Segment = (UINT16) (SipiVector >> 4);\r
+  JmpFar->Rip     = 0;\r
+  JmpFar->Segment = (UINT16)(SipiVector >> 4);\r
 }\r
 \r
 /**\r
@@ -1330,25 +1346,26 @@ SetSevEsJumpTable (
 **/\r
 VOID\r
 WakeUpAP (\r
-  IN CPU_MP_DATA               *CpuMpData,\r
-  IN BOOLEAN                   Broadcast,\r
-  IN UINTN                     ProcessorNumber,\r
-  IN EFI_AP_PROCEDURE          Procedure               OPTIONAL,\r
-  IN VOID                      *ProcedureArgument      OPTIONAL,\r
-  IN BOOLEAN                   WakeUpDisabledAps\r
+  IN CPU_MP_DATA       *CpuMpData,\r
+  IN BOOLEAN           Broadcast,\r
+  IN UINTN             ProcessorNumber,\r
+  IN EFI_AP_PROCEDURE  Procedure               OPTIONAL,\r
+  IN VOID              *ProcedureArgument      OPTIONAL,\r
+  IN BOOLEAN           WakeUpDisabledAps\r
   )\r
 {\r
-  volatile MP_CPU_EXCHANGE_INFO    *ExchangeInfo;\r
-  UINTN                            Index;\r
-  CPU_AP_DATA                      *CpuData;\r
-  BOOLEAN                          ResetVectorRequired;\r
-  CPU_INFO_IN_HOB                  *CpuInfoInHob;\r
+  volatile MP_CPU_EXCHANGE_INFO  *ExchangeInfo;\r
+  UINTN                          Index;\r
+  CPU_AP_DATA                    *CpuData;\r
+  BOOLEAN                        ResetVectorRequired;\r
+  CPU_INFO_IN_HOB                *CpuInfoInHob;\r
 \r
   CpuMpData->FinishedCount = 0;\r
-  ResetVectorRequired = FALSE;\r
+  ResetVectorRequired      = FALSE;\r
 \r
   if (CpuMpData->WakeUpByInitSipiSipi ||\r
-      CpuMpData->InitFlag   != ApInitDone) {\r
+      (CpuMpData->InitFlag   != ApInitDone))\r
+  {\r
     ResetVectorRequired = TRUE;\r
     AllocateResetVector (CpuMpData);\r
     AllocateSevEsAPMemory (CpuMpData);\r
@@ -1375,18 +1392,19 @@ WakeUpAP (
         // the AP procedure will be skipped for disabled AP because AP state\r
         // is not CpuStateReady.\r
         //\r
-        if (GetApState (CpuData) == CpuStateDisabled && !WakeUpDisabledAps) {\r
+        if ((GetApState (CpuData) == CpuStateDisabled) && !WakeUpDisabledAps) {\r
           continue;\r
         }\r
 \r
-        CpuData->ApFunction         = (UINTN) Procedure;\r
-        CpuData->ApFunctionArgument = (UINTN) ProcedureArgument;\r
+        CpuData->ApFunction         = (UINTN)Procedure;\r
+        CpuData->ApFunctionArgument = (UINTN)ProcedureArgument;\r
         SetApState (CpuData, CpuStateReady);\r
         if (CpuMpData->InitFlag != ApInitConfig) {\r
-          *(UINT32 *) CpuData->StartupApSignal = WAKEUP_AP_SIGNAL;\r
+          *(UINT32 *)CpuData->StartupApSignal = WAKEUP_AP_SIGNAL;\r
         }\r
       }\r
     }\r
+\r
     if (ResetVectorRequired) {\r
       //\r
       // For SEV-ES, the initial AP boot address will be defined by\r
@@ -1400,8 +1418,9 @@ WakeUpAP (
       //\r
       // Wakeup all APs\r
       //\r
-      SendInitSipiSipiAllExcludingSelf ((UINT32) ExchangeInfo->BufferStart);\r
+      SendInitSipiSipiAllExcludingSelf ((UINT32)ExchangeInfo->BufferStart);\r
     }\r
+\r
     if (CpuMpData->InitFlag == ApInitConfig) {\r
       if (PcdGet32 (PcdCpuBootLogicalProcessorNumber) > 0) {\r
         //\r
@@ -1462,7 +1481,7 @@ WakeUpAP (
           );\r
 \r
         while (CpuMpData->MpCpuExchangeInfo->NumApsExecuting != 0) {\r
-          CpuPause();\r
+          CpuPause ();\r
         }\r
       }\r
     } else {\r
@@ -1477,17 +1496,17 @@ WakeUpAP (
       }\r
     }\r
   } else {\r
-    CpuData = &CpuMpData->CpuData[ProcessorNumber];\r
-    CpuData->ApFunction         = (UINTN) Procedure;\r
-    CpuData->ApFunctionArgument = (UINTN) ProcedureArgument;\r
+    CpuData                     = &CpuMpData->CpuData[ProcessorNumber];\r
+    CpuData->ApFunction         = (UINTN)Procedure;\r
+    CpuData->ApFunctionArgument = (UINTN)ProcedureArgument;\r
     SetApState (CpuData, CpuStateReady);\r
     //\r
     // Wakeup specified AP\r
     //\r
     ASSERT (CpuMpData->InitFlag != ApInitConfig);\r
-    *(UINT32 *) CpuData->StartupApSignal = WAKEUP_AP_SIGNAL;\r
+    *(UINT32 *)CpuData->StartupApSignal = WAKEUP_AP_SIGNAL;\r
     if (ResetVectorRequired) {\r
-      CpuInfoInHob = (CPU_INFO_IN_HOB *) (UINTN) CpuMpData->CpuInfoInHob;\r
+      CpuInfoInHob = (CPU_INFO_IN_HOB *)(UINTN)CpuMpData->CpuInfoInHob;\r
 \r
       //\r
       // For SEV-ES, the initial AP boot address will be defined by\r
@@ -1500,9 +1519,10 @@ WakeUpAP (
 \r
       SendInitSipiSipi (\r
         CpuInfoInHob[ProcessorNumber].ApicId,\r
-        (UINT32) ExchangeInfo->BufferStart\r
+        (UINT32)ExchangeInfo->BufferStart\r
         );\r
     }\r
+\r
     //\r
     // Wait specified AP waken up\r
     //\r
@@ -1542,8 +1562,8 @@ CalculateTimeout (
   OUT UINT64  *CurrentTime\r
   )\r
 {\r
-  UINT64 TimeoutInSeconds;\r
-  UINT64 TimestampCounterFreq;\r
+  UINT64  TimeoutInSeconds;\r
+  UINT64  TimestampCounterFreq;\r
 \r
   //\r
   // Read the current value of the performance counter\r
@@ -1628,25 +1648,30 @@ CheckTimeout (
   if (Timeout == 0) {\r
     return FALSE;\r
   }\r
+\r
   GetPerformanceCounterProperties (&Start, &End);\r
   Cycle = End - Start;\r
   if (Cycle < 0) {\r
     Cycle = -Cycle;\r
   }\r
+\r
   Cycle++;\r
-  CurrentTime = GetPerformanceCounter();\r
-  Delta = (INT64) (CurrentTime - *PreviousTime);\r
+  CurrentTime = GetPerformanceCounter ();\r
+  Delta       = (INT64)(CurrentTime - *PreviousTime);\r
   if (Start > End) {\r
     Delta = -Delta;\r
   }\r
+\r
   if (Delta < 0) {\r
     Delta += Cycle;\r
   }\r
-  *TotalTime += Delta;\r
+\r
+  *TotalTime   += Delta;\r
   *PreviousTime = CurrentTime;\r
   if (*TotalTime > Timeout) {\r
     return TRUE;\r
   }\r
+\r
   return FALSE;\r
 }\r
 \r
@@ -1660,9 +1685,9 @@ CheckTimeout (
 **/\r
 VOID\r
 TimedWaitForApFinish (\r
-  IN CPU_MP_DATA               *CpuMpData,\r
-  IN UINT32                    FinishedApLimit,\r
-  IN UINT32                    TimeLimit\r
+  IN CPU_MP_DATA  *CpuMpData,\r
+  IN UINT32       FinishedApLimit,\r
+  IN UINT32       TimeLimit\r
   )\r
 {\r
   //\r
@@ -1673,7 +1698,7 @@ TimedWaitForApFinish (
     return;\r
   }\r
 \r
-  CpuMpData->TotalTime = 0;\r
+  CpuMpData->TotalTime    = 0;\r
   CpuMpData->ExpectedTime = CalculateTimeout (\r
                               TimeLimit,\r
                               &CpuMpData->CurrentTime\r
@@ -1683,7 +1708,8 @@ TimedWaitForApFinish (
             &CpuMpData->CurrentTime,\r
             &CpuMpData->TotalTime,\r
             CpuMpData->ExpectedTime\r
-            )) {\r
+            ))\r
+  {\r
     CpuPause ();\r
   }\r
 \r
@@ -1712,10 +1738,10 @@ TimedWaitForApFinish (
 **/\r
 VOID\r
 ResetProcessorToIdleState (\r
-  IN UINTN                     ProcessorNumber\r
+  IN UINTN  ProcessorNumber\r
   )\r
 {\r
-  CPU_MP_DATA           *CpuMpData;\r
+  CPU_MP_DATA  *CpuMpData;\r
 \r
   CpuMpData = GetCpuMpData ();\r
 \r
@@ -1724,6 +1750,7 @@ ResetProcessorToIdleState (
   while (CpuMpData->FinishedCount < 1) {\r
     CpuPause ();\r
   }\r
+\r
   CpuMpData->InitFlag = ApInitDone;\r
 \r
   SetApState (&CpuMpData->CpuData[ProcessorNumber], CpuStateIdle);\r
@@ -1742,11 +1769,11 @@ ResetProcessorToIdleState (
 **/\r
 EFI_STATUS\r
 GetNextWaitingProcessorNumber (\r
-  OUT UINTN                    *NextProcessorNumber\r
+  OUT UINTN  *NextProcessorNumber\r
   )\r
 {\r
-  UINTN           ProcessorNumber;\r
-  CPU_MP_DATA     *CpuMpData;\r
+  UINTN        ProcessorNumber;\r
+  CPU_MP_DATA  *CpuMpData;\r
 \r
   CpuMpData = GetCpuMpData ();\r
 \r
@@ -1773,11 +1800,11 @@ GetNextWaitingProcessorNumber (
 **/\r
 EFI_STATUS\r
 CheckThisAP (\r
-  IN UINTN        ProcessorNumber\r
+  IN UINTN  ProcessorNumber\r
   )\r
 {\r
-  CPU_MP_DATA     *CpuMpData;\r
-  CPU_AP_DATA     *CpuData;\r
+  CPU_MP_DATA  *CpuMpData;\r
+  CPU_AP_DATA  *CpuData;\r
 \r
   CpuMpData = GetCpuMpData ();\r
   CpuData   = &CpuMpData->CpuData[ProcessorNumber];\r
@@ -1790,10 +1817,11 @@ CheckThisAP (
   //\r
   // If the AP finishes for StartupThisAP(), return EFI_SUCCESS.\r
   //\r
-  if (GetApState(CpuData) == CpuStateFinished) {\r
+  if (GetApState (CpuData) == CpuStateFinished) {\r
     if (CpuData->Finished != NULL) {\r
       *(CpuData->Finished) = TRUE;\r
     }\r
+\r
     SetApState (CpuData, CpuStateIdle);\r
     return EFI_SUCCESS;\r
   } else {\r
@@ -1804,6 +1832,7 @@ CheckThisAP (
       if (CpuData->Finished != NULL) {\r
         *(CpuData->Finished) = FALSE;\r
       }\r
+\r
       //\r
       // Reset failed AP to idle state\r
       //\r
@@ -1812,6 +1841,7 @@ CheckThisAP (
       return EFI_TIMEOUT;\r
     }\r
   }\r
+\r
   return EFI_NOT_READY;\r
 }\r
 \r
@@ -1830,12 +1860,12 @@ CheckAllAPs (
   VOID\r
   )\r
 {\r
-  UINTN           ProcessorNumber;\r
-  UINTN           NextProcessorNumber;\r
-  UINTN           ListIndex;\r
-  EFI_STATUS      Status;\r
-  CPU_MP_DATA     *CpuMpData;\r
-  CPU_AP_DATA     *CpuData;\r
+  UINTN        ProcessorNumber;\r
+  UINTN        NextProcessorNumber;\r
+  UINTN        ListIndex;\r
+  EFI_STATUS   Status;\r
+  CPU_MP_DATA  *CpuMpData;\r
+  CPU_AP_DATA  *CpuData;\r
 \r
   CpuMpData = GetCpuMpData ();\r
 \r
@@ -1855,10 +1885,10 @@ CheckAllAPs (
     // Only BSP and corresponding AP access this unit of CPU Data. This means the AP will not modify the\r
     // value of state after setting the it to CpuStateIdle, so BSP can safely make use of its value.\r
     //\r
-    if (GetApState(CpuData) == CpuStateFinished) {\r
-      CpuMpData->RunningCount --;\r
+    if (GetApState (CpuData) == CpuStateFinished) {\r
+      CpuMpData->RunningCount--;\r
       CpuMpData->CpuData[ProcessorNumber].Waiting = FALSE;\r
-      SetApState(CpuData, CpuStateIdle);\r
+      SetApState (CpuData, CpuStateIdle);\r
 \r
       //\r
       // If in Single Thread mode, then search for the next waiting AP for execution.\r
@@ -1870,12 +1900,12 @@ CheckAllAPs (
           WakeUpAP (\r
             CpuMpData,\r
             FALSE,\r
-            (UINT32) NextProcessorNumber,\r
+            (UINT32)NextProcessorNumber,\r
             CpuMpData->Procedure,\r
             CpuMpData->ProcArguments,\r
             TRUE\r
             );\r
-         }\r
+        }\r
       }\r
     }\r
   }\r
@@ -1891,18 +1921,21 @@ CheckAllAPs (
   // If timeout expires, report timeout.\r
   //\r
   if (CheckTimeout (\r
-       &CpuMpData->CurrentTime,\r
-       &CpuMpData->TotalTime,\r
-       CpuMpData->ExpectedTime)\r
-       ) {\r
+        &CpuMpData->CurrentTime,\r
+        &CpuMpData->TotalTime,\r
+        CpuMpData->ExpectedTime\r
+        )\r
+      )\r
+  {\r
     //\r
     // If FailedCpuList is not NULL, record all failed APs in it.\r
     //\r
     if (CpuMpData->FailedCpuList != NULL) {\r
       *CpuMpData->FailedCpuList =\r
-         AllocatePool ((CpuMpData->RunningCount + 1) * sizeof (UINTN));\r
+        AllocatePool ((CpuMpData->RunningCount + 1) * sizeof (UINTN));\r
       ASSERT (*CpuMpData->FailedCpuList != NULL);\r
     }\r
+\r
     ListIndex = 0;\r
 \r
     for (ProcessorNumber = 0; ProcessorNumber < CpuMpData->CpuCount; ProcessorNumber++) {\r
@@ -1920,11 +1953,14 @@ CheckAllAPs (
         }\r
       }\r
     }\r
+\r
     if (CpuMpData->FailedCpuList != NULL) {\r
       (*CpuMpData->FailedCpuList)[ListIndex] = END_OF_CPU_LIST;\r
     }\r
+\r
     return EFI_TIMEOUT;\r
   }\r
+\r
   return EFI_NOT_READY;\r
 }\r
 \r
@@ -1967,16 +2003,17 @@ MpInitLibInitialize (
 \r
   OldCpuMpData = GetCpuMpDataFromGuidedHob ();\r
   if (OldCpuMpData == NULL) {\r
-    MaxLogicalProcessorNumber = PcdGet32(PcdCpuMaxLogicalProcessorNumber);\r
+    MaxLogicalProcessorNumber = PcdGet32 (PcdCpuMaxLogicalProcessorNumber);\r
   } else {\r
     MaxLogicalProcessorNumber = OldCpuMpData->CpuCount;\r
   }\r
+\r
   ASSERT (MaxLogicalProcessorNumber != 0);\r
 \r
   AsmGetAddressMap (&AddressMap);\r
   ApResetVectorSize = GetApResetVectorSize (&AddressMap);\r
-  ApStackSize = PcdGet32(PcdCpuApStackSize);\r
-  ApLoopMode  = GetApLoopMode (&MonitorFilterSize);\r
+  ApStackSize       = PcdGet32 (PcdCpuApStackSize);\r
+  ApLoopMode        = GetApLoopMode (&MonitorFilterSize);\r
 \r
   //\r
   // Save BSP's Control registers for APs.\r
@@ -1993,7 +2030,7 @@ MpInitLibInitialize (
   MpBuffer    = AllocatePages (EFI_SIZE_TO_PAGES (BufferSize));\r
   ASSERT (MpBuffer != NULL);\r
   ZeroMem (MpBuffer, BufferSize);\r
-  Buffer = (UINTN) MpBuffer;\r
+  Buffer = (UINTN)MpBuffer;\r
 \r
   //\r
   //  The layout of the Buffer is as below:\r
@@ -2016,31 +2053,33 @@ MpInitLibInitialize (
   //      CPU_INFO_IN_HOB (N)\r
   //    +--------------------+\r
   //\r
-  MonitorBuffer    = (UINT8 *) (Buffer + ApStackSize * MaxLogicalProcessorNumber);\r
-  BackupBufferAddr = (UINTN) MonitorBuffer + MonitorFilterSize * MaxLogicalProcessorNumber;\r
-  ApIdtBase        = ALIGN_VALUE (BackupBufferAddr + ApResetVectorSize, 8);\r
-  CpuMpData        = (CPU_MP_DATA *) (ApIdtBase + VolatileRegisters.Idtr.Limit + 1);\r
+  MonitorBuffer               = (UINT8 *)(Buffer + ApStackSize * MaxLogicalProcessorNumber);\r
+  BackupBufferAddr            = (UINTN)MonitorBuffer + MonitorFilterSize * MaxLogicalProcessorNumber;\r
+  ApIdtBase                   = ALIGN_VALUE (BackupBufferAddr + ApResetVectorSize, 8);\r
+  CpuMpData                   = (CPU_MP_DATA *)(ApIdtBase + VolatileRegisters.Idtr.Limit + 1);\r
   CpuMpData->Buffer           = Buffer;\r
   CpuMpData->CpuApStackSize   = ApStackSize;\r
   CpuMpData->BackupBuffer     = BackupBufferAddr;\r
   CpuMpData->BackupBufferSize = ApResetVectorSize;\r
-  CpuMpData->WakeupBuffer     = (UINTN) -1;\r
+  CpuMpData->WakeupBuffer     = (UINTN)-1;\r
   CpuMpData->CpuCount         = 1;\r
   CpuMpData->BspNumber        = 0;\r
   CpuMpData->WaitEvent        = NULL;\r
   CpuMpData->SwitchBspFlag    = FALSE;\r
-  CpuMpData->CpuData          = (CPU_AP_DATA *) (CpuMpData + 1);\r
-  CpuMpData->CpuInfoInHob     = (UINT64) (UINTN) (CpuMpData->CpuData + MaxLogicalProcessorNumber);\r
-  InitializeSpinLock(&CpuMpData->MpLock);\r
+  CpuMpData->CpuData          = (CPU_AP_DATA *)(CpuMpData + 1);\r
+  CpuMpData->CpuInfoInHob     = (UINT64)(UINTN)(CpuMpData->CpuData + MaxLogicalProcessorNumber);\r
+  InitializeSpinLock (&CpuMpData->MpLock);\r
   CpuMpData->SevEsIsEnabled = PcdGetBool (PcdSevEsIsEnabled);\r
-  CpuMpData->SevEsAPBuffer  = (UINTN) -1;\r
+  CpuMpData->SevEsAPBuffer  = (UINTN)-1;\r
   CpuMpData->GhcbBase       = PcdGet64 (PcdGhcbBase);\r
 \r
   //\r
   // Make sure no memory usage outside of the allocated buffer.\r
   //\r
-  ASSERT ((CpuMpData->CpuInfoInHob + sizeof (CPU_INFO_IN_HOB) * MaxLogicalProcessorNumber) ==\r
-          Buffer + BufferSize);\r
+  ASSERT (\r
+    (CpuMpData->CpuInfoInHob + sizeof (CPU_INFO_IN_HOB) * MaxLogicalProcessorNumber) ==\r
+    Buffer + BufferSize\r
+    );\r
 \r
   //\r
   // Duplicate BSP's IDT to APs.\r
@@ -2076,6 +2115,7 @@ MpInitLibInitialize (
     CpuMpData->CpuData[Index].StartupApSignal =\r
       (UINT32 *)(MonitorBuffer + MonitorFilterSize * Index);\r
   }\r
+\r
   //\r
   // Enable the local APIC for Virtual Wire Mode.\r
   //\r
@@ -2094,13 +2134,13 @@ MpInitLibInitialize (
     // from HOB\r
     //\r
     OldCpuMpData->NewCpuMpData = CpuMpData;\r
-    CpuMpData->CpuCount  = OldCpuMpData->CpuCount;\r
-    CpuMpData->BspNumber = OldCpuMpData->BspNumber;\r
-    CpuMpData->CpuInfoInHob = OldCpuMpData->CpuInfoInHob;\r
-    CpuInfoInHob = (CPU_INFO_IN_HOB *) (UINTN) CpuMpData->CpuInfoInHob;\r
+    CpuMpData->CpuCount        = OldCpuMpData->CpuCount;\r
+    CpuMpData->BspNumber       = OldCpuMpData->BspNumber;\r
+    CpuMpData->CpuInfoInHob    = OldCpuMpData->CpuInfoInHob;\r
+    CpuInfoInHob               = (CPU_INFO_IN_HOB *)(UINTN)CpuMpData->CpuInfoInHob;\r
     for (Index = 0; Index < CpuMpData->CpuCount; Index++) {\r
-      InitializeSpinLock(&CpuMpData->CpuData[Index].ApLock);\r
-      CpuMpData->CpuData[Index].CpuHealthy = (CpuInfoInHob[Index].Health == 0)? TRUE:FALSE;\r
+      InitializeSpinLock (&CpuMpData->CpuData[Index].ApLock);\r
+      CpuMpData->CpuData[Index].CpuHealthy = (CpuInfoInHob[Index].Health == 0) ? TRUE : FALSE;\r
       CpuMpData->CpuData[Index].ApFunction = 0;\r
     }\r
   }\r
@@ -2108,7 +2148,8 @@ MpInitLibInitialize (
   if (!GetMicrocodePatchInfoFromHob (\r
          &CpuMpData->MicrocodePatchAddress,\r
          &CpuMpData->MicrocodePatchRegionSize\r
-         )) {\r
+         ))\r
+  {\r
     //\r
     // The microcode patch information cache HOB does not exist, which means\r
     // the microcode patches data has not been loaded into memory yet\r
@@ -2137,6 +2178,7 @@ MpInitLibInitialize (
       //\r
       CpuMpData->InitFlag = ApInitReconfig;\r
     }\r
+\r
     WakeUpAP (CpuMpData, TRUE, 0, ApInitializeSync, CpuMpData, TRUE);\r
     //\r
     // Wait for all APs finished initialization\r
@@ -2144,9 +2186,11 @@ MpInitLibInitialize (
     while (CpuMpData->FinishedCount < (CpuMpData->CpuCount - 1)) {\r
       CpuPause ();\r
     }\r
+\r
     if (OldCpuMpData != NULL) {\r
       CpuMpData->InitFlag = ApInitDone;\r
     }\r
+\r
     for (Index = 0; Index < CpuMpData->CpuCount; Index++) {\r
       SetApState (&CpuMpData->CpuData[Index], CpuStateIdle);\r
     }\r
@@ -2156,26 +2200,32 @@ MpInitLibInitialize (
   // Dump the microcode revision for each core.\r
   //\r
   DEBUG_CODE_BEGIN ();\r
-    UINT32 ThreadId;\r
-    UINT32 ExpectedMicrocodeRevision;\r
-    CpuInfoInHob = (CPU_INFO_IN_HOB *) (UINTN) CpuMpData->CpuInfoInHob;\r
-    for (Index = 0; Index < CpuMpData->CpuCount; Index++) {\r
-      GetProcessorLocationByApicId (CpuInfoInHob[Index].InitialApicId, NULL, NULL, &ThreadId);\r
-      if (ThreadId == 0) {\r
-        //\r
-        // MicrocodeDetect() loads microcode in first thread of each core, so,\r
-        // CpuMpData->CpuData[Index].MicrocodeEntryAddr is initialized only for first thread of each core.\r
-        //\r
-        ExpectedMicrocodeRevision = 0;\r
-        if (CpuMpData->CpuData[Index].MicrocodeEntryAddr != 0) {\r
-          ExpectedMicrocodeRevision = ((CPU_MICROCODE_HEADER *)(UINTN)CpuMpData->CpuData[Index].MicrocodeEntryAddr)->UpdateRevision;\r
-        }\r
-        DEBUG ((\r
-          DEBUG_INFO, "CPU[%04d]: Microcode revision = %08x, expected = %08x\n",\r
-          Index, CpuMpData->CpuData[Index].MicrocodeRevision, ExpectedMicrocodeRevision\r
-          ));\r
+  UINT32  ThreadId;\r
+  UINT32  ExpectedMicrocodeRevision;\r
+\r
+  CpuInfoInHob = (CPU_INFO_IN_HOB *)(UINTN)CpuMpData->CpuInfoInHob;\r
+  for (Index = 0; Index < CpuMpData->CpuCount; Index++) {\r
+    GetProcessorLocationByApicId (CpuInfoInHob[Index].InitialApicId, NULL, NULL, &ThreadId);\r
+    if (ThreadId == 0) {\r
+      //\r
+      // MicrocodeDetect() loads microcode in first thread of each core, so,\r
+      // CpuMpData->CpuData[Index].MicrocodeEntryAddr is initialized only for first thread of each core.\r
+      //\r
+      ExpectedMicrocodeRevision = 0;\r
+      if (CpuMpData->CpuData[Index].MicrocodeEntryAddr != 0) {\r
+        ExpectedMicrocodeRevision = ((CPU_MICROCODE_HEADER *)(UINTN)CpuMpData->CpuData[Index].MicrocodeEntryAddr)->UpdateRevision;\r
       }\r
+\r
+      DEBUG ((\r
+        DEBUG_INFO,\r
+        "CPU[%04d]: Microcode revision = %08x, expected = %08x\n",\r
+        Index,\r
+        CpuMpData->CpuData[Index].MicrocodeRevision,\r
+        ExpectedMicrocodeRevision\r
+        ));\r
     }\r
+  }\r
+\r
   DEBUG_CODE_END ();\r
   //\r
   // Initialize global data for MP support\r
@@ -2210,19 +2260,19 @@ MpInitLibGetProcessorInfo (
   OUT EFI_HEALTH_FLAGS           *HealthData  OPTIONAL\r
   )\r
 {\r
-  CPU_MP_DATA            *CpuMpData;\r
-  UINTN                  CallerNumber;\r
-  CPU_INFO_IN_HOB        *CpuInfoInHob;\r
-  UINTN                  OriginalProcessorNumber;\r
+  CPU_MP_DATA      *CpuMpData;\r
+  UINTN            CallerNumber;\r
+  CPU_INFO_IN_HOB  *CpuInfoInHob;\r
+  UINTN            OriginalProcessorNumber;\r
 \r
-  CpuMpData = GetCpuMpData ();\r
-  CpuInfoInHob = (CPU_INFO_IN_HOB *) (UINTN) CpuMpData->CpuInfoInHob;\r
+  CpuMpData    = GetCpuMpData ();\r
+  CpuInfoInHob = (CPU_INFO_IN_HOB *)(UINTN)CpuMpData->CpuInfoInHob;\r
 \r
   //\r
   // Lower 24 bits contains the actual processor number.\r
   //\r
   OriginalProcessorNumber = ProcessorNumber;\r
-  ProcessorNumber &= BIT24 - 1;\r
+  ProcessorNumber        &= BIT24 - 1;\r
 \r
   //\r
   // Check whether caller processor is BSP\r
@@ -2240,14 +2290,16 @@ MpInitLibGetProcessorInfo (
     return EFI_NOT_FOUND;\r
   }\r
 \r
-  ProcessorInfoBuffer->ProcessorId = (UINT64) CpuInfoInHob[ProcessorNumber].ApicId;\r
+  ProcessorInfoBuffer->ProcessorId = (UINT64)CpuInfoInHob[ProcessorNumber].ApicId;\r
   ProcessorInfoBuffer->StatusFlag  = 0;\r
   if (ProcessorNumber == CpuMpData->BspNumber) {\r
     ProcessorInfoBuffer->StatusFlag |= PROCESSOR_AS_BSP_BIT;\r
   }\r
+\r
   if (CpuMpData->CpuData[ProcessorNumber].CpuHealthy) {\r
     ProcessorInfoBuffer->StatusFlag |= PROCESSOR_HEALTH_STATUS_BIT;\r
   }\r
+\r
   if (GetApState (&CpuMpData->CpuData[ProcessorNumber]) == CpuStateDisabled) {\r
     ProcessorInfoBuffer->StatusFlag &= ~PROCESSOR_ENABLED_BIT;\r
   } else {\r
@@ -2296,8 +2348,8 @@ MpInitLibGetProcessorInfo (
 **/\r
 EFI_STATUS\r
 SwitchBSPWorker (\r
-  IN UINTN                     ProcessorNumber,\r
-  IN BOOLEAN                   EnableOldBSP\r
+  IN UINTN    ProcessorNumber,\r
+  IN BOOLEAN  EnableOldBSP\r
   )\r
 {\r
   CPU_MP_DATA                  *CpuMpData;\r
@@ -2370,7 +2422,7 @@ SwitchBSPWorker (
   //\r
   // Clear the BSP bit of MSR_IA32_APIC_BASE\r
   //\r
-  ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);\r
+  ApicBaseMsr.Uint64   = AsmReadMsr64 (MSR_IA32_APIC_BASE);\r
   ApicBaseMsr.Bits.BSP = 0;\r
   AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64);\r
 \r
@@ -2384,7 +2436,7 @@ SwitchBSPWorker (
   //\r
   // Set the BSP bit of MSR_IA32_APIC_BASE on new BSP\r
   //\r
-  ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);\r
+  ApicBaseMsr.Uint64   = AsmReadMsr64 (MSR_IA32_APIC_BASE);\r
   ApicBaseMsr.Bits.BSP = 1;\r
   AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64);\r
   ProgramVirtualWireMode ();\r
@@ -2405,10 +2457,11 @@ SwitchBSPWorker (
   } else {\r
     SetApState (&CpuMpData->CpuData[CallerNumber], CpuStateIdle);\r
   }\r
+\r
   //\r
   // Save new BSP number\r
   //\r
-  CpuMpData->BspNumber = (UINT32) ProcessorNumber;\r
+  CpuMpData->BspNumber = (UINT32)ProcessorNumber;\r
 \r
   //\r
   // Restore interrupt state.\r
@@ -2438,13 +2491,13 @@ SwitchBSPWorker (
 **/\r
 EFI_STATUS\r
 EnableDisableApWorker (\r
-  IN  UINTN                     ProcessorNumber,\r
-  IN  BOOLEAN                   EnableAP,\r
-  IN  UINT32                    *HealthFlag OPTIONAL\r
+  IN  UINTN    ProcessorNumber,\r
+  IN  BOOLEAN  EnableAP,\r
+  IN  UINT32   *HealthFlag OPTIONAL\r
   )\r
 {\r
-  CPU_MP_DATA               *CpuMpData;\r
-  UINTN                     CallerNumber;\r
+  CPU_MP_DATA  *CpuMpData;\r
+  UINTN        CallerNumber;\r
 \r
   CpuMpData = GetCpuMpData ();\r
 \r
@@ -2472,7 +2525,7 @@ EnableDisableApWorker (
 \r
   if (HealthFlag != NULL) {\r
     CpuMpData->CpuData[ProcessorNumber].CpuHealthy =\r
-          (BOOLEAN) ((*HealthFlag & PROCESSOR_HEALTH_STATUS_BIT) != 0);\r
+      (BOOLEAN)((*HealthFlag & PROCESSOR_HEALTH_STATUS_BIT) != 0);\r
   }\r
 \r
   return EFI_SUCCESS;\r
@@ -2497,10 +2550,10 @@ EnableDisableApWorker (
 EFI_STATUS\r
 EFIAPI\r
 MpInitLibWhoAmI (\r
-  OUT UINTN                    *ProcessorNumber\r
+  OUT UINTN  *ProcessorNumber\r
   )\r
 {\r
-  CPU_MP_DATA           *CpuMpData;\r
+  CPU_MP_DATA  *CpuMpData;\r
 \r
   if (ProcessorNumber == NULL) {\r
     return EFI_INVALID_PARAMETER;\r
@@ -2534,15 +2587,15 @@ MpInitLibWhoAmI (
 EFI_STATUS\r
 EFIAPI\r
 MpInitLibGetNumberOfProcessors (\r
-  OUT UINTN                     *NumberOfProcessors        OPTIONAL,\r
-  OUT UINTN                     *NumberOfEnabledProcessors OPTIONAL\r
+  OUT UINTN  *NumberOfProcessors        OPTIONAL,\r
+  OUT UINTN  *NumberOfEnabledProcessors OPTIONAL\r
   )\r
 {\r
-  CPU_MP_DATA             *CpuMpData;\r
-  UINTN                   CallerNumber;\r
-  UINTN                   ProcessorNumber;\r
-  UINTN                   EnabledProcessorNumber;\r
-  UINTN                   Index;\r
+  CPU_MP_DATA  *CpuMpData;\r
+  UINTN        CallerNumber;\r
+  UINTN        ProcessorNumber;\r
+  UINTN        EnabledProcessorNumber;\r
+  UINTN        Index;\r
 \r
   CpuMpData = GetCpuMpData ();\r
 \r
@@ -2562,13 +2615,14 @@ MpInitLibGetNumberOfProcessors (
   EnabledProcessorNumber = 0;\r
   for (Index = 0; Index < ProcessorNumber; Index++) {\r
     if (GetApState (&CpuMpData->CpuData[Index]) != CpuStateDisabled) {\r
-      EnabledProcessorNumber ++;\r
+      EnabledProcessorNumber++;\r
     }\r
   }\r
 \r
   if (NumberOfProcessors != NULL) {\r
     *NumberOfProcessors = ProcessorNumber;\r
   }\r
+\r
   if (NumberOfEnabledProcessors != NULL) {\r
     *NumberOfEnabledProcessors = EnabledProcessorNumber;\r
   }\r
@@ -2576,7 +2630,6 @@ MpInitLibGetNumberOfProcessors (
   return EFI_SUCCESS;\r
 }\r
 \r
-\r
 /**\r
   Worker function to execute a caller provided function on all enabled APs.\r
 \r
@@ -2611,23 +2664,23 @@ MpInitLibGetNumberOfProcessors (
 **/\r
 EFI_STATUS\r
 StartupAllCPUsWorker (\r
-  IN  EFI_AP_PROCEDURE          Procedure,\r
-  IN  BOOLEAN                   SingleThread,\r
-  IN  BOOLEAN                   ExcludeBsp,\r
-  IN  EFI_EVENT                 WaitEvent               OPTIONAL,\r
-  IN  UINTN                     TimeoutInMicroseconds,\r
-  IN  VOID                      *ProcedureArgument      OPTIONAL,\r
-  OUT UINTN                     **FailedCpuList         OPTIONAL\r
+  IN  EFI_AP_PROCEDURE  Procedure,\r
+  IN  BOOLEAN           SingleThread,\r
+  IN  BOOLEAN           ExcludeBsp,\r
+  IN  EFI_EVENT         WaitEvent               OPTIONAL,\r
+  IN  UINTN             TimeoutInMicroseconds,\r
+  IN  VOID              *ProcedureArgument      OPTIONAL,\r
+  OUT UINTN             **FailedCpuList         OPTIONAL\r
   )\r
 {\r
-  EFI_STATUS              Status;\r
-  CPU_MP_DATA             *CpuMpData;\r
-  UINTN                   ProcessorCount;\r
-  UINTN                   ProcessorNumber;\r
-  UINTN                   CallerNumber;\r
-  CPU_AP_DATA             *CpuData;\r
-  BOOLEAN                 HasEnabledAp;\r
-  CPU_STATE               ApState;\r
+  EFI_STATUS   Status;\r
+  CPU_MP_DATA  *CpuMpData;\r
+  UINTN        ProcessorCount;\r
+  UINTN        ProcessorNumber;\r
+  UINTN        CallerNumber;\r
+  CPU_AP_DATA  *CpuData;\r
+  BOOLEAN      HasEnabledAp;\r
+  CPU_STATE    ApState;\r
 \r
   CpuMpData = GetCpuMpData ();\r
 \r
@@ -2635,7 +2688,7 @@ StartupAllCPUsWorker (
     *FailedCpuList = NULL;\r
   }\r
 \r
-  if (CpuMpData->CpuCount == 1 && ExcludeBsp) {\r
+  if ((CpuMpData->CpuCount == 1) && ExcludeBsp) {\r
     return EFI_NOT_STARTED;\r
   }\r
 \r
@@ -2687,7 +2740,7 @@ StartupAllCPUsWorker (
 \r
   CpuMpData->RunningCount = 0;\r
   for (ProcessorNumber = 0; ProcessorNumber < ProcessorCount; ProcessorNumber++) {\r
-    CpuData = &CpuMpData->CpuData[ProcessorNumber];\r
+    CpuData          = &CpuMpData->CpuData[ProcessorNumber];\r
     CpuData->Waiting = FALSE;\r
     if (ProcessorNumber != CpuMpData->BspNumber) {\r
       if (CpuData->State == CpuStateIdle) {\r
@@ -2709,8 +2762,8 @@ StartupAllCPUsWorker (
                                TimeoutInMicroseconds,\r
                                &CpuMpData->CurrentTime\r
                                );\r
-  CpuMpData->TotalTime     = 0;\r
-  CpuMpData->WaitEvent     = WaitEvent;\r
+  CpuMpData->TotalTime = 0;\r
+  CpuMpData->WaitEvent = WaitEvent;\r
 \r
   if (!SingleThread) {\r
     WakeUpAP (CpuMpData, TRUE, 0, Procedure, ProcedureArgument, FALSE);\r
@@ -2719,6 +2772,7 @@ StartupAllCPUsWorker (
       if (ProcessorNumber == CallerNumber) {\r
         continue;\r
       }\r
+\r
       if (CpuMpData->CpuData[ProcessorNumber].Waiting) {\r
         WakeUpAP (CpuMpData, FALSE, ProcessorNumber, Procedure, ProcedureArgument, TRUE);\r
         break;\r
@@ -2768,18 +2822,18 @@ StartupAllCPUsWorker (
 **/\r
 EFI_STATUS\r
 StartupThisAPWorker (\r
-  IN  EFI_AP_PROCEDURE          Procedure,\r
-  IN  UINTN                     ProcessorNumber,\r
-  IN  EFI_EVENT                 WaitEvent               OPTIONAL,\r
-  IN  UINTN                     TimeoutInMicroseconds,\r
-  IN  VOID                      *ProcedureArgument      OPTIONAL,\r
-  OUT BOOLEAN                   *Finished               OPTIONAL\r
+  IN  EFI_AP_PROCEDURE  Procedure,\r
+  IN  UINTN             ProcessorNumber,\r
+  IN  EFI_EVENT         WaitEvent               OPTIONAL,\r
+  IN  UINTN             TimeoutInMicroseconds,\r
+  IN  VOID              *ProcedureArgument      OPTIONAL,\r
+  OUT BOOLEAN           *Finished               OPTIONAL\r
   )\r
 {\r
-  EFI_STATUS              Status;\r
-  CPU_MP_DATA             *CpuMpData;\r
-  CPU_AP_DATA             *CpuData;\r
-  UINTN                   CallerNumber;\r
+  EFI_STATUS   Status;\r
+  CPU_MP_DATA  *CpuMpData;\r
+  CPU_AP_DATA  *CpuData;\r
+  UINTN        CallerNumber;\r
 \r
   CpuMpData = GetCpuMpData ();\r
 \r
@@ -2833,7 +2887,7 @@ StartupThisAPWorker (
   // BSP saves data for CheckAPsStatus(), and returns EFI_SUCCESS.\r
   // CheckAPsStatus() will check completion and timeout periodically.\r
   //\r
-  CpuData = &CpuMpData->CpuData[ProcessorNumber];\r
+  CpuData               = &CpuMpData->CpuData[ProcessorNumber];\r
   CpuData->WaitEvent    = WaitEvent;\r
   CpuData->Finished     = Finished;\r
   CpuData->ExpectedTime = CalculateTimeout (TimeoutInMicroseconds, &CpuData->CurrentTime);\r
@@ -2865,16 +2919,17 @@ GetCpuMpDataFromGuidedHob (
   VOID\r
   )\r
 {\r
-  EFI_HOB_GUID_TYPE       *GuidHob;\r
-  VOID                    *DataInHob;\r
-  CPU_MP_DATA             *CpuMpData;\r
+  EFI_HOB_GUID_TYPE  *GuidHob;\r
+  VOID               *DataInHob;\r
+  CPU_MP_DATA        *CpuMpData;\r
 \r
   CpuMpData = NULL;\r
-  GuidHob = GetFirstGuidHob (&mCpuInitMpLibHobGuid);\r
+  GuidHob   = GetFirstGuidHob (&mCpuInitMpLibHobGuid);\r
   if (GuidHob != NULL) {\r
     DataInHob = GET_GUID_HOB_DATA (GuidHob);\r
-    CpuMpData = (CPU_MP_DATA *) (*(UINTN *) DataInHob);\r
+    CpuMpData = (CPU_MP_DATA *)(*(UINTN *)DataInHob);\r
   }\r
+\r
   return CpuMpData;\r
 }\r
 \r
@@ -2907,9 +2962,9 @@ GetCpuMpDataFromGuidedHob (
 EFI_STATUS\r
 EFIAPI\r
 MpInitLibStartupAllCPUs (\r
-  IN  EFI_AP_PROCEDURE          Procedure,\r
-  IN  UINTN                     TimeoutInMicroseconds,\r
-  IN  VOID                      *ProcedureArgument      OPTIONAL\r
+  IN  EFI_AP_PROCEDURE  Procedure,\r
+  IN  UINTN             TimeoutInMicroseconds,\r
+  IN  VOID              *ProcedureArgument      OPTIONAL\r
   )\r
 {\r
   return StartupAllCPUsWorker (\r

diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.h b/UefiCpuPkg/Library/MpInitLib/MpLib.h
index 98a207c628bea4e5de09d2545759b5547e5c5afd..a647772088d9d979ddc0d5557105713a43e87d4e 100644 (file)
--- a/UefiCpuPkg/Library/MpInitLib/MpLib.h
+++ b/UefiCpuPkg/Library/MpInitLib/MpLib.h
@@ -36,7 +36,7 @@
 \r
 #include <Guid/MicrocodePatchHob.h>\r
 \r
-#define WAKEUP_AP_SIGNAL SIGNATURE_32 ('S', 'T', 'A', 'P')\r
+#define WAKEUP_AP_SIGNAL  SIGNATURE_32 ('S', 'T', 'A', 'P')\r
 \r
 #define CPU_INIT_MP_LIB_HOB_GUID \\r
   { \\r
@@ -46,14 +46,14 @@
 //\r
 //  The MP data for switch BSP\r
 //\r
-#define CPU_SWITCH_STATE_IDLE   0\r
-#define CPU_SWITCH_STATE_STORED 1\r
-#define CPU_SWITCH_STATE_LOADED 2\r
+#define CPU_SWITCH_STATE_IDLE    0\r
+#define CPU_SWITCH_STATE_STORED  1\r
+#define CPU_SWITCH_STATE_LOADED  2\r
 \r
 //\r
 // Default maximum number of entries to store the microcode patches information\r
 //\r
-#define DEFAULT_MAX_MICROCODE_PATCH_NUM 8\r
+#define DEFAULT_MAX_MICROCODE_PATCH_NUM  8\r
 \r
 //\r
 // Data structure for microcode patch information\r
@@ -67,10 +67,10 @@ typedef struct {
 // CPU exchange information for switch BSP\r
 //\r
 typedef struct {\r
-  UINT8             State;        // offset 0\r
-  UINTN             StackPointer; // offset 4 / 8\r
-  IA32_DESCRIPTOR   Gdtr;         // offset 8 / 16\r
-  IA32_DESCRIPTOR   Idtr;         // offset 14 / 26\r
+  UINT8              State;        // offset 0\r
+  UINTN              StackPointer; // offset 4 / 8\r
+  IA32_DESCRIPTOR    Gdtr;         // offset 8 / 16\r
+  IA32_DESCRIPTOR    Idtr;         // offset 14 / 26\r
 } CPU_EXCHANGE_ROLE_INFO;\r
 \r
 //\r
@@ -111,41 +111,41 @@ typedef enum {
 // CPU volatile registers around INIT-SIPI-SIPI\r
 //\r
 typedef struct {\r
-  UINTN                          Cr0;\r
-  UINTN                          Cr3;\r
-  UINTN                          Cr4;\r
-  UINTN                          Dr0;\r
-  UINTN                          Dr1;\r
-  UINTN                          Dr2;\r
-  UINTN                          Dr3;\r
-  UINTN                          Dr6;\r
-  UINTN                          Dr7;\r
-  IA32_DESCRIPTOR                Gdtr;\r
-  IA32_DESCRIPTOR                Idtr;\r
-  UINT16                         Tr;\r
+  UINTN              Cr0;\r
+  UINTN              Cr3;\r
+  UINTN              Cr4;\r
+  UINTN              Dr0;\r
+  UINTN              Dr1;\r
+  UINTN              Dr2;\r
+  UINTN              Dr3;\r
+  UINTN              Dr6;\r
+  UINTN              Dr7;\r
+  IA32_DESCRIPTOR    Gdtr;\r
+  IA32_DESCRIPTOR    Idtr;\r
+  UINT16             Tr;\r
 } CPU_VOLATILE_REGISTERS;\r
 \r
 //\r
 // AP related data\r
 //\r
 typedef struct {\r
-  SPIN_LOCK                      ApLock;\r
-  volatile UINT32                *StartupApSignal;\r
-  volatile UINTN                 ApFunction;\r
-  volatile UINTN                 ApFunctionArgument;\r
-  BOOLEAN                        CpuHealthy;\r
-  volatile CPU_STATE             State;\r
-  CPU_VOLATILE_REGISTERS         VolatileRegisters;\r
-  BOOLEAN                        Waiting;\r
-  BOOLEAN                        *Finished;\r
-  UINT64                         ExpectedTime;\r
-  UINT64                         CurrentTime;\r
-  UINT64                         TotalTime;\r
-  EFI_EVENT                      WaitEvent;\r
-  UINT32                         ProcessorSignature;\r
-  UINT8                          PlatformId;\r
-  UINT64                         MicrocodeEntryAddr;\r
-  UINT32                         MicrocodeRevision;\r
+  SPIN_LOCK                 ApLock;\r
+  volatile UINT32           *StartupApSignal;\r
+  volatile UINTN            ApFunction;\r
+  volatile UINTN            ApFunctionArgument;\r
+  BOOLEAN                   CpuHealthy;\r
+  volatile CPU_STATE        State;\r
+  CPU_VOLATILE_REGISTERS    VolatileRegisters;\r
+  BOOLEAN                   Waiting;\r
+  BOOLEAN                   *Finished;\r
+  UINT64                    ExpectedTime;\r
+  UINT64                    CurrentTime;\r
+  UINT64                    TotalTime;\r
+  EFI_EVENT                 WaitEvent;\r
+  UINT32                    ProcessorSignature;\r
+  UINT8                     PlatformId;\r
+  UINT64                    MicrocodeEntryAddr;\r
+  UINT32                    MicrocodeRevision;\r
 } CPU_AP_DATA;\r
 \r
 //\r
@@ -156,10 +156,10 @@ typedef struct {
 //\r
 #pragma pack (1)\r
 typedef struct {\r
-  UINT32                         InitialApicId;\r
-  UINT32                         ApicId;\r
-  UINT32                         Health;\r
-  UINT64                         ApTopOfStack;\r
+  UINT32    InitialApicId;\r
+  UINT32    ApicId;\r
+  UINT32    Health;\r
+  UINT64    ApTopOfStack;\r
 } CPU_INFO_IN_HOB;\r
 #pragma pack ()\r
 \r
@@ -169,20 +169,20 @@ typedef struct {
 // It is natural aligned by design.\r
 //\r
 typedef struct {\r
-  UINT8             *RendezvousFunnelAddress;\r
-  UINTN             ModeEntryOffset;\r
-  UINTN             RendezvousFunnelSize;\r
-  UINT8             *RelocateApLoopFuncAddress;\r
-  UINTN             RelocateApLoopFuncSize;\r
-  UINTN             ModeTransitionOffset;\r
-  UINTN             SwitchToRealSize;\r
-  UINTN             SwitchToRealOffset;\r
-  UINTN             SwitchToRealNoNxOffset;\r
-  UINTN             SwitchToRealPM16ModeOffset;\r
-  UINTN             SwitchToRealPM16ModeSize;\r
+  UINT8    *RendezvousFunnelAddress;\r
+  UINTN    ModeEntryOffset;\r
+  UINTN    RendezvousFunnelSize;\r
+  UINT8    *RelocateApLoopFuncAddress;\r
+  UINTN    RelocateApLoopFuncSize;\r
+  UINTN    ModeTransitionOffset;\r
+  UINTN    SwitchToRealSize;\r
+  UINTN    SwitchToRealOffset;\r
+  UINTN    SwitchToRealNoNxOffset;\r
+  UINTN    SwitchToRealPM16ModeOffset;\r
+  UINTN    SwitchToRealPM16ModeSize;\r
 } MP_ASSEMBLY_ADDRESS_MAP;\r
 \r
-typedef struct _CPU_MP_DATA  CPU_MP_DATA;\r
+typedef struct _CPU_MP_DATA CPU_MP_DATA;\r
 \r
 #pragma pack(1)\r
 \r
@@ -192,33 +192,33 @@ typedef struct _CPU_MP_DATA  CPU_MP_DATA;
 // into this structure are used in assembly code in this module\r
 //\r
 typedef struct {\r
-  UINTN                 StackStart;\r
-  UINTN                 StackSize;\r
-  UINTN                 CFunction;\r
-  IA32_DESCRIPTOR       GdtrProfile;\r
-  IA32_DESCRIPTOR       IdtrProfile;\r
-  UINTN                 BufferStart;\r
-  UINTN                 ModeOffset;\r
-  UINTN                 ApIndex;\r
-  UINTN                 CodeSegment;\r
-  UINTN                 DataSegment;\r
-  UINTN                 EnableExecuteDisable;\r
-  UINTN                 Cr3;\r
-  UINTN                 InitFlag;\r
-  CPU_INFO_IN_HOB       *CpuInfo;\r
-  UINTN                 NumApsExecuting;\r
-  CPU_MP_DATA           *CpuMpData;\r
-  UINTN                 InitializeFloatingPointUnitsAddress;\r
-  UINT32                ModeTransitionMemory;\r
-  UINT16                ModeTransitionSegment;\r
-  UINT32                ModeHighMemory;\r
-  UINT16                ModeHighSegment;\r
+  UINTN              StackStart;\r
+  UINTN              StackSize;\r
+  UINTN              CFunction;\r
+  IA32_DESCRIPTOR    GdtrProfile;\r
+  IA32_DESCRIPTOR    IdtrProfile;\r
+  UINTN              BufferStart;\r
+  UINTN              ModeOffset;\r
+  UINTN              ApIndex;\r
+  UINTN              CodeSegment;\r
+  UINTN              DataSegment;\r
+  UINTN              EnableExecuteDisable;\r
+  UINTN              Cr3;\r
+  UINTN              InitFlag;\r
+  CPU_INFO_IN_HOB    *CpuInfo;\r
+  UINTN              NumApsExecuting;\r
+  CPU_MP_DATA        *CpuMpData;\r
+  UINTN              InitializeFloatingPointUnitsAddress;\r
+  UINT32             ModeTransitionMemory;\r
+  UINT16             ModeTransitionSegment;\r
+  UINT32             ModeHighMemory;\r
+  UINT16             ModeHighSegment;\r
   //\r
   // Enable5LevelPaging indicates whether 5-level paging is enabled in long mode.\r
   //\r
-  BOOLEAN               Enable5LevelPaging;\r
-  BOOLEAN               SevEsIsEnabled;\r
-  UINTN                 GhcbBase;\r
+  BOOLEAN            Enable5LevelPaging;\r
+  BOOLEAN            SevEsIsEnabled;\r
+  UINTN              GhcbBase;\r
 } MP_CPU_EXCHANGE_INFO;\r
 \r
 #pragma pack()\r
@@ -227,55 +227,55 @@ typedef struct {
 // CPU MP Data save in memory\r
 //\r
 struct _CPU_MP_DATA {\r
-  UINT64                         CpuInfoInHob;\r
-  UINT32                         CpuCount;\r
-  UINT32                         BspNumber;\r
+  UINT64                           CpuInfoInHob;\r
+  UINT32                           CpuCount;\r
+  UINT32                           BspNumber;\r
   //\r
   // The above fields data will be passed from PEI to DXE\r
   // Please make sure the fields offset same in the different\r
   // architecture.\r
   //\r
-  SPIN_LOCK                      MpLock;\r
-  UINTN                          Buffer;\r
-  UINTN                          CpuApStackSize;\r
-  MP_ASSEMBLY_ADDRESS_MAP        AddressMap;\r
-  UINTN                          WakeupBuffer;\r
-  UINTN                          WakeupBufferHigh;\r
-  UINTN                          BackupBuffer;\r
-  UINTN                          BackupBufferSize;\r
-\r
-  volatile UINT32                FinishedCount;\r
-  UINT32                         RunningCount;\r
-  BOOLEAN                        SingleThread;\r
-  EFI_AP_PROCEDURE               Procedure;\r
-  VOID                           *ProcArguments;\r
-  BOOLEAN                        *Finished;\r
-  UINT64                         ExpectedTime;\r
-  UINT64                         CurrentTime;\r
-  UINT64                         TotalTime;\r
-  EFI_EVENT                      WaitEvent;\r
-  UINTN                          **FailedCpuList;\r
-\r
-  AP_INIT_STATE                  InitFlag;\r
-  BOOLEAN                        SwitchBspFlag;\r
-  UINTN                          NewBspNumber;\r
-  CPU_EXCHANGE_ROLE_INFO         BSPInfo;\r
-  CPU_EXCHANGE_ROLE_INFO         APInfo;\r
-  MTRR_SETTINGS                  MtrrTable;\r
-  UINT8                          ApLoopMode;\r
-  UINT8                          ApTargetCState;\r
-  UINT16                         PmCodeSegment;\r
-  UINT16                         Pm16CodeSegment;\r
-  CPU_AP_DATA                    *CpuData;\r
-  volatile MP_CPU_EXCHANGE_INFO  *MpCpuExchangeInfo;\r
-\r
-  UINT32                         CurrentTimerCount;\r
-  UINTN                          DivideValue;\r
-  UINT8                          Vector;\r
-  BOOLEAN                        PeriodicMode;\r
-  BOOLEAN                        TimerInterruptState;\r
-  UINT64                         MicrocodePatchAddress;\r
-  UINT64                         MicrocodePatchRegionSize;\r
+  SPIN_LOCK                        MpLock;\r
+  UINTN                            Buffer;\r
+  UINTN                            CpuApStackSize;\r
+  MP_ASSEMBLY_ADDRESS_MAP          AddressMap;\r
+  UINTN                            WakeupBuffer;\r
+  UINTN                            WakeupBufferHigh;\r
+  UINTN                            BackupBuffer;\r
+  UINTN                            BackupBufferSize;\r
+\r
+  volatile UINT32                  FinishedCount;\r
+  UINT32                           RunningCount;\r
+  BOOLEAN                          SingleThread;\r
+  EFI_AP_PROCEDURE                 Procedure;\r
+  VOID                             *ProcArguments;\r
+  BOOLEAN                          *Finished;\r
+  UINT64                           ExpectedTime;\r
+  UINT64                           CurrentTime;\r
+  UINT64                           TotalTime;\r
+  EFI_EVENT                        WaitEvent;\r
+  UINTN                            **FailedCpuList;\r
+\r
+  AP_INIT_STATE                    InitFlag;\r
+  BOOLEAN                          SwitchBspFlag;\r
+  UINTN                            NewBspNumber;\r
+  CPU_EXCHANGE_ROLE_INFO           BSPInfo;\r
+  CPU_EXCHANGE_ROLE_INFO           APInfo;\r
+  MTRR_SETTINGS                    MtrrTable;\r
+  UINT8                            ApLoopMode;\r
+  UINT8                            ApTargetCState;\r
+  UINT16                           PmCodeSegment;\r
+  UINT16                           Pm16CodeSegment;\r
+  CPU_AP_DATA                      *CpuData;\r
+  volatile MP_CPU_EXCHANGE_INFO    *MpCpuExchangeInfo;\r
+\r
+  UINT32                           CurrentTimerCount;\r
+  UINTN                            DivideValue;\r
+  UINT8                            Vector;\r
+  BOOLEAN                          PeriodicMode;\r
+  BOOLEAN                          TimerInterruptState;\r
+  UINT64                           MicrocodePatchAddress;\r
+  UINT64                           MicrocodePatchRegionSize;\r
 \r
   //\r
   // Whether need to use Init-Sipi-Sipi to wake up the APs.\r
@@ -284,25 +284,25 @@ struct _CPU_MP_DATA {
   // will be hardcode change to HLT mode by PiSmmCpuDxeSmm\r
   // driver.\r
   //\r
-  BOOLEAN                        WakeUpByInitSipiSipi;\r
+  BOOLEAN        WakeUpByInitSipiSipi;\r
 \r
-  BOOLEAN                        SevEsIsEnabled;\r
-  UINTN                          SevEsAPBuffer;\r
-  UINTN                          SevEsAPResetStackStart;\r
-  CPU_MP_DATA                    *NewCpuMpData;\r
+  BOOLEAN        SevEsIsEnabled;\r
+  UINTN          SevEsAPBuffer;\r
+  UINTN          SevEsAPResetStackStart;\r
+  CPU_MP_DATA    *NewCpuMpData;\r
 \r
-  UINT64                         GhcbBase;\r
+  UINT64         GhcbBase;\r
 };\r
 \r
-#define AP_SAFE_STACK_SIZE  128\r
-#define AP_RESET_STACK_SIZE AP_SAFE_STACK_SIZE\r
+#define AP_SAFE_STACK_SIZE   128\r
+#define AP_RESET_STACK_SIZE  AP_SAFE_STACK_SIZE\r
 \r
 #pragma pack(1)\r
 \r
 typedef struct {\r
-  UINT8   InsnBuffer[8];\r
-  UINT16  Rip;\r
-  UINT16  Segment;\r
+  UINT8     InsnBuffer[8];\r
+  UINT16    Rip;\r
+  UINT16    Segment;\r
 } SEV_ES_AP_JMP_FAR;\r
 \r
 #pragma pack()\r
@@ -322,14 +322,14 @@ typedef struct {
 **/\r
 typedef\r
 VOID\r
-(EFIAPI AP_RESET) (\r
+(EFIAPI AP_RESET)(\r
   IN UINTN    BufferStart,\r
   IN UINT16   Code16,\r
   IN UINT16   Code32,\r
   IN UINTN    StackStart\r
   );\r
 \r
-extern EFI_GUID mCpuInitMpLibHobGuid;\r
+extern EFI_GUID  mCpuInitMpLibHobGuid;\r
 \r
 /**\r
   Assembly code to place AP into safe loop mode.\r
@@ -347,7 +347,7 @@ extern EFI_GUID mCpuInitMpLibHobGuid;
 **/\r
 typedef\r
 VOID\r
-(EFIAPI * ASM_RELOCATE_AP_LOOP) (\r
+(EFIAPI *ASM_RELOCATE_AP_LOOP)(\r
   IN BOOLEAN                 MwaitSupport,\r
   IN UINTN                   ApTargetCState,\r
   IN UINTN                   PmCodeSegment,\r
@@ -367,7 +367,7 @@ VOID
 VOID\r
 EFIAPI\r
 AsmGetAddressMap (\r
-  OUT MP_ASSEMBLY_ADDRESS_MAP    *AddressMap\r
+  OUT MP_ASSEMBLY_ADDRESS_MAP  *AddressMap\r
   );\r
 \r
 /**\r
@@ -382,8 +382,8 @@ AsmGetAddressMap (
 VOID\r
 EFIAPI\r
 AsmExchangeRole (\r
-  IN CPU_EXCHANGE_ROLE_INFO    *MyInfo,\r
-  IN CPU_EXCHANGE_ROLE_INFO    *OthersInfo\r
+  IN CPU_EXCHANGE_ROLE_INFO  *MyInfo,\r
+  IN CPU_EXCHANGE_ROLE_INFO  *OthersInfo\r
   );\r
 \r
 /**\r
@@ -403,10 +403,9 @@ GetCpuMpData (
 **/\r
 VOID\r
 SaveCpuMpData (\r
-  IN CPU_MP_DATA   *CpuMpData\r
+  IN CPU_MP_DATA  *CpuMpData\r
   );\r
 \r
-\r
 /**\r
   Get available system memory below 1MB by specified size.\r
 \r
@@ -417,7 +416,7 @@ SaveCpuMpData (
 **/\r
 UINTN\r
 GetWakeupBuffer (\r
-  IN UINTN                WakeupBufferSize\r
+  IN UINTN  WakeupBufferSize\r
   );\r
 \r
 /**\r
@@ -434,7 +433,7 @@ GetWakeupBuffer (
 **/\r
 UINTN\r
 GetModeTransitionBuffer (\r
-  IN UINTN                BufferSize\r
+  IN UINTN  BufferSize\r
   );\r
 \r
 /**\r
@@ -463,12 +462,12 @@ GetSevEsAPMemory (
 **/\r
 VOID\r
 WakeUpAP (\r
-  IN CPU_MP_DATA               *CpuMpData,\r
-  IN BOOLEAN                   Broadcast,\r
-  IN UINTN                     ProcessorNumber,\r
-  IN EFI_AP_PROCEDURE          Procedure               OPTIONAL,\r
-  IN VOID                      *ProcedureArgument      OPTIONAL,\r
-  IN BOOLEAN                   WakeUpDisabledAps       OPTIONAL\r
+  IN CPU_MP_DATA       *CpuMpData,\r
+  IN BOOLEAN           Broadcast,\r
+  IN UINTN             ProcessorNumber,\r
+  IN EFI_AP_PROCEDURE  Procedure               OPTIONAL,\r
+  IN VOID              *ProcedureArgument      OPTIONAL,\r
+  IN BOOLEAN           WakeUpDisabledAps       OPTIONAL\r
   );\r
 \r
 /**\r
@@ -478,7 +477,7 @@ WakeUpAP (
 **/\r
 VOID\r
 InitMpGlobalData (\r
-  IN CPU_MP_DATA               *CpuMpData\r
+  IN CPU_MP_DATA  *CpuMpData\r
   );\r
 \r
 /**\r
@@ -515,13 +514,13 @@ InitMpGlobalData (
 **/\r
 EFI_STATUS\r
 StartupAllCPUsWorker (\r
-  IN  EFI_AP_PROCEDURE          Procedure,\r
-  IN  BOOLEAN                   SingleThread,\r
-  IN  BOOLEAN                   ExcludeBsp,\r
-  IN  EFI_EVENT                 WaitEvent               OPTIONAL,\r
-  IN  UINTN                     TimeoutInMicroseconds,\r
-  IN  VOID                      *ProcedureArgument      OPTIONAL,\r
-  OUT UINTN                     **FailedCpuList         OPTIONAL\r
+  IN  EFI_AP_PROCEDURE  Procedure,\r
+  IN  BOOLEAN           SingleThread,\r
+  IN  BOOLEAN           ExcludeBsp,\r
+  IN  EFI_EVENT         WaitEvent               OPTIONAL,\r
+  IN  UINTN             TimeoutInMicroseconds,\r
+  IN  VOID              *ProcedureArgument      OPTIONAL,\r
+  OUT UINTN             **FailedCpuList         OPTIONAL\r
   );\r
 \r
 /**\r
@@ -549,12 +548,12 @@ StartupAllCPUsWorker (
 **/\r
 EFI_STATUS\r
 StartupThisAPWorker (\r
-  IN  EFI_AP_PROCEDURE          Procedure,\r
-  IN  UINTN                     ProcessorNumber,\r
-  IN  EFI_EVENT                 WaitEvent               OPTIONAL,\r
-  IN  UINTN                     TimeoutInMicroseconds,\r
-  IN  VOID                      *ProcedureArgument      OPTIONAL,\r
-  OUT BOOLEAN                   *Finished               OPTIONAL\r
+  IN  EFI_AP_PROCEDURE  Procedure,\r
+  IN  UINTN             ProcessorNumber,\r
+  IN  EFI_EVENT         WaitEvent               OPTIONAL,\r
+  IN  UINTN             TimeoutInMicroseconds,\r
+  IN  VOID              *ProcedureArgument      OPTIONAL,\r
+  OUT BOOLEAN           *Finished               OPTIONAL\r
   );\r
 \r
 /**\r
@@ -570,8 +569,8 @@ StartupThisAPWorker (
 **/\r
 EFI_STATUS\r
 SwitchBSPWorker (\r
-  IN UINTN                     ProcessorNumber,\r
-  IN BOOLEAN                   EnableOldBSP\r
+  IN UINTN    ProcessorNumber,\r
+  IN BOOLEAN  EnableOldBSP\r
   );\r
 \r
 /**\r
@@ -590,9 +589,9 @@ SwitchBSPWorker (
 **/\r
 EFI_STATUS\r
 EnableDisableApWorker (\r
-  IN  UINTN                     ProcessorNumber,\r
-  IN  BOOLEAN                   EnableAP,\r
-  IN  UINT32                    *HealthFlag OPTIONAL\r
+  IN  UINTN    ProcessorNumber,\r
+  IN  BOOLEAN  EnableAP,\r
+  IN  UINT32   *HealthFlag OPTIONAL\r
   );\r
 \r
 /**\r
@@ -618,7 +617,7 @@ GetCpuMpDataFromGuidedHob (
 **/\r
 EFI_STATUS\r
 CheckThisAP (\r
-  IN UINTN        ProcessorNumber\r
+  IN UINTN  ProcessorNumber\r
   );\r
 \r
 /**\r
@@ -655,8 +654,8 @@ CheckAndUpdateApsStatus (
 **/\r
 VOID\r
 MicrocodeDetect (\r
-  IN CPU_MP_DATA             *CpuMpData,\r
-  IN UINTN                   ProcessorNumber\r
+  IN CPU_MP_DATA  *CpuMpData,\r
+  IN UINTN        ProcessorNumber\r
   );\r
 \r
 /**\r
@@ -666,7 +665,7 @@ MicrocodeDetect (
 **/\r
 VOID\r
 ShadowMicrocodeUpdatePatch (\r
-  IN OUT CPU_MP_DATA             *CpuMpData\r
+  IN OUT CPU_MP_DATA  *CpuMpData\r
   );\r
 \r
 /**\r
@@ -686,8 +685,8 @@ ShadowMicrocodeUpdatePatch (
 **/\r
 BOOLEAN\r
 GetMicrocodePatchInfoFromHob (\r
-  UINT64                         *Address,\r
-  UINT64                         *RegionSize\r
+  UINT64  *Address,\r
+  UINT64  *RegionSize\r
   );\r
 \r
 /**\r
@@ -721,8 +720,8 @@ EnableDebugAgent (
 **/\r
 EFI_STATUS\r
 GetProcessorNumber (\r
-  IN CPU_MP_DATA               *CpuMpData,\r
-  OUT UINTN                    *ProcessorNumber\r
+  IN CPU_MP_DATA  *CpuMpData,\r
+  OUT UINTN       *ProcessorNumber\r
   );\r
 \r
 /**\r
@@ -738,7 +737,7 @@ GetProcessorNumber (
 **/\r
 EFI_STATUS\r
 PlatformShadowMicrocode (\r
-  IN OUT CPU_MP_DATA             *CpuMpData\r
+  IN OUT CPU_MP_DATA  *CpuMpData\r
   );\r
 \r
 #endif\r

diff --git a/UefiCpuPkg/Library/MpInitLib/PeiMpLib.c b/UefiCpuPkg/Library/MpInitLib/PeiMpLib.c
index 90015c650c68127096ee338b37ac8429ac53d482..ab79360bb935eaaed47fe57e85e54a4d03756530 100644 (file)
--- a/UefiCpuPkg/Library/MpInitLib/PeiMpLib.c
+++ b/UefiCpuPkg/Library/MpInitLib/PeiMpLib.c
@@ -11,7 +11,7 @@
 #include <Guid/S3SmmInitDone.h>\r
 #include <Ppi/ShadowMicrocode.h>\r
 \r
-STATIC UINT64 mSevEsPeiWakeupBuffer = BASE_1MB;\r
+STATIC UINT64  mSevEsPeiWakeupBuffer = BASE_1MB;\r
 \r
 /**\r
   S3 SMM Init Done notification function.\r
@@ -26,16 +26,15 @@ STATIC UINT64 mSevEsPeiWakeupBuffer = BASE_1MB;
 EFI_STATUS\r
 EFIAPI\r
 NotifyOnS3SmmInitDonePpi (\r
-  IN  EFI_PEI_SERVICES                              **PeiServices,\r
-  IN  EFI_PEI_NOTIFY_DESCRIPTOR                     *NotifyDesc,\r
-  IN  VOID                                          *InvokePpi\r
+  IN  EFI_PEI_SERVICES           **PeiServices,\r
+  IN  EFI_PEI_NOTIFY_DESCRIPTOR  *NotifyDesc,\r
+  IN  VOID                       *InvokePpi\r
   );\r
 \r
-\r
 //\r
 // Global function\r
 //\r
-EFI_PEI_NOTIFY_DESCRIPTOR        mS3SmmInitDoneNotifyDesc = {\r
+EFI_PEI_NOTIFY_DESCRIPTOR  mS3SmmInitDoneNotifyDesc = {\r
   EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,\r
   &gEdkiiS3SmmInitDoneGuid,\r
   NotifyOnS3SmmInitDonePpi\r
@@ -54,12 +53,12 @@ EFI_PEI_NOTIFY_DESCRIPTOR        mS3SmmInitDoneNotifyDesc = {
 EFI_STATUS\r
 EFIAPI\r
 NotifyOnS3SmmInitDonePpi (\r
-  IN  EFI_PEI_SERVICES                              **PeiServices,\r
-  IN  EFI_PEI_NOTIFY_DESCRIPTOR                     *NotifyDesc,\r
-  IN  VOID                                          *InvokePpi\r
+  IN  EFI_PEI_SERVICES           **PeiServices,\r
+  IN  EFI_PEI_NOTIFY_DESCRIPTOR  *NotifyDesc,\r
+  IN  VOID                       *InvokePpi\r
   )\r
 {\r
-  CPU_MP_DATA     *CpuMpData;\r
+  CPU_MP_DATA  *CpuMpData;\r
 \r
   CpuMpData = GetCpuMpData ();\r
 \r
@@ -76,7 +75,6 @@ NotifyOnS3SmmInitDonePpi (
   return EFI_SUCCESS;\r
 }\r
 \r
-\r
 /**\r
   Enable Debug Agent to support source debugging on AP function.\r
 \r
@@ -110,8 +108,9 @@ GetCpuMpData (
     ASSERT (CpuMpData != NULL);\r
   } else {\r
     AsmReadIdtr (&Idtr);\r
-    CpuMpData = (CPU_MP_DATA *) (Idtr.Base + Idtr.Limit + 1);\r
+    CpuMpData = (CPU_MP_DATA *)(Idtr.Base + Idtr.Limit + 1);\r
   }\r
+\r
   return CpuMpData;\r
 }\r
 \r
@@ -122,17 +121,18 @@ GetCpuMpData (
 **/\r
 VOID\r
 SaveCpuMpData (\r
-  IN CPU_MP_DATA   *CpuMpData\r
+  IN CPU_MP_DATA  *CpuMpData\r
   )\r
 {\r
-  UINT64           Data64;\r
+  UINT64  Data64;\r
+\r
   //\r
   // Build location of CPU MP DATA buffer in HOB\r
   //\r
-  Data64 = (UINT64) (UINTN) CpuMpData;\r
+  Data64 = (UINT64)(UINTN)CpuMpData;\r
   BuildGuidDataHob (\r
     &mCpuInitMpLibHobGuid,\r
-    (VOID *) &Data64,\r
+    (VOID *)&Data64,\r
     sizeof (UINT64)\r
     );\r
 }\r
@@ -148,15 +148,15 @@ SaveCpuMpData (
 **/\r
 BOOLEAN\r
 CheckOverlapWithAllocatedBuffer (\r
-  IN UINT64               WakeupBufferStart,\r
-  IN UINT64               WakeupBufferEnd\r
+  IN UINT64  WakeupBufferStart,\r
+  IN UINT64  WakeupBufferEnd\r
   )\r
 {\r
-  EFI_PEI_HOB_POINTERS      Hob;\r
-  EFI_HOB_MEMORY_ALLOCATION *MemoryHob;\r
-  BOOLEAN                   Overlapped;\r
-  UINT64                    MemoryStart;\r
-  UINT64                    MemoryEnd;\r
+  EFI_PEI_HOB_POINTERS       Hob;\r
+  EFI_HOB_MEMORY_ALLOCATION  *MemoryHob;\r
+  BOOLEAN                    Overlapped;\r
+  UINT64                     MemoryStart;\r
+  UINT64                     MemoryEnd;\r
 \r
   Overlapped = FALSE;\r
   //\r
@@ -176,8 +176,10 @@ CheckOverlapWithAllocatedBuffer (
         break;\r
       }\r
     }\r
+\r
     Hob.Raw = GET_NEXT_HOB (Hob);\r
   }\r
+\r
   return Overlapped;\r
 }\r
 \r
@@ -191,12 +193,12 @@ CheckOverlapWithAllocatedBuffer (
 **/\r
 UINTN\r
 GetWakeupBuffer (\r
-  IN UINTN                WakeupBufferSize\r
+  IN UINTN  WakeupBufferSize\r
   )\r
 {\r
-  EFI_PEI_HOB_POINTERS    Hob;\r
-  UINT64                  WakeupBufferStart;\r
-  UINT64                  WakeupBufferEnd;\r
+  EFI_PEI_HOB_POINTERS  Hob;\r
+  UINT64                WakeupBufferStart;\r
+  UINT64                WakeupBufferEnd;\r
 \r
   WakeupBufferSize = (WakeupBufferSize + SIZE_4KB - 1) & ~(SIZE_4KB - 1);\r
 \r
@@ -216,14 +218,16 @@ GetWakeupBuffer (
             (EFI_RESOURCE_ATTRIBUTE_READ_PROTECTED |\r
              EFI_RESOURCE_ATTRIBUTE_WRITE_PROTECTED |\r
              EFI_RESOURCE_ATTRIBUTE_EXECUTION_PROTECTED\r
-             )) == 0)\r
-           ) {\r
+            )) == 0)\r
+          )\r
+      {\r
         //\r
         // Need memory under 1MB to be collected here\r
         //\r
         WakeupBufferEnd = Hob.ResourceDescriptor->PhysicalStart + Hob.ResourceDescriptor->ResourceLength;\r
         if (PcdGetBool (PcdSevEsIsEnabled) &&\r
-            WakeupBufferEnd > mSevEsPeiWakeupBuffer) {\r
+            (WakeupBufferEnd > mSevEsPeiWakeupBuffer))\r
+        {\r
           //\r
           // SEV-ES Wakeup buffer should be under 1MB and under any previous one\r
           //\r
@@ -234,6 +238,7 @@ GetWakeupBuffer (
           //\r
           WakeupBufferEnd = BASE_1MB;\r
         }\r
+\r
         while (WakeupBufferEnd > WakeupBufferSize) {\r
           //\r
           // Wakeup buffer should be aligned on 4KB\r
@@ -242,6 +247,7 @@ GetWakeupBuffer (
           if (WakeupBufferStart < Hob.ResourceDescriptor->PhysicalStart) {\r
             break;\r
           }\r
+\r
           if (CheckOverlapWithAllocatedBuffer (WakeupBufferStart, WakeupBufferEnd)) {\r
             //\r
             // If this range is overlapped with existing allocated buffer, skip it\r
@@ -250,8 +256,13 @@ GetWakeupBuffer (
             WakeupBufferEnd -= WakeupBufferSize;\r
             continue;\r
           }\r
-          DEBUG ((DEBUG_INFO, "WakeupBufferStart = %x, WakeupBufferSize = %x\n",\r
-                               WakeupBufferStart, WakeupBufferSize));\r
+\r
+          DEBUG ((\r
+            DEBUG_INFO,\r
+            "WakeupBufferStart = %x, WakeupBufferSize = %x\n",\r
+            WakeupBufferStart,\r
+            WakeupBufferSize\r
+            ));\r
 \r
           if (PcdGetBool (PcdSevEsIsEnabled)) {\r
             //\r
@@ -265,13 +276,14 @@ GetWakeupBuffer (
         }\r
       }\r
     }\r
+\r
     //\r
     // Find the next HOB\r
     //\r
     Hob.Raw = GET_NEXT_HOB (Hob);\r
   }\r
 \r
-  return (UINTN) -1;\r
+  return (UINTN)-1;\r
 }\r
 \r
 /**\r
@@ -288,7 +300,7 @@ GetWakeupBuffer (
 **/\r
 UINTN\r
 GetModeTransitionBuffer (\r
-  IN UINTN                BufferSize\r
+  IN UINTN  BufferSize\r
   )\r
 {\r
   //\r
@@ -336,17 +348,17 @@ CheckAndUpdateApsStatus (
 **/\r
 VOID\r
 BuildMicrocodeCacheHob (\r
-  IN CPU_MP_DATA    *CpuMpData\r
+  IN CPU_MP_DATA  *CpuMpData\r
   )\r
 {\r
-  EDKII_MICROCODE_PATCH_HOB    *MicrocodeHob;\r
-  UINTN                        HobDataLength;\r
-  UINT32                       Index;\r
+  EDKII_MICROCODE_PATCH_HOB  *MicrocodeHob;\r
+  UINTN                      HobDataLength;\r
+  UINT32                     Index;\r
 \r
   HobDataLength = sizeof (EDKII_MICROCODE_PATCH_HOB) +\r
                   sizeof (UINT64) * CpuMpData->CpuCount;\r
 \r
-  MicrocodeHob  = AllocatePool (HobDataLength);\r
+  MicrocodeHob = AllocatePool (HobDataLength);\r
   if (MicrocodeHob == NULL) {\r
     ASSERT (FALSE);\r
     return;\r
@@ -387,7 +399,7 @@ BuildMicrocodeCacheHob (
 **/\r
 VOID\r
 InitMpGlobalData (\r
-  IN CPU_MP_DATA               *CpuMpData\r
+  IN CPU_MP_DATA  *CpuMpData\r
   )\r
 {\r
   EFI_STATUS  Status;\r
@@ -480,12 +492,12 @@ InitMpGlobalData (
 EFI_STATUS\r
 EFIAPI\r
 MpInitLibStartupAllAPs (\r
-  IN  EFI_AP_PROCEDURE          Procedure,\r
-  IN  BOOLEAN                   SingleThread,\r
-  IN  EFI_EVENT                 WaitEvent               OPTIONAL,\r
-  IN  UINTN                     TimeoutInMicroseconds,\r
-  IN  VOID                      *ProcedureArgument      OPTIONAL,\r
-  OUT UINTN                     **FailedCpuList         OPTIONAL\r
+  IN  EFI_AP_PROCEDURE  Procedure,\r
+  IN  BOOLEAN           SingleThread,\r
+  IN  EFI_EVENT         WaitEvent               OPTIONAL,\r
+  IN  UINTN             TimeoutInMicroseconds,\r
+  IN  VOID              *ProcedureArgument      OPTIONAL,\r
+  OUT UINTN             **FailedCpuList         OPTIONAL\r
   )\r
 {\r
   if (WaitEvent != NULL) {\r
@@ -577,12 +589,12 @@ MpInitLibStartupAllAPs (
 EFI_STATUS\r
 EFIAPI\r
 MpInitLibStartupThisAP (\r
-  IN  EFI_AP_PROCEDURE          Procedure,\r
-  IN  UINTN                     ProcessorNumber,\r
-  IN  EFI_EVENT                 WaitEvent               OPTIONAL,\r
-  IN  UINTN                     TimeoutInMicroseconds,\r
-  IN  VOID                      *ProcedureArgument      OPTIONAL,\r
-  OUT BOOLEAN                   *Finished               OPTIONAL\r
+  IN  EFI_AP_PROCEDURE  Procedure,\r
+  IN  UINTN             ProcessorNumber,\r
+  IN  EFI_EVENT         WaitEvent               OPTIONAL,\r
+  IN  UINTN             TimeoutInMicroseconds,\r
+  IN  VOID              *ProcedureArgument      OPTIONAL,\r
+  OUT BOOLEAN           *Finished               OPTIONAL\r
   )\r
 {\r
   if (WaitEvent != NULL) {\r
@@ -628,8 +640,8 @@ MpInitLibStartupThisAP (
 EFI_STATUS\r
 EFIAPI\r
 MpInitLibSwitchBSP (\r
-  IN UINTN                     ProcessorNumber,\r
-  IN  BOOLEAN                  EnableOldBSP\r
+  IN UINTN     ProcessorNumber,\r
+  IN  BOOLEAN  EnableOldBSP\r
   )\r
 {\r
   return SwitchBSPWorker (ProcessorNumber, EnableOldBSP);\r
@@ -668,9 +680,9 @@ MpInitLibSwitchBSP (
 EFI_STATUS\r
 EFIAPI\r
 MpInitLibEnableDisableAP (\r
-  IN  UINTN                     ProcessorNumber,\r
-  IN  BOOLEAN                   EnableAP,\r
-  IN  UINT32                    *HealthFlag OPTIONAL\r
+  IN  UINTN    ProcessorNumber,\r
+  IN  BOOLEAN  EnableAP,\r
+  IN  UINT32   *HealthFlag OPTIONAL\r
   )\r
 {\r
   return EnableDisableApWorker (ProcessorNumber, EnableAP, HealthFlag);\r
@@ -689,29 +701,29 @@ MpInitLibEnableDisableAP (
 **/\r
 EFI_STATUS\r
 PlatformShadowMicrocode (\r
-  IN OUT CPU_MP_DATA             *CpuMpData\r
+  IN OUT CPU_MP_DATA  *CpuMpData\r
   )\r
 {\r
-  EFI_STATUS                         Status;\r
-  EDKII_PEI_SHADOW_MICROCODE_PPI     *ShadowMicrocodePpi;\r
-  UINTN                              CpuCount;\r
-  EDKII_PEI_MICROCODE_CPU_ID         *MicrocodeCpuId;\r
-  UINTN                              Index;\r
-  UINTN                              BufferSize;\r
-  VOID                               *Buffer;\r
+  EFI_STATUS                      Status;\r
+  EDKII_PEI_SHADOW_MICROCODE_PPI  *ShadowMicrocodePpi;\r
+  UINTN                           CpuCount;\r
+  EDKII_PEI_MICROCODE_CPU_ID      *MicrocodeCpuId;\r
+  UINTN                           Index;\r
+  UINTN                           BufferSize;\r
+  VOID                            *Buffer;\r
 \r
   Status = PeiServicesLocatePpi (\r
              &gEdkiiPeiShadowMicrocodePpiGuid,\r
              0,\r
              NULL,\r
-             (VOID **) &ShadowMicrocodePpi\r
+             (VOID **)&ShadowMicrocodePpi\r
              );\r
   if (EFI_ERROR (Status)) {\r
     return EFI_UNSUPPORTED;\r
   }\r
 \r
-  CpuCount = CpuMpData->CpuCount;\r
-  MicrocodeCpuId = (EDKII_PEI_MICROCODE_CPU_ID *) AllocateZeroPool (sizeof (EDKII_PEI_MICROCODE_CPU_ID) * CpuCount);\r
+  CpuCount       = CpuMpData->CpuCount;\r
+  MicrocodeCpuId = (EDKII_PEI_MICROCODE_CPU_ID *)AllocateZeroPool (sizeof (EDKII_PEI_MICROCODE_CPU_ID) * CpuCount);\r
   if (MicrocodeCpuId == NULL) {\r
     return EFI_OUT_OF_RESOURCES;\r
   }\r
@@ -722,24 +734,26 @@ PlatformShadowMicrocode (
   }\r
 \r
   Status = ShadowMicrocodePpi->ShadowMicrocode (\r
-             ShadowMicrocodePpi,\r
-             CpuCount,\r
-             MicrocodeCpuId,\r
-             &BufferSize,\r
-             &Buffer\r
-             );\r
+                                 ShadowMicrocodePpi,\r
+                                 CpuCount,\r
+                                 MicrocodeCpuId,\r
+                                 &BufferSize,\r
+                                 &Buffer\r
+                                 );\r
   FreePool (MicrocodeCpuId);\r
   if (EFI_ERROR (Status)) {\r
     return EFI_NOT_FOUND;\r
   }\r
 \r
-  CpuMpData->MicrocodePatchAddress    = (UINTN) Buffer;\r
+  CpuMpData->MicrocodePatchAddress    = (UINTN)Buffer;\r
   CpuMpData->MicrocodePatchRegionSize = BufferSize;\r
 \r
   DEBUG ((\r
     DEBUG_INFO,\r
     "%a: Required microcode patches have been loaded at 0x%lx, with size 0x%lx.\n",\r
-    __FUNCTION__, CpuMpData->MicrocodePatchAddress, CpuMpData->MicrocodePatchRegionSize\r
+    __FUNCTION__,\r
+    CpuMpData->MicrocodePatchAddress,\r
+    CpuMpData->MicrocodePatchRegionSize\r
     ));\r
 \r
   return EFI_SUCCESS;\r

diff --git a/UefiCpuPkg/Library/MpInitLibUp/MpInitLibUp.c b/UefiCpuPkg/Library/MpInitLibUp/MpInitLibUp.c
index 7a461af9b1cef6777a5ef49c31bd40d4154db36e..86f9fbf90366a42da8e986461fb9d879ab0491ee 100644 (file)
--- a/UefiCpuPkg/Library/MpInitLibUp/MpInitLibUp.c
+++ b/UefiCpuPkg/Library/MpInitLibUp/MpInitLibUp.c
@@ -63,8 +63,8 @@ MpInitLibInitialize (
 EFI_STATUS\r
 EFIAPI\r
 MpInitLibGetNumberOfProcessors (\r
-  OUT UINTN                     *NumberOfProcessors        OPTIONAL,\r
-  OUT UINTN                     *NumberOfEnabledProcessors OPTIONAL\r
+  OUT UINTN  *NumberOfProcessors        OPTIONAL,\r
+  OUT UINTN  *NumberOfEnabledProcessors OPTIONAL\r
   )\r
 {\r
   *NumberOfProcessors        = 1;\r
@@ -103,13 +103,15 @@ MpInitLibGetProcessorInfo (
   if (ProcessorInfoBuffer == NULL) {\r
     return EFI_INVALID_PARAMETER;\r
   }\r
+\r
   if (ProcessorNumber != 0) {\r
     return EFI_NOT_FOUND;\r
   }\r
-  ProcessorInfoBuffer->ProcessorId      = 0;\r
-  ProcessorInfoBuffer->StatusFlag       = PROCESSOR_AS_BSP_BIT  |\r
-                                          PROCESSOR_ENABLED_BIT |\r
-                                          PROCESSOR_HEALTH_STATUS_BIT;\r
+\r
+  ProcessorInfoBuffer->ProcessorId = 0;\r
+  ProcessorInfoBuffer->StatusFlag  = PROCESSOR_AS_BSP_BIT  |\r
+                                     PROCESSOR_ENABLED_BIT |\r
+                                     PROCESSOR_HEALTH_STATUS_BIT;\r
   ProcessorInfoBuffer->Location.Package = 0;\r
   ProcessorInfoBuffer->Location.Core    = 0;\r
   ProcessorInfoBuffer->Location.Thread  = 0;\r
@@ -117,12 +119,13 @@ MpInitLibGetProcessorInfo (
     GuidHob = GetFirstGuidHob (&gEfiSecPlatformInformationPpiGuid);\r
     if (GuidHob != NULL) {\r
       SecPlatformInformation = GET_GUID_HOB_DATA (GuidHob);\r
-      HealthData->Uint32 = SecPlatformInformation->IA32HealthFlags.Uint32;\r
+      HealthData->Uint32     = SecPlatformInformation->IA32HealthFlags.Uint32;\r
     } else {\r
       DEBUG ((DEBUG_INFO, "Does not find any HOB stored CPU BIST information!\n"));\r
       HealthData->Uint32 = 0;\r
     }\r
   }\r
+\r
   return EFI_SUCCESS;\r
 }\r
 \r
@@ -204,12 +207,12 @@ MpInitLibGetProcessorInfo (
 EFI_STATUS\r
 EFIAPI\r
 MpInitLibStartupAllAPs (\r
-  IN  EFI_AP_PROCEDURE          Procedure,\r
-  IN  BOOLEAN                   SingleThread,\r
-  IN  EFI_EVENT                 WaitEvent               OPTIONAL,\r
-  IN  UINTN                     TimeoutInMicroseconds,\r
-  IN  VOID                      *ProcedureArgument      OPTIONAL,\r
-  OUT UINTN                     **FailedCpuList         OPTIONAL\r
+  IN  EFI_AP_PROCEDURE  Procedure,\r
+  IN  BOOLEAN           SingleThread,\r
+  IN  EFI_EVENT         WaitEvent               OPTIONAL,\r
+  IN  UINTN             TimeoutInMicroseconds,\r
+  IN  VOID              *ProcedureArgument      OPTIONAL,\r
+  OUT UINTN             **FailedCpuList         OPTIONAL\r
   )\r
 {\r
   return EFI_NOT_STARTED;\r
@@ -289,12 +292,12 @@ MpInitLibStartupAllAPs (
 EFI_STATUS\r
 EFIAPI\r
 MpInitLibStartupThisAP (\r
-  IN  EFI_AP_PROCEDURE          Procedure,\r
-  IN  UINTN                     ProcessorNumber,\r
-  IN  EFI_EVENT                 WaitEvent               OPTIONAL,\r
-  IN  UINTN                     TimeoutInMicroseconds,\r
-  IN  VOID                      *ProcedureArgument      OPTIONAL,\r
-  OUT BOOLEAN                   *Finished               OPTIONAL\r
+  IN  EFI_AP_PROCEDURE  Procedure,\r
+  IN  UINTN             ProcessorNumber,\r
+  IN  EFI_EVENT         WaitEvent               OPTIONAL,\r
+  IN  UINTN             TimeoutInMicroseconds,\r
+  IN  VOID              *ProcedureArgument      OPTIONAL,\r
+  OUT BOOLEAN           *Finished               OPTIONAL\r
   )\r
 {\r
   return EFI_INVALID_PARAMETER;\r
@@ -329,8 +332,8 @@ MpInitLibStartupThisAP (
 EFI_STATUS\r
 EFIAPI\r
 MpInitLibSwitchBSP (\r
-  IN UINTN                     ProcessorNumber,\r
-  IN BOOLEAN                   EnableOldBSP\r
+  IN UINTN    ProcessorNumber,\r
+  IN BOOLEAN  EnableOldBSP\r
   )\r
 {\r
   return EFI_UNSUPPORTED;\r
@@ -369,9 +372,9 @@ MpInitLibSwitchBSP (
 EFI_STATUS\r
 EFIAPI\r
 MpInitLibEnableDisableAP (\r
-  IN  UINTN                     ProcessorNumber,\r
-  IN  BOOLEAN                   EnableAP,\r
-  IN  UINT32                    *HealthFlag OPTIONAL\r
+  IN  UINTN    ProcessorNumber,\r
+  IN  BOOLEAN  EnableAP,\r
+  IN  UINT32   *HealthFlag OPTIONAL\r
   )\r
 {\r
   return EFI_UNSUPPORTED;\r
@@ -396,12 +399,13 @@ MpInitLibEnableDisableAP (
 EFI_STATUS\r
 EFIAPI\r
 MpInitLibWhoAmI (\r
-  OUT UINTN                    *ProcessorNumber\r
+  OUT UINTN  *ProcessorNumber\r
   )\r
 {\r
   if (ProcessorNumber == NULL) {\r
     return EFI_INVALID_PARAMETER;\r
   }\r
+\r
   *ProcessorNumber = 0;\r
   return EFI_SUCCESS;\r
 }\r
@@ -427,9 +431,9 @@ MpInitLibWhoAmI (
 EFI_STATUS\r
 EFIAPI\r
 MpInitLibStartupAllCPUs (\r
-  IN  EFI_AP_PROCEDURE          Procedure,\r
-  IN  UINTN                     TimeoutInMicroseconds,\r
-  IN  VOID                      *ProcedureArgument      OPTIONAL\r
+  IN  EFI_AP_PROCEDURE  Procedure,\r
+  IN  UINTN             TimeoutInMicroseconds,\r
+  IN  VOID              *ProcedureArgument      OPTIONAL\r
   )\r
 {\r
   if (Procedure == NULL) {\r

diff --git a/UefiCpuPkg/Library/MtrrLib/MtrrLib.c b/UefiCpuPkg/Library/MtrrLib/MtrrLib.c
index 805a2f8d2145135e74fc5008d3cfd9a9f4864a6b..e5c862c83d61cb76bcb485d7008051fc55c7b82f 100644 (file)
--- a/UefiCpuPkg/Library/MtrrLib/MtrrLib.c
+++ b/UefiCpuPkg/Library/MtrrLib/MtrrLib.c
@@ -20,35 +20,35 @@
 #include <Library/BaseMemoryLib.h>\r
 #include <Library/DebugLib.h>\r
 \r
-#define OR_SEED      0x0101010101010101ull\r
-#define CLEAR_SEED   0xFFFFFFFFFFFFFFFFull\r
-#define MAX_WEIGHT   MAX_UINT8\r
-#define SCRATCH_BUFFER_SIZE           (4 * SIZE_4KB)\r
-#define MTRR_LIB_ASSERT_ALIGNED(B, L) ASSERT ((B & ~(L - 1)) == B);\r
+#define OR_SEED              0x0101010101010101ull\r
+#define CLEAR_SEED           0xFFFFFFFFFFFFFFFFull\r
+#define MAX_WEIGHT           MAX_UINT8\r
+#define SCRATCH_BUFFER_SIZE  (4 * SIZE_4KB)\r
+#define MTRR_LIB_ASSERT_ALIGNED(B, L)  ASSERT ((B & ~(L - 1)) == B);\r
 \r
-#define M(x,y) ((x) * VertexCount + (y))\r
-#define O(x,y) ((y) * VertexCount + (x))\r
+#define M(x, y)  ((x) * VertexCount + (y))\r
+#define O(x, y)  ((y) * VertexCount + (x))\r
 \r
 //\r
 // Context to save and restore when MTRRs are programmed\r
 //\r
 typedef struct {\r
-  UINTN    Cr4;\r
-  BOOLEAN  InterruptState;\r
+  UINTN      Cr4;\r
+  BOOLEAN    InterruptState;\r
 } MTRR_CONTEXT;\r
 \r
 typedef struct {\r
-  UINT64                 Address;\r
-  UINT64                 Alignment;\r
-  UINT64                 Length;\r
-  MTRR_MEMORY_CACHE_TYPE Type : 7;\r
+  UINT64                    Address;\r
+  UINT64                    Alignment;\r
+  UINT64                    Length;\r
+  MTRR_MEMORY_CACHE_TYPE    Type    : 7;\r
 \r
   //\r
   // Temprary use for calculating the best MTRR settings.\r
   //\r
-  BOOLEAN                Visited : 1;\r
-  UINT8                  Weight;\r
-  UINT16                 Previous;\r
+  BOOLEAN                   Visited : 1;\r
+  UINT8                     Weight;\r
+  UINT16                    Previous;\r
 } MTRR_LIB_ADDRESS;\r
 \r
 //\r
@@ -115,7 +115,7 @@ CONST FIXED_MTRR  mMtrrLibFixedMtrrTable[] = {
 //\r
 // Lookup table used to print MTRRs\r
 //\r
-GLOBAL_REMOVE_IF_UNREFERENCED CONST CHAR8 *mMtrrMemoryCacheTypeShortName[] = {\r
+GLOBAL_REMOVE_IF_UNREFERENCED CONST CHAR8  *mMtrrMemoryCacheTypeShortName[] = {\r
   "UC",  // CacheUncacheable\r
   "WC",  // CacheWriteCombining\r
   "R*",  // Invalid\r
@@ -126,7 +126,6 @@ GLOBAL_REMOVE_IF_UNREFERENCED CONST CHAR8 *mMtrrMemoryCacheTypeShortName[] = {
   "R*"   // Invalid\r
 };\r
 \r
-\r
 /**\r
   Worker function prints all MTRRs for debugging.\r
 \r
@@ -138,7 +137,7 @@ GLOBAL_REMOVE_IF_UNREFERENCED CONST CHAR8 *mMtrrMemoryCacheTypeShortName[] = {
 **/\r
 VOID\r
 MtrrDebugPrintAllMtrrsWorker (\r
-  IN MTRR_SETTINGS    *MtrrSetting\r
+  IN MTRR_SETTINGS  *MtrrSetting\r
   );\r
 \r
 /**\r
@@ -152,10 +151,10 @@ GetVariableMtrrCountWorker (
   VOID\r
   )\r
 {\r
-  MSR_IA32_MTRRCAP_REGISTER MtrrCap;\r
+  MSR_IA32_MTRRCAP_REGISTER  MtrrCap;\r
 \r
   MtrrCap.Uint64 = AsmReadMsr64 (MSR_IA32_MTRRCAP);\r
-  ASSERT (MtrrCap.Bits.VCNT <= ARRAY_SIZE (((MTRR_VARIABLE_SETTINGS *) 0)->Mtrr));\r
+  ASSERT (MtrrCap.Bits.VCNT <= ARRAY_SIZE (((MTRR_VARIABLE_SETTINGS *)0)->Mtrr));\r
   return MtrrCap.Bits.VCNT;\r
 }\r
 \r
@@ -174,6 +173,7 @@ GetVariableMtrrCount (
   if (!IsMtrrSupported ()) {\r
     return 0;\r
   }\r
+\r
   return GetVariableMtrrCountWorker ();\r
 }\r
 \r
@@ -191,7 +191,7 @@ GetFirmwareVariableMtrrCountWorker (
   UINT32  VariableMtrrCount;\r
   UINT32  ReservedMtrrNumber;\r
 \r
-  VariableMtrrCount = GetVariableMtrrCountWorker ();\r
+  VariableMtrrCount  = GetVariableMtrrCountWorker ();\r
   ReservedMtrrNumber = PcdGet32 (PcdCpuNumberOfReservedVariableMtrrs);\r
   if (VariableMtrrCount < ReservedMtrrNumber) {\r
     return 0;\r
@@ -215,6 +215,7 @@ GetFirmwareVariableMtrrCount (
   if (!IsMtrrSupported ()) {\r
     return 0;\r
   }\r
+\r
   return GetFirmwareVariableMtrrCountWorker ();\r
 }\r
 \r
@@ -232,10 +233,10 @@ GetFirmwareVariableMtrrCount (
 **/\r
 MTRR_MEMORY_CACHE_TYPE\r
 MtrrGetDefaultMemoryTypeWorker (\r
-  IN MTRR_SETTINGS      *MtrrSetting\r
+  IN MTRR_SETTINGS  *MtrrSetting\r
   )\r
 {\r
-  MSR_IA32_MTRR_DEF_TYPE_REGISTER DefType;\r
+  MSR_IA32_MTRR_DEF_TYPE_REGISTER  DefType;\r
 \r
   if (MtrrSetting == NULL) {\r
     DefType.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_DEF_TYPE);\r
@@ -243,10 +244,9 @@ MtrrGetDefaultMemoryTypeWorker (
     DefType.Uint64 = MtrrSetting->MtrrDefType;\r
   }\r
 \r
-  return (MTRR_MEMORY_CACHE_TYPE) DefType.Bits.Type;\r
+  return (MTRR_MEMORY_CACHE_TYPE)DefType.Bits.Type;\r
 }\r
 \r
-\r
 /**\r
   Returns the default MTRR cache type for the system.\r
 \r
@@ -262,6 +262,7 @@ MtrrGetDefaultMemoryType (
   if (!IsMtrrSupported ()) {\r
     return CacheUncacheable;\r
   }\r
+\r
   return MtrrGetDefaultMemoryTypeWorker (NULL);\r
 }\r
 \r
@@ -280,10 +281,11 @@ MtrrLibPreMtrrChange (
   )\r
 {\r
   MSR_IA32_MTRR_DEF_TYPE_REGISTER  DefType;\r
+\r
   //\r
   // Disable interrupts and save current interrupt state\r
   //\r
-  MtrrContext->InterruptState = SaveAndDisableInterrupts();\r
+  MtrrContext->InterruptState = SaveAndDisableInterrupts ();\r
 \r
   //\r
   // Enter no fill cache mode, CD=1(Bit30), NW=0 (Bit29)\r
@@ -359,11 +361,12 @@ MtrrLibPostMtrrChange (
   )\r
 {\r
   MSR_IA32_MTRR_DEF_TYPE_REGISTER  DefType;\r
+\r
   //\r
   // Enable Cache MTRR\r
   //\r
-  DefType.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_DEF_TYPE);\r
-  DefType.Bits.E = 1;\r
+  DefType.Uint64  = AsmReadMsr64 (MSR_IA32_MTRR_DEF_TYPE);\r
+  DefType.Bits.E  = 1;\r
   DefType.Bits.FE = 1;\r
   AsmWriteMsr64 (MSR_IA32_MTRR_DEF_TYPE, DefType.Uint64);\r
 \r
@@ -378,22 +381,21 @@ MtrrLibPostMtrrChange (
   @retval The pointer of FixedSettings\r
 \r
 **/\r
-MTRR_FIXED_SETTINGS*\r
+MTRR_FIXED_SETTINGS *\r
 MtrrGetFixedMtrrWorker (\r
-  OUT MTRR_FIXED_SETTINGS         *FixedSettings\r
+  OUT MTRR_FIXED_SETTINGS  *FixedSettings\r
   )\r
 {\r
   UINT32  Index;\r
 \r
   for (Index = 0; Index < MTRR_NUMBER_OF_FIXED_MTRR; Index++) {\r
-      FixedSettings->Mtrr[Index] =\r
-        AsmReadMsr64 (mMtrrLibFixedMtrrTable[Index].Msr);\r
+    FixedSettings->Mtrr[Index] =\r
+      AsmReadMsr64 (mMtrrLibFixedMtrrTable[Index].Msr);\r
   }\r
 \r
   return FixedSettings;\r
 }\r
 \r
-\r
 /**\r
   This function gets the content in fixed MTRRs\r
 \r
@@ -402,10 +404,10 @@ MtrrGetFixedMtrrWorker (
   @retval The pointer of FixedSettings\r
 \r
 **/\r
-MTRR_FIXED_SETTINGS*\r
+MTRR_FIXED_SETTINGS *\r
 EFIAPI\r
 MtrrGetFixedMtrr (\r
-  OUT MTRR_FIXED_SETTINGS         *FixedSettings\r
+  OUT MTRR_FIXED_SETTINGS  *FixedSettings\r
   )\r
 {\r
   if (!IsMtrrSupported ()) {\r
@@ -415,7 +417,6 @@ MtrrGetFixedMtrr (
   return MtrrGetFixedMtrrWorker (FixedSettings);\r
 }\r
 \r
-\r
 /**\r
   Worker function will get the raw value in variable MTRRs\r
 \r
@@ -430,7 +431,7 @@ MtrrGetFixedMtrr (
   @return The VariableSettings input pointer\r
 \r
 **/\r
-MTRR_VARIABLE_SETTINGS*\r
+MTRR_VARIABLE_SETTINGS *\r
 MtrrGetVariableMtrrWorker (\r
   IN  MTRR_SETTINGS           *MtrrSetting,\r
   IN  UINT32                  VariableMtrrCount,\r
@@ -453,7 +454,7 @@ MtrrGetVariableMtrrWorker (
     }\r
   }\r
 \r
-  return  VariableSettings;\r
+  return VariableSettings;\r
 }\r
 \r
 /**\r
@@ -493,12 +494,13 @@ MtrrLibProgramFixedMtrr (
   for (MsrIndex = *LastMsrIndex + 1; MsrIndex < ARRAY_SIZE (mMtrrLibFixedMtrrTable); MsrIndex++) {\r
     if ((*Base >= mMtrrLibFixedMtrrTable[MsrIndex].BaseAddress) &&\r
         (*Base <\r
-            (\r
-              mMtrrLibFixedMtrrTable[MsrIndex].BaseAddress +\r
-              (8 * mMtrrLibFixedMtrrTable[MsrIndex].Length)\r
-            )\r
-          )\r
-        ) {\r
+         (\r
+          mMtrrLibFixedMtrrTable[MsrIndex].BaseAddress +\r
+          (8 * mMtrrLibFixedMtrrTable[MsrIndex].Length)\r
+         )\r
+        )\r
+        )\r
+    {\r
       break;\r
     }\r
   }\r
@@ -514,6 +516,7 @@ MtrrLibProgramFixedMtrr (
     //\r
     return RETURN_UNSUPPORTED;\r
   }\r
+\r
   LeftByteShift = ((UINT32)*Base - mMtrrLibFixedMtrrTable[MsrIndex].BaseAddress) / mMtrrLibFixedMtrrTable[MsrIndex].Length;\r
   ASSERT (LeftByteShift < 8);\r
 \r
@@ -530,6 +533,7 @@ MtrrLibProgramFixedMtrr (
       //\r
       return RETURN_UNSUPPORTED;\r
     }\r
+\r
     RightByteShift = 8 - LeftByteShift - (UINT32)(*Length) / mMtrrLibFixedMtrrTable[MsrIndex].Length;\r
     //\r
     // Update SubLength by actual length\r
@@ -538,14 +542,14 @@ MtrrLibProgramFixedMtrr (
   }\r
 \r
   *ClearMask = CLEAR_SEED;\r
-  *OrMask    = MultU64x32 (OR_SEED, (UINT32) Type);\r
+  *OrMask    = MultU64x32 (OR_SEED, (UINT32)Type);\r
 \r
   if (LeftByteShift != 0) {\r
     //\r
     // Clear the low bits by LeftByteShift\r
     //\r
     *ClearMask &= LShiftU64 (*ClearMask, LeftByteShift * 8);\r
-    *OrMask    &= LShiftU64 (*OrMask,    LeftByteShift * 8);\r
+    *OrMask    &= LShiftU64 (*OrMask, LeftByteShift * 8);\r
   }\r
 \r
   if (RightByteShift != 0) {\r
@@ -553,18 +557,17 @@ MtrrLibProgramFixedMtrr (
     // Clear the high bits by RightByteShift\r
     //\r
     *ClearMask &= RShiftU64 (*ClearMask, RightByteShift * 8);\r
-    *OrMask    &= RShiftU64 (*OrMask,    RightByteShift * 8);\r
+    *OrMask    &= RShiftU64 (*OrMask, RightByteShift * 8);\r
   }\r
 \r
   *Length -= SubLength;\r
   *Base   += SubLength;\r
 \r
-  *LastMsrIndex    = MsrIndex;\r
+  *LastMsrIndex = MsrIndex;\r
 \r
   return RETURN_SUCCESS;\r
 }\r
 \r
-\r
 /**\r
   Worker function gets the attribute of variable MTRRs.\r
 \r
@@ -594,17 +597,18 @@ MtrrGetMemoryAttributeInVariableMtrrWorker (
 \r
   ZeroMem (VariableMtrr, sizeof (VARIABLE_MTRR) * ARRAY_SIZE (VariableSettings->Mtrr));\r
   for (Index = 0, UsedMtrr = 0; Index < VariableMtrrCount; Index++) {\r
-    if (((MSR_IA32_MTRR_PHYSMASK_REGISTER *) &VariableSettings->Mtrr[Index].Mask)->Bits.V != 0) {\r
+    if (((MSR_IA32_MTRR_PHYSMASK_REGISTER *)&VariableSettings->Mtrr[Index].Mask)->Bits.V != 0) {\r
       VariableMtrr[Index].Msr         = (UINT32)Index;\r
       VariableMtrr[Index].BaseAddress = (VariableSettings->Mtrr[Index].Base & MtrrValidAddressMask);\r
       VariableMtrr[Index].Length      =\r
         ((~(VariableSettings->Mtrr[Index].Mask & MtrrValidAddressMask)) & MtrrValidBitsMask) + 1;\r
-      VariableMtrr[Index].Type        = (VariableSettings->Mtrr[Index].Base & 0x0ff);\r
-      VariableMtrr[Index].Valid       = TRUE;\r
-      VariableMtrr[Index].Used        = TRUE;\r
+      VariableMtrr[Index].Type  = (VariableSettings->Mtrr[Index].Base & 0x0ff);\r
+      VariableMtrr[Index].Valid = TRUE;\r
+      VariableMtrr[Index].Used  = TRUE;\r
       UsedMtrr++;\r
     }\r
   }\r
+\r
   return UsedMtrr;\r
 }\r
 \r
@@ -636,14 +640,15 @@ MtrrLibGetRawVariableRanges (
 \r
   ZeroMem (VariableMtrr, sizeof (MTRR_MEMORY_RANGE) * ARRAY_SIZE (VariableSettings->Mtrr));\r
   for (Index = 0, UsedMtrr = 0; Index < VariableMtrrCount; Index++) {\r
-    if (((MSR_IA32_MTRR_PHYSMASK_REGISTER *) &VariableSettings->Mtrr[Index].Mask)->Bits.V != 0) {\r
+    if (((MSR_IA32_MTRR_PHYSMASK_REGISTER *)&VariableSettings->Mtrr[Index].Mask)->Bits.V != 0) {\r
       VariableMtrr[Index].BaseAddress = (VariableSettings->Mtrr[Index].Base & MtrrValidAddressMask);\r
       VariableMtrr[Index].Length      =\r
         ((~(VariableSettings->Mtrr[Index].Mask & MtrrValidAddressMask)) & MtrrValidBitsMask) + 1;\r
-      VariableMtrr[Index].Type        = (MTRR_MEMORY_CACHE_TYPE)(VariableSettings->Mtrr[Index].Base & 0x0ff);\r
+      VariableMtrr[Index].Type = (MTRR_MEMORY_CACHE_TYPE)(VariableSettings->Mtrr[Index].Base & 0x0ff);\r
       UsedMtrr++;\r
     }\r
   }\r
+\r
   return UsedMtrr;\r
 }\r
 \r
@@ -664,9 +669,9 @@ MtrrLibGetRawVariableRanges (
 UINT32\r
 EFIAPI\r
 MtrrGetMemoryAttributeInVariableMtrr (\r
-  IN  UINT64                    MtrrValidBitsMask,\r
-  IN  UINT64                    MtrrValidAddressMask,\r
-  OUT VARIABLE_MTRR             *VariableMtrr\r
+  IN  UINT64         MtrrValidBitsMask,\r
+  IN  UINT64         MtrrValidAddressMask,\r
+  OUT VARIABLE_MTRR  *VariableMtrr\r
   )\r
 {\r
   MTRR_VARIABLE_SETTINGS  VariableSettings;\r
@@ -701,9 +706,9 @@ MtrrGetMemoryAttributeInVariableMtrr (
 **/\r
 UINT64\r
 MtrrLibBiggestAlignment (\r
-  UINT64    Address,\r
-  UINT64    Alignment0\r
-)\r
+  UINT64  Address,\r
+  UINT64  Alignment0\r
+  )\r
 {\r
   if (Address == 0) {\r
     return Alignment0;\r
@@ -731,9 +736,9 @@ BOOLEAN
 MtrrLibTypeLeftPrecedeRight (\r
   IN MTRR_MEMORY_CACHE_TYPE  Left,\r
   IN MTRR_MEMORY_CACHE_TYPE  Right\r
-)\r
+  )\r
 {\r
-  return (BOOLEAN) (Left == CacheUncacheable || (Left == CacheWriteThrough && Right == CacheWriteBack));\r
+  return (BOOLEAN)(Left == CacheUncacheable || (Left == CacheWriteThrough && Right == CacheWriteBack));\r
 }\r
 \r
 /**\r
@@ -747,14 +752,13 @@ MtrrLibTypeLeftPrecedeRight (
 **/\r
 VOID\r
 MtrrLibInitializeMtrrMask (\r
-  OUT UINT64 *MtrrValidBitsMask,\r
-  OUT UINT64 *MtrrValidAddressMask\r
+  OUT UINT64  *MtrrValidBitsMask,\r
+  OUT UINT64  *MtrrValidAddressMask\r
   )\r
 {\r
   UINT32                          MaxExtendedFunction;\r
   CPUID_VIR_PHY_ADDRESS_SIZE_EAX  VirPhyAddressSize;\r
 \r
-\r
   AsmCpuid (CPUID_EXTENDED_FUNCTION, &MaxExtendedFunction, NULL, NULL, NULL);\r
 \r
   if (MaxExtendedFunction >= CPUID_VIR_PHY_ADDRESS_SIZE) {\r
@@ -763,11 +767,10 @@ MtrrLibInitializeMtrrMask (
     VirPhyAddressSize.Bits.PhysicalAddressBits = 36;\r
   }\r
 \r
-  *MtrrValidBitsMask = LShiftU64 (1, VirPhyAddressSize.Bits.PhysicalAddressBits) - 1;\r
+  *MtrrValidBitsMask    = LShiftU64 (1, VirPhyAddressSize.Bits.PhysicalAddressBits) - 1;\r
   *MtrrValidAddressMask = *MtrrValidBitsMask & 0xfffffffffffff000ULL;\r
 }\r
 \r
-\r
 /**\r
   Determines the real attribute of a memory range.\r
 \r
@@ -782,8 +785,8 @@ MtrrLibInitializeMtrrMask (
 **/\r
 MTRR_MEMORY_CACHE_TYPE\r
 MtrrLibPrecedence (\r
-  IN MTRR_MEMORY_CACHE_TYPE    MtrrType1,\r
-  IN MTRR_MEMORY_CACHE_TYPE    MtrrType2\r
+  IN MTRR_MEMORY_CACHE_TYPE  MtrrType1,\r
+  IN MTRR_MEMORY_CACHE_TYPE  MtrrType2\r
   )\r
 {\r
   if (MtrrType1 == MtrrType2) {\r
@@ -793,7 +796,7 @@ MtrrLibPrecedence (
   ASSERT (\r
     MtrrLibTypeLeftPrecedeRight (MtrrType1, MtrrType2) ||\r
     MtrrLibTypeLeftPrecedeRight (MtrrType2, MtrrType1)\r
-  );\r
+    );\r
 \r
   if (MtrrLibTypeLeftPrecedeRight (MtrrType1, MtrrType2)) {\r
     return MtrrType1;\r
@@ -817,20 +820,20 @@ MtrrLibPrecedence (
 **/\r
 MTRR_MEMORY_CACHE_TYPE\r
 MtrrGetMemoryAttributeByAddressWorker (\r
-  IN MTRR_SETTINGS      *MtrrSetting,\r
-  IN PHYSICAL_ADDRESS   Address\r
+  IN MTRR_SETTINGS     *MtrrSetting,\r
+  IN PHYSICAL_ADDRESS  Address\r
   )\r
 {\r
-  MSR_IA32_MTRR_DEF_TYPE_REGISTER DefType;\r
-  UINT64                          FixedMtrr;\r
-  UINTN                           Index;\r
-  UINTN                           SubIndex;\r
-  MTRR_MEMORY_CACHE_TYPE          MtrrType;\r
-  MTRR_MEMORY_RANGE               VariableMtrr[ARRAY_SIZE (MtrrSetting->Variables.Mtrr)];\r
-  UINT64                          MtrrValidBitsMask;\r
-  UINT64                          MtrrValidAddressMask;\r
-  UINT32                          VariableMtrrCount;\r
-  MTRR_VARIABLE_SETTINGS          VariableSettings;\r
+  MSR_IA32_MTRR_DEF_TYPE_REGISTER  DefType;\r
+  UINT64                           FixedMtrr;\r
+  UINTN                            Index;\r
+  UINTN                            SubIndex;\r
+  MTRR_MEMORY_CACHE_TYPE           MtrrType;\r
+  MTRR_MEMORY_RANGE                VariableMtrr[ARRAY_SIZE (MtrrSetting->Variables.Mtrr)];\r
+  UINT64                           MtrrValidBitsMask;\r
+  UINT64                           MtrrValidAddressMask;\r
+  UINT32                           VariableMtrrCount;\r
+  MTRR_VARIABLE_SETTINGS           VariableSettings;\r
 \r
   //\r
   // Check if MTRR is enabled, if not, return UC as attribute\r
@@ -854,18 +857,20 @@ MtrrGetMemoryAttributeByAddressWorker (
       // Go through the fixed MTRR\r
       //\r
       for (Index = 0; Index < MTRR_NUMBER_OF_FIXED_MTRR; Index++) {\r
-        if (Address >= mMtrrLibFixedMtrrTable[Index].BaseAddress &&\r
-            Address < mMtrrLibFixedMtrrTable[Index].BaseAddress +\r
-            (mMtrrLibFixedMtrrTable[Index].Length * 8)) {\r
+        if ((Address >= mMtrrLibFixedMtrrTable[Index].BaseAddress) &&\r
+            (Address < mMtrrLibFixedMtrrTable[Index].BaseAddress +\r
+             (mMtrrLibFixedMtrrTable[Index].Length * 8)))\r
+        {\r
           SubIndex =\r
-            ((UINTN) Address - mMtrrLibFixedMtrrTable[Index].BaseAddress) /\r
+            ((UINTN)Address - mMtrrLibFixedMtrrTable[Index].BaseAddress) /\r
             mMtrrLibFixedMtrrTable[Index].Length;\r
           if (MtrrSetting == NULL) {\r
             FixedMtrr = AsmReadMsr64 (mMtrrLibFixedMtrrTable[Index].Msr);\r
           } else {\r
             FixedMtrr = MtrrSetting->Fixed.Mtrr[Index];\r
           }\r
-          return (MTRR_MEMORY_CACHE_TYPE) (RShiftU64 (FixedMtrr, SubIndex * 8) & 0xFF);\r
+\r
+          return (MTRR_MEMORY_CACHE_TYPE)(RShiftU64 (FixedMtrr, SubIndex * 8) & 0xFF);\r
         }\r
       }\r
     }\r
@@ -882,7 +887,7 @@ MtrrGetMemoryAttributeByAddressWorker (
     MtrrValidBitsMask,\r
     MtrrValidAddressMask,\r
     VariableMtrr\r
-  );\r
+    );\r
 \r
   //\r
   // Go through the variable MTRR\r
@@ -890,12 +895,13 @@ MtrrGetMemoryAttributeByAddressWorker (
   MtrrType = CacheInvalid;\r
   for (Index = 0; Index < VariableMtrrCount; Index++) {\r
     if (VariableMtrr[Index].Length != 0) {\r
-      if (Address >= VariableMtrr[Index].BaseAddress &&\r
-          Address < VariableMtrr[Index].BaseAddress + VariableMtrr[Index].Length) {\r
+      if ((Address >= VariableMtrr[Index].BaseAddress) &&\r
+          (Address < VariableMtrr[Index].BaseAddress + VariableMtrr[Index].Length))\r
+      {\r
         if (MtrrType == CacheInvalid) {\r
-          MtrrType = (MTRR_MEMORY_CACHE_TYPE) VariableMtrr[Index].Type;\r
+          MtrrType = (MTRR_MEMORY_CACHE_TYPE)VariableMtrr[Index].Type;\r
         } else {\r
-          MtrrType = MtrrLibPrecedence (MtrrType, (MTRR_MEMORY_CACHE_TYPE) VariableMtrr[Index].Type);\r
+          MtrrType = MtrrLibPrecedence (MtrrType, (MTRR_MEMORY_CACHE_TYPE)VariableMtrr[Index].Type);\r
         }\r
       }\r
     }\r
@@ -905,13 +911,12 @@ MtrrGetMemoryAttributeByAddressWorker (
   // If there is no MTRR which covers the Address, use the default MTRR type.\r
   //\r
   if (MtrrType == CacheInvalid) {\r
-    MtrrType = (MTRR_MEMORY_CACHE_TYPE) DefType.Bits.Type;\r
+    MtrrType = (MTRR_MEMORY_CACHE_TYPE)DefType.Bits.Type;\r
   }\r
 \r
   return MtrrType;\r
 }\r
 \r
-\r
 /**\r
   This function will get the memory cache type of the specific address.\r
 \r
@@ -925,7 +930,7 @@ MtrrGetMemoryAttributeByAddressWorker (
 MTRR_MEMORY_CACHE_TYPE\r
 EFIAPI\r
 MtrrGetMemoryAttribute (\r
-  IN PHYSICAL_ADDRESS   Address\r
+  IN PHYSICAL_ADDRESS  Address\r
   )\r
 {\r
   if (!IsMtrrSupported ()) {\r
@@ -955,46 +960,48 @@ MtrrGetMemoryAttribute (
 **/\r
 RETURN_STATUS\r
 MtrrLibSetMemoryType (\r
-  IN MTRR_MEMORY_RANGE             *Ranges,\r
-  IN UINTN                         Capacity,\r
-  IN OUT UINTN                     *Count,\r
-  IN UINT64                        BaseAddress,\r
-  IN UINT64                        Length,\r
-  IN MTRR_MEMORY_CACHE_TYPE        Type\r
+  IN MTRR_MEMORY_RANGE       *Ranges,\r
+  IN UINTN                   Capacity,\r
+  IN OUT UINTN               *Count,\r
+  IN UINT64                  BaseAddress,\r
+  IN UINT64                  Length,\r
+  IN MTRR_MEMORY_CACHE_TYPE  Type\r
   )\r
 {\r
-  UINTN                            Index;\r
-  UINT64                           Limit;\r
-  UINT64                           LengthLeft;\r
-  UINT64                           LengthRight;\r
-  UINTN                            StartIndex;\r
-  UINTN                            EndIndex;\r
-  UINTN                            DeltaCount;\r
+  UINTN   Index;\r
+  UINT64  Limit;\r
+  UINT64  LengthLeft;\r
+  UINT64  LengthRight;\r
+  UINTN   StartIndex;\r
+  UINTN   EndIndex;\r
+  UINTN   DeltaCount;\r
 \r
   LengthRight = 0;\r
   LengthLeft  = 0;\r
-  Limit = BaseAddress + Length;\r
-  StartIndex = *Count;\r
-  EndIndex = *Count;\r
+  Limit       = BaseAddress + Length;\r
+  StartIndex  = *Count;\r
+  EndIndex    = *Count;\r
   for (Index = 0; Index < *Count; Index++) {\r
     if ((StartIndex == *Count) &&\r
         (Ranges[Index].BaseAddress <= BaseAddress) &&\r
-        (BaseAddress < Ranges[Index].BaseAddress + Ranges[Index].Length)) {\r
+        (BaseAddress < Ranges[Index].BaseAddress + Ranges[Index].Length))\r
+    {\r
       StartIndex = Index;\r
       LengthLeft = BaseAddress - Ranges[Index].BaseAddress;\r
     }\r
 \r
     if ((EndIndex == *Count) &&\r
         (Ranges[Index].BaseAddress < Limit) &&\r
-        (Limit <= Ranges[Index].BaseAddress + Ranges[Index].Length)) {\r
-      EndIndex = Index;\r
+        (Limit <= Ranges[Index].BaseAddress + Ranges[Index].Length))\r
+    {\r
+      EndIndex    = Index;\r
       LengthRight = Ranges[Index].BaseAddress + Ranges[Index].Length - Limit;\r
       break;\r
     }\r
   }\r
 \r
   ASSERT (StartIndex != *Count && EndIndex != *Count);\r
-  if (StartIndex == EndIndex && Ranges[StartIndex].Type == Type) {\r
+  if ((StartIndex == EndIndex) && (Ranges[StartIndex].Type == Type)) {\r
     return RETURN_ALREADY_STARTED;\r
   }\r
 \r
@@ -1004,14 +1011,15 @@ MtrrLibSetMemoryType (
   // logic doesn't need to consider merging.\r
   //\r
   if (StartIndex != 0) {\r
-    if (LengthLeft == 0 && Ranges[StartIndex - 1].Type == Type) {\r
+    if ((LengthLeft == 0) && (Ranges[StartIndex - 1].Type == Type)) {\r
       StartIndex--;\r
-      Length += Ranges[StartIndex].Length;\r
+      Length      += Ranges[StartIndex].Length;\r
       BaseAddress -= Ranges[StartIndex].Length;\r
     }\r
   }\r
+\r
   if (EndIndex != (*Count) - 1) {\r
-    if (LengthRight == 0 && Ranges[EndIndex + 1].Type == Type) {\r
+    if ((LengthRight == 0) && (Ranges[EndIndex + 1].Type == Type)) {\r
       EndIndex++;\r
       Length += Ranges[EndIndex].Length;\r
     }\r
@@ -1029,9 +1037,11 @@ MtrrLibSetMemoryType (
   if (LengthLeft == 0) {\r
     DeltaCount++;\r
   }\r
+\r
   if (LengthRight == 0) {\r
     DeltaCount++;\r
   }\r
+\r
   if (*Count - DeltaCount > Capacity) {\r
     return RETURN_OUT_OF_RESOURCES;\r
   }\r
@@ -1046,14 +1056,16 @@ MtrrLibSetMemoryType (
     Ranges[StartIndex].Length = LengthLeft;\r
     StartIndex++;\r
   }\r
+\r
   if (LengthRight != 0) {\r
     Ranges[EndIndex - DeltaCount].BaseAddress = BaseAddress + Length;\r
-    Ranges[EndIndex - DeltaCount].Length = LengthRight;\r
-    Ranges[EndIndex - DeltaCount].Type = Ranges[EndIndex].Type;\r
+    Ranges[EndIndex - DeltaCount].Length      = LengthRight;\r
+    Ranges[EndIndex - DeltaCount].Type        = Ranges[EndIndex].Type;\r
   }\r
+\r
   Ranges[StartIndex].BaseAddress = BaseAddress;\r
-  Ranges[StartIndex].Length = Length;\r
-  Ranges[StartIndex].Type = Type;\r
+  Ranges[StartIndex].Length      = Length;\r
+  Ranges[StartIndex].Type        = Type;\r
   return RETURN_SUCCESS;\r
 }\r
 \r
@@ -1070,30 +1082,31 @@ MtrrLibSetMemoryType (
 **/\r
 UINT8\r
 MtrrLibGetNumberOfTypes (\r
-  IN CONST MTRR_MEMORY_RANGE     *Ranges,\r
-  IN UINTN                       RangeCount,\r
-  IN UINT64                      BaseAddress,\r
-  IN UINT64                      Length,\r
-  IN OUT UINT8                   *Types  OPTIONAL\r
+  IN CONST MTRR_MEMORY_RANGE  *Ranges,\r
+  IN UINTN                    RangeCount,\r
+  IN UINT64                   BaseAddress,\r
+  IN UINT64                   Length,\r
+  IN OUT UINT8                *Types  OPTIONAL\r
   )\r
 {\r
-  UINTN                          Index;\r
-  UINT8                          TypeCount;\r
-  UINT8                          LocalTypes;\r
+  UINTN  Index;\r
+  UINT8  TypeCount;\r
+  UINT8  LocalTypes;\r
 \r
-  TypeCount = 0;\r
+  TypeCount  = 0;\r
   LocalTypes = 0;\r
   for (Index = 0; Index < RangeCount; Index++) {\r
     if ((Ranges[Index].BaseAddress <= BaseAddress) &&\r
         (BaseAddress < Ranges[Index].BaseAddress + Ranges[Index].Length)\r
-        ) {\r
+        )\r
+    {\r
       if ((LocalTypes & (1 << Ranges[Index].Type)) == 0) {\r
         LocalTypes |= (UINT8)(1 << Ranges[Index].Type);\r
         TypeCount++;\r
       }\r
 \r
       if (BaseAddress + Length > Ranges[Index].BaseAddress + Ranges[Index].Length) {\r
-        Length -= Ranges[Index].BaseAddress + Ranges[Index].Length - BaseAddress;\r
+        Length     -= Ranges[Index].BaseAddress + Ranges[Index].Length - BaseAddress;\r
         BaseAddress = Ranges[Index].BaseAddress + Ranges[Index].Length;\r
       } else {\r
         break;\r
@@ -1104,6 +1117,7 @@ MtrrLibGetNumberOfTypes (
   if (Types != NULL) {\r
     *Types = LocalTypes;\r
   }\r
+\r
   return TypeCount;\r
 }\r
 \r
@@ -1121,32 +1135,32 @@ MtrrLibGetNumberOfTypes (
 **/\r
 VOID\r
 MtrrLibCalculateLeastMtrrs (\r
-  IN UINT16                      VertexCount,\r
-  IN MTRR_LIB_ADDRESS            *Vertices,\r
-  IN OUT CONST UINT8             *Weight,\r
-  IN UINT16                      Start,\r
-  IN UINT16                      Stop,\r
-  IN BOOLEAN                     IncludeOptional\r
+  IN UINT16            VertexCount,\r
+  IN MTRR_LIB_ADDRESS  *Vertices,\r
+  IN OUT CONST UINT8   *Weight,\r
+  IN UINT16            Start,\r
+  IN UINT16            Stop,\r
+  IN BOOLEAN           IncludeOptional\r
   )\r
 {\r
-  UINT16                         Index;\r
-  UINT8                          MinWeight;\r
-  UINT16                         MinI;\r
-  UINT8                          Mandatory;\r
-  UINT8                          Optional;\r
+  UINT16  Index;\r
+  UINT8   MinWeight;\r
+  UINT16  MinI;\r
+  UINT8   Mandatory;\r
+  UINT8   Optional;\r
 \r
   for (Index = Start; Index <= Stop; Index++) {\r
     Vertices[Index].Visited = FALSE;\r
-    Mandatory = Weight[M(Start,Index)];\r
-    Vertices[Index].Weight = Mandatory;\r
+    Mandatory               = Weight[M (Start, Index)];\r
+    Vertices[Index].Weight  = Mandatory;\r
     if (Mandatory != MAX_WEIGHT) {\r
-      Optional = IncludeOptional ? Weight[O(Start, Index)] : 0;\r
+      Optional                = IncludeOptional ? Weight[O (Start, Index)] : 0;\r
       Vertices[Index].Weight += Optional;\r
       ASSERT (Vertices[Index].Weight >= Optional);\r
     }\r
   }\r
 \r
-  MinI = Start;\r
+  MinI      = Start;\r
   MinWeight = 0;\r
   while (!Vertices[Stop].Visited) {\r
     //\r
@@ -1154,9 +1168,9 @@ MtrrLibCalculateLeastMtrrs (
     //\r
     for (Index = Start + 1; Index <= Stop; Index++) {\r
       if (!Vertices[Index].Visited) {\r
-        Mandatory = Weight[M(MinI, Index)];\r
+        Mandatory = Weight[M (MinI, Index)];\r
         if (Mandatory != MAX_WEIGHT) {\r
-          Optional = IncludeOptional ? Weight[O(MinI, Index)] : 0;\r
+          Optional = IncludeOptional ? Weight[O (MinI, Index)] : 0;\r
           if (MinWeight + Mandatory + Optional <= Vertices[Index].Weight) {\r
             Vertices[Index].Weight   = MinWeight + Mandatory + Optional;\r
             Vertices[Index].Previous = MinI; // Previous is Start based.\r
@@ -1171,7 +1185,7 @@ MtrrLibCalculateLeastMtrrs (
     MinI      = VertexCount;\r
     MinWeight = MAX_WEIGHT;\r
     for (Index = Start + 1; Index <= Stop; Index++) {\r
-      if (!Vertices[Index].Visited && MinWeight > Vertices[Index].Weight) {\r
+      if (!Vertices[Index].Visited && (MinWeight > Vertices[Index].Weight)) {\r
         MinI      = Index;\r
         MinWeight = Vertices[Index].Weight;\r
       }\r
@@ -1227,13 +1241,15 @@ MtrrLibAppendVariableMtrr (
 **/\r
 MTRR_MEMORY_CACHE_TYPE\r
 MtrrLibLowestType (\r
-  IN      UINT8                    TypeBits\r
-)\r
+  IN      UINT8  TypeBits\r
+  )\r
 {\r
-  INT8                             Type;\r
+  INT8  Type;\r
 \r
   ASSERT (TypeBits != 0);\r
-  for (Type = 7; (INT8)TypeBits > 0; Type--, TypeBits <<= 1);\r
+  for (Type = 7; (INT8)TypeBits > 0; Type--, TypeBits <<= 1) {\r
+  }\r
+\r
   return (MTRR_MEMORY_CACHE_TYPE)Type;\r
 }\r
 \r
@@ -1245,11 +1261,11 @@ MtrrLibLowestType (
 **/\r
 BOOLEAN\r
 MtrrLibIsPowerOfTwo (\r
-  IN     UINT64                  Operand\r
-)\r
+  IN     UINT64  Operand\r
+  )\r
 {\r
   ASSERT (Operand != 0);\r
-  return (BOOLEAN) ((Operand & (Operand - 1)) == 0);\r
+  return (BOOLEAN)((Operand & (Operand - 1)) == 0);\r
 }\r
 \r
 /**\r
@@ -1276,36 +1292,36 @@ MtrrLibIsPowerOfTwo (
 **/\r
 RETURN_STATUS\r
 MtrrLibCalculateSubtractivePath (\r
-  IN MTRR_MEMORY_CACHE_TYPE      DefaultType,\r
-  IN UINT64                      A0,\r
-  IN CONST MTRR_MEMORY_RANGE     *Ranges,\r
-  IN UINTN                       RangeCount,\r
-  IN UINT16                      VertexCount,\r
-  IN MTRR_LIB_ADDRESS            *Vertices,\r
-  IN OUT UINT8                   *Weight,\r
-  IN UINT16                      Start,\r
-  IN UINT16                      Stop,\r
-  IN UINT8                       Types,\r
-  IN UINT8                       TypeCount,\r
-  IN OUT MTRR_MEMORY_RANGE       *Mtrrs        OPTIONAL,\r
-  IN UINT32                      MtrrCapacity  OPTIONAL,\r
-  IN OUT UINT32                  *MtrrCount    OPTIONAL\r
+  IN MTRR_MEMORY_CACHE_TYPE   DefaultType,\r
+  IN UINT64                   A0,\r
+  IN CONST MTRR_MEMORY_RANGE  *Ranges,\r
+  IN UINTN                    RangeCount,\r
+  IN UINT16                   VertexCount,\r
+  IN MTRR_LIB_ADDRESS         *Vertices,\r
+  IN OUT UINT8                *Weight,\r
+  IN UINT16                   Start,\r
+  IN UINT16                   Stop,\r
+  IN UINT8                    Types,\r
+  IN UINT8                    TypeCount,\r
+  IN OUT MTRR_MEMORY_RANGE    *Mtrrs        OPTIONAL,\r
+  IN UINT32                   MtrrCapacity  OPTIONAL,\r
+  IN OUT UINT32               *MtrrCount    OPTIONAL\r
   )\r
 {\r
-  RETURN_STATUS                  Status;\r
-  UINT64                         Base;\r
-  UINT64                         Length;\r
-  UINT8                          PrecedentTypes;\r
-  UINTN                          Index;\r
-  UINT64                         HBase;\r
-  UINT64                         HLength;\r
-  UINT64                         SubLength;\r
-  UINT16                         SubStart;\r
-  UINT16                         SubStop;\r
-  UINT16                         Cur;\r
-  UINT16                         Pre;\r
-  MTRR_MEMORY_CACHE_TYPE         LowestType;\r
-  MTRR_MEMORY_CACHE_TYPE         LowestPrecedentType;\r
+  RETURN_STATUS           Status;\r
+  UINT64                  Base;\r
+  UINT64                  Length;\r
+  UINT8                   PrecedentTypes;\r
+  UINTN                   Index;\r
+  UINT64                  HBase;\r
+  UINT64                  HLength;\r
+  UINT64                  SubLength;\r
+  UINT16                  SubStart;\r
+  UINT16                  SubStop;\r
+  UINT16                  Cur;\r
+  UINT16                  Pre;\r
+  MTRR_MEMORY_CACHE_TYPE  LowestType;\r
+  MTRR_MEMORY_CACHE_TYPE  LowestPrecedentType;\r
 \r
   Base   = Vertices[Start].Address;\r
   Length = Vertices[Stop].Address - Base;\r
@@ -1315,21 +1331,22 @@ MtrrLibCalculateSubtractivePath (
   //\r
   // Clear the lowest type (highest bit) to get the precedent types\r
   //\r
-  PrecedentTypes = ~(1 << LowestType) & Types;\r
+  PrecedentTypes      = ~(1 << LowestType) & Types;\r
   LowestPrecedentType = MtrrLibLowestType (PrecedentTypes);\r
 \r
   if (Mtrrs == NULL) {\r
-    Weight[M(Start, Stop)] = ((LowestType == DefaultType) ? 0 : 1);\r
-    Weight[O(Start, Stop)] = ((LowestType == DefaultType) ? 1 : 0);\r
+    Weight[M (Start, Stop)] = ((LowestType == DefaultType) ? 0 : 1);\r
+    Weight[O (Start, Stop)] = ((LowestType == DefaultType) ? 1 : 0);\r
   }\r
 \r
   // Add all high level ranges\r
-  HBase = MAX_UINT64;\r
+  HBase   = MAX_UINT64;\r
   HLength = 0;\r
   for (Index = 0; Index < RangeCount; Index++) {\r
     if (Length == 0) {\r
       break;\r
     }\r
+\r
     if ((Base < Ranges[Index].BaseAddress) || (Ranges[Index].BaseAddress + Ranges[Index].Length <= Base)) {\r
       continue;\r
     }\r
@@ -1342,6 +1359,7 @@ MtrrLibCalculateSubtractivePath (
     } else {\r
       SubLength = Length;\r
     }\r
+\r
     if (((1 << Ranges[Index].Type) & PrecedentTypes) != 0) {\r
       //\r
       // Meet a range whose types take precedence.\r
@@ -1351,17 +1369,19 @@ MtrrLibCalculateSubtractivePath (
       if (HBase == MAX_UINT64) {\r
         HBase = Base;\r
       }\r
+\r
       HLength += SubLength;\r
     }\r
 \r
-    Base += SubLength;\r
+    Base   += SubLength;\r
     Length -= SubLength;\r
 \r
     if (HLength == 0) {\r
       continue;\r
     }\r
 \r
-    if ((Ranges[Index].Type == LowestType) || (Length == 0)) { // meet low type or end\r
+    if ((Ranges[Index].Type == LowestType) || (Length == 0)) {\r
+      // meet low type or end\r
 \r
       //\r
       // Add the MTRRs for each high priority type range\r
@@ -1379,6 +1399,7 @@ MtrrLibCalculateSubtractivePath (
           break;\r
         }\r
       }\r
+\r
       ASSERT (Vertices[SubStart].Address == HBase);\r
       ASSERT (Vertices[SubStop].Address == HBase + HLength);\r
 \r
@@ -1393,12 +1414,17 @@ MtrrLibCalculateSubtractivePath (
         } else {\r
           while (SubStart != SubStop) {\r
             Status = MtrrLibAppendVariableMtrr (\r
-              Mtrrs, MtrrCapacity, MtrrCount,\r
-              Vertices[SubStart].Address, Vertices[SubStart].Length, Vertices[SubStart].Type\r
-            );\r
+                       Mtrrs,\r
+                       MtrrCapacity,\r
+                       MtrrCount,\r
+                       Vertices[SubStart].Address,\r
+                       Vertices[SubStart].Length,\r
+                       Vertices[SubStart].Type\r
+                       );\r
             if (RETURN_ERROR (Status)) {\r
               return Status;\r
             }\r
+\r
             SubStart++;\r
           }\r
         }\r
@@ -1411,43 +1437,57 @@ MtrrLibCalculateSubtractivePath (
         } else {\r
           // When we need to collect the optimal path from SubStart to SubStop\r
           while (SubStop != SubStart) {\r
-            Cur = SubStop;\r
-            Pre = Vertices[Cur].Previous;\r
+            Cur     = SubStop;\r
+            Pre     = Vertices[Cur].Previous;\r
             SubStop = Pre;\r
 \r
             if (Weight[M (Pre, Cur)] + Weight[O (Pre, Cur)] != 0) {\r
               Status = MtrrLibAppendVariableMtrr (\r
-                Mtrrs, MtrrCapacity, MtrrCount,\r
-                Vertices[Pre].Address, Vertices[Cur].Address - Vertices[Pre].Address,\r
-                (Pre != Cur - 1) ? LowestPrecedentType : Vertices[Pre].Type\r
-              );\r
+                         Mtrrs,\r
+                         MtrrCapacity,\r
+                         MtrrCount,\r
+                         Vertices[Pre].Address,\r
+                         Vertices[Cur].Address - Vertices[Pre].Address,\r
+                         (Pre != Cur - 1) ? LowestPrecedentType : Vertices[Pre].Type\r
+                         );\r
               if (RETURN_ERROR (Status)) {\r
                 return Status;\r
               }\r
             }\r
+\r
             if (Pre != Cur - 1) {\r
               Status = MtrrLibCalculateSubtractivePath (\r
-                DefaultType, A0,\r
-                Ranges, RangeCount,\r
-                VertexCount, Vertices, Weight,\r
-                Pre, Cur, PrecedentTypes, 2,\r
-                Mtrrs, MtrrCapacity, MtrrCount\r
-              );\r
+                         DefaultType,\r
+                         A0,\r
+                         Ranges,\r
+                         RangeCount,\r
+                         VertexCount,\r
+                         Vertices,\r
+                         Weight,\r
+                         Pre,\r
+                         Cur,\r
+                         PrecedentTypes,\r
+                         2,\r
+                         Mtrrs,\r
+                         MtrrCapacity,\r
+                         MtrrCount\r
+                         );\r
               if (RETURN_ERROR (Status)) {\r
                 return Status;\r
               }\r
             }\r
           }\r
         }\r
-\r
       }\r
+\r
       //\r
       // Reset HBase, HLength\r
       //\r
-      HBase = MAX_UINT64;\r
+      HBase   = MAX_UINT64;\r
       HLength = 0;\r
     }\r
   }\r
+\r
   return RETURN_SUCCESS;\r
 }\r
 \r
@@ -1474,34 +1514,34 @@ MtrrLibCalculateSubtractivePath (
 **/\r
 RETURN_STATUS\r
 MtrrLibCalculateMtrrs (\r
-  IN MTRR_MEMORY_CACHE_TYPE  DefaultType,\r
-  IN UINT64                  A0,\r
-  IN CONST MTRR_MEMORY_RANGE *Ranges,\r
-  IN UINTN                   RangeCount,\r
-  IN VOID                    *Scratch,\r
-  IN OUT UINTN               *ScratchSize,\r
-  IN OUT MTRR_MEMORY_RANGE   *Mtrrs,\r
-  IN UINT32                  MtrrCapacity,\r
-  IN OUT UINT32              *MtrrCount\r
+  IN MTRR_MEMORY_CACHE_TYPE   DefaultType,\r
+  IN UINT64                   A0,\r
+  IN CONST MTRR_MEMORY_RANGE  *Ranges,\r
+  IN UINTN                    RangeCount,\r
+  IN VOID                     *Scratch,\r
+  IN OUT UINTN                *ScratchSize,\r
+  IN OUT MTRR_MEMORY_RANGE    *Mtrrs,\r
+  IN UINT32                   MtrrCapacity,\r
+  IN OUT UINT32               *MtrrCount\r
   )\r
 {\r
-  UINT64                    Base0;\r
-  UINT64                    Base1;\r
-  UINTN                     Index;\r
-  UINT64                    Base;\r
-  UINT64                    Length;\r
-  UINT64                    Alignment;\r
-  UINT64                    SubLength;\r
-  MTRR_LIB_ADDRESS          *Vertices;\r
-  UINT8                     *Weight;\r
-  UINT32                    VertexIndex;\r
-  UINT32                    VertexCount;\r
-  UINTN                     RequiredScratchSize;\r
-  UINT8                     TypeCount;\r
-  UINT16                    Start;\r
-  UINT16                    Stop;\r
-  UINT8                     Type;\r
-  RETURN_STATUS             Status;\r
+  UINT64            Base0;\r
+  UINT64            Base1;\r
+  UINTN             Index;\r
+  UINT64            Base;\r
+  UINT64            Length;\r
+  UINT64            Alignment;\r
+  UINT64            SubLength;\r
+  MTRR_LIB_ADDRESS  *Vertices;\r
+  UINT8             *Weight;\r
+  UINT32            VertexIndex;\r
+  UINT32            VertexCount;\r
+  UINTN             RequiredScratchSize;\r
+  UINT8             TypeCount;\r
+  UINT16            Start;\r
+  UINT16            Stop;\r
+  UINT8             Type;\r
+  RETURN_STATUS     Status;\r
 \r
   Base0 = Ranges[0].BaseAddress;\r
   Base1 = Ranges[RangeCount - 1].BaseAddress + Ranges[RangeCount - 1].Length;\r
@@ -1510,9 +1550,9 @@ MtrrLibCalculateMtrrs (
   //\r
   // Count the number of vertices.\r
   //\r
-  Vertices = (MTRR_LIB_ADDRESS*)Scratch;\r
+  Vertices = (MTRR_LIB_ADDRESS *)Scratch;\r
   for (VertexIndex = 0, Index = 0; Index < RangeCount; Index++) {\r
-    Base = Ranges[Index].BaseAddress;\r
+    Base   = Ranges[Index].BaseAddress;\r
     Length = Ranges[Index].Length;\r
     while (Length != 0) {\r
       Alignment = MtrrLibBiggestAlignment (Base, A0);\r
@@ -1520,24 +1560,30 @@ MtrrLibCalculateMtrrs (
       if (SubLength > Length) {\r
         SubLength = GetPowerOfTwo64 (Length);\r
       }\r
+\r
       if (VertexIndex < *ScratchSize / sizeof (*Vertices)) {\r
         Vertices[VertexIndex].Address   = Base;\r
         Vertices[VertexIndex].Alignment = Alignment;\r
         Vertices[VertexIndex].Type      = Ranges[Index].Type;\r
         Vertices[VertexIndex].Length    = SubLength;\r
       }\r
+\r
       Base   += SubLength;\r
       Length -= SubLength;\r
       VertexIndex++;\r
     }\r
   }\r
+\r
   //\r
   // Vertices[VertexIndex] = Base1, so whole vertex count is (VertexIndex + 1).\r
   //\r
   VertexCount = VertexIndex + 1;\r
   DEBUG ((\r
-    DEBUG_CACHE, "  Count of vertices (%016llx - %016llx) = %d\n",\r
-    Ranges[0].BaseAddress, Ranges[RangeCount - 1].BaseAddress + Ranges[RangeCount - 1].Length, VertexCount\r
+    DEBUG_CACHE,\r
+    "  Count of vertices (%016llx - %016llx) = %d\n",\r
+    Ranges[0].BaseAddress,\r
+    Ranges[RangeCount - 1].BaseAddress + Ranges[RangeCount - 1].Length,\r
+    VertexCount\r
     ));\r
   ASSERT (VertexCount < MAX_UINT16);\r
 \r
@@ -1546,14 +1592,15 @@ MtrrLibCalculateMtrrs (
     *ScratchSize = RequiredScratchSize;\r
     return RETURN_BUFFER_TOO_SMALL;\r
   }\r
+\r
   Vertices[VertexCount - 1].Address = Base1;\r
 \r
-  Weight = (UINT8 *) &Vertices[VertexCount];\r
+  Weight = (UINT8 *)&Vertices[VertexCount];\r
   for (VertexIndex = 0; VertexIndex < VertexCount; VertexIndex++) {\r
     //\r
     // Set optional weight between vertices and self->self to 0\r
     //\r
-    SetMem (&Weight[M(VertexIndex, 0)], VertexIndex + 1, 0);\r
+    SetMem (&Weight[M (VertexIndex, 0)], VertexIndex + 1, 0);\r
     //\r
     // Set mandatory weight between vertices to MAX_WEIGHT\r
     //\r
@@ -1590,19 +1637,34 @@ MtrrLibCalculateMtrrs (
           //\r
           break;\r
         }\r
-        if ((Weight[M(Start, Stop)] == MAX_WEIGHT) && MtrrLibIsPowerOfTwo (Length)) {\r
+\r
+        if ((Weight[M (Start, Stop)] == MAX_WEIGHT) && MtrrLibIsPowerOfTwo (Length)) {\r
           if (MtrrLibGetNumberOfTypes (\r
-                Ranges, RangeCount, Vertices[Start].Address, Vertices[Stop].Address - Vertices[Start].Address, &Type\r
-                ) == TypeCount) {\r
+                Ranges,\r
+                RangeCount,\r
+                Vertices[Start].Address,\r
+                Vertices[Stop].Address - Vertices[Start].Address,\r
+                &Type\r
+                ) == TypeCount)\r
+          {\r
             //\r
             // Update the Weight[Start, Stop] using subtractive path.\r
             //\r
             MtrrLibCalculateSubtractivePath (\r
-              DefaultType, A0,\r
-              Ranges, RangeCount,\r
-              (UINT16)VertexCount, Vertices, Weight,\r
-              Start, Stop, Type, TypeCount,\r
-              NULL, 0, NULL\r
+              DefaultType,\r
+              A0,\r
+              Ranges,\r
+              RangeCount,\r
+              (UINT16)VertexCount,\r
+              Vertices,\r
+              Weight,\r
+              Start,\r
+              Stop,\r
+              Type,\r
+              TypeCount,\r
+              NULL,\r
+              0,\r
+              NULL\r
               );\r
           } else if (TypeCount == 2) {\r
             //\r
@@ -1617,19 +1679,22 @@ MtrrLibCalculateMtrrs (
   }\r
 \r
   Status = RETURN_SUCCESS;\r
-  MtrrLibCalculateLeastMtrrs ((UINT16) VertexCount, Vertices, Weight, 0, (UINT16) VertexCount - 1, FALSE);\r
-  Stop = (UINT16) VertexCount - 1;\r
+  MtrrLibCalculateLeastMtrrs ((UINT16)VertexCount, Vertices, Weight, 0, (UINT16)VertexCount - 1, FALSE);\r
+  Stop = (UINT16)VertexCount - 1;\r
   while (Stop != 0) {\r
-    Start = Vertices[Stop].Previous;\r
+    Start     = Vertices[Stop].Previous;\r
     TypeCount = MAX_UINT8;\r
-    Type = 0;\r
-    if (Weight[M(Start, Stop)] != 0) {\r
+    Type      = 0;\r
+    if (Weight[M (Start, Stop)] != 0) {\r
       TypeCount = MtrrLibGetNumberOfTypes (Ranges, RangeCount, Vertices[Start].Address, Vertices[Stop].Address - Vertices[Start].Address, &Type);\r
-      Status = MtrrLibAppendVariableMtrr (\r
-        Mtrrs, MtrrCapacity, MtrrCount,\r
-        Vertices[Start].Address, Vertices[Stop].Address - Vertices[Start].Address,\r
-        MtrrLibLowestType (Type)\r
-        );\r
+      Status    = MtrrLibAppendVariableMtrr (\r
+                    Mtrrs,\r
+                    MtrrCapacity,\r
+                    MtrrCount,\r
+                    Vertices[Start].Address,\r
+                    Vertices[Stop].Address - Vertices[Start].Address,\r
+                    MtrrLibLowestType (Type)\r
+                    );\r
       if (RETURN_ERROR (Status)) {\r
         break;\r
       }\r
@@ -1641,26 +1706,41 @@ MtrrLibCalculateMtrrs (
       //\r
       if (TypeCount == MAX_UINT8) {\r
         TypeCount = MtrrLibGetNumberOfTypes (\r
-                      Ranges, RangeCount, Vertices[Start].Address, Vertices[Stop].Address - Vertices[Start].Address, &Type\r
+                      Ranges,\r
+                      RangeCount,\r
+                      Vertices[Start].Address,\r
+                      Vertices[Stop].Address - Vertices[Start].Address,\r
+                      &Type\r
                       );\r
       }\r
+\r
       Status = MtrrLibCalculateSubtractivePath (\r
-                 DefaultType, A0,\r
-                 Ranges, RangeCount,\r
-                 (UINT16) VertexCount, Vertices, Weight, Start, Stop,\r
-                 Type, TypeCount,\r
-                 Mtrrs, MtrrCapacity, MtrrCount\r
+                 DefaultType,\r
+                 A0,\r
+                 Ranges,\r
+                 RangeCount,\r
+                 (UINT16)VertexCount,\r
+                 Vertices,\r
+                 Weight,\r
+                 Start,\r
+                 Stop,\r
+                 Type,\r
+                 TypeCount,\r
+                 Mtrrs,\r
+                 MtrrCapacity,\r
+                 MtrrCount\r
                  );\r
       if (RETURN_ERROR (Status)) {\r
         break;\r
       }\r
     }\r
+\r
     Stop = Start;\r
   }\r
+\r
   return Status;\r
 }\r
 \r
-\r
 /**\r
   Apply the fixed MTRR settings to memory range array.\r
 \r
@@ -1681,26 +1761,33 @@ MtrrLibApplyFixedMtrrs (
   IN OUT UINTN                *RangeCount\r
   )\r
 {\r
-  RETURN_STATUS               Status;\r
-  UINTN                       MsrIndex;\r
-  UINTN                       Index;\r
-  MTRR_MEMORY_CACHE_TYPE      MemoryType;\r
-  UINT64                      Base;\r
+  RETURN_STATUS           Status;\r
+  UINTN                   MsrIndex;\r
+  UINTN                   Index;\r
+  MTRR_MEMORY_CACHE_TYPE  MemoryType;\r
+  UINT64                  Base;\r
 \r
   Base = 0;\r
   for (MsrIndex = 0; MsrIndex < ARRAY_SIZE (mMtrrLibFixedMtrrTable); MsrIndex++) {\r
     ASSERT (Base == mMtrrLibFixedMtrrTable[MsrIndex].BaseAddress);\r
     for (Index = 0; Index < sizeof (UINT64); Index++) {\r
       MemoryType = (MTRR_MEMORY_CACHE_TYPE)((UINT8 *)(&Fixed->Mtrr[MsrIndex]))[Index];\r
-      Status = MtrrLibSetMemoryType (\r
-                 Ranges, RangeCapacity, RangeCount, Base, mMtrrLibFixedMtrrTable[MsrIndex].Length, MemoryType\r
-                 );\r
+      Status     = MtrrLibSetMemoryType (\r
+                     Ranges,\r
+                     RangeCapacity,\r
+                     RangeCount,\r
+                     Base,\r
+                     mMtrrLibFixedMtrrTable[MsrIndex].Length,\r
+                     MemoryType\r
+                     );\r
       if (Status == RETURN_OUT_OF_RESOURCES) {\r
         return Status;\r
       }\r
+\r
       Base += mMtrrLibFixedMtrrTable[MsrIndex].Length;\r
     }\r
   }\r
+\r
   ASSERT (Base == BASE_1MB);\r
   return RETURN_SUCCESS;\r
 }\r
@@ -1719,15 +1806,15 @@ MtrrLibApplyFixedMtrrs (
 **/\r
 RETURN_STATUS\r
 MtrrLibApplyVariableMtrrs (\r
-  IN     CONST MTRR_MEMORY_RANGE *VariableMtrr,\r
-  IN     UINT32                  VariableMtrrCount,\r
-  IN OUT MTRR_MEMORY_RANGE       *Ranges,\r
-  IN     UINTN                   RangeCapacity,\r
-  IN OUT UINTN                   *RangeCount\r
+  IN     CONST MTRR_MEMORY_RANGE  *VariableMtrr,\r
+  IN     UINT32                   VariableMtrrCount,\r
+  IN OUT MTRR_MEMORY_RANGE        *Ranges,\r
+  IN     UINTN                    RangeCapacity,\r
+  IN OUT UINTN                    *RangeCount\r
   )\r
 {\r
-  RETURN_STATUS                  Status;\r
-  UINTN                          Index;\r
+  RETURN_STATUS  Status;\r
+  UINTN          Index;\r
 \r
   //\r
   // WT > WB\r
@@ -1741,9 +1828,13 @@ MtrrLibApplyVariableMtrrs (
   for (Index = 0; Index < VariableMtrrCount; Index++) {\r
     if ((VariableMtrr[Index].Length != 0) && (VariableMtrr[Index].Type == CacheWriteBack)) {\r
       Status = MtrrLibSetMemoryType (\r
-        Ranges, RangeCapacity, RangeCount,\r
-        VariableMtrr[Index].BaseAddress, VariableMtrr[Index].Length, VariableMtrr[Index].Type\r
-      );\r
+                 Ranges,\r
+                 RangeCapacity,\r
+                 RangeCount,\r
+                 VariableMtrr[Index].BaseAddress,\r
+                 VariableMtrr[Index].Length,\r
+                 VariableMtrr[Index].Type\r
+                 );\r
       if (Status == RETURN_OUT_OF_RESOURCES) {\r
         return Status;\r
       }\r
@@ -1755,10 +1846,15 @@ MtrrLibApplyVariableMtrrs (
   //\r
   for (Index = 0; Index < VariableMtrrCount; Index++) {\r
     if ((VariableMtrr[Index].Length != 0) &&\r
-        (VariableMtrr[Index].Type != CacheWriteBack) && (VariableMtrr[Index].Type != CacheUncacheable)) {\r
+        (VariableMtrr[Index].Type != CacheWriteBack) && (VariableMtrr[Index].Type != CacheUncacheable))\r
+    {\r
       Status = MtrrLibSetMemoryType (\r
-                 Ranges, RangeCapacity, RangeCount,\r
-                 VariableMtrr[Index].BaseAddress, VariableMtrr[Index].Length, VariableMtrr[Index].Type\r
+                 Ranges,\r
+                 RangeCapacity,\r
+                 RangeCount,\r
+                 VariableMtrr[Index].BaseAddress,\r
+                 VariableMtrr[Index].Length,\r
+                 VariableMtrr[Index].Type\r
                  );\r
       if (Status == RETURN_OUT_OF_RESOURCES) {\r
         return Status;\r
@@ -1770,16 +1866,21 @@ MtrrLibApplyVariableMtrrs (
   // 3. Set UC\r
   //\r
   for (Index = 0; Index < VariableMtrrCount; Index++) {\r
-    if (VariableMtrr[Index].Length != 0 && VariableMtrr[Index].Type == CacheUncacheable) {\r
+    if ((VariableMtrr[Index].Length != 0) && (VariableMtrr[Index].Type == CacheUncacheable)) {\r
       Status = MtrrLibSetMemoryType (\r
-                 Ranges, RangeCapacity, RangeCount,\r
-                 VariableMtrr[Index].BaseAddress, VariableMtrr[Index].Length, VariableMtrr[Index].Type\r
+                 Ranges,\r
+                 RangeCapacity,\r
+                 RangeCount,\r
+                 VariableMtrr[Index].BaseAddress,\r
+                 VariableMtrr[Index].Length,\r
+                 VariableMtrr[Index].Type\r
                  );\r
       if (Status == RETURN_OUT_OF_RESOURCES) {\r
         return Status;\r
       }\r
     }\r
   }\r
+\r
   return RETURN_SUCCESS;\r
 }\r
 \r
@@ -1794,35 +1895,37 @@ MtrrLibApplyVariableMtrrs (
 **/\r
 UINT8\r
 MtrrLibGetCompatibleTypes (\r
-  IN CONST MTRR_MEMORY_RANGE *Ranges,\r
-  IN UINTN                   RangeCount\r
+  IN CONST MTRR_MEMORY_RANGE  *Ranges,\r
+  IN UINTN                    RangeCount\r
   )\r
 {\r
   ASSERT (RangeCount != 0);\r
 \r
   switch (Ranges[0].Type) {\r
-  case CacheWriteBack:\r
-  case CacheWriteThrough:\r
-    return (1 << CacheWriteBack) | (1 << CacheWriteThrough) | (1 << CacheUncacheable);\r
-    break;\r
-\r
-  case CacheWriteCombining:\r
-  case CacheWriteProtected:\r
-    return (1 << Ranges[0].Type) | (1 << CacheUncacheable);\r
-    break;\r
-\r
-  case CacheUncacheable:\r
-    if (RangeCount == 1) {\r
-      return (1 << CacheUncacheable);\r
-    }\r
-    return MtrrLibGetCompatibleTypes (&Ranges[1], RangeCount - 1);\r
-    break;\r
+    case CacheWriteBack:\r
+    case CacheWriteThrough:\r
+      return (1 << CacheWriteBack) | (1 << CacheWriteThrough) | (1 << CacheUncacheable);\r
+      break;\r
+\r
+    case CacheWriteCombining:\r
+    case CacheWriteProtected:\r
+      return (1 << Ranges[0].Type) | (1 << CacheUncacheable);\r
+      break;\r
+\r
+    case CacheUncacheable:\r
+      if (RangeCount == 1) {\r
+        return (1 << CacheUncacheable);\r
+      }\r
 \r
-  case CacheInvalid:\r
-  default:\r
-    ASSERT (FALSE);\r
-    break;\r
+      return MtrrLibGetCompatibleTypes (&Ranges[1], RangeCount - 1);\r
+      break;\r
+\r
+    case CacheInvalid:\r
+    default:\r
+      ASSERT (FALSE);\r
+      break;\r
   }\r
+\r
   return 0;\r
 }\r
 \r
@@ -1839,15 +1942,15 @@ MtrrLibGetCompatibleTypes (
 **/\r
 VOID\r
 MtrrLibMergeVariableMtrr (\r
-  MTRR_MEMORY_RANGE *DstMtrrs,\r
-  UINT32            DstMtrrCount,\r
-  MTRR_MEMORY_RANGE *SrcMtrrs,\r
-  UINT32            SrcMtrrCount,\r
-  BOOLEAN           *Modified\r
+  MTRR_MEMORY_RANGE  *DstMtrrs,\r
+  UINT32             DstMtrrCount,\r
+  MTRR_MEMORY_RANGE  *SrcMtrrs,\r
+  UINT32             SrcMtrrCount,\r
+  BOOLEAN            *Modified\r
   )\r
 {\r
-  UINT32          DstIndex;\r
-  UINT32          SrcIndex;\r
+  UINT32  DstIndex;\r
+  UINT32  SrcIndex;\r
 \r
   ASSERT (SrcMtrrCount <= DstMtrrCount);\r
 \r
@@ -1857,10 +1960,12 @@ MtrrLibMergeVariableMtrr (
     if (DstMtrrs[DstIndex].Length == 0) {\r
       continue;\r
     }\r
+\r
     for (SrcIndex = 0; SrcIndex < SrcMtrrCount; SrcIndex++) {\r
-      if (DstMtrrs[DstIndex].BaseAddress == SrcMtrrs[SrcIndex].BaseAddress &&\r
-        DstMtrrs[DstIndex].Length == SrcMtrrs[SrcIndex].Length &&\r
-        DstMtrrs[DstIndex].Type == SrcMtrrs[SrcIndex].Type) {\r
+      if ((DstMtrrs[DstIndex].BaseAddress == SrcMtrrs[SrcIndex].BaseAddress) &&\r
+          (DstMtrrs[DstIndex].Length == SrcMtrrs[SrcIndex].Length) &&\r
+          (DstMtrrs[DstIndex].Type == SrcMtrrs[SrcIndex].Type))\r
+      {\r
         break;\r
       }\r
     }\r
@@ -1870,7 +1975,7 @@ MtrrLibMergeVariableMtrr (
       // Remove the one from DstMtrrs which is not in SrcMtrrs\r
       //\r
       DstMtrrs[DstIndex].Length = 0;\r
-      Modified[DstIndex] = TRUE;\r
+      Modified[DstIndex]        = TRUE;\r
     } else {\r
       //\r
       // Remove the one from SrcMtrrs which is also in DstMtrrs\r
@@ -1886,7 +1991,6 @@ MtrrLibMergeVariableMtrr (
   DstIndex = 0;\r
   for (SrcIndex = 0; SrcIndex < SrcMtrrCount; SrcIndex++) {\r
     if (SrcMtrrs[SrcIndex].Length != 0) {\r
-\r
       //\r
       // Find the empty slot in DstMtrrs\r
       //\r
@@ -1894,8 +1998,10 @@ MtrrLibMergeVariableMtrr (
         if (DstMtrrs[DstIndex].Length == 0) {\r
           break;\r
         }\r
+\r
         DstIndex++;\r
       }\r
+\r
       ASSERT (DstIndex < DstMtrrCount);\r
       CopyMem (&DstMtrrs[DstIndex], &SrcMtrrs[SrcIndex], sizeof (SrcMtrrs[0]));\r
       Modified[DstIndex] = TRUE;\r
@@ -1924,27 +2030,27 @@ MtrrLibMergeVariableMtrr (
 **/\r
 RETURN_STATUS\r
 MtrrLibSetMemoryRanges (\r
-  IN MTRR_MEMORY_CACHE_TYPE DefaultType,\r
-  IN UINT64                 A0,\r
-  IN MTRR_MEMORY_RANGE      *Ranges,\r
-  IN UINTN                  RangeCount,\r
-  IN VOID                   *Scratch,\r
-  IN OUT UINTN              *ScratchSize,\r
-  OUT MTRR_MEMORY_RANGE     *VariableMtrr,\r
-  IN UINT32                 VariableMtrrCapacity,\r
-  OUT UINT32                *VariableMtrrCount\r
+  IN MTRR_MEMORY_CACHE_TYPE  DefaultType,\r
+  IN UINT64                  A0,\r
+  IN MTRR_MEMORY_RANGE       *Ranges,\r
+  IN UINTN                   RangeCount,\r
+  IN VOID                    *Scratch,\r
+  IN OUT UINTN               *ScratchSize,\r
+  OUT MTRR_MEMORY_RANGE      *VariableMtrr,\r
+  IN UINT32                  VariableMtrrCapacity,\r
+  OUT UINT32                 *VariableMtrrCount\r
   )\r
 {\r
-  RETURN_STATUS             Status;\r
-  UINT32                    Index;\r
-  UINT64                    Base0;\r
-  UINT64                    Base1;\r
-  UINT64                    Alignment;\r
-  UINT8                     CompatibleTypes;\r
-  UINT64                    Length;\r
-  UINT32                    End;\r
-  UINTN                     ActualScratchSize;\r
-  UINTN                     BiggestScratchSize;\r
+  RETURN_STATUS  Status;\r
+  UINT32         Index;\r
+  UINT64         Base0;\r
+  UINT64         Base1;\r
+  UINT64         Alignment;\r
+  UINT8          CompatibleTypes;\r
+  UINT64         Length;\r
+  UINT32         End;\r
+  UINTN          ActualScratchSize;\r
+  UINTN          BiggestScratchSize;\r
 \r
   *VariableMtrrCount = 0;\r
 \r
@@ -1969,21 +2075,26 @@ MtrrLibSetMemoryRanges (
       while (Base0 + Alignment <= Ranges[Index].BaseAddress + Ranges[Index].Length) {\r
         if ((BiggestScratchSize <= *ScratchSize) && (Ranges[Index].Type != DefaultType)) {\r
           Status = MtrrLibAppendVariableMtrr (\r
-            VariableMtrr, VariableMtrrCapacity, VariableMtrrCount,\r
-            Base0, Alignment, Ranges[Index].Type\r
-            );\r
+                     VariableMtrr,\r
+                     VariableMtrrCapacity,\r
+                     VariableMtrrCount,\r
+                     Base0,\r
+                     Alignment,\r
+                     Ranges[Index].Type\r
+                     );\r
           if (RETURN_ERROR (Status)) {\r
             return Status;\r
           }\r
         }\r
-        Base0 += Alignment;\r
+\r
+        Base0    += Alignment;\r
         Alignment = MtrrLibBiggestAlignment (Base0, A0);\r
       }\r
 \r
       //\r
       // Remove the above range from Ranges[Index]\r
       //\r
-      Ranges[Index].Length -= Base0 - Ranges[Index].BaseAddress;\r
+      Ranges[Index].Length     -= Base0 - Ranges[Index].BaseAddress;\r
       Ranges[Index].BaseAddress = Base0;\r
       if (Ranges[Index].Length != 0) {\r
         break;\r
@@ -2010,8 +2121,10 @@ MtrrLibSetMemoryRanges (
       if (((1 << Ranges[End + 1].Type) & CompatibleTypes) == 0) {\r
         break;\r
       }\r
+\r
       End++;\r
     }\r
+\r
     Alignment = MtrrLibBiggestAlignment (Base0, A0);\r
     Length    = GetPowerOfTwo64 (Ranges[End].BaseAddress + Ranges[End].Length - Base0);\r
     Base1     = Base0 + MIN (Alignment, Length);\r
@@ -2024,18 +2137,24 @@ MtrrLibSetMemoryRanges (
       if (Base1 <= Ranges[End + 1].BaseAddress) {\r
         break;\r
       }\r
+\r
       End++;\r
     }\r
 \r
-    Length = Ranges[End].Length;\r
+    Length             = Ranges[End].Length;\r
     Ranges[End].Length = Base1 - Ranges[End].BaseAddress;\r
     ActualScratchSize  = *ScratchSize;\r
-    Status = MtrrLibCalculateMtrrs (\r
-               DefaultType, A0,\r
-               &Ranges[Index], End + 1 - Index,\r
-               Scratch, &ActualScratchSize,\r
-               VariableMtrr, VariableMtrrCapacity, VariableMtrrCount\r
-               );\r
+    Status             = MtrrLibCalculateMtrrs (\r
+                           DefaultType,\r
+                           A0,\r
+                           &Ranges[Index],\r
+                           End + 1 - Index,\r
+                           Scratch,\r
+                           &ActualScratchSize,\r
+                           VariableMtrr,\r
+                           VariableMtrrCapacity,\r
+                           VariableMtrrCount\r
+                           );\r
     if (Status == RETURN_BUFFER_TOO_SMALL) {\r
       BiggestScratchSize = MAX (BiggestScratchSize, ActualScratchSize);\r
       //\r
@@ -2044,14 +2163,15 @@ MtrrLibSetMemoryRanges (
       //\r
       Status = RETURN_SUCCESS;\r
     }\r
+\r
     if (RETURN_ERROR (Status)) {\r
       return Status;\r
     }\r
 \r
     if (Length != Ranges[End].Length) {\r
       Ranges[End].BaseAddress = Base1;\r
-      Ranges[End].Length = Length - Ranges[End].Length;\r
-      Index = End;\r
+      Ranges[End].Length      = Length - Ranges[End].Length;\r
+      Index                   = End;\r
     } else {\r
       Index = End + 1;\r
     }\r
@@ -2061,6 +2181,7 @@ MtrrLibSetMemoryRanges (
     *ScratchSize = BiggestScratchSize;\r
     return RETURN_BUFFER_TOO_SMALL;\r
   }\r
+\r
   return RETURN_SUCCESS;\r
 }\r
 \r
@@ -2080,17 +2201,17 @@ MtrrLibSetMemoryRanges (
 **/\r
 RETURN_STATUS\r
 MtrrLibSetBelow1MBMemoryAttribute (\r
-  IN OUT UINT64                  *ClearMasks,\r
-  IN OUT UINT64                  *OrMasks,\r
-  IN PHYSICAL_ADDRESS            BaseAddress,\r
-  IN UINT64                      Length,\r
-  IN MTRR_MEMORY_CACHE_TYPE      Type\r
+  IN OUT UINT64              *ClearMasks,\r
+  IN OUT UINT64              *OrMasks,\r
+  IN PHYSICAL_ADDRESS        BaseAddress,\r
+  IN UINT64                  Length,\r
+  IN MTRR_MEMORY_CACHE_TYPE  Type\r
   )\r
 {\r
-  RETURN_STATUS             Status;\r
-  UINT32                    MsrIndex;\r
-  UINT64                    ClearMask;\r
-  UINT64                    OrMask;\r
+  RETURN_STATUS  Status;\r
+  UINT32         MsrIndex;\r
+  UINT64         ClearMask;\r
+  UINT64         OrMask;\r
 \r
   ASSERT (BaseAddress < BASE_1MB);\r
 \r
@@ -2100,9 +2221,11 @@ MtrrLibSetBelow1MBMemoryAttribute (
     if (RETURN_ERROR (Status)) {\r
       return Status;\r
     }\r
+\r
     ClearMasks[MsrIndex] = ClearMasks[MsrIndex] | ClearMask;\r
     OrMasks[MsrIndex]    = (OrMasks[MsrIndex] & ~ClearMask) | OrMask;\r
   }\r
+\r
   return RETURN_SUCCESS;\r
 }\r
 \r
@@ -2135,39 +2258,39 @@ MtrrLibSetBelow1MBMemoryAttribute (
 RETURN_STATUS\r
 EFIAPI\r
 MtrrSetMemoryAttributesInMtrrSettings (\r
-  IN OUT MTRR_SETTINGS           *MtrrSetting,\r
-  IN     VOID                    *Scratch,\r
-  IN OUT UINTN                   *ScratchSize,\r
-  IN     CONST MTRR_MEMORY_RANGE *Ranges,\r
-  IN     UINTN                   RangeCount\r
+  IN OUT MTRR_SETTINGS            *MtrrSetting,\r
+  IN     VOID                     *Scratch,\r
+  IN OUT UINTN                    *ScratchSize,\r
+  IN     CONST MTRR_MEMORY_RANGE  *Ranges,\r
+  IN     UINTN                    RangeCount\r
   )\r
 {\r
-  RETURN_STATUS             Status;\r
-  UINT32                    Index;\r
-  UINT64                    BaseAddress;\r
-  UINT64                    Length;\r
-  BOOLEAN                   Above1MbExist;\r
-\r
-  UINT64                    MtrrValidBitsMask;\r
-  UINT64                    MtrrValidAddressMask;\r
-  MTRR_MEMORY_CACHE_TYPE    DefaultType;\r
-  MTRR_VARIABLE_SETTINGS    VariableSettings;\r
-  MTRR_MEMORY_RANGE         WorkingRanges[2 * ARRAY_SIZE (MtrrSetting->Variables.Mtrr) + 2];\r
-  UINTN                     WorkingRangeCount;\r
-  BOOLEAN                   Modified;\r
-  MTRR_VARIABLE_SETTING     VariableSetting;\r
-  UINT32                    OriginalVariableMtrrCount;\r
-  UINT32                    FirmwareVariableMtrrCount;\r
-  UINT32                    WorkingVariableMtrrCount;\r
-  MTRR_MEMORY_RANGE         OriginalVariableMtrr[ARRAY_SIZE (MtrrSetting->Variables.Mtrr)];\r
-  MTRR_MEMORY_RANGE         WorkingVariableMtrr[ARRAY_SIZE (MtrrSetting->Variables.Mtrr)];\r
-  BOOLEAN                   VariableSettingModified[ARRAY_SIZE (MtrrSetting->Variables.Mtrr)];\r
-\r
-  UINT64                    ClearMasks[ARRAY_SIZE (mMtrrLibFixedMtrrTable)];\r
-  UINT64                    OrMasks[ARRAY_SIZE (mMtrrLibFixedMtrrTable)];\r
-\r
-  MTRR_CONTEXT              MtrrContext;\r
-  BOOLEAN                   MtrrContextValid;\r
+  RETURN_STATUS  Status;\r
+  UINT32         Index;\r
+  UINT64         BaseAddress;\r
+  UINT64         Length;\r
+  BOOLEAN        Above1MbExist;\r
+\r
+  UINT64                  MtrrValidBitsMask;\r
+  UINT64                  MtrrValidAddressMask;\r
+  MTRR_MEMORY_CACHE_TYPE  DefaultType;\r
+  MTRR_VARIABLE_SETTINGS  VariableSettings;\r
+  MTRR_MEMORY_RANGE       WorkingRanges[2 * ARRAY_SIZE (MtrrSetting->Variables.Mtrr) + 2];\r
+  UINTN                   WorkingRangeCount;\r
+  BOOLEAN                 Modified;\r
+  MTRR_VARIABLE_SETTING   VariableSetting;\r
+  UINT32                  OriginalVariableMtrrCount;\r
+  UINT32                  FirmwareVariableMtrrCount;\r
+  UINT32                  WorkingVariableMtrrCount;\r
+  MTRR_MEMORY_RANGE       OriginalVariableMtrr[ARRAY_SIZE (MtrrSetting->Variables.Mtrr)];\r
+  MTRR_MEMORY_RANGE       WorkingVariableMtrr[ARRAY_SIZE (MtrrSetting->Variables.Mtrr)];\r
+  BOOLEAN                 VariableSettingModified[ARRAY_SIZE (MtrrSetting->Variables.Mtrr)];\r
+\r
+  UINT64  ClearMasks[ARRAY_SIZE (mMtrrLibFixedMtrrTable)];\r
+  UINT64  OrMasks[ARRAY_SIZE (mMtrrLibFixedMtrrTable)];\r
+\r
+  MTRR_CONTEXT  MtrrContext;\r
+  BOOLEAN       MtrrContextValid;\r
 \r
   Status = RETURN_SUCCESS;\r
   MtrrLibInitializeMtrrMask (&MtrrValidBitsMask, &MtrrValidAddressMask);\r
@@ -2187,16 +2310,23 @@ MtrrSetMemoryAttributesInMtrrSettings (
   // 0. Dump the requests.\r
   //\r
   DEBUG_CODE_BEGIN ();\r
-    DEBUG ((DEBUG_CACHE, "Mtrr: Set Mem Attribute to %a, ScratchSize = %x%a",\r
-            (MtrrSetting == NULL) ? "Hardware" : "Buffer", *ScratchSize,\r
-            (RangeCount <= 1) ? "," : "\n"\r
-            ));\r
-    for (Index = 0; Index < RangeCount; Index++) {\r
-      DEBUG ((DEBUG_CACHE, " %a: [%016lx, %016lx)\n",\r
-              mMtrrMemoryCacheTypeShortName[MIN (Ranges[Index].Type, CacheInvalid)],\r
-              Ranges[Index].BaseAddress, Ranges[Index].BaseAddress + Ranges[Index].Length\r
-              ));\r
-    }\r
+  DEBUG ((\r
+    DEBUG_CACHE,\r
+    "Mtrr: Set Mem Attribute to %a, ScratchSize = %x%a",\r
+    (MtrrSetting == NULL) ? "Hardware" : "Buffer",\r
+    *ScratchSize,\r
+    (RangeCount <= 1) ? "," : "\n"\r
+    ));\r
+  for (Index = 0; Index < RangeCount; Index++) {\r
+    DEBUG ((\r
+      DEBUG_CACHE,\r
+      " %a: [%016lx, %016lx)\n",\r
+      mMtrrMemoryCacheTypeShortName[MIN (Ranges[Index].Type, CacheInvalid)],\r
+      Ranges[Index].BaseAddress,\r
+      Ranges[Index].BaseAddress + Ranges[Index].Length\r
+      ));\r
+  }\r
+\r
   DEBUG_CODE_END ();\r
 \r
   //\r
@@ -2212,10 +2342,12 @@ MtrrSetMemoryAttributesInMtrrSettings (
       Status = RETURN_INVALID_PARAMETER;\r
       goto Exit;\r
     }\r
+\r
     if (((Ranges[Index].BaseAddress & ~MtrrValidAddressMask) != 0) ||\r
         ((((Ranges[Index].BaseAddress + Ranges[Index].Length) & ~MtrrValidAddressMask) != 0) &&\r
-          (Ranges[Index].BaseAddress + Ranges[Index].Length) != MtrrValidBitsMask + 1)\r
-        ) {\r
+         ((Ranges[Index].BaseAddress + Ranges[Index].Length) != MtrrValidBitsMask + 1))\r
+        )\r
+    {\r
       //\r
       // Either the BaseAddress or the Limit doesn't follow the alignment requirement.\r
       // Note: It's still valid if Limit doesn't follow the alignment requirement but equals to MAX Address.\r
@@ -2223,14 +2355,17 @@ MtrrSetMemoryAttributesInMtrrSettings (
       Status = RETURN_UNSUPPORTED;\r
       goto Exit;\r
     }\r
+\r
     if ((Ranges[Index].Type != CacheUncacheable) &&\r
         (Ranges[Index].Type != CacheWriteCombining) &&\r
         (Ranges[Index].Type != CacheWriteThrough) &&\r
         (Ranges[Index].Type != CacheWriteProtected) &&\r
-        (Ranges[Index].Type != CacheWriteBack)) {\r
+        (Ranges[Index].Type != CacheWriteBack))\r
+    {\r
       Status = RETURN_INVALID_PARAMETER;\r
       goto Exit;\r
     }\r
+\r
     if (Ranges[Index].BaseAddress + Ranges[Index].Length > BASE_1MB) {\r
       Above1MbExist = TRUE;\r
     }\r
@@ -2246,19 +2381,26 @@ MtrrSetMemoryAttributesInMtrrSettings (
     OriginalVariableMtrrCount = GetVariableMtrrCountWorker ();\r
     MtrrGetVariableMtrrWorker (MtrrSetting, OriginalVariableMtrrCount, &VariableSettings);\r
     MtrrLibGetRawVariableRanges (\r
-      &VariableSettings, OriginalVariableMtrrCount,\r
-      MtrrValidBitsMask, MtrrValidAddressMask, OriginalVariableMtrr\r
+      &VariableSettings,\r
+      OriginalVariableMtrrCount,\r
+      MtrrValidBitsMask,\r
+      MtrrValidAddressMask,\r
+      OriginalVariableMtrr\r
       );\r
 \r
-    DefaultType = MtrrGetDefaultMemoryTypeWorker (MtrrSetting);\r
-    WorkingRangeCount = 1;\r
+    DefaultType                  = MtrrGetDefaultMemoryTypeWorker (MtrrSetting);\r
+    WorkingRangeCount            = 1;\r
     WorkingRanges[0].BaseAddress = 0;\r
     WorkingRanges[0].Length      = MtrrValidBitsMask + 1;\r
     WorkingRanges[0].Type        = DefaultType;\r
 \r
     Status = MtrrLibApplyVariableMtrrs (\r
-               OriginalVariableMtrr, OriginalVariableMtrrCount,\r
-               WorkingRanges, ARRAY_SIZE (WorkingRanges), &WorkingRangeCount);\r
+               OriginalVariableMtrr,\r
+               OriginalVariableMtrrCount,\r
+               WorkingRanges,\r
+               ARRAY_SIZE (WorkingRanges),\r
+               &WorkingRangeCount\r
+               );\r
     ASSERT_RETURN_ERROR (Status);\r
 \r
     ASSERT (OriginalVariableMtrrCount >= PcdGet32 (PcdCpuNumberOfReservedVariableMtrrs));\r
@@ -2269,8 +2411,12 @@ MtrrSetMemoryAttributesInMtrrSettings (
     // 2.2. Force [0, 1M) to UC, so that it doesn't impact subtraction algorithm.\r
     //\r
     Status = MtrrLibSetMemoryType (\r
-               WorkingRanges, ARRAY_SIZE (WorkingRanges), &WorkingRangeCount,\r
-               0, SIZE_1MB, CacheUncacheable\r
+               WorkingRanges,\r
+               ARRAY_SIZE (WorkingRanges),\r
+               &WorkingRangeCount,\r
+               0,\r
+               SIZE_1MB,\r
+               CacheUncacheable\r
                );\r
     ASSERT (Status != RETURN_OUT_OF_RESOURCES);\r
 \r
@@ -2280,17 +2426,23 @@ MtrrSetMemoryAttributesInMtrrSettings (
     Modified = FALSE;\r
     for (Index = 0; Index < RangeCount; Index++) {\r
       BaseAddress = Ranges[Index].BaseAddress;\r
-      Length = Ranges[Index].Length;\r
+      Length      = Ranges[Index].Length;\r
       if (BaseAddress < BASE_1MB) {\r
         if (Length <= BASE_1MB - BaseAddress) {\r
           continue;\r
         }\r
-        Length -= BASE_1MB - BaseAddress;\r
+\r
+        Length     -= BASE_1MB - BaseAddress;\r
         BaseAddress = BASE_1MB;\r
       }\r
+\r
       Status = MtrrLibSetMemoryType (\r
-                 WorkingRanges, ARRAY_SIZE (WorkingRanges), &WorkingRangeCount,\r
-                 BaseAddress, Length, Ranges[Index].Type\r
+                 WorkingRanges,\r
+                 ARRAY_SIZE (WorkingRanges),\r
+                 &WorkingRangeCount,\r
+                 BaseAddress,\r
+                 Length,\r
+                 Ranges[Index].Type\r
                  );\r
       if (Status == RETURN_ALREADY_STARTED) {\r
         Status = RETURN_SUCCESS;\r
@@ -2308,9 +2460,15 @@ MtrrSetMemoryAttributesInMtrrSettings (
       //      Buffer Too Small may be returned if the scratch buffer size is insufficient.\r
       //\r
       Status = MtrrLibSetMemoryRanges (\r
-                 DefaultType, LShiftU64 (1, (UINTN)HighBitSet64 (MtrrValidBitsMask)), WorkingRanges, WorkingRangeCount,\r
-                 Scratch, ScratchSize,\r
-                 WorkingVariableMtrr, FirmwareVariableMtrrCount + 1, &WorkingVariableMtrrCount\r
+                 DefaultType,\r
+                 LShiftU64 (1, (UINTN)HighBitSet64 (MtrrValidBitsMask)),\r
+                 WorkingRanges,\r
+                 WorkingRangeCount,\r
+                 Scratch,\r
+                 ScratchSize,\r
+                 WorkingVariableMtrr,\r
+                 FirmwareVariableMtrrCount + 1,\r
+                 &WorkingVariableMtrrCount\r
                  );\r
       if (RETURN_ERROR (Status)) {\r
         goto Exit;\r
@@ -2320,11 +2478,12 @@ MtrrSetMemoryAttributesInMtrrSettings (
       // 2.5. Remove the [0, 1MB) MTRR if it still exists (not merged with other range)\r
       //\r
       for (Index = 0; Index < WorkingVariableMtrrCount; Index++) {\r
-        if (WorkingVariableMtrr[Index].BaseAddress == 0 && WorkingVariableMtrr[Index].Length == SIZE_1MB) {\r
+        if ((WorkingVariableMtrr[Index].BaseAddress == 0) && (WorkingVariableMtrr[Index].Length == SIZE_1MB)) {\r
           ASSERT (WorkingVariableMtrr[Index].Type == CacheUncacheable);\r
           WorkingVariableMtrrCount--;\r
           CopyMem (\r
-            &WorkingVariableMtrr[Index], &WorkingVariableMtrr[Index + 1],\r
+            &WorkingVariableMtrr[Index],\r
+            &WorkingVariableMtrr[Index + 1],\r
             (WorkingVariableMtrrCount - Index) * sizeof (WorkingVariableMtrr[0])\r
             );\r
           break;\r
@@ -2341,10 +2500,12 @@ MtrrSetMemoryAttributesInMtrrSettings (
       //      Make sure least modification is made to OriginalVariableMtrr.\r
       //\r
       MtrrLibMergeVariableMtrr (\r
-        OriginalVariableMtrr, OriginalVariableMtrrCount,\r
-        WorkingVariableMtrr, WorkingVariableMtrrCount,\r
+        OriginalVariableMtrr,\r
+        OriginalVariableMtrrCount,\r
+        WorkingVariableMtrr,\r
+        WorkingVariableMtrrCount,\r
         VariableSettingModified\r
-      );\r
+        );\r
     }\r
   }\r
 \r
@@ -2361,8 +2522,11 @@ MtrrSetMemoryAttributesInMtrrSettings (
     }\r
 \r
     Status = MtrrLibSetBelow1MBMemoryAttribute (\r
-               ClearMasks, OrMasks,\r
-               Ranges[Index].BaseAddress, Ranges[Index].Length, Ranges[Index].Type\r
+               ClearMasks,\r
+               OrMasks,\r
+               Ranges[Index].BaseAddress,\r
+               Ranges[Index].Length,\r
+               Ranges[Index].Type\r
                );\r
     if (RETURN_ERROR (Status)) {\r
       goto Exit;\r
@@ -2382,6 +2546,7 @@ MtrrSetMemoryAttributesInMtrrSettings (
           MtrrLibPreMtrrChange (&MtrrContext);\r
           MtrrContextValid = TRUE;\r
         }\r
+\r
         AsmMsrAndThenOr64 (mMtrrLibFixedMtrrTable[Index].Msr, ~ClearMasks[Index], OrMasks[Index]);\r
       }\r
     }\r
@@ -2394,12 +2559,13 @@ MtrrSetMemoryAttributesInMtrrSettings (
     if (VariableSettingModified[Index]) {\r
       if (OriginalVariableMtrr[Index].Length != 0) {\r
         VariableSetting.Base = (OriginalVariableMtrr[Index].BaseAddress & MtrrValidAddressMask)\r
-                             | (UINT8)OriginalVariableMtrr[Index].Type;\r
+                               | (UINT8)OriginalVariableMtrr[Index].Type;\r
         VariableSetting.Mask = ((~(OriginalVariableMtrr[Index].Length - 1)) & MtrrValidAddressMask) | BIT11;\r
       } else {\r
         VariableSetting.Base = 0;\r
         VariableSetting.Mask = 0;\r
       }\r
+\r
       if (MtrrSetting != NULL) {\r
         CopyMem (&MtrrSetting->Variables.Mtrr[Index], &VariableSetting, sizeof (VariableSetting));\r
       } else {\r
@@ -2407,20 +2573,21 @@ MtrrSetMemoryAttributesInMtrrSettings (
           MtrrLibPreMtrrChange (&MtrrContext);\r
           MtrrContextValid = TRUE;\r
         }\r
+\r
         AsmWriteMsr64 (\r
           MSR_IA32_MTRR_PHYSBASE0 + (Index << 1),\r
           VariableSetting.Base\r
-        );\r
+          );\r
         AsmWriteMsr64 (\r
           MSR_IA32_MTRR_PHYSMASK0 + (Index << 1),\r
           VariableSetting.Mask\r
-        );\r
+          );\r
       }\r
     }\r
   }\r
 \r
   if (MtrrSetting != NULL) {\r
-    ((MSR_IA32_MTRR_DEF_TYPE_REGISTER *)&MtrrSetting->MtrrDefType)->Bits.E = 1;\r
+    ((MSR_IA32_MTRR_DEF_TYPE_REGISTER *)&MtrrSetting->MtrrDefType)->Bits.E  = 1;\r
     ((MSR_IA32_MTRR_DEF_TYPE_REGISTER *)&MtrrSetting->MtrrDefType)->Bits.FE = 1;\r
   } else {\r
     if (MtrrContextValid) {\r
@@ -2433,6 +2600,7 @@ Exit:
   if (!RETURN_ERROR (Status)) {\r
     MtrrDebugPrintAllMtrrsWorker (MtrrSetting);\r
   }\r
+\r
   return Status;\r
 }\r
 \r
@@ -2474,14 +2642,14 @@ MtrrSetMemoryAttributeInMtrrSettings (
   IN MTRR_MEMORY_CACHE_TYPE  Attribute\r
   )\r
 {\r
-  UINT8                      Scratch[SCRATCH_BUFFER_SIZE];\r
-  UINTN                      ScratchSize;\r
-  MTRR_MEMORY_RANGE          Range;\r
+  UINT8              Scratch[SCRATCH_BUFFER_SIZE];\r
+  UINTN              ScratchSize;\r
+  MTRR_MEMORY_RANGE  Range;\r
 \r
   Range.BaseAddress = BaseAddress;\r
   Range.Length      = Length;\r
   Range.Type        = Attribute;\r
-  ScratchSize = sizeof (Scratch);\r
+  ScratchSize       = sizeof (Scratch);\r
   return MtrrSetMemoryAttributesInMtrrSettings (MtrrSetting, Scratch, &ScratchSize, &Range, 1);\r
 }\r
 \r
@@ -2537,7 +2705,7 @@ MtrrSetMemoryAttribute (
 **/\r
 VOID\r
 MtrrSetVariableMtrrWorker (\r
-  IN MTRR_VARIABLE_SETTINGS         *VariableSettings\r
+  IN MTRR_VARIABLE_SETTINGS  *VariableSettings\r
   )\r
 {\r
   UINT32  Index;\r
@@ -2566,20 +2734,19 @@ MtrrSetVariableMtrrWorker (
 **/\r
 VOID\r
 MtrrSetFixedMtrrWorker (\r
-  IN MTRR_FIXED_SETTINGS          *FixedSettings\r
+  IN MTRR_FIXED_SETTINGS  *FixedSettings\r
   )\r
 {\r
   UINT32  Index;\r
 \r
   for (Index = 0; Index < MTRR_NUMBER_OF_FIXED_MTRR; Index++) {\r
-     AsmWriteMsr64 (\r
-       mMtrrLibFixedMtrrTable[Index].Msr,\r
-       FixedSettings->Mtrr[Index]\r
-       );\r
+    AsmWriteMsr64 (\r
+      mMtrrLibFixedMtrrTable[Index].Msr,\r
+      FixedSettings->Mtrr[Index]\r
+      );\r
   }\r
 }\r
 \r
-\r
 /**\r
   This function gets the content in all MTRRs (variable and fixed)\r
 \r
@@ -2591,7 +2758,7 @@ MtrrSetFixedMtrrWorker (
 MTRR_SETTINGS *\r
 EFIAPI\r
 MtrrGetAllMtrrs (\r
-  OUT MTRR_SETTINGS                *MtrrSetting\r
+  OUT MTRR_SETTINGS  *MtrrSetting\r
   )\r
 {\r
   if (!IsMtrrSupported ()) {\r
@@ -2620,7 +2787,6 @@ MtrrGetAllMtrrs (
   return MtrrSetting;\r
 }\r
 \r
-\r
 /**\r
   This function sets all MTRRs (variable and fixed)\r
 \r
@@ -2632,7 +2798,7 @@ MtrrGetAllMtrrs (
 MTRR_SETTINGS *\r
 EFIAPI\r
 MtrrSetAllMtrrs (\r
-  IN MTRR_SETTINGS                *MtrrSetting\r
+  IN MTRR_SETTINGS  *MtrrSetting\r
   )\r
 {\r
   MTRR_CONTEXT  MtrrContext;\r
@@ -2663,7 +2829,6 @@ MtrrSetAllMtrrs (
   return MtrrSetting;\r
 }\r
 \r
-\r
 /**\r
   Checks if MTRR is supported.\r
 \r
@@ -2677,8 +2842,8 @@ IsMtrrSupported (
   VOID\r
   )\r
 {\r
-  CPUID_VERSION_INFO_EDX    Edx;\r
-  MSR_IA32_MTRRCAP_REGISTER MtrrCap;\r
+  CPUID_VERSION_INFO_EDX     Edx;\r
+  MSR_IA32_MTRRCAP_REGISTER  MtrrCap;\r
 \r
   //\r
   // Check CPUID(1).EDX[12] for MTRR capability\r
@@ -2697,10 +2862,10 @@ IsMtrrSupported (
   if ((MtrrCap.Bits.VCNT == 0) || (MtrrCap.Bits.FIX == 0)) {\r
     return FALSE;\r
   }\r
+\r
   return TRUE;\r
 }\r
 \r
-\r
 /**\r
   Worker function prints all MTRRs for debugging.\r
 \r
@@ -2712,93 +2877,109 @@ IsMtrrSupported (
 **/\r
 VOID\r
 MtrrDebugPrintAllMtrrsWorker (\r
-  IN MTRR_SETTINGS    *MtrrSetting\r
+  IN MTRR_SETTINGS  *MtrrSetting\r
   )\r
 {\r
   DEBUG_CODE_BEGIN ();\r
-    MTRR_SETTINGS     LocalMtrrs;\r
-    MTRR_SETTINGS     *Mtrrs;\r
-    UINTN             Index;\r
-    UINTN             RangeCount;\r
-    UINT64            MtrrValidBitsMask;\r
-    UINT64            MtrrValidAddressMask;\r
-    UINT32            VariableMtrrCount;\r
-    BOOLEAN           ContainVariableMtrr;\r
-    MTRR_MEMORY_RANGE Ranges[\r
-      ARRAY_SIZE (mMtrrLibFixedMtrrTable) * sizeof (UINT64) + 2 * ARRAY_SIZE (Mtrrs->Variables.Mtrr) + 1\r
-      ];\r
-    MTRR_MEMORY_RANGE RawVariableRanges[ARRAY_SIZE (Mtrrs->Variables.Mtrr)];\r
-\r
-    if (!IsMtrrSupported ()) {\r
-      return;\r
-    }\r
+  MTRR_SETTINGS      LocalMtrrs;\r
+  MTRR_SETTINGS      *Mtrrs;\r
+  UINTN              Index;\r
+  UINTN              RangeCount;\r
+  UINT64             MtrrValidBitsMask;\r
+  UINT64             MtrrValidAddressMask;\r
+  UINT32             VariableMtrrCount;\r
+  BOOLEAN            ContainVariableMtrr;\r
+  MTRR_MEMORY_RANGE  Ranges[\r
+                            ARRAY_SIZE (mMtrrLibFixedMtrrTable) * sizeof (UINT64) + 2 * ARRAY_SIZE (Mtrrs->Variables.Mtrr) + 1\r
+  ];\r
+  MTRR_MEMORY_RANGE  RawVariableRanges[ARRAY_SIZE (Mtrrs->Variables.Mtrr)];\r
 \r
-    VariableMtrrCount = GetVariableMtrrCountWorker ();\r
+  if (!IsMtrrSupported ()) {\r
+    return;\r
+  }\r
 \r
-    if (MtrrSetting != NULL) {\r
-      Mtrrs = MtrrSetting;\r
-    } else {\r
-      MtrrGetAllMtrrs (&LocalMtrrs);\r
-      Mtrrs = &LocalMtrrs;\r
-    }\r
+  VariableMtrrCount = GetVariableMtrrCountWorker ();\r
 \r
-    //\r
-    // Dump RAW MTRR contents\r
-    //\r
-    DEBUG ((DEBUG_CACHE, "MTRR Settings:\n"));\r
-    DEBUG ((DEBUG_CACHE, "=============\n"));\r
-    DEBUG ((DEBUG_CACHE, "MTRR Default Type: %016lx\n", Mtrrs->MtrrDefType));\r
-    for (Index = 0; Index < ARRAY_SIZE (mMtrrLibFixedMtrrTable); Index++) {\r
-      DEBUG ((DEBUG_CACHE, "Fixed MTRR[%02d]   : %016lx\n", Index, Mtrrs->Fixed.Mtrr[Index]));\r
-    }\r
-    ContainVariableMtrr = FALSE;\r
-    for (Index = 0; Index < VariableMtrrCount; Index++) {\r
-      if ((Mtrrs->Variables.Mtrr[Index].Mask & BIT11) == 0) {\r
-        //\r
-        // If mask is not valid, then do not display range\r
-        //\r
-        continue;\r
-      }\r
-      ContainVariableMtrr = TRUE;\r
-      DEBUG ((DEBUG_CACHE, "Variable MTRR[%02d]: Base=%016lx Mask=%016lx\n",\r
-        Index,\r
-        Mtrrs->Variables.Mtrr[Index].Base,\r
-        Mtrrs->Variables.Mtrr[Index].Mask\r
-        ));\r
-    }\r
-    if (!ContainVariableMtrr) {\r
-      DEBUG ((DEBUG_CACHE, "Variable MTRR    : None.\n"));\r
+  if (MtrrSetting != NULL) {\r
+    Mtrrs = MtrrSetting;\r
+  } else {\r
+    MtrrGetAllMtrrs (&LocalMtrrs);\r
+    Mtrrs = &LocalMtrrs;\r
+  }\r
+\r
+  //\r
+  // Dump RAW MTRR contents\r
+  //\r
+  DEBUG ((DEBUG_CACHE, "MTRR Settings:\n"));\r
+  DEBUG ((DEBUG_CACHE, "=============\n"));\r
+  DEBUG ((DEBUG_CACHE, "MTRR Default Type: %016lx\n", Mtrrs->MtrrDefType));\r
+  for (Index = 0; Index < ARRAY_SIZE (mMtrrLibFixedMtrrTable); Index++) {\r
+    DEBUG ((DEBUG_CACHE, "Fixed MTRR[%02d]   : %016lx\n", Index, Mtrrs->Fixed.Mtrr[Index]));\r
+  }\r
+\r
+  ContainVariableMtrr = FALSE;\r
+  for (Index = 0; Index < VariableMtrrCount; Index++) {\r
+    if ((Mtrrs->Variables.Mtrr[Index].Mask & BIT11) == 0) {\r
+      //\r
+      // If mask is not valid, then do not display range\r
+      //\r
+      continue;\r
     }\r
-    DEBUG((DEBUG_CACHE, "\n"));\r
 \r
-    //\r
-    // Dump MTRR setting in ranges\r
-    //\r
-    DEBUG((DEBUG_CACHE, "Memory Ranges:\n"));\r
-    DEBUG((DEBUG_CACHE, "====================================\n"));\r
-    MtrrLibInitializeMtrrMask (&MtrrValidBitsMask, &MtrrValidAddressMask);\r
-    Ranges[0].BaseAddress = 0;\r
-    Ranges[0].Length      = MtrrValidBitsMask + 1;\r
-    Ranges[0].Type        = MtrrGetDefaultMemoryTypeWorker (Mtrrs);\r
-    RangeCount = 1;\r
+    ContainVariableMtrr = TRUE;\r
+    DEBUG ((\r
+      DEBUG_CACHE,\r
+      "Variable MTRR[%02d]: Base=%016lx Mask=%016lx\n",\r
+      Index,\r
+      Mtrrs->Variables.Mtrr[Index].Base,\r
+      Mtrrs->Variables.Mtrr[Index].Mask\r
+      ));\r
+  }\r
 \r
-    MtrrLibGetRawVariableRanges (\r
-      &Mtrrs->Variables, VariableMtrrCount,\r
-      MtrrValidBitsMask, MtrrValidAddressMask, RawVariableRanges\r
-      );\r
-    MtrrLibApplyVariableMtrrs (\r
-      RawVariableRanges, VariableMtrrCount,\r
-      Ranges, ARRAY_SIZE (Ranges), &RangeCount\r
-      );\r
+  if (!ContainVariableMtrr) {\r
+    DEBUG ((DEBUG_CACHE, "Variable MTRR    : None.\n"));\r
+  }\r
 \r
-    MtrrLibApplyFixedMtrrs (&Mtrrs->Fixed, Ranges, ARRAY_SIZE (Ranges), &RangeCount);\r
+  DEBUG ((DEBUG_CACHE, "\n"));\r
+\r
+  //\r
+  // Dump MTRR setting in ranges\r
+  //\r
+  DEBUG ((DEBUG_CACHE, "Memory Ranges:\n"));\r
+  DEBUG ((DEBUG_CACHE, "====================================\n"));\r
+  MtrrLibInitializeMtrrMask (&MtrrValidBitsMask, &MtrrValidAddressMask);\r
+  Ranges[0].BaseAddress = 0;\r
+  Ranges[0].Length      = MtrrValidBitsMask + 1;\r
+  Ranges[0].Type        = MtrrGetDefaultMemoryTypeWorker (Mtrrs);\r
+  RangeCount            = 1;\r
+\r
+  MtrrLibGetRawVariableRanges (\r
+    &Mtrrs->Variables,\r
+    VariableMtrrCount,\r
+    MtrrValidBitsMask,\r
+    MtrrValidAddressMask,\r
+    RawVariableRanges\r
+    );\r
+  MtrrLibApplyVariableMtrrs (\r
+    RawVariableRanges,\r
+    VariableMtrrCount,\r
+    Ranges,\r
+    ARRAY_SIZE (Ranges),\r
+    &RangeCount\r
+    );\r
+\r
+  MtrrLibApplyFixedMtrrs (&Mtrrs->Fixed, Ranges, ARRAY_SIZE (Ranges), &RangeCount);\r
+\r
+  for (Index = 0; Index < RangeCount; Index++) {\r
+    DEBUG ((\r
+      DEBUG_CACHE,\r
+      "%a:%016lx-%016lx\n",\r
+      mMtrrMemoryCacheTypeShortName[Ranges[Index].Type],\r
+      Ranges[Index].BaseAddress,\r
+      Ranges[Index].BaseAddress + Ranges[Index].Length - 1\r
+      ));\r
+  }\r
 \r
-    for (Index = 0; Index < RangeCount; Index++) {\r
-      DEBUG ((DEBUG_CACHE, "%a:%016lx-%016lx\n",\r
-        mMtrrMemoryCacheTypeShortName[Ranges[Index].Type],\r
-        Ranges[Index].BaseAddress, Ranges[Index].BaseAddress + Ranges[Index].Length - 1\r
-        ));\r
-    }\r
   DEBUG_CODE_END ();\r
 }\r
 \r

diff --git a/UefiCpuPkg/Library/MtrrLib/UnitTest/MtrrLibUnitTest.c b/UefiCpuPkg/Library/MtrrLib/UnitTest/MtrrLibUnitTest.c
index e84b9390601d4897eaccc714fa928444392a7bdf..b9a97dee09dbedbc4b8633819972fc71fd87de96 100644 (file)
--- a/UefiCpuPkg/Library/MtrrLib/UnitTest/MtrrLibUnitTest.c
+++ b/UefiCpuPkg/Library/MtrrLib/UnitTest/MtrrLibUnitTest.c
@@ -8,11 +8,11 @@
 \r
 #include "MtrrLibUnitTest.h"\r
 \r
-STATIC CONST MTRR_LIB_SYSTEM_PARAMETER mDefaultSystemParameter = {\r
+STATIC CONST MTRR_LIB_SYSTEM_PARAMETER  mDefaultSystemParameter = {\r
   42, TRUE, TRUE, CacheUncacheable, 12\r
 };\r
 \r
-STATIC MTRR_LIB_SYSTEM_PARAMETER mSystemParameters[] = {\r
+STATIC MTRR_LIB_SYSTEM_PARAMETER  mSystemParameters[] = {\r
   { 38, TRUE, TRUE, CacheUncacheable,    12 },\r
   { 38, TRUE, TRUE, CacheWriteBack,      12 },\r
   { 38, TRUE, TRUE, CacheWriteThrough,   12 },\r
@@ -32,7 +32,7 @@ STATIC MTRR_LIB_SYSTEM_PARAMETER mSystemParameters[] = {
   { 48, TRUE, TRUE, CacheWriteCombining, 12 },\r
 };\r
 \r
-UINT32                    mFixedMtrrsIndex[] = {\r
+UINT32  mFixedMtrrsIndex[] = {\r
   MSR_IA32_MTRR_FIX64K_00000,\r
   MSR_IA32_MTRR_FIX16K_80000,\r
   MSR_IA32_MTRR_FIX16K_A0000,\r
@@ -54,18 +54,18 @@ STATIC_ASSERT (
 // Context structure to be used for most of the test cases.\r
 //\r
 typedef struct {\r
-  CONST MTRR_LIB_SYSTEM_PARAMETER *SystemParameter;\r
+  CONST MTRR_LIB_SYSTEM_PARAMETER    *SystemParameter;\r
 } MTRR_LIB_TEST_CONTEXT;\r
 \r
 //\r
 // Context structure to be used for GetFirmwareVariableMtrrCount() test.\r
 //\r
 typedef struct {\r
-  UINT32                          NumberOfReservedVariableMtrrs;\r
-  CONST MTRR_LIB_SYSTEM_PARAMETER *SystemParameter;\r
+  UINT32                             NumberOfReservedVariableMtrrs;\r
+  CONST MTRR_LIB_SYSTEM_PARAMETER    *SystemParameter;\r
 } MTRR_LIB_GET_FIRMWARE_VARIABLE_MTRR_COUNT_CONTEXT;\r
 \r
-STATIC CHAR8 *mCacheDescription[] = { "UC", "WC", "N/A", "N/A", "WT", "WP", "WB" };\r
+STATIC CHAR8  *mCacheDescription[] = { "UC", "WC", "N/A", "N/A", "WT", "WP", "WB" };\r
 \r
 /**\r
   Compare the actual memory ranges against expected memory ranges and return PASS when they match.\r
@@ -87,6 +87,7 @@ VerifyMemoryRanges (
   )\r
 {\r
   UINTN  Index;\r
+\r
   UT_ASSERT_EQUAL (ExpectedMemoryRangeCount, ActualRangeCount);\r
   for (Index = 0; Index < ExpectedMemoryRangeCount; Index++) {\r
     UT_ASSERT_EQUAL (ExpectedMemoryRanges[Index].BaseAddress, ActualRanges[Index].BaseAddress);\r
@@ -105,11 +106,12 @@ VerifyMemoryRanges (
 **/\r
 VOID\r
 DumpMemoryRanges (\r
-  MTRR_MEMORY_RANGE    *Ranges,\r
-  UINTN                RangeCount\r
+  MTRR_MEMORY_RANGE  *Ranges,\r
+  UINTN              RangeCount\r
   )\r
 {\r
-  UINTN     Index;\r
+  UINTN  Index;\r
+\r
   for (Index = 0; Index < RangeCount; Index++) {\r
     UT_LOG_INFO ("\t{ 0x%016llx, 0x%016llx, %a },\n", Ranges[Index].BaseAddress, Ranges[Index].Length, mCacheDescription[Ranges[Index].Type]);\r
   }\r
@@ -130,17 +132,17 @@ DumpMemoryRanges (
 **/\r
 VOID\r
 GenerateRandomMemoryTypeCombination (\r
-  IN  UINT32 TotalCount,\r
-  OUT UINT32 *UcCount,\r
-  OUT UINT32 *WtCount,\r
-  OUT UINT32 *WbCount,\r
-  OUT UINT32 *WpCount,\r
-  OUT UINT32 *WcCount\r
+  IN  UINT32  TotalCount,\r
+  OUT UINT32  *UcCount,\r
+  OUT UINT32  *WtCount,\r
+  OUT UINT32  *WbCount,\r
+  OUT UINT32  *WpCount,\r
+  OUT UINT32  *WcCount\r
   )\r
 {\r
-  UINTN  Index;\r
-  UINT32 TotalMtrrCount;\r
-  UINT32 *CountPerType[5];\r
+  UINTN   Index;\r
+  UINT32  TotalMtrrCount;\r
+  UINT32  *CountPerType[5];\r
 \r
   CountPerType[0] = UcCount;\r
   CountPerType[1] = WtCount;\r
@@ -183,38 +185,47 @@ UnitTestMtrrSetMemoryAttributesInMtrrSettings (
   IN UNIT_TEST_CONTEXT  Context\r
   )\r
 {\r
-  CONST MTRR_LIB_SYSTEM_PARAMETER *SystemParameter;\r
-  RETURN_STATUS                   Status;\r
-  UINT32                          UcCount;\r
-  UINT32                          WtCount;\r
-  UINT32                          WbCount;\r
-  UINT32                          WpCount;\r
-  UINT32                          WcCount;\r
-\r
-  UINT32                          MtrrIndex;\r
-  UINT8                           *Scratch;\r
-  UINTN                           ScratchSize;\r
-  MTRR_SETTINGS                   LocalMtrrs;\r
-\r
-  MTRR_MEMORY_RANGE               RawMtrrRange[MTRR_NUMBER_OF_VARIABLE_MTRR];\r
-  MTRR_MEMORY_RANGE               ExpectedMemoryRanges[MTRR_NUMBER_OF_FIXED_MTRR * sizeof (UINT64) + 2 * MTRR_NUMBER_OF_VARIABLE_MTRR + 1];\r
-  UINT32                          ExpectedVariableMtrrUsage;\r
-  UINTN                           ExpectedMemoryRangesCount;\r
-\r
-  MTRR_MEMORY_RANGE               ActualMemoryRanges[MTRR_NUMBER_OF_FIXED_MTRR   * sizeof (UINT64) + 2 * MTRR_NUMBER_OF_VARIABLE_MTRR + 1];\r
-  UINT32                          ActualVariableMtrrUsage;\r
-  UINTN                           ActualMemoryRangesCount;\r
-\r
-  MTRR_SETTINGS             *Mtrrs[2];\r
-\r
-  SystemParameter = (MTRR_LIB_SYSTEM_PARAMETER *) Context;\r
+  CONST MTRR_LIB_SYSTEM_PARAMETER  *SystemParameter;\r
+  RETURN_STATUS                    Status;\r
+  UINT32                           UcCount;\r
+  UINT32                           WtCount;\r
+  UINT32                           WbCount;\r
+  UINT32                           WpCount;\r
+  UINT32                           WcCount;\r
+\r
+  UINT32         MtrrIndex;\r
+  UINT8          *Scratch;\r
+  UINTN          ScratchSize;\r
+  MTRR_SETTINGS  LocalMtrrs;\r
+\r
+  MTRR_MEMORY_RANGE  RawMtrrRange[MTRR_NUMBER_OF_VARIABLE_MTRR];\r
+  MTRR_MEMORY_RANGE  ExpectedMemoryRanges[MTRR_NUMBER_OF_FIXED_MTRR * sizeof (UINT64) + 2 * MTRR_NUMBER_OF_VARIABLE_MTRR + 1];\r
+  UINT32             ExpectedVariableMtrrUsage;\r
+  UINTN              ExpectedMemoryRangesCount;\r
+\r
+  MTRR_MEMORY_RANGE  ActualMemoryRanges[MTRR_NUMBER_OF_FIXED_MTRR   * sizeof (UINT64) + 2 * MTRR_NUMBER_OF_VARIABLE_MTRR + 1];\r
+  UINT32             ActualVariableMtrrUsage;\r
+  UINTN              ActualMemoryRangesCount;\r
+\r
+  MTRR_SETTINGS  *Mtrrs[2];\r
+\r
+  SystemParameter = (MTRR_LIB_SYSTEM_PARAMETER *)Context;\r
   GenerateRandomMemoryTypeCombination (\r
     SystemParameter->VariableMtrrCount - PatchPcdGet32 (PcdCpuNumberOfReservedVariableMtrrs),\r
-    &UcCount, &WtCount, &WbCount, &WpCount, &WcCount\r
+    &UcCount,\r
+    &WtCount,\r
+    &WbCount,\r
+    &WpCount,\r
+    &WcCount\r
     );\r
   GenerateValidAndConfigurableMtrrPairs (\r
-    SystemParameter->PhysicalAddressBits, RawMtrrRange,\r
-    UcCount, WtCount, WbCount, WpCount, WcCount\r
+    SystemParameter->PhysicalAddressBits,\r
+    RawMtrrRange,\r
+    UcCount,\r
+    WtCount,\r
+    WbCount,\r
+    WpCount,\r
+    WcCount\r
     );\r
 \r
   ExpectedVariableMtrrUsage = UcCount + WtCount + WbCount + WpCount + WcCount;\r
@@ -222,13 +233,20 @@ UnitTestMtrrSetMemoryAttributesInMtrrSettings (
   GetEffectiveMemoryRanges (\r
     SystemParameter->DefaultCacheType,\r
     SystemParameter->PhysicalAddressBits,\r
-    RawMtrrRange, ExpectedVariableMtrrUsage,\r
-    ExpectedMemoryRanges, &ExpectedMemoryRangesCount\r
+    RawMtrrRange,\r
+    ExpectedVariableMtrrUsage,\r
+    ExpectedMemoryRanges,\r
+    &ExpectedMemoryRangesCount\r
     );\r
 \r
   UT_LOG_INFO (\r
     "Total MTRR [%d]: UC=%d, WT=%d, WB=%d, WP=%d, WC=%d\n",\r
-    ExpectedVariableMtrrUsage, UcCount, WtCount, WbCount, WpCount, WcCount\r
+    ExpectedVariableMtrrUsage,\r
+    UcCount,\r
+    WtCount,\r
+    WbCount,\r
+    WpCount,\r
+    WcCount\r
     );\r
   UT_LOG_INFO ("--- Expected Memory Ranges [%d] ---\n", ExpectedMemoryRangesCount);\r
   DumpMemoryRanges (ExpectedMemoryRanges, ExpectedMemoryRangesCount);\r
@@ -244,21 +262,28 @@ UnitTestMtrrSetMemoryAttributesInMtrrSettings (
 \r
   for (MtrrIndex = 0; MtrrIndex < ARRAY_SIZE (Mtrrs); MtrrIndex++) {\r
     Scratch = calloc (ScratchSize, sizeof (UINT8));\r
-    Status = MtrrSetMemoryAttributesInMtrrSettings (Mtrrs[MtrrIndex], Scratch, &ScratchSize, ExpectedMemoryRanges, ExpectedMemoryRangesCount);\r
+    Status  = MtrrSetMemoryAttributesInMtrrSettings (Mtrrs[MtrrIndex], Scratch, &ScratchSize, ExpectedMemoryRanges, ExpectedMemoryRangesCount);\r
     if (Status == RETURN_BUFFER_TOO_SMALL) {\r
       Scratch = realloc (Scratch, ScratchSize);\r
-      Status = MtrrSetMemoryAttributesInMtrrSettings (Mtrrs[MtrrIndex], Scratch, &ScratchSize, ExpectedMemoryRanges, ExpectedMemoryRangesCount);\r
+      Status  = MtrrSetMemoryAttributesInMtrrSettings (Mtrrs[MtrrIndex], Scratch, &ScratchSize, ExpectedMemoryRanges, ExpectedMemoryRangesCount);\r
     }\r
+\r
     UT_ASSERT_STATUS_EQUAL (Status, RETURN_SUCCESS);\r
 \r
     if (Mtrrs[MtrrIndex] == NULL) {\r
       ZeroMem (&LocalMtrrs, sizeof (LocalMtrrs));\r
       MtrrGetAllMtrrs (&LocalMtrrs);\r
     }\r
+\r
     ActualMemoryRangesCount = ARRAY_SIZE (ActualMemoryRanges);\r
     CollectTestResult (\r
-      SystemParameter->DefaultCacheType, SystemParameter->PhysicalAddressBits, SystemParameter->VariableMtrrCount,\r
-      &LocalMtrrs, ActualMemoryRanges, &ActualMemoryRangesCount, &ActualVariableMtrrUsage\r
+      SystemParameter->DefaultCacheType,\r
+      SystemParameter->PhysicalAddressBits,\r
+      SystemParameter->VariableMtrrCount,\r
+      &LocalMtrrs,\r
+      ActualMemoryRanges,\r
+      &ActualMemoryRangesCount,\r
+      &ActualVariableMtrrUsage\r
       );\r
 \r
     UT_LOG_INFO ("--- Actual Memory Ranges [%d] ---\n", ActualMemoryRangesCount);\r
@@ -284,20 +309,20 @@ UnitTestMtrrSetMemoryAttributesInMtrrSettings (
 UNIT_TEST_STATUS\r
 EFIAPI\r
 UnitTestInvalidMemoryLayouts (\r
-  IN UNIT_TEST_CONTEXT          Context\r
+  IN UNIT_TEST_CONTEXT  Context\r
   )\r
 {\r
-  CONST MTRR_LIB_SYSTEM_PARAMETER *SystemParameter;\r
-  MTRR_MEMORY_RANGE               Ranges[MTRR_NUMBER_OF_VARIABLE_MTRR * 2 + 1];\r
-  UINTN                           RangeCount;\r
-  UINT64                          MaxAddress;\r
-  UINT32                          Index;\r
-  UINT64                          BaseAddress;\r
-  UINT64                          Length;\r
-  RETURN_STATUS                   Status;\r
-  UINTN                           ScratchSize;\r
-\r
-  SystemParameter = (MTRR_LIB_SYSTEM_PARAMETER *) Context;\r
+  CONST MTRR_LIB_SYSTEM_PARAMETER  *SystemParameter;\r
+  MTRR_MEMORY_RANGE                Ranges[MTRR_NUMBER_OF_VARIABLE_MTRR * 2 + 1];\r
+  UINTN                            RangeCount;\r
+  UINT64                           MaxAddress;\r
+  UINT32                           Index;\r
+  UINT64                           BaseAddress;\r
+  UINT64                           Length;\r
+  RETURN_STATUS                    Status;\r
+  UINTN                            ScratchSize;\r
+\r
+  SystemParameter = (MTRR_LIB_SYSTEM_PARAMETER *)Context;\r
 \r
   RangeCount = Random32 (1, ARRAY_SIZE (Ranges));\r
   MaxAddress = 1ull << SystemParameter->PhysicalAddressBits;\r
@@ -313,13 +338,15 @@ UnitTestInvalidMemoryLayouts (
     Ranges[Index].Type        = GenerateRandomCacheType ();\r
 \r
     Status = MtrrSetMemoryAttribute (\r
-      Ranges[Index].BaseAddress, Ranges[Index].Length, Ranges[Index].Type\r
-      );\r
+               Ranges[Index].BaseAddress,\r
+               Ranges[Index].Length,\r
+               Ranges[Index].Type\r
+               );\r
     UT_ASSERT_TRUE (RETURN_ERROR (Status));\r
   }\r
 \r
   ScratchSize = 0;\r
-  Status = MtrrSetMemoryAttributesInMtrrSettings (NULL, NULL, &ScratchSize, Ranges, RangeCount);\r
+  Status      = MtrrSetMemoryAttributesInMtrrSettings (NULL, NULL, &ScratchSize, Ranges, RangeCount);\r
   UT_ASSERT_TRUE (RETURN_ERROR (Status));\r
 \r
   return UNIT_TEST_PASSED;\r
@@ -344,7 +371,7 @@ UnitTestIsMtrrSupported (
   MTRR_LIB_SYSTEM_PARAMETER  SystemParameter;\r
   MTRR_LIB_TEST_CONTEXT      *LocalContext;\r
 \r
-  LocalContext = (MTRR_LIB_TEST_CONTEXT *) Context;\r
+  LocalContext = (MTRR_LIB_TEST_CONTEXT *)Context;\r
 \r
   CopyMem (&SystemParameter, LocalContext->SystemParameter, sizeof (SystemParameter));\r
   //\r
@@ -357,8 +384,8 @@ UnitTestIsMtrrSupported (
   //\r
   // MTRR capability on in CPUID leaf, but no variable or fixed MTRRs.\r
   //\r
-  SystemParameter.MtrrSupported = TRUE;\r
-  SystemParameter.VariableMtrrCount = 0;\r
+  SystemParameter.MtrrSupported      = TRUE;\r
+  SystemParameter.VariableMtrrCount  = 0;\r
   SystemParameter.FixedMtrrSupported = FALSE;\r
   InitializeMtrrRegs (&SystemParameter);\r
   UT_ASSERT_FALSE (IsMtrrSupported ());\r
@@ -366,8 +393,8 @@ UnitTestIsMtrrSupported (
   //\r
   // MTRR capability on in CPUID leaf, but no variable MTRRs.\r
   //\r
-  SystemParameter.MtrrSupported = TRUE;\r
-  SystemParameter.VariableMtrrCount = 0;\r
+  SystemParameter.MtrrSupported      = TRUE;\r
+  SystemParameter.VariableMtrrCount  = 0;\r
   SystemParameter.FixedMtrrSupported = TRUE;\r
   InitializeMtrrRegs (&SystemParameter);\r
   UT_ASSERT_FALSE (IsMtrrSupported ());\r
@@ -375,8 +402,8 @@ UnitTestIsMtrrSupported (
   //\r
   // MTRR capability on in CPUID leaf, but no fixed MTRRs.\r
   //\r
-  SystemParameter.MtrrSupported = TRUE;\r
-  SystemParameter.VariableMtrrCount = 7;\r
+  SystemParameter.MtrrSupported      = TRUE;\r
+  SystemParameter.VariableMtrrCount  = 7;\r
   SystemParameter.FixedMtrrSupported = FALSE;\r
   InitializeMtrrRegs (&SystemParameter);\r
   UT_ASSERT_FALSE (IsMtrrSupported ());\r
@@ -384,8 +411,8 @@ UnitTestIsMtrrSupported (
   //\r
   // MTRR capability on in CPUID leaf with both variable and fixed MTRRs.\r
   //\r
-  SystemParameter.MtrrSupported = TRUE;\r
-  SystemParameter.VariableMtrrCount = 7;\r
+  SystemParameter.MtrrSupported      = TRUE;\r
+  SystemParameter.VariableMtrrCount  = 7;\r
   SystemParameter.FixedMtrrSupported = TRUE;\r
   InitializeMtrrRegs (&SystemParameter);\r
   UT_ASSERT_TRUE (IsMtrrSupported ());\r
@@ -409,11 +436,11 @@ UnitTestGetVariableMtrrCount (
   IN UNIT_TEST_CONTEXT  Context\r
   )\r
 {\r
-  UINT32                    Result;\r
-  MTRR_LIB_SYSTEM_PARAMETER SystemParameter;\r
-  MTRR_LIB_TEST_CONTEXT     *LocalContext;\r
+  UINT32                     Result;\r
+  MTRR_LIB_SYSTEM_PARAMETER  SystemParameter;\r
+  MTRR_LIB_TEST_CONTEXT      *LocalContext;\r
 \r
-  LocalContext = (MTRR_LIB_TEST_CONTEXT *) Context;\r
+  LocalContext = (MTRR_LIB_TEST_CONTEXT *)Context;\r
 \r
   CopyMem (&SystemParameter, LocalContext->SystemParameter, sizeof (SystemParameter));\r
   //\r
@@ -445,7 +472,7 @@ UnitTestGetVariableMtrrCount (
   InitializeMtrrRegs (&SystemParameter);\r
   UT_EXPECT_ASSERT_FAILURE (GetVariableMtrrCount (), NULL);\r
 \r
-  SystemParameter.MtrrSupported = TRUE;\r
+  SystemParameter.MtrrSupported     = TRUE;\r
   SystemParameter.VariableMtrrCount = MAX_UINT8;\r
   InitializeMtrrRegs (&SystemParameter);\r
   UT_EXPECT_ASSERT_FAILURE (GetVariableMtrrCount (), NULL);\r
@@ -469,12 +496,12 @@ UnitTestGetFirmwareVariableMtrrCount (
   IN UNIT_TEST_CONTEXT  Context\r
   )\r
 {\r
-  UINT32                                            Result;\r
-  UINT32                                            ReservedMtrrs;\r
-  MTRR_LIB_SYSTEM_PARAMETER                         SystemParameter;\r
-  MTRR_LIB_GET_FIRMWARE_VARIABLE_MTRR_COUNT_CONTEXT *LocalContext;\r
+  UINT32                                             Result;\r
+  UINT32                                             ReservedMtrrs;\r
+  MTRR_LIB_SYSTEM_PARAMETER                          SystemParameter;\r
+  MTRR_LIB_GET_FIRMWARE_VARIABLE_MTRR_COUNT_CONTEXT  *LocalContext;\r
 \r
-  LocalContext = (MTRR_LIB_GET_FIRMWARE_VARIABLE_MTRR_COUNT_CONTEXT *) Context;\r
+  LocalContext = (MTRR_LIB_GET_FIRMWARE_VARIABLE_MTRR_COUNT_CONTEXT *)Context;\r
 \r
   CopyMem (&SystemParameter, LocalContext->SystemParameter, sizeof (SystemParameter));\r
 \r
@@ -516,7 +543,7 @@ UnitTestGetFirmwareVariableMtrrCount (
   //\r
   // Negative test case when Fixed MTRRs are not supported\r
   //\r
-  SystemParameter.MtrrSupported = TRUE;\r
+  SystemParameter.MtrrSupported      = TRUE;\r
   SystemParameter.FixedMtrrSupported = FALSE;\r
   InitializeMtrrRegs (&SystemParameter);\r
   PatchPcdSet32 (PcdCpuNumberOfReservedVariableMtrrs, 2);\r
@@ -527,7 +554,7 @@ UnitTestGetFirmwareVariableMtrrCount (
   // Expect ASSERT() if variable MTRR count is > MTRR_NUMBER_OF_VARIABLE_MTRR\r
   //\r
   SystemParameter.FixedMtrrSupported = TRUE;\r
-  SystemParameter.VariableMtrrCount = MTRR_NUMBER_OF_VARIABLE_MTRR + 1;\r
+  SystemParameter.VariableMtrrCount  = MTRR_NUMBER_OF_VARIABLE_MTRR + 1;\r
   InitializeMtrrRegs (&SystemParameter);\r
   UT_EXPECT_ASSERT_FAILURE (GetFirmwareVariableMtrrCount (), NULL);\r
 \r
@@ -569,17 +596,17 @@ UnitTestMtrrGetFixedMtrr (
   IN UNIT_TEST_CONTEXT  Context\r
   )\r
 {\r
-  MTRR_FIXED_SETTINGS       *Result;\r
-  MTRR_FIXED_SETTINGS       ExpectedFixedSettings;\r
-  MTRR_FIXED_SETTINGS       FixedSettings;\r
-  UINTN                     Index;\r
-  UINTN                     MsrIndex;\r
-  UINTN                     ByteIndex;\r
-  UINT64                    MsrValue;\r
-  MTRR_LIB_SYSTEM_PARAMETER SystemParameter;\r
-  MTRR_LIB_TEST_CONTEXT     *LocalContext;\r
-\r
-  LocalContext = (MTRR_LIB_TEST_CONTEXT *) Context;\r
+  MTRR_FIXED_SETTINGS        *Result;\r
+  MTRR_FIXED_SETTINGS        ExpectedFixedSettings;\r
+  MTRR_FIXED_SETTINGS        FixedSettings;\r
+  UINTN                      Index;\r
+  UINTN                      MsrIndex;\r
+  UINTN                      ByteIndex;\r
+  UINT64                     MsrValue;\r
+  MTRR_LIB_SYSTEM_PARAMETER  SystemParameter;\r
+  MTRR_LIB_TEST_CONTEXT      *LocalContext;\r
+\r
+  LocalContext = (MTRR_LIB_TEST_CONTEXT *)Context;\r
 \r
   CopyMem (&SystemParameter, LocalContext->SystemParameter, sizeof (SystemParameter));\r
   InitializeMtrrRegs (&SystemParameter);\r
@@ -594,6 +621,7 @@ UnitTestMtrrGetFixedMtrr (
       for (ByteIndex = 0; ByteIndex < sizeof (UINT64); ByteIndex++) {\r
         MsrValue = MsrValue | LShiftU64 (GenerateRandomCacheType (), ByteIndex * 8);\r
       }\r
+\r
       ExpectedFixedSettings.Mtrr[MsrIndex] = MsrValue;\r
       AsmWriteMsr64 (mFixedMtrrsIndex[MsrIndex], MsrValue);\r
     }\r
@@ -631,18 +659,18 @@ UnitTestMtrrGetFixedMtrr (
 UNIT_TEST_STATUS\r
 EFIAPI\r
 UnitTestMtrrGetAllMtrrs (\r
-  IN UNIT_TEST_CONTEXT      Context\r
+  IN UNIT_TEST_CONTEXT  Context\r
   )\r
 {\r
-  MTRR_SETTINGS             *Result;\r
-  MTRR_SETTINGS             Mtrrs;\r
-  MTRR_SETTINGS             ExpectedMtrrs;\r
-  MTRR_VARIABLE_SETTING     VariableMtrr[MTRR_NUMBER_OF_VARIABLE_MTRR];\r
-  UINT32                    Index;\r
-  MTRR_LIB_SYSTEM_PARAMETER SystemParameter;\r
-  MTRR_LIB_TEST_CONTEXT     *LocalContext;\r
+  MTRR_SETTINGS              *Result;\r
+  MTRR_SETTINGS              Mtrrs;\r
+  MTRR_SETTINGS              ExpectedMtrrs;\r
+  MTRR_VARIABLE_SETTING      VariableMtrr[MTRR_NUMBER_OF_VARIABLE_MTRR];\r
+  UINT32                     Index;\r
+  MTRR_LIB_SYSTEM_PARAMETER  SystemParameter;\r
+  MTRR_LIB_TEST_CONTEXT      *LocalContext;\r
 \r
-  LocalContext = (MTRR_LIB_TEST_CONTEXT *) Context;\r
+  LocalContext = (MTRR_LIB_TEST_CONTEXT *)Context;\r
 \r
   CopyMem (&SystemParameter, LocalContext->SystemParameter, sizeof (SystemParameter));\r
   InitializeMtrrRegs (&SystemParameter);\r
@@ -652,6 +680,7 @@ UnitTestMtrrGetAllMtrrs (
     AsmWriteMsr64 (MSR_IA32_MTRR_PHYSBASE0 + (Index << 1), VariableMtrr[Index].Base);\r
     AsmWriteMsr64 (MSR_IA32_MTRR_PHYSMASK0 + (Index << 1), VariableMtrr[Index].Mask);\r
   }\r
+\r
   Result = MtrrGetAllMtrrs (&Mtrrs);\r
   UT_ASSERT_EQUAL ((UINTN)Result, (UINTN)&Mtrrs);\r
   UT_ASSERT_MEM_EQUAL (Mtrrs.Variables.Mtrr, VariableMtrr, sizeof (MTRR_VARIABLE_SETTING) * SystemParameter.VariableMtrrCount);\r
@@ -671,7 +700,7 @@ UnitTestMtrrGetAllMtrrs (
   //\r
   // Expect ASSERT() if variable MTRR count is > MTRR_NUMBER_OF_VARIABLE_MTRR\r
   //\r
-  SystemParameter.MtrrSupported = TRUE;\r
+  SystemParameter.MtrrSupported     = TRUE;\r
   SystemParameter.VariableMtrrCount = MTRR_NUMBER_OF_VARIABLE_MTRR + 1;\r
   InitializeMtrrRegs (&SystemParameter);\r
   UT_EXPECT_ASSERT_FAILURE (MtrrGetAllMtrrs (&Mtrrs), NULL);\r
@@ -695,21 +724,21 @@ UnitTestMtrrSetAllMtrrs (
   IN UNIT_TEST_CONTEXT  Context\r
   )\r
 {\r
-  MTRR_SETTINGS                   *Result;\r
-  MTRR_SETTINGS                   Mtrrs;\r
-  UINT32                          Index;\r
-  MSR_IA32_MTRR_DEF_TYPE_REGISTER Default;\r
-  MTRR_LIB_SYSTEM_PARAMETER       SystemParameter;\r
-  MTRR_LIB_TEST_CONTEXT           *LocalContext;\r
+  MTRR_SETTINGS                    *Result;\r
+  MTRR_SETTINGS                    Mtrrs;\r
+  UINT32                           Index;\r
+  MSR_IA32_MTRR_DEF_TYPE_REGISTER  Default;\r
+  MTRR_LIB_SYSTEM_PARAMETER        SystemParameter;\r
+  MTRR_LIB_TEST_CONTEXT            *LocalContext;\r
 \r
-  LocalContext = (MTRR_LIB_TEST_CONTEXT *) Context;\r
+  LocalContext = (MTRR_LIB_TEST_CONTEXT *)Context;\r
 \r
   CopyMem (&SystemParameter, LocalContext->SystemParameter, sizeof (SystemParameter));\r
   InitializeMtrrRegs (&SystemParameter);\r
 \r
-  Default.Uint64 = 0;\r
-  Default.Bits.E = 1;\r
-  Default.Bits.FE = 1;\r
+  Default.Uint64    = 0;\r
+  Default.Bits.E    = 1;\r
+  Default.Bits.FE   = 1;\r
   Default.Bits.Type = GenerateRandomCacheType ();\r
 \r
   ZeroMem (&Mtrrs, sizeof (Mtrrs));\r
@@ -717,6 +746,7 @@ UnitTestMtrrSetAllMtrrs (
   for (Index = 0; Index < SystemParameter.VariableMtrrCount; Index++) {\r
     GenerateRandomMtrrPair (SystemParameter.PhysicalAddressBits, GenerateRandomCacheType (), &Mtrrs.Variables.Mtrr[Index], NULL);\r
   }\r
+\r
   Result = MtrrSetAllMtrrs (&Mtrrs);\r
   UT_ASSERT_EQUAL ((UINTN)Result, (UINTN)&Mtrrs);\r
 \r
@@ -745,18 +775,18 @@ UnitTestMtrrGetMemoryAttributeInVariableMtrr (
   IN UNIT_TEST_CONTEXT  Context\r
   )\r
 {\r
-  MTRR_LIB_TEST_CONTEXT           *LocalContext;\r
-  MTRR_LIB_SYSTEM_PARAMETER       SystemParameter;\r
-  UINT32                          Result;\r
-  MTRR_VARIABLE_SETTING           VariableSetting[MTRR_NUMBER_OF_VARIABLE_MTRR];\r
-  VARIABLE_MTRR                   VariableMtrr[MTRR_NUMBER_OF_VARIABLE_MTRR];\r
-  UINT64                          ValidMtrrBitsMask;\r
-  UINT64                          ValidMtrrAddressMask;\r
-  UINT32                          Index;\r
-  MSR_IA32_MTRR_PHYSBASE_REGISTER Base;\r
-  MSR_IA32_MTRR_PHYSMASK_REGISTER Mask;\r
-\r
-  LocalContext = (MTRR_LIB_TEST_CONTEXT *) Context;\r
+  MTRR_LIB_TEST_CONTEXT            *LocalContext;\r
+  MTRR_LIB_SYSTEM_PARAMETER        SystemParameter;\r
+  UINT32                           Result;\r
+  MTRR_VARIABLE_SETTING            VariableSetting[MTRR_NUMBER_OF_VARIABLE_MTRR];\r
+  VARIABLE_MTRR                    VariableMtrr[MTRR_NUMBER_OF_VARIABLE_MTRR];\r
+  UINT64                           ValidMtrrBitsMask;\r
+  UINT64                           ValidMtrrAddressMask;\r
+  UINT32                           Index;\r
+  MSR_IA32_MTRR_PHYSBASE_REGISTER  Base;\r
+  MSR_IA32_MTRR_PHYSMASK_REGISTER  Mask;\r
+\r
+  LocalContext = (MTRR_LIB_TEST_CONTEXT *)Context;\r
 \r
   CopyMem (&SystemParameter, LocalContext->SystemParameter, sizeof (SystemParameter));\r
 \r
@@ -770,16 +800,17 @@ UnitTestMtrrGetMemoryAttributeInVariableMtrr (
     AsmWriteMsr64 (MSR_IA32_MTRR_PHYSBASE0 + (Index << 1), VariableSetting[Index].Base);\r
     AsmWriteMsr64 (MSR_IA32_MTRR_PHYSMASK0 + (Index << 1), VariableSetting[Index].Mask);\r
   }\r
+\r
   Result = MtrrGetMemoryAttributeInVariableMtrr (ValidMtrrBitsMask, ValidMtrrAddressMask, VariableMtrr);\r
   UT_ASSERT_EQUAL (Result, SystemParameter.VariableMtrrCount);\r
 \r
   for (Index = 0; Index < SystemParameter.VariableMtrrCount; Index++) {\r
     Base.Uint64    = VariableMtrr[Index].BaseAddress;\r
-    Base.Bits.Type = (UINT32) VariableMtrr[Index].Type;\r
+    Base.Bits.Type = (UINT32)VariableMtrr[Index].Type;\r
     UT_ASSERT_EQUAL (Base.Uint64, VariableSetting[Index].Base);\r
 \r
-    Mask.Uint64    = ~(VariableMtrr[Index].Length - 1) & ValidMtrrBitsMask;\r
-    Mask.Bits.V    = 1;\r
+    Mask.Uint64 = ~(VariableMtrr[Index].Length - 1) & ValidMtrrBitsMask;\r
+    Mask.Bits.V = 1;\r
     UT_ASSERT_EQUAL (Mask.Uint64, VariableSetting[Index].Mask);\r
   }\r
 \r
@@ -794,7 +825,7 @@ UnitTestMtrrGetMemoryAttributeInVariableMtrr (
   //\r
   // Expect ASSERT() if variable MTRR count is > MTRR_NUMBER_OF_VARIABLE_MTRR\r
   //\r
-  SystemParameter.MtrrSupported = TRUE;\r
+  SystemParameter.MtrrSupported     = TRUE;\r
   SystemParameter.VariableMtrrCount = MTRR_NUMBER_OF_VARIABLE_MTRR + 1;\r
   InitializeMtrrRegs (&SystemParameter);\r
   UT_EXPECT_ASSERT_FAILURE (MtrrGetMemoryAttributeInVariableMtrr (ValidMtrrBitsMask, ValidMtrrAddressMask, VariableMtrr), NULL);\r
@@ -837,11 +868,11 @@ UnitTestMtrrGetDefaultMemoryType (
   IN UNIT_TEST_CONTEXT  Context\r
   )\r
 {\r
-  MTRR_LIB_TEST_CONTEXT     *LocalContext;\r
-  UINTN                     Index;\r
-  MTRR_MEMORY_CACHE_TYPE    Result;\r
-  MTRR_LIB_SYSTEM_PARAMETER SystemParameter;\r
-  MTRR_MEMORY_CACHE_TYPE    CacheType[5];\r
+  MTRR_LIB_TEST_CONTEXT      *LocalContext;\r
+  UINTN                      Index;\r
+  MTRR_MEMORY_CACHE_TYPE     Result;\r
+  MTRR_LIB_SYSTEM_PARAMETER  SystemParameter;\r
+  MTRR_MEMORY_CACHE_TYPE     CacheType[5];\r
 \r
   CacheType[0] = CacheUncacheable;\r
   CacheType[1] = CacheWriteCombining;\r
@@ -849,7 +880,7 @@ UnitTestMtrrGetDefaultMemoryType (
   CacheType[3] = CacheWriteProtected;\r
   CacheType[4] = CacheWriteBack;\r
 \r
-  LocalContext = (MTRR_LIB_TEST_CONTEXT *) Context;\r
+  LocalContext = (MTRR_LIB_TEST_CONTEXT *)Context;\r
 \r
   CopyMem (&SystemParameter, LocalContext->SystemParameter, sizeof (SystemParameter));\r
   //\r
@@ -871,15 +902,15 @@ UnitTestMtrrGetDefaultMemoryType (
   Result = MtrrGetDefaultMemoryType ();\r
   UT_ASSERT_EQUAL (Result, CacheUncacheable);\r
 \r
-  SystemParameter.MtrrSupported = TRUE;\r
+  SystemParameter.MtrrSupported      = TRUE;\r
   SystemParameter.FixedMtrrSupported = FALSE;\r
   InitializeMtrrRegs (&SystemParameter);\r
   Result = MtrrGetDefaultMemoryType ();\r
   UT_ASSERT_EQUAL (Result, CacheUncacheable);\r
 \r
-  SystemParameter.MtrrSupported = TRUE;\r
+  SystemParameter.MtrrSupported      = TRUE;\r
   SystemParameter.FixedMtrrSupported = TRUE;\r
-  SystemParameter.VariableMtrrCount = 0;\r
+  SystemParameter.VariableMtrrCount  = 0;\r
   InitializeMtrrRegs (&SystemParameter);\r
   Result = MtrrGetDefaultMemoryType ();\r
   UT_ASSERT_EQUAL (Result, CacheUncacheable);\r
@@ -903,37 +934,46 @@ UnitTestMtrrSetMemoryAttributeInMtrrSettings (
   IN UNIT_TEST_CONTEXT  Context\r
   )\r
 {\r
-  CONST MTRR_LIB_SYSTEM_PARAMETER *SystemParameter;\r
-  RETURN_STATUS                   Status;\r
-  UINT32                          UcCount;\r
-  UINT32                          WtCount;\r
-  UINT32                          WbCount;\r
-  UINT32                          WpCount;\r
-  UINT32                          WcCount;\r
-\r
-  UINTN                           MtrrIndex;\r
-  UINTN                           Index;\r
-  MTRR_SETTINGS                   LocalMtrrs;\r
-\r
-  MTRR_MEMORY_RANGE               RawMtrrRange[MTRR_NUMBER_OF_VARIABLE_MTRR];\r
-  MTRR_MEMORY_RANGE               ExpectedMemoryRanges[MTRR_NUMBER_OF_FIXED_MTRR * sizeof (UINT64) + 2 * MTRR_NUMBER_OF_VARIABLE_MTRR + 1];\r
-  UINT32                          ExpectedVariableMtrrUsage;\r
-  UINTN                           ExpectedMemoryRangesCount;\r
-\r
-  MTRR_MEMORY_RANGE               ActualMemoryRanges[MTRR_NUMBER_OF_FIXED_MTRR * sizeof (UINT64) + 2 * MTRR_NUMBER_OF_VARIABLE_MTRR + 1];\r
-  UINT32                          ActualVariableMtrrUsage;\r
-  UINTN                           ActualMemoryRangesCount;\r
-\r
-  MTRR_SETTINGS                   *Mtrrs[2];\r
-\r
-  SystemParameter = (MTRR_LIB_SYSTEM_PARAMETER *) Context;\r
+  CONST MTRR_LIB_SYSTEM_PARAMETER  *SystemParameter;\r
+  RETURN_STATUS                    Status;\r
+  UINT32                           UcCount;\r
+  UINT32                           WtCount;\r
+  UINT32                           WbCount;\r
+  UINT32                           WpCount;\r
+  UINT32                           WcCount;\r
+\r
+  UINTN          MtrrIndex;\r
+  UINTN          Index;\r
+  MTRR_SETTINGS  LocalMtrrs;\r
+\r
+  MTRR_MEMORY_RANGE  RawMtrrRange[MTRR_NUMBER_OF_VARIABLE_MTRR];\r
+  MTRR_MEMORY_RANGE  ExpectedMemoryRanges[MTRR_NUMBER_OF_FIXED_MTRR * sizeof (UINT64) + 2 * MTRR_NUMBER_OF_VARIABLE_MTRR + 1];\r
+  UINT32             ExpectedVariableMtrrUsage;\r
+  UINTN              ExpectedMemoryRangesCount;\r
+\r
+  MTRR_MEMORY_RANGE  ActualMemoryRanges[MTRR_NUMBER_OF_FIXED_MTRR * sizeof (UINT64) + 2 * MTRR_NUMBER_OF_VARIABLE_MTRR + 1];\r
+  UINT32             ActualVariableMtrrUsage;\r
+  UINTN              ActualMemoryRangesCount;\r
+\r
+  MTRR_SETTINGS  *Mtrrs[2];\r
+\r
+  SystemParameter = (MTRR_LIB_SYSTEM_PARAMETER *)Context;\r
   GenerateRandomMemoryTypeCombination (\r
     SystemParameter->VariableMtrrCount - PatchPcdGet32 (PcdCpuNumberOfReservedVariableMtrrs),\r
-    &UcCount, &WtCount, &WbCount, &WpCount, &WcCount\r
+    &UcCount,\r
+    &WtCount,\r
+    &WbCount,\r
+    &WpCount,\r
+    &WcCount\r
     );\r
   GenerateValidAndConfigurableMtrrPairs (\r
-    SystemParameter->PhysicalAddressBits, RawMtrrRange,\r
-    UcCount, WtCount, WbCount, WpCount, WcCount\r
+    SystemParameter->PhysicalAddressBits,\r
+    RawMtrrRange,\r
+    UcCount,\r
+    WtCount,\r
+    WbCount,\r
+    WpCount,\r
+    WcCount\r
     );\r
 \r
   ExpectedVariableMtrrUsage = UcCount + WtCount + WbCount + WpCount + WcCount;\r
@@ -941,8 +981,10 @@ UnitTestMtrrSetMemoryAttributeInMtrrSettings (
   GetEffectiveMemoryRanges (\r
     SystemParameter->DefaultCacheType,\r
     SystemParameter->PhysicalAddressBits,\r
-    RawMtrrRange, ExpectedVariableMtrrUsage,\r
-    ExpectedMemoryRanges, &ExpectedMemoryRangesCount\r
+    RawMtrrRange,\r
+    ExpectedVariableMtrrUsage,\r
+    ExpectedMemoryRanges,\r
+    &ExpectedMemoryRangesCount\r
     );\r
 \r
   UT_LOG_INFO ("--- Expected Memory Ranges [%d] ---\n", ExpectedMemoryRangesCount);\r
@@ -964,7 +1006,7 @@ UnitTestMtrrSetMemoryAttributeInMtrrSettings (
                  ExpectedMemoryRanges[Index].Type\r
                  );\r
       UT_ASSERT_TRUE (Status == RETURN_SUCCESS || Status == RETURN_OUT_OF_RESOURCES || Status == RETURN_BUFFER_TOO_SMALL);\r
-      if (Status == RETURN_OUT_OF_RESOURCES || Status == RETURN_BUFFER_TOO_SMALL) {\r
+      if ((Status == RETURN_OUT_OF_RESOURCES) || (Status == RETURN_BUFFER_TOO_SMALL)) {\r
         return UNIT_TEST_SKIPPED;\r
       }\r
     }\r
@@ -973,10 +1015,16 @@ UnitTestMtrrSetMemoryAttributeInMtrrSettings (
       ZeroMem (&LocalMtrrs, sizeof (LocalMtrrs));\r
       MtrrGetAllMtrrs (&LocalMtrrs);\r
     }\r
+\r
     ActualMemoryRangesCount = ARRAY_SIZE (ActualMemoryRanges);\r
     CollectTestResult (\r
-      SystemParameter->DefaultCacheType, SystemParameter->PhysicalAddressBits, SystemParameter->VariableMtrrCount,\r
-      &LocalMtrrs, ActualMemoryRanges, &ActualMemoryRangesCount, &ActualVariableMtrrUsage\r
+      SystemParameter->DefaultCacheType,\r
+      SystemParameter->PhysicalAddressBits,\r
+      SystemParameter->VariableMtrrCount,\r
+      &LocalMtrrs,\r
+      ActualMemoryRanges,\r
+      &ActualMemoryRangesCount,\r
+      &ActualVariableMtrrUsage\r
       );\r
     UT_LOG_INFO ("--- Actual Memory Ranges [%d] ---\n", ActualMemoryRangesCount);\r
     DumpMemoryRanges (ActualMemoryRanges, ActualMemoryRangesCount);\r
@@ -989,7 +1037,6 @@ UnitTestMtrrSetMemoryAttributeInMtrrSettings (
   return UNIT_TEST_PASSED;\r
 }\r
 \r
-\r
 /**\r
   Prep routine for UnitTestGetFirmwareVariableMtrrCount().\r
 \r
@@ -1003,7 +1050,7 @@ SavePcdValue (
 {\r
   MTRR_LIB_GET_FIRMWARE_VARIABLE_MTRR_COUNT_CONTEXT  *LocalContext;\r
 \r
-  LocalContext = (MTRR_LIB_GET_FIRMWARE_VARIABLE_MTRR_COUNT_CONTEXT *) Context;\r
+  LocalContext                                = (MTRR_LIB_GET_FIRMWARE_VARIABLE_MTRR_COUNT_CONTEXT *)Context;\r
   LocalContext->NumberOfReservedVariableMtrrs = PatchPcdGet32 (PcdCpuNumberOfReservedVariableMtrrs);\r
   return UNIT_TEST_PASSED;\r
 }\r
@@ -1021,7 +1068,7 @@ RestorePcdValue (
 {\r
   MTRR_LIB_GET_FIRMWARE_VARIABLE_MTRR_COUNT_CONTEXT  *LocalContext;\r
 \r
-  LocalContext = (MTRR_LIB_GET_FIRMWARE_VARIABLE_MTRR_COUNT_CONTEXT *) Context;\r
+  LocalContext = (MTRR_LIB_GET_FIRMWARE_VARIABLE_MTRR_COUNT_CONTEXT *)Context;\r
   PatchPcdSet32 (PcdCpuNumberOfReservedVariableMtrrs, LocalContext->NumberOfReservedVariableMtrrs);\r
 }\r
 \r
@@ -1040,20 +1087,20 @@ STATIC
 EFI_STATUS\r
 EFIAPI\r
 UnitTestingEntry (\r
-  UINTN                       Iteration\r
+  UINTN  Iteration\r
   )\r
 {\r
-  EFI_STATUS                                        Status;\r
-  UNIT_TEST_FRAMEWORK_HANDLE                        Framework;\r
-  UNIT_TEST_SUITE_HANDLE                            MtrrApiTests;\r
-  UINTN                                             Index;\r
-  UINTN                                             SystemIndex;\r
-  MTRR_LIB_TEST_CONTEXT                             Context;\r
-  MTRR_LIB_GET_FIRMWARE_VARIABLE_MTRR_COUNT_CONTEXT GetFirmwareVariableMtrrCountContext;\r
+  EFI_STATUS                                         Status;\r
+  UNIT_TEST_FRAMEWORK_HANDLE                         Framework;\r
+  UNIT_TEST_SUITE_HANDLE                             MtrrApiTests;\r
+  UINTN                                              Index;\r
+  UINTN                                              SystemIndex;\r
+  MTRR_LIB_TEST_CONTEXT                              Context;\r
+  MTRR_LIB_GET_FIRMWARE_VARIABLE_MTRR_COUNT_CONTEXT  GetFirmwareVariableMtrrCountContext;\r
 \r
   Context.SystemParameter                             = &mDefaultSystemParameter;\r
   GetFirmwareVariableMtrrCountContext.SystemParameter = &mDefaultSystemParameter;\r
-  Framework = NULL;\r
+  Framework                                           = NULL;\r
 \r
   //\r
   // Setup the test framework for running the tests.\r
@@ -1077,24 +1124,26 @@ UnitTestingEntry (
     Status = EFI_OUT_OF_RESOURCES;\r
     goto EXIT;\r
   }\r
-  AddTestCase (MtrrApiTests, "Test IsMtrrSupported",                      "MtrrSupported",                        UnitTestIsMtrrSupported,                      NULL, NULL, &Context);\r
-  AddTestCase (MtrrApiTests, "Test GetVariableMtrrCount",                 "GetVariableMtrrCount",                 UnitTestGetVariableMtrrCount,                 NULL, NULL, &Context);\r
-  AddTestCase (MtrrApiTests, "Test GetFirmwareVariableMtrrCount",         "GetFirmwareVariableMtrrCount",         UnitTestGetFirmwareVariableMtrrCount,         SavePcdValue, RestorePcdValue, &GetFirmwareVariableMtrrCountContext);\r
-  AddTestCase (MtrrApiTests, "Test MtrrGetMemoryAttribute",               "MtrrGetMemoryAttribute",               UnitTestMtrrGetMemoryAttribute,               NULL, NULL, &Context);\r
-  AddTestCase (MtrrApiTests, "Test MtrrGetFixedMtrr",                     "MtrrGetFixedMtrr",                     UnitTestMtrrGetFixedMtrr,                     NULL, NULL, &Context);\r
-  AddTestCase (MtrrApiTests, "Test MtrrGetAllMtrrs",                      "MtrrGetAllMtrrs",                      UnitTestMtrrGetAllMtrrs,                      NULL, NULL, &Context);\r
-  AddTestCase (MtrrApiTests, "Test MtrrSetAllMtrrs",                      "MtrrSetAllMtrrs",                      UnitTestMtrrSetAllMtrrs,                      NULL, NULL, &Context);\r
+\r
+  AddTestCase (MtrrApiTests, "Test IsMtrrSupported", "MtrrSupported", UnitTestIsMtrrSupported, NULL, NULL, &Context);\r
+  AddTestCase (MtrrApiTests, "Test GetVariableMtrrCount", "GetVariableMtrrCount", UnitTestGetVariableMtrrCount, NULL, NULL, &Context);\r
+  AddTestCase (MtrrApiTests, "Test GetFirmwareVariableMtrrCount", "GetFirmwareVariableMtrrCount", UnitTestGetFirmwareVariableMtrrCount, SavePcdValue, RestorePcdValue, &GetFirmwareVariableMtrrCountContext);\r
+  AddTestCase (MtrrApiTests, "Test MtrrGetMemoryAttribute", "MtrrGetMemoryAttribute", UnitTestMtrrGetMemoryAttribute, NULL, NULL, &Context);\r
+  AddTestCase (MtrrApiTests, "Test MtrrGetFixedMtrr", "MtrrGetFixedMtrr", UnitTestMtrrGetFixedMtrr, NULL, NULL, &Context);\r
+  AddTestCase (MtrrApiTests, "Test MtrrGetAllMtrrs", "MtrrGetAllMtrrs", UnitTestMtrrGetAllMtrrs, NULL, NULL, &Context);\r
+  AddTestCase (MtrrApiTests, "Test MtrrSetAllMtrrs", "MtrrSetAllMtrrs", UnitTestMtrrSetAllMtrrs, NULL, NULL, &Context);\r
   AddTestCase (MtrrApiTests, "Test MtrrGetMemoryAttributeInVariableMtrr", "MtrrGetMemoryAttributeInVariableMtrr", UnitTestMtrrGetMemoryAttributeInVariableMtrr, NULL, NULL, &Context);\r
-  AddTestCase (MtrrApiTests, "Test MtrrDebugPrintAllMtrrs",               "MtrrDebugPrintAllMtrrs",               UnitTestMtrrDebugPrintAllMtrrs,               NULL, NULL, &Context);\r
-  AddTestCase (MtrrApiTests, "Test MtrrGetDefaultMemoryType",             "MtrrGetDefaultMemoryType",             UnitTestMtrrGetDefaultMemoryType,             NULL, NULL, &Context);\r
+  AddTestCase (MtrrApiTests, "Test MtrrDebugPrintAllMtrrs", "MtrrDebugPrintAllMtrrs", UnitTestMtrrDebugPrintAllMtrrs, NULL, NULL, &Context);\r
+  AddTestCase (MtrrApiTests, "Test MtrrGetDefaultMemoryType", "MtrrGetDefaultMemoryType", UnitTestMtrrGetDefaultMemoryType, NULL, NULL, &Context);\r
 \r
   for (SystemIndex = 0; SystemIndex < ARRAY_SIZE (mSystemParameters); SystemIndex++) {\r
     for (Index = 0; Index < Iteration; Index++) {\r
-      AddTestCase (MtrrApiTests, "Test InvalidMemoryLayouts",                  "InvalidMemoryLayouts",                  UnitTestInvalidMemoryLayouts,                  InitializeSystem, NULL, &mSystemParameters[SystemIndex]);\r
-      AddTestCase (MtrrApiTests, "Test MtrrSetMemoryAttributeInMtrrSettings",  "MtrrSetMemoryAttributeInMtrrSettings",  UnitTestMtrrSetMemoryAttributeInMtrrSettings,  InitializeSystem, NULL, &mSystemParameters[SystemIndex]);\r
+      AddTestCase (MtrrApiTests, "Test InvalidMemoryLayouts", "InvalidMemoryLayouts", UnitTestInvalidMemoryLayouts, InitializeSystem, NULL, &mSystemParameters[SystemIndex]);\r
+      AddTestCase (MtrrApiTests, "Test MtrrSetMemoryAttributeInMtrrSettings", "MtrrSetMemoryAttributeInMtrrSettings", UnitTestMtrrSetMemoryAttributeInMtrrSettings, InitializeSystem, NULL, &mSystemParameters[SystemIndex]);\r
       AddTestCase (MtrrApiTests, "Test MtrrSetMemoryAttributesInMtrrSettings", "MtrrSetMemoryAttributesInMtrrSettings", UnitTestMtrrSetMemoryAttributesInMtrrSettings, InitializeSystem, NULL, &mSystemParameters[SystemIndex]);\r
     }\r
   }\r
+\r
   //\r
   // Execute the tests.\r
   //\r
@@ -1118,14 +1167,14 @@ EXIT:
 **/\r
 INT32\r
 main (\r
-  INT32 Argc,\r
-  CHAR8 *Argv[]\r
+  INT32  Argc,\r
+  CHAR8  *Argv[]\r
   )\r
 {\r
-  UINTN    Count;\r
+  UINTN  Count;\r
 \r
   DEBUG ((DEBUG_INFO, "%a v%a\n", UNIT_TEST_APP_NAME, UNIT_TEST_APP_VERSION));\r
-  srand ((unsigned int) time (NULL));\r
+  srand ((unsigned int)time (NULL));\r
 \r
   //\r
   // MtrrLibUnitTest generate-random-numbers <path to MtrrLib/UnitTest/RandomNumber.c> <random-number count>\r

diff --git a/UefiCpuPkg/Library/MtrrLib/UnitTest/MtrrLibUnitTest.h b/UefiCpuPkg/Library/MtrrLib/UnitTest/MtrrLibUnitTest.h
index 071c858a4cc166ff92f24aeb50726fe62e240925..57e656c5550e48ab355cc013c6f189e70a6b5b08 100644 (file)
--- a/UefiCpuPkg/Library/MtrrLib/UnitTest/MtrrLibUnitTest.h
+++ b/UefiCpuPkg/Library/MtrrLib/UnitTest/MtrrLibUnitTest.h
@@ -29,21 +29,21 @@
 #include <Register/Cpuid.h>\r
 #include <Register/Msr.h>\r
 \r
-#define UNIT_TEST_APP_NAME        "MtrrLib Unit Tests"\r
-#define UNIT_TEST_APP_VERSION     "1.0"\r
+#define UNIT_TEST_APP_NAME     "MtrrLib Unit Tests"\r
+#define UNIT_TEST_APP_VERSION  "1.0"\r
 \r
-#define SCRATCH_BUFFER_SIZE       SIZE_16KB\r
+#define SCRATCH_BUFFER_SIZE  SIZE_16KB\r
 \r
 typedef struct {\r
-  UINT8                  PhysicalAddressBits;\r
-  BOOLEAN                MtrrSupported;\r
-  BOOLEAN                FixedMtrrSupported;\r
-  MTRR_MEMORY_CACHE_TYPE DefaultCacheType;\r
-  UINT32                 VariableMtrrCount;\r
+  UINT8                     PhysicalAddressBits;\r
+  BOOLEAN                   MtrrSupported;\r
+  BOOLEAN                   FixedMtrrSupported;\r
+  MTRR_MEMORY_CACHE_TYPE    DefaultCacheType;\r
+  UINT32                    VariableMtrrCount;\r
 } MTRR_LIB_SYSTEM_PARAMETER;\r
 \r
-extern UINT32                           mFixedMtrrsIndex[];\r
-extern BOOLEAN                          mRandomInput;\r
+extern UINT32   mFixedMtrrsIndex[];\r
+extern BOOLEAN  mRandomInput;\r
 \r
 /**\r
   Initialize the MTRR registers.\r
@@ -64,7 +64,7 @@ InitializeMtrrRegs (
 UNIT_TEST_STATUS\r
 EFIAPI\r
 InitializeSystem (\r
-  IN UNIT_TEST_CONTEXT        Context\r
+  IN UNIT_TEST_CONTEXT  Context\r
   );\r
 \r
 /**\r
@@ -88,13 +88,13 @@ GenerateRandomCacheType (
 **/\r
 VOID\r
 GenerateValidAndConfigurableMtrrPairs (\r
-  IN     UINT32                    PhysicalAddressBits,\r
-  IN OUT MTRR_MEMORY_RANGE         *RawMemoryRanges,\r
-  IN     UINT32                    UcCount,\r
-  IN     UINT32                    WtCount,\r
-  IN     UINT32                    WbCount,\r
-  IN     UINT32                    WpCount,\r
-  IN     UINT32                    WcCount\r
+  IN     UINT32             PhysicalAddressBits,\r
+  IN OUT MTRR_MEMORY_RANGE  *RawMemoryRanges,\r
+  IN     UINT32             UcCount,\r
+  IN     UINT32             WtCount,\r
+  IN     UINT32             WbCount,\r
+  IN     UINT32             WpCount,\r
+  IN     UINT32             WcCount\r
   );\r
 \r
 /**\r
@@ -109,12 +109,12 @@ GenerateValidAndConfigurableMtrrPairs (
 **/\r
 VOID\r
 GetEffectiveMemoryRanges (\r
-  IN MTRR_MEMORY_CACHE_TYPE DefaultType,\r
-  IN UINT32                 PhysicalAddressBits,\r
-  IN MTRR_MEMORY_RANGE      *RawMemoryRanges,\r
-  IN UINT32                 RawMemoryRangeCount,\r
-  OUT MTRR_MEMORY_RANGE     *MemoryRanges,\r
-  OUT UINTN                 *MemoryRangeCount\r
+  IN MTRR_MEMORY_CACHE_TYPE  DefaultType,\r
+  IN UINT32                  PhysicalAddressBits,\r
+  IN MTRR_MEMORY_RANGE       *RawMemoryRanges,\r
+  IN UINT32                  RawMemoryRangeCount,\r
+  OUT MTRR_MEMORY_RANGE      *MemoryRanges,\r
+  OUT UINTN                  *MemoryRangeCount\r
   );\r
 \r
 /**\r
@@ -127,10 +127,10 @@ GetEffectiveMemoryRanges (
 **/\r
 VOID\r
 GenerateRandomMtrrPair (\r
-  IN  UINT32                 PhysicalAddressBits,\r
-  IN  MTRR_MEMORY_CACHE_TYPE CacheType,\r
-  OUT MTRR_VARIABLE_SETTING  *MtrrPair        OPTIONAL,\r
-  OUT MTRR_MEMORY_RANGE      *MtrrMemoryRange OPTIONAL\r
+  IN  UINT32                  PhysicalAddressBits,\r
+  IN  MTRR_MEMORY_CACHE_TYPE  CacheType,\r
+  OUT MTRR_VARIABLE_SETTING   *MtrrPair        OPTIONAL,\r
+  OUT MTRR_MEMORY_RANGE       *MtrrMemoryRange OPTIONAL\r
   );\r
 \r
 /**\r
@@ -146,13 +146,13 @@ GenerateRandomMtrrPair (
 **/\r
 VOID\r
 CollectTestResult (\r
-  IN     MTRR_MEMORY_CACHE_TYPE DefaultType,\r
-  IN     UINT32                 PhysicalAddressBits,\r
-  IN     UINT32                 VariableMtrrCount,\r
-  IN     MTRR_SETTINGS          *Mtrrs,\r
-  OUT    MTRR_MEMORY_RANGE      *Ranges,\r
-  IN OUT UINTN                  *RangeCount,\r
-  OUT    UINT32                 *MtrrCount\r
+  IN     MTRR_MEMORY_CACHE_TYPE  DefaultType,\r
+  IN     UINT32                  PhysicalAddressBits,\r
+  IN     UINT32                  VariableMtrrCount,\r
+  IN     MTRR_SETTINGS           *Mtrrs,\r
+  OUT    MTRR_MEMORY_RANGE       *Ranges,\r
+  IN OUT UINTN                   *RangeCount,\r
+  OUT    UINT32                  *MtrrCount\r
   );\r
 \r
 /**\r
@@ -189,7 +189,8 @@ Random32 (
 **/\r
 VOID\r
 GenerateRandomNumbers (\r
-  CHAR8         *FilePath,\r
-  UINTN         Count\r
+  CHAR8  *FilePath,\r
+  UINTN  Count\r
   );\r
+\r
 #endif\r

diff --git a/UefiCpuPkg/Library/MtrrLib/UnitTest/RandomNumber.c b/UefiCpuPkg/Library/MtrrLib/UnitTest/RandomNumber.c
index 06104d892801957288252a4dc016e794efa32567..7190decc98cce93df5424f317ddc789d737aae8b 100644 (file)
--- a/UefiCpuPkg/Library/MtrrLib/UnitTest/RandomNumber.c
+++ b/UefiCpuPkg/Library/MtrrLib/UnitTest/RandomNumber.c
@@ -4,5006 +4,5006 @@
   Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>\r
   SPDX-License-Identifier: BSD-2-Clause-Patent\r
 **/\r
-UINTN mNumberCount = 50000;\r
-UINTN mNumbers[] = {\r
-  7791, 9427, 6867, 23807, 10984, 16661, 1863, 16690, 14810, 14550,\r
-  11382, 15755, 19806, 32737, 209, 14661, 4112, 13680, 2425, 15502,\r
-  25268, 2882, 29953, 12346, 27936, 8942, 21365, 17849, 13910, 21879,\r
-  3995, 6982, 2032, 6432, 3448, 28770, 8385, 31106, 4630, 32385,\r
-  31417, 21979, 22661, 18947, 10249, 22953, 30752, 32613, 2952, 25464,\r
-  17, 12473, 28757, 19960, 27672, 1875, 17598, 20306, 22152, 15814,\r
-  31841, 25276, 2962, 30223, 23953, 28748, 25029, 16399, 15868, 9993,\r
-  31702, 25663, 29322, 15688, 22429, 18079, 30344, 2870, 20065, 30191,\r
-  3589, 13233, 27221, 15138, 26492, 20316, 13666, 15632, 180, 19954,\r
-  25895, 3179, 21221, 474, 2111, 11252, 2588, 2556, 6338, 26862,\r
-  19424, 3540, 6158, 6099, 20758, 32708, 6087, 2375, 22306, 22959,\r
-  21532, 19274, 11343, 1987, 17228, 2737, 23409, 30102, 15977, 10455,\r
+UINTN  mNumberCount = 50000;\r
+UINTN  mNumbers[]   = {\r
+  7791,  9427,  6867,  23807, 10984, 16661, 1863,  16690, 14810, 14550,\r
+  11382, 15755, 19806, 32737, 209,   14661, 4112,  13680, 2425,  15502,\r
+  25268, 2882,  29953, 12346, 27936, 8942,  21365, 17849, 13910, 21879,\r
+  3995,  6982,  2032,  6432,  3448,  28770, 8385,  31106, 4630,  32385,\r
+  31417, 21979, 22661, 18947, 10249, 22953, 30752, 32613, 2952,  25464,\r
+  17,    12473, 28757, 19960, 27672, 1875,  17598, 20306, 22152, 15814,\r
+  31841, 25276, 2962,  30223, 23953, 28748, 25029, 16399, 15868, 9993,\r
+  31702, 25663, 29322, 15688, 22429, 18079, 30344, 2870,  20065, 30191,\r
+  3589,  13233, 27221, 15138, 26492, 20316, 13666, 15632, 180,   19954,\r
+  25895, 3179,  21221, 474,   2111,  11252, 2588,  2556,  6338,  26862,\r
+  19424, 3540,  6158,  6099,  20758, 32708, 6087,  2375,  22306, 22959,\r
+  21532, 19274, 11343, 1987,  17228, 2737,  23409, 30102, 15977, 10455,\r
   15049, 29045, 10077, 22928, 25128, 23033, 12330, 23902, 19543, 18906,\r
-  10102, 11240, 10167, 13832, 28230, 8871, 6693, 12792, 31498, 3043,\r
-  31776, 20028, 3546, 4574, 20270, 17751, 31231, 29263, 29563, 27343,\r
-  10421, 1553, 24772, 4228, 14639, 28957, 26227, 22079, 25052, 3766,\r
-  14092, 6030, 30441, 28131, 17095, 27600, 14855, 29218, 9599, 27788,\r
+  10102, 11240, 10167, 13832, 28230, 8871,  6693,  12792, 31498, 3043,\r
+  31776, 20028, 3546,  4574,  20270, 17751, 31231, 29263, 29563, 27343,\r
+  10421, 1553,  24772, 4228,  14639, 28957, 26227, 22079, 25052, 3766,\r
+  14092, 6030,  30441, 28131, 17095, 27600, 14855, 29218, 9599,  27788,\r
   22382, 27739, 11210, 13831, 13345, 16403, 13162, 22037, 29044, 26850,\r
-  27364, 7471, 18892, 29735, 13422, 1478, 10919, 17146, 12302, 9687,\r
-  12252, 10338, 12545, 24256, 25635, 14280, 8794, 16210, 27351, 22444,\r
-  7915, 19495, 30459, 27799, 16488, 8757, 13180, 12369, 27082, 10148,\r
-  181, 2387, 4338, 16093, 11064, 30335, 19343, 12260, 32716, 25359,\r
-  9025, 15335, 24754, 30412, 29951, 3863, 16429, 13952, 24502, 1206,\r
-  9281, 2221, 1586, 29041, 6074, 29311, 10306, 26609, 11376, 8448,\r
-  22295, 11181, 29386, 4747, 18670, 17922, 2689, 29827, 4079, 29061,\r
-  12454, 2372, 14420, 20376, 28391, 10842, 4557, 7227, 20494, 15090,\r
-  10275, 21541, 15818, 7821, 12060, 276, 27570, 2044, 26016, 8289,\r
-  29575, 13448, 13337, 22487, 1721, 26481, 2592, 27845, 22829, 14746,\r
-  16213, 12626, 10558, 4482, 31630, 23569, 2306, 22390, 27189, 32213,\r
-  19662, 14853, 15595, 2503, 17148, 5813, 16753, 9141, 6379, 23284,\r
-  3785, 10413, 4424, 29009, 3480, 9675, 28556, 3820, 24527, 12623,\r
-  15558, 29995, 27530, 23026, 18843, 31663, 3385, 8315, 4491, 30343,\r
+  27364, 7471,  18892, 29735, 13422, 1478,  10919, 17146, 12302, 9687,\r
+  12252, 10338, 12545, 24256, 25635, 14280, 8794,  16210, 27351, 22444,\r
+  7915,  19495, 30459, 27799, 16488, 8757,  13180, 12369, 27082, 10148,\r
+  181,   2387,  4338,  16093, 11064, 30335, 19343, 12260, 32716, 25359,\r
+  9025,  15335, 24754, 30412, 29951, 3863,  16429, 13952, 24502, 1206,\r
+  9281,  2221,  1586,  29041, 6074,  29311, 10306, 26609, 11376, 8448,\r
+  22295, 11181, 29386, 4747,  18670, 17922, 2689,  29827, 4079,  29061,\r
+  12454, 2372,  14420, 20376, 28391, 10842, 4557,  7227,  20494, 15090,\r
+  10275, 21541, 15818, 7821,  12060, 276,   27570, 2044,  26016, 8289,\r
+  29575, 13448, 13337, 22487, 1721,  26481, 2592,  27845, 22829, 14746,\r
+  16213, 12626, 10558, 4482,  31630, 23569, 2306,  22390, 27189, 32213,\r
+  19662, 14853, 15595, 2503,  17148, 5813,  16753, 9141,  6379,  23284,\r
+  3785,  10413, 4424,  29009, 3480,  9675,  28556, 3820,  24527, 12623,\r
+  15558, 29995, 27530, 23026, 18843, 31663, 3385,  8315,  4491,  30343,\r
   13565, 12173, 25462, 19619, 29525, 17859, 29534, 21131, 14585, 1535,\r
-  14702, 15697, 19974, 8702, 16955, 16835, 17500, 4912, 21579, 13286,\r
-  26948, 21959, 3796, 15008, 31319, 23054, 26053, 27573, 8603, 8189,\r
-  7946, 25589, 31982, 12554, 13580, 12211, 13480, 27713, 17016, 6008,\r
-  25980, 22679, 23362, 9465, 24991, 29052, 30441, 29767, 3372, 8623,\r
-  20476, 9542, 22984, 24662, 23773, 352, 9602, 9294, 17861, 10618,\r
-  252, 8640, 31752, 24615, 8400, 1525, 22171, 17436, 32301, 9579,\r
-  22483, 3813, 27329, 20520, 111, 11222, 7132, 16462, 21465, 15171,\r
-  28882, 22256, 29097, 22004, 30881, 6948, 26731, 9427, 31443, 12121,\r
-  9634, 8424, 1958, 12523, 9997, 3975, 21355, 13813, 20776, 3784,\r
-  24876, 23911, 3830, 17976, 16529, 9560, 7934, 4046, 25348, 31645,\r
-  12691, 11553, 19476, 15514, 15449, 23767, 8471, 5208, 9989, 25697,\r
-  23572, 30168, 13668, 25062, 9696, 7335, 21151, 31356, 7046, 19635,\r
-  8637, 14494, 748, 17501, 30569, 11995, 12980, 5327, 8438, 13003,\r
-  12641, 21648, 7328, 17479, 20411, 24661, 10005, 29913, 17012, 7707,\r
-  16948, 25458, 32523, 30322, 6420, 8283, 24561, 30748, 25928, 3438,\r
-  21483, 22998, 14689, 3718, 7351, 20086, 21685, 7732, 24818, 24374,\r
-  25695, 6836, 5433, 16464, 21895, 24351, 143, 21451, 7396, 31969,\r
-  24574, 20116, 6014, 10606, 28033, 13264, 26809, 13361, 20002, 6769,\r
-  31119, 6341, 11104, 28935, 32029, 360, 31699, 13273, 7777, 19885,\r
+  14702, 15697, 19974, 8702,  16955, 16835, 17500, 4912,  21579, 13286,\r
+  26948, 21959, 3796,  15008, 31319, 23054, 26053, 27573, 8603,  8189,\r
+  7946,  25589, 31982, 12554, 13580, 12211, 13480, 27713, 17016, 6008,\r
+  25980, 22679, 23362, 9465,  24991, 29052, 30441, 29767, 3372,  8623,\r
+  20476, 9542,  22984, 24662, 23773, 352,   9602,  9294,  17861, 10618,\r
+  252,   8640,  31752, 24615, 8400,  1525,  22171, 17436, 32301, 9579,\r
+  22483, 3813,  27329, 20520, 111,   11222, 7132,  16462, 21465, 15171,\r
+  28882, 22256, 29097, 22004, 30881, 6948,  26731, 9427,  31443, 12121,\r
+  9634,  8424,  1958,  12523, 9997,  3975,  21355, 13813, 20776, 3784,\r
+  24876, 23911, 3830,  17976, 16529, 9560,  7934,  4046,  25348, 31645,\r
+  12691, 11553, 19476, 15514, 15449, 23767, 8471,  5208,  9989,  25697,\r
+  23572, 30168, 13668, 25062, 9696,  7335,  21151, 31356, 7046,  19635,\r
+  8637,  14494, 748,   17501, 30569, 11995, 12980, 5327,  8438,  13003,\r
+  12641, 21648, 7328,  17479, 20411, 24661, 10005, 29913, 17012, 7707,\r
+  16948, 25458, 32523, 30322, 6420,  8283,  24561, 30748, 25928, 3438,\r
+  21483, 22998, 14689, 3718,  7351,  20086, 21685, 7732,  24818, 24374,\r
+  25695, 6836,  5433,  16464, 21895, 24351, 143,   21451, 7396,  31969,\r
+  24574, 20116, 6014,  10606, 28033, 13264, 26809, 13361, 20002, 6769,\r
+  31119, 6341,  11104, 28935, 32029, 360,   31699, 13273, 7777,  19885,\r
   16147, 18741, 15170, 29041, 12501, 30724, 20688, 16399, 14167, 11425,\r
-  31950, 30680, 4351, 32748, 14446, 8637, 1343, 13466, 12379, 6479,\r
-  7355, 7887, 24060, 20714, 9390, 10734, 17912, 9772, 393, 28848,\r
-  32757, 23212, 5342, 7027, 27558, 1257, 14973, 30933, 14084, 3457,\r
-  8413, 1154, 6619, 3236, 189, 20554, 27273, 7111, 30730, 887,\r
-  28674, 28573, 3076, 25693, 5400, 20035, 5789, 8242, 24826, 13755,\r
-  8993, 17696, 22778, 18075, 32284, 8857, 12179, 18182, 31865, 1003,\r
-  25770, 20956, 15847, 30996, 15124, 1582, 28289, 8663, 10073, 19189,\r
-  19373, 12047, 7095, 31491, 28740, 3652, 21866, 3385, 11252, 29564,\r
-  3883, 3323, 27107, 13651, 15607, 30433, 27285, 12110, 13585, 19887,\r
-  21776, 7789, 27210, 31624, 25406, 11263, 7040, 21342, 11666, 6842,\r
-  7269, 18093, 23022, 18955, 7041, 9065, 12741, 939, 2427, 28213,\r
-  25469, 18291, 1428, 11477, 29463, 2417, 29556, 13542, 7697, 5691,\r
-  7721, 21196, 13963, 4483, 3181, 23789, 14762, 17132, 27175, 1821,\r
-  9530, 9500, 11061, 2648, 20631, 27411, 19305, 29879, 19661, 28603,\r
-  20433, 13725, 4094, 17344, 27964, 14897, 28676, 19873, 30713, 11794,\r
-  12376, 12296, 226, 13382, 10034, 27223, 17306, 11379, 15858, 26499,\r
+  31950, 30680, 4351,  32748, 14446, 8637,  1343,  13466, 12379, 6479,\r
+  7355,  7887,  24060, 20714, 9390,  10734, 17912, 9772,  393,   28848,\r
+  32757, 23212, 5342,  7027,  27558, 1257,  14973, 30933, 14084, 3457,\r
+  8413,  1154,  6619,  3236,  189,   20554, 27273, 7111,  30730, 887,\r
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+  7039,  23576, 7453,  17229, 32757, 15243, 30351, 29919, 16841, 16812,\r
+  5004,  22786, 2122,  10406, 30057, 7247,  31745, 11243, 2717,  20710,\r
+  3545,  17096, 20241, 7592,  14724, 26942, 16791, 28070, 18201, 27405,\r
+  21175, 13272, 20482, 25873, 12466, 5907,  2837,  28881, 5313,  6709,\r
+  9217,  11862, 30110, 5283,  8684,  8249,  17221, 3829,  8538,  3584,\r
+  4092,  22511, 25937, 24747, 19089, 26035, 955,   11657, 28131, 22326,\r
+  12555, 25424, 18851, 10737, 28451, 19821, 18524, 30681, 9077,  24985,\r
+  22193, 20880, 22633, 2989,  20455, 2269,  11775, 27575, 5027,  32602,\r
+  15798, 14925, 10484, 19820, 30124, 18209, 4755,  21880, 12038, 17878,\r
+  14442, 5972,  914,   23826, 2644,  22524, 9899,  11221, 16420, 29063,\r
+  17758, 14601, 23272, 24409, 12747, 346,   19311, 23193, 24013, 5959,\r
+  25096, 6886,  26845, 2425,  27533, 3909,  17715, 852,   8096,  9054,\r
+  14383, 23501, 17461, 25833, 14840, 1659,  10833, 7523,  30819, 6896,\r
+  26640, 13317, 278,   26185, 29677, 27638, 22253, 15108, 1342,  21184,\r
+  30364, 29458, 24062, 29441, 3734,  22573, 25039, 8035,  28206, 26220,\r
+  7743,  27085, 28668, 7445,  10315, 6875,  25475, 20914, 29474, 15756,\r
+  14864, 14695, 1067,  4923,  31461, 7298,  10312, 977,   17047, 26708,\r
+  3677,  24120, 20917, 4928,  27404, 32019, 28330, 1809,  2499,  9132,\r
+  7909,  1424,  28409, 10029, 31543, 15191, 28596, 14356, 9084,  29920,\r
+  25167, 24545, 5501,  10721, 19578, 1809,  27413, 21212, 12930, 5968,\r
+  17299, 15601, 27603, 3563,  23648, 20472, 8379,  4740,  7394,  31436,\r
+  21872, 26121, 6559,  14825, 9813,  15847, 21158, 27706, 6521,  24442,\r
+  12587, 27180, 10592, 4040,  2161,  4871,  27911, 11120, 7661,  17534,\r
+  290,   31453, 31912, 28805, 5800,  5823,  6117,  17762, 19089, 28860,\r
+  260,   7175,  10975, 21602, 13478, 8351,  3291,  29793, 17170, 26983,\r
+  6305,  22519, 22487, 28607, 11742, 15531, 25779, 8065,  1497,  16446,\r
+  29620, 28817, 14000, 26335, 25757, 16053, 31716, 20894, 6539,  21415,\r
+  26648, 14627, 22232, 22377, 25622, 160,   23104, 6873,  7955,  29956,\r
 };\r

diff --git a/UefiCpuPkg/Library/MtrrLib/UnitTest/Support.c b/UefiCpuPkg/Library/MtrrLib/UnitTest/Support.c
index d8511fefe827f8856a05a51332cbabf92c15d127..748c403281dfd1f5891f44fbbe70f74236f73416 100644 (file)
--- a/UefiCpuPkg/Library/MtrrLib/UnitTest/Support.c
+++ b/UefiCpuPkg/Library/MtrrLib/UnitTest/Support.c
@@ -8,9 +8,9 @@
 \r
 #include "MtrrLibUnitTest.h"\r
 \r
-MTRR_MEMORY_CACHE_TYPE mMemoryCacheTypes[] = {\r
+MTRR_MEMORY_CACHE_TYPE  mMemoryCacheTypes[] = {\r
   CacheUncacheable, CacheWriteCombining, CacheWriteThrough, CacheWriteProtected, CacheWriteBack\r
-  };\r
+};\r
 \r
 UINT64                           mFixedMtrrsValue[MTRR_NUMBER_OF_FIXED_MTRR];\r
 MSR_IA32_MTRR_PHYSBASE_REGISTER  mVariableMtrrsPhysBase[MTRR_NUMBER_OF_VARIABLE_MTRR];\r
@@ -20,10 +20,10 @@ MSR_IA32_MTRRCAP_REGISTER        mMtrrCapMsr;
 CPUID_VERSION_INFO_EDX           mCpuidVersionInfoEdx;\r
 CPUID_VIR_PHY_ADDRESS_SIZE_EAX   mCpuidVirPhyAddressSizeEax;\r
 \r
-BOOLEAN                          mRandomInput;\r
-UINTN                            mNumberIndex = 0;\r
-extern UINTN                     mNumbers[];\r
-extern UINTN                     mNumberCount;\r
+BOOLEAN       mRandomInput;\r
+UINTN         mNumberIndex = 0;\r
+extern UINTN  mNumbers[];\r
+extern UINTN  mNumberCount;\r
 \r
 /**\r
   Return a random number between 0 and RAND_MAX.\r
@@ -65,8 +65,8 @@ CHAR8  mContentTemplate[] = {
 **/\r
 VOID\r
 GenerateRandomNumbers (\r
-  CHAR8         *FilePath,\r
-  UINTN         Count\r
+  CHAR8  *FilePath,\r
+  UINTN  Count\r
   )\r
 {\r
   FILE   *File;\r
@@ -78,8 +78,10 @@ GenerateRandomNumbers (
     if (Index % 10 == 0) {\r
       fprintf (File, "\n ");\r
     }\r
+\r
     fprintf (File, " %d,", rand ());\r
   }\r
+\r
   fprintf (File, "\n};\n");\r
   fclose (File);\r
 }\r
@@ -112,38 +114,41 @@ GenerateRandomNumbers (
 UINT32\r
 EFIAPI\r
 UnitTestMtrrLibAsmCpuid (\r
-  IN      UINT32                    Index,\r
-  OUT     UINT32                    *Eax   OPTIONAL,\r
-  OUT     UINT32                    *Ebx   OPTIONAL,\r
-  OUT     UINT32                    *Ecx   OPTIONAL,\r
-  OUT     UINT32                    *Edx   OPTIONAL\r
+  IN      UINT32  Index,\r
+  OUT     UINT32  *Eax   OPTIONAL,\r
+  OUT     UINT32  *Ebx   OPTIONAL,\r
+  OUT     UINT32  *Ecx   OPTIONAL,\r
+  OUT     UINT32  *Edx   OPTIONAL\r
   )\r
 {\r
   switch (Index) {\r
-  case CPUID_VERSION_INFO:\r
-    if (Edx != NULL) {\r
-      *Edx = mCpuidVersionInfoEdx.Uint32;\r
-    }\r
-    return Index;\r
-    break;\r
-  case CPUID_EXTENDED_FUNCTION:\r
-    if (Eax != NULL) {\r
-      *Eax = CPUID_VIR_PHY_ADDRESS_SIZE;\r
-    }\r
-    return Index;\r
-    break;\r
-  case CPUID_VIR_PHY_ADDRESS_SIZE:\r
-    if (Eax != NULL) {\r
-      *Eax = mCpuidVirPhyAddressSizeEax.Uint32;\r
-    }\r
-    return Index;\r
-    break;\r
+    case CPUID_VERSION_INFO:\r
+      if (Edx != NULL) {\r
+        *Edx = mCpuidVersionInfoEdx.Uint32;\r
+      }\r
+\r
+      return Index;\r
+      break;\r
+    case CPUID_EXTENDED_FUNCTION:\r
+      if (Eax != NULL) {\r
+        *Eax = CPUID_VIR_PHY_ADDRESS_SIZE;\r
+      }\r
+\r
+      return Index;\r
+      break;\r
+    case CPUID_VIR_PHY_ADDRESS_SIZE:\r
+      if (Eax != NULL) {\r
+        *Eax = mCpuidVirPhyAddressSizeEax.Uint32;\r
+      }\r
+\r
+      return Index;\r
+      break;\r
   }\r
 \r
   //\r
   // Should never fall through to here\r
   //\r
-  ASSERT(FALSE);\r
+  ASSERT (FALSE);\r
   return Index;\r
 }\r
 \r
@@ -163,11 +168,11 @@ UnitTestMtrrLibAsmCpuid (
 **/\r
 UINT64\r
 EFIAPI\r
-UnitTestMtrrLibAsmReadMsr64(\r
+UnitTestMtrrLibAsmReadMsr64 (\r
   IN UINT32  MsrIndex\r
   )\r
 {\r
-  UINT32 Index;\r
+  UINT32  Index;\r
 \r
   for (Index = 0; Index < ARRAY_SIZE (mFixedMtrrsValue); Index++) {\r
     if (MsrIndex == mFixedMtrrsIndex[Index]) {\r
@@ -176,7 +181,8 @@ UnitTestMtrrLibAsmReadMsr64(
   }\r
 \r
   if ((MsrIndex >= MSR_IA32_MTRR_PHYSBASE0) &&\r
-      (MsrIndex <= MSR_IA32_MTRR_PHYSMASK0 + (MTRR_NUMBER_OF_VARIABLE_MTRR << 1))) {\r
+      (MsrIndex <= MSR_IA32_MTRR_PHYSMASK0 + (MTRR_NUMBER_OF_VARIABLE_MTRR << 1)))\r
+  {\r
     if (MsrIndex % 2 == 0) {\r
       Index = (MsrIndex - MSR_IA32_MTRR_PHYSBASE0) >> 1;\r
       return mVariableMtrrsPhysBase[Index].Uint64;\r
@@ -197,7 +203,7 @@ UnitTestMtrrLibAsmReadMsr64(
   //\r
   // Should never fall through to here\r
   //\r
-  ASSERT(FALSE);\r
+  ASSERT (FALSE);\r
   return 0;\r
 }\r
 \r
@@ -220,12 +226,12 @@ UnitTestMtrrLibAsmReadMsr64(
 **/\r
 UINT64\r
 EFIAPI\r
-UnitTestMtrrLibAsmWriteMsr64(\r
-  IN      UINT32                    MsrIndex,\r
-  IN      UINT64                    Value\r
+UnitTestMtrrLibAsmWriteMsr64 (\r
+  IN      UINT32  MsrIndex,\r
+  IN      UINT64  Value\r
   )\r
 {\r
-  UINT32 Index;\r
+  UINT32  Index;\r
 \r
   for (Index = 0; Index < ARRAY_SIZE (mFixedMtrrsValue); Index++) {\r
     if (MsrIndex == mFixedMtrrsIndex[Index]) {\r
@@ -235,13 +241,14 @@ UnitTestMtrrLibAsmWriteMsr64(
   }\r
 \r
   if ((MsrIndex >= MSR_IA32_MTRR_PHYSBASE0) &&\r
-      (MsrIndex <= MSR_IA32_MTRR_PHYSMASK0 + (MTRR_NUMBER_OF_VARIABLE_MTRR << 1))) {\r
+      (MsrIndex <= MSR_IA32_MTRR_PHYSMASK0 + (MTRR_NUMBER_OF_VARIABLE_MTRR << 1)))\r
+  {\r
     if (MsrIndex % 2 == 0) {\r
-      Index = (MsrIndex - MSR_IA32_MTRR_PHYSBASE0) >> 1;\r
+      Index                                = (MsrIndex - MSR_IA32_MTRR_PHYSBASE0) >> 1;\r
       mVariableMtrrsPhysBase[Index].Uint64 = Value;\r
       return Value;\r
     } else {\r
-      Index = (MsrIndex - MSR_IA32_MTRR_PHYSMASK0) >> 1;\r
+      Index                                = (MsrIndex - MSR_IA32_MTRR_PHYSMASK0) >> 1;\r
       mVariableMtrrsPhysMask[Index].Uint64 = Value;\r
       return Value;\r
     }\r
@@ -260,7 +267,7 @@ UnitTestMtrrLibAsmWriteMsr64(
   //\r
   // Should never fall through to here\r
   //\r
-  ASSERT(FALSE);\r
+  ASSERT (FALSE);\r
   return 0;\r
 }\r
 \r
@@ -275,7 +282,7 @@ InitializeMtrrRegs (
   IN MTRR_LIB_SYSTEM_PARAMETER  *SystemParameter\r
   )\r
 {\r
-  UINT32                    Index;\r
+  UINT32  Index;\r
 \r
   SetMem (mFixedMtrrsValue, sizeof (mFixedMtrrsValue), SystemParameter->DefaultCacheType);\r
 \r
@@ -325,10 +332,10 @@ InitializeMtrrRegs (
 UNIT_TEST_STATUS\r
 EFIAPI\r
 InitializeSystem (\r
-  IN UNIT_TEST_CONTEXT        Context\r
+  IN UNIT_TEST_CONTEXT  Context\r
   )\r
 {\r
-  return InitializeMtrrRegs ((MTRR_LIB_SYSTEM_PARAMETER *) Context);\r
+  return InitializeMtrrRegs ((MTRR_LIB_SYSTEM_PARAMETER *)Context);\r
 }\r
 \r
 /**\r
@@ -344,34 +351,34 @@ InitializeSystem (
 **/\r
 VOID\r
 CollectTestResult (\r
-  IN     MTRR_MEMORY_CACHE_TYPE DefaultType,\r
-  IN     UINT32                 PhysicalAddressBits,\r
-  IN     UINT32                 VariableMtrrCount,\r
-  IN     MTRR_SETTINGS          *Mtrrs,\r
-  OUT    MTRR_MEMORY_RANGE      *Ranges,\r
-  IN OUT UINTN                  *RangeCount,\r
-  OUT    UINT32                 *MtrrCount\r
+  IN     MTRR_MEMORY_CACHE_TYPE  DefaultType,\r
+  IN     UINT32                  PhysicalAddressBits,\r
+  IN     UINT32                  VariableMtrrCount,\r
+  IN     MTRR_SETTINGS           *Mtrrs,\r
+  OUT    MTRR_MEMORY_RANGE       *Ranges,\r
+  IN OUT UINTN                   *RangeCount,\r
+  OUT    UINT32                  *MtrrCount\r
   )\r
 {\r
-  UINTN             Index;\r
-  UINT64            MtrrValidBitsMask;\r
-  UINT64            MtrrValidAddressMask;\r
-  MTRR_MEMORY_RANGE RawMemoryRanges[ARRAY_SIZE (Mtrrs->Variables.Mtrr)];\r
+  UINTN              Index;\r
+  UINT64             MtrrValidBitsMask;\r
+  UINT64             MtrrValidAddressMask;\r
+  MTRR_MEMORY_RANGE  RawMemoryRanges[ARRAY_SIZE (Mtrrs->Variables.Mtrr)];\r
 \r
   ASSERT (Mtrrs != NULL);\r
   ASSERT (VariableMtrrCount <= ARRAY_SIZE (Mtrrs->Variables.Mtrr));\r
 \r
-  MtrrValidBitsMask = (1ull << PhysicalAddressBits) - 1;\r
+  MtrrValidBitsMask    = (1ull << PhysicalAddressBits) - 1;\r
   MtrrValidAddressMask = MtrrValidBitsMask & ~0xFFFull;\r
 \r
   *MtrrCount = 0;\r
   for (Index = 0; Index < VariableMtrrCount; Index++) {\r
-    if (((MSR_IA32_MTRR_PHYSMASK_REGISTER *) &Mtrrs->Variables.Mtrr[Index].Mask)->Bits.V == 1) {\r
+    if (((MSR_IA32_MTRR_PHYSMASK_REGISTER *)&Mtrrs->Variables.Mtrr[Index].Mask)->Bits.V == 1) {\r
       RawMemoryRanges[*MtrrCount].BaseAddress = Mtrrs->Variables.Mtrr[Index].Base & MtrrValidAddressMask;\r
       RawMemoryRanges[*MtrrCount].Type        =\r
-        ((MSR_IA32_MTRR_PHYSBASE_REGISTER *) &Mtrrs->Variables.Mtrr[Index].Base)->Bits.Type;\r
-      RawMemoryRanges[*MtrrCount].Length      =\r
-          ((~(Mtrrs->Variables.Mtrr[Index].Mask & MtrrValidAddressMask)) & MtrrValidBitsMask) + 1;\r
+        ((MSR_IA32_MTRR_PHYSBASE_REGISTER *)&Mtrrs->Variables.Mtrr[Index].Base)->Bits.Type;\r
+      RawMemoryRanges[*MtrrCount].Length =\r
+        ((~(Mtrrs->Variables.Mtrr[Index].Mask & MtrrValidAddressMask)) & MtrrValidBitsMask) + 1;\r
       (*MtrrCount)++;\r
     }\r
   }\r
@@ -392,7 +399,7 @@ Random32 (
   UINT32  Limit\r
   )\r
 {\r
-  return (UINT32) (((double) Rand () / RAND_MAX) * (Limit - Start)) + Start;\r
+  return (UINT32)(((double)Rand () / RAND_MAX) * (Limit - Start)) + Start;\r
 }\r
 \r
 /**\r
@@ -408,7 +415,7 @@ Random64 (
   UINT64  Limit\r
   )\r
 {\r
-  return (UINT64) (((double) Rand () / RAND_MAX) * (Limit - Start)) + Start;\r
+  return (UINT64)(((double)Rand () / RAND_MAX) * (Limit - Start)) + Start;\r
 }\r
 \r
 /**\r
@@ -421,30 +428,30 @@ Random64 (
 **/\r
 VOID\r
 GenerateRandomMtrrPair (\r
-  IN  UINT32                 PhysicalAddressBits,\r
-  IN  MTRR_MEMORY_CACHE_TYPE CacheType,\r
-  OUT MTRR_VARIABLE_SETTING  *MtrrPair        OPTIONAL,\r
-  OUT MTRR_MEMORY_RANGE      *MtrrMemoryRange OPTIONAL\r
+  IN  UINT32                  PhysicalAddressBits,\r
+  IN  MTRR_MEMORY_CACHE_TYPE  CacheType,\r
+  OUT MTRR_VARIABLE_SETTING   *MtrrPair        OPTIONAL,\r
+  OUT MTRR_MEMORY_RANGE       *MtrrMemoryRange OPTIONAL\r
   )\r
 {\r
-  MSR_IA32_MTRR_PHYSBASE_REGISTER PhysBase;\r
-  MSR_IA32_MTRR_PHYSMASK_REGISTER PhysMask;\r
-  UINT32                          SizeShift;\r
-  UINT32                          BaseShift;\r
-  UINT64                          RandomBoundary;\r
-  UINT64                          MaxPhysicalAddress;\r
-  UINT64                          RangeSize;\r
-  UINT64                          RangeBase;\r
-  UINT64                          PhysBasePhyMaskValidBitsMask;\r
+  MSR_IA32_MTRR_PHYSBASE_REGISTER  PhysBase;\r
+  MSR_IA32_MTRR_PHYSMASK_REGISTER  PhysMask;\r
+  UINT32                           SizeShift;\r
+  UINT32                           BaseShift;\r
+  UINT64                           RandomBoundary;\r
+  UINT64                           MaxPhysicalAddress;\r
+  UINT64                           RangeSize;\r
+  UINT64                           RangeBase;\r
+  UINT64                           PhysBasePhyMaskValidBitsMask;\r
 \r
   MaxPhysicalAddress = 1ull << PhysicalAddressBits;\r
   do {\r
     SizeShift = Random32 (12, PhysicalAddressBits - 1);\r
     RangeSize = 1ull << SizeShift;\r
 \r
-    BaseShift = Random32 (SizeShift, PhysicalAddressBits - 1);\r
+    BaseShift      = Random32 (SizeShift, PhysicalAddressBits - 1);\r
     RandomBoundary = Random64 (0, 1ull << (PhysicalAddressBits - BaseShift));\r
-    RangeBase = RandomBoundary << BaseShift;\r
+    RangeBase      = RandomBoundary << BaseShift;\r
   } while (RangeBase < SIZE_1MB || RangeBase > MaxPhysicalAddress - 1);\r
 \r
   PhysBasePhyMaskValidBitsMask = (MaxPhysicalAddress - 1) & 0xfffffffffffff000ULL;\r
@@ -468,7 +475,6 @@ GenerateRandomMtrrPair (
   }\r
 }\r
 \r
-\r
 /**\r
   Check whether the Range overlaps with any one in Ranges.\r
 \r
@@ -480,9 +486,9 @@ GenerateRandomMtrrPair (
 **/\r
 BOOLEAN\r
 RangesOverlap (\r
-  IN MTRR_MEMORY_RANGE *Range,\r
-  IN MTRR_MEMORY_RANGE *Ranges,\r
-  IN UINTN             Count\r
+  IN MTRR_MEMORY_RANGE  *Range,\r
+  IN MTRR_MEMORY_RANGE  *Ranges,\r
+  IN UINTN              Count\r
   )\r
 {\r
   while (Count-- != 0) {\r
@@ -491,11 +497,13 @@ RangesOverlap (
     // 1. range#2.base is in the middle of range#1\r
     // 2. range#1.base is in the middle of range#2\r
     //\r
-    if ((Range->BaseAddress <= Ranges[Count].BaseAddress && Ranges[Count].BaseAddress < Range->BaseAddress + Range->Length)\r
-     || (Ranges[Count].BaseAddress <= Range->BaseAddress && Range->BaseAddress < Ranges[Count].BaseAddress + Ranges[Count].Length)) {\r
+    if (  ((Range->BaseAddress <= Ranges[Count].BaseAddress) && (Ranges[Count].BaseAddress < Range->BaseAddress + Range->Length))\r
+       || ((Ranges[Count].BaseAddress <= Range->BaseAddress) && (Range->BaseAddress < Ranges[Count].BaseAddress + Ranges[Count].Length)))\r
+    {\r
       return TRUE;\r
     }\r
   }\r
+\r
   return FALSE;\r
 }\r
 \r
@@ -512,16 +520,16 @@ RangesOverlap (
 **/\r
 VOID\r
 GenerateValidAndConfigurableMtrrPairs (\r
-  IN     UINT32                    PhysicalAddressBits,\r
-  IN OUT MTRR_MEMORY_RANGE         *RawMemoryRanges,\r
-  IN     UINT32                    UcCount,\r
-  IN     UINT32                    WtCount,\r
-  IN     UINT32                    WbCount,\r
-  IN     UINT32                    WpCount,\r
-  IN     UINT32                    WcCount\r
+  IN     UINT32             PhysicalAddressBits,\r
+  IN OUT MTRR_MEMORY_RANGE  *RawMemoryRanges,\r
+  IN     UINT32             UcCount,\r
+  IN     UINT32             WtCount,\r
+  IN     UINT32             WbCount,\r
+  IN     UINT32             WpCount,\r
+  IN     UINT32             WcCount\r
   )\r
 {\r
-  UINT32                          Index;\r
+  UINT32  Index;\r
 \r
   //\r
   // 1. Generate UC, WT, WB in order.\r
@@ -567,7 +575,7 @@ GenerateRandomCacheType (
   VOID\r
   )\r
 {\r
-    return mMemoryCacheTypes[Random32 (0, ARRAY_SIZE (mMemoryCacheTypes) - 1)];\r
+  return mMemoryCacheTypes[Random32 (0, ARRAY_SIZE (mMemoryCacheTypes) - 1)];\r
 }\r
 \r
 /**\r
@@ -586,19 +594,20 @@ GenerateRandomCacheType (
 **/\r
 INT32\r
 CompareFuncUint64 (\r
-  CONST VOID * Left,\r
-  CONST VOID * Right\r
+  CONST VOID  *Left,\r
+  CONST VOID  *Right\r
   )\r
 {\r
-    INT64 Delta;\r
-    Delta = (*(UINT64*)Left - *(UINT64*)Right);\r
-    if (Delta > 0) {\r
-      return 1;\r
-    } else if (Delta == 0) {\r
-      return 0;\r
-    } else {\r
-      return -1;\r
-    }\r
+  INT64  Delta;\r
+\r
+  Delta = (*(UINT64 *)Left - *(UINT64 *)Right);\r
+  if (Delta > 0) {\r
+    return 1;\r
+  } else if (Delta == 0) {\r
+    return 0;\r
+  } else {\r
+    return -1;\r
+  }\r
 }\r
 \r
 /**\r
@@ -611,13 +620,14 @@ CompareFuncUint64 (
 **/\r
 VOID\r
 DetermineMemoryCacheType (\r
-  IN     MTRR_MEMORY_CACHE_TYPE DefaultType,\r
-  IN OUT MTRR_MEMORY_RANGE      *Range,\r
-  IN     MTRR_MEMORY_RANGE      *Ranges,\r
-  IN     UINT32                 RangeCount\r
+  IN     MTRR_MEMORY_CACHE_TYPE  DefaultType,\r
+  IN OUT MTRR_MEMORY_RANGE       *Range,\r
+  IN     MTRR_MEMORY_RANGE       *Ranges,\r
+  IN     UINT32                  RangeCount\r
   )\r
 {\r
-  UINT32 Index;\r
+  UINT32  Index;\r
+\r
   Range->Type = CacheInvalid;\r
   for (Index = 0; Index < RangeCount; Index++) {\r
     if (RangesOverlap (Range, &Ranges[Index], 1)) {\r
@@ -643,16 +653,18 @@ DetermineMemoryCacheType (
 **/\r
 UINT32\r
 GetNextDifferentElementInSortedArray (\r
-  IN UINT32 Index,\r
-  IN UINT64 *Array,\r
-  IN UINT32 Count\r
+  IN UINT32  Index,\r
+  IN UINT64  *Array,\r
+  IN UINT32  Count\r
   )\r
 {\r
-  UINT64 CurrentElement;\r
+  UINT64  CurrentElement;\r
+\r
   CurrentElement = Array[Index];\r
   while (CurrentElement == Array[Index] && Index < Count) {\r
     Index++;\r
   }\r
+\r
   return Index;\r
 }\r
 \r
@@ -664,12 +676,12 @@ GetNextDifferentElementInSortedArray (
 **/\r
 VOID\r
 RemoveDuplicatesInSortedArray (\r
-  IN OUT UINT64 *Array,\r
-  IN OUT UINT32 *Count\r
+  IN OUT UINT64  *Array,\r
+  IN OUT UINT32  *Count\r
   )\r
 {\r
-  UINT32 Index;\r
-  UINT32 NewCount;\r
+  UINT32  Index;\r
+  UINT32  NewCount;\r
 \r
   Index    = 0;\r
   NewCount = 0;\r
@@ -678,6 +690,7 @@ RemoveDuplicatesInSortedArray (
     NewCount++;\r
     Index = GetNextDifferentElementInSortedArray (Index, Array, *Count);\r
   }\r
+\r
   *Count = NewCount;\r
 }\r
 \r
@@ -690,11 +703,11 @@ RemoveDuplicatesInSortedArray (
 **/\r
 BOOLEAN\r
 AddressInRange (\r
-  IN UINT64            Address,\r
-  IN MTRR_MEMORY_RANGE Range\r
+  IN UINT64             Address,\r
+  IN MTRR_MEMORY_RANGE  Range\r
   )\r
 {\r
-    return (Address >= Range.BaseAddress) && (Address <= Range.BaseAddress + Range.Length - 1);\r
+  return (Address >= Range.BaseAddress) && (Address <= Range.BaseAddress + Range.Length - 1);\r
 }\r
 \r
 /**\r
@@ -706,13 +719,14 @@ AddressInRange (
 **/\r
 UINT64\r
 GetOverlapBitFlag (\r
-  IN MTRR_MEMORY_RANGE *RawMemoryRanges,\r
-  IN UINT32            RawMemoryRangeCount,\r
-  IN UINT64            Address\r
+  IN MTRR_MEMORY_RANGE  *RawMemoryRanges,\r
+  IN UINT32             RawMemoryRangeCount,\r
+  IN UINT64             Address\r
   )\r
 {\r
-  UINT64 OverlapBitFlag;\r
-  UINT32 Index;\r
+  UINT64  OverlapBitFlag;\r
+  UINT32  Index;\r
+\r
   OverlapBitFlag = 0;\r
   for (Index = 0; Index < RawMemoryRangeCount; Index++) {\r
     if (AddressInRange (Address, RawMemoryRanges[Index])) {\r
@@ -736,14 +750,23 @@ GetOverlapBitFlag (
 **/\r
 UINT32\r
 CheckOverlapBitFlagsRelation (\r
-  IN UINT64 Flag1,\r
-  IN UINT64 Flag2\r
+  IN UINT64  Flag1,\r
+  IN UINT64  Flag2\r
   )\r
 {\r
-    if (Flag1 == Flag2) return 0;\r
-    if ((Flag1 | Flag2) == Flag2) return 1;\r
-    if ((Flag1 | Flag2) == Flag1) return 2;\r
-    return 3;\r
+  if (Flag1 == Flag2) {\r
+    return 0;\r
+  }\r
+\r
+  if ((Flag1 | Flag2) == Flag2) {\r
+    return 1;\r
+  }\r
+\r
+  if ((Flag1 | Flag2) == Flag1) {\r
+    return 2;\r
+  }\r
+\r
+  return 3;\r
 }\r
 \r
 /**\r
@@ -758,20 +781,21 @@ CheckOverlapBitFlagsRelation (
 **/\r
 BOOLEAN\r
 IsEndpointInRanges (\r
-  IN UINT64            Endpoint,\r
-  IN MTRR_MEMORY_RANGE *Ranges,\r
-  IN UINTN             RangeCount\r
+  IN UINT64             Endpoint,\r
+  IN MTRR_MEMORY_RANGE  *Ranges,\r
+  IN UINTN              RangeCount\r
   )\r
 {\r
-    UINT32 Index;\r
-    for (Index = 0; Index < RangeCount; Index++) {\r
-      if (AddressInRange (Endpoint, Ranges[Index])) {\r
-        return TRUE;\r
-      }\r
+  UINT32  Index;\r
+\r
+  for (Index = 0; Index < RangeCount; Index++) {\r
+    if (AddressInRange (Endpoint, Ranges[Index])) {\r
+      return TRUE;\r
     }\r
-    return FALSE;\r
-}\r
+  }\r
 \r
+  return FALSE;\r
+}\r
 \r
 /**\r
   Compact adjacent ranges of the same type.\r
@@ -783,26 +807,26 @@ IsEndpointInRanges (
 **/\r
 VOID\r
 CompactAndExtendEffectiveMtrrMemoryRanges (\r
-  IN     MTRR_MEMORY_CACHE_TYPE DefaultType,\r
-  IN     UINT32                 PhysicalAddressBits,\r
-  IN OUT MTRR_MEMORY_RANGE      **EffectiveMtrrMemoryRanges,\r
-  IN OUT UINTN                  *EffectiveMtrrMemoryRangesCount\r
+  IN     MTRR_MEMORY_CACHE_TYPE  DefaultType,\r
+  IN     UINT32                  PhysicalAddressBits,\r
+  IN OUT MTRR_MEMORY_RANGE       **EffectiveMtrrMemoryRanges,\r
+  IN OUT UINTN                   *EffectiveMtrrMemoryRangesCount\r
   )\r
 {\r
-  UINT64                        MaxAddress;\r
-  UINTN                         NewRangesCountAtMost;\r
-  MTRR_MEMORY_RANGE             *NewRanges;\r
-  UINTN                         NewRangesCountActual;\r
-  MTRR_MEMORY_RANGE             *CurrentRangeInNewRanges;\r
-  MTRR_MEMORY_CACHE_TYPE        CurrentRangeTypeInOldRanges;\r
+  UINT64                  MaxAddress;\r
+  UINTN                   NewRangesCountAtMost;\r
+  MTRR_MEMORY_RANGE       *NewRanges;\r
+  UINTN                   NewRangesCountActual;\r
+  MTRR_MEMORY_RANGE       *CurrentRangeInNewRanges;\r
+  MTRR_MEMORY_CACHE_TYPE  CurrentRangeTypeInOldRanges;\r
 \r
-  MTRR_MEMORY_RANGE             *OldRanges;\r
-  MTRR_MEMORY_RANGE             OldLastRange;\r
-  UINTN                         OldRangesIndex;\r
+  MTRR_MEMORY_RANGE  *OldRanges;\r
+  MTRR_MEMORY_RANGE  OldLastRange;\r
+  UINTN              OldRangesIndex;\r
 \r
   NewRangesCountActual = 0;\r
   NewRangesCountAtMost = *EffectiveMtrrMemoryRangesCount + 2;   // At most with 2 more range entries.\r
-  NewRanges            = (MTRR_MEMORY_RANGE *) calloc (NewRangesCountAtMost, sizeof (MTRR_MEMORY_RANGE));\r
+  NewRanges            = (MTRR_MEMORY_RANGE *)calloc (NewRangesCountAtMost, sizeof (MTRR_MEMORY_RANGE));\r
   OldRanges            = *EffectiveMtrrMemoryRanges;\r
   if (OldRanges[0].BaseAddress > 0) {\r
     NewRanges[NewRangesCountActual].BaseAddress = 0;\r
@@ -814,44 +838,45 @@ CompactAndExtendEffectiveMtrrMemoryRanges (
   OldRangesIndex = 0;\r
   while (OldRangesIndex < *EffectiveMtrrMemoryRangesCount) {\r
     CurrentRangeTypeInOldRanges = OldRanges[OldRangesIndex].Type;\r
-    CurrentRangeInNewRanges = NULL;\r
-    if (NewRangesCountActual > 0)   // We need to check CurrentNewRange first before generate a new NewRange.\r
-    {\r
+    CurrentRangeInNewRanges     = NULL;\r
+    if (NewRangesCountActual > 0) {\r
+      // We need to check CurrentNewRange first before generate a new NewRange.\r
       CurrentRangeInNewRanges = &NewRanges[NewRangesCountActual - 1];\r
     }\r
-    if (CurrentRangeInNewRanges != NULL && CurrentRangeInNewRanges->Type == CurrentRangeTypeInOldRanges) {\r
+\r
+    if ((CurrentRangeInNewRanges != NULL) && (CurrentRangeInNewRanges->Type == CurrentRangeTypeInOldRanges)) {\r
       CurrentRangeInNewRanges->Length += OldRanges[OldRangesIndex].Length;\r
     } else {\r
       NewRanges[NewRangesCountActual].BaseAddress = OldRanges[OldRangesIndex].BaseAddress;\r
       NewRanges[NewRangesCountActual].Length     += OldRanges[OldRangesIndex].Length;\r
       NewRanges[NewRangesCountActual].Type        = CurrentRangeTypeInOldRanges;\r
-      while (OldRangesIndex + 1 < *EffectiveMtrrMemoryRangesCount && OldRanges[OldRangesIndex + 1].Type == CurrentRangeTypeInOldRanges)\r
-      {\r
+      while (OldRangesIndex + 1 < *EffectiveMtrrMemoryRangesCount && OldRanges[OldRangesIndex + 1].Type == CurrentRangeTypeInOldRanges) {\r
         OldRangesIndex++;\r
         NewRanges[NewRangesCountActual].Length += OldRanges[OldRangesIndex].Length;\r
       }\r
+\r
       NewRangesCountActual++;\r
     }\r
 \r
     OldRangesIndex++;\r
   }\r
 \r
-  MaxAddress = (1ull << PhysicalAddressBits) - 1;\r
-  OldLastRange = OldRanges[(*EffectiveMtrrMemoryRangesCount) - 1];\r
+  MaxAddress              = (1ull << PhysicalAddressBits) - 1;\r
+  OldLastRange            = OldRanges[(*EffectiveMtrrMemoryRangesCount) - 1];\r
   CurrentRangeInNewRanges = &NewRanges[NewRangesCountActual - 1];\r
   if (OldLastRange.BaseAddress + OldLastRange.Length - 1 < MaxAddress) {\r
     if (CurrentRangeInNewRanges->Type == DefaultType) {\r
       CurrentRangeInNewRanges->Length = MaxAddress - CurrentRangeInNewRanges->BaseAddress + 1;\r
     } else {\r
       NewRanges[NewRangesCountActual].BaseAddress = OldLastRange.BaseAddress + OldLastRange.Length;\r
-      NewRanges[NewRangesCountActual].Length = MaxAddress - NewRanges[NewRangesCountActual].BaseAddress + 1;\r
-      NewRanges[NewRangesCountActual].Type = DefaultType;\r
+      NewRanges[NewRangesCountActual].Length      = MaxAddress - NewRanges[NewRangesCountActual].BaseAddress + 1;\r
+      NewRanges[NewRangesCountActual].Type        = DefaultType;\r
       NewRangesCountActual++;\r
     }\r
   }\r
 \r
   free (*EffectiveMtrrMemoryRanges);\r
-  *EffectiveMtrrMemoryRanges = NewRanges;\r
+  *EffectiveMtrrMemoryRanges      = NewRanges;\r
   *EffectiveMtrrMemoryRangesCount = NewRangesCountActual;\r
 }\r
 \r
@@ -865,20 +890,20 @@ CompactAndExtendEffectiveMtrrMemoryRanges (
 **/\r
 VOID\r
 CollectEndpoints (\r
-  IN OUT UINT64        *Endpoints,\r
-  IN OUT UINT32        *EndPointCount,\r
-  IN MTRR_MEMORY_RANGE *RawMemoryRanges,\r
-  IN UINT32            RawMemoryRangeCount\r
+  IN OUT UINT64         *Endpoints,\r
+  IN OUT UINT32         *EndPointCount,\r
+  IN MTRR_MEMORY_RANGE  *RawMemoryRanges,\r
+  IN UINT32             RawMemoryRangeCount\r
   )\r
 {\r
-  UINT32 Index;\r
-  UINT32 RawRangeIndex;\r
+  UINT32  Index;\r
+  UINT32  RawRangeIndex;\r
 \r
   ASSERT ((RawMemoryRangeCount << 1) == *EndPointCount);\r
 \r
   for (Index = 0; Index < *EndPointCount; Index += 2) {\r
-    RawRangeIndex = Index >> 1;\r
-    Endpoints[Index] = RawMemoryRanges[RawRangeIndex].BaseAddress;\r
+    RawRangeIndex        = Index >> 1;\r
+    Endpoints[Index]     = RawMemoryRanges[RawRangeIndex].BaseAddress;\r
     Endpoints[Index + 1] = RawMemoryRanges[RawRangeIndex].BaseAddress + RawMemoryRanges[RawRangeIndex].Length - 1;\r
   }\r
 \r
@@ -898,41 +923,41 @@ CollectEndpoints (
 **/\r
 VOID\r
 GetEffectiveMemoryRanges (\r
-  IN MTRR_MEMORY_CACHE_TYPE DefaultType,\r
-  IN UINT32                 PhysicalAddressBits,\r
-  IN MTRR_MEMORY_RANGE      *RawMemoryRanges,\r
-  IN UINT32                 RawMemoryRangeCount,\r
-  OUT MTRR_MEMORY_RANGE     *MemoryRanges,\r
-  OUT UINTN                 *MemoryRangeCount\r
+  IN MTRR_MEMORY_CACHE_TYPE  DefaultType,\r
+  IN UINT32                  PhysicalAddressBits,\r
+  IN MTRR_MEMORY_RANGE       *RawMemoryRanges,\r
+  IN UINT32                  RawMemoryRangeCount,\r
+  OUT MTRR_MEMORY_RANGE      *MemoryRanges,\r
+  OUT UINTN                  *MemoryRangeCount\r
   )\r
 {\r
-  UINTN                 Index;\r
-  UINT32                AllEndPointsCount;\r
-  UINT64                *AllEndPointsInclusive;\r
-  UINT32                AllRangePiecesCountMax;\r
-  MTRR_MEMORY_RANGE     *AllRangePieces;\r
-  UINTN                 AllRangePiecesCountActual;\r
-  UINT64                OverlapBitFlag1;\r
-  UINT64                OverlapBitFlag2;\r
-  INT32                 OverlapFlagRelation;\r
+  UINTN              Index;\r
+  UINT32             AllEndPointsCount;\r
+  UINT64             *AllEndPointsInclusive;\r
+  UINT32             AllRangePiecesCountMax;\r
+  MTRR_MEMORY_RANGE  *AllRangePieces;\r
+  UINTN              AllRangePiecesCountActual;\r
+  UINT64             OverlapBitFlag1;\r
+  UINT64             OverlapBitFlag2;\r
+  INT32              OverlapFlagRelation;\r
 \r
   if (RawMemoryRangeCount == 0) {\r
     MemoryRanges[0].BaseAddress = 0;\r
     MemoryRanges[0].Length      = (1ull << PhysicalAddressBits);\r
     MemoryRanges[0].Type        = DefaultType;\r
-    *MemoryRangeCount = 1;\r
+    *MemoryRangeCount           = 1;\r
     return;\r
   }\r
 \r
-  AllEndPointsCount         = RawMemoryRangeCount << 1;\r
-  AllEndPointsInclusive     = calloc (AllEndPointsCount, sizeof (UINT64));\r
-  AllRangePiecesCountMax    = RawMemoryRangeCount * 3 + 1;\r
-  AllRangePieces            = calloc (AllRangePiecesCountMax, sizeof (MTRR_MEMORY_RANGE));\r
+  AllEndPointsCount      = RawMemoryRangeCount << 1;\r
+  AllEndPointsInclusive  = calloc (AllEndPointsCount, sizeof (UINT64));\r
+  AllRangePiecesCountMax = RawMemoryRangeCount * 3 + 1;\r
+  AllRangePieces         = calloc (AllRangePiecesCountMax, sizeof (MTRR_MEMORY_RANGE));\r
   CollectEndpoints (AllEndPointsInclusive, &AllEndPointsCount, RawMemoryRanges, RawMemoryRangeCount);\r
 \r
   for (Index = 0, AllRangePiecesCountActual = 0; Index < AllEndPointsCount - 1; Index++) {\r
-    OverlapBitFlag1 = GetOverlapBitFlag (RawMemoryRanges, RawMemoryRangeCount, AllEndPointsInclusive[Index]);\r
-    OverlapBitFlag2 = GetOverlapBitFlag (RawMemoryRanges, RawMemoryRangeCount, AllEndPointsInclusive[Index + 1]);\r
+    OverlapBitFlag1     = GetOverlapBitFlag (RawMemoryRanges, RawMemoryRangeCount, AllEndPointsInclusive[Index]);\r
+    OverlapBitFlag2     = GetOverlapBitFlag (RawMemoryRanges, RawMemoryRangeCount, AllEndPointsInclusive[Index + 1]);\r
     OverlapFlagRelation = CheckOverlapBitFlagsRelation (OverlapBitFlag1, OverlapBitFlag2);\r
     switch (OverlapFlagRelation) {\r
       case 0:   // [1, 2]\r
@@ -955,18 +980,23 @@ GetEffectiveMemoryRanges (
           AllRangePieces[AllRangePiecesCountActual].Length      = 1;\r
           AllRangePiecesCountActual++;\r
         }\r
+\r
         break;\r
       case 3:   // (1, 2)\r
         AllRangePieces[AllRangePiecesCountActual].BaseAddress = AllEndPointsInclusive[Index] + 1;\r
         AllRangePieces[AllRangePiecesCountActual].Length      = (AllEndPointsInclusive[Index + 1] - 1) - (AllEndPointsInclusive[Index] + 1) + 1;\r
-        if (AllRangePieces[AllRangePiecesCountActual].Length == 0)   // Only in case 3 can exists Length=0, we should skip such "segment".\r
+        if (AllRangePieces[AllRangePiecesCountActual].Length == 0) {\r
+          // Only in case 3 can exists Length=0, we should skip such "segment".\r
           break;\r
+        }\r
+\r
         AllRangePiecesCountActual++;\r
         if (!IsEndpointInRanges (AllEndPointsInclusive[Index], AllRangePieces, AllRangePiecesCountActual)) {\r
           AllRangePieces[AllRangePiecesCountActual].BaseAddress = AllEndPointsInclusive[Index];\r
           AllRangePieces[AllRangePiecesCountActual].Length      = 1;\r
           AllRangePiecesCountActual++;\r
         }\r
+\r
         break;\r
       default:\r
         ASSERT (FALSE);\r

diff --git a/UefiCpuPkg/Library/PlatformSecLibNull/PlatformSecLibNull.c b/UefiCpuPkg/Library/PlatformSecLibNull/PlatformSecLibNull.c
index cebaa81399bb2c351ada4adac48ff0b5e165c8b2..9f71c2611cfbe5613e5b5582868b0c1b18c53cc0 100644 (file)
--- a/UefiCpuPkg/Library/PlatformSecLibNull/PlatformSecLibNull.c
+++ b/UefiCpuPkg/Library/PlatformSecLibNull/PlatformSecLibNull.c
@@ -30,7 +30,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
 EFI_PEI_PPI_DESCRIPTOR *\r
 EFIAPI\r
 SecPlatformMain (\r
-  IN OUT   EFI_SEC_PEI_HAND_OFF        *SecCoreData\r
+  IN OUT   EFI_SEC_PEI_HAND_OFF  *SecCoreData\r
   )\r
 {\r
   return NULL;\r
@@ -50,9 +50,9 @@ SecPlatformMain (
 EFI_STATUS\r
 EFIAPI\r
 SecPlatformInformation (\r
-  IN CONST EFI_PEI_SERVICES                     **PeiServices,\r
-  IN OUT   UINT64                               *StructureSize,\r
-     OUT   EFI_SEC_PLATFORM_INFORMATION_RECORD  *PlatformInformationRecord\r
+  IN CONST EFI_PEI_SERVICES                  **PeiServices,\r
+  IN OUT   UINT64                            *StructureSize,\r
+  OUT   EFI_SEC_PLATFORM_INFORMATION_RECORD  *PlatformInformationRecord\r
   )\r
 {\r
   return EFI_SUCCESS;\r

diff --git a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
index 2f77ab3aeb559b1f6a3565dcf06470e7e19b395a..a8e4f920fc9e7e90159729a07d9365bd1961d76d 100644 (file)
--- a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
+++ b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
@@ -8,7 +8,7 @@
 \r
 #include "RegisterCpuFeatures.h"\r
 \r
-CHAR16 *mDependTypeStr[]   = {L"None", L"Thread", L"Core", L"Package", L"Invalid" };\r
+CHAR16  *mDependTypeStr[] = { L"None", L"Thread", L"Core", L"Package", L"Invalid" };\r
 \r
 /**\r
   Worker function to save PcdCpuFeaturesCapability.\r
@@ -19,11 +19,11 @@ CHAR16 *mDependTypeStr[]   = {L"None", L"Thread", L"Core", L"Package", L"Invalid
 **/\r
 VOID\r
 SetCapabilityPcd (\r
-  IN UINT8               *SupportedFeatureMask,\r
-  IN UINTN               BitMaskSize\r
+  IN UINT8  *SupportedFeatureMask,\r
+  IN UINTN  BitMaskSize\r
   )\r
 {\r
-  EFI_STATUS             Status;\r
+  EFI_STATUS  Status;\r
 \r
   Status = PcdSetPtrS (PcdCpuFeaturesCapability, &BitMaskSize, SupportedFeatureMask);\r
   ASSERT_EFI_ERROR (Status);\r
@@ -37,11 +37,11 @@ SetCapabilityPcd (
 **/\r
 VOID\r
 SetSettingPcd (\r
-  IN UINT8               *SupportedFeatureMask,\r
-  IN UINTN               BitMaskSize\r
+  IN UINT8  *SupportedFeatureMask,\r
+  IN UINTN  BitMaskSize\r
   )\r
 {\r
-  EFI_STATUS             Status;\r
+  EFI_STATUS  Status;\r
 \r
   Status = PcdSetPtrS (PcdCpuFeaturesSetting, &BitMaskSize, SupportedFeatureMask);\r
   ASSERT_EFI_ERROR (Status);\r
@@ -54,14 +54,14 @@ SetSettingPcd (
 **/\r
 VOID\r
 FillProcessorInfo (\r
-  IN OUT REGISTER_CPU_FEATURE_INFORMATION        *CpuInfo\r
+  IN OUT REGISTER_CPU_FEATURE_INFORMATION  *CpuInfo\r
   )\r
 {\r
-  CPUID_VERSION_INFO_EAX Eax;\r
-  CPUID_VERSION_INFO_ECX Ecx;\r
-  CPUID_VERSION_INFO_EDX Edx;\r
-  UINT32                 DisplayedFamily;\r
-  UINT32                 DisplayedModel;\r
+  CPUID_VERSION_INFO_EAX  Eax;\r
+  CPUID_VERSION_INFO_ECX  Ecx;\r
+  CPUID_VERSION_INFO_EDX  Edx;\r
+  UINT32                  DisplayedFamily;\r
+  UINT32                  DisplayedModel;\r
 \r
   AsmCpuid (CPUID_VERSION_INFO, &Eax.Uint32, NULL, &Ecx.Uint32, &Edx.Uint32);\r
 \r
@@ -71,14 +71,14 @@ FillProcessorInfo (
   }\r
 \r
   DisplayedModel = Eax.Bits.Model;\r
-  if (Eax.Bits.FamilyId == 0x06 || Eax.Bits.FamilyId == 0x0f) {\r
+  if ((Eax.Bits.FamilyId == 0x06) || (Eax.Bits.FamilyId == 0x0f)) {\r
     DisplayedModel |= (Eax.Bits.ExtendedModelId << 4);\r
   }\r
 \r
-  CpuInfo->DisplayFamily = DisplayedFamily;\r
-  CpuInfo->DisplayModel  = DisplayedModel;\r
-  CpuInfo->SteppingId    = Eax.Bits.SteppingId;\r
-  CpuInfo->ProcessorType = Eax.Bits.ProcessorType;\r
+  CpuInfo->DisplayFamily              = DisplayedFamily;\r
+  CpuInfo->DisplayModel               = DisplayedModel;\r
+  CpuInfo->SteppingId                 = Eax.Bits.SteppingId;\r
+  CpuInfo->ProcessorType              = Eax.Bits.ProcessorType;\r
   CpuInfo->CpuIdVersionInfoEcx.Uint32 = Ecx.Uint32;\r
   CpuInfo->CpuIdVersionInfoEdx.Uint32 = Edx.Uint32;\r
 }\r
@@ -92,29 +92,29 @@ CpuInitDataInitialize (
   VOID\r
   )\r
 {\r
-  EFI_STATUS                           Status;\r
-  UINTN                                ProcessorNumber;\r
-  EFI_PROCESSOR_INFORMATION            ProcessorInfoBuffer;\r
-  CPU_FEATURES_ENTRY                   *CpuFeature;\r
-  CPU_FEATURES_INIT_ORDER              *InitOrder;\r
-  CPU_FEATURES_DATA                    *CpuFeaturesData;\r
-  LIST_ENTRY                           *Entry;\r
-  UINT32                               Core;\r
-  UINT32                               Package;\r
-  UINT32                               Thread;\r
-  EFI_CPU_PHYSICAL_LOCATION            *Location;\r
-  UINT32                               PackageIndex;\r
-  UINT32                               CoreIndex;\r
-  UINTN                                Pages;\r
-  UINT32                               FirstPackage;\r
-  UINT32                               *FirstCore;\r
-  UINT32                               *FirstThread;\r
-  ACPI_CPU_DATA                        *AcpiCpuData;\r
-  CPU_STATUS_INFORMATION               *CpuStatus;\r
-  UINT32                               *ThreadCountPerPackage;\r
-  UINT8                                *ThreadCountPerCore;\r
-  UINTN                                NumberOfCpus;\r
-  UINTN                                NumberOfEnabledProcessors;\r
+  EFI_STATUS                 Status;\r
+  UINTN                      ProcessorNumber;\r
+  EFI_PROCESSOR_INFORMATION  ProcessorInfoBuffer;\r
+  CPU_FEATURES_ENTRY         *CpuFeature;\r
+  CPU_FEATURES_INIT_ORDER    *InitOrder;\r
+  CPU_FEATURES_DATA          *CpuFeaturesData;\r
+  LIST_ENTRY                 *Entry;\r
+  UINT32                     Core;\r
+  UINT32                     Package;\r
+  UINT32                     Thread;\r
+  EFI_CPU_PHYSICAL_LOCATION  *Location;\r
+  UINT32                     PackageIndex;\r
+  UINT32                     CoreIndex;\r
+  UINTN                      Pages;\r
+  UINT32                     FirstPackage;\r
+  UINT32                     *FirstCore;\r
+  UINT32                     *FirstThread;\r
+  ACPI_CPU_DATA              *AcpiCpuData;\r
+  CPU_STATUS_INFORMATION     *CpuStatus;\r
+  UINT32                     *ThreadCountPerPackage;\r
+  UINT8                      *ThreadCountPerCore;\r
+  UINTN                      NumberOfCpus;\r
+  UINTN                      NumberOfEnabledProcessors;\r
 \r
   Core    = 0;\r
   Package = 0;\r
@@ -143,23 +143,24 @@ CpuInitDataInitialize (
     if (CpuFeature->GetConfigDataFunc != NULL) {\r
       CpuFeature->ConfigData = CpuFeature->GetConfigDataFunc (NumberOfCpus);\r
     }\r
+\r
     Entry = Entry->ForwardLink;\r
   }\r
 \r
-  CpuFeaturesData->NumberOfCpus = (UINT32) NumberOfCpus;\r
+  CpuFeaturesData->NumberOfCpus = (UINT32)NumberOfCpus;\r
 \r
   AcpiCpuData = GetAcpiCpuData ();\r
   ASSERT (AcpiCpuData != NULL);\r
-  CpuFeaturesData->AcpiCpuData= AcpiCpuData;\r
+  CpuFeaturesData->AcpiCpuData = AcpiCpuData;\r
 \r
   CpuStatus = &AcpiCpuData->CpuFeatureInitData.CpuStatus;\r
-  Location = AllocatePages (EFI_SIZE_TO_PAGES (sizeof (EFI_CPU_PHYSICAL_LOCATION) * NumberOfCpus));\r
+  Location  = AllocatePages (EFI_SIZE_TO_PAGES (sizeof (EFI_CPU_PHYSICAL_LOCATION) * NumberOfCpus));\r
   ASSERT (Location != NULL);\r
   ZeroMem (Location, sizeof (EFI_CPU_PHYSICAL_LOCATION) * NumberOfCpus);\r
   AcpiCpuData->CpuFeatureInitData.ApLocation = (EFI_PHYSICAL_ADDRESS)(UINTN)Location;\r
 \r
   for (ProcessorNumber = 0; ProcessorNumber < NumberOfCpus; ProcessorNumber++) {\r
-    InitOrder = &CpuFeaturesData->InitOrder[ProcessorNumber];\r
+    InitOrder                        = &CpuFeaturesData->InitOrder[ProcessorNumber];\r
     InitOrder->FeaturesSupportedMask = AllocateZeroPool (CpuFeaturesData->BitMaskSize);\r
     ASSERT (InitOrder->FeaturesSupportedMask != NULL);\r
     InitializeListHead (&InitOrder->OrderList);\r
@@ -182,12 +183,14 @@ CpuInitDataInitialize (
     if (Package < ProcessorInfoBuffer.Location.Package) {\r
       Package = ProcessorInfoBuffer.Location.Package;\r
     }\r
+\r
     //\r
     // Collect CPU max core count info.\r
     //\r
     if (Core < ProcessorInfoBuffer.Location.Core) {\r
       Core = ProcessorInfoBuffer.Location.Core;\r
     }\r
+\r
     //\r
     // Collect CPU max thread count info.\r
     //\r
@@ -195,13 +198,17 @@ CpuInitDataInitialize (
       Thread = ProcessorInfoBuffer.Location.Thread;\r
     }\r
   }\r
-  CpuStatus->PackageCount    = Package + 1;\r
-  CpuStatus->MaxCoreCount    = Core + 1;\r
-  CpuStatus->MaxThreadCount  = Thread + 1;\r
-  DEBUG ((DEBUG_INFO, "Processor Info: Package: %d, MaxCore : %d, MaxThread: %d\n",\r
-         CpuStatus->PackageCount,\r
-         CpuStatus->MaxCoreCount,\r
-         CpuStatus->MaxThreadCount));\r
+\r
+  CpuStatus->PackageCount   = Package + 1;\r
+  CpuStatus->MaxCoreCount   = Core + 1;\r
+  CpuStatus->MaxThreadCount = Thread + 1;\r
+  DEBUG ((\r
+    DEBUG_INFO,\r
+    "Processor Info: Package: %d, MaxCore : %d, MaxThread: %d\n",\r
+    CpuStatus->PackageCount,\r
+    CpuStatus->MaxCoreCount,\r
+    CpuStatus->MaxThreadCount\r
+    ));\r
 \r
   //\r
   // Collect valid core count in each package because not all cores are valid.\r
@@ -228,7 +235,10 @@ CpuInitDataInitialize (
       for (CoreIndex = 0; CoreIndex < CpuStatus->MaxCoreCount; CoreIndex++) {\r
         if (ThreadCountPerCore[PackageIndex * CpuStatus->MaxCoreCount + CoreIndex] != 0) {\r
           DEBUG ((\r
-            DEBUG_INFO, "  P%02d C%04d, Thread Count = %d\n", PackageIndex, CoreIndex,\r
+            DEBUG_INFO,\r
+            "  P%02d C%04d, Thread Count = %d\n",\r
+            PackageIndex,\r
+            CoreIndex,\r
             ThreadCountPerCore[PackageIndex * CpuStatus->MaxCoreCount + CoreIndex]\r
             ));\r
         }\r
@@ -248,13 +258,13 @@ CpuInitDataInitialize (
   Pages     = EFI_SIZE_TO_PAGES (CpuStatus->PackageCount * sizeof (UINT32) + CpuStatus->PackageCount * CpuStatus->MaxCoreCount * sizeof (UINT32));\r
   FirstCore = AllocatePages (Pages);\r
   ASSERT (FirstCore != NULL);\r
-  FirstThread  = FirstCore + CpuStatus->PackageCount;\r
+  FirstThread = FirstCore + CpuStatus->PackageCount;\r
 \r
   //\r
   // Set FirstPackage, FirstCore[], FirstThread[] to maximum package ID, core ID, thread ID.\r
   //\r
   FirstPackage = MAX_UINT32;\r
-  SetMem32 (FirstCore,   CpuStatus->PackageCount * sizeof (UINT32), MAX_UINT32);\r
+  SetMem32 (FirstCore, CpuStatus->PackageCount * sizeof (UINT32), MAX_UINT32);\r
   SetMem32 (FirstThread, CpuStatus->PackageCount * CpuStatus->MaxCoreCount * sizeof (UINT32), MAX_UINT32);\r
 \r
   for (ProcessorNumber = 0; ProcessorNumber < NumberOfCpus; ProcessorNumber++) {\r
@@ -263,7 +273,7 @@ CpuInitDataInitialize (
     //\r
     // Save the minimum package ID in the platform.\r
     //\r
-    FirstPackage                 = MIN (Location->Package, FirstPackage);\r
+    FirstPackage = MIN (Location->Package, FirstPackage);\r
 \r
     //\r
     // Save the minimum core ID per package.\r
@@ -274,9 +284,9 @@ CpuInitDataInitialize (
     // Save the minimum thread ID per core.\r
     //\r
     FirstThread[Location->Package * CpuStatus->MaxCoreCount + Location->Core] = MIN (\r
-      Location->Thread,\r
-      FirstThread[Location->Package * CpuStatus->MaxCoreCount + Location->Core]\r
-    );\r
+                                                                                  Location->Thread,\r
+                                                                                  FirstThread[Location->Package * CpuStatus->MaxCoreCount + Location->Core]\r
+                                                                                  );\r
   }\r
 \r
   //\r
@@ -293,13 +303,14 @@ CpuInitDataInitialize (
     // Set First.Die/Tile/Module for each thread assuming:\r
     //  single Die under each package, single Tile under each Die, single Module under each Tile\r
     //\r
-    CpuFeaturesData->InitOrder[ProcessorNumber].CpuInfo.First.Die = 1;\r
-    CpuFeaturesData->InitOrder[ProcessorNumber].CpuInfo.First.Tile = 1;\r
+    CpuFeaturesData->InitOrder[ProcessorNumber].CpuInfo.First.Die    = 1;\r
+    CpuFeaturesData->InitOrder[ProcessorNumber].CpuInfo.First.Tile   = 1;\r
     CpuFeaturesData->InitOrder[ProcessorNumber].CpuInfo.First.Module = 1;\r
 \r
     if (Location->Core == FirstCore[Location->Package]) {\r
       CpuFeaturesData->InitOrder[ProcessorNumber].CpuInfo.First.Core = 1;\r
     }\r
+\r
     if (Location->Thread == FirstThread[Location->Package * CpuStatus->MaxCoreCount + Location->Core]) {\r
       CpuFeaturesData->InitOrder[ProcessorNumber].CpuInfo.First.Thread = 1;\r
     }\r
@@ -318,14 +329,14 @@ CpuInitDataInitialize (
 **/\r
 VOID\r
 SupportedMaskOr (\r
-  IN UINT8               *SupportedFeatureMask,\r
-  IN UINT8               *OrFeatureBitMask,\r
-  IN UINT32              BitMaskSize\r
+  IN UINT8   *SupportedFeatureMask,\r
+  IN UINT8   *OrFeatureBitMask,\r
+  IN UINT32  BitMaskSize\r
   )\r
 {\r
-  UINTN                  Index;\r
-  UINT8                  *Data1;\r
-  UINT8                  *Data2;\r
+  UINTN  Index;\r
+  UINT8  *Data1;\r
+  UINT8  *Data2;\r
 \r
   Data1 = SupportedFeatureMask;\r
   Data2 = OrFeatureBitMask;\r
@@ -344,14 +355,14 @@ SupportedMaskOr (
 **/\r
 VOID\r
 SupportedMaskAnd (\r
-  IN       UINT8               *SupportedFeatureMask,\r
-  IN CONST UINT8               *AndFeatureBitMask,\r
-  IN       UINT32              BitMaskSize\r
+  IN       UINT8   *SupportedFeatureMask,\r
+  IN CONST UINT8   *AndFeatureBitMask,\r
+  IN       UINT32  BitMaskSize\r
   )\r
 {\r
-  UINTN                  Index;\r
-  UINT8                  *Data1;\r
-  CONST UINT8            *Data2;\r
+  UINTN        Index;\r
+  UINT8        *Data1;\r
+  CONST UINT8  *Data2;\r
 \r
   Data1 = SupportedFeatureMask;\r
   Data2 = AndFeatureBitMask;\r
@@ -369,14 +380,14 @@ SupportedMaskAnd (
 **/\r
 VOID\r
 SupportedMaskCleanBit (\r
-  IN UINT8               *SupportedFeatureMask,\r
-  IN UINT8               *AndFeatureBitMask,\r
-  IN UINT32              BitMaskSize\r
+  IN UINT8   *SupportedFeatureMask,\r
+  IN UINT8   *AndFeatureBitMask,\r
+  IN UINT32  BitMaskSize\r
   )\r
 {\r
-  UINTN                  Index;\r
-  UINT8                  *Data1;\r
-  UINT8                  *Data2;\r
+  UINTN  Index;\r
+  UINT8  *Data1;\r
+  UINT8  *Data2;\r
 \r
   Data1 = SupportedFeatureMask;\r
   Data2 = AndFeatureBitMask;\r
@@ -400,14 +411,14 @@ SupportedMaskCleanBit (
 **/\r
 BOOLEAN\r
 IsBitMaskMatch (\r
-  IN UINT8               *SupportedFeatureMask,\r
-  IN UINT8               *ComparedFeatureBitMask,\r
-  IN UINT32              BitMaskSize\r
+  IN UINT8   *SupportedFeatureMask,\r
+  IN UINT8   *ComparedFeatureBitMask,\r
+  IN UINT32  BitMaskSize\r
   )\r
 {\r
-  UINTN                  Index;\r
-  UINT8                  *Data1;\r
-  UINT8                  *Data2;\r
+  UINTN  Index;\r
+  UINT8  *Data1;\r
+  UINT8  *Data2;\r
 \r
   Data1 = SupportedFeatureMask;\r
   Data2 = ComparedFeatureBitMask;\r
@@ -416,6 +427,7 @@ IsBitMaskMatch (
       return TRUE;\r
     }\r
   }\r
+\r
   return FALSE;\r
 }\r
 \r
@@ -427,18 +439,18 @@ IsBitMaskMatch (
 VOID\r
 EFIAPI\r
 CollectProcessorData (\r
-  IN OUT VOID                          *Buffer\r
+  IN OUT VOID  *Buffer\r
   )\r
 {\r
-  UINTN                                ProcessorNumber;\r
-  CPU_FEATURES_ENTRY                   *CpuFeature;\r
-  REGISTER_CPU_FEATURE_INFORMATION     *CpuInfo;\r
-  LIST_ENTRY                           *Entry;\r
-  CPU_FEATURES_DATA                    *CpuFeaturesData;\r
+  UINTN                             ProcessorNumber;\r
+  CPU_FEATURES_ENTRY                *CpuFeature;\r
+  REGISTER_CPU_FEATURE_INFORMATION  *CpuInfo;\r
+  LIST_ENTRY                        *Entry;\r
+  CPU_FEATURES_DATA                 *CpuFeaturesData;\r
 \r
   CpuFeaturesData = (CPU_FEATURES_DATA *)Buffer;\r
   ProcessorNumber = GetProcessorIndex (CpuFeaturesData);\r
-  CpuInfo = &CpuFeaturesData->InitOrder[ProcessorNumber].CpuInfo;\r
+  CpuInfo         = &CpuFeaturesData->InitOrder[ProcessorNumber].CpuInfo;\r
   //\r
   // collect processor information\r
   //\r
@@ -462,6 +474,7 @@ CollectProcessorData (
         CpuFeaturesData->BitMaskSize\r
         );\r
     }\r
+\r
     Entry = Entry->ForwardLink;\r
   }\r
 }\r
@@ -475,15 +488,15 @@ CollectProcessorData (
 **/\r
 VOID\r
 DumpRegisterTableOnProcessor (\r
-  IN UINTN                             ProcessorNumber\r
+  IN UINTN  ProcessorNumber\r
   )\r
 {\r
-  CPU_FEATURES_DATA                    *CpuFeaturesData;\r
-  UINTN                                FeatureIndex;\r
-  CPU_REGISTER_TABLE                   *RegisterTable;\r
-  CPU_REGISTER_TABLE_ENTRY             *RegisterTableEntry;\r
-  CPU_REGISTER_TABLE_ENTRY             *RegisterTableEntryHead;\r
-  UINT32                               DebugPrintErrorLevel;\r
+  CPU_FEATURES_DATA         *CpuFeaturesData;\r
+  UINTN                     FeatureIndex;\r
+  CPU_REGISTER_TABLE        *RegisterTable;\r
+  CPU_REGISTER_TABLE_ENTRY  *RegisterTableEntry;\r
+  CPU_REGISTER_TABLE_ENTRY  *RegisterTableEntryHead;\r
+  UINT32                    DebugPrintErrorLevel;\r
 \r
   DebugPrintErrorLevel = (ProcessorNumber == 0) ? DEBUG_INFO : DEBUG_VERBOSE;\r
   CpuFeaturesData      = GetCpuFeaturesData ();\r
@@ -493,71 +506,71 @@ DumpRegisterTableOnProcessor (
   RegisterTable = &CpuFeaturesData->RegisterTable[ProcessorNumber];\r
   DEBUG ((DebugPrintErrorLevel, "RegisterTable->TableLength = %d\n", RegisterTable->TableLength));\r
 \r
-  RegisterTableEntryHead = (CPU_REGISTER_TABLE_ENTRY *) (UINTN) RegisterTable->RegisterTableEntry;\r
+  RegisterTableEntryHead = (CPU_REGISTER_TABLE_ENTRY *)(UINTN)RegisterTable->RegisterTableEntry;\r
 \r
   for (FeatureIndex = 0; FeatureIndex < RegisterTable->TableLength; FeatureIndex++) {\r
     RegisterTableEntry = &RegisterTableEntryHead[FeatureIndex];\r
     switch (RegisterTableEntry->RegisterType) {\r
-    case Msr:\r
-      DEBUG ((\r
-        DebugPrintErrorLevel,\r
-        "Processor: %04d: Index %04d, MSR  : %08x, Bit Start: %02d, Bit Length: %02d, Value: %016lx\r\n",\r
-        (UINT32) ProcessorNumber,\r
-        (UINT32) FeatureIndex,\r
-        RegisterTableEntry->Index,\r
-        RegisterTableEntry->ValidBitStart,\r
-        RegisterTableEntry->ValidBitLength,\r
-        RegisterTableEntry->Value\r
-        ));\r
-      break;\r
-    case ControlRegister:\r
-      DEBUG ((\r
-        DebugPrintErrorLevel,\r
-        "Processor: %04d: Index %04d, CR   : %08x, Bit Start: %02d, Bit Length: %02d, Value: %016lx\r\n",\r
-        (UINT32) ProcessorNumber,\r
-        (UINT32) FeatureIndex,\r
-        RegisterTableEntry->Index,\r
-        RegisterTableEntry->ValidBitStart,\r
-        RegisterTableEntry->ValidBitLength,\r
-        RegisterTableEntry->Value\r
-        ));\r
-      break;\r
-    case MemoryMapped:\r
-      DEBUG ((\r
-        DebugPrintErrorLevel,\r
-        "Processor: %04d: Index %04d, MMIO : %016lx, Bit Start: %02d, Bit Length: %02d, Value: %016lx\r\n",\r
-        (UINT32) ProcessorNumber,\r
-        (UINT32) FeatureIndex,\r
-        RegisterTableEntry->Index | LShiftU64 (RegisterTableEntry->HighIndex, 32),\r
-        RegisterTableEntry->ValidBitStart,\r
-        RegisterTableEntry->ValidBitLength,\r
-        RegisterTableEntry->Value\r
-        ));\r
-      break;\r
-    case CacheControl:\r
-      DEBUG ((\r
-        DebugPrintErrorLevel,\r
-        "Processor: %04d: Index %04d, CACHE: %08x, Bit Start: %02d, Bit Length: %02d, Value: %016lx\r\n",\r
-        (UINT32) ProcessorNumber,\r
-        (UINT32) FeatureIndex,\r
-        RegisterTableEntry->Index,\r
-        RegisterTableEntry->ValidBitStart,\r
-        RegisterTableEntry->ValidBitLength,\r
-        RegisterTableEntry->Value\r
-        ));\r
-      break;\r
-    case Semaphore:\r
-      DEBUG ((\r
-        DebugPrintErrorLevel,\r
-        "Processor: %04d: Index %04d, SEMAP: %s\r\n",\r
-        (UINT32) ProcessorNumber,\r
-        (UINT32) FeatureIndex,\r
-        mDependTypeStr[MIN ((UINT32)RegisterTableEntry->Value, InvalidDepType)]\r
-        ));\r
-      break;\r
+      case Msr:\r
+        DEBUG ((\r
+          DebugPrintErrorLevel,\r
+          "Processor: %04d: Index %04d, MSR  : %08x, Bit Start: %02d, Bit Length: %02d, Value: %016lx\r\n",\r
+          (UINT32)ProcessorNumber,\r
+          (UINT32)FeatureIndex,\r
+          RegisterTableEntry->Index,\r
+          RegisterTableEntry->ValidBitStart,\r
+          RegisterTableEntry->ValidBitLength,\r
+          RegisterTableEntry->Value\r
+          ));\r
+        break;\r
+      case ControlRegister:\r
+        DEBUG ((\r
+          DebugPrintErrorLevel,\r
+          "Processor: %04d: Index %04d, CR   : %08x, Bit Start: %02d, Bit Length: %02d, Value: %016lx\r\n",\r
+          (UINT32)ProcessorNumber,\r
+          (UINT32)FeatureIndex,\r
+          RegisterTableEntry->Index,\r
+          RegisterTableEntry->ValidBitStart,\r
+          RegisterTableEntry->ValidBitLength,\r
+          RegisterTableEntry->Value\r
+          ));\r
+        break;\r
+      case MemoryMapped:\r
+        DEBUG ((\r
+          DebugPrintErrorLevel,\r
+          "Processor: %04d: Index %04d, MMIO : %016lx, Bit Start: %02d, Bit Length: %02d, Value: %016lx\r\n",\r
+          (UINT32)ProcessorNumber,\r
+          (UINT32)FeatureIndex,\r
+          RegisterTableEntry->Index | LShiftU64 (RegisterTableEntry->HighIndex, 32),\r
+          RegisterTableEntry->ValidBitStart,\r
+          RegisterTableEntry->ValidBitLength,\r
+          RegisterTableEntry->Value\r
+          ));\r
+        break;\r
+      case CacheControl:\r
+        DEBUG ((\r
+          DebugPrintErrorLevel,\r
+          "Processor: %04d: Index %04d, CACHE: %08x, Bit Start: %02d, Bit Length: %02d, Value: %016lx\r\n",\r
+          (UINT32)ProcessorNumber,\r
+          (UINT32)FeatureIndex,\r
+          RegisterTableEntry->Index,\r
+          RegisterTableEntry->ValidBitStart,\r
+          RegisterTableEntry->ValidBitLength,\r
+          RegisterTableEntry->Value\r
+          ));\r
+        break;\r
+      case Semaphore:\r
+        DEBUG ((\r
+          DebugPrintErrorLevel,\r
+          "Processor: %04d: Index %04d, SEMAP: %s\r\n",\r
+          (UINT32)ProcessorNumber,\r
+          (UINT32)FeatureIndex,\r
+          mDependTypeStr[MIN ((UINT32)RegisterTableEntry->Value, InvalidDepType)]\r
+          ));\r
+        break;\r
 \r
-    default:\r
-      break;\r
+      default:\r
+        break;\r
     }\r
   }\r
 }\r
@@ -581,11 +594,11 @@ BiggestDep (
   IN CPU_FEATURE_DEPENDENCE_TYPE  NoneNeibAfterDep\r
   )\r
 {\r
-  CPU_FEATURE_DEPENDENCE_TYPE Bigger;\r
+  CPU_FEATURE_DEPENDENCE_TYPE  Bigger;\r
 \r
   Bigger = MAX (BeforeDep, AfterDep);\r
   Bigger = MAX (Bigger, NoneNeibBeforeDep);\r
-  return MAX(Bigger, NoneNeibAfterDep);\r
+  return MAX (Bigger, NoneNeibAfterDep);\r
 }\r
 \r
 /**\r
@@ -596,26 +609,26 @@ BiggestDep (
 **/\r
 VOID\r
 AnalysisProcessorFeatures (\r
-  IN UINTN                             NumberOfCpus\r
+  IN UINTN  NumberOfCpus\r
   )\r
 {\r
-  EFI_STATUS                           Status;\r
-  UINTN                                ProcessorNumber;\r
-  CPU_FEATURES_ENTRY                   *CpuFeature;\r
-  CPU_FEATURES_ENTRY                   *CpuFeatureInOrder;\r
-  CPU_FEATURES_INIT_ORDER              *CpuInitOrder;\r
-  REGISTER_CPU_FEATURE_INFORMATION     *CpuInfo;\r
-  LIST_ENTRY                           *Entry;\r
-  CPU_FEATURES_DATA                    *CpuFeaturesData;\r
-  LIST_ENTRY                           *NextEntry;\r
-  CPU_FEATURES_ENTRY                   *NextCpuFeatureInOrder;\r
-  BOOLEAN                              Success;\r
-  CPU_FEATURE_DEPENDENCE_TYPE          BeforeDep;\r
-  CPU_FEATURE_DEPENDENCE_TYPE          AfterDep;\r
-  CPU_FEATURE_DEPENDENCE_TYPE          NoneNeibBeforeDep;\r
-  CPU_FEATURE_DEPENDENCE_TYPE          NoneNeibAfterDep;\r
-\r
-  CpuFeaturesData = GetCpuFeaturesData ();\r
+  EFI_STATUS                        Status;\r
+  UINTN                             ProcessorNumber;\r
+  CPU_FEATURES_ENTRY                *CpuFeature;\r
+  CPU_FEATURES_ENTRY                *CpuFeatureInOrder;\r
+  CPU_FEATURES_INIT_ORDER           *CpuInitOrder;\r
+  REGISTER_CPU_FEATURE_INFORMATION  *CpuInfo;\r
+  LIST_ENTRY                        *Entry;\r
+  CPU_FEATURES_DATA                 *CpuFeaturesData;\r
+  LIST_ENTRY                        *NextEntry;\r
+  CPU_FEATURES_ENTRY                *NextCpuFeatureInOrder;\r
+  BOOLEAN                           Success;\r
+  CPU_FEATURE_DEPENDENCE_TYPE       BeforeDep;\r
+  CPU_FEATURE_DEPENDENCE_TYPE       AfterDep;\r
+  CPU_FEATURE_DEPENDENCE_TYPE       NoneNeibBeforeDep;\r
+  CPU_FEATURE_DEPENDENCE_TYPE       NoneNeibAfterDep;\r
+\r
+  CpuFeaturesData                = GetCpuFeaturesData ();\r
   CpuFeaturesData->CapabilityPcd = AllocatePool (CpuFeaturesData->BitMaskSize);\r
   ASSERT (CpuFeaturesData->CapabilityPcd != NULL);\r
   SetMem (CpuFeaturesData->CapabilityPcd, CpuFeaturesData->BitMaskSize, 0xFF);\r
@@ -626,6 +639,7 @@ AnalysisProcessorFeatures (
     //\r
     SupportedMaskAnd (CpuFeaturesData->CapabilityPcd, CpuInitOrder->FeaturesSupportedMask, CpuFeaturesData->BitMaskSize);\r
   }\r
+\r
   //\r
   // Calculate the last setting\r
   //\r
@@ -637,28 +651,30 @@ AnalysisProcessorFeatures (
   // Dump the last CPU feature list\r
   //\r
   DEBUG_CODE_BEGIN ();\r
-    DEBUG ((DEBUG_INFO, "Last CPU features list...\n"));\r
-    Entry = GetFirstNode (&CpuFeaturesData->FeatureList);\r
-    while (!IsNull (&CpuFeaturesData->FeatureList, Entry)) {\r
-      CpuFeature = CPU_FEATURE_ENTRY_FROM_LINK (Entry);\r
-      if (IsBitMaskMatch (CpuFeature->FeatureMask, CpuFeaturesData->CapabilityPcd, CpuFeaturesData->BitMaskSize)) {\r
-        if (IsBitMaskMatch (CpuFeature->FeatureMask, CpuFeaturesData->SettingPcd, CpuFeaturesData->BitMaskSize)) {\r
-          DEBUG ((DEBUG_INFO, "[Enable   ] "));\r
-        } else {\r
-          DEBUG ((DEBUG_INFO, "[Disable  ] "));\r
-        }\r
+  DEBUG ((DEBUG_INFO, "Last CPU features list...\n"));\r
+  Entry = GetFirstNode (&CpuFeaturesData->FeatureList);\r
+  while (!IsNull (&CpuFeaturesData->FeatureList, Entry)) {\r
+    CpuFeature = CPU_FEATURE_ENTRY_FROM_LINK (Entry);\r
+    if (IsBitMaskMatch (CpuFeature->FeatureMask, CpuFeaturesData->CapabilityPcd, CpuFeaturesData->BitMaskSize)) {\r
+      if (IsBitMaskMatch (CpuFeature->FeatureMask, CpuFeaturesData->SettingPcd, CpuFeaturesData->BitMaskSize)) {\r
+        DEBUG ((DEBUG_INFO, "[Enable   ] "));\r
       } else {\r
-        DEBUG ((DEBUG_INFO, "[Unsupport] "));\r
+        DEBUG ((DEBUG_INFO, "[Disable  ] "));\r
       }\r
-      DumpCpuFeature (CpuFeature, CpuFeaturesData->BitMaskSize);\r
-      Entry = Entry->ForwardLink;\r
+    } else {\r
+      DEBUG ((DEBUG_INFO, "[Unsupport] "));\r
     }\r
-    DEBUG ((DEBUG_INFO, "PcdCpuFeaturesCapability:\n"));\r
-    DumpCpuFeatureMask (CpuFeaturesData->CapabilityPcd, CpuFeaturesData->BitMaskSize);\r
-    DEBUG ((DEBUG_INFO, "Origin PcdCpuFeaturesSetting:\n"));\r
-    DumpCpuFeatureMask (PcdGetPtr (PcdCpuFeaturesSetting), CpuFeaturesData->BitMaskSize);\r
-    DEBUG ((DEBUG_INFO, "Final PcdCpuFeaturesSetting:\n"));\r
-    DumpCpuFeatureMask (CpuFeaturesData->SettingPcd, CpuFeaturesData->BitMaskSize);\r
+\r
+    DumpCpuFeature (CpuFeature, CpuFeaturesData->BitMaskSize);\r
+    Entry = Entry->ForwardLink;\r
+  }\r
+\r
+  DEBUG ((DEBUG_INFO, "PcdCpuFeaturesCapability:\n"));\r
+  DumpCpuFeatureMask (CpuFeaturesData->CapabilityPcd, CpuFeaturesData->BitMaskSize);\r
+  DEBUG ((DEBUG_INFO, "Origin PcdCpuFeaturesSetting:\n"));\r
+  DumpCpuFeatureMask (PcdGetPtr (PcdCpuFeaturesSetting), CpuFeaturesData->BitMaskSize);\r
+  DEBUG ((DEBUG_INFO, "Final PcdCpuFeaturesSetting:\n"));\r
+  DumpCpuFeatureMask (CpuFeaturesData->SettingPcd, CpuFeaturesData->BitMaskSize);\r
   DEBUG_CODE_END ();\r
 \r
   //\r
@@ -669,7 +685,7 @@ AnalysisProcessorFeatures (
 \r
   for (ProcessorNumber = 0; ProcessorNumber < NumberOfCpus; ProcessorNumber++) {\r
     CpuInitOrder = &CpuFeaturesData->InitOrder[ProcessorNumber];\r
-    Entry = GetFirstNode (&CpuFeaturesData->FeatureList);\r
+    Entry        = GetFirstNode (&CpuFeaturesData->FeatureList);\r
     while (!IsNull (&CpuFeaturesData->FeatureList, Entry)) {\r
       //\r
       // Insert each feature into processor's order list\r
@@ -680,13 +696,15 @@ AnalysisProcessorFeatures (
         ASSERT (CpuFeatureInOrder != NULL);\r
         InsertTailList (&CpuInitOrder->OrderList, &CpuFeatureInOrder->Link);\r
       }\r
+\r
       Entry = Entry->ForwardLink;\r
     }\r
+\r
     //\r
     // Go through ordered feature list to initialize CPU features\r
     //\r
     CpuInfo = &CpuFeaturesData->InitOrder[ProcessorNumber].CpuInfo;\r
-    Entry = GetFirstNode (&CpuInitOrder->OrderList);\r
+    Entry   = GetFirstNode (&CpuInitOrder->OrderList);\r
     while (!IsNull (&CpuInitOrder->OrderList, Entry)) {\r
       CpuFeatureInOrder = CPU_FEATURE_ENTRY_FROM_LINK (Entry);\r
 \r
@@ -736,23 +754,24 @@ AnalysisProcessorFeatures (
           // Check whether next feature has After type dependence with not neighborhood CPU\r
           // Features in former CPU features.\r
           //\r
-          NoneNeibAfterDep = DetectNoneNeighborhoodFeatureScope(NextCpuFeatureInOrder, FALSE, &CpuInitOrder->OrderList);\r
+          NoneNeibAfterDep = DetectNoneNeighborhoodFeatureScope (NextCpuFeatureInOrder, FALSE, &CpuInitOrder->OrderList);\r
         } else {\r
           BeforeDep        = NoneDepType;\r
           AfterDep         = NoneDepType;\r
           NoneNeibAfterDep = NoneDepType;\r
         }\r
+\r
         //\r
         // Check whether current feature has Before type dependence with none neighborhood\r
         // CPU features in after Cpu features.\r
         //\r
-        NoneNeibBeforeDep = DetectNoneNeighborhoodFeatureScope(CpuFeatureInOrder, TRUE, &CpuInitOrder->OrderList);\r
+        NoneNeibBeforeDep = DetectNoneNeighborhoodFeatureScope (CpuFeatureInOrder, TRUE, &CpuInitOrder->OrderList);\r
 \r
         //\r
         // Get the biggest dependence and add semaphore for it.\r
         // PackageDepType > CoreDepType > ThreadDepType > NoneDepType.\r
         //\r
-        BeforeDep = BiggestDep(BeforeDep, AfterDep, NoneNeibBeforeDep, NoneNeibAfterDep);\r
+        BeforeDep = BiggestDep (BeforeDep, AfterDep, NoneNeibBeforeDep, NoneNeibAfterDep);\r
         if (BeforeDep > ThreadDepType) {\r
           CPU_REGISTER_TABLE_WRITE32 (ProcessorNumber, Semaphore, 0, BeforeDep);\r
         }\r
@@ -783,7 +802,7 @@ AnalysisProcessorFeatures (
 **/\r
 VOID\r
 LibReleaseSemaphore (\r
-  IN OUT  volatile UINT32           *Sem\r
+  IN OUT  volatile UINT32  *Sem\r
   )\r
 {\r
   InterlockedIncrement (Sem);\r
@@ -801,7 +820,7 @@ LibReleaseSemaphore (
 **/\r
 VOID\r
 LibWaitForSemaphore (\r
-  IN OUT  volatile UINT32           *Sem\r
+  IN OUT  volatile UINT32  *Sem\r
   )\r
 {\r
   UINT32  Value;\r
@@ -827,42 +846,46 @@ LibWaitForSemaphore (
 **/\r
 UINTN\r
 ReadWriteCr (\r
-  IN     UINT32       CrIndex,\r
-  IN     BOOLEAN      Read,\r
-  IN OUT UINTN        *CrValue\r
+  IN     UINT32   CrIndex,\r
+  IN     BOOLEAN  Read,\r
+  IN OUT UINTN    *CrValue\r
   )\r
 {\r
   switch (CrIndex) {\r
-  case 0:\r
-    if (Read) {\r
-      *CrValue = AsmReadCr0 ();\r
-    } else {\r
-      AsmWriteCr0 (*CrValue);\r
-    }\r
-    break;\r
-  case 2:\r
-    if (Read) {\r
-      *CrValue = AsmReadCr2 ();\r
-    } else {\r
-      AsmWriteCr2 (*CrValue);\r
-    }\r
-    break;\r
-  case 3:\r
-    if (Read) {\r
-      *CrValue = AsmReadCr3 ();\r
-    } else {\r
-      AsmWriteCr3 (*CrValue);\r
-    }\r
-    break;\r
-  case 4:\r
-    if (Read) {\r
-      *CrValue = AsmReadCr4 ();\r
-    } else {\r
-      AsmWriteCr4 (*CrValue);\r
-    }\r
-    break;\r
-  default:\r
-    return EFI_UNSUPPORTED;;\r
+    case 0:\r
+      if (Read) {\r
+        *CrValue = AsmReadCr0 ();\r
+      } else {\r
+        AsmWriteCr0 (*CrValue);\r
+      }\r
+\r
+      break;\r
+    case 2:\r
+      if (Read) {\r
+        *CrValue = AsmReadCr2 ();\r
+      } else {\r
+        AsmWriteCr2 (*CrValue);\r
+      }\r
+\r
+      break;\r
+    case 3:\r
+      if (Read) {\r
+        *CrValue = AsmReadCr3 ();\r
+      } else {\r
+        AsmWriteCr3 (*CrValue);\r
+      }\r
+\r
+      break;\r
+    case 4:\r
+      if (Read) {\r
+        *CrValue = AsmReadCr4 ();\r
+      } else {\r
+        AsmWriteCr4 (*CrValue);\r
+      }\r
+\r
+      break;\r
+    default:\r
+      return EFI_UNSUPPORTED;\r
   }\r
 \r
   return EFI_SUCCESS;\r
@@ -880,10 +903,10 @@ ReadWriteCr (
 **/\r
 VOID\r
 ProgramProcessorRegister (\r
-  IN CPU_REGISTER_TABLE           *RegisterTable,\r
-  IN EFI_CPU_PHYSICAL_LOCATION    *ApLocation,\r
-  IN CPU_STATUS_INFORMATION       *CpuStatus,\r
-  IN PROGRAM_CPU_REGISTER_FLAGS   *CpuFlags\r
+  IN CPU_REGISTER_TABLE          *RegisterTable,\r
+  IN EFI_CPU_PHYSICAL_LOCATION   *ApLocation,\r
+  IN CPU_STATUS_INFORMATION      *CpuStatus,\r
+  IN PROGRAM_CPU_REGISTER_FLAGS  *CpuFlags\r
   )\r
 {\r
   CPU_REGISTER_TABLE_ENTRY  *RegisterTableEntry;\r
@@ -903,54 +926,25 @@ ProgramProcessorRegister (
   //\r
   // Traverse Register Table of this logical processor\r
   //\r
-  RegisterTableEntryHead = (CPU_REGISTER_TABLE_ENTRY *) (UINTN) RegisterTable->RegisterTableEntry;\r
+  RegisterTableEntryHead = (CPU_REGISTER_TABLE_ENTRY *)(UINTN)RegisterTable->RegisterTableEntry;\r
 \r
   for (Index = 0; Index < RegisterTable->TableLength; Index++) {\r
-\r
     RegisterTableEntry = &RegisterTableEntryHead[Index];\r
 \r
     //\r
     // Check the type of specified register\r
     //\r
     switch (RegisterTableEntry->RegisterType) {\r
-    //\r
-    // The specified register is Control Register\r
-    //\r
-    case ControlRegister:\r
-      Status = ReadWriteCr (RegisterTableEntry->Index, TRUE, &Value);\r
-      if (EFI_ERROR (Status)) {\r
-        break;\r
-      }\r
-      if (RegisterTableEntry->TestThenWrite) {\r
-        CurrentValue = BitFieldRead64 (\r
-                         Value,\r
-                         RegisterTableEntry->ValidBitStart,\r
-                         RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1\r
-                         );\r
-        if (CurrentValue == RegisterTableEntry->Value) {\r
+      //\r
+      // The specified register is Control Register\r
+      //\r
+      case ControlRegister:\r
+        Status = ReadWriteCr (RegisterTableEntry->Index, TRUE, &Value);\r
+        if (EFI_ERROR (Status)) {\r
           break;\r
         }\r
-      }\r
-      Value = (UINTN) BitFieldWrite64 (\r
-                        Value,\r
-                        RegisterTableEntry->ValidBitStart,\r
-                        RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1,\r
-                        RegisterTableEntry->Value\r
-                        );\r
-      ReadWriteCr (RegisterTableEntry->Index, FALSE, &Value);\r
-      break;\r
 \r
-    //\r
-    // The specified register is Model Specific Register\r
-    //\r
-    case Msr:\r
-      if (RegisterTableEntry->TestThenWrite) {\r
-        Value = (UINTN)AsmReadMsr64 (RegisterTableEntry->Index);\r
-        if (RegisterTableEntry->ValidBitLength >= 64) {\r
-          if (Value == RegisterTableEntry->Value) {\r
-            break;\r
-          }\r
-        } else {\r
+        if (RegisterTableEntry->TestThenWrite) {\r
           CurrentValue = BitFieldRead64 (\r
                            Value,\r
                            RegisterTableEntry->ValidBitStart,\r
@@ -960,153 +954,190 @@ ProgramProcessorRegister (
             break;\r
           }\r
         }\r
-      }\r
 \r
-      if (RegisterTableEntry->ValidBitLength >= 64) {\r
-        //\r
-        // If length is not less than 64 bits, then directly write without reading\r
-        //\r
-        AsmWriteMsr64 (\r
-          RegisterTableEntry->Index,\r
-          RegisterTableEntry->Value\r
-          );\r
-      } else {\r
-        //\r
-        // Set the bit section according to bit start and length\r
-        //\r
-        AsmMsrBitFieldWrite64 (\r
-          RegisterTableEntry->Index,\r
-          RegisterTableEntry->ValidBitStart,\r
-          RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1,\r
-          RegisterTableEntry->Value\r
-          );\r
-      }\r
-      break;\r
-    //\r
-    // MemoryMapped operations\r
-    //\r
-    case MemoryMapped:\r
-      AcquireSpinLock (&CpuFlags->MemoryMappedLock);\r
-      MmioBitFieldWrite32 (\r
-        (UINTN)(RegisterTableEntry->Index | LShiftU64 (RegisterTableEntry->HighIndex, 32)),\r
-        RegisterTableEntry->ValidBitStart,\r
-        RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1,\r
-        (UINT32)RegisterTableEntry->Value\r
-        );\r
-      ReleaseSpinLock (&CpuFlags->MemoryMappedLock);\r
-      break;\r
-    //\r
-    // Enable or disable cache\r
-    //\r
-    case CacheControl:\r
-      //\r
-      // If value of the entry is 0, then disable cache.  Otherwise, enable cache.\r
-      //\r
-      if (RegisterTableEntry->Value == 0) {\r
-        AsmDisableCache ();\r
-      } else {\r
-        AsmEnableCache ();\r
-      }\r
-      break;\r
+        Value = (UINTN)BitFieldWrite64 (\r
+                         Value,\r
+                         RegisterTableEntry->ValidBitStart,\r
+                         RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1,\r
+                         RegisterTableEntry->Value\r
+                         );\r
+        ReadWriteCr (RegisterTableEntry->Index, FALSE, &Value);\r
+        break;\r
 \r
-    case Semaphore:\r
-      // Semaphore works logic like below:\r
       //\r
-      //  V(x) = LibReleaseSemaphore (Semaphore[FirstThread + x]);\r
-      //  P(x) = LibWaitForSemaphore (Semaphore[FirstThread + x]);\r
+      // The specified register is Model Specific Register\r
       //\r
-      //  All threads (T0...Tn) waits in P() line and continues running\r
-      //  together.\r
+      case Msr:\r
+        if (RegisterTableEntry->TestThenWrite) {\r
+          Value = (UINTN)AsmReadMsr64 (RegisterTableEntry->Index);\r
+          if (RegisterTableEntry->ValidBitLength >= 64) {\r
+            if (Value == RegisterTableEntry->Value) {\r
+              break;\r
+            }\r
+          } else {\r
+            CurrentValue = BitFieldRead64 (\r
+                             Value,\r
+                             RegisterTableEntry->ValidBitStart,\r
+                             RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1\r
+                             );\r
+            if (CurrentValue == RegisterTableEntry->Value) {\r
+              break;\r
+            }\r
+          }\r
+        }\r
+\r
+        if (RegisterTableEntry->ValidBitLength >= 64) {\r
+          //\r
+          // If length is not less than 64 bits, then directly write without reading\r
+          //\r
+          AsmWriteMsr64 (\r
+            RegisterTableEntry->Index,\r
+            RegisterTableEntry->Value\r
+            );\r
+        } else {\r
+          //\r
+          // Set the bit section according to bit start and length\r
+          //\r
+          AsmMsrBitFieldWrite64 (\r
+            RegisterTableEntry->Index,\r
+            RegisterTableEntry->ValidBitStart,\r
+            RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1,\r
+            RegisterTableEntry->Value\r
+            );\r
+        }\r
+\r
+        break;\r
       //\r
+      // MemoryMapped operations\r
       //\r
-      //  T0             T1            ...           Tn\r
+      case MemoryMapped:\r
+        AcquireSpinLock (&CpuFlags->MemoryMappedLock);\r
+        MmioBitFieldWrite32 (\r
+          (UINTN)(RegisterTableEntry->Index | LShiftU64 (RegisterTableEntry->HighIndex, 32)),\r
+          RegisterTableEntry->ValidBitStart,\r
+          RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1,\r
+          (UINT32)RegisterTableEntry->Value\r
+          );\r
+        ReleaseSpinLock (&CpuFlags->MemoryMappedLock);\r
+        break;\r
       //\r
-      //  V(0...n)       V(0...n)      ...           V(0...n)\r
-      //  n * P(0)       n * P(1)      ...           n * P(n)\r
+      // Enable or disable cache\r
       //\r
-      switch (RegisterTableEntry->Value) {\r
-      case CoreDepType:\r
-        SemaphorePtr = CpuFlags->CoreSemaphoreCount;\r
-        ThreadCountPerCore = (UINT8 *)(UINTN)CpuStatus->ThreadCountPerCore;\r
-\r
-        CurrentCore = ApLocation->Package * CpuStatus->MaxCoreCount + ApLocation->Core;\r
+      case CacheControl:\r
         //\r
-        // Get Offset info for the first thread in the core which current thread belongs to.\r
+        // If value of the entry is 0, then disable cache.  Otherwise, enable cache.\r
         //\r
-        FirstThread   = CurrentCore * CpuStatus->MaxThreadCount;\r
-        CurrentThread = FirstThread + ApLocation->Thread;\r
-\r
-        //\r
-        // Different cores may have different valid threads in them. If driver maintail clearly\r
-        // thread index in different cores, the logic will be much complicated.\r
-        // Here driver just simply records the max thread number in all cores and use it as expect\r
-        // thread number for all cores.\r
-        // In below two steps logic, first current thread will Release semaphore for each thread\r
-        // in current core. Maybe some threads are not valid in this core, but driver don't\r
-        // care. Second, driver will let current thread wait semaphore for all valid threads in\r
-        // current core. Because only the valid threads will do release semaphore for this\r
-        // thread, driver here only need to wait the valid thread count.\r
-        //\r
-\r
-        //\r
-        // First Notify ALL THREADs in current Core that this thread is ready.\r
-        //\r
-        for (ProcessorIndex = 0; ProcessorIndex < CpuStatus->MaxThreadCount; ProcessorIndex ++) {\r
-          LibReleaseSemaphore (&SemaphorePtr[FirstThread + ProcessorIndex]);\r
-        }\r
-        //\r
-        // Second, check whether all VALID THREADs (not all threads) in current core are ready.\r
-        //\r
-        for (ProcessorIndex = 0; ProcessorIndex < ThreadCountPerCore[CurrentCore]; ProcessorIndex ++) {\r
-          LibWaitForSemaphore (&SemaphorePtr[CurrentThread]);\r
+        if (RegisterTableEntry->Value == 0) {\r
+          AsmDisableCache ();\r
+        } else {\r
+          AsmEnableCache ();\r
         }\r
+\r
         break;\r
 \r
-      case PackageDepType:\r
-        SemaphorePtr = CpuFlags->PackageSemaphoreCount;\r
-        ThreadCountPerPackage = (UINT32 *)(UINTN)CpuStatus->ThreadCountPerPackage;\r
+      case Semaphore:\r
+        // Semaphore works logic like below:\r
         //\r
-        // Get Offset info for the first thread in the package which current thread belongs to.\r
+        //  V(x) = LibReleaseSemaphore (Semaphore[FirstThread + x]);\r
+        //  P(x) = LibWaitForSemaphore (Semaphore[FirstThread + x]);\r
         //\r
-        FirstThread = ApLocation->Package * CpuStatus->MaxCoreCount * CpuStatus->MaxThreadCount;\r
+        //  All threads (T0...Tn) waits in P() line and continues running\r
+        //  together.\r
         //\r
-        // Get the possible threads count for current package.\r
         //\r
-        CurrentThread = FirstThread + CpuStatus->MaxThreadCount * ApLocation->Core + ApLocation->Thread;\r
-\r
+        //  T0             T1            ...           Tn\r
         //\r
-        // Different packages may have different valid threads in them. If driver maintail clearly\r
-        // thread index in different packages, the logic will be much complicated.\r
-        // Here driver just simply records the max thread number in all packages and use it as expect\r
-        // thread number for all packages.\r
-        // In below two steps logic, first current thread will Release semaphore for each thread\r
-        // in current package. Maybe some threads are not valid in this package, but driver don't\r
-        // care. Second, driver will let current thread wait semaphore for all valid threads in\r
-        // current package. Because only the valid threads will do release semaphore for this\r
-        // thread, driver here only need to wait the valid thread count.\r
+        //  V(0...n)       V(0...n)      ...           V(0...n)\r
+        //  n * P(0)       n * P(1)      ...           n * P(n)\r
         //\r
+        switch (RegisterTableEntry->Value) {\r
+          case CoreDepType:\r
+            SemaphorePtr       = CpuFlags->CoreSemaphoreCount;\r
+            ThreadCountPerCore = (UINT8 *)(UINTN)CpuStatus->ThreadCountPerCore;\r
+\r
+            CurrentCore = ApLocation->Package * CpuStatus->MaxCoreCount + ApLocation->Core;\r
+            //\r
+            // Get Offset info for the first thread in the core which current thread belongs to.\r
+            //\r
+            FirstThread   = CurrentCore * CpuStatus->MaxThreadCount;\r
+            CurrentThread = FirstThread + ApLocation->Thread;\r
+\r
+            //\r
+            // Different cores may have different valid threads in them. If driver maintail clearly\r
+            // thread index in different cores, the logic will be much complicated.\r
+            // Here driver just simply records the max thread number in all cores and use it as expect\r
+            // thread number for all cores.\r
+            // In below two steps logic, first current thread will Release semaphore for each thread\r
+            // in current core. Maybe some threads are not valid in this core, but driver don't\r
+            // care. Second, driver will let current thread wait semaphore for all valid threads in\r
+            // current core. Because only the valid threads will do release semaphore for this\r
+            // thread, driver here only need to wait the valid thread count.\r
+            //\r
+\r
+            //\r
+            // First Notify ALL THREADs in current Core that this thread is ready.\r
+            //\r
+            for (ProcessorIndex = 0; ProcessorIndex < CpuStatus->MaxThreadCount; ProcessorIndex++) {\r
+              LibReleaseSemaphore (&SemaphorePtr[FirstThread + ProcessorIndex]);\r
+            }\r
+\r
+            //\r
+            // Second, check whether all VALID THREADs (not all threads) in current core are ready.\r
+            //\r
+            for (ProcessorIndex = 0; ProcessorIndex < ThreadCountPerCore[CurrentCore]; ProcessorIndex++) {\r
+              LibWaitForSemaphore (&SemaphorePtr[CurrentThread]);\r
+            }\r
 \r
-        //\r
-        // First Notify ALL THREADS in current package that this thread is ready.\r
-        //\r
-        for (ProcessorIndex = 0; ProcessorIndex < CpuStatus->MaxThreadCount * CpuStatus->MaxCoreCount; ProcessorIndex ++) {\r
-          LibReleaseSemaphore (&SemaphorePtr[FirstThread + ProcessorIndex]);\r
-        }\r
-        //\r
-        // Second, check whether VALID THREADS (not all threads) in current package are ready.\r
-        //\r
-        for (ProcessorIndex = 0; ProcessorIndex < ThreadCountPerPackage[ApLocation->Package]; ProcessorIndex ++) {\r
-          LibWaitForSemaphore (&SemaphorePtr[CurrentThread]);\r
+            break;\r
+\r
+          case PackageDepType:\r
+            SemaphorePtr          = CpuFlags->PackageSemaphoreCount;\r
+            ThreadCountPerPackage = (UINT32 *)(UINTN)CpuStatus->ThreadCountPerPackage;\r
+            //\r
+            // Get Offset info for the first thread in the package which current thread belongs to.\r
+            //\r
+            FirstThread = ApLocation->Package * CpuStatus->MaxCoreCount * CpuStatus->MaxThreadCount;\r
+            //\r
+            // Get the possible threads count for current package.\r
+            //\r
+            CurrentThread = FirstThread + CpuStatus->MaxThreadCount * ApLocation->Core + ApLocation->Thread;\r
+\r
+            //\r
+            // Different packages may have different valid threads in them. If driver maintail clearly\r
+            // thread index in different packages, the logic will be much complicated.\r
+            // Here driver just simply records the max thread number in all packages and use it as expect\r
+            // thread number for all packages.\r
+            // In below two steps logic, first current thread will Release semaphore for each thread\r
+            // in current package. Maybe some threads are not valid in this package, but driver don't\r
+            // care. Second, driver will let current thread wait semaphore for all valid threads in\r
+            // current package. Because only the valid threads will do release semaphore for this\r
+            // thread, driver here only need to wait the valid thread count.\r
+            //\r
+\r
+            //\r
+            // First Notify ALL THREADS in current package that this thread is ready.\r
+            //\r
+            for (ProcessorIndex = 0; ProcessorIndex < CpuStatus->MaxThreadCount * CpuStatus->MaxCoreCount; ProcessorIndex++) {\r
+              LibReleaseSemaphore (&SemaphorePtr[FirstThread + ProcessorIndex]);\r
+            }\r
+\r
+            //\r
+            // Second, check whether VALID THREADS (not all threads) in current package are ready.\r
+            //\r
+            for (ProcessorIndex = 0; ProcessorIndex < ThreadCountPerPackage[ApLocation->Package]; ProcessorIndex++) {\r
+              LibWaitForSemaphore (&SemaphorePtr[CurrentThread]);\r
+            }\r
+\r
+            break;\r
+\r
+          default:\r
+            break;\r
         }\r
+\r
         break;\r
 \r
       default:\r
         break;\r
-      }\r
-      break;\r
-\r
-    default:\r
-      break;\r
     }\r
   }\r
 }\r
@@ -1120,32 +1151,33 @@ ProgramProcessorRegister (
 VOID\r
 EFIAPI\r
 SetProcessorRegister (\r
-  IN OUT VOID            *Buffer\r
+  IN OUT VOID  *Buffer\r
   )\r
 {\r
-  CPU_FEATURES_DATA         *CpuFeaturesData;\r
-  CPU_REGISTER_TABLE        *RegisterTable;\r
-  CPU_REGISTER_TABLE        *RegisterTables;\r
-  UINT32                    InitApicId;\r
-  UINTN                     ProcIndex;\r
-  UINTN                     Index;\r
-  ACPI_CPU_DATA             *AcpiCpuData;\r
+  CPU_FEATURES_DATA   *CpuFeaturesData;\r
+  CPU_REGISTER_TABLE  *RegisterTable;\r
+  CPU_REGISTER_TABLE  *RegisterTables;\r
+  UINT32              InitApicId;\r
+  UINTN               ProcIndex;\r
+  UINTN               Index;\r
+  ACPI_CPU_DATA       *AcpiCpuData;\r
 \r
-  CpuFeaturesData = (CPU_FEATURES_DATA *) Buffer;\r
-  AcpiCpuData = CpuFeaturesData->AcpiCpuData;\r
+  CpuFeaturesData = (CPU_FEATURES_DATA *)Buffer;\r
+  AcpiCpuData     = CpuFeaturesData->AcpiCpuData;\r
 \r
   RegisterTables = (CPU_REGISTER_TABLE *)(UINTN)AcpiCpuData->CpuFeatureInitData.RegisterTable;\r
 \r
-  InitApicId = GetInitialApicId ();\r
+  InitApicId    = GetInitialApicId ();\r
   RegisterTable = NULL;\r
-  ProcIndex = (UINTN)-1;\r
+  ProcIndex     = (UINTN)-1;\r
   for (Index = 0; Index < AcpiCpuData->NumberOfCpus; Index++) {\r
     if (RegisterTables[Index].InitialApicId == InitApicId) {\r
       RegisterTable =  &RegisterTables[Index];\r
-      ProcIndex = Index;\r
+      ProcIndex     = Index;\r
       break;\r
     }\r
   }\r
+\r
   ASSERT (RegisterTable != NULL);\r
 \r
   ProgramProcessorRegister (\r
@@ -1170,9 +1202,9 @@ CpuFeaturesDetect (
   VOID\r
   )\r
 {\r
-  CPU_FEATURES_DATA      *CpuFeaturesData;\r
+  CPU_FEATURES_DATA  *CpuFeaturesData;\r
 \r
-  CpuFeaturesData = GetCpuFeaturesData();\r
+  CpuFeaturesData = GetCpuFeaturesData ();\r
 \r
   CpuInitDataInitialize ();\r
 \r

diff --git a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/DxeRegisterCpuFeaturesLib.c b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/DxeRegisterCpuFeaturesLib.c
index e2e06e88e0a787a38edc6ba21078b2f1d57d50c4..e635cade5d5b0b04c211310835f3efcc14570721 100644 (file)
--- a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/DxeRegisterCpuFeaturesLib.c
+++ b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/DxeRegisterCpuFeaturesLib.c
@@ -13,7 +13,7 @@
 \r
 #include "RegisterCpuFeatures.h"\r
 \r
-CPU_FEATURES_DATA          mCpuFeaturesData = {0};\r
+CPU_FEATURES_DATA  mCpuFeaturesData = { 0 };\r
 \r
 /**\r
   Worker function to get CPU_FEATURES_DATA pointer.\r
@@ -38,17 +38,17 @@ GetMpService (
   VOID\r
   )\r
 {\r
-  EFI_STATUS                Status;\r
-  MP_SERVICES               MpService;\r
+  EFI_STATUS   Status;\r
+  MP_SERVICES  MpService;\r
 \r
   //\r
   // Get MP Services Protocol\r
   //\r
   Status = gBS->LocateProtocol (\r
-                &gEfiMpServiceProtocolGuid,\r
-                NULL,\r
-                (VOID **)&MpService.Protocol\r
-                );\r
+                  &gEfiMpServiceProtocolGuid,\r
+                  NULL,\r
+                  (VOID **)&MpService.Protocol\r
+                  );\r
   ASSERT_EFI_ERROR (Status);\r
 \r
   return MpService;\r
@@ -63,15 +63,15 @@ GetMpService (
 **/\r
 UINTN\r
 GetProcessorIndex (\r
-  IN CPU_FEATURES_DATA        *CpuFeaturesData\r
+  IN CPU_FEATURES_DATA  *CpuFeaturesData\r
   )\r
 {\r
-  EFI_STATUS                           Status;\r
-  UINTN                                ProcessorIndex;\r
-  EFI_MP_SERVICES_PROTOCOL             *MpServices;\r
+  EFI_STATUS                Status;\r
+  UINTN                     ProcessorIndex;\r
+  EFI_MP_SERVICES_PROTOCOL  *MpServices;\r
 \r
   MpServices = CpuFeaturesData->MpService.Protocol;\r
-  Status = MpServices->WhoAmI(MpServices, &ProcessorIndex);\r
+  Status     = MpServices->WhoAmI (MpServices, &ProcessorIndex);\r
   ASSERT_EFI_ERROR (Status);\r
   return ProcessorIndex;\r
 }\r
@@ -88,22 +88,22 @@ GetProcessorIndex (
 **/\r
 EFI_STATUS\r
 GetProcessorInformation (\r
-  IN  UINTN                            ProcessorNumber,\r
-  OUT EFI_PROCESSOR_INFORMATION        *ProcessorInfoBuffer\r
+  IN  UINTN                      ProcessorNumber,\r
+  OUT EFI_PROCESSOR_INFORMATION  *ProcessorInfoBuffer\r
   )\r
 {\r
-  EFI_STATUS                           Status;\r
-  EFI_MP_SERVICES_PROTOCOL             *MpServices;\r
-  CPU_FEATURES_DATA                    *CpuFeaturesData;\r
+  EFI_STATUS                Status;\r
+  EFI_MP_SERVICES_PROTOCOL  *MpServices;\r
+  CPU_FEATURES_DATA         *CpuFeaturesData;\r
 \r
   CpuFeaturesData = GetCpuFeaturesData ();\r
-  MpServices = CpuFeaturesData->MpService.Protocol;\r
+  MpServices      = CpuFeaturesData->MpService.Protocol;\r
 \r
   Status = MpServices->GetProcessorInfo (\r
-               MpServices,\r
-               ProcessorNumber,\r
-               ProcessorInfoBuffer\r
-               );\r
+                         MpServices,\r
+                         ProcessorNumber,\r
+                         ProcessorInfoBuffer\r
+                         );\r
   return Status;\r
 }\r
 \r
@@ -117,29 +117,29 @@ GetProcessorInformation (
 **/\r
 VOID\r
 StartupAllAPsWorker (\r
-  IN  EFI_AP_PROCEDURE                 Procedure,\r
-  IN  EFI_EVENT                        MpEvent\r
+  IN  EFI_AP_PROCEDURE  Procedure,\r
+  IN  EFI_EVENT         MpEvent\r
   )\r
 {\r
-  EFI_STATUS                           Status;\r
-  EFI_MP_SERVICES_PROTOCOL             *MpServices;\r
-  CPU_FEATURES_DATA                    *CpuFeaturesData;\r
+  EFI_STATUS                Status;\r
+  EFI_MP_SERVICES_PROTOCOL  *MpServices;\r
+  CPU_FEATURES_DATA         *CpuFeaturesData;\r
 \r
   CpuFeaturesData = GetCpuFeaturesData ();\r
-  MpServices = CpuFeaturesData->MpService.Protocol;\r
+  MpServices      = CpuFeaturesData->MpService.Protocol;\r
 \r
   //\r
   // Wakeup all APs\r
   //\r
   Status = MpServices->StartupAllAPs (\r
-                 MpServices,\r
-                 Procedure,\r
-                 FALSE,\r
-                 MpEvent,\r
-                 0,\r
-                 CpuFeaturesData,\r
-                 NULL\r
-                 );\r
+                         MpServices,\r
+                         Procedure,\r
+                         FALSE,\r
+                         MpEvent,\r
+                         0,\r
+                         CpuFeaturesData,\r
+                         NULL\r
+                         );\r
   ASSERT_EFI_ERROR (Status);\r
 }\r
 \r
@@ -150,24 +150,24 @@ StartupAllAPsWorker (
 **/\r
 VOID\r
 SwitchNewBsp (\r
-  IN  UINTN                            ProcessorNumber\r
+  IN  UINTN  ProcessorNumber\r
   )\r
 {\r
-  EFI_STATUS                           Status;\r
-  EFI_MP_SERVICES_PROTOCOL             *MpServices;\r
-  CPU_FEATURES_DATA                    *CpuFeaturesData;\r
+  EFI_STATUS                Status;\r
+  EFI_MP_SERVICES_PROTOCOL  *MpServices;\r
+  CPU_FEATURES_DATA         *CpuFeaturesData;\r
 \r
   CpuFeaturesData = GetCpuFeaturesData ();\r
-  MpServices = CpuFeaturesData->MpService.Protocol;\r
+  MpServices      = CpuFeaturesData->MpService.Protocol;\r
 \r
   //\r
   // Wakeup all APs\r
   //\r
   Status = MpServices->SwitchBSP (\r
-                 MpServices,\r
-                 ProcessorNumber,\r
-                 TRUE\r
-                 );\r
+                         MpServices,\r
+                         ProcessorNumber,\r
+                         TRUE\r
+                         );\r
   ASSERT_EFI_ERROR (Status);\r
 }\r
 \r
@@ -183,16 +183,16 @@ SwitchNewBsp (
 **/\r
 VOID\r
 GetNumberOfProcessor (\r
-  OUT UINTN                            *NumberOfCpus,\r
-  OUT UINTN                            *NumberOfEnabledProcessors\r
+  OUT UINTN  *NumberOfCpus,\r
+  OUT UINTN  *NumberOfEnabledProcessors\r
   )\r
 {\r
-  EFI_STATUS                           Status;\r
-  EFI_MP_SERVICES_PROTOCOL             *MpServices;\r
-  CPU_FEATURES_DATA                    *CpuFeaturesData;\r
+  EFI_STATUS                Status;\r
+  EFI_MP_SERVICES_PROTOCOL  *MpServices;\r
+  CPU_FEATURES_DATA         *CpuFeaturesData;\r
 \r
   CpuFeaturesData = GetCpuFeaturesData ();\r
-  MpServices = CpuFeaturesData->MpService.Protocol;\r
+  MpServices      = CpuFeaturesData->MpService.Protocol;\r
 \r
   //\r
   // Get the number of CPUs\r
@@ -219,14 +219,14 @@ CpuFeaturesInitialize (
   VOID\r
   )\r
 {\r
-  CPU_FEATURES_DATA          *CpuFeaturesData;\r
-  UINTN                      OldBspNumber;\r
-  EFI_EVENT                  MpEvent;\r
-  EFI_STATUS                 Status;\r
+  CPU_FEATURES_DATA  *CpuFeaturesData;\r
+  UINTN              OldBspNumber;\r
+  EFI_EVENT          MpEvent;\r
+  EFI_STATUS         Status;\r
 \r
   CpuFeaturesData = GetCpuFeaturesData ();\r
 \r
-  OldBspNumber = GetProcessorIndex (CpuFeaturesData);\r
+  OldBspNumber               = GetProcessorIndex (CpuFeaturesData);\r
   CpuFeaturesData->BspNumber = OldBspNumber;\r
 \r
   //\r
@@ -263,6 +263,7 @@ CpuFeaturesInitialize (
     do {\r
       Status = gBS->CheckEvent (MpEvent);\r
     } while (Status == EFI_NOT_READY);\r
+\r
     ASSERT_EFI_ERROR (Status);\r
   }\r
 \r
@@ -273,4 +274,3 @@ CpuFeaturesInitialize (
     SwitchNewBsp (CpuFeaturesData->BspNumber);\r
   }\r
 }\r
-\r

diff --git a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/PeiRegisterCpuFeaturesLib.c b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/PeiRegisterCpuFeaturesLib.c
index 4e558e9fee5a2476f599f1d6cd2ed92c8a5a5d55..d4c528b3e9c26d4985c0fa6a1c6d024fee1fe7ce 100644 (file)
--- a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/PeiRegisterCpuFeaturesLib.c
+++ b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/PeiRegisterCpuFeaturesLib.c
@@ -20,7 +20,7 @@
     0xa694c467, 0x697a, 0x446b, { 0xb9, 0x29, 0x5b, 0x14, 0xa0, 0xcf, 0x39, 0xf } \\r
   }\r
 \r
-EFI_GUID mRegisterCpuFeaturesHobGuid = REGISTER_CPU_FEATURES_GUID;\r
+EFI_GUID  mRegisterCpuFeaturesHobGuid = REGISTER_CPU_FEATURES_GUID;\r
 \r
 /**\r
   Worker function to get CPU_FEATURES_DATA pointer.\r
@@ -32,16 +32,16 @@ GetCpuFeaturesData (
   VOID\r
   )\r
 {\r
-  CPU_FEATURES_DATA       *CpuInitData;\r
-  EFI_HOB_GUID_TYPE       *GuidHob;\r
-  VOID                    *DataInHob;\r
-  UINT64                  Data64;\r
+  CPU_FEATURES_DATA  *CpuInitData;\r
+  EFI_HOB_GUID_TYPE  *GuidHob;\r
+  VOID               *DataInHob;\r
+  UINT64             Data64;\r
 \r
   CpuInitData = NULL;\r
-  GuidHob = GetFirstGuidHob (&mRegisterCpuFeaturesHobGuid);\r
+  GuidHob     = GetFirstGuidHob (&mRegisterCpuFeaturesHobGuid);\r
   if (GuidHob != NULL) {\r
-    DataInHob = GET_GUID_HOB_DATA (GuidHob);\r
-    CpuInitData = (CPU_FEATURES_DATA *) (*(UINTN *) DataInHob);\r
+    DataInHob   = GET_GUID_HOB_DATA (GuidHob);\r
+    CpuInitData = (CPU_FEATURES_DATA *)(*(UINTN *)DataInHob);\r
     ASSERT (CpuInitData != NULL);\r
   } else {\r
     CpuInitData = AllocateZeroPool (sizeof (CPU_FEATURES_DATA));\r
@@ -49,10 +49,10 @@ GetCpuFeaturesData (
     //\r
     // Build location of CPU MP DATA buffer in HOB\r
     //\r
-    Data64 = (UINT64) (UINTN) CpuInitData;\r
+    Data64 = (UINT64)(UINTN)CpuInitData;\r
     BuildGuidDataHob (\r
       &mRegisterCpuFeaturesHobGuid,\r
-      (VOID *) &Data64,\r
+      (VOID *)&Data64,\r
       sizeof (UINT64)\r
       );\r
   }\r
@@ -70,8 +70,8 @@ GetMpService (
   VOID\r
   )\r
 {\r
-  EFI_STATUS                 Status;\r
-  MP_SERVICES                MpService;\r
+  EFI_STATUS   Status;\r
+  MP_SERVICES  MpService;\r
 \r
   //\r
   // Get MP Services2 Ppi\r
@@ -95,12 +95,12 @@ GetMpService (
 **/\r
 UINTN\r
 GetProcessorIndex (\r
-  IN CPU_FEATURES_DATA        *CpuFeaturesData\r
+  IN CPU_FEATURES_DATA  *CpuFeaturesData\r
   )\r
 {\r
-  EFI_STATUS                 Status;\r
-  EDKII_PEI_MP_SERVICES2_PPI *CpuMp2Ppi;\r
-  UINTN                      ProcessorIndex;\r
+  EFI_STATUS                  Status;\r
+  EDKII_PEI_MP_SERVICES2_PPI  *CpuMp2Ppi;\r
+  UINTN                       ProcessorIndex;\r
 \r
   CpuMp2Ppi = CpuFeaturesData->MpService.Ppi;\r
 \r
@@ -126,22 +126,22 @@ GetProcessorIndex (
 **/\r
 EFI_STATUS\r
 GetProcessorInformation (\r
-  IN  UINTN                            ProcessorNumber,\r
-  OUT EFI_PROCESSOR_INFORMATION        *ProcessorInfoBuffer\r
+  IN  UINTN                      ProcessorNumber,\r
+  OUT EFI_PROCESSOR_INFORMATION  *ProcessorInfoBuffer\r
   )\r
 {\r
-  EDKII_PEI_MP_SERVICES2_PPI *CpuMp2Ppi;\r
-  EFI_STATUS                 Status;\r
-  CPU_FEATURES_DATA          *CpuFeaturesData;\r
+  EDKII_PEI_MP_SERVICES2_PPI  *CpuMp2Ppi;\r
+  EFI_STATUS                  Status;\r
+  CPU_FEATURES_DATA           *CpuFeaturesData;\r
 \r
   CpuFeaturesData = GetCpuFeaturesData ();\r
-  CpuMp2Ppi = CpuFeaturesData->MpService.Ppi;\r
+  CpuMp2Ppi       = CpuFeaturesData->MpService.Ppi;\r
 \r
   Status = CpuMp2Ppi->GetProcessorInfo (\r
-               CpuMp2Ppi,\r
-               ProcessorNumber,\r
-               ProcessorInfoBuffer\r
-               );\r
+                        CpuMp2Ppi,\r
+                        ProcessorNumber,\r
+                        ProcessorInfoBuffer\r
+                        );\r
   return Status;\r
 }\r
 \r
@@ -155,27 +155,27 @@ GetProcessorInformation (
 **/\r
 VOID\r
 StartupAllAPsWorker (\r
-  IN  EFI_AP_PROCEDURE                 Procedure,\r
-  IN  EFI_EVENT                        MpEvent\r
+  IN  EFI_AP_PROCEDURE  Procedure,\r
+  IN  EFI_EVENT         MpEvent\r
   )\r
 {\r
-  EFI_STATUS                           Status;\r
-  EDKII_PEI_MP_SERVICES2_PPI           *CpuMp2Ppi;\r
-  CPU_FEATURES_DATA                    *CpuFeaturesData;\r
+  EFI_STATUS                  Status;\r
+  EDKII_PEI_MP_SERVICES2_PPI  *CpuMp2Ppi;\r
+  CPU_FEATURES_DATA           *CpuFeaturesData;\r
 \r
   CpuFeaturesData = GetCpuFeaturesData ();\r
-  CpuMp2Ppi = CpuFeaturesData->MpService.Ppi;\r
+  CpuMp2Ppi       = CpuFeaturesData->MpService.Ppi;\r
 \r
   //\r
   // Wakeup all APs for data collection.\r
   //\r
   Status = CpuMp2Ppi->StartupAllAPs (\r
-                 CpuMp2Ppi,\r
-                 Procedure,\r
-                 FALSE,\r
-                 0,\r
-                 CpuFeaturesData\r
-                 );\r
+                        CpuMp2Ppi,\r
+                        Procedure,\r
+                        FALSE,\r
+                        0,\r
+                        CpuFeaturesData\r
+                        );\r
   ASSERT_EFI_ERROR (Status);\r
 }\r
 \r
@@ -188,12 +188,12 @@ StartupAllAPsWorker (
 **/\r
 VOID\r
 StartupAllCPUsWorker (\r
-  IN  EFI_AP_PROCEDURE                 Procedure\r
+  IN  EFI_AP_PROCEDURE  Procedure\r
   )\r
 {\r
-  EFI_STATUS                           Status;\r
-  EDKII_PEI_MP_SERVICES2_PPI           *CpuMp2Ppi;\r
-  CPU_FEATURES_DATA                    *CpuFeaturesData;\r
+  EFI_STATUS                  Status;\r
+  EDKII_PEI_MP_SERVICES2_PPI  *CpuMp2Ppi;\r
+  CPU_FEATURES_DATA           *CpuFeaturesData;\r
 \r
   CpuFeaturesData = GetCpuFeaturesData ();\r
 \r
@@ -201,12 +201,12 @@ StartupAllCPUsWorker (
   // Get MP Services2 Ppi\r
   //\r
   CpuMp2Ppi = CpuFeaturesData->MpService.Ppi;\r
-  Status = CpuMp2Ppi->StartupAllCPUs (\r
-                 CpuMp2Ppi,\r
-                 Procedure,\r
-                 0,\r
-                 CpuFeaturesData\r
-                 );\r
+  Status    = CpuMp2Ppi->StartupAllCPUs (\r
+                           CpuMp2Ppi,\r
+                           Procedure,\r
+                           0,\r
+                           CpuFeaturesData\r
+                           );\r
   ASSERT_EFI_ERROR (Status);\r
 }\r
 \r
@@ -217,24 +217,24 @@ StartupAllCPUsWorker (
 **/\r
 VOID\r
 SwitchNewBsp (\r
-  IN  UINTN                            ProcessorNumber\r
+  IN  UINTN  ProcessorNumber\r
   )\r
 {\r
-  EFI_STATUS                           Status;\r
-  EDKII_PEI_MP_SERVICES2_PPI           *CpuMp2Ppi;\r
-  CPU_FEATURES_DATA                    *CpuFeaturesData;\r
+  EFI_STATUS                  Status;\r
+  EDKII_PEI_MP_SERVICES2_PPI  *CpuMp2Ppi;\r
+  CPU_FEATURES_DATA           *CpuFeaturesData;\r
 \r
   CpuFeaturesData = GetCpuFeaturesData ();\r
-  CpuMp2Ppi = CpuFeaturesData->MpService.Ppi;\r
+  CpuMp2Ppi       = CpuFeaturesData->MpService.Ppi;\r
 \r
   //\r
   // Wakeup all APs for data collection.\r
   //\r
   Status = CpuMp2Ppi->SwitchBSP (\r
-                 CpuMp2Ppi,\r
-                 ProcessorNumber,\r
-                 TRUE\r
-                 );\r
+                        CpuMp2Ppi,\r
+                        ProcessorNumber,\r
+                        TRUE\r
+                        );\r
   ASSERT_EFI_ERROR (Status);\r
 }\r
 \r
@@ -250,25 +250,25 @@ SwitchNewBsp (
 **/\r
 VOID\r
 GetNumberOfProcessor (\r
-  OUT UINTN                            *NumberOfCpus,\r
-  OUT UINTN                            *NumberOfEnabledProcessors\r
+  OUT UINTN  *NumberOfCpus,\r
+  OUT UINTN  *NumberOfEnabledProcessors\r
   )\r
 {\r
-  EFI_STATUS                 Status;\r
-  EDKII_PEI_MP_SERVICES2_PPI *CpuMp2Ppi;\r
-  CPU_FEATURES_DATA          *CpuFeaturesData;\r
+  EFI_STATUS                  Status;\r
+  EDKII_PEI_MP_SERVICES2_PPI  *CpuMp2Ppi;\r
+  CPU_FEATURES_DATA           *CpuFeaturesData;\r
 \r
   CpuFeaturesData = GetCpuFeaturesData ();\r
-  CpuMp2Ppi = CpuFeaturesData->MpService.Ppi;\r
+  CpuMp2Ppi       = CpuFeaturesData->MpService.Ppi;\r
 \r
   //\r
   // Get the number of CPUs\r
   //\r
   Status = CpuMp2Ppi->GetNumberOfProcessors (\r
-                         CpuMp2Ppi,\r
-                         NumberOfCpus,\r
-                         NumberOfEnabledProcessors\r
-                         );\r
+                        CpuMp2Ppi,\r
+                        NumberOfCpus,\r
+                        NumberOfEnabledProcessors\r
+                        );\r
   ASSERT_EFI_ERROR (Status);\r
 }\r
 \r
@@ -286,12 +286,12 @@ CpuFeaturesInitialize (
   VOID\r
   )\r
 {\r
-  CPU_FEATURES_DATA          *CpuFeaturesData;\r
-  UINTN                      OldBspNumber;\r
+  CPU_FEATURES_DATA  *CpuFeaturesData;\r
+  UINTN              OldBspNumber;\r
 \r
   CpuFeaturesData = GetCpuFeaturesData ();\r
 \r
-  OldBspNumber = GetProcessorIndex (CpuFeaturesData);\r
+  OldBspNumber               = GetProcessorIndex (CpuFeaturesData);\r
   CpuFeaturesData->BspNumber = OldBspNumber;\r
 \r
   //\r
@@ -306,4 +306,3 @@ CpuFeaturesInitialize (
     SwitchNewBsp (CpuFeaturesData->BspNumber);\r
   }\r
 }\r
-\r

diff --git a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeatures.h b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeatures.h
index e8a4aa644d25ace3a44b9581b2e8ac56297d5055..4a84954cac9d6a2be778051ad0cd4cb4628f9040 100644 (file)
--- a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeatures.h
+++ b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeatures.h
@@ -27,66 +27,66 @@
 \r
 #define CPU_FEATURE_ENTRY_SIGNATURE  SIGNATURE_32 ('C', 'F', 'E', 'S')\r
 \r
-#define CPU_FEATURE_NAME_SIZE        128\r
+#define CPU_FEATURE_NAME_SIZE  128\r
 \r
 typedef struct {\r
-  REGISTER_CPU_FEATURE_INFORMATION     CpuInfo;\r
-  UINT8                                *FeaturesSupportedMask;\r
-  LIST_ENTRY                           OrderList;\r
+  REGISTER_CPU_FEATURE_INFORMATION    CpuInfo;\r
+  UINT8                               *FeaturesSupportedMask;\r
+  LIST_ENTRY                          OrderList;\r
 } CPU_FEATURES_INIT_ORDER;\r
 \r
 typedef struct {\r
-  UINT32                       Signature;\r
-  LIST_ENTRY                   Link;\r
-  UINT8                        *FeatureMask;\r
-  CHAR8                        *FeatureName;\r
-  CPU_FEATURE_GET_CONFIG_DATA  GetConfigDataFunc;\r
-  CPU_FEATURE_SUPPORT          SupportFunc;\r
-  CPU_FEATURE_INITIALIZE       InitializeFunc;\r
-  UINT8                        *ThreadBeforeFeatureBitMask;\r
-  UINT8                        *ThreadAfterFeatureBitMask;\r
-  UINT8                        *CoreBeforeFeatureBitMask;\r
-  UINT8                        *CoreAfterFeatureBitMask;\r
-  UINT8                        *PackageBeforeFeatureBitMask;\r
-  UINT8                        *PackageAfterFeatureBitMask;\r
-  VOID                         *ConfigData;\r
-  BOOLEAN                      BeforeAll;\r
-  BOOLEAN                      AfterAll;\r
+  UINT32                         Signature;\r
+  LIST_ENTRY                     Link;\r
+  UINT8                          *FeatureMask;\r
+  CHAR8                          *FeatureName;\r
+  CPU_FEATURE_GET_CONFIG_DATA    GetConfigDataFunc;\r
+  CPU_FEATURE_SUPPORT            SupportFunc;\r
+  CPU_FEATURE_INITIALIZE         InitializeFunc;\r
+  UINT8                          *ThreadBeforeFeatureBitMask;\r
+  UINT8                          *ThreadAfterFeatureBitMask;\r
+  UINT8                          *CoreBeforeFeatureBitMask;\r
+  UINT8                          *CoreAfterFeatureBitMask;\r
+  UINT8                          *PackageBeforeFeatureBitMask;\r
+  UINT8                          *PackageAfterFeatureBitMask;\r
+  VOID                           *ConfigData;\r
+  BOOLEAN                        BeforeAll;\r
+  BOOLEAN                        AfterAll;\r
 } CPU_FEATURES_ENTRY;\r
 \r
 //\r
 // Flags used when program the register.\r
 //\r
 typedef struct {\r
-  volatile UINTN           MemoryMappedLock;        // Spinlock used to program mmio\r
-  volatile UINT32          *CoreSemaphoreCount;     // Semaphore containers used to program Core semaphore.\r
-  volatile UINT32          *PackageSemaphoreCount;  // Semaphore containers used to program Package semaphore.\r
+  volatile UINTN     MemoryMappedLock;              // Spinlock used to program mmio\r
+  volatile UINT32    *CoreSemaphoreCount;           // Semaphore containers used to program Core semaphore.\r
+  volatile UINT32    *PackageSemaphoreCount;        // Semaphore containers used to program Package semaphore.\r
 } PROGRAM_CPU_REGISTER_FLAGS;\r
 \r
 typedef union {\r
-  EFI_MP_SERVICES_PROTOCOL   *Protocol;\r
-  EDKII_PEI_MP_SERVICES2_PPI *Ppi;\r
+  EFI_MP_SERVICES_PROTOCOL      *Protocol;\r
+  EDKII_PEI_MP_SERVICES2_PPI    *Ppi;\r
 } MP_SERVICES;\r
 \r
 typedef struct {\r
-  UINTN                    FeaturesCount;\r
-  UINT32                   BitMaskSize;\r
-  LIST_ENTRY               FeatureList;\r
+  UINTN                         FeaturesCount;\r
+  UINT32                        BitMaskSize;\r
+  LIST_ENTRY                    FeatureList;\r
 \r
-  CPU_FEATURES_INIT_ORDER  *InitOrder;\r
-  UINT8                    *CapabilityPcd;\r
-  UINT8                    *SettingPcd;\r
+  CPU_FEATURES_INIT_ORDER       *InitOrder;\r
+  UINT8                         *CapabilityPcd;\r
+  UINT8                         *SettingPcd;\r
 \r
-  UINT32                   NumberOfCpus;\r
-  ACPI_CPU_DATA            *AcpiCpuData;\r
+  UINT32                        NumberOfCpus;\r
+  ACPI_CPU_DATA                 *AcpiCpuData;\r
 \r
-  CPU_REGISTER_TABLE       *RegisterTable;\r
-  CPU_REGISTER_TABLE       *PreSmmRegisterTable;\r
-  UINTN                    BspNumber;\r
+  CPU_REGISTER_TABLE            *RegisterTable;\r
+  CPU_REGISTER_TABLE            *PreSmmRegisterTable;\r
+  UINTN                         BspNumber;\r
 \r
-  PROGRAM_CPU_REGISTER_FLAGS  CpuFlags;\r
+  PROGRAM_CPU_REGISTER_FLAGS    CpuFlags;\r
 \r
-  MP_SERVICES              MpService;\r
+  MP_SERVICES                   MpService;\r
 } CPU_FEATURES_DATA;\r
 \r
 #define CPU_FEATURE_ENTRY_FROM_LINK(a) \\r
@@ -116,7 +116,7 @@ GetCpuFeaturesData (
 **/\r
 UINTN\r
 GetProcessorIndex (\r
-  IN CPU_FEATURES_DATA        *CpuFeaturesData\r
+  IN CPU_FEATURES_DATA  *CpuFeaturesData\r
   );\r
 \r
 /**\r
@@ -131,8 +131,8 @@ GetProcessorIndex (
 **/\r
 EFI_STATUS\r
 GetProcessorInformation (\r
-  IN  UINTN                            ProcessorNumber,\r
-  OUT EFI_PROCESSOR_INFORMATION        *ProcessorInfoBuffer\r
+  IN  UINTN                      ProcessorNumber,\r
+  OUT EFI_PROCESSOR_INFORMATION  *ProcessorInfoBuffer\r
   );\r
 \r
 /**\r
@@ -145,8 +145,8 @@ GetProcessorInformation (
 **/\r
 VOID\r
 StartupAllAPsWorker (\r
-  IN  EFI_AP_PROCEDURE                 Procedure,\r
-  IN  EFI_EVENT                        MpEvent\r
+  IN  EFI_AP_PROCEDURE  Procedure,\r
+  IN  EFI_EVENT         MpEvent\r
   );\r
 \r
 /**\r
@@ -161,8 +161,8 @@ StartupAllAPsWorker (
 **/\r
 VOID\r
 GetNumberOfProcessor (\r
-  OUT UINTN                            *NumberOfCpus,\r
-  OUT UINTN                            *NumberOfEnabledProcessors\r
+  OUT UINTN  *NumberOfCpus,\r
+  OUT UINTN  *NumberOfEnabledProcessors\r
   );\r
 \r
 /**\r
@@ -172,7 +172,7 @@ GetNumberOfProcessor (
 **/\r
 VOID\r
 SwitchNewBsp (\r
-  IN  UINTN                            ProcessorNumber\r
+  IN  UINTN  ProcessorNumber\r
   );\r
 \r
 /**\r
@@ -184,8 +184,8 @@ SwitchNewBsp (
 **/\r
 VOID\r
 DumpCpuFeatureMask (\r
-  IN UINT8               *FeatureMask,\r
-  IN UINT32              BitMaskSize\r
+  IN UINT8   *FeatureMask,\r
+  IN UINT32  BitMaskSize\r
   );\r
 \r
 /**\r
@@ -212,9 +212,9 @@ DumpCpuFeature (
 **/\r
 CPU_FEATURE_DEPENDENCE_TYPE\r
 DetectFeatureScope (\r
-  IN CPU_FEATURES_ENTRY         *CpuFeature,\r
-  IN BOOLEAN                    Before,\r
-  IN UINT8                      *NextCpuFeatureMask\r
+  IN CPU_FEATURES_ENTRY  *CpuFeature,\r
+  IN BOOLEAN             Before,\r
+  IN UINT8               *NextCpuFeatureMask\r
   );\r
 \r
 /**\r
@@ -228,9 +228,9 @@ DetectFeatureScope (
 **/\r
 CPU_FEATURE_DEPENDENCE_TYPE\r
 DetectNoneNeighborhoodFeatureScope (\r
-  IN CPU_FEATURES_ENTRY         *CpuFeature,\r
-  IN BOOLEAN                    Before,\r
-  IN LIST_ENTRY                 *FeatureList\r
+  IN CPU_FEATURES_ENTRY  *CpuFeature,\r
+  IN BOOLEAN             Before,\r
+  IN LIST_ENTRY          *FeatureList\r
   );\r
 \r
 /**\r
@@ -242,7 +242,7 @@ DetectNoneNeighborhoodFeatureScope (
 VOID\r
 EFIAPI\r
 SetProcessorRegister (\r
-  IN OUT VOID            *Buffer\r
+  IN OUT VOID  *Buffer\r
   );\r
 \r
 /**\r

diff --git a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.c b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.c
index ffe34ffb4836c7bb01bf01b56f9604e2c43ca97f..0285aaf5c91a2cd1dbc65bc5dc5860f0c767ee36 100644 (file)
--- a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.c
+++ b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.c
@@ -17,17 +17,18 @@
 **/\r
 VOID\r
 DumpCpuFeatureMask (\r
-  IN UINT8               *FeatureMask,\r
-  IN UINT32              BitMaskSize\r
+  IN UINT8   *FeatureMask,\r
+  IN UINT32  BitMaskSize\r
   )\r
 {\r
-  UINTN                  Index;\r
-  UINT8                  *Data8;\r
+  UINTN  Index;\r
+  UINT8  *Data8;\r
 \r
-  Data8       = (UINT8 *) FeatureMask;\r
+  Data8 = (UINT8 *)FeatureMask;\r
   for (Index = 0; Index < BitMaskSize; Index++) {\r
     DEBUG ((DEBUG_INFO, " %02x ", *Data8++));\r
   }\r
+\r
   DEBUG ((DEBUG_INFO, "\n"));\r
 }\r
 \r
@@ -44,7 +45,6 @@ DumpCpuFeature (
   IN UINT32              BitMaskSize\r
   )\r
 {\r
-\r
   if (CpuFeature->FeatureName != NULL) {\r
     DEBUG ((DEBUG_INFO, "FeatureName: %a\n", CpuFeature->FeatureName));\r
   } else {\r
@@ -64,8 +64,8 @@ DumpCpuFeature (
 **/\r
 BOOLEAN\r
 IsBitMaskMatchCheck (\r
-  IN UINT8        *FeatureMask,\r
-  IN UINT8        *DependentBitMask\r
+  IN UINT8  *FeatureMask,\r
+  IN UINT8  *DependentBitMask\r
   )\r
 {\r
   UINTN              Index;\r
@@ -82,6 +82,7 @@ IsBitMaskMatchCheck (
       return TRUE;\r
     }\r
   }\r
+\r
   return FALSE;\r
 }\r
 \r
@@ -98,14 +99,14 @@ IsBitMaskMatchCheck (
 **/\r
 BOOLEAN\r
 FindSpecifyFeature (\r
-  IN LIST_ENTRY              *FeatureList,\r
-  IN LIST_ENTRY              *CurrentEntry,\r
-  IN BOOLEAN                 SearchFormer,\r
-  IN UINT8                   *FeatureMask\r
+  IN LIST_ENTRY  *FeatureList,\r
+  IN LIST_ENTRY  *CurrentEntry,\r
+  IN BOOLEAN     SearchFormer,\r
+  IN UINT8       *FeatureMask\r
   )\r
 {\r
-  CPU_FEATURES_ENTRY         *CpuFeature;\r
-  LIST_ENTRY                 *NextEntry;\r
+  CPU_FEATURES_ENTRY  *CpuFeature;\r
+  LIST_ENTRY          *NextEntry;\r
 \r
   //\r
   // Check whether exist the not neighborhood entry first.\r
@@ -165,9 +166,9 @@ FindSpecifyFeature (
 **/\r
 CPU_FEATURE_DEPENDENCE_TYPE\r
 DetectFeatureScope (\r
-  IN CPU_FEATURES_ENTRY         *CpuFeature,\r
-  IN BOOLEAN                    Before,\r
-  IN UINT8                      *NextCpuFeatureMask\r
+  IN CPU_FEATURES_ENTRY  *CpuFeature,\r
+  IN BOOLEAN             Before,\r
+  IN UINT8               *NextCpuFeatureMask\r
   )\r
 {\r
   //\r
@@ -185,17 +186,20 @@ DetectFeatureScope (
 \r
   if (Before) {\r
     if ((CpuFeature->PackageBeforeFeatureBitMask != NULL) &&\r
-        IsBitMaskMatchCheck (NextCpuFeatureMask, CpuFeature->PackageBeforeFeatureBitMask)) {\r
+        IsBitMaskMatchCheck (NextCpuFeatureMask, CpuFeature->PackageBeforeFeatureBitMask))\r
+    {\r
       return PackageDepType;\r
     }\r
 \r
     if ((CpuFeature->CoreBeforeFeatureBitMask != NULL) &&\r
-        IsBitMaskMatchCheck (NextCpuFeatureMask, CpuFeature->CoreBeforeFeatureBitMask)) {\r
+        IsBitMaskMatchCheck (NextCpuFeatureMask, CpuFeature->CoreBeforeFeatureBitMask))\r
+    {\r
       return CoreDepType;\r
     }\r
 \r
     if ((CpuFeature->ThreadBeforeFeatureBitMask != NULL) &&\r
-        IsBitMaskMatchCheck (NextCpuFeatureMask, CpuFeature->ThreadBeforeFeatureBitMask)) {\r
+        IsBitMaskMatchCheck (NextCpuFeatureMask, CpuFeature->ThreadBeforeFeatureBitMask))\r
+    {\r
       return ThreadDepType;\r
     }\r
 \r
@@ -203,17 +207,20 @@ DetectFeatureScope (
   }\r
 \r
   if ((CpuFeature->PackageAfterFeatureBitMask != NULL) &&\r
-      IsBitMaskMatchCheck (NextCpuFeatureMask, CpuFeature->PackageAfterFeatureBitMask)) {\r
+      IsBitMaskMatchCheck (NextCpuFeatureMask, CpuFeature->PackageAfterFeatureBitMask))\r
+  {\r
     return PackageDepType;\r
   }\r
 \r
   if ((CpuFeature->CoreAfterFeatureBitMask != NULL) &&\r
-      IsBitMaskMatchCheck (NextCpuFeatureMask, CpuFeature->CoreAfterFeatureBitMask)) {\r
+      IsBitMaskMatchCheck (NextCpuFeatureMask, CpuFeature->CoreAfterFeatureBitMask))\r
+  {\r
     return CoreDepType;\r
   }\r
 \r
   if ((CpuFeature->ThreadAfterFeatureBitMask != NULL) &&\r
-      IsBitMaskMatchCheck (NextCpuFeatureMask, CpuFeature->ThreadAfterFeatureBitMask)) {\r
+      IsBitMaskMatchCheck (NextCpuFeatureMask, CpuFeature->ThreadAfterFeatureBitMask))\r
+  {\r
     return ThreadDepType;\r
   }\r
 \r
@@ -231,24 +238,27 @@ DetectFeatureScope (
 **/\r
 CPU_FEATURE_DEPENDENCE_TYPE\r
 DetectNoneNeighborhoodFeatureScope (\r
-  IN CPU_FEATURES_ENTRY         *CpuFeature,\r
-  IN BOOLEAN                    Before,\r
-  IN LIST_ENTRY                 *FeatureList\r
+  IN CPU_FEATURES_ENTRY  *CpuFeature,\r
+  IN BOOLEAN             Before,\r
+  IN LIST_ENTRY          *FeatureList\r
   )\r
 {\r
   if (Before) {\r
     if ((CpuFeature->PackageBeforeFeatureBitMask != NULL) &&\r
-        FindSpecifyFeature(FeatureList, &CpuFeature->Link, FALSE, CpuFeature->PackageBeforeFeatureBitMask)) {\r
+        FindSpecifyFeature (FeatureList, &CpuFeature->Link, FALSE, CpuFeature->PackageBeforeFeatureBitMask))\r
+    {\r
       return PackageDepType;\r
     }\r
 \r
     if ((CpuFeature->CoreBeforeFeatureBitMask != NULL) &&\r
-        FindSpecifyFeature(FeatureList, &CpuFeature->Link, FALSE, CpuFeature->CoreBeforeFeatureBitMask)) {\r
+        FindSpecifyFeature (FeatureList, &CpuFeature->Link, FALSE, CpuFeature->CoreBeforeFeatureBitMask))\r
+    {\r
       return CoreDepType;\r
     }\r
 \r
     if ((CpuFeature->ThreadBeforeFeatureBitMask != NULL) &&\r
-        FindSpecifyFeature(FeatureList, &CpuFeature->Link, FALSE, CpuFeature->ThreadBeforeFeatureBitMask)) {\r
+        FindSpecifyFeature (FeatureList, &CpuFeature->Link, FALSE, CpuFeature->ThreadBeforeFeatureBitMask))\r
+    {\r
       return ThreadDepType;\r
     }\r
 \r
@@ -256,17 +266,20 @@ DetectNoneNeighborhoodFeatureScope (
   }\r
 \r
   if ((CpuFeature->PackageAfterFeatureBitMask != NULL) &&\r
-      FindSpecifyFeature(FeatureList, &CpuFeature->Link, TRUE, CpuFeature->PackageAfterFeatureBitMask)) {\r
+      FindSpecifyFeature (FeatureList, &CpuFeature->Link, TRUE, CpuFeature->PackageAfterFeatureBitMask))\r
+  {\r
     return PackageDepType;\r
   }\r
 \r
   if ((CpuFeature->CoreAfterFeatureBitMask != NULL) &&\r
-      FindSpecifyFeature(FeatureList, &CpuFeature->Link, TRUE, CpuFeature->CoreAfterFeatureBitMask)) {\r
+      FindSpecifyFeature (FeatureList, &CpuFeature->Link, TRUE, CpuFeature->CoreAfterFeatureBitMask))\r
+  {\r
     return CoreDepType;\r
   }\r
 \r
   if ((CpuFeature->ThreadAfterFeatureBitMask != NULL) &&\r
-      FindSpecifyFeature(FeatureList, &CpuFeature->Link, TRUE, CpuFeature->ThreadAfterFeatureBitMask)) {\r
+      FindSpecifyFeature (FeatureList, &CpuFeature->Link, TRUE, CpuFeature->ThreadAfterFeatureBitMask))\r
+  {\r
     return ThreadDepType;\r
   }\r
 \r
@@ -294,17 +307,17 @@ DetectNoneNeighborhoodFeatureScope (
 **/\r
 BOOLEAN\r
 AdjustFeaturesDependence (\r
-  IN OUT CPU_FEATURES_ENTRY         *PreviousFeature,\r
-  IN OUT CPU_FEATURES_ENTRY         *CurrentFeature,\r
-  IN     CPU_FEATURES_ENTRY         *FindFeature,\r
-  IN     BOOLEAN                    Before\r
+  IN OUT CPU_FEATURES_ENTRY  *PreviousFeature,\r
+  IN OUT CPU_FEATURES_ENTRY  *CurrentFeature,\r
+  IN     CPU_FEATURES_ENTRY  *FindFeature,\r
+  IN     BOOLEAN             Before\r
   )\r
 {\r
-  CPU_FEATURE_DEPENDENCE_TYPE            PreDependType;\r
-  CPU_FEATURE_DEPENDENCE_TYPE            CurrentDependType;\r
+  CPU_FEATURE_DEPENDENCE_TYPE  PreDependType;\r
+  CPU_FEATURE_DEPENDENCE_TYPE  CurrentDependType;\r
 \r
-  PreDependType     = DetectFeatureScope(PreviousFeature, Before, FindFeature->FeatureMask);\r
-  CurrentDependType = DetectFeatureScope(CurrentFeature, Before, FindFeature->FeatureMask);\r
+  PreDependType     = DetectFeatureScope (PreviousFeature, Before, FindFeature->FeatureMask);\r
+  CurrentDependType = DetectFeatureScope (CurrentFeature, Before, FindFeature->FeatureMask);\r
 \r
   //\r
   // If previous feature has no dependence with the find featue.\r
@@ -336,16 +349,16 @@ AdjustFeaturesDependence (
 **/\r
 VOID\r
 AdjustEntry (\r
-  IN      LIST_ENTRY                *FeatureList,\r
-  IN OUT  LIST_ENTRY                *FindEntry,\r
-  IN OUT  LIST_ENTRY                *CurrentEntry,\r
-  IN      BOOLEAN                   Before\r
+  IN      LIST_ENTRY  *FeatureList,\r
+  IN OUT  LIST_ENTRY  *FindEntry,\r
+  IN OUT  LIST_ENTRY  *CurrentEntry,\r
+  IN      BOOLEAN     Before\r
   )\r
 {\r
-  LIST_ENTRY                *PreviousEntry;\r
-  CPU_FEATURES_ENTRY        *PreviousFeature;\r
-  CPU_FEATURES_ENTRY        *CurrentFeature;\r
-  CPU_FEATURES_ENTRY        *FindFeature;\r
+  LIST_ENTRY          *PreviousEntry;\r
+  CPU_FEATURES_ENTRY  *PreviousFeature;\r
+  CPU_FEATURES_ENTRY  *CurrentFeature;\r
+  CPU_FEATURES_ENTRY  *FindFeature;\r
 \r
   //\r
   // For CPU feature which has core or package type dependence, later code need to insert\r
@@ -363,11 +376,10 @@ AdjustEntry (
   if (Before) {\r
     PreviousEntry = GetPreviousNode (FeatureList, FindEntry);\r
   } else {\r
-\r
     PreviousEntry = GetNextNode (FeatureList, FindEntry);\r
   }\r
 \r
-  CurrentFeature  = CPU_FEATURE_ENTRY_FROM_LINK (CurrentEntry);\r
+  CurrentFeature = CPU_FEATURE_ENTRY_FROM_LINK (CurrentEntry);\r
   RemoveEntryList (CurrentEntry);\r
 \r
   if (IsNull (FeatureList, PreviousEntry)) {\r
@@ -407,7 +419,6 @@ AdjustEntry (
   }\r
 }\r
 \r
-\r
 /**\r
   Checks and adjusts current CPU features per dependency relationship.\r
 \r
@@ -419,14 +430,14 @@ AdjustEntry (
 **/\r
 BOOLEAN\r
 InsertToBeforeEntry (\r
-  IN LIST_ENTRY              *FeatureList,\r
-  IN LIST_ENTRY              *CurrentEntry,\r
-  IN UINT8                   *FeatureMask\r
+  IN LIST_ENTRY  *FeatureList,\r
+  IN LIST_ENTRY  *CurrentEntry,\r
+  IN UINT8       *FeatureMask\r
   )\r
 {\r
-  LIST_ENTRY                 *CheckEntry;\r
-  CPU_FEATURES_ENTRY         *CheckFeature;\r
-  BOOLEAN                    Swapped;\r
+  LIST_ENTRY          *CheckEntry;\r
+  CPU_FEATURES_ENTRY  *CheckFeature;\r
+  BOOLEAN             Swapped;\r
 \r
   Swapped = FALSE;\r
 \r
@@ -441,6 +452,7 @@ InsertToBeforeEntry (
       Swapped = TRUE;\r
       break;\r
     }\r
+\r
     CheckEntry = CheckEntry->ForwardLink;\r
   }\r
 \r
@@ -458,14 +470,14 @@ InsertToBeforeEntry (
 **/\r
 BOOLEAN\r
 InsertToAfterEntry (\r
-  IN LIST_ENTRY              *FeatureList,\r
-  IN LIST_ENTRY              *CurrentEntry,\r
-  IN UINT8                   *FeatureMask\r
+  IN LIST_ENTRY  *FeatureList,\r
+  IN LIST_ENTRY  *CurrentEntry,\r
+  IN UINT8       *FeatureMask\r
   )\r
 {\r
-  LIST_ENTRY                 *CheckEntry;\r
-  CPU_FEATURES_ENTRY         *CheckFeature;\r
-  BOOLEAN                    Swapped;\r
+  LIST_ENTRY          *CheckEntry;\r
+  CPU_FEATURES_ENTRY  *CheckFeature;\r
+  BOOLEAN             Swapped;\r
 \r
   Swapped = FALSE;\r
 \r
@@ -480,6 +492,7 @@ InsertToAfterEntry (
       Swapped = TRUE;\r
       break;\r
     }\r
+\r
     CheckEntry = CheckEntry->ForwardLink;\r
   }\r
 \r
@@ -493,22 +506,22 @@ InsertToAfterEntry (
 **/\r
 VOID\r
 CheckCpuFeaturesDependency (\r
-  IN LIST_ENTRY              *FeatureList\r
+  IN LIST_ENTRY  *FeatureList\r
   )\r
 {\r
-  LIST_ENTRY                 *CurrentEntry;\r
-  CPU_FEATURES_ENTRY         *CpuFeature;\r
-  LIST_ENTRY                 *CheckEntry;\r
-  CPU_FEATURES_ENTRY         *CheckFeature;\r
-  BOOLEAN                    Swapped;\r
-  LIST_ENTRY                 *TempEntry;\r
-  LIST_ENTRY                 *NextEntry;\r
+  LIST_ENTRY          *CurrentEntry;\r
+  CPU_FEATURES_ENTRY  *CpuFeature;\r
+  LIST_ENTRY          *CheckEntry;\r
+  CPU_FEATURES_ENTRY  *CheckFeature;\r
+  BOOLEAN             Swapped;\r
+  LIST_ENTRY          *TempEntry;\r
+  LIST_ENTRY          *NextEntry;\r
 \r
   CurrentEntry = GetFirstNode (FeatureList);\r
   while (!IsNull (FeatureList, CurrentEntry)) {\r
-    Swapped = FALSE;\r
+    Swapped    = FALSE;\r
     CpuFeature = CPU_FEATURE_ENTRY_FROM_LINK (CurrentEntry);\r
-    NextEntry = CurrentEntry->ForwardLink;\r
+    NextEntry  = CurrentEntry->ForwardLink;\r
     if (CpuFeature->BeforeAll) {\r
       //\r
       // Check all features dispatched before this entry\r
@@ -526,8 +539,10 @@ CheckCpuFeaturesDependency (
           Swapped = TRUE;\r
           break;\r
         }\r
+\r
         CheckEntry = CheckEntry->ForwardLink;\r
       }\r
+\r
       if (Swapped) {\r
         CurrentEntry = NextEntry;\r
         continue;\r
@@ -550,11 +565,13 @@ CheckCpuFeaturesDependency (
           RemoveEntryList (CurrentEntry);\r
           InsertHeadList (CheckEntry, CurrentEntry);\r
           CurrentEntry = TempEntry;\r
-          Swapped = TRUE;\r
+          Swapped      = TRUE;\r
           break;\r
         }\r
+\r
         CheckEntry = CheckEntry->ForwardLink;\r
       }\r
+\r
       if (Swapped) {\r
         CurrentEntry = NextEntry;\r
         continue;\r
@@ -622,18 +639,18 @@ CheckCpuFeaturesDependency (
 **/\r
 RETURN_STATUS\r
 RegisterCpuFeatureWorker (\r
-  IN CPU_FEATURES_DATA       *CpuFeaturesData,\r
-  IN CPU_FEATURES_ENTRY      *CpuFeature\r
+  IN CPU_FEATURES_DATA   *CpuFeaturesData,\r
+  IN CPU_FEATURES_ENTRY  *CpuFeature\r
   )\r
 {\r
-  EFI_STATUS                 Status;\r
-  CPU_FEATURES_ENTRY         *CpuFeatureEntry;\r
-  LIST_ENTRY                 *Entry;\r
-  BOOLEAN                    FeatureExist;\r
+  EFI_STATUS          Status;\r
+  CPU_FEATURES_ENTRY  *CpuFeatureEntry;\r
+  LIST_ENTRY          *Entry;\r
+  BOOLEAN             FeatureExist;\r
 \r
-  FeatureExist = FALSE;\r
+  FeatureExist    = FALSE;\r
   CpuFeatureEntry = NULL;\r
-  Entry = GetFirstNode (&CpuFeaturesData->FeatureList);\r
+  Entry           = GetFirstNode (&CpuFeaturesData->FeatureList);\r
   while (!IsNull (&CpuFeaturesData->FeatureList, Entry)) {\r
     CpuFeatureEntry = CPU_FEATURE_ENTRY_FROM_LINK (Entry);\r
     if (CompareMem (CpuFeature->FeatureMask, CpuFeatureEntry->FeatureMask, CpuFeaturesData->BitMaskSize) == 0) {\r
@@ -643,6 +660,7 @@ RegisterCpuFeatureWorker (
       FeatureExist = TRUE;\r
       break;\r
     }\r
+\r
     Entry = Entry->ForwardLink;\r
   }\r
 \r
@@ -661,55 +679,71 @@ RegisterCpuFeatureWorker (
     if (CpuFeature->GetConfigDataFunc != NULL) {\r
       CpuFeatureEntry->GetConfigDataFunc = CpuFeature->GetConfigDataFunc;\r
     }\r
+\r
     if (CpuFeature->SupportFunc != NULL) {\r
       CpuFeatureEntry->SupportFunc = CpuFeature->SupportFunc;\r
     }\r
+\r
     if (CpuFeature->InitializeFunc != NULL) {\r
       CpuFeatureEntry->InitializeFunc = CpuFeature->InitializeFunc;\r
     }\r
+\r
     if (CpuFeature->FeatureName != NULL) {\r
       if (CpuFeatureEntry->FeatureName == NULL) {\r
         CpuFeatureEntry->FeatureName = AllocatePool (CPU_FEATURE_NAME_SIZE);\r
         ASSERT (CpuFeatureEntry->FeatureName != NULL);\r
       }\r
+\r
       Status = AsciiStrCpyS (CpuFeatureEntry->FeatureName, CPU_FEATURE_NAME_SIZE, CpuFeature->FeatureName);\r
       ASSERT_EFI_ERROR (Status);\r
       FreePool (CpuFeature->FeatureName);\r
     }\r
+\r
     if (CpuFeature->ThreadBeforeFeatureBitMask != NULL) {\r
       if (CpuFeatureEntry->ThreadBeforeFeatureBitMask != NULL) {\r
         FreePool (CpuFeatureEntry->ThreadBeforeFeatureBitMask);\r
       }\r
+\r
       CpuFeatureEntry->ThreadBeforeFeatureBitMask = CpuFeature->ThreadBeforeFeatureBitMask;\r
     }\r
+\r
     if (CpuFeature->ThreadAfterFeatureBitMask != NULL) {\r
       if (CpuFeatureEntry->ThreadAfterFeatureBitMask != NULL) {\r
         FreePool (CpuFeatureEntry->ThreadAfterFeatureBitMask);\r
       }\r
+\r
       CpuFeatureEntry->ThreadAfterFeatureBitMask = CpuFeature->ThreadAfterFeatureBitMask;\r
     }\r
+\r
     if (CpuFeature->CoreBeforeFeatureBitMask != NULL) {\r
       if (CpuFeatureEntry->CoreBeforeFeatureBitMask != NULL) {\r
         FreePool (CpuFeatureEntry->CoreBeforeFeatureBitMask);\r
       }\r
+\r
       CpuFeatureEntry->CoreBeforeFeatureBitMask = CpuFeature->CoreBeforeFeatureBitMask;\r
     }\r
+\r
     if (CpuFeature->CoreAfterFeatureBitMask != NULL) {\r
       if (CpuFeatureEntry->CoreAfterFeatureBitMask != NULL) {\r
         FreePool (CpuFeatureEntry->CoreAfterFeatureBitMask);\r
       }\r
+\r
       CpuFeatureEntry->CoreAfterFeatureBitMask = CpuFeature->CoreAfterFeatureBitMask;\r
     }\r
+\r
     if (CpuFeature->PackageBeforeFeatureBitMask != NULL) {\r
       if (CpuFeatureEntry->PackageBeforeFeatureBitMask != NULL) {\r
         FreePool (CpuFeatureEntry->PackageBeforeFeatureBitMask);\r
       }\r
+\r
       CpuFeatureEntry->PackageBeforeFeatureBitMask = CpuFeature->PackageBeforeFeatureBitMask;\r
     }\r
+\r
     if (CpuFeature->PackageAfterFeatureBitMask != NULL) {\r
       if (CpuFeatureEntry->PackageAfterFeatureBitMask != NULL) {\r
         FreePool (CpuFeatureEntry->PackageAfterFeatureBitMask);\r
       }\r
+\r
       CpuFeatureEntry->PackageAfterFeatureBitMask = CpuFeature->PackageAfterFeatureBitMask;\r
     }\r
 \r
@@ -719,6 +753,7 @@ RegisterCpuFeatureWorker (
     FreePool (CpuFeature->FeatureMask);\r
     FreePool (CpuFeature);\r
   }\r
+\r
   //\r
   // Verify CPU features dependency can change CPU feature order\r
   //\r
@@ -735,12 +770,12 @@ RegisterCpuFeatureWorker (
 **/\r
 VOID\r
 SetCpuFeaturesBitMask (\r
-  IN UINT8               **FeaturesBitMask,\r
-  IN UINT32              Feature,\r
-  IN UINTN               BitMaskSize\r
+  IN UINT8   **FeaturesBitMask,\r
+  IN UINT32  Feature,\r
+  IN UINTN   BitMaskSize\r
   )\r
 {\r
-  UINT8                  *CpuFeaturesBitMask;\r
+  UINT8  *CpuFeaturesBitMask;\r
 \r
   ASSERT (FeaturesBitMask != NULL);\r
   CpuFeaturesBitMask = *FeaturesBitMask;\r
@@ -751,7 +786,7 @@ SetCpuFeaturesBitMask (
   }\r
 \r
   CpuFeaturesBitMask  += (Feature / 8);\r
-  *CpuFeaturesBitMask |= (UINT8) (1 << (Feature % 8));\r
+  *CpuFeaturesBitMask |= (UINT8)(1 << (Feature % 8));\r
 }\r
 \r
 /**\r
@@ -803,27 +838,27 @@ SetCpuFeaturesBitMask (
 RETURN_STATUS\r
 EFIAPI\r
 RegisterCpuFeature (\r
-  IN CHAR8                             *FeatureName        OPTIONAL,\r
-  IN CPU_FEATURE_GET_CONFIG_DATA       GetConfigDataFunc   OPTIONAL,\r
-  IN CPU_FEATURE_SUPPORT               SupportFunc         OPTIONAL,\r
-  IN CPU_FEATURE_INITIALIZE            InitializeFunc      OPTIONAL,\r
+  IN CHAR8                        *FeatureName        OPTIONAL,\r
+  IN CPU_FEATURE_GET_CONFIG_DATA  GetConfigDataFunc   OPTIONAL,\r
+  IN CPU_FEATURE_SUPPORT          SupportFunc         OPTIONAL,\r
+  IN CPU_FEATURE_INITIALIZE       InitializeFunc      OPTIONAL,\r
   ...\r
   )\r
 {\r
-  EFI_STATUS                 Status;\r
-  VA_LIST                    Marker;\r
-  UINT32                     Feature;\r
-  CPU_FEATURES_ENTRY         *CpuFeature;\r
-  UINT8                      *FeatureMask;\r
-  UINT8                      *ThreadBeforeFeatureBitMask;\r
-  UINT8                      *ThreadAfterFeatureBitMask;\r
-  UINT8                      *CoreBeforeFeatureBitMask;\r
-  UINT8                      *CoreAfterFeatureBitMask;\r
-  UINT8                      *PackageBeforeFeatureBitMask;\r
-  UINT8                      *PackageAfterFeatureBitMask;\r
-  BOOLEAN                    BeforeAll;\r
-  BOOLEAN                    AfterAll;\r
-  CPU_FEATURES_DATA          *CpuFeaturesData;\r
+  EFI_STATUS          Status;\r
+  VA_LIST             Marker;\r
+  UINT32              Feature;\r
+  CPU_FEATURES_ENTRY  *CpuFeature;\r
+  UINT8               *FeatureMask;\r
+  UINT8               *ThreadBeforeFeatureBitMask;\r
+  UINT8               *ThreadAfterFeatureBitMask;\r
+  UINT8               *CoreBeforeFeatureBitMask;\r
+  UINT8               *CoreAfterFeatureBitMask;\r
+  UINT8               *PackageBeforeFeatureBitMask;\r
+  UINT8               *PackageAfterFeatureBitMask;\r
+  BOOLEAN             BeforeAll;\r
+  BOOLEAN             AfterAll;\r
+  CPU_FEATURES_DATA   *CpuFeaturesData;\r
 \r
   FeatureMask                 = NULL;\r
   ThreadBeforeFeatureBitMask  = NULL;\r
@@ -832,8 +867,8 @@ RegisterCpuFeature (
   CoreAfterFeatureBitMask     = NULL;\r
   PackageBeforeFeatureBitMask = NULL;\r
   PackageAfterFeatureBitMask  = NULL;\r
-  BeforeAll            = FALSE;\r
-  AfterAll             = FALSE;\r
+  BeforeAll                   = FALSE;\r
+  AfterAll                    = FALSE;\r
 \r
   CpuFeaturesData = GetCpuFeaturesData ();\r
   if (CpuFeaturesData->FeaturesCount == 0) {\r
@@ -844,7 +879,7 @@ RegisterCpuFeature (
     //\r
     ASSERT (PcdGetSize (PcdCpuFeaturesSetting) == PcdGetSize (PcdCpuFeaturesCapability));\r
     ASSERT (PcdGetSize (PcdCpuFeaturesSetting) == PcdGetSize (PcdCpuFeaturesSupport));\r
-    CpuFeaturesData->BitMaskSize = (UINT32) PcdGetSize (PcdCpuFeaturesSetting);\r
+    CpuFeaturesData->BitMaskSize = (UINT32)PcdGetSize (PcdCpuFeaturesSetting);\r
   }\r
 \r
   VA_START (Marker, InitializeFunc);\r
@@ -853,19 +888,27 @@ RegisterCpuFeature (
     //\r
     // It's invalid to require a feature is before AND after all other features.\r
     //\r
-    ASSERT ((Feature & (CPU_FEATURE_BEFORE_ALL | CPU_FEATURE_AFTER_ALL))\r
-                    != (CPU_FEATURE_BEFORE_ALL | CPU_FEATURE_AFTER_ALL));\r
+    ASSERT (\r
+      (Feature & (CPU_FEATURE_BEFORE_ALL | CPU_FEATURE_AFTER_ALL))\r
+      != (CPU_FEATURE_BEFORE_ALL | CPU_FEATURE_AFTER_ALL)\r
+      );\r
 \r
     //\r
     // It's invalid to require feature A is before AND after before feature B,\r
     // either in thread level, core level or package level.\r
     //\r
-    ASSERT ((Feature & (CPU_FEATURE_THREAD_BEFORE | CPU_FEATURE_THREAD_AFTER))\r
-                    != (CPU_FEATURE_THREAD_BEFORE | CPU_FEATURE_THREAD_AFTER));\r
-    ASSERT ((Feature & (CPU_FEATURE_CORE_BEFORE | CPU_FEATURE_CORE_AFTER))\r
-                    != (CPU_FEATURE_CORE_BEFORE | CPU_FEATURE_CORE_AFTER));\r
-    ASSERT ((Feature & (CPU_FEATURE_PACKAGE_BEFORE | CPU_FEATURE_PACKAGE_AFTER))\r
-                    != (CPU_FEATURE_PACKAGE_BEFORE | CPU_FEATURE_PACKAGE_AFTER));\r
+    ASSERT (\r
+      (Feature & (CPU_FEATURE_THREAD_BEFORE | CPU_FEATURE_THREAD_AFTER))\r
+      != (CPU_FEATURE_THREAD_BEFORE | CPU_FEATURE_THREAD_AFTER)\r
+      );\r
+    ASSERT (\r
+      (Feature & (CPU_FEATURE_CORE_BEFORE | CPU_FEATURE_CORE_AFTER))\r
+      != (CPU_FEATURE_CORE_BEFORE | CPU_FEATURE_CORE_AFTER)\r
+      );\r
+    ASSERT (\r
+      (Feature & (CPU_FEATURE_PACKAGE_BEFORE | CPU_FEATURE_PACKAGE_AFTER))\r
+      != (CPU_FEATURE_PACKAGE_BEFORE | CPU_FEATURE_PACKAGE_AFTER)\r
+      );\r
     if (Feature < CPU_FEATURE_THREAD_BEFORE) {\r
       BeforeAll = ((Feature & CPU_FEATURE_BEFORE_ALL) != 0) ? TRUE : FALSE;\r
       AfterAll  = ((Feature & CPU_FEATURE_AFTER_ALL) != 0) ? TRUE : FALSE;\r
@@ -885,8 +928,10 @@ RegisterCpuFeature (
     } else if ((Feature & CPU_FEATURE_PACKAGE_AFTER) != 0) {\r
       SetCpuFeaturesBitMask (&PackageAfterFeatureBitMask, Feature & ~CPU_FEATURE_PACKAGE_AFTER, CpuFeaturesData->BitMaskSize);\r
     }\r
+\r
     Feature = VA_ARG (Marker, UINT32);\r
   }\r
+\r
   VA_END (Marker);\r
 \r
   CpuFeature = AllocateZeroPool (sizeof (CPU_FEATURES_ENTRY));\r
@@ -905,7 +950,7 @@ RegisterCpuFeature (
   CpuFeature->SupportFunc                 = SupportFunc;\r
   CpuFeature->InitializeFunc              = InitializeFunc;\r
   if (FeatureName != NULL) {\r
-    CpuFeature->FeatureName          = AllocatePool (CPU_FEATURE_NAME_SIZE);\r
+    CpuFeature->FeatureName = AllocatePool (CPU_FEATURE_NAME_SIZE);\r
     ASSERT (CpuFeature->FeatureName != NULL);\r
     Status = AsciiStrCpyS (CpuFeature->FeatureName, CPU_FEATURE_NAME_SIZE, FeatureName);\r
     ASSERT_EFI_ERROR (Status);\r
@@ -927,18 +972,18 @@ GetAcpiCpuData (
   VOID\r
   )\r
 {\r
-  EFI_STATUS                           Status;\r
-  UINTN                                NumberOfCpus;\r
-  UINTN                                NumberOfEnabledProcessors;\r
-  ACPI_CPU_DATA                        *AcpiCpuData;\r
-  UINTN                                TableSize;\r
-  CPU_REGISTER_TABLE                   *RegisterTable;\r
-  UINTN                                Index;\r
-  EFI_PROCESSOR_INFORMATION            ProcessorInfoBuffer;\r
-\r
-  AcpiCpuData = (ACPI_CPU_DATA *) (UINTN) PcdGet64 (PcdCpuS3DataAddress);\r
+  EFI_STATUS                 Status;\r
+  UINTN                      NumberOfCpus;\r
+  UINTN                      NumberOfEnabledProcessors;\r
+  ACPI_CPU_DATA              *AcpiCpuData;\r
+  UINTN                      TableSize;\r
+  CPU_REGISTER_TABLE         *RegisterTable;\r
+  UINTN                      Index;\r
+  EFI_PROCESSOR_INFORMATION  ProcessorInfoBuffer;\r
+\r
+  AcpiCpuData = (ACPI_CPU_DATA *)(UINTN)PcdGet64 (PcdCpuS3DataAddress);\r
   if (AcpiCpuData == NULL) {\r
-    AcpiCpuData  = AllocatePages (EFI_SIZE_TO_PAGES (sizeof (ACPI_CPU_DATA)));\r
+    AcpiCpuData = AllocatePages (EFI_SIZE_TO_PAGES (sizeof (ACPI_CPU_DATA)));\r
     ASSERT (AcpiCpuData != NULL);\r
     ZeroMem (AcpiCpuData, sizeof (ACPI_CPU_DATA));\r
 \r
@@ -952,14 +997,15 @@ GetAcpiCpuData (
     AcpiCpuData->NumberOfCpus = (UINT32)NumberOfCpus;\r
   }\r
 \r
-  if (AcpiCpuData->CpuFeatureInitData.RegisterTable == 0 ||\r
-      AcpiCpuData->CpuFeatureInitData.PreSmmInitRegisterTable == 0) {\r
+  if ((AcpiCpuData->CpuFeatureInitData.RegisterTable == 0) ||\r
+      (AcpiCpuData->CpuFeatureInitData.PreSmmInitRegisterTable == 0))\r
+  {\r
     //\r
     // Allocate buffer for empty RegisterTable and PreSmmInitRegisterTable for all CPUs\r
     //\r
-    NumberOfCpus = AcpiCpuData->NumberOfCpus;\r
-    TableSize = 2 * NumberOfCpus * sizeof (CPU_REGISTER_TABLE);\r
-    RegisterTable  = AllocatePages (EFI_SIZE_TO_PAGES (TableSize));\r
+    NumberOfCpus  = AcpiCpuData->NumberOfCpus;\r
+    TableSize     = 2 * NumberOfCpus * sizeof (CPU_REGISTER_TABLE);\r
+    RegisterTable = AllocatePages (EFI_SIZE_TO_PAGES (TableSize));\r
     ASSERT (RegisterTable != NULL);\r
 \r
     for (Index = 0; Index < NumberOfCpus; Index++) {\r
@@ -976,9 +1022,11 @@ GetAcpiCpuData (
       RegisterTable[NumberOfCpus + Index].AllocatedSize      = 0;\r
       RegisterTable[NumberOfCpus + Index].RegisterTableEntry = 0;\r
     }\r
+\r
     if (AcpiCpuData->CpuFeatureInitData.RegisterTable == 0) {\r
       AcpiCpuData->CpuFeatureInitData.RegisterTable = (EFI_PHYSICAL_ADDRESS)(UINTN)RegisterTable;\r
     }\r
+\r
     if (AcpiCpuData->CpuFeatureInitData.PreSmmInitRegisterTable == 0) {\r
       AcpiCpuData->CpuFeatureInitData.PreSmmInitRegisterTable = (EFI_PHYSICAL_ADDRESS)(UINTN)(RegisterTable + NumberOfCpus);\r
     }\r
@@ -995,14 +1043,14 @@ GetAcpiCpuData (
 STATIC\r
 VOID\r
 EnlargeRegisterTable (\r
-  IN OUT CPU_REGISTER_TABLE            *RegisterTable\r
+  IN OUT CPU_REGISTER_TABLE  *RegisterTable\r
   )\r
 {\r
   EFI_PHYSICAL_ADDRESS  Address;\r
   UINTN                 UsedPages;\r
 \r
   UsedPages = RegisterTable->AllocatedSize / EFI_PAGE_SIZE;\r
-  Address  = (UINTN)AllocatePages (UsedPages + 1);\r
+  Address   = (UINTN)AllocatePages (UsedPages + 1);\r
   ASSERT (Address != 0);\r
 \r
   //\r
@@ -1011,8 +1059,8 @@ EnlargeRegisterTable (
   //\r
   if (RegisterTable->AllocatedSize > 0) {\r
     CopyMem (\r
-      (VOID *) (UINTN) Address,\r
-      (VOID *) (UINTN) RegisterTable->RegisterTableEntry,\r
+      (VOID *)(UINTN)Address,\r
+      (VOID *)(UINTN)RegisterTable->RegisterTableEntry,\r
       RegisterTable->AllocatedSize\r
       );\r
 \r
@@ -1045,27 +1093,27 @@ EnlargeRegisterTable (
 **/\r
 VOID\r
 CpuRegisterTableWriteWorker (\r
-  IN BOOLEAN                 PreSmmFlag,\r
-  IN UINTN                   ProcessorNumber,\r
-  IN REGISTER_TYPE           RegisterType,\r
-  IN UINT64                  Index,\r
-  IN UINT8                   ValidBitStart,\r
-  IN UINT8                   ValidBitLength,\r
-  IN UINT64                  Value,\r
-  IN BOOLEAN                 TestThenWrite\r
+  IN BOOLEAN        PreSmmFlag,\r
+  IN UINTN          ProcessorNumber,\r
+  IN REGISTER_TYPE  RegisterType,\r
+  IN UINT64         Index,\r
+  IN UINT8          ValidBitStart,\r
+  IN UINT8          ValidBitLength,\r
+  IN UINT64         Value,\r
+  IN BOOLEAN        TestThenWrite\r
   )\r
 {\r
-  CPU_FEATURES_DATA        *CpuFeaturesData;\r
-  ACPI_CPU_DATA            *AcpiCpuData;\r
-  CPU_REGISTER_TABLE       *RegisterTable;\r
-  CPU_REGISTER_TABLE_ENTRY *RegisterTableEntry;\r
+  CPU_FEATURES_DATA         *CpuFeaturesData;\r
+  ACPI_CPU_DATA             *AcpiCpuData;\r
+  CPU_REGISTER_TABLE        *RegisterTable;\r
+  CPU_REGISTER_TABLE_ENTRY  *RegisterTableEntry;\r
 \r
   CpuFeaturesData = GetCpuFeaturesData ();\r
   if (CpuFeaturesData->RegisterTable == NULL) {\r
     AcpiCpuData = GetAcpiCpuData ();\r
     ASSERT ((AcpiCpuData != NULL) && (AcpiCpuData->CpuFeatureInitData.RegisterTable != 0));\r
-    CpuFeaturesData->RegisterTable = (CPU_REGISTER_TABLE *) (UINTN) AcpiCpuData->CpuFeatureInitData.RegisterTable;\r
-    CpuFeaturesData->PreSmmRegisterTable = (CPU_REGISTER_TABLE *) (UINTN) AcpiCpuData->CpuFeatureInitData.PreSmmInitRegisterTable;\r
+    CpuFeaturesData->RegisterTable       = (CPU_REGISTER_TABLE *)(UINTN)AcpiCpuData->CpuFeatureInitData.RegisterTable;\r
+    CpuFeaturesData->PreSmmRegisterTable = (CPU_REGISTER_TABLE *)(UINTN)AcpiCpuData->CpuFeatureInitData.PreSmmInitRegisterTable;\r
   }\r
 \r
   if (PreSmmFlag) {\r
@@ -1081,10 +1129,10 @@ CpuRegisterTableWriteWorker (
   //\r
   // Append entry in the register table.\r
   //\r
-  RegisterTableEntry = (CPU_REGISTER_TABLE_ENTRY *) (UINTN) RegisterTable->RegisterTableEntry;\r
+  RegisterTableEntry                                            = (CPU_REGISTER_TABLE_ENTRY *)(UINTN)RegisterTable->RegisterTableEntry;\r
   RegisterTableEntry[RegisterTable->TableLength].RegisterType   = RegisterType;\r
-  RegisterTableEntry[RegisterTable->TableLength].Index          = (UINT32) Index;\r
-  RegisterTableEntry[RegisterTable->TableLength].HighIndex      = (UINT32) RShiftU64 (Index, 32);\r
+  RegisterTableEntry[RegisterTable->TableLength].Index          = (UINT32)Index;\r
+  RegisterTableEntry[RegisterTable->TableLength].HighIndex      = (UINT32)RShiftU64 (Index, 32);\r
   RegisterTableEntry[RegisterTable->TableLength].ValidBitStart  = ValidBitStart;\r
   RegisterTableEntry[RegisterTable->TableLength].ValidBitLength = ValidBitLength;\r
   RegisterTableEntry[RegisterTable->TableLength].Value          = Value;\r
@@ -1110,18 +1158,18 @@ CpuRegisterTableWriteWorker (
 VOID\r
 EFIAPI\r
 CpuRegisterTableWrite (\r
-  IN UINTN               ProcessorNumber,\r
-  IN REGISTER_TYPE       RegisterType,\r
-  IN UINT64              Index,\r
-  IN UINT64              ValueMask,\r
-  IN UINT64              Value\r
+  IN UINTN          ProcessorNumber,\r
+  IN REGISTER_TYPE  RegisterType,\r
+  IN UINT64         Index,\r
+  IN UINT64         ValueMask,\r
+  IN UINT64         Value\r
   )\r
 {\r
-  UINT8                   Start;\r
-  UINT8                   End;\r
-  UINT8                   Length;\r
+  UINT8  Start;\r
+  UINT8  End;\r
+  UINT8  Length;\r
 \r
-  Start  = (UINT8)LowBitSet64  (ValueMask);\r
+  Start  = (UINT8)LowBitSet64 (ValueMask);\r
   End    = (UINT8)HighBitSet64 (ValueMask);\r
   Length = End - Start + 1;\r
   CpuRegisterTableWriteWorker (FALSE, ProcessorNumber, RegisterType, Index, Start, Length, Value, FALSE);\r
@@ -1144,18 +1192,18 @@ CpuRegisterTableWrite (
 VOID\r
 EFIAPI\r
 CpuRegisterTableTestThenWrite (\r
-  IN UINTN               ProcessorNumber,\r
-  IN REGISTER_TYPE       RegisterType,\r
-  IN UINT64              Index,\r
-  IN UINT64              ValueMask,\r
-  IN UINT64              Value\r
+  IN UINTN          ProcessorNumber,\r
+  IN REGISTER_TYPE  RegisterType,\r
+  IN UINT64         Index,\r
+  IN UINT64         ValueMask,\r
+  IN UINT64         Value\r
   )\r
 {\r
-  UINT8                   Start;\r
-  UINT8                   End;\r
-  UINT8                   Length;\r
+  UINT8  Start;\r
+  UINT8  End;\r
+  UINT8  Length;\r
 \r
-  Start  = (UINT8)LowBitSet64  (ValueMask);\r
+  Start  = (UINT8)LowBitSet64 (ValueMask);\r
   End    = (UINT8)HighBitSet64 (ValueMask);\r
   Length = End - Start + 1;\r
   CpuRegisterTableWriteWorker (FALSE, ProcessorNumber, RegisterType, Index, Start, Length, Value, TRUE);\r
@@ -1178,18 +1226,18 @@ CpuRegisterTableTestThenWrite (
 VOID\r
 EFIAPI\r
 PreSmmCpuRegisterTableWrite (\r
-  IN UINTN               ProcessorNumber,\r
-  IN REGISTER_TYPE       RegisterType,\r
-  IN UINT64              Index,\r
-  IN UINT64              ValueMask,\r
-  IN UINT64              Value\r
+  IN UINTN          ProcessorNumber,\r
+  IN REGISTER_TYPE  RegisterType,\r
+  IN UINT64         Index,\r
+  IN UINT64         ValueMask,\r
+  IN UINT64         Value\r
   )\r
 {\r
   UINT8  Start;\r
   UINT8  End;\r
   UINT8  Length;\r
 \r
-  Start  = (UINT8)LowBitSet64  (ValueMask);\r
+  Start  = (UINT8)LowBitSet64 (ValueMask);\r
   End    = (UINT8)HighBitSet64 (ValueMask);\r
   Length = End - Start + 1;\r
   CpuRegisterTableWriteWorker (TRUE, ProcessorNumber, RegisterType, Index, Start, Length, Value, FALSE);\r
@@ -1208,14 +1256,15 @@ PreSmmCpuRegisterTableWrite (
 **/\r
 BOOLEAN\r
 IsCpuFeatureSetInCpuPcd (\r
-  IN UINT8               *CpuBitMask,\r
-  IN UINTN               CpuBitMaskSize,\r
-  IN UINT32              Feature\r
+  IN UINT8   *CpuBitMask,\r
+  IN UINTN   CpuBitMaskSize,\r
+  IN UINT32  Feature\r
   )\r
 {\r
   if ((Feature >> 3) >= CpuBitMaskSize) {\r
     return FALSE;\r
   }\r
+\r
   return ((*(CpuBitMask + (Feature >> 3)) & (1 << (Feature & 0x07))) != 0);\r
 }\r
 \r
@@ -1236,7 +1285,7 @@ IsCpuFeatureSetInCpuPcd (
 BOOLEAN\r
 EFIAPI\r
 IsCpuFeatureSupported (\r
-  IN UINT32              Feature\r
+  IN UINT32  Feature\r
   )\r
 {\r
   return IsCpuFeatureSetInCpuPcd (\r
@@ -1260,7 +1309,7 @@ IsCpuFeatureSupported (
 BOOLEAN\r
 EFIAPI\r
 IsCpuFeatureInSetting (\r
-  IN UINT32              Feature\r
+  IN UINT32  Feature\r
   )\r
 {\r
   return IsCpuFeatureSetInCpuPcd (\r
@@ -1280,11 +1329,11 @@ IsCpuFeatureInSetting (
 VOID\r
 EFIAPI\r
 SwitchBspAfterFeaturesInitialize (\r
-  IN UINTN               ProcessorNumber\r
+  IN UINTN  ProcessorNumber\r
   )\r
 {\r
-  CPU_FEATURES_DATA      *CpuFeaturesData;\r
+  CPU_FEATURES_DATA  *CpuFeaturesData;\r
 \r
-  CpuFeaturesData = GetCpuFeaturesData ();\r
+  CpuFeaturesData            = GetCpuFeaturesData ();\r
   CpuFeaturesData->BspNumber = ProcessorNumber;\r
 }\r

diff --git a/UefiCpuPkg/Library/SecPeiDxeTimerLibUefiCpu/X86TimerLib.c b/UefiCpuPkg/Library/SecPeiDxeTimerLibUefiCpu/X86TimerLib.c
index 8e2a420f80d0380b322976cc6a3c2bc40c5d13e0..e0149df0449ff4f2637135f94d59b644a2c99c83 100644 (file)
--- a/UefiCpuPkg/Library/SecPeiDxeTimerLibUefiCpu/X86TimerLib.c
+++ b/UefiCpuPkg/Library/SecPeiDxeTimerLibUefiCpu/X86TimerLib.c
@@ -27,10 +27,10 @@ InternalX86GetTimerFrequency (
   VOID\r
   )\r
 {\r
-  UINTN Divisor;\r
+  UINTN  Divisor;\r
 \r
   GetApicTimerState (&Divisor, NULL, NULL);\r
-  return PcdGet32(PcdFSBClock) / (UINT32)Divisor;\r
+  return PcdGet32 (PcdFSBClock) / (UINT32)Divisor;\r
 }\r
 \r
 /**\r
@@ -48,13 +48,13 @@ InternalX86GetTimerFrequency (
 VOID\r
 EFIAPI\r
 InternalX86Delay (\r
-  IN      UINT32                    Delay\r
+  IN      UINT32  Delay\r
   )\r
 {\r
-  INT32                             Ticks;\r
-  UINT32                            Times;\r
-  UINT32                            InitCount;\r
-  UINT32                            StartTick;\r
+  INT32   Ticks;\r
+  UINT32  Times;\r
+  UINT32  InitCount;\r
+  UINT32  StartTick;\r
 \r
   //\r
   // In case Delay is too larger, separate it into several small delay slot.\r
@@ -65,13 +65,13 @@ InternalX86Delay (
   //\r
   InitCount = GetApicTimerInitCount ();\r
   ASSERT (InitCount != 0);\r
-  Times     = Delay / (InitCount / 2);\r
-  Delay     = Delay % (InitCount / 2);\r
+  Times = Delay / (InitCount / 2);\r
+  Delay = Delay % (InitCount / 2);\r
 \r
   //\r
   // Get Start Tick and do delay\r
   //\r
-  StartTick  = GetApicTimerCurrentCount ();\r
+  StartTick = GetApicTimerCurrentCount ();\r
   do {\r
     //\r
     // Wait until time out by Delay value\r
@@ -111,7 +111,7 @@ InternalX86Delay (
 UINTN\r
 EFIAPI\r
 MicroSecondDelay (\r
-  IN      UINTN                     MicroSeconds\r
+  IN      UINTN  MicroSeconds\r
   )\r
 {\r
   InternalX86Delay (\r
@@ -139,7 +139,7 @@ MicroSecondDelay (
 UINTN\r
 EFIAPI\r
 NanoSecondDelay (\r
-  IN      UINTN                     NanoSeconds\r
+  IN      UINTN  NanoSeconds\r
   )\r
 {\r
   InternalX86Delay (\r
@@ -200,8 +200,8 @@ GetPerformanceCounter (
 UINT64\r
 EFIAPI\r
 GetPerformanceCounterProperties (\r
-  OUT      UINT64                    *StartValue   OPTIONAL,\r
-  OUT      UINT64                    *EndValue     OPTIONAL\r
+  OUT      UINT64  *StartValue   OPTIONAL,\r
+  OUT      UINT64  *EndValue     OPTIONAL\r
   )\r
 {\r
   if (StartValue != NULL) {\r
@@ -212,7 +212,7 @@ GetPerformanceCounterProperties (
     *EndValue = 0;\r
   }\r
 \r
-  return (UINT64) InternalX86GetTimerFrequency ();\r
+  return (UINT64)InternalX86GetTimerFrequency ();\r
 }\r
 \r
 /**\r
@@ -229,7 +229,7 @@ GetPerformanceCounterProperties (
 UINT64\r
 EFIAPI\r
 GetTimeInNanoSecond (\r
-  IN      UINT64                     Ticks\r
+  IN      UINT64  Ticks\r
   )\r
 {\r
   UINT64  Frequency;\r
@@ -251,9 +251,9 @@ GetTimeInNanoSecond (
   // Since 2^29 < 1,000,000,000 = 0x3B9ACA00 < 2^30, Remainder should < 2^(64-30) = 2^34,\r
   // i.e. highest bit set in Remainder should <= 33.\r
   //\r
-  Shift = MAX (0, HighBitSet64 (Remainder) - 33);\r
-  Remainder = RShiftU64 (Remainder, (UINTN) Shift);\r
-  Frequency = RShiftU64 (Frequency, (UINTN) Shift);\r
+  Shift        = MAX (0, HighBitSet64 (Remainder) - 33);\r
+  Remainder    = RShiftU64 (Remainder, (UINTN)Shift);\r
+  Frequency    = RShiftU64 (Frequency, (UINTN)Shift);\r
   NanoSeconds += DivU64x64Remainder (MultU64x32 (Remainder, 1000000000u), Frequency, NULL);\r
 \r
   return NanoSeconds;\r

diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmmStmSupport.c b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmmStmSupport.c
index 24bd6d0a946d000700878bc93615cca2d47c870d..249cd40f9ddbdc08a3e4039ebe147fa40f40ad6b 100644 (file)
--- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmmStmSupport.c
+++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmmStmSupport.c
@@ -14,9 +14,9 @@
 ///\r
 /// Page Table Entry\r
 ///\r
-#define IA32_PG_P                   BIT0\r
-#define IA32_PG_RW                  BIT1\r
-#define IA32_PG_PS                  BIT7\r
+#define IA32_PG_P   BIT0\r
+#define IA32_PG_RW  BIT1\r
+#define IA32_PG_PS  BIT7\r
 \r
 /**\r
 \r
@@ -28,14 +28,14 @@
 **/\r
 VOID\r
 StmGen4GPageTable (\r
-  IN UINTN              PageTableBase\r
+  IN UINTN  PageTableBase\r
   )\r
 {\r
-  UINTN                             Index;\r
-  UINT32                            *Pte;\r
-  UINT32                            Address;\r
+  UINTN   Index;\r
+  UINT32  *Pte;\r
+  UINT32  Address;\r
 \r
-  Pte = (UINT32*)(UINTN)PageTableBase;\r
+  Pte = (UINT32 *)(UINTN)PageTableBase;\r
 \r
   Address = 0;\r
   for (Index = 0; Index < SIZE_4KB / sizeof (*Pte); Index++) {\r
@@ -63,7 +63,7 @@ StmGen4GPageTable (
 UINT32\r
 EFIAPI\r
 SmmStmExceptionHandler (\r
-  IN OUT STM_PROTECTION_EXCEPTION_STACK_FRAME Context\r
+  IN OUT STM_PROTECTION_EXCEPTION_STACK_FRAME  Context\r
   )\r
 {\r
   // TBD - SmmStmExceptionHandler, record information\r

diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibCommon.c b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibCommon.c
index fa3a866ab6f672d3cdd0de656e6082b62ff2c27e..78de7f8407bd241c97b0be6398da54590a3d0f21 100644 (file)
--- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibCommon.c
+++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibCommon.c
@@ -34,8 +34,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
 //\r
 // MSRs required for configuration of SMM Code Access Check\r
 //\r
-#define SMM_FEATURES_LIB_IA32_MCA_CAP              0x17D\r
-#define   SMM_CODE_ACCESS_CHK_BIT                  BIT58\r
+#define SMM_FEATURES_LIB_IA32_MCA_CAP  0x17D\r
+#define   SMM_CODE_ACCESS_CHK_BIT      BIT58\r
 \r
 //\r
 // Set default value to assume SMRR is not supported\r
@@ -86,7 +86,7 @@ CpuFeaturesLibInitialization (
   AsmCpuid (CPUID_VERSION_INFO, &RegEax, NULL, NULL, &RegEdx);\r
   FamilyId = (RegEax >> 8) & 0xf;\r
   ModelId  = (RegEax >> 4) & 0xf;\r
-  if (FamilyId == 0x06 || FamilyId == 0x0f) {\r
+  if ((FamilyId == 0x06) || (FamilyId == 0x0f)) {\r
     ModelId = ModelId | ((RegEax >> 12) & 0xf0);\r
   }\r
 \r
@@ -110,7 +110,7 @@ CpuFeaturesLibInitialization (
   // SMRR Physical Base and SMM Physical Mask MSRs are not available.\r
   //\r
   if (FamilyId == 0x06) {\r
-    if (ModelId == 0x1C || ModelId == 0x26 || ModelId == 0x27 || ModelId == 0x35 || ModelId == 0x36) {\r
+    if ((ModelId == 0x1C) || (ModelId == 0x26) || (ModelId == 0x27) || (ModelId == 0x35) || (ModelId == 0x36)) {\r
       mSmrrSupported = FALSE;\r
     }\r
   }\r
@@ -123,7 +123,7 @@ CpuFeaturesLibInitialization (
   // Processor Family MSRs\r
   //\r
   if (FamilyId == 0x06) {\r
-    if (ModelId == 0x17 || ModelId == 0x0f) {\r
+    if ((ModelId == 0x17) || (ModelId == 0x0f)) {\r
       mSmrrPhysBaseMsr = SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSBASE;\r
       mSmrrPhysMaskMsr = SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSMASK;\r
     }\r
@@ -204,7 +204,7 @@ SmmCpuFeaturesInitializeProcessor (
   //\r
   // Configure SMBASE.\r
   //\r
-  CpuState = (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET);\r
+  CpuState             = (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET);\r
   CpuState->x86.SMBASE = (UINT32)CpuHotPlugData->SmBase[CpuIndex];\r
 \r
   //\r
@@ -216,7 +216,7 @@ SmmCpuFeaturesInitializeProcessor (
   // accessing SMRR base/mask MSRs.  If Lock(BIT0) of MSR_FEATURE_CONTROL MSR(0x3A)\r
   // is set, then the MSR is locked and can not be modified.\r
   //\r
-  if (mSmrrSupported && mSmrrPhysBaseMsr == SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSBASE) {\r
+  if (mSmrrSupported && (mSmrrPhysBaseMsr == SMM_FEATURES_LIB_IA32_CORE_SMRR_PHYSBASE)) {\r
     FeatureControl = AsmReadMsr64 (SMM_FEATURES_LIB_IA32_FEATURE_CONTROL);\r
     if ((FeatureControl & BIT3) == 0) {\r
       if ((FeatureControl & BIT0) == 0) {\r
@@ -242,7 +242,8 @@ SmmCpuFeaturesInitializeProcessor (
     //\r
     if ((CpuHotPlugData->SmrrSize < SIZE_4KB) ||\r
         (CpuHotPlugData->SmrrSize != GetPowerOfTwo32 (CpuHotPlugData->SmrrSize)) ||\r
-        ((CpuHotPlugData->SmrrBase & ~(CpuHotPlugData->SmrrSize - 1)) != CpuHotPlugData->SmrrBase)) {\r
+        ((CpuHotPlugData->SmrrBase & ~(CpuHotPlugData->SmrrSize - 1)) != CpuHotPlugData->SmrrBase))\r
+    {\r
       //\r
       // Print message and halt if CPU is Monarch\r
       //\r
@@ -263,7 +264,7 @@ SmmCpuFeaturesInitializeProcessor (
   AsmCpuid (CPUID_VERSION_INFO, &RegEax, NULL, NULL, &RegEdx);\r
   FamilyId = (RegEax >> 8) & 0xf;\r
   ModelId  = (RegEax >> 4) & 0xf;\r
-  if (FamilyId == 0x06 || FamilyId == 0x0f) {\r
+  if ((FamilyId == 0x06) || (FamilyId == 0x0f)) {\r
     ModelId = ModelId | ((RegEax >> 12) & 0xf0);\r
   }\r
 \r
@@ -276,10 +277,11 @@ SmmCpuFeaturesInitializeProcessor (
   // Intel(R) Core(TM) Processor Family MSRs.\r
   //\r
   if (FamilyId == 0x06) {\r
-    if (ModelId == 0x3C || ModelId == 0x45 || ModelId == 0x46 ||\r
-        ModelId == 0x3D || ModelId == 0x47 || ModelId == 0x4E || ModelId == 0x4F ||\r
-        ModelId == 0x3F || ModelId == 0x56 || ModelId == 0x57 || ModelId == 0x5C ||\r
-        ModelId == 0x8C) {\r
+    if ((ModelId == 0x3C) || (ModelId == 0x45) || (ModelId == 0x46) ||\r
+        (ModelId == 0x3D) || (ModelId == 0x47) || (ModelId == 0x4E) || (ModelId == 0x4F) ||\r
+        (ModelId == 0x3F) || (ModelId == 0x56) || (ModelId == 0x57) || (ModelId == 0x5C) ||\r
+        (ModelId == 0x8C))\r
+    {\r
       //\r
       // Check to see if the CPU supports the SMM Code Access Check feature\r
       // Do not access this MSR unless the CPU supports the SmmRegFeatureControl\r
@@ -382,7 +384,7 @@ SmmCpuFeaturesDisableSmrr (
   )\r
 {\r
   if (mSmrrSupported && mNeedConfigureMtrrs) {\r
-    AsmWriteMsr64 (mSmrrPhysMaskMsr, AsmReadMsr64(mSmrrPhysMaskMsr) & ~EFI_MSR_SMRR_PHYS_MASK_VALID);\r
+    AsmWriteMsr64 (mSmrrPhysMaskMsr, AsmReadMsr64 (mSmrrPhysMaskMsr) & ~EFI_MSR_SMRR_PHYS_MASK_VALID);\r
   }\r
 }\r
 \r
@@ -397,7 +399,7 @@ SmmCpuFeaturesReenableSmrr (
   )\r
 {\r
   if (mSmrrSupported && mNeedConfigureMtrrs) {\r
-    AsmWriteMsr64 (mSmrrPhysMaskMsr, AsmReadMsr64(mSmrrPhysMaskMsr) | EFI_MSR_SMRR_PHYS_MASK_VALID);\r
+    AsmWriteMsr64 (mSmrrPhysMaskMsr, AsmReadMsr64 (mSmrrPhysMaskMsr) | EFI_MSR_SMRR_PHYS_MASK_VALID);\r
   }\r
 }\r
 \r
@@ -458,9 +460,10 @@ SmmCpuFeaturesIsSmmRegisterSupported (
   IN SMM_REG_NAME  RegName\r
   )\r
 {\r
-  if (mSmmFeatureControlSupported && RegName == SmmRegFeatureControl) {\r
+  if (mSmmFeatureControlSupported && (RegName == SmmRegFeatureControl)) {\r
     return TRUE;\r
   }\r
+\r
   return FALSE;\r
 }\r
 \r
@@ -483,9 +486,10 @@ SmmCpuFeaturesGetSmmRegister (
   IN SMM_REG_NAME  RegName\r
   )\r
 {\r
-  if (mSmmFeatureControlSupported && RegName == SmmRegFeatureControl) {\r
+  if (mSmmFeatureControlSupported && (RegName == SmmRegFeatureControl)) {\r
     return AsmReadMsr64 (SMM_FEATURES_LIB_SMM_FEATURE_CONTROL);\r
   }\r
+\r
   return 0;\r
 }\r
 \r
@@ -508,7 +512,7 @@ SmmCpuFeaturesSetSmmRegister (
   IN UINT64        Value\r
   )\r
 {\r
-  if (mSmmFeatureControlSupported && RegName == SmmRegFeatureControl) {\r
+  if (mSmmFeatureControlSupported && (RegName == SmmRegFeatureControl)) {\r
     AsmWriteMsr64 (SMM_FEATURES_LIB_SMM_FEATURE_CONTROL, Value);\r
   }\r
 }\r
@@ -605,9 +609,8 @@ SmmCpuFeaturesCompleteSmmReadyToLock (
 VOID *\r
 EFIAPI\r
 SmmCpuFeaturesAllocatePageTableMemory (\r
-  IN UINTN           Pages\r
+  IN UINTN  Pages\r
   )\r
 {\r
   return NULL;\r
 }\r
-\r

diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c
index c92387625ddc6da2b669bfd8734b4452c5d81679..4e8f897f5e9cf7a00a6a502354a4a554fb9489aa 100644 (file)
--- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c
+++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c
@@ -24,21 +24,21 @@
 #include "CpuFeaturesLib.h"\r
 #include "SmmStm.h"\r
 \r
-#define TXT_EVTYPE_BASE                  0x400\r
-#define TXT_EVTYPE_STM_HASH              (TXT_EVTYPE_BASE + 14)\r
+#define TXT_EVTYPE_BASE      0x400\r
+#define TXT_EVTYPE_STM_HASH  (TXT_EVTYPE_BASE + 14)\r
 \r
-#define RDWR_ACCS             3\r
-#define FULL_ACCS             7\r
+#define RDWR_ACCS  3\r
+#define FULL_ACCS  7\r
 \r
 EFI_HANDLE  mStmSmmCpuHandle = NULL;\r
 \r
-BOOLEAN mLockLoadMonitor = FALSE;\r
+BOOLEAN  mLockLoadMonitor = FALSE;\r
 \r
 //\r
 // Template of STM_RSC_END structure for copying.\r
 //\r
-GLOBAL_REMOVE_IF_UNREFERENCED STM_RSC_END mRscEndNode = {\r
-  {END_OF_RESOURCES, sizeof (STM_RSC_END)},\r
+GLOBAL_REMOVE_IF_UNREFERENCED STM_RSC_END  mRscEndNode = {\r
+  { END_OF_RESOURCES, sizeof (STM_RSC_END) },\r
 };\r
 \r
 GLOBAL_REMOVE_IF_UNREFERENCED UINT8  *mStmResourcesPtr         = NULL;\r
@@ -52,7 +52,7 @@ GLOBAL_REMOVE_IF_UNREFERENCED UINT32  mStmState = 0;
 // System Configuration Table pointing to STM Configuration Table\r
 //\r
 GLOBAL_REMOVE_IF_UNREFERENCED\r
-EFI_SM_MONITOR_INIT_PROTOCOL mSmMonitorInitProtocol = {\r
+EFI_SM_MONITOR_INIT_PROTOCOL  mSmMonitorInitProtocol = {\r
   LoadMonitor,\r
   AddPiResource,\r
   DeletePiResource,\r
@@ -60,10 +60,7 @@ EFI_SM_MONITOR_INIT_PROTOCOL mSmMonitorInitProtocol = {
   GetMonitorState,\r
 };\r
 \r
-\r
-\r
-\r
-#define   CPUID1_EDX_XD_SUPPORT      0x100000\r
+#define   CPUID1_EDX_XD_SUPPORT  0x100000\r
 \r
 //\r
 // External global variables associated with SMI Handler Template\r
@@ -146,10 +143,10 @@ SmmCpuFeaturesLibStmConstructor (
       //\r
       // Retrieve MSEG location from MSEG SRAM HOB\r
       //\r
-      SmramDescriptor = (EFI_SMRAM_DESCRIPTOR *) GET_GUID_HOB_DATA (GuidHob);\r
+      SmramDescriptor = (EFI_SMRAM_DESCRIPTOR *)GET_GUID_HOB_DATA (GuidHob);\r
       if (SmramDescriptor->PhysicalSize > 0) {\r
-        mMsegBase       = (UINTN)SmramDescriptor->CpuStart;\r
-        mMsegSize       = (UINTN)SmramDescriptor->PhysicalSize;\r
+        mMsegBase = (UINTN)SmramDescriptor->CpuStart;\r
+        mMsegSize = (UINTN)SmramDescriptor->PhysicalSize;\r
       }\r
     } else if (PcdGet32 (PcdCpuMsegSize) > 0) {\r
       //\r
@@ -162,6 +159,7 @@ SmmCpuFeaturesLibStmConstructor (
         DEBUG ((DEBUG_ERROR, "Not enough SMRAM resource to allocate MSEG size %08x\n", PcdGet32 (PcdCpuMsegSize)));\r
       }\r
     }\r
+\r
     if (mMsegBase > 0) {\r
       DEBUG ((DEBUG_INFO, "MsegBase: 0x%08x, MsegSize: 0x%08x\n", mMsegBase, mMsegSize));\r
     }\r
@@ -251,16 +249,16 @@ SmmCpuFeaturesInstallSmiHandler (
   IN UINT32  Cr3\r
   )\r
 {\r
-  EFI_STATUS                     Status;\r
-  TXT_PROCESSOR_SMM_DESCRIPTOR   *Psd;\r
-  VOID                           *Hob;\r
-  UINT32                         RegEax;\r
-  UINT32                         RegEdx;\r
-  EFI_PROCESSOR_INFORMATION      ProcessorInfo;\r
+  EFI_STATUS                    Status;\r
+  TXT_PROCESSOR_SMM_DESCRIPTOR  *Psd;\r
+  VOID                          *Hob;\r
+  UINT32                        RegEax;\r
+  UINT32                        RegEdx;\r
+  EFI_PROCESSOR_INFORMATION     ProcessorInfo;\r
 \r
   CopyMem ((VOID *)((UINTN)SmBase + TXT_SMM_PSD_OFFSET), &gcStmPsd, sizeof (gcStmPsd));\r
-  Psd = (TXT_PROCESSOR_SMM_DESCRIPTOR *)(VOID *)((UINTN)SmBase + TXT_SMM_PSD_OFFSET);\r
-  Psd->SmmGdtPtr = GdtBase;\r
+  Psd             = (TXT_PROCESSOR_SMM_DESCRIPTOR *)(VOID *)((UINTN)SmBase + TXT_SMM_PSD_OFFSET);\r
+  Psd->SmmGdtPtr  = GdtBase;\r
   Psd->SmmGdtSize = (UINT32)GdtSize;\r
 \r
   //\r
@@ -293,49 +291,49 @@ SmmCpuFeaturesInstallSmiHandler (
   //\r
   // Set the value at the top of the CPU stack to the CPU Index\r
   //\r
-  *(UINTN*)(UINTN)gStmSmiStack = CpuIndex;\r
+  *(UINTN *)(UINTN)gStmSmiStack = CpuIndex;\r
 \r
   //\r
   // Copy template to CPU specific SMI handler location\r
   //\r
   CopyMem (\r
-    (VOID*)((UINTN)SmBase + SMM_HANDLER_OFFSET),\r
-    (VOID*)gcStmSmiHandlerTemplate,\r
+    (VOID *)((UINTN)SmBase + SMM_HANDLER_OFFSET),\r
+    (VOID *)gcStmSmiHandlerTemplate,\r
     gcStmSmiHandlerSize\r
     );\r
 \r
   Psd->SmmSmiHandlerRip = SmBase + SMM_HANDLER_OFFSET + gcStmSmiHandlerOffset;\r
-  Psd->SmmSmiHandlerRsp = (UINTN)SmiStack + StackSize - sizeof(UINTN);\r
+  Psd->SmmSmiHandlerRsp = (UINTN)SmiStack + StackSize - sizeof (UINTN);\r
   Psd->SmmCr3           = Cr3;\r
 \r
-  DEBUG((DEBUG_INFO, "CpuSmmStmExceptionStackSize - %x\n", PcdGet32(PcdCpuSmmStmExceptionStackSize)));\r
-  DEBUG((DEBUG_INFO, "Pages - %x\n", EFI_SIZE_TO_PAGES(PcdGet32(PcdCpuSmmStmExceptionStackSize))));\r
-  Psd->StmProtectionExceptionHandler.SpeRsp = (UINT64)(UINTN)AllocatePages (EFI_SIZE_TO_PAGES (PcdGet32 (PcdCpuSmmStmExceptionStackSize)));\r
+  DEBUG ((DEBUG_INFO, "CpuSmmStmExceptionStackSize - %x\n", PcdGet32 (PcdCpuSmmStmExceptionStackSize)));\r
+  DEBUG ((DEBUG_INFO, "Pages - %x\n", EFI_SIZE_TO_PAGES (PcdGet32 (PcdCpuSmmStmExceptionStackSize))));\r
+  Psd->StmProtectionExceptionHandler.SpeRsp  = (UINT64)(UINTN)AllocatePages (EFI_SIZE_TO_PAGES (PcdGet32 (PcdCpuSmmStmExceptionStackSize)));\r
   Psd->StmProtectionExceptionHandler.SpeRsp += EFI_PAGES_TO_SIZE (EFI_SIZE_TO_PAGES (PcdGet32 (PcdCpuSmmStmExceptionStackSize)));\r
 \r
-  Psd->BiosHwResourceRequirementsPtr        = (UINT64)(UINTN)GetStmResource ();\r
+  Psd->BiosHwResourceRequirementsPtr = (UINT64)(UINTN)GetStmResource ();\r
 \r
   //\r
   // Get the APIC ID for the CPU specified by CpuIndex\r
   //\r
   Status = mSmmCpuFeaturesLibMpService->GetProcessorInfo (\r
-             mSmmCpuFeaturesLibMpService,\r
-             CpuIndex,\r
-             &ProcessorInfo\r
-             );\r
+                                          mSmmCpuFeaturesLibMpService,\r
+                                          CpuIndex,\r
+                                          &ProcessorInfo\r
+                                          );\r
   ASSERT_EFI_ERROR (Status);\r
 \r
   Psd->LocalApicId = (UINT32)ProcessorInfo.ProcessorId;\r
-  Psd->AcpiRsdp = 0;\r
+  Psd->AcpiRsdp    = 0;\r
 \r
   Hob = GetFirstHob (EFI_HOB_TYPE_CPU);\r
   if (Hob != NULL) {\r
-    Psd->PhysicalAddressBits = ((EFI_HOB_CPU *) Hob)->SizeOfMemorySpace;\r
+    Psd->PhysicalAddressBits = ((EFI_HOB_CPU *)Hob)->SizeOfMemorySpace;\r
   } else {\r
     AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);\r
     if (RegEax >= 0x80000008) {\r
       AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);\r
-      Psd->PhysicalAddressBits = (UINT8) RegEax;\r
+      Psd->PhysicalAddressBits = (UINT8)RegEax;\r
     } else {\r
       Psd->PhysicalAddressBits = 36;\r
     }\r
@@ -385,6 +383,7 @@ SmmEndOfDxeEventNotify (
       break;\r
     }\r
   }\r
+\r
   if (Rsdp == NULL) {\r
     for (Index = 0; Index < gST->NumberOfTableEntries; Index++) {\r
       if (CompareGuid (&(gST->ConfigurationTable[Index].VendorGuid), &gEfiAcpi10TableGuid)) {\r
@@ -416,8 +415,8 @@ StmSmmConfigurationTableInit (
   VOID\r
   )\r
 {\r
-  EFI_STATUS    Status;\r
-    VOID        *Registration;\r
+  EFI_STATUS  Status;\r
+  VOID        *Registration;\r
 \r
   Status = gSmst->SmmInstallProtocolInterface (\r
                     &mStmSmmCpuHandle,\r
@@ -468,19 +467,19 @@ GetMonitorState (
 **/\r
 BOOLEAN\r
 HandleSingleResource (\r
-  IN  STM_RSC      *Resource,\r
-  IN  STM_RSC      *Record\r
+  IN  STM_RSC  *Resource,\r
+  IN  STM_RSC  *Record\r
   )\r
 {\r
-  UINT64      ResourceLo;\r
-  UINT64      ResourceHi;\r
-  UINT64      RecordLo;\r
-  UINT64      RecordHi;\r
+  UINT64  ResourceLo;\r
+  UINT64  ResourceHi;\r
+  UINT64  RecordLo;\r
+  UINT64  RecordHi;\r
 \r
   ResourceLo = 0;\r
   ResourceHi = 0;\r
-  RecordLo = 0;\r
-  RecordHi = 0;\r
+  RecordLo   = 0;\r
+  RecordHi   = 0;\r
 \r
   //\r
   // Calling code is responsible for making sure that\r
@@ -488,62 +487,69 @@ HandleSingleResource (
   // thus we use just one of them as switch variable.\r
   //\r
   switch (Resource->Header.RscType) {\r
-  case MEM_RANGE:\r
-  case MMIO_RANGE:\r
-    ResourceLo = Resource->Mem.Base;\r
-    ResourceHi = Resource->Mem.Base + Resource->Mem.Length;\r
-    RecordLo = Record->Mem.Base;\r
-    RecordHi = Record->Mem.Base + Record->Mem.Length;\r
-    if (Resource->Mem.RWXAttributes != Record->Mem.RWXAttributes) {\r
-      if ((ResourceLo == RecordLo) && (ResourceHi == RecordHi)) {\r
-        Record->Mem.RWXAttributes = Resource->Mem.RWXAttributes | Record->Mem.RWXAttributes;\r
-        return TRUE;\r
-      } else {\r
+    case MEM_RANGE:\r
+    case MMIO_RANGE:\r
+      ResourceLo = Resource->Mem.Base;\r
+      ResourceHi = Resource->Mem.Base + Resource->Mem.Length;\r
+      RecordLo   = Record->Mem.Base;\r
+      RecordHi   = Record->Mem.Base + Record->Mem.Length;\r
+      if (Resource->Mem.RWXAttributes != Record->Mem.RWXAttributes) {\r
+        if ((ResourceLo == RecordLo) && (ResourceHi == RecordHi)) {\r
+          Record->Mem.RWXAttributes = Resource->Mem.RWXAttributes | Record->Mem.RWXAttributes;\r
+          return TRUE;\r
+        } else {\r
+          return FALSE;\r
+        }\r
+      }\r
+\r
+      break;\r
+    case IO_RANGE:\r
+    case TRAPPED_IO_RANGE:\r
+      ResourceLo = (UINT64)Resource->Io.Base;\r
+      ResourceHi = (UINT64)Resource->Io.Base + (UINT64)Resource->Io.Length;\r
+      RecordLo   = (UINT64)Record->Io.Base;\r
+      RecordHi   = (UINT64)Record->Io.Base + (UINT64)Record->Io.Length;\r
+      break;\r
+    case PCI_CFG_RANGE:\r
+      if ((Resource->PciCfg.OriginatingBusNumber != Record->PciCfg.OriginatingBusNumber) ||\r
+          (Resource->PciCfg.LastNodeIndex != Record->PciCfg.LastNodeIndex))\r
+      {\r
         return FALSE;\r
       }\r
-    }\r
-    break;\r
-  case IO_RANGE:\r
-  case TRAPPED_IO_RANGE:\r
-    ResourceLo = (UINT64) Resource->Io.Base;\r
-    ResourceHi = (UINT64) Resource->Io.Base + (UINT64) Resource->Io.Length;\r
-    RecordLo = (UINT64) Record->Io.Base;\r
-    RecordHi = (UINT64) Record->Io.Base + (UINT64) Record->Io.Length;\r
-    break;\r
-  case PCI_CFG_RANGE:\r
-    if ((Resource->PciCfg.OriginatingBusNumber != Record->PciCfg.OriginatingBusNumber) ||\r
-        (Resource->PciCfg.LastNodeIndex != Record->PciCfg.LastNodeIndex)) {\r
-      return FALSE;\r
-    }\r
-    if (CompareMem (Resource->PciCfg.PciDevicePath, Record->PciCfg.PciDevicePath, sizeof(STM_PCI_DEVICE_PATH_NODE) * (Resource->PciCfg.LastNodeIndex + 1)) != 0) {\r
-      return FALSE;\r
-    }\r
-    ResourceLo = (UINT64) Resource->PciCfg.Base;\r
-    ResourceHi = (UINT64) Resource->PciCfg.Base + (UINT64) Resource->PciCfg.Length;\r
-    RecordLo = (UINT64) Record->PciCfg.Base;\r
-    RecordHi = (UINT64) Record->PciCfg.Base + (UINT64) Record->PciCfg.Length;\r
-    if (Resource->PciCfg.RWAttributes != Record->PciCfg.RWAttributes) {\r
-      if ((ResourceLo == RecordLo) && (ResourceHi == RecordHi)) {\r
-        Record->PciCfg.RWAttributes = Resource->PciCfg.RWAttributes | Record->PciCfg.RWAttributes;\r
-        return TRUE;\r
-      } else {\r
+\r
+      if (CompareMem (Resource->PciCfg.PciDevicePath, Record->PciCfg.PciDevicePath, sizeof (STM_PCI_DEVICE_PATH_NODE) * (Resource->PciCfg.LastNodeIndex + 1)) != 0) {\r
         return FALSE;\r
       }\r
-    }\r
-    break;\r
-  case MACHINE_SPECIFIC_REG:\r
-    //\r
-    // Special case - merge MSR masks in place.\r
-    //\r
-    if (Resource->Msr.MsrIndex != Record->Msr.MsrIndex) {\r
+\r
+      ResourceLo = (UINT64)Resource->PciCfg.Base;\r
+      ResourceHi = (UINT64)Resource->PciCfg.Base + (UINT64)Resource->PciCfg.Length;\r
+      RecordLo   = (UINT64)Record->PciCfg.Base;\r
+      RecordHi   = (UINT64)Record->PciCfg.Base + (UINT64)Record->PciCfg.Length;\r
+      if (Resource->PciCfg.RWAttributes != Record->PciCfg.RWAttributes) {\r
+        if ((ResourceLo == RecordLo) && (ResourceHi == RecordHi)) {\r
+          Record->PciCfg.RWAttributes = Resource->PciCfg.RWAttributes | Record->PciCfg.RWAttributes;\r
+          return TRUE;\r
+        } else {\r
+          return FALSE;\r
+        }\r
+      }\r
+\r
+      break;\r
+    case MACHINE_SPECIFIC_REG:\r
+      //\r
+      // Special case - merge MSR masks in place.\r
+      //\r
+      if (Resource->Msr.MsrIndex != Record->Msr.MsrIndex) {\r
+        return FALSE;\r
+      }\r
+\r
+      Record->Msr.ReadMask  |= Resource->Msr.ReadMask;\r
+      Record->Msr.WriteMask |= Resource->Msr.WriteMask;\r
+      return TRUE;\r
+    default:\r
       return FALSE;\r
-    }\r
-    Record->Msr.ReadMask |= Resource->Msr.ReadMask;\r
-    Record->Msr.WriteMask |= Resource->Msr.WriteMask;\r
-    return TRUE;\r
-  default:\r
-    return FALSE;\r
   }\r
+\r
   //\r
   // If resources are disjoint\r
   //\r
@@ -557,6 +563,7 @@ HandleSingleResource (
   if ((ResourceLo >= RecordLo) && (ResourceHi <= RecordHi)) {\r
     return TRUE;\r
   }\r
+\r
   //\r
   // Resources are overlapping.\r
   // Resource and record are merged.\r
@@ -565,22 +572,22 @@ HandleSingleResource (
   ResourceHi = (ResourceHi > RecordHi) ? ResourceHi : RecordHi;\r
 \r
   switch (Resource->Header.RscType) {\r
-  case MEM_RANGE:\r
-  case MMIO_RANGE:\r
-    Record->Mem.Base = ResourceLo;\r
-    Record->Mem.Length = ResourceHi - ResourceLo;\r
-    break;\r
-  case IO_RANGE:\r
-  case TRAPPED_IO_RANGE:\r
-    Record->Io.Base = (UINT16) ResourceLo;\r
-    Record->Io.Length = (UINT16) (ResourceHi - ResourceLo);\r
-    break;\r
-  case PCI_CFG_RANGE:\r
-    Record->PciCfg.Base = (UINT16) ResourceLo;\r
-    Record->PciCfg.Length = (UINT16) (ResourceHi - ResourceLo);\r
-    break;\r
-  default:\r
-    return FALSE;\r
+    case MEM_RANGE:\r
+    case MMIO_RANGE:\r
+      Record->Mem.Base   = ResourceLo;\r
+      Record->Mem.Length = ResourceHi - ResourceLo;\r
+      break;\r
+    case IO_RANGE:\r
+    case TRAPPED_IO_RANGE:\r
+      Record->Io.Base   = (UINT16)ResourceLo;\r
+      Record->Io.Length = (UINT16)(ResourceHi - ResourceLo);\r
+      break;\r
+    case PCI_CFG_RANGE:\r
+      Record->PciCfg.Base   = (UINT16)ResourceLo;\r
+      Record->PciCfg.Length = (UINT16)(ResourceHi - ResourceLo);\r
+      break;\r
+    default:\r
+      return FALSE;\r
   }\r
 \r
   return TRUE;\r
@@ -595,10 +602,10 @@ HandleSingleResource (
 **/\r
 VOID\r
 AddSingleResource (\r
-  IN  STM_RSC    *Resource\r
+  IN  STM_RSC  *Resource\r
   )\r
 {\r
-  STM_RSC    *Record;\r
+  STM_RSC  *Record;\r
 \r
   Record = (STM_RSC *)mStmResourcesPtr;\r
 \r
@@ -606,6 +613,7 @@ AddSingleResource (
     if (Record->Header.RscType == END_OF_RESOURCES) {\r
       break;\r
     }\r
+\r
     //\r
     // Go to next record if resource and record types don't match.\r
     //\r
@@ -613,12 +621,14 @@ AddSingleResource (
       Record = (STM_RSC *)((UINTN)Record + Record->Header.Length);\r
       continue;\r
     }\r
+\r
     //\r
     // Record is handled inside of procedure - don't adjust.\r
     //\r
     if (HandleSingleResource (Resource, Record)) {\r
-      return ;\r
+      return;\r
     }\r
+\r
     Record = (STM_RSC *)((UINTN)Record + Record->Header.Length);\r
   }\r
 \r
@@ -626,19 +636,19 @@ AddSingleResource (
   // Add resource to the end of area.\r
   //\r
   CopyMem (\r
-    mStmResourcesPtr + mStmResourceSizeUsed - sizeof(mRscEndNode),\r
+    mStmResourcesPtr + mStmResourceSizeUsed - sizeof (mRscEndNode),\r
     Resource,\r
     Resource->Header.Length\r
     );\r
   CopyMem (\r
-    mStmResourcesPtr + mStmResourceSizeUsed - sizeof(mRscEndNode) + Resource->Header.Length,\r
+    mStmResourcesPtr + mStmResourceSizeUsed - sizeof (mRscEndNode) + Resource->Header.Length,\r
     &mRscEndNode,\r
-    sizeof(mRscEndNode)\r
+    sizeof (mRscEndNode)\r
     );\r
-  mStmResourceSizeUsed += Resource->Header.Length;\r
+  mStmResourceSizeUsed     += Resource->Header.Length;\r
   mStmResourceSizeAvailable = mStmResourceTotalSize - mStmResourceSizeUsed;\r
 \r
-  return ;\r
+  return;\r
 }\r
 \r
 /**\r
@@ -652,13 +662,13 @@ AddSingleResource (
 **/\r
 VOID\r
 AddResource (\r
-  IN  STM_RSC    *ResourceList,\r
-  IN  UINT32      NumEntries OPTIONAL\r
+  IN  STM_RSC  *ResourceList,\r
+  IN  UINT32   NumEntries OPTIONAL\r
   )\r
 {\r
-  UINT32      Count;\r
-  UINTN       Index;\r
-  STM_RSC    *Resource;\r
+  UINT32   Count;\r
+  UINTN    Index;\r
+  STM_RSC  *Resource;\r
 \r
   if (NumEntries == 0) {\r
     Count = 0xFFFFFFFF;\r
@@ -670,12 +680,14 @@ AddResource (
 \r
   for (Index = 0; Index < Count; Index++) {\r
     if (Resource->Header.RscType == END_OF_RESOURCES) {\r
-      return ;\r
+      return;\r
     }\r
+\r
     AddSingleResource (Resource);\r
     Resource = (STM_RSC *)((UINTN)Resource + Resource->Header.Length);\r
   }\r
-  return ;\r
+\r
+  return;\r
 }\r
 \r
 /**\r
@@ -692,14 +704,14 @@ AddResource (
 **/\r
 BOOLEAN\r
 ValidateResource (\r
-  IN  STM_RSC    *ResourceList,\r
-  IN  UINT32      NumEntries OPTIONAL\r
+  IN  STM_RSC  *ResourceList,\r
+  IN  UINT32   NumEntries OPTIONAL\r
   )\r
 {\r
-  UINT32      Count;\r
-  UINTN       Index;\r
-  STM_RSC    *Resource;\r
-  UINTN       SubIndex;\r
+  UINT32   Count;\r
+  UINTN    Index;\r
+  STM_RSC  *Resource;\r
+  UINTN    SubIndex;\r
 \r
   //\r
   // If NumEntries == 0 make it very big. Scan will be terminated by\r
@@ -724,21 +736,23 @@ ValidateResource (
     switch (Resource->Header.RscType) {\r
       case END_OF_RESOURCES:\r
         if (Resource->Header.Length != sizeof (STM_RSC_END)) {\r
-          return  FALSE;\r
+          return FALSE;\r
         }\r
+\r
         //\r
         // If we are passed actual number of resources to add,\r
         // END_OF_RESOURCES structure between them is considered an\r
         // error. If NumEntries == 0 END_OF_RESOURCES is a termination.\r
         //\r
         if (NumEntries != 0) {\r
-          return  FALSE;\r
+          return FALSE;\r
         } else {\r
           //\r
           // If NumEntries == 0 and list reached end - return success.\r
           //\r
           return TRUE;\r
         }\r
+\r
         break;\r
 \r
       case MEM_RANGE:\r
@@ -750,6 +764,7 @@ ValidateResource (
         if (Resource->Mem.RWXAttributes > FULL_ACCS) {\r
           return FALSE;\r
         }\r
+\r
         break;\r
 \r
       case IO_RANGE:\r
@@ -761,35 +776,42 @@ ValidateResource (
         if ((Resource->Io.Base + Resource->Io.Length) > 0xFFFF) {\r
           return FALSE;\r
         }\r
+\r
         break;\r
 \r
       case PCI_CFG_RANGE:\r
         DEBUG ((DEBUG_INFO, "ValidateResource - PCI (0x%02x, 0x%08x, 0x%02x, 0x%02x)\n", Resource->PciCfg.OriginatingBusNumber, Resource->PciCfg.LastNodeIndex, Resource->PciCfg.PciDevicePath[0].PciDevice, Resource->PciCfg.PciDevicePath[0].PciFunction));\r
-        if (Resource->Header.Length != sizeof (STM_RSC_PCI_CFG_DESC) + (sizeof(STM_PCI_DEVICE_PATH_NODE) * Resource->PciCfg.LastNodeIndex)) {\r
+        if (Resource->Header.Length != sizeof (STM_RSC_PCI_CFG_DESC) + (sizeof (STM_PCI_DEVICE_PATH_NODE) * Resource->PciCfg.LastNodeIndex)) {\r
           return FALSE;\r
         }\r
+\r
         for (SubIndex = 0; SubIndex <= Resource->PciCfg.LastNodeIndex; SubIndex++) {\r
           if ((Resource->PciCfg.PciDevicePath[SubIndex].PciDevice > 0x1F) || (Resource->PciCfg.PciDevicePath[SubIndex].PciFunction > 7)) {\r
             return FALSE;\r
           }\r
         }\r
+\r
         if ((Resource->PciCfg.Base + Resource->PciCfg.Length) > 0x1000) {\r
           return FALSE;\r
         }\r
+\r
         break;\r
 \r
       case MACHINE_SPECIFIC_REG:\r
         if (Resource->Header.Length != sizeof (STM_RSC_MSR_DESC)) {\r
           return FALSE;\r
         }\r
+\r
         break;\r
 \r
-      default :\r
+      default:\r
         DEBUG ((DEBUG_ERROR, "ValidateResource - Unknown RscType(%x)\n", Resource->Header.RscType));\r
         return FALSE;\r
     }\r
+\r
     Resource = (STM_RSC *)((UINTN)Resource + Resource->Header.Length);\r
   }\r
+\r
   return TRUE;\r
 }\r
 \r
@@ -808,13 +830,13 @@ ValidateResource (
 **/\r
 UINTN\r
 GetResourceSize (\r
-  IN  STM_RSC    *ResourceList,\r
-  IN  UINT32      NumEntries OPTIONAL\r
+  IN  STM_RSC  *ResourceList,\r
+  IN  UINT32   NumEntries OPTIONAL\r
   )\r
 {\r
-  UINT32      Count;\r
-  UINTN       Index;\r
-  STM_RSC    *Resource;\r
+  UINT32   Count;\r
+  UINTN    Index;\r
+  STM_RSC  *Resource;\r
 \r
   Resource = ResourceList;\r
 \r
@@ -837,6 +859,7 @@ GetResourceSize (
     if (Resource->Header.RscType == END_OF_RESOURCES) {\r
       break;\r
     }\r
+\r
     Resource = (STM_RSC *)((UINTN)Resource + Resource->Header.Length);\r
   }\r
 \r
@@ -859,8 +882,8 @@ GetResourceSize (
 EFI_STATUS\r
 EFIAPI\r
 AddPiResource (\r
-  IN  STM_RSC    *ResourceList,\r
-  IN  UINT32      NumEntries OPTIONAL\r
+  IN  STM_RSC  *ResourceList,\r
+  IN  UINT32   NumEntries OPTIONAL\r
   )\r
 {\r
   EFI_STATUS            Status;\r
@@ -884,7 +907,7 @@ AddPiResource (
     //\r
     // First time allocation\r
     //\r
-    NewResourceSize = EFI_PAGES_TO_SIZE (EFI_SIZE_TO_PAGES (ResourceSize + sizeof(mRscEndNode)));\r
+    NewResourceSize = EFI_PAGES_TO_SIZE (EFI_SIZE_TO_PAGES (ResourceSize + sizeof (mRscEndNode)));\r
     DEBUG ((DEBUG_INFO, "Allocate - 0x%08x\n", NewResourceSize));\r
     Status = gSmst->SmmAllocatePages (\r
                       AllocateAnyPages,\r
@@ -899,11 +922,11 @@ AddPiResource (
     //\r
     // Copy EndResource for initialization\r
     //\r
-    mStmResourcesPtr = (UINT8 *)(UINTN)NewResource;\r
+    mStmResourcesPtr      = (UINT8 *)(UINTN)NewResource;\r
     mStmResourceTotalSize = NewResourceSize;\r
-    CopyMem (mStmResourcesPtr, &mRscEndNode, sizeof(mRscEndNode));\r
-    mStmResourceSizeUsed      = sizeof(mRscEndNode);\r
-    mStmResourceSizeAvailable = mStmResourceTotalSize - sizeof(mRscEndNode);\r
+    CopyMem (mStmResourcesPtr, &mRscEndNode, sizeof (mRscEndNode));\r
+    mStmResourceSizeUsed      = sizeof (mRscEndNode);\r
+    mStmResourceSizeAvailable = mStmResourceTotalSize - sizeof (mRscEndNode);\r
 \r
     //\r
     // Let SmmCore change resource ptr\r
@@ -925,6 +948,7 @@ AddPiResource (
     if (EFI_ERROR (Status)) {\r
       return Status;\r
     }\r
+\r
     CopyMem ((VOID *)(UINTN)NewResource, mStmResourcesPtr, mStmResourceSizeUsed);\r
     mStmResourceSizeAvailable = NewResourceSize - mStmResourceSizeUsed;\r
 \r
@@ -934,7 +958,7 @@ AddPiResource (
              );\r
 \r
     mStmResourceTotalSize = NewResourceSize;\r
-    mStmResourcesPtr = (UINT8 *)(UINTN)NewResource;\r
+    mStmResourcesPtr      = (UINT8 *)(UINTN)NewResource;\r
 \r
     //\r
     // Let SmmCore change resource ptr\r
@@ -966,8 +990,8 @@ AddPiResource (
 EFI_STATUS\r
 EFIAPI\r
 DeletePiResource (\r
-  IN  STM_RSC    *ResourceList,\r
-  IN  UINT32      NumEntries OPTIONAL\r
+  IN  STM_RSC  *ResourceList,\r
+  IN  UINT32   NumEntries OPTIONAL\r
   )\r
 {\r
   if (ResourceList != NULL) {\r
@@ -975,12 +999,13 @@ DeletePiResource (
     ASSERT (FALSE);\r
     return EFI_UNSUPPORTED;\r
   }\r
+\r
   //\r
   // Delete all\r
   //\r
-  CopyMem (mStmResourcesPtr, &mRscEndNode, sizeof(mRscEndNode));\r
-  mStmResourceSizeUsed      = sizeof(mRscEndNode);\r
-  mStmResourceSizeAvailable = mStmResourceTotalSize - sizeof(mRscEndNode);\r
+  CopyMem (mStmResourcesPtr, &mRscEndNode, sizeof (mRscEndNode));\r
+  mStmResourceSizeUsed      = sizeof (mRscEndNode);\r
+  mStmResourceSizeAvailable = mStmResourceTotalSize - sizeof (mRscEndNode);\r
   return EFI_SUCCESS;\r
 }\r
 \r
@@ -1000,8 +1025,8 @@ DeletePiResource (
 EFI_STATUS\r
 EFIAPI\r
 GetPiResource (\r
-  OUT    STM_RSC *ResourceList,\r
-  IN OUT UINT32  *ResourceSize\r
+  OUT    STM_RSC  *ResourceList,\r
+  IN OUT UINT32   *ResourceSize\r
   )\r
 {\r
   if (*ResourceSize < mStmResourceSizeUsed) {\r
@@ -1029,7 +1054,7 @@ EnableMsegMsr (
 {\r
   MSR_IA32_SMM_MONITOR_CTL_REGISTER  SmmMonitorCtl;\r
 \r
-  SmmMonitorCtl.Uint64 = AsmReadMsr64 (MSR_IA32_SMM_MONITOR_CTL);\r
+  SmmMonitorCtl.Uint64     = AsmReadMsr64 (MSR_IA32_SMM_MONITOR_CTL);\r
   SmmMonitorCtl.Bits.Valid = 1;\r
   AsmWriteMsr64 (MSR_IA32_SMM_MONITOR_CTL, SmmMonitorCtl.Uint64);\r
 }\r
@@ -1067,18 +1092,18 @@ GetVmcsSize (
 **/\r
 BOOLEAN\r
 StmCheckStmImage (\r
-  IN EFI_PHYSICAL_ADDRESS StmImage,\r
-  IN UINTN                StmImageSize\r
+  IN EFI_PHYSICAL_ADDRESS  StmImage,\r
+  IN UINTN                 StmImageSize\r
   )\r
 {\r
-  UINTN                     MinMsegSize;\r
-  STM_HEADER                *StmHeader;\r
-  IA32_VMX_MISC_REGISTER    VmxMiscMsr;\r
+  UINTN                   MinMsegSize;\r
+  STM_HEADER              *StmHeader;\r
+  IA32_VMX_MISC_REGISTER  VmxMiscMsr;\r
 \r
   //\r
   // Check to see if STM image is compatible with CPU\r
   //\r
-  StmHeader = (STM_HEADER *)(UINTN)StmImage;\r
+  StmHeader         = (STM_HEADER *)(UINTN)StmImage;\r
   VmxMiscMsr.Uint64 = AsmReadMsr64 (MSR_IA32_VMX_MISC);\r
   if (StmHeader->HwStmHdr.MsegHeaderRevision != VmxMiscMsr.Bits.MsegRevisionIdentifier) {\r
     DEBUG ((DEBUG_ERROR, "STM Image not compatible with CPU\n"));\r
@@ -1101,8 +1126,8 @@ StmCheckStmImage (
     //\r
     // We will create page table, just in case that SINIT does not create it.\r
     //\r
-    if (MinMsegSize < StmHeader->HwStmHdr.Cr3Offset + EFI_PAGES_TO_SIZE(6)) {\r
-      MinMsegSize = StmHeader->HwStmHdr.Cr3Offset + EFI_PAGES_TO_SIZE(6);\r
+    if (MinMsegSize < StmHeader->HwStmHdr.Cr3Offset + EFI_PAGES_TO_SIZE (6)) {\r
+      MinMsegSize = StmHeader->HwStmHdr.Cr3Offset + EFI_PAGES_TO_SIZE (6);\r
     }\r
   }\r
 \r
@@ -1133,8 +1158,8 @@ StmCheckStmImage (
 **/\r
 VOID\r
 StmLoadStmImage (\r
-  IN EFI_PHYSICAL_ADDRESS StmImage,\r
-  IN UINTN                StmImageSize\r
+  IN EFI_PHYSICAL_ADDRESS  StmImage,\r
+  IN UINTN                 StmImageSize\r
   )\r
 {\r
   MSR_IA32_SMM_MONITOR_CTL_REGISTER  SmmMonitorCtl;\r
@@ -1145,7 +1170,7 @@ StmLoadStmImage (
   // Get MSEG base address from MSR_IA32_SMM_MONITOR_CTL\r
   //\r
   SmmMonitorCtl.Uint64 = AsmReadMsr64 (MSR_IA32_SMM_MONITOR_CTL);\r
-  MsegBase = SmmMonitorCtl.Bits.MsegBase << 12;\r
+  MsegBase             = SmmMonitorCtl.Bits.MsegBase << 12;\r
 \r
   //\r
   // Zero all of MSEG base address\r
@@ -1181,8 +1206,8 @@ StmLoadStmImage (
 EFI_STATUS\r
 EFIAPI\r
 LoadMonitor (\r
-  IN EFI_PHYSICAL_ADDRESS StmImage,\r
-  IN UINTN                StmImageSize\r
+  IN EFI_PHYSICAL_ADDRESS  StmImage,\r
+  IN UINTN                 StmImageSize\r
   )\r
 {\r
   MSR_IA32_SMM_MONITOR_CTL_REGISTER  SmmMonitorCtl;\r
@@ -1201,7 +1226,7 @@ LoadMonitor (
   }\r
 \r
   // Record STM_HASH to PCR 0, just in case it is NOT TXT launch, we still need provide the evidence.\r
-  TpmMeasureAndLogData(\r
+  TpmMeasureAndLogData (\r
     0,                        // PcrIndex\r
     TXT_EVTYPE_STM_HASH,      // EventType\r
     NULL,                     // EventLog\r
@@ -1226,7 +1251,7 @@ LoadMonitor (
 \r
 **/\r
 VOID *\r
-GetStmResource(\r
+GetStmResource (\r
   VOID\r
   )\r
 {\r
@@ -1241,19 +1266,19 @@ GetStmResource(
 **/\r
 VOID\r
 NotifyStmResourceChange (\r
-  VOID *StmResource\r
+  VOID  *StmResource\r
   )\r
 {\r
   UINTN                         Index;\r
   TXT_PROCESSOR_SMM_DESCRIPTOR  *Psd;\r
 \r
   for (Index = 0; Index < gSmst->NumberOfCpus; Index++) {\r
-    Psd = (TXT_PROCESSOR_SMM_DESCRIPTOR *)((UINTN)gSmst->CpuSaveState[Index] - SMRAM_SAVE_STATE_MAP_OFFSET + TXT_SMM_PSD_OFFSET);\r
+    Psd                                = (TXT_PROCESSOR_SMM_DESCRIPTOR *)((UINTN)gSmst->CpuSaveState[Index] - SMRAM_SAVE_STATE_MAP_OFFSET + TXT_SMM_PSD_OFFSET);\r
     Psd->BiosHwResourceRequirementsPtr = (UINT64)(UINTN)StmResource;\r
   }\r
-  return ;\r
-}\r
 \r
+  return;\r
+}\r
 \r
 /**\r
   This is STM setup BIOS callback.\r
@@ -1278,4 +1303,3 @@ SmmStmTeardown (
 {\r
   mStmState &= ~EFI_SM_MONITOR_STATE_ACTIVATED;\r
 }\r
-\r

diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.h b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.h
index da551cc4a6a64fd6a49a6ad4bcad0d99d27d8338..597c3abf0089ce3d1aed8143e2f7cbbfa5d07c17 100644 (file)
--- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.h
+++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.h
@@ -21,7 +21,7 @@
 **/\r
 VOID\r
 StmGen4GPageTable (\r
-  IN UINTN              PageTableBase\r
+  IN UINTN  PageTableBase\r
   );\r
 \r
 /**\r
@@ -42,10 +42,9 @@ StmGen4GPageTable (
 UINT32\r
 EFIAPI\r
 SmmStmExceptionHandler (\r
-  IN OUT STM_PROTECTION_EXCEPTION_STACK_FRAME Context\r
+  IN OUT STM_PROTECTION_EXCEPTION_STACK_FRAME  Context\r
   );\r
 \r
-\r
 /**\r
 \r
   Get STM state.\r
@@ -73,8 +72,8 @@ GetMonitorState (
 EFI_STATUS\r
 EFIAPI\r
 LoadMonitor (\r
-  IN EFI_PHYSICAL_ADDRESS StmImage,\r
-  IN UINTN                StmImageSize\r
+  IN EFI_PHYSICAL_ADDRESS  StmImage,\r
+  IN UINTN                 StmImageSize\r
   );\r
 \r
 /**\r
@@ -94,7 +93,7 @@ EFI_STATUS
 EFIAPI\r
 AddPiResource (\r
   IN  STM_RSC  *ResourceList,\r
-  IN  UINT32    NumEntries OPTIONAL\r
+  IN  UINT32   NumEntries OPTIONAL\r
   );\r
 \r
 /**\r
@@ -113,8 +112,8 @@ AddPiResource (
 EFI_STATUS\r
 EFIAPI\r
 DeletePiResource (\r
-  IN  STM_RSC    *ResourceList,\r
-  IN  UINT32      NumEntries OPTIONAL\r
+  IN  STM_RSC  *ResourceList,\r
+  IN  UINT32   NumEntries OPTIONAL\r
   );\r
 \r
 /**\r
@@ -133,8 +132,8 @@ DeletePiResource (
 EFI_STATUS\r
 EFIAPI\r
 GetPiResource (\r
-  OUT    STM_RSC *ResourceList,\r
-  IN OUT UINT32  *ResourceSize\r
+  OUT    STM_RSC  *ResourceList,\r
+  IN OUT UINT32   *ResourceSize\r
   );\r
 \r
 /**\r
@@ -153,7 +152,7 @@ StmSmmConfigurationTableInit (
 **/\r
 VOID\r
 NotifyStmResourceChange (\r
-  IN VOID *StmResource\r
+  IN VOID  *StmResource\r
   );\r
 \r
 /**\r
@@ -174,6 +173,6 @@ GetStmResource (
 VOID\r
 EFIAPI\r
 SmmCpuFeaturesLibStmSmiEntryFixupAddress (\r
- );\r
+  );\r
 \r
 #endif\r

diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmmStmSupport.c b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmmStmSupport.c
index c8a3f58e0ca5ef49e3ad03304498a5751050827c..00ab9bd0cd0d91c99e3bad8794c6003f47dc89ae 100644 (file)
--- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmmStmSupport.c
+++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmmStmSupport.c
@@ -14,9 +14,9 @@
 ///\r
 /// Page Table Entry\r
 ///\r
-#define IA32_PG_P                   BIT0\r
-#define IA32_PG_RW                  BIT1\r
-#define IA32_PG_PS                  BIT7\r
+#define IA32_PG_P   BIT0\r
+#define IA32_PG_RW  BIT1\r
+#define IA32_PG_PS  BIT7\r
 \r
 /**\r
 \r
@@ -28,22 +28,22 @@
 **/\r
 VOID\r
 StmGen4GPageTable (\r
-  IN UINTN              PageTableBase\r
+  IN UINTN  PageTableBase\r
   )\r
 {\r
-  UINTN                             Index;\r
-  UINTN                             SubIndex;\r
-  UINT64                            *Pde;\r
-  UINT64                            *Pte;\r
-  UINT64                            *Pml4;\r
+  UINTN   Index;\r
+  UINTN   SubIndex;\r
+  UINT64  *Pde;\r
+  UINT64  *Pte;\r
+  UINT64  *Pml4;\r
 \r
-  Pml4 = (UINT64*)(UINTN)PageTableBase;\r
+  Pml4           = (UINT64 *)(UINTN)PageTableBase;\r
   PageTableBase += SIZE_4KB;\r
-  *Pml4 = PageTableBase | IA32_PG_RW | IA32_PG_P;\r
+  *Pml4          = PageTableBase | IA32_PG_RW | IA32_PG_P;\r
 \r
-  Pde = (UINT64*)(UINTN)PageTableBase;\r
+  Pde            = (UINT64 *)(UINTN)PageTableBase;\r
   PageTableBase += SIZE_4KB;\r
-  Pte = (UINT64 *)(UINTN)PageTableBase;\r
+  Pte            = (UINT64 *)(UINTN)PageTableBase;\r
 \r
   for (Index = 0; Index < 4; Index++) {\r
     *Pde = PageTableBase | IA32_PG_RW | IA32_PG_P;\r
@@ -75,7 +75,7 @@ StmGen4GPageTable (
 UINT32\r
 EFIAPI\r
 SmmStmExceptionHandler (\r
-  IN OUT STM_PROTECTION_EXCEPTION_STACK_FRAME Context\r
+  IN OUT STM_PROTECTION_EXCEPTION_STACK_FRAME  Context\r
   )\r
 {\r
   // TBD - SmmStmExceptionHandler, record information\r

diff --git a/UefiCpuPkg/Library/SmmCpuPlatformHookLibNull/SmmCpuPlatformHookLibNull.c b/UefiCpuPkg/Library/SmmCpuPlatformHookLibNull/SmmCpuPlatformHookLibNull.c
index 6c2010dc0a6758d0660285be5132cbf9dd9c2726..085a03e52a4a7bb13df7478cf7bb206ed478d88c 100644 (file)
--- a/UefiCpuPkg/Library/SmmCpuPlatformHookLibNull/SmmCpuPlatformHookLibNull.c
+++ b/UefiCpuPkg/Library/SmmCpuPlatformHookLibNull/SmmCpuPlatformHookLibNull.c
@@ -69,7 +69,7 @@ ClearTopLevelSmiStatus (
 EFI_STATUS\r
 EFIAPI\r
 PlatformSmmBspElection (\r
-  OUT BOOLEAN     *IsBsp\r
+  OUT BOOLEAN  *IsBsp\r
   )\r
 {\r
   return EFI_NOT_READY;\r
@@ -92,10 +92,10 @@ PlatformSmmBspElection (
 EFI_STATUS\r
 EFIAPI\r
 GetPlatformPageTableAttribute (\r
-  IN  UINT64                Address,\r
-  IN OUT SMM_PAGE_SIZE_TYPE *PageSize,\r
-  IN OUT UINTN              *NumOfPages,\r
-  IN OUT UINTN              *PageAttribute\r
+  IN  UINT64                 Address,\r
+  IN OUT SMM_PAGE_SIZE_TYPE  *PageSize,\r
+  IN OUT UINTN               *NumOfPages,\r
+  IN OUT UINTN               *PageAttribute\r
   )\r
 {\r
   return EFI_UNSUPPORTED;\r

diff --git a/UefiCpuPkg/Library/VmgExitLibNull/VmgExitLibNull.c b/UefiCpuPkg/Library/VmgExitLibNull/VmgExitLibNull.c
index 89b065cb3ff31d837763f51b69b9ceaefc761a9c..d661d85974342a2c1f7b84a55dc2dc901dda3db6 100644 (file)
--- a/UefiCpuPkg/Library/VmgExitLibNull/VmgExitLibNull.c
+++ b/UefiCpuPkg/Library/VmgExitLibNull/VmgExitLibNull.c
@@ -35,15 +35,15 @@
 UINT64\r
 EFIAPI\r
 VmgExit (\r
-  IN OUT GHCB                *Ghcb,\r
-  IN     UINT64              ExitCode,\r
-  IN     UINT64              ExitInfo1,\r
-  IN     UINT64              ExitInfo2\r
+  IN OUT GHCB    *Ghcb,\r
+  IN     UINT64  ExitCode,\r
+  IN     UINT64  ExitInfo1,\r
+  IN     UINT64  ExitInfo2\r
   )\r
 {\r
   GHCB_EVENT_INJECTION  Event;\r
 \r
-  Event.Uint64 = 0;\r
+  Event.Uint64          = 0;\r
   Event.Elements.Vector = GP_EXCEPTION;\r
   Event.Elements.Type   = GHCB_EVENT_INJECTION_TYPE_EXCEPTION;\r
   Event.Elements.Valid  = 1;\r
@@ -65,8 +65,8 @@ VmgExit (
 VOID\r
 EFIAPI\r
 VmgInit (\r
-  IN OUT GHCB                *Ghcb,\r
-  IN OUT BOOLEAN             *InterruptState\r
+  IN OUT GHCB     *Ghcb,\r
+  IN OUT BOOLEAN  *InterruptState\r
   )\r
 {\r
 }\r
@@ -85,8 +85,8 @@ VmgInit (
 VOID\r
 EFIAPI\r
 VmgDone (\r
-  IN OUT GHCB                *Ghcb,\r
-  IN     BOOLEAN             InterruptState\r
+  IN OUT GHCB     *Ghcb,\r
+  IN     BOOLEAN  InterruptState\r
   )\r
 {\r
 }\r
@@ -104,8 +104,8 @@ VmgDone (
 VOID\r
 EFIAPI\r
 VmgSetOffsetValid (\r
-  IN OUT GHCB                *Ghcb,\r
-  IN     GHCB_REGISTER       Offset\r
+  IN OUT GHCB           *Ghcb,\r
+  IN     GHCB_REGISTER  Offset\r
   )\r
 {\r
 }\r
@@ -126,8 +126,8 @@ VmgSetOffsetValid (
 BOOLEAN\r
 EFIAPI\r
 VmgIsOffsetValid (\r
-  IN GHCB                    *Ghcb,\r
-  IN GHCB_REGISTER           Offset\r
+  IN GHCB           *Ghcb,\r
+  IN GHCB_REGISTER  Offset\r
   )\r
 {\r
   return FALSE;\r

diff --git a/UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationPei.c b/UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationPei.c
index e9e2464be7b89782c4ad7f8741d43507c7785feb..8bd0612c7bab0d917d318909f5f4eb572a67e46f 100644 (file)
--- a/UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationPei.c
+++ b/UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationPei.c
@@ -86,14 +86,14 @@ typedef struct {
 } EFI_SMM_SYSTEM_TABLE2_64;\r
 \r
 typedef struct {\r
-  EFI_GUID                          VendorGuid;\r
-  UINT64                            VendorTable;\r
+  EFI_GUID    VendorGuid;\r
+  UINT64      VendorTable;\r
 } EFI_CONFIGURATION_TABLE64;\r
 #endif\r
 \r
 #if defined (MDE_CPU_X64)\r
-typedef EFI_SMM_SYSTEM_TABLE2 EFI_SMM_SYSTEM_TABLE2_64;\r
-typedef EFI_CONFIGURATION_TABLE EFI_CONFIGURATION_TABLE64;\r
+typedef EFI_SMM_SYSTEM_TABLE2    EFI_SMM_SYSTEM_TABLE2_64;\r
+typedef EFI_CONFIGURATION_TABLE  EFI_CONFIGURATION_TABLE64;\r
 #endif\r
 \r
 /**\r
@@ -113,14 +113,14 @@ typedef EFI_CONFIGURATION_TABLE EFI_CONFIGURATION_TABLE64;
 EFI_STATUS\r
 EFIAPI\r
 Communicate (\r
-  IN CONST EFI_PEI_SMM_COMMUNICATION_PPI   *This,\r
-  IN OUT VOID                              *CommBuffer,\r
-  IN OUT UINTN                             *CommSize\r
+  IN CONST EFI_PEI_SMM_COMMUNICATION_PPI  *This,\r
+  IN OUT VOID                             *CommBuffer,\r
+  IN OUT UINTN                            *CommSize\r
   );\r
 \r
-EFI_PEI_SMM_COMMUNICATION_PPI      mSmmCommunicationPpi = { Communicate };\r
+EFI_PEI_SMM_COMMUNICATION_PPI  mSmmCommunicationPpi = { Communicate };\r
 \r
-EFI_PEI_PPI_DESCRIPTOR mPpiList = {\r
+EFI_PEI_PPI_DESCRIPTOR  mPpiList = {\r
   (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),\r
   &gEfiPeiSmmCommunicationPpiGuid,\r
   &mSmmCommunicationPpi\r
@@ -136,8 +136,8 @@ GetCommunicationContext (
   VOID\r
   )\r
 {\r
-  EFI_HOB_GUID_TYPE                *GuidHob;\r
-  EFI_SMM_COMMUNICATION_CONTEXT    *SmmCommunicationContext;\r
+  EFI_HOB_GUID_TYPE              *GuidHob;\r
+  EFI_SMM_COMMUNICATION_CONTEXT  *SmmCommunicationContext;\r
 \r
   GuidHob = GetFirstGuidHob (&gEfiPeiSmmCommunicationPpiGuid);\r
   ASSERT (GuidHob != NULL);\r
@@ -154,20 +154,20 @@ GetCommunicationContext (
 **/\r
 VOID\r
 SetCommunicationContext (\r
-  IN EFI_SMM_COMMUNICATION_CONTEXT    *SmmCommunicationContext\r
+  IN EFI_SMM_COMMUNICATION_CONTEXT  *SmmCommunicationContext\r
   )\r
 {\r
-  EFI_PEI_HOB_POINTERS             Hob;\r
-  UINTN                            BufferSize;\r
+  EFI_PEI_HOB_POINTERS  Hob;\r
+  UINTN                 BufferSize;\r
 \r
   BufferSize = sizeof (*SmmCommunicationContext);\r
-  Hob.Raw = BuildGuidHob (\r
-              &gEfiPeiSmmCommunicationPpiGuid,\r
-              BufferSize\r
-              );\r
+  Hob.Raw    = BuildGuidHob (\r
+                 &gEfiPeiSmmCommunicationPpiGuid,\r
+                 BufferSize\r
+                 );\r
   ASSERT (Hob.Raw);\r
 \r
-  CopyMem ((VOID *)Hob.Raw, SmmCommunicationContext, sizeof(*SmmCommunicationContext));\r
+  CopyMem ((VOID *)Hob.Raw, SmmCommunicationContext, sizeof (*SmmCommunicationContext));\r
 }\r
 \r
 /**\r
@@ -181,18 +181,18 @@ SetCommunicationContext (
 **/\r
 VOID *\r
 InternalSmstGetVendorTableByGuid (\r
-  IN UINT64                                        Signature,\r
-  IN EFI_SMM_SYSTEM_TABLE2                         *Smst,\r
-  IN EFI_GUID                                      *VendorGuid\r
+  IN UINT64                 Signature,\r
+  IN EFI_SMM_SYSTEM_TABLE2  *Smst,\r
+  IN EFI_GUID               *VendorGuid\r
   )\r
 {\r
-  EFI_CONFIGURATION_TABLE                       *SmmConfigurationTable;\r
-  UINTN                                         NumberOfTableEntries;\r
-  UINTN                                         Index;\r
-  EFI_SMM_SYSTEM_TABLE2_64                      *Smst64;\r
-  EFI_CONFIGURATION_TABLE64                     *SmmConfigurationTable64;\r
+  EFI_CONFIGURATION_TABLE    *SmmConfigurationTable;\r
+  UINTN                      NumberOfTableEntries;\r
+  UINTN                      Index;\r
+  EFI_SMM_SYSTEM_TABLE2_64   *Smst64;\r
+  EFI_CONFIGURATION_TABLE64  *SmmConfigurationTable64;\r
 \r
-  if ((sizeof(UINTN) == sizeof(UINT32)) && (Signature == SMM_S3_RESUME_SMM_64)) {\r
+  if ((sizeof (UINTN) == sizeof (UINT32)) && (Signature == SMM_S3_RESUME_SMM_64)) {\r
     //\r
     // 32 PEI + 64 DXE\r
     //\r
@@ -200,23 +200,25 @@ InternalSmstGetVendorTableByGuid (
     DEBUG ((DEBUG_INFO, "InitCommunicationContext - SmmConfigurationTable: %x\n", Smst64->SmmConfigurationTable));\r
     DEBUG ((DEBUG_INFO, "InitCommunicationContext - NumberOfTableEntries: %x\n", Smst64->NumberOfTableEntries));\r
     SmmConfigurationTable64 = (EFI_CONFIGURATION_TABLE64 *)(UINTN)Smst64->SmmConfigurationTable;\r
-    NumberOfTableEntries = (UINTN)Smst64->NumberOfTableEntries;\r
+    NumberOfTableEntries    = (UINTN)Smst64->NumberOfTableEntries;\r
     for (Index = 0; Index < NumberOfTableEntries; Index++) {\r
       if (CompareGuid (&SmmConfigurationTable64[Index].VendorGuid, VendorGuid)) {\r
         return (VOID *)(UINTN)SmmConfigurationTable64[Index].VendorTable;\r
       }\r
     }\r
+\r
     return NULL;\r
   } else {\r
     DEBUG ((DEBUG_INFO, "InitCommunicationContext - SmmConfigurationTable: %x\n", Smst->SmmConfigurationTable));\r
     DEBUG ((DEBUG_INFO, "InitCommunicationContext - NumberOfTableEntries: %x\n", Smst->NumberOfTableEntries));\r
     SmmConfigurationTable = Smst->SmmConfigurationTable;\r
-    NumberOfTableEntries = Smst->NumberOfTableEntries;\r
+    NumberOfTableEntries  = Smst->NumberOfTableEntries;\r
     for (Index = 0; Index < NumberOfTableEntries; Index++) {\r
       if (CompareGuid (&SmmConfigurationTable[Index].VendorGuid, VendorGuid)) {\r
         return (VOID *)SmmConfigurationTable[Index].VendorTable;\r
       }\r
     }\r
+\r
     return NULL;\r
   }\r
 }\r
@@ -229,14 +231,14 @@ InitCommunicationContext (
   VOID\r
   )\r
 {\r
-  EFI_SMRAM_DESCRIPTOR                          *SmramDescriptor;\r
-  SMM_S3_RESUME_STATE                           *SmmS3ResumeState;\r
-  VOID                                          *GuidHob;\r
-  EFI_SMM_COMMUNICATION_CONTEXT                 *SmmCommunicationContext;\r
+  EFI_SMRAM_DESCRIPTOR           *SmramDescriptor;\r
+  SMM_S3_RESUME_STATE            *SmmS3ResumeState;\r
+  VOID                           *GuidHob;\r
+  EFI_SMM_COMMUNICATION_CONTEXT  *SmmCommunicationContext;\r
 \r
   GuidHob = GetFirstGuidHob (&gEfiAcpiVariableGuid);\r
   ASSERT (GuidHob != NULL);\r
-  SmramDescriptor = (EFI_SMRAM_DESCRIPTOR *) GET_GUID_HOB_DATA (GuidHob);\r
+  SmramDescriptor  = (EFI_SMRAM_DESCRIPTOR *)GET_GUID_HOB_DATA (GuidHob);\r
   SmmS3ResumeState = (SMM_S3_RESUME_STATE *)(UINTN)SmramDescriptor->CpuStart;\r
 \r
   DEBUG ((DEBUG_INFO, "InitCommunicationContext - SmmS3ResumeState: %x\n", SmmS3ResumeState));\r
@@ -251,7 +253,7 @@ InitCommunicationContext (
 \r
   SetCommunicationContext (SmmCommunicationContext);\r
 \r
-  return ;\r
+  return;\r
 }\r
 \r
 /**\r
@@ -271,17 +273,17 @@ InitCommunicationContext (
 EFI_STATUS\r
 EFIAPI\r
 Communicate (\r
-  IN CONST EFI_PEI_SMM_COMMUNICATION_PPI   *This,\r
-  IN OUT VOID                              *CommBuffer,\r
-  IN OUT UINTN                             *CommSize\r
+  IN CONST EFI_PEI_SMM_COMMUNICATION_PPI  *This,\r
+  IN OUT VOID                             *CommBuffer,\r
+  IN OUT UINTN                            *CommSize\r
   )\r
 {\r
-  EFI_STATUS                       Status;\r
-  PEI_SMM_CONTROL_PPI              *SmmControl;\r
-  PEI_SMM_ACCESS_PPI               *SmmAccess;\r
-  UINT8                            SmiCommand;\r
-  UINTN                            Size;\r
-  EFI_SMM_COMMUNICATION_CONTEXT    *SmmCommunicationContext;\r
+  EFI_STATUS                     Status;\r
+  PEI_SMM_CONTROL_PPI            *SmmControl;\r
+  PEI_SMM_ACCESS_PPI             *SmmAccess;\r
+  UINT8                          SmiCommand;\r
+  UINTN                          Size;\r
+  EFI_SMM_COMMUNICATION_CONTEXT  *SmmCommunicationContext;\r
 \r
   DEBUG ((DEBUG_INFO, "PiSmmCommunicationPei Communicate Enter\n"));\r
 \r
@@ -333,15 +335,15 @@ Communicate (
   // Send command\r
   //\r
   SmiCommand = (UINT8)SmmCommunicationContext->SwSmiNumber;\r
-  Size = sizeof(SmiCommand);\r
-  Status = SmmControl->Trigger (\r
-                         (EFI_PEI_SERVICES **)GetPeiServicesTablePointer (),\r
-                         SmmControl,\r
-                         (INT8 *)&SmiCommand,\r
-                         &Size,\r
-                         FALSE,\r
-                         0\r
-                         );\r
+  Size       = sizeof (SmiCommand);\r
+  Status     = SmmControl->Trigger (\r
+                             (EFI_PEI_SERVICES **)GetPeiServicesTablePointer (),\r
+                             SmmControl,\r
+                             (INT8 *)&SmiCommand,\r
+                             &Size,\r
+                             FALSE,\r
+                             0\r
+                             );\r
   ASSERT_EFI_ERROR (Status);\r
 \r
   //\r
@@ -366,14 +368,14 @@ Communicate (
 EFI_STATUS\r
 EFIAPI\r
 PiSmmCommunicationPeiEntryPoint (\r
-  IN EFI_PEI_FILE_HANDLE       FileHandle,\r
-  IN CONST EFI_PEI_SERVICES    **PeiServices\r
+  IN EFI_PEI_FILE_HANDLE     FileHandle,\r
+  IN CONST EFI_PEI_SERVICES  **PeiServices\r
   )\r
 {\r
-  EFI_STATUS                      Status;\r
-  PEI_SMM_ACCESS_PPI              *SmmAccess;\r
-  EFI_BOOT_MODE                   BootMode;\r
-  UINTN                           Index;\r
+  EFI_STATUS          Status;\r
+  PEI_SMM_ACCESS_PPI  *SmmAccess;\r
+  EFI_BOOT_MODE       BootMode;\r
+  UINTN               Index;\r
 \r
   BootMode = GetBootModeHob ();\r
   if (BootMode != BOOT_ON_S3_RESUME) {\r

diff --git a/UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationPrivate.h b/UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationPrivate.h
index cf1c57eeffc8ead873dc3caf762aef85028c712e..c51c012ebc565b16cc81a9ca0160dac8dab7a778 100644 (file)
--- a/UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationPrivate.h
+++ b/UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationPrivate.h
@@ -11,12 +11,12 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
 \r
 #pragma pack(push, 1)\r
 \r
-#define SMM_COMMUNICATION_SIGNATURE SIGNATURE_32 ('S','M','M','C')\r
+#define SMM_COMMUNICATION_SIGNATURE  SIGNATURE_32 ('S','M','M','C')\r
 \r
 typedef struct {\r
-  UINT32                   Signature;\r
-  UINT32                   SwSmiNumber;\r
-  EFI_PHYSICAL_ADDRESS     BufferPtrAddress;\r
+  UINT32                  Signature;\r
+  UINT32                  SwSmiNumber;\r
+  EFI_PHYSICAL_ADDRESS    BufferPtrAddress;\r
 } EFI_SMM_COMMUNICATION_CONTEXT;\r
 \r
 #pragma pack(pop)\r

diff --git a/UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationSmm.c b/UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationSmm.c
index 4fdea359d822e06fb729add16f1a0c9edf841bcc..2e76ade76997460ed53f3e70fc026c9ef141fc61 100644 (file)
--- a/UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationSmm.c
+++ b/UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationSmm.c
@@ -39,7 +39,7 @@ SetCommunicationContext (
                     gSmst,\r
                     &gEfiPeiSmmCommunicationPpiGuid,\r
                     &mSmmCommunicationContext,\r
-                    sizeof(mSmmCommunicationContext)\r
+                    sizeof (mSmmCommunicationContext)\r
                     );\r
   ASSERT_EFI_ERROR (Status);\r
 }\r
@@ -66,14 +66,14 @@ PiSmmCommunicationHandler (
   IN OUT UINTN   *CommBufferSize  OPTIONAL\r
   )\r
 {\r
-  UINTN                            CommSize;\r
-  EFI_STATUS                       Status;\r
-  EFI_SMM_COMMUNICATE_HEADER       *CommunicateHeader;\r
-  EFI_PHYSICAL_ADDRESS             *BufferPtrAddress;\r
+  UINTN                       CommSize;\r
+  EFI_STATUS                  Status;\r
+  EFI_SMM_COMMUNICATE_HEADER  *CommunicateHeader;\r
+  EFI_PHYSICAL_ADDRESS        *BufferPtrAddress;\r
 \r
   DEBUG ((DEBUG_INFO, "PiSmmCommunicationHandler Enter\n"));\r
 \r
-  BufferPtrAddress = (EFI_PHYSICAL_ADDRESS *)(UINTN)mSmmCommunicationContext.BufferPtrAddress;\r
+  BufferPtrAddress  = (EFI_PHYSICAL_ADDRESS *)(UINTN)mSmmCommunicationContext.BufferPtrAddress;\r
   CommunicateHeader = (EFI_SMM_COMMUNICATE_HEADER *)(UINTN)*BufferPtrAddress;\r
   DEBUG ((DEBUG_INFO, "PiSmmCommunicationHandler CommunicateHeader - %x\n", CommunicateHeader));\r
   if (CommunicateHeader == NULL) {\r
@@ -122,28 +122,28 @@ Done:
   @return Allocated address for output.\r
 \r
 **/\r
-VOID*\r
+VOID *\r
 AllocateAcpiNvsMemoryBelow4G (\r
-  IN   UINTN   Size\r
+  IN   UINTN  Size\r
   )\r
 {\r
   UINTN                 Pages;\r
   EFI_PHYSICAL_ADDRESS  Address;\r
   EFI_STATUS            Status;\r
-  VOID*                 Buffer;\r
+  VOID                  *Buffer;\r
 \r
-  Pages = EFI_SIZE_TO_PAGES (Size);\r
+  Pages   = EFI_SIZE_TO_PAGES (Size);\r
   Address = 0xffffffff;\r
 \r
-  Status  = gBS->AllocatePages (\r
-                   AllocateMaxAddress,\r
-                   EfiACPIMemoryNVS,\r
-                   Pages,\r
-                   &Address\r
-                   );\r
+  Status = gBS->AllocatePages (\r
+                  AllocateMaxAddress,\r
+                  EfiACPIMemoryNVS,\r
+                  Pages,\r
+                  &Address\r
+                  );\r
   ASSERT_EFI_ERROR (Status);\r
 \r
-  Buffer = (VOID *) (UINTN) Address;\r
+  Buffer = (VOID *)(UINTN)Address;\r
   ZeroMem (Buffer, Size);\r
 \r
   return Buffer;\r
@@ -165,11 +165,11 @@ PiSmmCommunicationSmmEntryPoint (
   IN EFI_SYSTEM_TABLE  *SystemTable\r
   )\r
 {\r
-  EFI_STATUS                    Status;\r
-  EFI_SMM_SW_DISPATCH2_PROTOCOL *SmmSwDispatch2;\r
-  EFI_SMM_SW_REGISTER_CONTEXT   SmmSwDispatchContext;\r
-  EFI_HANDLE                    DispatchHandle;\r
-  EFI_PHYSICAL_ADDRESS          *BufferPtrAddress;\r
+  EFI_STATUS                     Status;\r
+  EFI_SMM_SW_DISPATCH2_PROTOCOL  *SmmSwDispatch2;\r
+  EFI_SMM_SW_REGISTER_CONTEXT    SmmSwDispatchContext;\r
+  EFI_HANDLE                     DispatchHandle;\r
+  EFI_PHYSICAL_ADDRESS           *BufferPtrAddress;\r
 \r
   //\r
   // Register software SMI handler\r
@@ -182,24 +182,24 @@ PiSmmCommunicationSmmEntryPoint (
   ASSERT_EFI_ERROR (Status);\r
 \r
   SmmSwDispatchContext.SwSmiInputValue = (UINTN)-1;\r
-  Status = SmmSwDispatch2->Register (\r
-                             SmmSwDispatch2,\r
-                             PiSmmCommunicationHandler,\r
-                             &SmmSwDispatchContext,\r
-                             &DispatchHandle\r
-                             );\r
+  Status                               = SmmSwDispatch2->Register (\r
+                                                           SmmSwDispatch2,\r
+                                                           PiSmmCommunicationHandler,\r
+                                                           &SmmSwDispatchContext,\r
+                                                           &DispatchHandle\r
+                                                           );\r
   ASSERT_EFI_ERROR (Status);\r
 \r
   DEBUG ((DEBUG_INFO, "SmmCommunication SwSmi: %x\n", (UINTN)SmmSwDispatchContext.SwSmiInputValue));\r
 \r
-  BufferPtrAddress = AllocateAcpiNvsMemoryBelow4G (sizeof(EFI_PHYSICAL_ADDRESS));\r
+  BufferPtrAddress = AllocateAcpiNvsMemoryBelow4G (sizeof (EFI_PHYSICAL_ADDRESS));\r
   ASSERT (BufferPtrAddress != NULL);\r
   DEBUG ((DEBUG_INFO, "SmmCommunication BufferPtrAddress: 0x%016lx, BufferPtr: 0x%016lx\n", (EFI_PHYSICAL_ADDRESS)(UINTN)BufferPtrAddress, *BufferPtrAddress));\r
 \r
   //\r
   // Save context\r
   //\r
-  mSmmCommunicationContext.SwSmiNumber = (UINT32)SmmSwDispatchContext.SwSmiInputValue;\r
+  mSmmCommunicationContext.SwSmiNumber      = (UINT32)SmmSwDispatchContext.SwSmiInputValue;\r
   mSmmCommunicationContext.BufferPtrAddress = (EFI_PHYSICAL_ADDRESS)(UINTN)BufferPtrAddress;\r
   SetCommunicationContext ();\r
 \r

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
index 0d723336e4d68cf7e657037176fbc0af109a8f20..9b45c442c98ed90540eb0f13913562650ccf0316 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
@@ -10,42 +10,42 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
 \r
 #pragma pack(1)\r
 typedef struct {\r
-  UINTN             Lock;\r
-  VOID              *StackStart;\r
-  UINTN             StackSize;\r
-  VOID              *ApFunction;\r
-  IA32_DESCRIPTOR   GdtrProfile;\r
-  IA32_DESCRIPTOR   IdtrProfile;\r
-  UINT32            BufferStart;\r
-  UINT32            Cr3;\r
-  UINTN             InitializeFloatingPointUnitsAddress;\r
+  UINTN              Lock;\r
+  VOID               *StackStart;\r
+  UINTN              StackSize;\r
+  VOID               *ApFunction;\r
+  IA32_DESCRIPTOR    GdtrProfile;\r
+  IA32_DESCRIPTOR    IdtrProfile;\r
+  UINT32             BufferStart;\r
+  UINT32             Cr3;\r
+  UINTN              InitializeFloatingPointUnitsAddress;\r
 } MP_CPU_EXCHANGE_INFO;\r
 #pragma pack()\r
 \r
 typedef struct {\r
-  UINT8 *RendezvousFunnelAddress;\r
-  UINTN PModeEntryOffset;\r
-  UINTN FlatJumpOffset;\r
-  UINTN Size;\r
-  UINTN LModeEntryOffset;\r
-  UINTN LongJumpOffset;\r
+  UINT8    *RendezvousFunnelAddress;\r
+  UINTN    PModeEntryOffset;\r
+  UINTN    FlatJumpOffset;\r
+  UINTN    Size;\r
+  UINTN    LModeEntryOffset;\r
+  UINTN    LongJumpOffset;\r
 } MP_ASSEMBLY_ADDRESS_MAP;\r
 \r
 //\r
 // Flags used when program the register.\r
 //\r
 typedef struct {\r
-  volatile UINTN           MemoryMappedLock;        // Spinlock used to program mmio\r
-  volatile UINT32          *CoreSemaphoreCount;     // Semaphore container used to program\r
+  volatile UINTN     MemoryMappedLock;              // Spinlock used to program mmio\r
+  volatile UINT32    *CoreSemaphoreCount;           // Semaphore container used to program\r
                                                     // core level semaphore.\r
-  volatile UINT32          *PackageSemaphoreCount;  // Semaphore container used to program\r
+  volatile UINT32    *PackageSemaphoreCount;        // Semaphore container used to program\r
                                                     // package level semaphore.\r
 } PROGRAM_CPU_REGISTER_FLAGS;\r
 \r
 //\r
 // Signal that SMM BASE relocation is complete.\r
 //\r
-volatile BOOLEAN         mInitApsAfterSmmBaseReloc;\r
+volatile BOOLEAN  mInitApsAfterSmmBaseReloc;\r
 \r
 /**\r
   Get starting address and size of the rendezvous entry for APs.\r
@@ -56,38 +56,38 @@ volatile BOOLEAN         mInitApsAfterSmmBaseReloc;
 VOID *\r
 EFIAPI\r
 AsmGetAddressMap (\r
-  MP_ASSEMBLY_ADDRESS_MAP                     *AddressMap\r
+  MP_ASSEMBLY_ADDRESS_MAP  *AddressMap\r
   );\r
 \r
-#define LEGACY_REGION_SIZE    (2 * 0x1000)\r
-#define LEGACY_REGION_BASE    (0xA0000 - LEGACY_REGION_SIZE)\r
+#define LEGACY_REGION_SIZE  (2 * 0x1000)\r
+#define LEGACY_REGION_BASE  (0xA0000 - LEGACY_REGION_SIZE)\r
 \r
-PROGRAM_CPU_REGISTER_FLAGS   mCpuFlags;\r
-ACPI_CPU_DATA                mAcpiCpuData;\r
-volatile UINT32              mNumberToFinish;\r
-MP_CPU_EXCHANGE_INFO         *mExchangeInfo;\r
-BOOLEAN                      mRestoreSmmConfigurationInS3 = FALSE;\r
+PROGRAM_CPU_REGISTER_FLAGS  mCpuFlags;\r
+ACPI_CPU_DATA               mAcpiCpuData;\r
+volatile UINT32             mNumberToFinish;\r
+MP_CPU_EXCHANGE_INFO        *mExchangeInfo;\r
+BOOLEAN                     mRestoreSmmConfigurationInS3 = FALSE;\r
 \r
 //\r
 // S3 boot flag\r
 //\r
-BOOLEAN                      mSmmS3Flag = FALSE;\r
+BOOLEAN  mSmmS3Flag = FALSE;\r
 \r
 //\r
 // Pointer to structure used during S3 Resume\r
 //\r
-SMM_S3_RESUME_STATE          *mSmmS3ResumeState = NULL;\r
+SMM_S3_RESUME_STATE  *mSmmS3ResumeState = NULL;\r
 \r
-BOOLEAN                      mAcpiS3Enable = TRUE;\r
+BOOLEAN  mAcpiS3Enable = TRUE;\r
 \r
-UINT8                        *mApHltLoopCode = NULL;\r
-UINT8                        mApHltLoopCodeTemplate[] = {\r
-                               0x8B, 0x44, 0x24, 0x04,  // mov  eax, dword ptr [esp+4]\r
-                               0xF0, 0xFF, 0x08,        // lock dec  dword ptr [eax]\r
-                               0xFA,                    // cli\r
-                               0xF4,                    // hlt\r
-                               0xEB, 0xFC               // jmp $-2\r
-                               };\r
+UINT8  *mApHltLoopCode          = NULL;\r
+UINT8  mApHltLoopCodeTemplate[] = {\r
+  0x8B, 0x44, 0x24, 0x04, // mov  eax, dword ptr [esp+4]\r
+  0xF0, 0xFF, 0x08,       // lock dec  dword ptr [eax]\r
+  0xFA,                   // cli\r
+  0xF4,                   // hlt\r
+  0xEB, 0xFC              // jmp $-2\r
+};\r
 \r
 /**\r
   Sync up the MTRR values for all processors.\r
@@ -97,8 +97,9 @@ UINT8                        mApHltLoopCodeTemplate[] = {
 VOID\r
 EFIAPI\r
 LoadMtrrData (\r
-  EFI_PHYSICAL_ADDRESS       MtrrTable\r
+  EFI_PHYSICAL_ADDRESS  MtrrTable\r
   )\r
+\r
 /*++\r
 \r
 Routine Description:\r
@@ -112,9 +113,9 @@ Returns:
 \r
 --*/\r
 {\r
-  MTRR_SETTINGS   *MtrrSettings;\r
+  MTRR_SETTINGS  *MtrrSettings;\r
 \r
-  MtrrSettings = (MTRR_SETTINGS *) (UINTN) MtrrTable;\r
+  MtrrSettings = (MTRR_SETTINGS *)(UINTN)MtrrTable;\r
   MtrrSetAllMtrrs (MtrrSettings);\r
 }\r
 \r
@@ -126,7 +127,7 @@ Returns:
 **/\r
 VOID\r
 S3ReleaseSemaphore (\r
-  IN OUT  volatile UINT32           *Sem\r
+  IN OUT  volatile UINT32  *Sem\r
   )\r
 {\r
   InterlockedIncrement (Sem);\r
@@ -144,7 +145,7 @@ S3ReleaseSemaphore (
 **/\r
 VOID\r
 S3WaitForSemaphore (\r
-  IN OUT  volatile UINT32           *Sem\r
+  IN OUT  volatile UINT32  *Sem\r
   )\r
 {\r
   UINT32  Value;\r
@@ -170,42 +171,46 @@ S3WaitForSemaphore (
 **/\r
 UINTN\r
 ReadWriteCr (\r
-  IN     UINT32       CrIndex,\r
-  IN     BOOLEAN      Read,\r
-  IN OUT UINTN        *CrValue\r
+  IN     UINT32   CrIndex,\r
+  IN     BOOLEAN  Read,\r
+  IN OUT UINTN    *CrValue\r
   )\r
 {\r
   switch (CrIndex) {\r
-  case 0:\r
-    if (Read) {\r
-      *CrValue = AsmReadCr0 ();\r
-    } else {\r
-      AsmWriteCr0 (*CrValue);\r
-    }\r
-    break;\r
-  case 2:\r
-    if (Read) {\r
-      *CrValue = AsmReadCr2 ();\r
-    } else {\r
-      AsmWriteCr2 (*CrValue);\r
-    }\r
-    break;\r
-  case 3:\r
-    if (Read) {\r
-      *CrValue = AsmReadCr3 ();\r
-    } else {\r
-      AsmWriteCr3 (*CrValue);\r
-    }\r
-    break;\r
-  case 4:\r
-    if (Read) {\r
-      *CrValue = AsmReadCr4 ();\r
-    } else {\r
-      AsmWriteCr4 (*CrValue);\r
-    }\r
-    break;\r
-  default:\r
-    return EFI_UNSUPPORTED;;\r
+    case 0:\r
+      if (Read) {\r
+        *CrValue = AsmReadCr0 ();\r
+      } else {\r
+        AsmWriteCr0 (*CrValue);\r
+      }\r
+\r
+      break;\r
+    case 2:\r
+      if (Read) {\r
+        *CrValue = AsmReadCr2 ();\r
+      } else {\r
+        AsmWriteCr2 (*CrValue);\r
+      }\r
+\r
+      break;\r
+    case 3:\r
+      if (Read) {\r
+        *CrValue = AsmReadCr3 ();\r
+      } else {\r
+        AsmWriteCr3 (*CrValue);\r
+      }\r
+\r
+      break;\r
+    case 4:\r
+      if (Read) {\r
+        *CrValue = AsmReadCr4 ();\r
+      } else {\r
+        AsmWriteCr4 (*CrValue);\r
+      }\r
+\r
+      break;\r
+    default:\r
+      return EFI_UNSUPPORTED;\r
   }\r
 \r
   return EFI_SUCCESS;\r
@@ -223,10 +228,10 @@ ReadWriteCr (
 **/\r
 VOID\r
 ProgramProcessorRegister (\r
-  IN CPU_REGISTER_TABLE           *RegisterTable,\r
-  IN EFI_CPU_PHYSICAL_LOCATION    *ApLocation,\r
-  IN CPU_STATUS_INFORMATION       *CpuStatus,\r
-  IN PROGRAM_CPU_REGISTER_FLAGS   *CpuFlags\r
+  IN CPU_REGISTER_TABLE          *RegisterTable,\r
+  IN EFI_CPU_PHYSICAL_LOCATION   *ApLocation,\r
+  IN CPU_STATUS_INFORMATION      *CpuStatus,\r
+  IN PROGRAM_CPU_REGISTER_FLAGS  *CpuFlags\r
   )\r
 {\r
   CPU_REGISTER_TABLE_ENTRY  *RegisterTableEntry;\r
@@ -246,53 +251,25 @@ ProgramProcessorRegister (
   //\r
   // Traverse Register Table of this logical processor\r
   //\r
-  RegisterTableEntryHead = (CPU_REGISTER_TABLE_ENTRY *) (UINTN) RegisterTable->RegisterTableEntry;\r
+  RegisterTableEntryHead = (CPU_REGISTER_TABLE_ENTRY *)(UINTN)RegisterTable->RegisterTableEntry;\r
 \r
   for (Index = 0; Index < RegisterTable->TableLength; Index++) {\r
-\r
     RegisterTableEntry = &RegisterTableEntryHead[Index];\r
 \r
     //\r
     // Check the type of specified register\r
     //\r
     switch (RegisterTableEntry->RegisterType) {\r
-    //\r
-    // The specified register is Control Register\r
-    //\r
-    case ControlRegister:\r
-      Status = ReadWriteCr (RegisterTableEntry->Index, TRUE, &Value);\r
-      if (EFI_ERROR (Status)) {\r
-        break;\r
-      }\r
-      if (RegisterTableEntry->TestThenWrite) {\r
-        CurrentValue = BitFieldRead64 (\r
-                         Value,\r
-                         RegisterTableEntry->ValidBitStart,\r
-                         RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1\r
-                         );\r
-        if (CurrentValue == RegisterTableEntry->Value) {\r
+      //\r
+      // The specified register is Control Register\r
+      //\r
+      case ControlRegister:\r
+        Status = ReadWriteCr (RegisterTableEntry->Index, TRUE, &Value);\r
+        if (EFI_ERROR (Status)) {\r
           break;\r
         }\r
-      }\r
-      Value = (UINTN) BitFieldWrite64 (\r
-                        Value,\r
-                        RegisterTableEntry->ValidBitStart,\r
-                        RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1,\r
-                        RegisterTableEntry->Value\r
-                        );\r
-      ReadWriteCr (RegisterTableEntry->Index, FALSE, &Value);\r
-      break;\r
-    //\r
-    // The specified register is Model Specific Register\r
-    //\r
-    case Msr:\r
-      if (RegisterTableEntry->TestThenWrite) {\r
-        Value = (UINTN)AsmReadMsr64 (RegisterTableEntry->Index);\r
-        if (RegisterTableEntry->ValidBitLength >= 64) {\r
-          if (Value == RegisterTableEntry->Value) {\r
-            break;\r
-          }\r
-        } else {\r
+\r
+        if (RegisterTableEntry->TestThenWrite) {\r
           CurrentValue = BitFieldRead64 (\r
                            Value,\r
                            RegisterTableEntry->ValidBitStart,\r
@@ -302,164 +279,200 @@ ProgramProcessorRegister (
             break;\r
           }\r
         }\r
-      }\r
 \r
+        Value = (UINTN)BitFieldWrite64 (\r
+                         Value,\r
+                         RegisterTableEntry->ValidBitStart,\r
+                         RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1,\r
+                         RegisterTableEntry->Value\r
+                         );\r
+        ReadWriteCr (RegisterTableEntry->Index, FALSE, &Value);\r
+        break;\r
       //\r
-      // If this function is called to restore register setting after INIT signal,\r
-      // there is no need to restore MSRs in register table.\r
+      // The specified register is Model Specific Register\r
       //\r
-      if (RegisterTableEntry->ValidBitLength >= 64) {\r
-        //\r
-        // If length is not less than 64 bits, then directly write without reading\r
-        //\r
-        AsmWriteMsr64 (\r
-          RegisterTableEntry->Index,\r
-          RegisterTableEntry->Value\r
-          );\r
-      } else {\r
+      case Msr:\r
+        if (RegisterTableEntry->TestThenWrite) {\r
+          Value = (UINTN)AsmReadMsr64 (RegisterTableEntry->Index);\r
+          if (RegisterTableEntry->ValidBitLength >= 64) {\r
+            if (Value == RegisterTableEntry->Value) {\r
+              break;\r
+            }\r
+          } else {\r
+            CurrentValue = BitFieldRead64 (\r
+                             Value,\r
+                             RegisterTableEntry->ValidBitStart,\r
+                             RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1\r
+                             );\r
+            if (CurrentValue == RegisterTableEntry->Value) {\r
+              break;\r
+            }\r
+          }\r
+        }\r
+\r
         //\r
-        // Set the bit section according to bit start and length\r
+        // If this function is called to restore register setting after INIT signal,\r
+        // there is no need to restore MSRs in register table.\r
         //\r
-        AsmMsrBitFieldWrite64 (\r
-          RegisterTableEntry->Index,\r
-          RegisterTableEntry->ValidBitStart,\r
-          RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1,\r
-          RegisterTableEntry->Value\r
-          );\r
-      }\r
-      break;\r
-    //\r
-    // MemoryMapped operations\r
-    //\r
-    case MemoryMapped:\r
-      AcquireSpinLock (&CpuFlags->MemoryMappedLock);\r
-      MmioBitFieldWrite32 (\r
-        (UINTN)(RegisterTableEntry->Index | LShiftU64 (RegisterTableEntry->HighIndex, 32)),\r
-        RegisterTableEntry->ValidBitStart,\r
-        RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1,\r
-        (UINT32)RegisterTableEntry->Value\r
-        );\r
-      ReleaseSpinLock (&CpuFlags->MemoryMappedLock);\r
-      break;\r
-    //\r
-    // Enable or disable cache\r
-    //\r
-    case CacheControl:\r
-      //\r
-      // If value of the entry is 0, then disable cache.  Otherwise, enable cache.\r
-      //\r
-      if (RegisterTableEntry->Value == 0) {\r
-        AsmDisableCache ();\r
-      } else {\r
-        AsmEnableCache ();\r
-      }\r
-      break;\r
+        if (RegisterTableEntry->ValidBitLength >= 64) {\r
+          //\r
+          // If length is not less than 64 bits, then directly write without reading\r
+          //\r
+          AsmWriteMsr64 (\r
+            RegisterTableEntry->Index,\r
+            RegisterTableEntry->Value\r
+            );\r
+        } else {\r
+          //\r
+          // Set the bit section according to bit start and length\r
+          //\r
+          AsmMsrBitFieldWrite64 (\r
+            RegisterTableEntry->Index,\r
+            RegisterTableEntry->ValidBitStart,\r
+            RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1,\r
+            RegisterTableEntry->Value\r
+            );\r
+        }\r
 \r
-    case Semaphore:\r
-      // Semaphore works logic like below:\r
-      //\r
-      //  V(x) = LibReleaseSemaphore (Semaphore[FirstThread + x]);\r
-      //  P(x) = LibWaitForSemaphore (Semaphore[FirstThread + x]);\r
-      //\r
-      //  All threads (T0...Tn) waits in P() line and continues running\r
-      //  together.\r
+        break;\r
       //\r
+      // MemoryMapped operations\r
       //\r
-      //  T0             T1            ...           Tn\r
+      case MemoryMapped:\r
+        AcquireSpinLock (&CpuFlags->MemoryMappedLock);\r
+        MmioBitFieldWrite32 (\r
+          (UINTN)(RegisterTableEntry->Index | LShiftU64 (RegisterTableEntry->HighIndex, 32)),\r
+          RegisterTableEntry->ValidBitStart,\r
+          RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1,\r
+          (UINT32)RegisterTableEntry->Value\r
+          );\r
+        ReleaseSpinLock (&CpuFlags->MemoryMappedLock);\r
+        break;\r
       //\r
-      //  V(0...n)       V(0...n)      ...           V(0...n)\r
-      //  n * P(0)       n * P(1)      ...           n * P(n)\r
+      // Enable or disable cache\r
       //\r
-      ASSERT (\r
-        (ApLocation != NULL) &&\r
-        (CpuStatus->ThreadCountPerPackage != 0) &&\r
-        (CpuStatus->ThreadCountPerCore != 0) &&\r
-        (CpuFlags->CoreSemaphoreCount != NULL) &&\r
-        (CpuFlags->PackageSemaphoreCount != NULL)\r
-        );\r
-      switch (RegisterTableEntry->Value) {\r
-      case CoreDepType:\r
-        SemaphorePtr = CpuFlags->CoreSemaphoreCount;\r
-        ThreadCountPerCore = (UINT8 *)(UINTN)CpuStatus->ThreadCountPerCore;\r
-\r
-        CurrentCore = ApLocation->Package * CpuStatus->MaxCoreCount + ApLocation->Core;\r
-        //\r
-        // Get Offset info for the first thread in the core which current thread belongs to.\r
+      case CacheControl:\r
         //\r
-        FirstThread   = CurrentCore * CpuStatus->MaxThreadCount;\r
-        CurrentThread = FirstThread + ApLocation->Thread;\r
-\r
-        //\r
-        // Different cores may have different valid threads in them. If driver maintail clearly\r
-        // thread index in different cores, the logic will be much complicated.\r
-        // Here driver just simply records the max thread number in all cores and use it as expect\r
-        // thread number for all cores.\r
-        // In below two steps logic, first current thread will Release semaphore for each thread\r
-        // in current core. Maybe some threads are not valid in this core, but driver don't\r
-        // care. Second, driver will let current thread wait semaphore for all valid threads in\r
-        // current core. Because only the valid threads will do release semaphore for this\r
-        // thread, driver here only need to wait the valid thread count.\r
-        //\r
-\r
+        // If value of the entry is 0, then disable cache.  Otherwise, enable cache.\r
         //\r
-        // First Notify ALL THREADs in current Core that this thread is ready.\r
-        //\r
-        for (ProcessorIndex = 0; ProcessorIndex < CpuStatus->MaxThreadCount; ProcessorIndex ++) {\r
-          S3ReleaseSemaphore (&SemaphorePtr[FirstThread + ProcessorIndex]);\r
-        }\r
-        //\r
-        // Second, check whether all VALID THREADs (not all threads) in current core are ready.\r
-        //\r
-        for (ProcessorIndex = 0; ProcessorIndex < ThreadCountPerCore[CurrentCore]; ProcessorIndex ++) {\r
-          S3WaitForSemaphore (&SemaphorePtr[CurrentThread]);\r
+        if (RegisterTableEntry->Value == 0) {\r
+          AsmDisableCache ();\r
+        } else {\r
+          AsmEnableCache ();\r
         }\r
+\r
         break;\r
 \r
-      case PackageDepType:\r
-        SemaphorePtr = CpuFlags->PackageSemaphoreCount;\r
-        ThreadCountPerPackage = (UINT32 *)(UINTN)CpuStatus->ThreadCountPerPackage;\r
+      case Semaphore:\r
+        // Semaphore works logic like below:\r
         //\r
-        // Get Offset info for the first thread in the package which current thread belongs to.\r
+        //  V(x) = LibReleaseSemaphore (Semaphore[FirstThread + x]);\r
+        //  P(x) = LibWaitForSemaphore (Semaphore[FirstThread + x]);\r
         //\r
-        FirstThread = ApLocation->Package * CpuStatus->MaxCoreCount * CpuStatus->MaxThreadCount;\r
+        //  All threads (T0...Tn) waits in P() line and continues running\r
+        //  together.\r
         //\r
-        // Get the possible threads count for current package.\r
         //\r
-        CurrentThread = FirstThread + CpuStatus->MaxThreadCount * ApLocation->Core + ApLocation->Thread;\r
-\r
+        //  T0             T1            ...           Tn\r
         //\r
-        // Different packages may have different valid threads in them. If driver maintail clearly\r
-        // thread index in different packages, the logic will be much complicated.\r
-        // Here driver just simply records the max thread number in all packages and use it as expect\r
-        // thread number for all packages.\r
-        // In below two steps logic, first current thread will Release semaphore for each thread\r
-        // in current package. Maybe some threads are not valid in this package, but driver don't\r
-        // care. Second, driver will let current thread wait semaphore for all valid threads in\r
-        // current package. Because only the valid threads will do release semaphore for this\r
-        // thread, driver here only need to wait the valid thread count.\r
+        //  V(0...n)       V(0...n)      ...           V(0...n)\r
+        //  n * P(0)       n * P(1)      ...           n * P(n)\r
         //\r
+        ASSERT (\r
+          (ApLocation != NULL) &&\r
+          (CpuStatus->ThreadCountPerPackage != 0) &&\r
+          (CpuStatus->ThreadCountPerCore != 0) &&\r
+          (CpuFlags->CoreSemaphoreCount != NULL) &&\r
+          (CpuFlags->PackageSemaphoreCount != NULL)\r
+          );\r
+        switch (RegisterTableEntry->Value) {\r
+          case CoreDepType:\r
+            SemaphorePtr       = CpuFlags->CoreSemaphoreCount;\r
+            ThreadCountPerCore = (UINT8 *)(UINTN)CpuStatus->ThreadCountPerCore;\r
+\r
+            CurrentCore = ApLocation->Package * CpuStatus->MaxCoreCount + ApLocation->Core;\r
+            //\r
+            // Get Offset info for the first thread in the core which current thread belongs to.\r
+            //\r
+            FirstThread   = CurrentCore * CpuStatus->MaxThreadCount;\r
+            CurrentThread = FirstThread + ApLocation->Thread;\r
+\r
+            //\r
+            // Different cores may have different valid threads in them. If driver maintail clearly\r
+            // thread index in different cores, the logic will be much complicated.\r
+            // Here driver just simply records the max thread number in all cores and use it as expect\r
+            // thread number for all cores.\r
+            // In below two steps logic, first current thread will Release semaphore for each thread\r
+            // in current core. Maybe some threads are not valid in this core, but driver don't\r
+            // care. Second, driver will let current thread wait semaphore for all valid threads in\r
+            // current core. Because only the valid threads will do release semaphore for this\r
+            // thread, driver here only need to wait the valid thread count.\r
+            //\r
+\r
+            //\r
+            // First Notify ALL THREADs in current Core that this thread is ready.\r
+            //\r
+            for (ProcessorIndex = 0; ProcessorIndex < CpuStatus->MaxThreadCount; ProcessorIndex++) {\r
+              S3ReleaseSemaphore (&SemaphorePtr[FirstThread + ProcessorIndex]);\r
+            }\r
+\r
+            //\r
+            // Second, check whether all VALID THREADs (not all threads) in current core are ready.\r
+            //\r
+            for (ProcessorIndex = 0; ProcessorIndex < ThreadCountPerCore[CurrentCore]; ProcessorIndex++) {\r
+              S3WaitForSemaphore (&SemaphorePtr[CurrentThread]);\r
+            }\r
 \r
-        //\r
-        // First Notify ALL THREADS in current package that this thread is ready.\r
-        //\r
-        for (ProcessorIndex = 0; ProcessorIndex < CpuStatus->MaxThreadCount * CpuStatus->MaxCoreCount; ProcessorIndex ++) {\r
-          S3ReleaseSemaphore (&SemaphorePtr[FirstThread + ProcessorIndex]);\r
-        }\r
-        //\r
-        // Second, check whether VALID THREADS (not all threads) in current package are ready.\r
-        //\r
-        for (ProcessorIndex = 0; ProcessorIndex < ThreadCountPerPackage[ApLocation->Package]; ProcessorIndex ++) {\r
-          S3WaitForSemaphore (&SemaphorePtr[CurrentThread]);\r
+            break;\r
+\r
+          case PackageDepType:\r
+            SemaphorePtr          = CpuFlags->PackageSemaphoreCount;\r
+            ThreadCountPerPackage = (UINT32 *)(UINTN)CpuStatus->ThreadCountPerPackage;\r
+            //\r
+            // Get Offset info for the first thread in the package which current thread belongs to.\r
+            //\r
+            FirstThread = ApLocation->Package * CpuStatus->MaxCoreCount * CpuStatus->MaxThreadCount;\r
+            //\r
+            // Get the possible threads count for current package.\r
+            //\r
+            CurrentThread = FirstThread + CpuStatus->MaxThreadCount * ApLocation->Core + ApLocation->Thread;\r
+\r
+            //\r
+            // Different packages may have different valid threads in them. If driver maintail clearly\r
+            // thread index in different packages, the logic will be much complicated.\r
+            // Here driver just simply records the max thread number in all packages and use it as expect\r
+            // thread number for all packages.\r
+            // In below two steps logic, first current thread will Release semaphore for each thread\r
+            // in current package. Maybe some threads are not valid in this package, but driver don't\r
+            // care. Second, driver will let current thread wait semaphore for all valid threads in\r
+            // current package. Because only the valid threads will do release semaphore for this\r
+            // thread, driver here only need to wait the valid thread count.\r
+            //\r
+\r
+            //\r
+            // First Notify ALL THREADS in current package that this thread is ready.\r
+            //\r
+            for (ProcessorIndex = 0; ProcessorIndex < CpuStatus->MaxThreadCount * CpuStatus->MaxCoreCount; ProcessorIndex++) {\r
+              S3ReleaseSemaphore (&SemaphorePtr[FirstThread + ProcessorIndex]);\r
+            }\r
+\r
+            //\r
+            // Second, check whether VALID THREADS (not all threads) in current package are ready.\r
+            //\r
+            for (ProcessorIndex = 0; ProcessorIndex < ThreadCountPerPackage[ApLocation->Package]; ProcessorIndex++) {\r
+              S3WaitForSemaphore (&SemaphorePtr[CurrentThread]);\r
+            }\r
+\r
+            break;\r
+\r
+          default:\r
+            break;\r
         }\r
+\r
         break;\r
 \r
       default:\r
         break;\r
-      }\r
-      break;\r
-\r
-    default:\r
-      break;\r
     }\r
   }\r
 }\r
@@ -473,15 +486,15 @@ ProgramProcessorRegister (
 **/\r
 VOID\r
 SetRegister (\r
-  IN BOOLEAN                 PreSmmRegisterTable\r
+  IN BOOLEAN  PreSmmRegisterTable\r
   )\r
 {\r
-  CPU_FEATURE_INIT_DATA     *FeatureInitData;\r
-  CPU_REGISTER_TABLE        *RegisterTable;\r
-  CPU_REGISTER_TABLE        *RegisterTables;\r
-  UINT32                    InitApicId;\r
-  UINTN                     ProcIndex;\r
-  UINTN                     Index;\r
+  CPU_FEATURE_INIT_DATA  *FeatureInitData;\r
+  CPU_REGISTER_TABLE     *RegisterTable;\r
+  CPU_REGISTER_TABLE     *RegisterTables;\r
+  UINT32                 InitApicId;\r
+  UINTN                  ProcIndex;\r
+  UINTN                  Index;\r
 \r
   FeatureInitData = &mAcpiCpuData.CpuFeatureInitData;\r
 \r
@@ -490,20 +503,22 @@ SetRegister (
   } else {\r
     RegisterTables = (CPU_REGISTER_TABLE *)(UINTN)FeatureInitData->RegisterTable;\r
   }\r
+\r
   if (RegisterTables == NULL) {\r
     return;\r
   }\r
 \r
-  InitApicId = GetInitialApicId ();\r
+  InitApicId    = GetInitialApicId ();\r
   RegisterTable = NULL;\r
-  ProcIndex = (UINTN)-1;\r
+  ProcIndex     = (UINTN)-1;\r
   for (Index = 0; Index < mAcpiCpuData.NumberOfCpus; Index++) {\r
     if (RegisterTables[Index].InitialApicId == InitApicId) {\r
       RegisterTable = &RegisterTables[Index];\r
-      ProcIndex = Index;\r
+      ProcIndex     = Index;\r
       break;\r
     }\r
   }\r
+\r
   ASSERT (RegisterTable != NULL);\r
 \r
   if (FeatureInitData->ApLocation != 0) {\r
@@ -531,8 +546,8 @@ InitializeAp (
   VOID\r
   )\r
 {\r
-  UINTN                      TopOfStack;\r
-  UINT8                      Stack[128];\r
+  UINTN  TopOfStack;\r
+  UINT8  Stack[128];\r
 \r
   LoadMtrrData (mAcpiCpuData.MtrrTable);\r
 \r
@@ -558,9 +573,9 @@ InitializeAp (
   //\r
   // Place AP into the safe code, count down the number with lock mechanism in the safe code.\r
   //\r
-  TopOfStack  = (UINTN) Stack + sizeof (Stack);\r
-  TopOfStack &= ~(UINTN) (CPU_STACK_ALIGNMENT - 1);\r
-  CopyMem ((VOID *) (UINTN) mApHltLoopCode, mApHltLoopCodeTemplate, sizeof (mApHltLoopCodeTemplate));\r
+  TopOfStack  = (UINTN)Stack + sizeof (Stack);\r
+  TopOfStack &= ~(UINTN)(CPU_STACK_ALIGNMENT - 1);\r
+  CopyMem ((VOID *)(UINTN)mApHltLoopCode, mApHltLoopCodeTemplate, sizeof (mApHltLoopCodeTemplate));\r
   TransferApToSafeState ((UINTN)mApHltLoopCode, TopOfStack, (UINTN)&mNumberToFinish);\r
 }\r
 \r
@@ -576,8 +591,8 @@ PrepareApStartupVector (
   EFI_PHYSICAL_ADDRESS  WorkingBuffer\r
   )\r
 {\r
-  EFI_PHYSICAL_ADDRESS                        StartupVector;\r
-  MP_ASSEMBLY_ADDRESS_MAP                     AddressMap;\r
+  EFI_PHYSICAL_ADDRESS     StartupVector;\r
+  MP_ASSEMBLY_ADDRESS_MAP  AddressMap;\r
 \r
   //\r
   // Get the address map of startup code for AP,\r
@@ -592,25 +607,25 @@ PrepareApStartupVector (
   // Copy AP startup code to startup vector, and then redirect the long jump\r
   // instructions for mode switching.\r
   //\r
-  CopyMem ((VOID *) (UINTN) StartupVector, AddressMap.RendezvousFunnelAddress, AddressMap.Size);\r
-  *(UINT32 *) (UINTN) (StartupVector + AddressMap.FlatJumpOffset + 3) = (UINT32) (StartupVector + AddressMap.PModeEntryOffset);\r
+  CopyMem ((VOID *)(UINTN)StartupVector, AddressMap.RendezvousFunnelAddress, AddressMap.Size);\r
+  *(UINT32 *)(UINTN)(StartupVector + AddressMap.FlatJumpOffset + 3) = (UINT32)(StartupVector + AddressMap.PModeEntryOffset);\r
   if (AddressMap.LongJumpOffset != 0) {\r
-    *(UINT32 *) (UINTN) (StartupVector + AddressMap.LongJumpOffset + 2) = (UINT32) (StartupVector + AddressMap.LModeEntryOffset);\r
+    *(UINT32 *)(UINTN)(StartupVector + AddressMap.LongJumpOffset + 2) = (UINT32)(StartupVector + AddressMap.LModeEntryOffset);\r
   }\r
 \r
   //\r
   // Get the start address of exchange data between BSP and AP.\r
   //\r
-  mExchangeInfo = (MP_CPU_EXCHANGE_INFO *) (UINTN) (StartupVector + AddressMap.Size);\r
-  ZeroMem ((VOID *) mExchangeInfo, sizeof (MP_CPU_EXCHANGE_INFO));\r
+  mExchangeInfo = (MP_CPU_EXCHANGE_INFO *)(UINTN)(StartupVector + AddressMap.Size);\r
+  ZeroMem ((VOID *)mExchangeInfo, sizeof (MP_CPU_EXCHANGE_INFO));\r
 \r
-  CopyMem ((VOID *) (UINTN) &mExchangeInfo->GdtrProfile, (VOID *) (UINTN) mAcpiCpuData.GdtrProfile, sizeof (IA32_DESCRIPTOR));\r
-  CopyMem ((VOID *) (UINTN) &mExchangeInfo->IdtrProfile, (VOID *) (UINTN) mAcpiCpuData.IdtrProfile, sizeof (IA32_DESCRIPTOR));\r
+  CopyMem ((VOID *)(UINTN)&mExchangeInfo->GdtrProfile, (VOID *)(UINTN)mAcpiCpuData.GdtrProfile, sizeof (IA32_DESCRIPTOR));\r
+  CopyMem ((VOID *)(UINTN)&mExchangeInfo->IdtrProfile, (VOID *)(UINTN)mAcpiCpuData.IdtrProfile, sizeof (IA32_DESCRIPTOR));\r
 \r
-  mExchangeInfo->StackStart  = (VOID *) (UINTN) mAcpiCpuData.StackAddress;\r
-  mExchangeInfo->StackSize   = mAcpiCpuData.StackSize;\r
-  mExchangeInfo->BufferStart = (UINT32) StartupVector;\r
-  mExchangeInfo->Cr3         = (UINT32) (AsmReadCr3 ());\r
+  mExchangeInfo->StackStart                          = (VOID *)(UINTN)mAcpiCpuData.StackAddress;\r
+  mExchangeInfo->StackSize                           = mAcpiCpuData.StackSize;\r
+  mExchangeInfo->BufferStart                         = (UINT32)StartupVector;\r
+  mExchangeInfo->Cr3                                 = (UINT32)(AsmReadCr3 ());\r
   mExchangeInfo->InitializeFloatingPointUnitsAddress = (UINTN)InitializeFloatingPointUnits;\r
 }\r
 \r
@@ -639,8 +654,9 @@ InitializeCpuBeforeRebase (
   } else {\r
     ASSERT (mNumberOfCpus == mAcpiCpuData.NumberOfCpus);\r
   }\r
-  mNumberToFinish = (UINT32)(mNumberOfCpus - 1);\r
-  mExchangeInfo->ApFunction  = (VOID *) (UINTN) InitializeAp;\r
+\r
+  mNumberToFinish           = (UINT32)(mNumberOfCpus - 1);\r
+  mExchangeInfo->ApFunction = (VOID *)(UINTN)InitializeAp;\r
 \r
   //\r
   // Execute code for before SmmBaseReloc. Note: This flag is maintained across S3 boots.\r
@@ -674,6 +690,7 @@ InitializeCpuAfterRebase (
   } else {\r
     ASSERT (mNumberOfCpus == mAcpiCpuData.NumberOfCpus);\r
   }\r
+\r
   mNumberToFinish = (UINT32)(mNumberOfCpus - 1);\r
 \r
   //\r
@@ -745,11 +762,11 @@ SmmRestoreCpu (
   VOID\r
   )\r
 {\r
-  SMM_S3_RESUME_STATE           *SmmS3ResumeState;\r
-  IA32_DESCRIPTOR               Ia32Idtr;\r
-  IA32_DESCRIPTOR               X64Idtr;\r
-  IA32_IDT_GATE_DESCRIPTOR      IdtEntryTable[EXCEPTION_VECTOR_NUMBER];\r
-  EFI_STATUS                    Status;\r
+  SMM_S3_RESUME_STATE       *SmmS3ResumeState;\r
+  IA32_DESCRIPTOR           Ia32Idtr;\r
+  IA32_DESCRIPTOR           X64Idtr;\r
+  IA32_IDT_GATE_DESCRIPTOR  IdtEntryTable[EXCEPTION_VECTOR_NUMBER];\r
+  EFI_STATUS                Status;\r
 \r
   DEBUG ((DEBUG_INFO, "SmmRestoreCpu()\n"));\r
 \r
@@ -770,15 +787,15 @@ SmmRestoreCpu (
     //\r
     // Save the IA32 IDT Descriptor\r
     //\r
-    AsmReadIdtr ((IA32_DESCRIPTOR *) &Ia32Idtr);\r
+    AsmReadIdtr ((IA32_DESCRIPTOR *)&Ia32Idtr);\r
 \r
     //\r
     // Setup X64 IDT table\r
     //\r
     ZeroMem (IdtEntryTable, sizeof (IA32_IDT_GATE_DESCRIPTOR) * 32);\r
-    X64Idtr.Base = (UINTN) IdtEntryTable;\r
-    X64Idtr.Limit = (UINT16) (sizeof (IA32_IDT_GATE_DESCRIPTOR) * 32 - 1);\r
-    AsmWriteIdtr ((IA32_DESCRIPTOR *) &X64Idtr);\r
+    X64Idtr.Base  = (UINTN)IdtEntryTable;\r
+    X64Idtr.Limit = (UINT16)(sizeof (IA32_IDT_GATE_DESCRIPTOR) * 32 - 1);\r
+    AsmWriteIdtr ((IA32_DESCRIPTOR *)&X64Idtr);\r
 \r
     //\r
     // Setup the default exception handler\r
@@ -822,11 +839,11 @@ SmmRestoreCpu (
   //\r
   mRestoreSmmConfigurationInS3 = TRUE;\r
 \r
-  DEBUG (( DEBUG_INFO, "SMM S3 Return CS                = %x\n", SmmS3ResumeState->ReturnCs));\r
-  DEBUG (( DEBUG_INFO, "SMM S3 Return Entry Point       = %x\n", SmmS3ResumeState->ReturnEntryPoint));\r
-  DEBUG (( DEBUG_INFO, "SMM S3 Return Context1          = %x\n", SmmS3ResumeState->ReturnContext1));\r
-  DEBUG (( DEBUG_INFO, "SMM S3 Return Context2          = %x\n", SmmS3ResumeState->ReturnContext2));\r
-  DEBUG (( DEBUG_INFO, "SMM S3 Return Stack Pointer     = %x\n", SmmS3ResumeState->ReturnStackPointer));\r
+  DEBUG ((DEBUG_INFO, "SMM S3 Return CS                = %x\n", SmmS3ResumeState->ReturnCs));\r
+  DEBUG ((DEBUG_INFO, "SMM S3 Return Entry Point       = %x\n", SmmS3ResumeState->ReturnEntryPoint));\r
+  DEBUG ((DEBUG_INFO, "SMM S3 Return Context1          = %x\n", SmmS3ResumeState->ReturnContext1));\r
+  DEBUG ((DEBUG_INFO, "SMM S3 Return Context2          = %x\n", SmmS3ResumeState->ReturnContext2));\r
+  DEBUG ((DEBUG_INFO, "SMM S3 Return Stack Pointer     = %x\n", SmmS3ResumeState->ReturnStackPointer));\r
 \r
   //\r
   // If SMM is in 32-bit mode, then use SwitchStack() to resume PEI Phase\r
@@ -854,7 +871,7 @@ SmmRestoreCpu (
     //\r
     // Restore IA32 IDT table\r
     //\r
-    AsmWriteIdtr ((IA32_DESCRIPTOR *) &Ia32Idtr);\r
+    AsmWriteIdtr ((IA32_DESCRIPTOR *)&Ia32Idtr);\r
     AsmDisablePaging64 (\r
       SmmS3ResumeState->ReturnCs,\r
       (UINT32)SmmS3ResumeState->ReturnEntryPoint,\r
@@ -882,11 +899,11 @@ InitSmmS3ResumeState (
   IN UINT32  Cr3\r
   )\r
 {\r
-  VOID                       *GuidHob;\r
-  EFI_SMRAM_DESCRIPTOR       *SmramDescriptor;\r
-  SMM_S3_RESUME_STATE        *SmmS3ResumeState;\r
-  EFI_PHYSICAL_ADDRESS       Address;\r
-  EFI_STATUS                 Status;\r
+  VOID                  *GuidHob;\r
+  EFI_SMRAM_DESCRIPTOR  *SmramDescriptor;\r
+  SMM_S3_RESUME_STATE   *SmmS3ResumeState;\r
+  EFI_PHYSICAL_ADDRESS  Address;\r
+  EFI_STATUS            Status;\r
 \r
   if (!mAcpiS3Enable) {\r
     return;\r
@@ -899,10 +916,10 @@ InitSmmS3ResumeState (
       "ERROR:%a(): HOB(gEfiAcpiVariableGuid=%g) needed by S3 resume doesn't exist!\n",\r
       __FUNCTION__,\r
       &gEfiAcpiVariableGuid\r
-    ));\r
+      ));\r
     CpuDeadLoop ();\r
   } else {\r
-    SmramDescriptor = (EFI_SMRAM_DESCRIPTOR *) GET_GUID_HOB_DATA (GuidHob);\r
+    SmramDescriptor = (EFI_SMRAM_DESCRIPTOR *)GET_GUID_HOB_DATA (GuidHob);\r
 \r
     DEBUG ((DEBUG_INFO, "SMM S3 SMRAM Structure = %x\n", SmramDescriptor));\r
     DEBUG ((DEBUG_INFO, "SMM S3 Structure = %x\n", SmramDescriptor->CpuStart));\r
@@ -910,7 +927,7 @@ InitSmmS3ResumeState (
     SmmS3ResumeState = (SMM_S3_RESUME_STATE *)(UINTN)SmramDescriptor->CpuStart;\r
     ZeroMem (SmmS3ResumeState, sizeof (SMM_S3_RESUME_STATE));\r
 \r
-    mSmmS3ResumeState = SmmS3ResumeState;\r
+    mSmmS3ResumeState      = SmmS3ResumeState;\r
     SmmS3ResumeState->Smst = (EFI_PHYSICAL_ADDRESS)(UINTN)gSmst;\r
 \r
     SmmS3ResumeState->SmmS3ResumeEntryPoint = (EFI_PHYSICAL_ADDRESS)(UINTN)SmmRestoreCpu;\r
@@ -928,6 +945,7 @@ InitSmmS3ResumeState (
     if (sizeof (UINTN) == sizeof (UINT64)) {\r
       SmmS3ResumeState->Signature = SMM_S3_RESUME_SMM_64;\r
     }\r
+\r
     if (sizeof (UINTN) == sizeof (UINT32)) {\r
       SmmS3ResumeState->Signature = SMM_S3_RESUME_SMM_32;\r
     }\r
@@ -950,7 +968,7 @@ InitSmmS3ResumeState (
                    &Address\r
                    );\r
   ASSERT_EFI_ERROR (Status);\r
-  mApHltLoopCode = (UINT8 *) (UINTN) Address;\r
+  mApHltLoopCode = (UINT8 *)(UINTN)Address;\r
 }\r
 \r
 /**\r
@@ -963,22 +981,22 @@ InitSmmS3ResumeState (
 **/\r
 VOID\r
 CopyRegisterTable (\r
-  IN CPU_REGISTER_TABLE         *DestinationRegisterTableList,\r
-  IN CPU_REGISTER_TABLE         *SourceRegisterTableList,\r
-  IN UINT32                     NumberOfCpus\r
+  IN CPU_REGISTER_TABLE  *DestinationRegisterTableList,\r
+  IN CPU_REGISTER_TABLE  *SourceRegisterTableList,\r
+  IN UINT32              NumberOfCpus\r
   )\r
 {\r
-  UINTN                      Index;\r
-  CPU_REGISTER_TABLE_ENTRY   *RegisterTableEntry;\r
+  UINTN                     Index;\r
+  CPU_REGISTER_TABLE_ENTRY  *RegisterTableEntry;\r
 \r
   CopyMem (DestinationRegisterTableList, SourceRegisterTableList, NumberOfCpus * sizeof (CPU_REGISTER_TABLE));\r
   for (Index = 0; Index < NumberOfCpus; Index++) {\r
     if (DestinationRegisterTableList[Index].TableLength != 0) {\r
       DestinationRegisterTableList[Index].AllocatedSize = DestinationRegisterTableList[Index].TableLength * sizeof (CPU_REGISTER_TABLE_ENTRY);\r
-      RegisterTableEntry = AllocateCopyPool (\r
-        DestinationRegisterTableList[Index].AllocatedSize,\r
-        (VOID *)(UINTN)SourceRegisterTableList[Index].RegisterTableEntry\r
-        );\r
+      RegisterTableEntry                                = AllocateCopyPool (\r
+                                                            DestinationRegisterTableList[Index].AllocatedSize,\r
+                                                            (VOID *)(UINTN)SourceRegisterTableList[Index].RegisterTableEntry\r
+                                                            );\r
       ASSERT (RegisterTableEntry != NULL);\r
       DestinationRegisterTableList[Index].RegisterTableEntry = (EFI_PHYSICAL_ADDRESS)(UINTN)RegisterTableEntry;\r
     }\r
@@ -996,11 +1014,11 @@ CopyRegisterTable (
 **/\r
 BOOLEAN\r
 IsRegisterTableEmpty (\r
-  IN CPU_REGISTER_TABLE     *RegisterTable,\r
-  IN UINT32                 NumberOfCpus\r
+  IN CPU_REGISTER_TABLE  *RegisterTable,\r
+  IN UINT32              NumberOfCpus\r
   )\r
 {\r
-  UINTN                     Index;\r
+  UINTN  Index;\r
 \r
   if (RegisterTable != NULL) {\r
     for (Index = 0; Index < NumberOfCpus; Index++) {\r
@@ -1022,11 +1040,11 @@ IsRegisterTableEmpty (
 **/\r
 VOID\r
 CopyCpuFeatureInitDatatoSmram (\r
-  IN OUT CPU_FEATURE_INIT_DATA    *CpuFeatureInitDataDst,\r
-  IN     CPU_FEATURE_INIT_DATA    *CpuFeatureInitDataSrc\r
+  IN OUT CPU_FEATURE_INIT_DATA  *CpuFeatureInitDataDst,\r
+  IN     CPU_FEATURE_INIT_DATA  *CpuFeatureInitDataSrc\r
   )\r
 {\r
-  CPU_STATUS_INFORMATION    *CpuStatus;\r
+  CPU_STATUS_INFORMATION  *CpuStatus;\r
 \r
   if (!IsRegisterTableEmpty ((CPU_REGISTER_TABLE *)(UINTN)CpuFeatureInitDataSrc->PreSmmInitRegisterTable, mAcpiCpuData.NumberOfCpus)) {\r
     CpuFeatureInitDataDst->PreSmmInitRegisterTable = (EFI_PHYSICAL_ADDRESS)(UINTN)AllocatePool (mAcpiCpuData.NumberOfCpus * sizeof (CPU_REGISTER_TABLE));\r
@@ -1055,25 +1073,25 @@ CopyCpuFeatureInitDatatoSmram (
 \r
   if (CpuFeatureInitDataSrc->CpuStatus.ThreadCountPerPackage != 0) {\r
     CpuStatus->ThreadCountPerPackage = (EFI_PHYSICAL_ADDRESS)(UINTN)AllocateCopyPool (\r
-                                            sizeof (UINT32) * CpuStatus->PackageCount,\r
-                                            (UINT32 *)(UINTN)CpuFeatureInitDataSrc->CpuStatus.ThreadCountPerPackage\r
-                                            );\r
+                                                                      sizeof (UINT32) * CpuStatus->PackageCount,\r
+                                                                      (UINT32 *)(UINTN)CpuFeatureInitDataSrc->CpuStatus.ThreadCountPerPackage\r
+                                                                      );\r
     ASSERT (CpuStatus->ThreadCountPerPackage != 0);\r
   }\r
 \r
   if (CpuFeatureInitDataSrc->CpuStatus.ThreadCountPerCore != 0) {\r
     CpuStatus->ThreadCountPerCore = (EFI_PHYSICAL_ADDRESS)(UINTN)AllocateCopyPool (\r
-                                            sizeof (UINT8) * (CpuStatus->PackageCount * CpuStatus->MaxCoreCount),\r
-                                            (UINT32 *)(UINTN)CpuFeatureInitDataSrc->CpuStatus.ThreadCountPerCore\r
-                                            );\r
+                                                                   sizeof (UINT8) * (CpuStatus->PackageCount * CpuStatus->MaxCoreCount),\r
+                                                                   (UINT32 *)(UINTN)CpuFeatureInitDataSrc->CpuStatus.ThreadCountPerCore\r
+                                                                   );\r
     ASSERT (CpuStatus->ThreadCountPerCore != 0);\r
   }\r
 \r
   if (CpuFeatureInitDataSrc->ApLocation != 0) {\r
     CpuFeatureInitDataDst->ApLocation = (EFI_PHYSICAL_ADDRESS)(UINTN)AllocateCopyPool (\r
-                                mAcpiCpuData.NumberOfCpus * sizeof (EFI_CPU_PHYSICAL_LOCATION),\r
-                                (EFI_CPU_PHYSICAL_LOCATION *)(UINTN)CpuFeatureInitDataSrc->ApLocation\r
-                                );\r
+                                                                       mAcpiCpuData.NumberOfCpus * sizeof (EFI_CPU_PHYSICAL_LOCATION),\r
+                                                                       (EFI_CPU_PHYSICAL_LOCATION *)(UINTN)CpuFeatureInitDataSrc->ApLocation\r
+                                                                       );\r
     ASSERT (CpuFeatureInitDataDst->ApLocation != 0);\r
   }\r
 }\r
@@ -1087,13 +1105,13 @@ GetAcpiCpuData (
   VOID\r
   )\r
 {\r
-  ACPI_CPU_DATA              *AcpiCpuData;\r
-  IA32_DESCRIPTOR            *Gdtr;\r
-  IA32_DESCRIPTOR            *Idtr;\r
-  VOID                       *GdtForAp;\r
-  VOID                       *IdtForAp;\r
-  VOID                       *MachineCheckHandlerForAp;\r
-  CPU_STATUS_INFORMATION     *CpuStatus;\r
+  ACPI_CPU_DATA           *AcpiCpuData;\r
+  IA32_DESCRIPTOR         *Gdtr;\r
+  IA32_DESCRIPTOR         *Idtr;\r
+  VOID                    *GdtForAp;\r
+  VOID                    *IdtForAp;\r
+  VOID                    *MachineCheckHandlerForAp;\r
+  CPU_STATUS_INFORMATION  *CpuStatus;\r
 \r
   if (!mAcpiS3Enable) {\r
     return;\r
@@ -1140,15 +1158,15 @@ GetAcpiCpuData (
 \r
   GdtForAp = AllocatePool ((Gdtr->Limit + 1) + (Idtr->Limit + 1) + mAcpiCpuData.ApMachineCheckHandlerSize);\r
   ASSERT (GdtForAp != NULL);\r
-  IdtForAp = (VOID *) ((UINTN)GdtForAp + (Gdtr->Limit + 1));\r
-  MachineCheckHandlerForAp = (VOID *) ((UINTN)IdtForAp + (Idtr->Limit + 1));\r
+  IdtForAp                 = (VOID *)((UINTN)GdtForAp + (Gdtr->Limit + 1));\r
+  MachineCheckHandlerForAp = (VOID *)((UINTN)IdtForAp + (Idtr->Limit + 1));\r
 \r
   CopyMem (GdtForAp, (VOID *)Gdtr->Base, Gdtr->Limit + 1);\r
   CopyMem (IdtForAp, (VOID *)Idtr->Base, Idtr->Limit + 1);\r
   CopyMem (MachineCheckHandlerForAp, (VOID *)(UINTN)mAcpiCpuData.ApMachineCheckHandlerBase, mAcpiCpuData.ApMachineCheckHandlerSize);\r
 \r
-  Gdtr->Base = (UINTN)GdtForAp;\r
-  Idtr->Base = (UINTN)IdtForAp;\r
+  Gdtr->Base                             = (UINTN)GdtForAp;\r
+  Idtr->Base                             = (UINTN)IdtForAp;\r
   mAcpiCpuData.ApMachineCheckHandlerBase = (EFI_PHYSICAL_ADDRESS)(UINTN)MachineCheckHandlerForAp;\r
 \r
   ZeroMem (&mAcpiCpuData.CpuFeatureInitData, sizeof (CPU_FEATURE_INIT_DATA));\r
@@ -1175,7 +1193,7 @@ GetAcpiCpuData (
                                         );\r
     ASSERT (mCpuFlags.PackageSemaphoreCount != NULL);\r
 \r
-    InitializeSpinLock((SPIN_LOCK*) &mCpuFlags.MemoryMappedLock);\r
+    InitializeSpinLock ((SPIN_LOCK *)&mCpuFlags.MemoryMappedLock);\r
   }\r
 }\r
 \r

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c
index c9138a531a318214d052d2e98a5fbfdbcb7b22e0..5d624f8e9ed65b47fe2f1c43b1794e8d0e4d7564 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c
@@ -38,15 +38,15 @@ EFI_SMM_CPU_SERVICE_PROTOCOL  mSmmCpuService = {
 EFI_STATUS\r
 EFIAPI\r
 SmmGetProcessorInfo (\r
-  IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL *This,\r
-  IN       UINTN                        ProcessorNumber,\r
-  OUT      EFI_PROCESSOR_INFORMATION    *ProcessorInfoBuffer\r
+  IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL  *This,\r
+  IN       UINTN                         ProcessorNumber,\r
+  OUT      EFI_PROCESSOR_INFORMATION     *ProcessorInfoBuffer\r
   )\r
 {\r
   //\r
   // Check parameter\r
   //\r
-  if (ProcessorNumber >= mMaxNumberOfCpus || ProcessorInfoBuffer == NULL) {\r
+  if ((ProcessorNumber >= mMaxNumberOfCpus) || (ProcessorInfoBuffer == NULL)) {\r
     return EFI_INVALID_PARAMETER;\r
   }\r
 \r
@@ -75,8 +75,8 @@ SmmGetProcessorInfo (
 EFI_STATUS\r
 EFIAPI\r
 SmmSwitchBsp (\r
-  IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL *This,\r
-  IN       UINTN                        ProcessorNumber\r
+  IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL  *This,\r
+  IN       UINTN                         ProcessorNumber\r
   )\r
 {\r
   //\r
@@ -90,8 +90,9 @@ SmmSwitchBsp (
     return EFI_NOT_FOUND;\r
   }\r
 \r
-  if (gSmmCpuPrivate->Operation[ProcessorNumber] != SmmCpuNone ||\r
-      gSmst->CurrentlyExecutingCpu == ProcessorNumber) {\r
+  if ((gSmmCpuPrivate->Operation[ProcessorNumber] != SmmCpuNone) ||\r
+      (gSmst->CurrentlyExecutingCpu == ProcessorNumber))\r
+  {\r
     return EFI_UNSUPPORTED;\r
   }\r
 \r
@@ -132,7 +133,7 @@ SmmAddProcessor (
   //\r
   // Check parameter\r
   //\r
-  if (ProcessorNumber == NULL || ProcessorId == INVALID_APIC_ID) {\r
+  if ((ProcessorNumber == NULL) || (ProcessorId == INVALID_APIC_ID)) {\r
     return EFI_INVALID_PARAMETER;\r
   }\r
 \r
@@ -151,10 +152,11 @@ SmmAddProcessor (
   // of the APIC ID to SMBASE.\r
   //\r
   for (Index = 0; Index < mMaxNumberOfCpus; Index++) {\r
-    if (mCpuHotPlugData.ApicId[Index] == ProcessorId &&\r
-        gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId == INVALID_APIC_ID) {\r
+    if ((mCpuHotPlugData.ApicId[Index] == ProcessorId) &&\r
+        (gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId == INVALID_APIC_ID))\r
+    {\r
       gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId = ProcessorId;\r
-      gSmmCpuPrivate->ProcessorInfo[Index].StatusFlag = 0;\r
+      gSmmCpuPrivate->ProcessorInfo[Index].StatusFlag  = 0;\r
       GetProcessorLocationByApicId (\r
         (UINT32)ProcessorId,\r
         &gSmmCpuPrivate->ProcessorInfo[Index].Location.Package,\r
@@ -162,7 +164,7 @@ SmmAddProcessor (
         &gSmmCpuPrivate->ProcessorInfo[Index].Location.Thread\r
         );\r
 \r
-      *ProcessorNumber = Index;\r
+      *ProcessorNumber                 = Index;\r
       gSmmCpuPrivate->Operation[Index] = SmmCpuAdd;\r
       return EFI_SUCCESS;\r
     }\r
@@ -197,8 +199,9 @@ SmmRemoveProcessor (
   //\r
   // Check parameter\r
   //\r
-  if (ProcessorNumber >= mMaxNumberOfCpus ||\r
-      gSmmCpuPrivate->ProcessorInfo[ProcessorNumber].ProcessorId == INVALID_APIC_ID) {\r
+  if ((ProcessorNumber >= mMaxNumberOfCpus) ||\r
+      (gSmmCpuPrivate->ProcessorInfo[ProcessorNumber].ProcessorId == INVALID_APIC_ID))\r
+  {\r
     return EFI_INVALID_PARAMETER;\r
   }\r
 \r
@@ -214,7 +217,7 @@ SmmRemoveProcessor (
   }\r
 \r
   gSmmCpuPrivate->ProcessorInfo[ProcessorNumber].ProcessorId = INVALID_APIC_ID;\r
-  mCpuHotPlugData.ApicId[ProcessorNumber] = INVALID_APIC_ID;\r
+  mCpuHotPlugData.ApicId[ProcessorNumber]                    = INVALID_APIC_ID;\r
 \r
   //\r
   // Removal of the processor from the CPU list is pending until all SMI handlers are finished\r
@@ -237,12 +240,12 @@ SmmRemoveProcessor (
 EFI_STATUS\r
 EFIAPI\r
 SmmWhoAmI (\r
-  IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL *This,\r
-  OUT      UINTN                        *ProcessorNumber\r
+  IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL  *This,\r
+  OUT      UINTN                         *ProcessorNumber\r
   )\r
 {\r
-  UINTN  Index;\r
-  UINT64 ApicId;\r
+  UINTN   Index;\r
+  UINT64  ApicId;\r
 \r
   //\r
   // Check parameter\r
@@ -259,6 +262,7 @@ SmmWhoAmI (
       return EFI_SUCCESS;\r
     }\r
   }\r
+\r
   //\r
   // This should not happen\r
   //\r
@@ -276,15 +280,15 @@ SmmCpuUpdate (
   VOID\r
   )\r
 {\r
-  UINTN   Index;\r
+  UINTN  Index;\r
 \r
   //\r
   // Handle pending BSP switch operations\r
   //\r
   for (Index = 0; Index < mMaxNumberOfCpus; Index++) {\r
     if (gSmmCpuPrivate->Operation[Index] == SmmCpuSwitchBsp) {\r
-      gSmmCpuPrivate->Operation[Index] = SmmCpuNone;\r
-      mSmmMpSyncData->SwitchBsp = TRUE;\r
+      gSmmCpuPrivate->Operation[Index]    = SmmCpuNone;\r
+      mSmmMpSyncData->SwitchBsp           = TRUE;\r
       mSmmMpSyncData->CandidateBsp[Index] = TRUE;\r
     }\r
   }\r
@@ -330,10 +334,10 @@ SmmCpuUpdate (
 EFI_STATUS\r
 EFIAPI\r
 SmmRegisterExceptionHandler (\r
-    IN EFI_SMM_CPU_SERVICE_PROTOCOL  *This,\r
-    IN EFI_EXCEPTION_TYPE            ExceptionType,\r
-    IN EFI_CPU_INTERRUPT_HANDLER     InterruptHandler\r
-    )\r
+  IN EFI_SMM_CPU_SERVICE_PROTOCOL  *This,\r
+  IN EFI_EXCEPTION_TYPE            ExceptionType,\r
+  IN EFI_CPU_INTERRUPT_HANDLER     InterruptHandler\r
+  )\r
 {\r
   return RegisterCpuInterruptHandler (ExceptionType, InterruptHandler);\r
 }\r
@@ -352,7 +356,7 @@ InitializeSmmCpuServices (
   IN EFI_HANDLE  Handle\r
   )\r
 {\r
-  EFI_STATUS Status;\r
+  EFI_STATUS  Status;\r
 \r
   Status = gSmst->SmmInstallProtocolInterface (\r
                     &Handle,\r
@@ -363,4 +367,3 @@ InitializeSmmCpuServices (
   ASSERT_EFI_ERROR (Status);\r
   return Status;\r
 }\r
-\r

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.h b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.h
index 98b0feb42ca15af9e8ba27794f6fb3a46b3741c1..8847dbb8516c0b64b8c1c754ba945a0dbbecf013 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.h
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.h
@@ -38,9 +38,9 @@ typedef enum {
 EFI_STATUS\r
 EFIAPI\r
 SmmGetProcessorInfo (\r
-  IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL *This,\r
-  IN       UINTN                        ProcessorNumber,\r
-  OUT      EFI_PROCESSOR_INFORMATION    *ProcessorInfoBuffer\r
+  IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL  *This,\r
+  IN       UINTN                         ProcessorNumber,\r
+  OUT      EFI_PROCESSOR_INFORMATION     *ProcessorInfoBuffer\r
   );\r
 \r
 /**\r
@@ -57,8 +57,8 @@ SmmGetProcessorInfo (
 EFI_STATUS\r
 EFIAPI\r
 SmmSwitchBsp (\r
-  IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL *This,\r
-  IN       UINTN                        ProcessorNumber\r
+  IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL  *This,\r
+  IN       UINTN                         ProcessorNumber\r
   );\r
 \r
 /**\r
@@ -115,8 +115,8 @@ SmmRemoveProcessor (
 EFI_STATUS\r
 EFIAPI\r
 SmmWhoAmI (\r
-  IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL *This,\r
-  OUT      UINTN                        *ProcessorNumber\r
+  IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL  *This,\r
+  OUT      UINTN                         *ProcessorNumber\r
   );\r
 \r
 /**\r

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c
index 9c8e2d15ac46a9d2bf3e153d959273682db53b34..8ec8790c05b690a06ad163e8b568d5a4d1c44c45 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c
@@ -36,13 +36,13 @@ EnableCet (
 **/\r
 VOID\r
 GetPageTable (\r
-  OUT UINTN   *Base,\r
-  OUT BOOLEAN *FiveLevels OPTIONAL\r
+  OUT UINTN    *Base,\r
+  OUT BOOLEAN  *FiveLevels OPTIONAL\r
   )\r
 {\r
   *Base = ((mInternalCr3 == 0) ?\r
-            (AsmReadCr3 () & PAGING_4K_ADDRESS_MASK_64) :\r
-            mInternalCr3);\r
+           (AsmReadCr3 () & PAGING_4K_ADDRESS_MASK_64) :\r
+           mInternalCr3);\r
   if (FiveLevels != NULL) {\r
     *FiveLevels = FALSE;\r
   }\r
@@ -59,9 +59,9 @@ SmmInitPageTable (
   VOID\r
   )\r
 {\r
-  UINTN                             PageFaultHandlerHookAddress;\r
-  IA32_IDT_GATE_DESCRIPTOR          *IdtEntry;\r
-  EFI_STATUS                        Status;\r
+  UINTN                     PageFaultHandlerHookAddress;\r
+  IA32_IDT_GATE_DESCRIPTOR  *IdtEntry;\r
+  EFI_STATUS                Status;\r
 \r
   //\r
   // Initialize spin lock\r
@@ -72,18 +72,19 @@ SmmInitPageTable (
 \r
   if (FeaturePcdGet (PcdCpuSmmProfileEnable) ||\r
       HEAP_GUARD_NONSTOP_MODE ||\r
-      NULL_DETECTION_NONSTOP_MODE) {\r
+      NULL_DETECTION_NONSTOP_MODE)\r
+  {\r
     //\r
     // Set own Page Fault entry instead of the default one, because SMM Profile\r
     // feature depends on IRET instruction to do Single Step\r
     //\r
     PageFaultHandlerHookAddress = (UINTN)PageFaultIdtHandlerSmmProfile;\r
-    IdtEntry  = (IA32_IDT_GATE_DESCRIPTOR *) gcSmiIdtr.Base;\r
-    IdtEntry += EXCEPT_IA32_PAGE_FAULT;\r
-    IdtEntry->Bits.OffsetLow      = (UINT16)PageFaultHandlerHookAddress;\r
-    IdtEntry->Bits.Reserved_0     = 0;\r
-    IdtEntry->Bits.GateType       = IA32_IDT_GATE_TYPE_INTERRUPT_32;\r
-    IdtEntry->Bits.OffsetHigh     = (UINT16)(PageFaultHandlerHookAddress >> 16);\r
+    IdtEntry                    = (IA32_IDT_GATE_DESCRIPTOR *)gcSmiIdtr.Base;\r
+    IdtEntry                   += EXCEPT_IA32_PAGE_FAULT;\r
+    IdtEntry->Bits.OffsetLow    = (UINT16)PageFaultHandlerHookAddress;\r
+    IdtEntry->Bits.Reserved_0   = 0;\r
+    IdtEntry->Bits.GateType     = IA32_IDT_GATE_TYPE_INTERRUPT_32;\r
+    IdtEntry->Bits.OffsetHigh   = (UINT16)(PageFaultHandlerHookAddress >> 16);\r
   } else {\r
     //\r
     // Register SMM Page Fault Handler\r
@@ -98,6 +99,7 @@ SmmInitPageTable (
   if (FeaturePcdGet (PcdCpuSmmStackGuard)) {\r
     InitializeIDTSmmStackGuard ();\r
   }\r
+\r
   return Gen4GPageTable (TRUE);\r
 }\r
 \r
@@ -124,13 +126,13 @@ SmiDefaultPFHandler (
 VOID\r
 EFIAPI\r
 SmiPFHandler (\r
-  IN EFI_EXCEPTION_TYPE   InterruptType,\r
-  IN EFI_SYSTEM_CONTEXT   SystemContext\r
+  IN EFI_EXCEPTION_TYPE  InterruptType,\r
+  IN EFI_SYSTEM_CONTEXT  SystemContext\r
   )\r
 {\r
-  UINTN             PFAddress;\r
-  UINTN             GuardPageAddress;\r
-  UINTN             CpuIndex;\r
+  UINTN  PFAddress;\r
+  UINTN  GuardPageAddress;\r
+  UINTN  CpuIndex;\r
 \r
   ASSERT (InterruptType == EXCEPT_IA32_PAGE_FAULT);\r
 \r
@@ -143,25 +145,27 @@ SmiPFHandler (
   // or SMM page protection violation.\r
   //\r
   if ((PFAddress >= mCpuHotPlugData.SmrrBase) &&\r
-      (PFAddress < (mCpuHotPlugData.SmrrBase + mCpuHotPlugData.SmrrSize))) {\r
+      (PFAddress < (mCpuHotPlugData.SmrrBase + mCpuHotPlugData.SmrrSize)))\r
+  {\r
     DumpCpuContext (InterruptType, SystemContext);\r
-    CpuIndex = GetCpuIndex ();\r
+    CpuIndex         = GetCpuIndex ();\r
     GuardPageAddress = (mSmmStackArrayBase + EFI_PAGE_SIZE + CpuIndex * mSmmStackSize);\r
     if ((FeaturePcdGet (PcdCpuSmmStackGuard)) &&\r
         (PFAddress >= GuardPageAddress) &&\r
-        (PFAddress < (GuardPageAddress + EFI_PAGE_SIZE))) {\r
+        (PFAddress < (GuardPageAddress + EFI_PAGE_SIZE)))\r
+    {\r
       DEBUG ((DEBUG_ERROR, "SMM stack overflow!\n"));\r
     } else {\r
       if ((SystemContext.SystemContextIa32->ExceptionData & IA32_PF_EC_ID) != 0) {\r
         DEBUG ((DEBUG_ERROR, "SMM exception at execution (0x%x)\n", PFAddress));\r
         DEBUG_CODE (\r
           DumpModuleInfoByIp (*(UINTN *)(UINTN)SystemContext.SystemContextIa32->Esp);\r
-        );\r
+          );\r
       } else {\r
         DEBUG ((DEBUG_ERROR, "SMM exception at access (0x%x)\n", PFAddress));\r
         DEBUG_CODE (\r
           DumpModuleInfoByIp ((UINTN)SystemContext.SystemContextIa32->Eip);\r
-        );\r
+          );\r
       }\r
 \r
       if (HEAP_GUARD_NONSTOP_MODE) {\r
@@ -169,6 +173,7 @@ SmiPFHandler (
         goto Exit;\r
       }\r
     }\r
+\r
     CpuDeadLoop ();\r
     goto Exit;\r
   }\r
@@ -177,13 +182,14 @@ SmiPFHandler (
   // If a page fault occurs in non-SMRAM range.\r
   //\r
   if ((PFAddress < mCpuHotPlugData.SmrrBase) ||\r
-      (PFAddress >= mCpuHotPlugData.SmrrBase + mCpuHotPlugData.SmrrSize)) {\r
+      (PFAddress >= mCpuHotPlugData.SmrrBase + mCpuHotPlugData.SmrrSize))\r
+  {\r
     if ((SystemContext.SystemContextIa32->ExceptionData & IA32_PF_EC_ID) != 0) {\r
       DumpCpuContext (InterruptType, SystemContext);\r
       DEBUG ((DEBUG_ERROR, "Code executed on IP(0x%x) out of SMM range after SMM is locked!\n", PFAddress));\r
       DEBUG_CODE (\r
         DumpModuleInfoByIp (*(UINTN *)(UINTN)SystemContext.SystemContextIa32->Esp);\r
-      );\r
+        );\r
       CpuDeadLoop ();\r
       goto Exit;\r
     }\r
@@ -191,13 +197,14 @@ SmiPFHandler (
     //\r
     // If NULL pointer was just accessed\r
     //\r
-    if ((PcdGet8 (PcdNullPointerDetectionPropertyMask) & BIT1) != 0 &&\r
-        (PFAddress < EFI_PAGE_SIZE)) {\r
+    if (((PcdGet8 (PcdNullPointerDetectionPropertyMask) & BIT1) != 0) &&\r
+        (PFAddress < EFI_PAGE_SIZE))\r
+    {\r
       DumpCpuContext (InterruptType, SystemContext);\r
       DEBUG ((DEBUG_ERROR, "!!! NULL pointer access !!!\n"));\r
       DEBUG_CODE (\r
         DumpModuleInfoByIp ((UINTN)SystemContext.SystemContextIa32->Eip);\r
-      );\r
+        );\r
 \r
       if (NULL_DETECTION_NONSTOP_MODE) {\r
         GuardPagePFHandler (SystemContext.SystemContextIa32->ExceptionData);\r
@@ -213,7 +220,7 @@ SmiPFHandler (
       DEBUG ((DEBUG_ERROR, "Access SMM communication forbidden address (0x%x)!\n", PFAddress));\r
       DEBUG_CODE (\r
         DumpModuleInfoByIp ((UINTN)SystemContext.SystemContextIa32->Eip);\r
-      );\r
+        );\r
       CpuDeadLoop ();\r
       goto Exit;\r
     }\r
@@ -241,15 +248,15 @@ SetPageTableAttributes (
   VOID\r
   )\r
 {\r
-  UINTN                 Index2;\r
-  UINTN                 Index3;\r
-  UINT64                *L1PageTable;\r
-  UINT64                *L2PageTable;\r
-  UINT64                *L3PageTable;\r
-  UINTN                 PageTableBase;\r
-  BOOLEAN               IsSplitted;\r
-  BOOLEAN               PageTableSplitted;\r
-  BOOLEAN               CetEnabled;\r
+  UINTN    Index2;\r
+  UINTN    Index3;\r
+  UINT64   *L1PageTable;\r
+  UINT64   *L2PageTable;\r
+  UINT64   *L3PageTable;\r
+  UINTN    PageTableBase;\r
+  BOOLEAN  IsSplitted;\r
+  BOOLEAN  PageTableSplitted;\r
+  BOOLEAN  CetEnabled;\r
 \r
   //\r
   // Don't mark page table to read-only if heap guard is enabled.\r
@@ -259,7 +266,7 @@ SetPageTableAttributes (
   //\r
   if ((PcdGet8 (PcdHeapGuardPropertyMask) & (BIT3 | BIT2)) != 0) {\r
     DEBUG ((DEBUG_INFO, "Don't mark page table to read-only as heap guard is enabled\n"));\r
-    return ;\r
+    return;\r
   }\r
 \r
   //\r
@@ -267,7 +274,7 @@ SetPageTableAttributes (
   //\r
   if (FeaturePcdGet (PcdCpuSmmProfileEnable)) {\r
     DEBUG ((DEBUG_INFO, "Don't mark page table to read-only as SMM profile is enabled\n"));\r
-    return ;\r
+    return;\r
   }\r
 \r
   DEBUG ((DEBUG_INFO, "SetPageTableAttributes\n"));\r
@@ -276,14 +283,15 @@ SetPageTableAttributes (
   // Disable write protection, because we need mark page table to be write protected.\r
   // We need *write* page table memory, to mark itself to be *read only*.\r
   //\r
-  CetEnabled = ((AsmReadCr4() & CR4_CET_ENABLE) != 0) ? TRUE : FALSE;\r
+  CetEnabled = ((AsmReadCr4 () & CR4_CET_ENABLE) != 0) ? TRUE : FALSE;\r
   if (CetEnabled) {\r
     //\r
     // CET must be disabled if WP is disabled.\r
     //\r
-    DisableCet();\r
+    DisableCet ();\r
   }\r
-  AsmWriteCr0 (AsmReadCr0() & ~CR0_WP);\r
+\r
+  AsmWriteCr0 (AsmReadCr0 () & ~CR0_WP);\r
 \r
   do {\r
     DEBUG ((DEBUG_INFO, "Start...\n"));\r
@@ -304,15 +312,17 @@ SetPageTableAttributes (
       SmmSetMemoryAttributesEx ((EFI_PHYSICAL_ADDRESS)(UINTN)L2PageTable, SIZE_4KB, EFI_MEMORY_RO, &IsSplitted);\r
       PageTableSplitted = (PageTableSplitted || IsSplitted);\r
 \r
-      for (Index2 = 0; Index2 < SIZE_4KB/sizeof(UINT64); Index2++) {\r
+      for (Index2 = 0; Index2 < SIZE_4KB/sizeof (UINT64); Index2++) {\r
         if ((L2PageTable[Index2] & IA32_PG_PS) != 0) {\r
           // 2M\r
           continue;\r
         }\r
+\r
         L1PageTable = (UINT64 *)(UINTN)(L2PageTable[Index2] & ~mAddressEncMask & PAGING_4K_ADDRESS_MASK_64);\r
         if (L1PageTable == NULL) {\r
           continue;\r
         }\r
+\r
         SmmSetMemoryAttributesEx ((EFI_PHYSICAL_ADDRESS)(UINTN)L1PageTable, SIZE_4KB, EFI_MEMORY_RO, &IsSplitted);\r
         PageTableSplitted = (PageTableSplitted || IsSplitted);\r
       }\r
@@ -322,15 +332,15 @@ SetPageTableAttributes (
   //\r
   // Enable write protection, after page table updated.\r
   //\r
-  AsmWriteCr0 (AsmReadCr0() | CR0_WP);\r
+  AsmWriteCr0 (AsmReadCr0 () | CR0_WP);\r
   if (CetEnabled) {\r
     //\r
     // re-enable CET.\r
     //\r
-    EnableCet();\r
+    EnableCet ();\r
   }\r
 \r
-  return ;\r
+  return;\r
 }\r
 \r
 /**\r
@@ -343,7 +353,7 @@ SaveCr2 (
   OUT UINTN  *Cr2\r
   )\r
 {\r
-  return ;\r
+  return;\r
 }\r
 \r
 /**\r
@@ -356,7 +366,7 @@ RestoreCr2 (
   IN UINTN  Cr2\r
   )\r
 {\r
-  return ;\r
+  return;\r
 }\r
 \r
 /**\r

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/Semaphore.c b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/Semaphore.c
index 31ee067ad612a60887974df9abdce7ed7c8db50e..a9fcc89dda550955669883be21a8b01ebac16727 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/Semaphore.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/Semaphore.c
@@ -32,7 +32,7 @@ SemaphoreHook (
 \r
   mRebasedFlag = RebasedFlag;\r
 \r
-  CpuState = (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET);\r
+  CpuState                      = (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET);\r
   mSmmRelocationOriginalAddress = (UINTN)HookReturnFromSmm (\r
                                            CpuIndex,\r
                                            CpuState,\r

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmFuncsArch.c b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmFuncsArch.c
index ef277349d4ea557d24447096994c0e40f2a146c7..6c48a53f67dac55e06c5dc36abf1cb9756e7b345 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmFuncsArch.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmFuncsArch.c
@@ -8,18 +8,18 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
 \r
 #include "PiSmmCpuDxeSmm.h"\r
 \r
-extern UINT64 gTaskGateDescriptor;\r
+extern UINT64  gTaskGateDescriptor;\r
 \r
-EFI_PHYSICAL_ADDRESS                mGdtBuffer;\r
-UINTN                               mGdtBufferSize;\r
+EFI_PHYSICAL_ADDRESS  mGdtBuffer;\r
+UINTN                 mGdtBufferSize;\r
 \r
-extern BOOLEAN mCetSupported;\r
-extern UINTN mSmmShadowStackSize;\r
+extern BOOLEAN  mCetSupported;\r
+extern UINTN    mSmmShadowStackSize;\r
 \r
-X86_ASSEMBLY_PATCH_LABEL mPatchCetPl0Ssp;\r
-X86_ASSEMBLY_PATCH_LABEL mPatchCetInterruptSsp;\r
-UINT32 mCetPl0Ssp;\r
-UINT32 mCetInterruptSsp;\r
+X86_ASSEMBLY_PATCH_LABEL  mPatchCetPl0Ssp;\r
+X86_ASSEMBLY_PATCH_LABEL  mPatchCetInterruptSsp;\r
+UINT32                    mCetPl0Ssp;\r
+UINT32                    mCetInterruptSsp;\r
 \r
 /**\r
   Initialize IDT for SMM Stack Guard.\r
@@ -38,8 +38,8 @@ InitializeIDTSmmStackGuard (
   // is a Task Gate Descriptor so that when a Page Fault Exception occurs,\r
   // the processors can use a known good stack in case stack is ran out.\r
   //\r
-  IdtGate = (IA32_IDT_GATE_DESCRIPTOR *)gcSmiIdtr.Base;\r
-  IdtGate += EXCEPT_IA32_PAGE_FAULT;\r
+  IdtGate         = (IA32_IDT_GATE_DESCRIPTOR *)gcSmiIdtr.Base;\r
+  IdtGate        += EXCEPT_IA32_PAGE_FAULT;\r
   IdtGate->Uint64 = gTaskGateDescriptor;\r
 }\r
 \r
@@ -58,13 +58,13 @@ InitGdt (
   OUT UINTN  *GdtStepSize\r
   )\r
 {\r
-  UINTN                     Index;\r
-  IA32_SEGMENT_DESCRIPTOR   *GdtDescriptor;\r
-  UINTN                     TssBase;\r
-  UINTN                     GdtTssTableSize;\r
-  UINT8                     *GdtTssTables;\r
-  UINTN                     GdtTableStepSize;\r
-  UINTN                     InterruptShadowStack;\r
+  UINTN                    Index;\r
+  IA32_SEGMENT_DESCRIPTOR  *GdtDescriptor;\r
+  UINTN                    TssBase;\r
+  UINTN                    GdtTssTableSize;\r
+  UINT8                    *GdtTssTables;\r
+  UINTN                    GdtTableStepSize;\r
+  UINTN                    InterruptShadowStack;\r
 \r
   if (FeaturePcdGet (PcdCpuSmmStackGuard)) {\r
     //\r
@@ -79,46 +79,46 @@ InitGdt (
     gcSmiGdtr.Limit += (UINT16)(2 * sizeof (IA32_SEGMENT_DESCRIPTOR));\r
 \r
     GdtTssTableSize = (gcSmiGdtr.Limit + 1 + TSS_SIZE + EXCEPTION_TSS_SIZE + 7) & ~7; // 8 bytes aligned\r
-    mGdtBufferSize = GdtTssTableSize * gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus;\r
+    mGdtBufferSize  = GdtTssTableSize * gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus;\r
     //\r
     // IA32 Stack Guard need use task switch to switch stack that need\r
     // write GDT and TSS, so AllocateCodePages() could not be used here\r
     // as code pages will be set to RO.\r
     //\r
-    GdtTssTables = (UINT8*)AllocatePages (EFI_SIZE_TO_PAGES (mGdtBufferSize));\r
+    GdtTssTables = (UINT8 *)AllocatePages (EFI_SIZE_TO_PAGES (mGdtBufferSize));\r
     ASSERT (GdtTssTables != NULL);\r
-    mGdtBuffer = (UINTN)GdtTssTables;\r
+    mGdtBuffer       = (UINTN)GdtTssTables;\r
     GdtTableStepSize = GdtTssTableSize;\r
 \r
     for (Index = 0; Index < gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus; Index++) {\r
-      CopyMem (GdtTssTables + GdtTableStepSize * Index, (VOID*)(UINTN)gcSmiGdtr.Base, gcSmiGdtr.Limit + 1 + TSS_SIZE + EXCEPTION_TSS_SIZE);\r
+      CopyMem (GdtTssTables + GdtTableStepSize * Index, (VOID *)(UINTN)gcSmiGdtr.Base, gcSmiGdtr.Limit + 1 + TSS_SIZE + EXCEPTION_TSS_SIZE);\r
       //\r
       // Fixup TSS descriptors\r
       //\r
-      TssBase = (UINTN)(GdtTssTables + GdtTableStepSize * Index + gcSmiGdtr.Limit + 1);\r
-      GdtDescriptor = (IA32_SEGMENT_DESCRIPTOR *)(TssBase) - 2;\r
-      GdtDescriptor->Bits.BaseLow = (UINT16)TssBase;\r
-      GdtDescriptor->Bits.BaseMid = (UINT8)(TssBase >> 16);\r
+      TssBase                      = (UINTN)(GdtTssTables + GdtTableStepSize * Index + gcSmiGdtr.Limit + 1);\r
+      GdtDescriptor                = (IA32_SEGMENT_DESCRIPTOR *)(TssBase) - 2;\r
+      GdtDescriptor->Bits.BaseLow  = (UINT16)TssBase;\r
+      GdtDescriptor->Bits.BaseMid  = (UINT8)(TssBase >> 16);\r
       GdtDescriptor->Bits.BaseHigh = (UINT8)(TssBase >> 24);\r
 \r
       TssBase += TSS_SIZE;\r
       GdtDescriptor++;\r
-      GdtDescriptor->Bits.BaseLow = (UINT16)TssBase;\r
-      GdtDescriptor->Bits.BaseMid = (UINT8)(TssBase >> 16);\r
+      GdtDescriptor->Bits.BaseLow  = (UINT16)TssBase;\r
+      GdtDescriptor->Bits.BaseMid  = (UINT8)(TssBase >> 16);\r
       GdtDescriptor->Bits.BaseHigh = (UINT8)(TssBase >> 24);\r
       //\r
       // Fixup TSS segments\r
       //\r
       // ESP as known good stack\r
       //\r
-      *(UINTN *)(TssBase + TSS_IA32_ESP_OFFSET) =  mSmmStackArrayBase + EFI_PAGE_SIZE + Index * mSmmStackSize;\r
+      *(UINTN *)(TssBase + TSS_IA32_ESP_OFFSET)  =  mSmmStackArrayBase + EFI_PAGE_SIZE + Index * mSmmStackSize;\r
       *(UINT32 *)(TssBase + TSS_IA32_CR3_OFFSET) = Cr3;\r
 \r
       //\r
       // Setup ShadowStack for stack switch\r
       //\r
       if ((PcdGet32 (PcdControlFlowEnforcementPropertyMask) != 0) && mCetSupported) {\r
-        InterruptShadowStack = (UINTN)(mSmmStackArrayBase + mSmmStackSize + EFI_PAGES_TO_SIZE (1) - sizeof(UINT64) + (mSmmStackSize + mSmmShadowStackSize) * Index);\r
+        InterruptShadowStack                       = (UINTN)(mSmmStackArrayBase + mSmmStackSize + EFI_PAGES_TO_SIZE (1) - sizeof (UINT64) + (mSmmStackSize + mSmmShadowStackSize) * Index);\r
         *(UINT32 *)(TssBase + TSS_IA32_SSP_OFFSET) = (UINT32)InterruptShadowStack;\r
       }\r
     }\r
@@ -127,14 +127,14 @@ InitGdt (
     // Just use original table, AllocatePage and copy them here to make sure GDTs are covered in page memory.\r
     //\r
     GdtTssTableSize = gcSmiGdtr.Limit + 1;\r
-    mGdtBufferSize = GdtTssTableSize * gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus;\r
-    GdtTssTables = (UINT8*)AllocateCodePages (EFI_SIZE_TO_PAGES (mGdtBufferSize));\r
+    mGdtBufferSize  = GdtTssTableSize * gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus;\r
+    GdtTssTables    = (UINT8 *)AllocateCodePages (EFI_SIZE_TO_PAGES (mGdtBufferSize));\r
     ASSERT (GdtTssTables != NULL);\r
-    mGdtBuffer = (UINTN)GdtTssTables;\r
+    mGdtBuffer       = (UINTN)GdtTssTables;\r
     GdtTableStepSize = GdtTssTableSize;\r
 \r
     for (Index = 0; Index < gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus; Index++) {\r
-      CopyMem (GdtTssTables + GdtTableStepSize * Index, (VOID*)(UINTN)gcSmiGdtr.Base, gcSmiGdtr.Limit + 1);\r
+      CopyMem (GdtTssTables + GdtTableStepSize * Index, (VOID *)(UINTN)gcSmiGdtr.Base, gcSmiGdtr.Limit + 1);\r
     }\r
   }\r
 \r
@@ -181,24 +181,24 @@ InitShadowStack (
   IN VOID   *ShadowStack\r
   )\r
 {\r
-  UINTN       SmmShadowStackSize;\r
+  UINTN  SmmShadowStackSize;\r
 \r
   if ((PcdGet32 (PcdControlFlowEnforcementPropertyMask) != 0) && mCetSupported) {\r
     SmmShadowStackSize = EFI_PAGES_TO_SIZE (EFI_SIZE_TO_PAGES (PcdGet32 (PcdCpuSmmShadowStackSize)));\r
     if (FeaturePcdGet (PcdCpuSmmStackGuard)) {\r
       SmmShadowStackSize += EFI_PAGES_TO_SIZE (2);\r
     }\r
-    mCetPl0Ssp = (UINT32)((UINTN)ShadowStack + SmmShadowStackSize - sizeof(UINT64));\r
+\r
+    mCetPl0Ssp = (UINT32)((UINTN)ShadowStack + SmmShadowStackSize - sizeof (UINT64));\r
     PatchInstructionX86 (mPatchCetPl0Ssp, mCetPl0Ssp, 4);\r
     DEBUG ((DEBUG_INFO, "mCetPl0Ssp - 0x%x\n", mCetPl0Ssp));\r
     DEBUG ((DEBUG_INFO, "ShadowStack - 0x%x\n", ShadowStack));\r
     DEBUG ((DEBUG_INFO, "  SmmShadowStackSize - 0x%x\n", SmmShadowStackSize));\r
 \r
     if (FeaturePcdGet (PcdCpuSmmStackGuard)) {\r
-      mCetInterruptSsp = (UINT32)((UINTN)ShadowStack + EFI_PAGES_TO_SIZE(1) - sizeof(UINT64));\r
+      mCetInterruptSsp = (UINT32)((UINTN)ShadowStack + EFI_PAGES_TO_SIZE (1) - sizeof (UINT64));\r
       PatchInstructionX86 (mPatchCetInterruptSsp, mCetInterruptSsp, 4);\r
       DEBUG ((DEBUG_INFO, "mCetInterruptSsp - 0x%x\n", mCetInterruptSsp));\r
     }\r
   }\r
 }\r
-\r

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmProfileArch.c b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmProfileArch.c
index e83031fc018432fb2844736d3f55823385d1962c..bba4a6f058e20ed605b2dcb665744f359ec79896 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmProfileArch.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmProfileArch.c
@@ -20,7 +20,7 @@ InitSmmS3Cr3 (
 {\r
   mSmmS3ResumeState->SmmS3Cr3 = Gen4GPageTable (TRUE);\r
 \r
-  return ;\r
+  return;\r
 }\r
 \r
 /**\r
@@ -49,11 +49,11 @@ InitPagesForPFHandler (
 **/\r
 VOID\r
 RestorePageTableAbove4G (\r
-  UINT64        *PageTable,\r
-  UINT64        PFAddress,\r
-  UINTN         CpuIndex,\r
-  UINTN         ErrorCode,\r
-  BOOLEAN       *IsValidPFAddress\r
+  UINT64   *PageTable,\r
+  UINT64   PFAddress,\r
+  UINTN    CpuIndex,\r
+  UINTN    ErrorCode,\r
+  BOOLEAN  *IsValidPFAddress\r
   )\r
 {\r
 }\r
@@ -67,7 +67,7 @@ RestorePageTableAbove4G (
 **/\r
 VOID\r
 ClearTrapFlag (\r
-  IN OUT EFI_SYSTEM_CONTEXT   SystemContext\r
+  IN OUT EFI_SYSTEM_CONTEXT  SystemContext\r
   )\r
 {\r
   SystemContext.SystemContextIa32->Eflags &= (UINTN) ~BIT8;\r

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmProfileArch.h b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmProfileArch.h
index 533e8561b2255eb4dd3b4274874cecca05dad48e..6c95f2bb19f17fc06fc7d52b56a5ee204c5f40a3 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmProfileArch.h
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmProfileArch.h
@@ -12,42 +12,42 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
 #pragma pack (1)\r
 \r
 typedef struct _MSR_DS_AREA_STRUCT {\r
-  UINT32  BTSBufferBase;\r
-  UINT32  BTSIndex;\r
-  UINT32  BTSAbsoluteMaximum;\r
-  UINT32  BTSInterruptThreshold;\r
-  UINT32  PEBSBufferBase;\r
-  UINT32  PEBSIndex;\r
-  UINT32  PEBSAbsoluteMaximum;\r
-  UINT32  PEBSInterruptThreshold;\r
-  UINT32  PEBSCounterReset[4];\r
-  UINT32  Reserved;\r
+  UINT32    BTSBufferBase;\r
+  UINT32    BTSIndex;\r
+  UINT32    BTSAbsoluteMaximum;\r
+  UINT32    BTSInterruptThreshold;\r
+  UINT32    PEBSBufferBase;\r
+  UINT32    PEBSIndex;\r
+  UINT32    PEBSAbsoluteMaximum;\r
+  UINT32    PEBSInterruptThreshold;\r
+  UINT32    PEBSCounterReset[4];\r
+  UINT32    Reserved;\r
 } MSR_DS_AREA_STRUCT;\r
 \r
 typedef struct _BRANCH_TRACE_RECORD {\r
-  UINT32  LastBranchFrom;\r
-  UINT32  LastBranchTo;\r
-  UINT32  Rsvd0 : 4;\r
-  UINT32  BranchPredicted : 1;\r
-  UINT32  Rsvd1 : 27;\r
+  UINT32    LastBranchFrom;\r
+  UINT32    LastBranchTo;\r
+  UINT32    Rsvd0           : 4;\r
+  UINT32    BranchPredicted : 1;\r
+  UINT32    Rsvd1           : 27;\r
 } BRANCH_TRACE_RECORD;\r
 \r
 typedef struct _PEBS_RECORD {\r
-  UINT32  Eflags;\r
-  UINT32  LinearIP;\r
-  UINT32  Eax;\r
-  UINT32  Ebx;\r
-  UINT32  Ecx;\r
-  UINT32  Edx;\r
-  UINT32  Esi;\r
-  UINT32  Edi;\r
-  UINT32  Ebp;\r
-  UINT32  Esp;\r
+  UINT32    Eflags;\r
+  UINT32    LinearIP;\r
+  UINT32    Eax;\r
+  UINT32    Ebx;\r
+  UINT32    Ecx;\r
+  UINT32    Edx;\r
+  UINT32    Esi;\r
+  UINT32    Edi;\r
+  UINT32    Ebp;\r
+  UINT32    Esp;\r
 } PEBS_RECORD;\r
 \r
 #pragma pack ()\r
 \r
-#define PHYSICAL_ADDRESS_MASK       ((1ull << 32) - SIZE_4KB)\r
+#define PHYSICAL_ADDRESS_MASK  ((1ull << 32) - SIZE_4KB)\r
 \r
 /**\r
   Update page table to map the memory correctly in order to make the instruction\r
@@ -63,11 +63,11 @@ typedef struct _PEBS_RECORD {
 **/\r
 VOID\r
 RestorePageTableAbove4G (\r
-  UINT64        *PageTable,\r
-  UINT64        PFAddress,\r
-  UINTN         CpuIndex,\r
-  UINTN         ErrorCode,\r
-  BOOLEAN       *IsValidPFAddress\r
+  UINT64   *PageTable,\r
+  UINT64   PFAddress,\r
+  UINTN    CpuIndex,\r
+  UINTN    ErrorCode,\r
+  BOOLEAN  *IsValidPFAddress\r
   );\r
 \r
 /**\r

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c
index 48f9c330b8cf450b43cd14f9fb5e905b8eef3cf8..882dee4fe246697bc1ff6a8ae97cdefb7e8fc443 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c
@@ -13,18 +13,18 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
 //\r
 // Slots for all MTRR( FIXED MTRR + VARIABLE MTRR + MTRR_LIB_IA32_MTRR_DEF_TYPE)\r
 //\r
-MTRR_SETTINGS                               gSmiMtrrs;\r
-UINT64                                      gPhyMask;\r
-SMM_DISPATCHER_MP_SYNC_DATA                 *mSmmMpSyncData = NULL;\r
-UINTN                                       mSmmMpSyncDataSize;\r
-SMM_CPU_SEMAPHORES                          mSmmCpuSemaphores;\r
-UINTN                                       mSemaphoreSize;\r
-SPIN_LOCK                                   *mPFLock = NULL;\r
-SMM_CPU_SYNC_MODE                           mCpuSmmSyncMode;\r
-BOOLEAN                                     mMachineCheckSupported = FALSE;\r
-MM_COMPLETION                               mSmmStartupThisApToken;\r
-\r
-extern UINTN mSmmShadowStackSize;\r
+MTRR_SETTINGS                gSmiMtrrs;\r
+UINT64                       gPhyMask;\r
+SMM_DISPATCHER_MP_SYNC_DATA  *mSmmMpSyncData = NULL;\r
+UINTN                        mSmmMpSyncDataSize;\r
+SMM_CPU_SEMAPHORES           mSmmCpuSemaphores;\r
+UINTN                        mSemaphoreSize;\r
+SPIN_LOCK                    *mPFLock = NULL;\r
+SMM_CPU_SYNC_MODE            mCpuSmmSyncMode;\r
+BOOLEAN                      mMachineCheckSupported = FALSE;\r
+MM_COMPLETION                mSmmStartupThisApToken;\r
+\r
+extern UINTN  mSmmShadowStackSize;\r
 \r
 /**\r
   Performs an atomic compare exchange operation to get semaphore.\r
@@ -38,27 +38,29 @@ extern UINTN mSmmShadowStackSize;
 **/\r
 UINT32\r
 WaitForSemaphore (\r
-  IN OUT  volatile UINT32           *Sem\r
+  IN OUT  volatile UINT32  *Sem\r
   )\r
 {\r
-  UINT32                            Value;\r
+  UINT32  Value;\r
 \r
-  for (;;) {\r
+  for ( ; ;) {\r
     Value = *Sem;\r
-    if (Value != 0 &&\r
-        InterlockedCompareExchange32 (\r
-          (UINT32*)Sem,\r
-          Value,\r
-          Value - 1\r
-          ) == Value) {\r
+    if ((Value != 0) &&\r
+        (InterlockedCompareExchange32 (\r
+           (UINT32 *)Sem,\r
+           Value,\r
+           Value - 1\r
+           ) == Value))\r
+    {\r
       break;\r
     }\r
+\r
     CpuPause ();\r
   }\r
+\r
   return Value - 1;\r
 }\r
 \r
-\r
 /**\r
   Performs an atomic compare exchange operation to release semaphore.\r
   The compare exchange operation must be performed using\r
@@ -71,19 +73,20 @@ WaitForSemaphore (
 **/\r
 UINT32\r
 ReleaseSemaphore (\r
-  IN OUT  volatile UINT32           *Sem\r
+  IN OUT  volatile UINT32  *Sem\r
   )\r
 {\r
-  UINT32                            Value;\r
+  UINT32  Value;\r
 \r
   do {\r
     Value = *Sem;\r
   } while (Value + 1 != 0 &&\r
            InterlockedCompareExchange32 (\r
-             (UINT32*)Sem,\r
+             (UINT32 *)Sem,\r
              Value,\r
              Value + 1\r
              ) != Value);\r
+\r
   return Value + 1;\r
 }\r
 \r
@@ -99,17 +102,19 @@ ReleaseSemaphore (
 **/\r
 UINT32\r
 LockdownSemaphore (\r
-  IN OUT  volatile UINT32           *Sem\r
+  IN OUT  volatile UINT32  *Sem\r
   )\r
 {\r
-  UINT32                            Value;\r
+  UINT32  Value;\r
 \r
   do {\r
     Value = *Sem;\r
   } while (InterlockedCompareExchange32 (\r
-             (UINT32*)Sem,\r
-             Value, (UINT32)-1\r
+             (UINT32 *)Sem,\r
+             Value,\r
+             (UINT32)-1\r
              ) != Value);\r
+\r
   return Value;\r
 }\r
 \r
@@ -121,10 +126,10 @@ LockdownSemaphore (
 **/\r
 VOID\r
 WaitForAllAPs (\r
-  IN      UINTN                     NumberOfAPs\r
+  IN      UINTN  NumberOfAPs\r
   )\r
 {\r
-  UINTN                             BspIndex;\r
+  UINTN  BspIndex;\r
 \r
   BspIndex = mSmmMpSyncData->BspIndex;\r
   while (NumberOfAPs-- > 0) {\r
@@ -142,7 +147,7 @@ ReleaseAllAPs (
   VOID\r
   )\r
 {\r
-  UINTN                             Index;\r
+  UINTN  Index;\r
 \r
   for (Index = 0; Index < mMaxNumberOfCpus; Index++) {\r
     if (IsPresentAp (Index)) {\r
@@ -165,9 +170,9 @@ AllCpusInSmmWithExceptions (
   SMM_CPU_ARRIVAL_EXCEPTIONS  Exceptions\r
   )\r
 {\r
-  UINTN                             Index;\r
-  SMM_CPU_DATA_BLOCK                *CpuData;\r
-  EFI_PROCESSOR_INFORMATION         *ProcessorInfo;\r
+  UINTN                      Index;\r
+  SMM_CPU_DATA_BLOCK         *CpuData;\r
+  EFI_PROCESSOR_INFORMATION  *ProcessorInfo;\r
 \r
   ASSERT (*mSmmMpSyncData->Counter <= mNumberOfCpus);\r
 \r
@@ -175,24 +180,26 @@ AllCpusInSmmWithExceptions (
     return TRUE;\r
   }\r
 \r
-  CpuData = mSmmMpSyncData->CpuData;\r
+  CpuData       = mSmmMpSyncData->CpuData;\r
   ProcessorInfo = gSmmCpuPrivate->ProcessorInfo;\r
   for (Index = 0; Index < mMaxNumberOfCpus; Index++) {\r
-    if (!(*(CpuData[Index].Present)) && ProcessorInfo[Index].ProcessorId != INVALID_APIC_ID) {\r
-      if (((Exceptions & ARRIVAL_EXCEPTION_DELAYED) != 0) && SmmCpuFeaturesGetSmmRegister (Index, SmmRegSmmDelayed) != 0) {\r
+    if (!(*(CpuData[Index].Present)) && (ProcessorInfo[Index].ProcessorId != INVALID_APIC_ID)) {\r
+      if (((Exceptions & ARRIVAL_EXCEPTION_DELAYED) != 0) && (SmmCpuFeaturesGetSmmRegister (Index, SmmRegSmmDelayed) != 0)) {\r
         continue;\r
       }\r
-      if (((Exceptions & ARRIVAL_EXCEPTION_BLOCKED) != 0) && SmmCpuFeaturesGetSmmRegister (Index, SmmRegSmmBlocked) != 0) {\r
+\r
+      if (((Exceptions & ARRIVAL_EXCEPTION_BLOCKED) != 0) && (SmmCpuFeaturesGetSmmRegister (Index, SmmRegSmmBlocked) != 0)) {\r
         continue;\r
       }\r
-      if (((Exceptions & ARRIVAL_EXCEPTION_SMI_DISABLED) != 0) && SmmCpuFeaturesGetSmmRegister (Index, SmmRegSmmEnable) != 0) {\r
+\r
+      if (((Exceptions & ARRIVAL_EXCEPTION_SMI_DISABLED) != 0) && (SmmCpuFeaturesGetSmmRegister (Index, SmmRegSmmEnable) != 0)) {\r
         continue;\r
       }\r
+\r
       return FALSE;\r
     }\r
   }\r
 \r
-\r
   return TRUE;\r
 }\r
 \r
@@ -223,7 +230,7 @@ IsLmceOsEnabled (
   }\r
 \r
   McgExtCtrl.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_EXT_CTL);\r
-  return (BOOLEAN) (McgExtCtrl.Bits.LMCE_EN == 1);\r
+  return (BOOLEAN)(McgExtCtrl.Bits.LMCE_EN == 1);\r
 }\r
 \r
 /**\r
@@ -241,10 +248,10 @@ IsLmceSignaled (
   VOID\r
   )\r
 {\r
-  MSR_IA32_MCG_STATUS_REGISTER McgStatus;\r
+  MSR_IA32_MCG_STATUS_REGISTER  McgStatus;\r
 \r
   McgStatus.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_STATUS);\r
-  return (BOOLEAN) (McgStatus.Bits.LMCE_S == 1);\r
+  return (BOOLEAN)(McgStatus.Bits.LMCE_S == 1);\r
 }\r
 \r
 /**\r
@@ -257,10 +264,10 @@ SmmWaitForApArrival (
   VOID\r
   )\r
 {\r
-  UINT64                            Timer;\r
-  UINTN                             Index;\r
-  BOOLEAN                           LmceEn;\r
-  BOOLEAN                           LmceSignal;\r
+  UINT64   Timer;\r
+  UINTN    Index;\r
+  BOOLEAN  LmceEn;\r
+  BOOLEAN  LmceSignal;\r
 \r
   ASSERT (*mSmmMpSyncData->Counter <= mNumberOfCpus);\r
 \r
@@ -268,7 +275,7 @@ SmmWaitForApArrival (
   LmceSignal = FALSE;\r
   if (mMachineCheckSupported) {\r
     LmceEn     = IsLmceOsEnabled ();\r
-    LmceSignal = IsLmceSignaled();\r
+    LmceSignal = IsLmceSignaled ();\r
   }\r
 \r
   //\r
@@ -287,8 +294,9 @@ SmmWaitForApArrival (
   //\r
   for (Timer = StartSyncTimer ();\r
        !IsSyncTimerTimeout (Timer) && !(LmceEn && LmceSignal) &&\r
-       !AllCpusInSmmWithExceptions (ARRIVAL_EXCEPTION_BLOCKED | ARRIVAL_EXCEPTION_SMI_DISABLED );\r
-       ) {\r
+       !AllCpusInSmmWithExceptions (ARRIVAL_EXCEPTION_BLOCKED | ARRIVAL_EXCEPTION_SMI_DISABLED);\r
+       )\r
+  {\r
     CpuPause ();\r
   }\r
 \r
@@ -313,7 +321,7 @@ SmmWaitForApArrival (
     // Send SMI IPIs to bring outside processors in\r
     //\r
     for (Index = 0; Index < mMaxNumberOfCpus; Index++) {\r
-      if (!(*(mSmmMpSyncData->CpuData[Index].Present)) && gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId != INVALID_APIC_ID) {\r
+      if (!(*(mSmmMpSyncData->CpuData[Index].Present)) && (gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId != INVALID_APIC_ID)) {\r
         SendSmiIpi ((UINT32)gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId);\r
       }\r
     }\r
@@ -323,8 +331,9 @@ SmmWaitForApArrival (
     //\r
     for (Timer = StartSyncTimer ();\r
          !IsSyncTimerTimeout (Timer) &&\r
-         !AllCpusInSmmWithExceptions (ARRIVAL_EXCEPTION_BLOCKED | ARRIVAL_EXCEPTION_SMI_DISABLED );\r
-         ) {\r
+         !AllCpusInSmmWithExceptions (ARRIVAL_EXCEPTION_BLOCKED | ARRIVAL_EXCEPTION_SMI_DISABLED);\r
+         )\r
+    {\r
       CpuPause ();\r
     }\r
   }\r
@@ -332,7 +341,6 @@ SmmWaitForApArrival (
   return;\r
 }\r
 \r
-\r
 /**\r
   Replace OS MTRR's with SMI MTRR's.\r
 \r
@@ -341,7 +349,7 @@ SmmWaitForApArrival (
 **/\r
 VOID\r
 ReplaceOSMtrrs (\r
-  IN      UINTN                     CpuIndex\r
+  IN      UINTN  CpuIndex\r
   )\r
 {\r
   SmmCpuFeaturesDisableSmrr ();\r
@@ -363,25 +371,25 @@ ReplaceOSMtrrs (
 **/\r
 BOOLEAN\r
 WaitForAllAPsNotBusy (\r
-  IN BOOLEAN                        BlockMode\r
+  IN BOOLEAN  BlockMode\r
   )\r
 {\r
-  UINTN                             Index;\r
+  UINTN  Index;\r
 \r
   for (Index = 0; Index < mMaxNumberOfCpus; Index++) {\r
     //\r
     // Ignore BSP and APs which not call in SMM.\r
     //\r
-    if (!IsPresentAp(Index)) {\r
+    if (!IsPresentAp (Index)) {\r
       continue;\r
     }\r
 \r
     if (BlockMode) {\r
-      AcquireSpinLock(mSmmMpSyncData->CpuData[Index].Busy);\r
-      ReleaseSpinLock(mSmmMpSyncData->CpuData[Index].Busy);\r
+      AcquireSpinLock (mSmmMpSyncData->CpuData[Index].Busy);\r
+      ReleaseSpinLock (mSmmMpSyncData->CpuData[Index].Busy);\r
     } else {\r
       if (AcquireSpinLockOrFail (mSmmMpSyncData->CpuData[Index].Busy)) {\r
-        ReleaseSpinLock(mSmmMpSyncData->CpuData[Index].Busy);\r
+        ReleaseSpinLock (mSmmMpSyncData->CpuData[Index].Busy);\r
       } else {\r
         return FALSE;\r
       }\r
@@ -402,11 +410,11 @@ WaitForAllAPsNotBusy (
 **/\r
 BOOLEAN\r
 IsPresentAp (\r
-  IN UINTN        CpuIndex\r
+  IN UINTN  CpuIndex\r
   )\r
 {\r
   return ((CpuIndex != gSmmCpuPrivate->SmmCoreEntryContext.CurrentlyExecutingCpu) &&\r
-    *(mSmmMpSyncData->CpuData[CpuIndex].Present));\r
+          *(mSmmMpSyncData->CpuData[CpuIndex].Present));\r
 }\r
 \r
 /**\r
@@ -417,10 +425,10 @@ IsPresentAp (
 **/\r
 VOID\r
 ReleaseToken (\r
-  IN UINTN                  CpuIndex\r
+  IN UINTN  CpuIndex\r
   )\r
 {\r
-  PROCEDURE_TOKEN                         *Token;\r
+  PROCEDURE_TOKEN  *Token;\r
 \r
   Token = mSmmMpSyncData->CpuData[CpuIndex].Token;\r
 \r
@@ -455,15 +463,15 @@ ResetTokens (
 **/\r
 VOID\r
 BSPHandler (\r
-  IN      UINTN                     CpuIndex,\r
-  IN      SMM_CPU_SYNC_MODE         SyncMode\r
+  IN      UINTN              CpuIndex,\r
+  IN      SMM_CPU_SYNC_MODE  SyncMode\r
   )\r
 {\r
-  UINTN                             Index;\r
-  MTRR_SETTINGS                     Mtrrs;\r
-  UINTN                             ApCount;\r
-  BOOLEAN                           ClearTopLevelSmiResult;\r
-  UINTN                             PresentCount;\r
+  UINTN          Index;\r
+  MTRR_SETTINGS  Mtrrs;\r
+  UINTN          ApCount;\r
+  BOOLEAN        ClearTopLevelSmiResult;\r
+  UINTN          PresentCount;\r
 \r
   ASSERT (CpuIndex == mSmmMpSyncData->BspIndex);\r
   ApCount = 0;\r
@@ -488,7 +496,7 @@ BSPHandler (
   // we cleared it after SMI handlers are run, we would miss the SMI that\r
   // occurs after SMI handlers are done and before SMI status bit is cleared.\r
   //\r
-  ClearTopLevelSmiResult = ClearTopLevelSmiStatus();\r
+  ClearTopLevelSmiResult = ClearTopLevelSmiStatus ();\r
   ASSERT (ClearTopLevelSmiResult == TRUE);\r
 \r
   //\r
@@ -499,25 +507,24 @@ BSPHandler (
   //\r
   // If Traditional Sync Mode or need to configure MTRRs: gather all available APs.\r
   //\r
-  if (SyncMode == SmmCpuSyncModeTradition || SmmCpuFeaturesNeedConfigureMtrrs()) {\r
-\r
+  if ((SyncMode == SmmCpuSyncModeTradition) || SmmCpuFeaturesNeedConfigureMtrrs ()) {\r
     //\r
     // Wait for APs to arrive\r
     //\r
-    SmmWaitForApArrival();\r
+    SmmWaitForApArrival ();\r
 \r
     //\r
     // Lock the counter down and retrieve the number of APs\r
     //\r
     *mSmmMpSyncData->AllCpusInSync = TRUE;\r
-    ApCount = LockdownSemaphore (mSmmMpSyncData->Counter) - 1;\r
+    ApCount                        = LockdownSemaphore (mSmmMpSyncData->Counter) - 1;\r
 \r
     //\r
     // Wait for all APs to get ready for programming MTRRs\r
     //\r
     WaitForAllAPs (ApCount);\r
 \r
-    if (SmmCpuFeaturesNeedConfigureMtrrs()) {\r
+    if (SmmCpuFeaturesNeedConfigureMtrrs ()) {\r
       //\r
       // Signal all APs it's time for backup MTRRs\r
       //\r
@@ -531,7 +538,7 @@ BSPHandler (
       // We do the backup first and then set MTRR to avoid race condition for threads\r
       // in the same core.\r
       //\r
-      MtrrGetAllMtrrs(&Mtrrs);\r
+      MtrrGetAllMtrrs (&Mtrrs);\r
 \r
       //\r
       // Wait for all APs to complete their MTRR saving\r
@@ -587,13 +594,12 @@ BSPHandler (
   // make those APs to exit SMI synchronously. APs which arrive later will be excluded and\r
   // will run through freely.\r
   //\r
-  if (SyncMode != SmmCpuSyncModeTradition && !SmmCpuFeaturesNeedConfigureMtrrs()) {\r
-\r
+  if ((SyncMode != SmmCpuSyncModeTradition) && !SmmCpuFeaturesNeedConfigureMtrrs ()) {\r
     //\r
     // Lock the counter down and retrieve the number of APs\r
     //\r
     *mSmmMpSyncData->AllCpusInSync = TRUE;\r
-    ApCount = LockdownSemaphore (mSmmMpSyncData->Counter) - 1;\r
+    ApCount                        = LockdownSemaphore (mSmmMpSyncData->Counter) - 1;\r
     //\r
     // Make sure all APs have their Present flag set\r
     //\r
@@ -601,9 +607,10 @@ BSPHandler (
       PresentCount = 0;\r
       for (Index = 0; Index < mMaxNumberOfCpus; Index++) {\r
         if (*(mSmmMpSyncData->CpuData[Index].Present)) {\r
-          PresentCount ++;\r
+          PresentCount++;\r
         }\r
       }\r
+\r
       if (PresentCount > ApCount) {\r
         break;\r
       }\r
@@ -621,7 +628,7 @@ BSPHandler (
   //\r
   WaitForAllAPs (ApCount);\r
 \r
-  if (SmmCpuFeaturesNeedConfigureMtrrs()) {\r
+  if (SmmCpuFeaturesNeedConfigureMtrrs ()) {\r
     //\r
     // Signal APs to restore MTRRs\r
     //\r
@@ -631,7 +638,7 @@ BSPHandler (
     // Restore OS MTRRs\r
     //\r
     SmmCpuFeaturesReenableSmrr ();\r
-    MtrrSetAllMtrrs(&Mtrrs);\r
+    MtrrSetAllMtrrs (&Mtrrs);\r
 \r
     //\r
     // Wait for all APs to complete MTRR programming\r
@@ -681,7 +688,7 @@ BSPHandler (
   //\r
   // Allow APs to check in from this point on\r
   //\r
-  *mSmmMpSyncData->Counter = 0;\r
+  *mSmmMpSyncData->Counter       = 0;\r
   *mSmmMpSyncData->AllCpusInSync = FALSE;\r
 }\r
 \r
@@ -695,15 +702,15 @@ BSPHandler (
 **/\r
 VOID\r
 APHandler (\r
-  IN      UINTN                     CpuIndex,\r
-  IN      BOOLEAN                   ValidSmi,\r
-  IN      SMM_CPU_SYNC_MODE         SyncMode\r
+  IN      UINTN              CpuIndex,\r
+  IN      BOOLEAN            ValidSmi,\r
+  IN      SMM_CPU_SYNC_MODE  SyncMode\r
   )\r
 {\r
-  UINT64                            Timer;\r
-  UINTN                             BspIndex;\r
-  MTRR_SETTINGS                     Mtrrs;\r
-  EFI_STATUS                        ProcedureStatus;\r
+  UINT64         Timer;\r
+  UINTN          BspIndex;\r
+  MTRR_SETTINGS  Mtrrs;\r
+  EFI_STATUS     ProcedureStatus;\r
 \r
   //\r
   // Timeout BSP\r
@@ -711,7 +718,8 @@ APHandler (
   for (Timer = StartSyncTimer ();\r
        !IsSyncTimerTimeout (Timer) &&\r
        !(*mSmmMpSyncData->InsideSmm);\r
-       ) {\r
+       )\r
+  {\r
     CpuPause ();\r
   }\r
 \r
@@ -737,7 +745,8 @@ APHandler (
       for (Timer = StartSyncTimer ();\r
            !IsSyncTimerTimeout (Timer) &&\r
            !(*mSmmMpSyncData->InsideSmm);\r
-           ) {\r
+           )\r
+      {\r
         CpuPause ();\r
       }\r
 \r
@@ -768,14 +777,14 @@ APHandler (
   //\r
   *(mSmmMpSyncData->CpuData[CpuIndex].Present) = TRUE;\r
 \r
-  if (SyncMode == SmmCpuSyncModeTradition || SmmCpuFeaturesNeedConfigureMtrrs()) {\r
+  if ((SyncMode == SmmCpuSyncModeTradition) || SmmCpuFeaturesNeedConfigureMtrrs ()) {\r
     //\r
     // Notify BSP of arrival at this point\r
     //\r
     ReleaseSemaphore (mSmmMpSyncData->CpuData[BspIndex].Run);\r
   }\r
 \r
-  if (SmmCpuFeaturesNeedConfigureMtrrs()) {\r
+  if (SmmCpuFeaturesNeedConfigureMtrrs ()) {\r
     //\r
     // Wait for the signal from BSP to backup MTRRs\r
     //\r
@@ -784,7 +793,7 @@ APHandler (
     //\r
     // Backup OS MTRRs\r
     //\r
-    MtrrGetAllMtrrs(&Mtrrs);\r
+    MtrrGetAllMtrrs (&Mtrrs);\r
 \r
     //\r
     // Signal BSP the completion of this AP\r
@@ -830,9 +839,9 @@ APHandler (
     //\r
     // Invoke the scheduled procedure\r
     //\r
-    ProcedureStatus = (*mSmmMpSyncData->CpuData[CpuIndex].Procedure) (\r
-                          (VOID*)mSmmMpSyncData->CpuData[CpuIndex].Parameter\r
-                          );\r
+    ProcedureStatus = (*mSmmMpSyncData->CpuData[CpuIndex].Procedure)(\r
+         (VOID *)mSmmMpSyncData->CpuData[CpuIndex].Parameter\r
+  );\r
     if (mSmmMpSyncData->CpuData[CpuIndex].Status != NULL) {\r
       *mSmmMpSyncData->CpuData[CpuIndex].Status = ProcedureStatus;\r
     }\r
@@ -847,7 +856,7 @@ APHandler (
     ReleaseSpinLock (mSmmMpSyncData->CpuData[CpuIndex].Busy);\r
   }\r
 \r
-  if (SmmCpuFeaturesNeedConfigureMtrrs()) {\r
+  if (SmmCpuFeaturesNeedConfigureMtrrs ()) {\r
     //\r
     // Notify BSP the readiness of this AP to program MTRRs\r
     //\r
@@ -862,7 +871,7 @@ APHandler (
     // Restore OS MTRRs\r
     //\r
     SmmCpuFeaturesReenableSmrr ();\r
-    MtrrSetAllMtrrs(&Mtrrs);\r
+    MtrrSetAllMtrrs (&Mtrrs);\r
   }\r
 \r
   //\r
@@ -884,7 +893,6 @@ APHandler (
   // Notify BSP the readiness of this AP to exit SMM\r
   //\r
   ReleaseSemaphore (mSmmMpSyncData->CpuData[BspIndex].Run);\r
-\r
 }\r
 \r
 /**\r
@@ -896,7 +904,7 @@ APHandler (
 **/\r
 UINT32\r
 Gen4GPageTable (\r
-  IN      BOOLEAN                   Is32BitPageTable\r
+  IN      BOOLEAN  Is32BitPageTable\r
   )\r
 {\r
   VOID    *PageTable;\r
@@ -911,9 +919,9 @@ Gen4GPageTable (
   UINTN   PageIndex;\r
   UINTN   PageAddress;\r
 \r
-  Low2MBoundary = 0;\r
+  Low2MBoundary  = 0;\r
   High2MBoundary = 0;\r
-  PagesNeeded = 0;\r
+  PagesNeeded    = 0;\r
   if (FeaturePcdGet (PcdCpuSmmStackGuard)) {\r
     //\r
     // Add one more page for known good stack, then find the lower 2MB aligned address.\r
@@ -924,8 +932,9 @@ Gen4GPageTable (
     // then find the lower 2MB aligned address.\r
     //\r
     High2MBoundary = (mSmmStackArrayEnd - mSmmStackSize - mSmmShadowStackSize + EFI_PAGE_SIZE * 2) & ~(SIZE_2MB-1);\r
-    PagesNeeded = ((High2MBoundary - Low2MBoundary) / SIZE_2MB) + 1;\r
+    PagesNeeded    = ((High2MBoundary - Low2MBoundary) / SIZE_2MB) + 1;\r
   }\r
+\r
   //\r
   // Allocate the page table\r
   //\r
@@ -933,7 +942,7 @@ Gen4GPageTable (
   ASSERT (PageTable != NULL);\r
 \r
   PageTable = (VOID *)((UINTN)PageTable);\r
-  Pte = (UINT64*)PageTable;\r
+  Pte       = (UINT64 *)PageTable;\r
 \r
   //\r
   // Zero out all page table entries first\r
@@ -945,8 +954,9 @@ Gen4GPageTable (
   //\r
   for (Index = 0; Index < 4; Index++) {\r
     Pte[Index] = ((UINTN)PageTable + EFI_PAGE_SIZE * (Index + 1)) | mAddressEncMask |\r
-                   (Is32BitPageTable ? IA32_PAE_PDPTE_ATTRIBUTE_BITS : PAGE_ATTRIBUTE_BITS);\r
+                 (Is32BitPageTable ? IA32_PAE_PDPTE_ATTRIBUTE_BITS : PAGE_ATTRIBUTE_BITS);\r
   }\r
+\r
   Pte += EFI_PAGE_SIZE / sizeof (*Pte);\r
 \r
   //\r
@@ -956,17 +966,17 @@ Gen4GPageTable (
     Pte[Index] = (Index << 21) | mAddressEncMask | IA32_PG_PS | PAGE_ATTRIBUTE_BITS;\r
   }\r
 \r
-  Pdpte = (UINT64*)PageTable;\r
+  Pdpte = (UINT64 *)PageTable;\r
   if (FeaturePcdGet (PcdCpuSmmStackGuard)) {\r
-    Pages = (UINTN)PageTable + EFI_PAGES_TO_SIZE (5);\r
+    Pages     = (UINTN)PageTable + EFI_PAGES_TO_SIZE (5);\r
     GuardPage = mSmmStackArrayBase + EFI_PAGE_SIZE;\r
     for (PageIndex = Low2MBoundary; PageIndex <= High2MBoundary; PageIndex += SIZE_2MB) {\r
-      Pte = (UINT64*)(UINTN)(Pdpte[BitFieldRead32 ((UINT32)PageIndex, 30, 31)] & ~mAddressEncMask & ~(EFI_PAGE_SIZE - 1));\r
+      Pte                                             = (UINT64 *)(UINTN)(Pdpte[BitFieldRead32 ((UINT32)PageIndex, 30, 31)] & ~mAddressEncMask & ~(EFI_PAGE_SIZE - 1));\r
       Pte[BitFieldRead32 ((UINT32)PageIndex, 21, 29)] = (UINT64)Pages | mAddressEncMask | PAGE_ATTRIBUTE_BITS;\r
       //\r
       // Fill in Page Table Entries\r
       //\r
-      Pte = (UINT64*)Pages;\r
+      Pte         = (UINT64 *)Pages;\r
       PageAddress = PageIndex;\r
       for (Index = 0; Index < EFI_PAGE_SIZE / sizeof (*Pte); Index++) {\r
         if (PageAddress == GuardPage) {\r
@@ -981,17 +991,19 @@ Gen4GPageTable (
         } else {\r
           Pte[Index] = PageAddress | mAddressEncMask | PAGE_ATTRIBUTE_BITS;\r
         }\r
-        PageAddress+= EFI_PAGE_SIZE;\r
+\r
+        PageAddress += EFI_PAGE_SIZE;\r
       }\r
+\r
       Pages += EFI_PAGE_SIZE;\r
     }\r
   }\r
 \r
   if ((PcdGet8 (PcdNullPointerDetectionPropertyMask) & BIT1) != 0) {\r
-    Pte = (UINT64*)(UINTN)(Pdpte[0] & ~mAddressEncMask & ~(EFI_PAGE_SIZE - 1));\r
+    Pte = (UINT64 *)(UINTN)(Pdpte[0] & ~mAddressEncMask & ~(EFI_PAGE_SIZE - 1));\r
     if ((Pte[0] & IA32_PG_PS) == 0) {\r
       // 4K-page entries are already mapped. Just hide the first one anyway.\r
-      Pte = (UINT64*)(UINTN)(Pte[0] & ~mAddressEncMask & ~(EFI_PAGE_SIZE - 1));\r
+      Pte     = (UINT64 *)(UINTN)(Pte[0] & ~mAddressEncMask & ~(EFI_PAGE_SIZE - 1));\r
       Pte[0] &= ~(UINT64)IA32_PG_P; // Hide page 0\r
     } else {\r
       // Create 4K-page entries\r
@@ -1000,12 +1012,12 @@ Gen4GPageTable (
 \r
       Pte[0] = (UINT64)(Pages | mAddressEncMask | PAGE_ATTRIBUTE_BITS);\r
 \r
-      Pte = (UINT64*)Pages;\r
+      Pte         = (UINT64 *)Pages;\r
       PageAddress = 0;\r
-      Pte[0] = PageAddress | mAddressEncMask; // Hide page 0 but present left\r
+      Pte[0]      = PageAddress | mAddressEncMask; // Hide page 0 but present left\r
       for (Index = 1; Index < EFI_PAGE_SIZE / sizeof (*Pte); Index++) {\r
         PageAddress += EFI_PAGE_SIZE;\r
-        Pte[Index] = PageAddress | mAddressEncMask | PAGE_ATTRIBUTE_BITS;\r
+        Pte[Index]   = PageAddress | mAddressEncMask | PAGE_ATTRIBUTE_BITS;\r
       }\r
     }\r
   }\r
@@ -1024,11 +1036,11 @@ Gen4GPageTable (
 **/\r
 BOOLEAN\r
 IsTokenInUse (\r
-  IN SPIN_LOCK           *Token\r
+  IN SPIN_LOCK  *Token\r
   )\r
 {\r
-  LIST_ENTRY        *Link;\r
-  PROCEDURE_TOKEN   *ProcToken;\r
+  LIST_ENTRY       *Link;\r
+  PROCEDURE_TOKEN  *ProcToken;\r
 \r
   if (Token == NULL) {\r
     return FALSE;\r
@@ -1061,12 +1073,12 @@ AllocateTokenBuffer (
   VOID\r
   )\r
 {\r
-  UINTN               SpinLockSize;\r
-  UINT32              TokenCountPerChunk;\r
-  UINTN               Index;\r
-  SPIN_LOCK           *SpinLock;\r
-  UINT8               *SpinLockBuffer;\r
-  PROCEDURE_TOKEN     *ProcTokens;\r
+  UINTN            SpinLockSize;\r
+  UINT32           TokenCountPerChunk;\r
+  UINTN            Index;\r
+  SPIN_LOCK        *SpinLock;\r
+  UINT8            *SpinLockBuffer;\r
+  PROCEDURE_TOKEN  *ProcTokens;\r
 \r
   SpinLockSize = GetSpinLockProperties ();\r
 \r
@@ -1076,6 +1088,7 @@ AllocateTokenBuffer (
     DEBUG ((DEBUG_ERROR, "PcdCpuSmmMpTokenCountPerChunk should not be Zero!\n"));\r
     CpuDeadLoop ();\r
   }\r
+\r
   DEBUG ((DEBUG_INFO, "CpuSmm: SpinLock Size = 0x%x, PcdCpuSmmMpTokenCountPerChunk = 0x%x\n", SpinLockSize, TokenCountPerChunk));\r
 \r
   //\r
@@ -1113,7 +1126,7 @@ AllocateTokenBuffer (
 **/\r
 PROCEDURE_TOKEN *\r
 GetFreeToken (\r
-  IN UINT32       RunningApsCount\r
+  IN UINT32  RunningApsCount\r
   )\r
 {\r
   PROCEDURE_TOKEN  *NewToken;\r
@@ -1125,7 +1138,8 @@ GetFreeToken (
   if (gSmmCpuPrivate->FirstFreeToken == &gSmmCpuPrivate->TokenList) {\r
     gSmmCpuPrivate->FirstFreeToken = AllocateTokenBuffer ();\r
   }\r
-  NewToken = PROCEDURE_TOKEN_FROM_LINK (gSmmCpuPrivate->FirstFreeToken);\r
+\r
+  NewToken                       = PROCEDURE_TOKEN_FROM_LINK (gSmmCpuPrivate->FirstFreeToken);\r
   gSmmCpuPrivate->FirstFreeToken = GetNextNode (&gSmmCpuPrivate->TokenList, gSmmCpuPrivate->FirstFreeToken);\r
 \r
   NewToken->RunningApCount = RunningApsCount;\r
@@ -1148,7 +1162,7 @@ GetFreeToken (
 **/\r
 EFI_STATUS\r
 IsApReady (\r
-  IN SPIN_LOCK          *Token\r
+  IN SPIN_LOCK  *Token\r
   )\r
 {\r
   if (AcquireSpinLockOrFail (Token)) {\r
@@ -1196,42 +1210,50 @@ IsApReady (
 **/\r
 EFI_STATUS\r
 InternalSmmStartupThisAp (\r
-  IN      EFI_AP_PROCEDURE2              Procedure,\r
-  IN      UINTN                          CpuIndex,\r
-  IN OUT  VOID                           *ProcArguments OPTIONAL,\r
-  IN      MM_COMPLETION                  *Token,\r
-  IN      UINTN                          TimeoutInMicroseconds,\r
-  IN OUT  EFI_STATUS                     *CpuStatus\r
+  IN      EFI_AP_PROCEDURE2  Procedure,\r
+  IN      UINTN              CpuIndex,\r
+  IN OUT  VOID               *ProcArguments OPTIONAL,\r
+  IN      MM_COMPLETION      *Token,\r
+  IN      UINTN              TimeoutInMicroseconds,\r
+  IN OUT  EFI_STATUS         *CpuStatus\r
   )\r
 {\r
-  PROCEDURE_TOKEN    *ProcToken;\r
+  PROCEDURE_TOKEN  *ProcToken;\r
 \r
   if (CpuIndex >= gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus) {\r
-    DEBUG((DEBUG_ERROR, "CpuIndex(%d) >= gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus(%d)\n", CpuIndex, gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus));\r
+    DEBUG ((DEBUG_ERROR, "CpuIndex(%d) >= gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus(%d)\n", CpuIndex, gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus));\r
     return EFI_INVALID_PARAMETER;\r
   }\r
+\r
   if (CpuIndex == gSmmCpuPrivate->SmmCoreEntryContext.CurrentlyExecutingCpu) {\r
-    DEBUG((DEBUG_ERROR, "CpuIndex(%d) == gSmmCpuPrivate->SmmCoreEntryContext.CurrentlyExecutingCpu\n", CpuIndex));\r
+    DEBUG ((DEBUG_ERROR, "CpuIndex(%d) == gSmmCpuPrivate->SmmCoreEntryContext.CurrentlyExecutingCpu\n", CpuIndex));\r
     return EFI_INVALID_PARAMETER;\r
   }\r
+\r
   if (gSmmCpuPrivate->ProcessorInfo[CpuIndex].ProcessorId == INVALID_APIC_ID) {\r
     return EFI_INVALID_PARAMETER;\r
   }\r
+\r
   if (!(*(mSmmMpSyncData->CpuData[CpuIndex].Present))) {\r
     if (mSmmMpSyncData->EffectiveSyncMode == SmmCpuSyncModeTradition) {\r
-      DEBUG((DEBUG_ERROR, "!mSmmMpSyncData->CpuData[%d].Present\n", CpuIndex));\r
+      DEBUG ((DEBUG_ERROR, "!mSmmMpSyncData->CpuData[%d].Present\n", CpuIndex));\r
     }\r
+\r
     return EFI_INVALID_PARAMETER;\r
   }\r
+\r
   if (gSmmCpuPrivate->Operation[CpuIndex] == SmmCpuRemove) {\r
     if (!FeaturePcdGet (PcdCpuHotPlugSupport)) {\r
-      DEBUG((DEBUG_ERROR, "gSmmCpuPrivate->Operation[%d] == SmmCpuRemove\n", CpuIndex));\r
+      DEBUG ((DEBUG_ERROR, "gSmmCpuPrivate->Operation[%d] == SmmCpuRemove\n", CpuIndex));\r
     }\r
+\r
     return EFI_INVALID_PARAMETER;\r
   }\r
+\r
   if ((TimeoutInMicroseconds != 0) && ((mSmmMp.Attributes & EFI_MM_MP_TIMEOUT_SUPPORTED) == 0)) {\r
     return EFI_INVALID_PARAMETER;\r
   }\r
+\r
   if (Procedure == NULL) {\r
     return EFI_INVALID_PARAMETER;\r
   }\r
@@ -1257,12 +1279,13 @@ InternalSmmStartupThisAp (
       // 2. Get a free token from the token buffer.\r
       // 3. Call ReleaseToken() in APHandler().\r
       //\r
-      ProcToken = GetFreeToken (1);\r
+      ProcToken                               = GetFreeToken (1);\r
       mSmmMpSyncData->CpuData[CpuIndex].Token = ProcToken;\r
-      *Token = (MM_COMPLETION)ProcToken->SpinLock;\r
+      *Token                                  = (MM_COMPLETION)ProcToken->SpinLock;\r
     }\r
   }\r
-  mSmmMpSyncData->CpuData[CpuIndex].Status    = CpuStatus;\r
+\r
+  mSmmMpSyncData->CpuData[CpuIndex].Status = CpuStatus;\r
   if (mSmmMpSyncData->CpuData[CpuIndex].Status != NULL) {\r
     *mSmmMpSyncData->CpuData[CpuIndex].Status = EFI_NOT_READY;\r
   }\r
@@ -1309,20 +1332,21 @@ InternalSmmStartupThisAp (
 **/\r
 EFI_STATUS\r
 InternalSmmStartupAllAPs (\r
-  IN       EFI_AP_PROCEDURE2             Procedure,\r
-  IN       UINTN                         TimeoutInMicroseconds,\r
-  IN OUT   VOID                          *ProcedureArguments OPTIONAL,\r
-  IN OUT   MM_COMPLETION                 *Token,\r
-  IN OUT   EFI_STATUS                    *CPUStatus\r
+  IN       EFI_AP_PROCEDURE2  Procedure,\r
+  IN       UINTN              TimeoutInMicroseconds,\r
+  IN OUT   VOID               *ProcedureArguments OPTIONAL,\r
+  IN OUT   MM_COMPLETION      *Token,\r
+  IN OUT   EFI_STATUS         *CPUStatus\r
   )\r
 {\r
-  UINTN               Index;\r
-  UINTN               CpuCount;\r
-  PROCEDURE_TOKEN     *ProcToken;\r
+  UINTN            Index;\r
+  UINTN            CpuCount;\r
+  PROCEDURE_TOKEN  *ProcToken;\r
 \r
   if ((TimeoutInMicroseconds != 0) && ((mSmmMp.Attributes & EFI_MM_MP_TIMEOUT_SUPPORTED) == 0)) {\r
     return EFI_INVALID_PARAMETER;\r
   }\r
+\r
   if (Procedure == NULL) {\r
     return EFI_INVALID_PARAMETER;\r
   }\r
@@ -1330,25 +1354,27 @@ InternalSmmStartupAllAPs (
   CpuCount = 0;\r
   for (Index = 0; Index < mMaxNumberOfCpus; Index++) {\r
     if (IsPresentAp (Index)) {\r
-      CpuCount ++;\r
+      CpuCount++;\r
 \r
       if (gSmmCpuPrivate->Operation[Index] == SmmCpuRemove) {\r
         return EFI_INVALID_PARAMETER;\r
       }\r
 \r
-      if (!AcquireSpinLockOrFail(mSmmMpSyncData->CpuData[Index].Busy)) {\r
+      if (!AcquireSpinLockOrFail (mSmmMpSyncData->CpuData[Index].Busy)) {\r
         return EFI_NOT_READY;\r
       }\r
+\r
       ReleaseSpinLock (mSmmMpSyncData->CpuData[Index].Busy);\r
     }\r
   }\r
+\r
   if (CpuCount == 0) {\r
     return EFI_NOT_STARTED;\r
   }\r
 \r
   if (Token != NULL) {\r
     ProcToken = GetFreeToken ((UINT32)mMaxNumberOfCpus);\r
-    *Token = (MM_COMPLETION)ProcToken->SpinLock;\r
+    *Token    = (MM_COMPLETION)ProcToken->SpinLock;\r
   } else {\r
     ProcToken = NULL;\r
   }\r
@@ -1368,13 +1394,14 @@ InternalSmmStartupAllAPs (
 \r
   for (Index = 0; Index < mMaxNumberOfCpus; Index++) {\r
     if (IsPresentAp (Index)) {\r
-      mSmmMpSyncData->CpuData[Index].Procedure = (EFI_AP_PROCEDURE2) Procedure;\r
+      mSmmMpSyncData->CpuData[Index].Procedure = (EFI_AP_PROCEDURE2)Procedure;\r
       mSmmMpSyncData->CpuData[Index].Parameter = ProcedureArguments;\r
       if (ProcToken != NULL) {\r
-        mSmmMpSyncData->CpuData[Index].Token   = ProcToken;\r
+        mSmmMpSyncData->CpuData[Index].Token = ProcToken;\r
       }\r
+\r
       if (CPUStatus != NULL) {\r
-        mSmmMpSyncData->CpuData[Index].Status    = &CPUStatus[Index];\r
+        mSmmMpSyncData->CpuData[Index].Status = &CPUStatus[Index];\r
         if (mSmmMpSyncData->CpuData[Index].Status != NULL) {\r
           *mSmmMpSyncData->CpuData[Index].Status = EFI_NOT_READY;\r
         }\r
@@ -1426,10 +1453,10 @@ InternalSmmStartupAllAPs (
 EFI_STATUS\r
 EFIAPI\r
 ProcedureWrapper (\r
-  IN     VOID *Buffer\r
+  IN     VOID  *Buffer\r
   )\r
 {\r
-  PROCEDURE_WRAPPER *Wrapper;\r
+  PROCEDURE_WRAPPER  *Wrapper;\r
 \r
   Wrapper = Buffer;\r
   Wrapper->Procedure (Wrapper->ProcedureArgument);\r
@@ -1454,14 +1481,14 @@ ProcedureWrapper (
 EFI_STATUS\r
 EFIAPI\r
 SmmBlockingStartupThisAp (\r
-  IN      EFI_AP_PROCEDURE          Procedure,\r
-  IN      UINTN                     CpuIndex,\r
-  IN OUT  VOID                      *ProcArguments OPTIONAL\r
+  IN      EFI_AP_PROCEDURE  Procedure,\r
+  IN      UINTN             CpuIndex,\r
+  IN OUT  VOID              *ProcArguments OPTIONAL\r
   )\r
 {\r
   PROCEDURE_WRAPPER  Wrapper;\r
 \r
-  Wrapper.Procedure = Procedure;\r
+  Wrapper.Procedure         = Procedure;\r
   Wrapper.ProcedureArgument = ProcArguments;\r
 \r
   //\r
@@ -1487,25 +1514,25 @@ SmmBlockingStartupThisAp (
 EFI_STATUS\r
 EFIAPI\r
 SmmStartupThisAp (\r
-  IN      EFI_AP_PROCEDURE          Procedure,\r
-  IN      UINTN                     CpuIndex,\r
-  IN OUT  VOID                      *ProcArguments OPTIONAL\r
+  IN      EFI_AP_PROCEDURE  Procedure,\r
+  IN      UINTN             CpuIndex,\r
+  IN OUT  VOID              *ProcArguments OPTIONAL\r
   )\r
 {\r
-  gSmmCpuPrivate->ApWrapperFunc[CpuIndex].Procedure = Procedure;\r
+  gSmmCpuPrivate->ApWrapperFunc[CpuIndex].Procedure         = Procedure;\r
   gSmmCpuPrivate->ApWrapperFunc[CpuIndex].ProcedureArgument = ProcArguments;\r
 \r
   //\r
   // Use wrapper function to convert EFI_AP_PROCEDURE to EFI_AP_PROCEDURE2.\r
   //\r
   return InternalSmmStartupThisAp (\r
-    ProcedureWrapper,\r
-    CpuIndex,\r
-    &gSmmCpuPrivate->ApWrapperFunc[CpuIndex],\r
-    FeaturePcdGet (PcdCpuSmmBlockStartupThisAp) ? NULL : &mSmmStartupThisApToken,\r
-    0,\r
-    NULL\r
-    );\r
+           ProcedureWrapper,\r
+           CpuIndex,\r
+           &gSmmCpuPrivate->ApWrapperFunc[CpuIndex],\r
+           FeaturePcdGet (PcdCpuSmmBlockStartupThisAp) ? NULL : &mSmmStartupThisApToken,\r
+           0,\r
+           NULL\r
+           );\r
 }\r
 \r
 /**\r
@@ -1524,10 +1551,10 @@ CpuSmmDebugEntry (
   IN UINTN  CpuIndex\r
   )\r
 {\r
-  SMRAM_SAVE_STATE_MAP *CpuSaveState;\r
+  SMRAM_SAVE_STATE_MAP  *CpuSaveState;\r
 \r
   if (FeaturePcdGet (PcdCpuSmmDebug)) {\r
-    ASSERT(CpuIndex < mMaxNumberOfCpus);\r
+    ASSERT (CpuIndex < mMaxNumberOfCpus);\r
     CpuSaveState = (SMRAM_SAVE_STATE_MAP *)gSmmCpuPrivate->CpuSaveState[CpuIndex];\r
     if (mSmmSaveStateRegisterLma == EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT) {\r
       AsmWriteDr6 (CpuSaveState->x86._DR6);\r
@@ -1554,10 +1581,10 @@ CpuSmmDebugExit (
   IN UINTN  CpuIndex\r
   )\r
 {\r
-  SMRAM_SAVE_STATE_MAP *CpuSaveState;\r
+  SMRAM_SAVE_STATE_MAP  *CpuSaveState;\r
 \r
   if (FeaturePcdGet (PcdCpuSmmDebug)) {\r
-    ASSERT(CpuIndex < mMaxNumberOfCpus);\r
+    ASSERT (CpuIndex < mMaxNumberOfCpus);\r
     CpuSaveState = (SMRAM_SAVE_STATE_MAP *)gSmmCpuPrivate->CpuSaveState[CpuIndex];\r
     if (mSmmSaveStateRegisterLma == EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT) {\r
       CpuSaveState->x86._DR7 = (UINT32)AsmReadDr7 ();\r
@@ -1578,17 +1605,17 @@ CpuSmmDebugExit (
 VOID\r
 EFIAPI\r
 SmiRendezvous (\r
-  IN      UINTN                     CpuIndex\r
+  IN      UINTN  CpuIndex\r
   )\r
 {\r
-  EFI_STATUS                     Status;\r
-  BOOLEAN                        ValidSmi;\r
-  BOOLEAN                        IsBsp;\r
-  BOOLEAN                        BspInProgress;\r
-  UINTN                          Index;\r
-  UINTN                          Cr2;\r
+  EFI_STATUS  Status;\r
+  BOOLEAN     ValidSmi;\r
+  BOOLEAN     IsBsp;\r
+  BOOLEAN     BspInProgress;\r
+  UINTN       Index;\r
+  UINTN       Cr2;\r
 \r
-  ASSERT(CpuIndex < mMaxNumberOfCpus);\r
+  ASSERT (CpuIndex < mMaxNumberOfCpus);\r
 \r
   //\r
   // Save Cr2 because Page Fault exception in SMM may override its value,\r
@@ -1612,7 +1639,7 @@ SmiRendezvous (
   //\r
   // Determine if this is a valid SMI\r
   //\r
-  ValidSmi = PlatformValidSmi();\r
+  ValidSmi = PlatformValidSmi ();\r
 \r
   //\r
   // Determine if BSP has been already in progress. Note this must be checked after\r
@@ -1644,9 +1671,9 @@ SmiRendezvous (
       while (*mSmmMpSyncData->AllCpusInSync) {\r
         CpuPause ();\r
       }\r
+\r
       goto Exit;\r
     } else {\r
-\r
       //\r
       // The BUSY lock is initialized to Released state.\r
       // This needs to be done early enough to be ready for BSP's SmmStartupThisAp() call.\r
@@ -1693,7 +1720,7 @@ SmiRendezvous (
             // Platform hook fails to determine, use default BSP election method\r
             //\r
             InterlockedCompareExchange32 (\r
-              (UINT32*)&mSmmMpSyncData->BspIndex,\r
+              (UINT32 *)&mSmmMpSyncData->BspIndex,\r
               (UINT32)-1,\r
               (UINT32)CpuIndex\r
               );\r
@@ -1705,7 +1732,6 @@ SmiRendezvous (
       // "mSmmMpSyncData->BspIndex == CpuIndex" means this is the BSP\r
       //\r
       if (mSmmMpSyncData->BspIndex == CpuIndex) {\r
-\r
         //\r
         // Clear last request for SwitchBsp.\r
         //\r
@@ -1774,45 +1800,45 @@ InitializeSmmCpuSemaphores (
   VOID\r
   )\r
 {\r
-  UINTN                      ProcessorCount;\r
-  UINTN                      TotalSize;\r
-  UINTN                      GlobalSemaphoresSize;\r
-  UINTN                      CpuSemaphoresSize;\r
-  UINTN                      SemaphoreSize;\r
-  UINTN                      Pages;\r
-  UINTN                      *SemaphoreBlock;\r
-  UINTN                      SemaphoreAddr;\r
-\r
-  SemaphoreSize   = GetSpinLockProperties ();\r
-  ProcessorCount = gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus;\r
+  UINTN  ProcessorCount;\r
+  UINTN  TotalSize;\r
+  UINTN  GlobalSemaphoresSize;\r
+  UINTN  CpuSemaphoresSize;\r
+  UINTN  SemaphoreSize;\r
+  UINTN  Pages;\r
+  UINTN  *SemaphoreBlock;\r
+  UINTN  SemaphoreAddr;\r
+\r
+  SemaphoreSize        = GetSpinLockProperties ();\r
+  ProcessorCount       = gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus;\r
   GlobalSemaphoresSize = (sizeof (SMM_CPU_SEMAPHORE_GLOBAL) / sizeof (VOID *)) * SemaphoreSize;\r
   CpuSemaphoresSize    = (sizeof (SMM_CPU_SEMAPHORE_CPU) / sizeof (VOID *)) * ProcessorCount * SemaphoreSize;\r
-  TotalSize = GlobalSemaphoresSize + CpuSemaphoresSize;\r
-  DEBUG((DEBUG_INFO, "One Semaphore Size    = 0x%x\n", SemaphoreSize));\r
-  DEBUG((DEBUG_INFO, "Total Semaphores Size = 0x%x\n", TotalSize));\r
-  Pages = EFI_SIZE_TO_PAGES (TotalSize);\r
+  TotalSize            = GlobalSemaphoresSize + CpuSemaphoresSize;\r
+  DEBUG ((DEBUG_INFO, "One Semaphore Size    = 0x%x\n", SemaphoreSize));\r
+  DEBUG ((DEBUG_INFO, "Total Semaphores Size = 0x%x\n", TotalSize));\r
+  Pages          = EFI_SIZE_TO_PAGES (TotalSize);\r
   SemaphoreBlock = AllocatePages (Pages);\r
   ASSERT (SemaphoreBlock != NULL);\r
   ZeroMem (SemaphoreBlock, TotalSize);\r
 \r
-  SemaphoreAddr = (UINTN)SemaphoreBlock;\r
+  SemaphoreAddr                                   = (UINTN)SemaphoreBlock;\r
   mSmmCpuSemaphores.SemaphoreGlobal.Counter       = (UINT32 *)SemaphoreAddr;\r
-  SemaphoreAddr += SemaphoreSize;\r
+  SemaphoreAddr                                  += SemaphoreSize;\r
   mSmmCpuSemaphores.SemaphoreGlobal.InsideSmm     = (BOOLEAN *)SemaphoreAddr;\r
-  SemaphoreAddr += SemaphoreSize;\r
+  SemaphoreAddr                                  += SemaphoreSize;\r
   mSmmCpuSemaphores.SemaphoreGlobal.AllCpusInSync = (BOOLEAN *)SemaphoreAddr;\r
-  SemaphoreAddr += SemaphoreSize;\r
+  SemaphoreAddr                                  += SemaphoreSize;\r
   mSmmCpuSemaphores.SemaphoreGlobal.PFLock        = (SPIN_LOCK *)SemaphoreAddr;\r
-  SemaphoreAddr += SemaphoreSize;\r
+  SemaphoreAddr                                  += SemaphoreSize;\r
   mSmmCpuSemaphores.SemaphoreGlobal.CodeAccessCheckLock\r
-                                                  = (SPIN_LOCK *)SemaphoreAddr;\r
+                 = (SPIN_LOCK *)SemaphoreAddr;\r
   SemaphoreAddr += SemaphoreSize;\r
 \r
-  SemaphoreAddr = (UINTN)SemaphoreBlock + GlobalSemaphoresSize;\r
+  SemaphoreAddr                          = (UINTN)SemaphoreBlock + GlobalSemaphoresSize;\r
   mSmmCpuSemaphores.SemaphoreCpu.Busy    = (SPIN_LOCK *)SemaphoreAddr;\r
-  SemaphoreAddr += ProcessorCount * SemaphoreSize;\r
+  SemaphoreAddr                         += ProcessorCount * SemaphoreSize;\r
   mSmmCpuSemaphores.SemaphoreCpu.Run     = (UINT32 *)SemaphoreAddr;\r
-  SemaphoreAddr += ProcessorCount * SemaphoreSize;\r
+  SemaphoreAddr                         += ProcessorCount * SemaphoreSize;\r
   mSmmCpuSemaphores.SemaphoreCpu.Present = (BOOLEAN *)SemaphoreAddr;\r
 \r
   mPFLock                       = mSmmCpuSemaphores.SemaphoreGlobal.PFLock;\r
@@ -1831,7 +1857,7 @@ InitializeMpSyncData (
   VOID\r
   )\r
 {\r
-  UINTN                      CpuIndex;\r
+  UINTN  CpuIndex;\r
 \r
   if (mSmmMpSyncData != NULL) {\r
     //\r
@@ -1839,7 +1865,7 @@ InitializeMpSyncData (
     // CpuData array of SMM_CPU_DATA_BLOCK and one CandidateBsp array of BOOLEAN.\r
     //\r
     ZeroMem (mSmmMpSyncData, mSmmMpSyncDataSize);\r
-    mSmmMpSyncData->CpuData = (SMM_CPU_DATA_BLOCK *)((UINT8 *)mSmmMpSyncData + sizeof (SMM_DISPATCHER_MP_SYNC_DATA));\r
+    mSmmMpSyncData->CpuData      = (SMM_CPU_DATA_BLOCK *)((UINT8 *)mSmmMpSyncData + sizeof (SMM_DISPATCHER_MP_SYNC_DATA));\r
     mSmmMpSyncData->CandidateBsp = (BOOLEAN *)(mSmmMpSyncData->CpuData + gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus);\r
     if (FeaturePcdGet (PcdCpuSmmEnableBspElection)) {\r
       //\r
@@ -1847,21 +1873,24 @@ InitializeMpSyncData (
       //\r
       mSmmMpSyncData->BspIndex = (UINT32)-1;\r
     }\r
+\r
     mSmmMpSyncData->EffectiveSyncMode = mCpuSmmSyncMode;\r
 \r
     mSmmMpSyncData->Counter       = mSmmCpuSemaphores.SemaphoreGlobal.Counter;\r
     mSmmMpSyncData->InsideSmm     = mSmmCpuSemaphores.SemaphoreGlobal.InsideSmm;\r
     mSmmMpSyncData->AllCpusInSync = mSmmCpuSemaphores.SemaphoreGlobal.AllCpusInSync;\r
-    ASSERT (mSmmMpSyncData->Counter != NULL && mSmmMpSyncData->InsideSmm != NULL &&\r
-            mSmmMpSyncData->AllCpusInSync != NULL);\r
+    ASSERT (\r
+      mSmmMpSyncData->Counter != NULL && mSmmMpSyncData->InsideSmm != NULL &&\r
+      mSmmMpSyncData->AllCpusInSync != NULL\r
+      );\r
     *mSmmMpSyncData->Counter       = 0;\r
     *mSmmMpSyncData->InsideSmm     = FALSE;\r
     *mSmmMpSyncData->AllCpusInSync = FALSE;\r
 \r
-    for (CpuIndex = 0; CpuIndex < gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus; CpuIndex ++) {\r
-      mSmmMpSyncData->CpuData[CpuIndex].Busy    =\r
+    for (CpuIndex = 0; CpuIndex < gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus; CpuIndex++) {\r
+      mSmmMpSyncData->CpuData[CpuIndex].Busy =\r
         (SPIN_LOCK *)((UINTN)mSmmCpuSemaphores.SemaphoreCpu.Busy + mSemaphoreSize * CpuIndex);\r
-      mSmmMpSyncData->CpuData[CpuIndex].Run     =\r
+      mSmmMpSyncData->CpuData[CpuIndex].Run =\r
         (UINT32 *)((UINTN)mSmmCpuSemaphores.SemaphoreCpu.Run + mSemaphoreSize * CpuIndex);\r
       mSmmMpSyncData->CpuData[CpuIndex].Present =\r
         (BOOLEAN *)((UINTN)mSmmCpuSemaphores.SemaphoreCpu.Present + mSemaphoreSize * CpuIndex);\r
@@ -1882,9 +1911,9 @@ InitializeMpSyncData (
 **/\r
 UINT32\r
 InitializeMpServiceData (\r
-  IN VOID        *Stacks,\r
-  IN UINTN       StackSize,\r
-  IN UINTN       ShadowStackSize\r
+  IN VOID   *Stacks,\r
+  IN UINTN  StackSize,\r
+  IN UINTN  ShadowStackSize\r
   )\r
 {\r
   UINT32                          Cr3;\r
@@ -1911,7 +1940,7 @@ InitializeMpServiceData (
   //\r
   mSmmMpSyncDataSize = sizeof (SMM_DISPATCHER_MP_SYNC_DATA) +\r
                        (sizeof (SMM_CPU_DATA_BLOCK) + sizeof (BOOLEAN)) * gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus;\r
-  mSmmMpSyncData = (SMM_DISPATCHER_MP_SYNC_DATA*) AllocatePages (EFI_SIZE_TO_PAGES (mSmmMpSyncDataSize));\r
+  mSmmMpSyncData = (SMM_DISPATCHER_MP_SYNC_DATA *)AllocatePages (EFI_SIZE_TO_PAGES (mSmmMpSyncDataSize));\r
   ASSERT (mSmmMpSyncData != NULL);\r
   mCpuSmmSyncMode = (SMM_CPU_SYNC_MODE)PcdGet8 (PcdCpuSmmSyncMode);\r
   InitializeMpSyncData ();\r
@@ -1926,7 +1955,8 @@ InitializeMpServiceData (
   } else {\r
     VirPhyAddressSize.Bits.PhysicalAddressBits = 36;\r
   }\r
-  gPhyMask  = LShiftU64 (1, VirPhyAddressSize.Bits.PhysicalAddressBits) - 1;\r
+\r
+  gPhyMask = LShiftU64 (1, VirPhyAddressSize.Bits.PhysicalAddressBits) - 1;\r
   //\r
   // Clear the low 12 bits\r
   //\r
@@ -1946,7 +1976,7 @@ InitializeMpServiceData (
     InstallSmiHandler (\r
       Index,\r
       (UINT32)mCpuHotPlugData.SmBase[Index],\r
-      (VOID*)((UINTN)Stacks + (StackSize + ShadowStackSize) * Index),\r
+      (VOID *)((UINTN)Stacks + (StackSize + ShadowStackSize) * Index),\r
       StackSize,\r
       (UINTN)(GdtTssTables + GdtTableStepSize * Index),\r
       gcSmiGdtr.Limit + 1,\r
@@ -2009,13 +2039,14 @@ RegisterSmmEntry (
 **/\r
 EFI_STATUS\r
 RegisterStartupProcedure (\r
-  IN     EFI_AP_PROCEDURE    Procedure,\r
-  IN OUT VOID                *ProcedureArguments OPTIONAL\r
+  IN     EFI_AP_PROCEDURE  Procedure,\r
+  IN OUT VOID              *ProcedureArguments OPTIONAL\r
   )\r
 {\r
-  if (Procedure == NULL && ProcedureArguments != NULL) {\r
+  if ((Procedure == NULL) && (ProcedureArguments != NULL)) {\r
     return EFI_INVALID_PARAMETER;\r
   }\r
+\r
   if (mSmmMpSyncData == NULL) {\r
     return EFI_NOT_READY;\r
   }\r

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
index fbf45d652565c489c52aff87aa4e56bfc8ed2ec6..40aabeda724a76cb49061aaec5497977f1efba82 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
@@ -21,7 +21,9 @@ SMM_CPU_PRIVATE_DATA  mSmmCpuPrivateData = {
   NULL,                                         // Pointer to Operation array\r
   NULL,                                         // Pointer to CpuSaveStateSize array\r
   NULL,                                         // Pointer to CpuSaveState array\r
-  { {0} },                                      // SmmReservedSmramRegion\r
+  {\r
+    { 0    }\r
+  },                                            // SmmReservedSmramRegion\r
   {\r
     SmmStartupThisAp,                           // SmmCoreEntryContext.SmmStartupThisAp\r
     0,                                          // SmmCoreEntryContext.CurrentlyExecutingCpu\r
@@ -35,10 +37,10 @@ SMM_CPU_PRIVATE_DATA  mSmmCpuPrivateData = {
     RegisterSmmEntry                            // SmmConfiguration.RegisterSmmEntry\r
   },\r
   NULL,                                         // pointer to Ap Wrapper Func array\r
-  {NULL, NULL},                                 // List_Entry for Tokens.\r
+  { NULL, NULL },                               // List_Entry for Tokens.\r
 };\r
 \r
-CPU_HOT_PLUG_DATA mCpuHotPlugData = {\r
+CPU_HOT_PLUG_DATA  mCpuHotPlugData = {\r
   CPU_HOT_PLUG_DATA_REVISION_1,                 // Revision\r
   0,                                            // Array Length of SmBase and APIC ID\r
   NULL,                                         // Pointer to APIC ID array\r
@@ -67,7 +69,7 @@ EFI_HANDLE  mSmmCpuHandle = NULL;
 ///\r
 /// SMM CPU Protocol instance\r
 ///\r
-EFI_SMM_CPU_PROTOCOL  mSmmCpu  = {\r
+EFI_SMM_CPU_PROTOCOL  mSmmCpu = {\r
   SmmReadSaveState,\r
   SmmWriteSaveState\r
 };\r
@@ -75,60 +77,60 @@ EFI_SMM_CPU_PROTOCOL  mSmmCpu  = {
 ///\r
 /// SMM Memory Attribute Protocol instance\r
 ///\r
-EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL  mSmmMemoryAttribute  = {\r
+EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL  mSmmMemoryAttribute = {\r
   EdkiiSmmGetMemoryAttributes,\r
   EdkiiSmmSetMemoryAttributes,\r
   EdkiiSmmClearMemoryAttributes\r
 };\r
 \r
-EFI_CPU_INTERRUPT_HANDLER   mExternalVectorTable[EXCEPTION_VECTOR_NUMBER];\r
+EFI_CPU_INTERRUPT_HANDLER  mExternalVectorTable[EXCEPTION_VECTOR_NUMBER];\r
 \r
 //\r
 // SMM stack information\r
 //\r
-UINTN mSmmStackArrayBase;\r
-UINTN mSmmStackArrayEnd;\r
-UINTN mSmmStackSize;\r
+UINTN  mSmmStackArrayBase;\r
+UINTN  mSmmStackArrayEnd;\r
+UINTN  mSmmStackSize;\r
 \r
-UINTN mSmmShadowStackSize;\r
-BOOLEAN mCetSupported = TRUE;\r
+UINTN    mSmmShadowStackSize;\r
+BOOLEAN  mCetSupported = TRUE;\r
 \r
-UINTN mMaxNumberOfCpus = 1;\r
-UINTN mNumberOfCpus = 1;\r
+UINTN  mMaxNumberOfCpus = 1;\r
+UINTN  mNumberOfCpus    = 1;\r
 \r
 //\r
 // SMM ready to lock flag\r
 //\r
-BOOLEAN mSmmReadyToLock = FALSE;\r
+BOOLEAN  mSmmReadyToLock = FALSE;\r
 \r
 //\r
 // Global used to cache PCD for SMM Code Access Check enable\r
 //\r
-BOOLEAN                  mSmmCodeAccessCheckEnable = FALSE;\r
+BOOLEAN  mSmmCodeAccessCheckEnable = FALSE;\r
 \r
 //\r
 // Global copy of the PcdPteMemoryEncryptionAddressOrMask\r
 //\r
-UINT64                   mAddressEncMask = 0;\r
+UINT64  mAddressEncMask = 0;\r
 \r
 //\r
 // Spin lock used to serialize setting of SMM Code Access Check feature\r
 //\r
-SPIN_LOCK                *mConfigSmmCodeAccessCheckLock = NULL;\r
+SPIN_LOCK  *mConfigSmmCodeAccessCheckLock = NULL;\r
 \r
 //\r
 // Saved SMM ranges information\r
 //\r
-EFI_SMRAM_DESCRIPTOR     *mSmmCpuSmramRanges;\r
-UINTN                    mSmmCpuSmramRangeCount;\r
+EFI_SMRAM_DESCRIPTOR  *mSmmCpuSmramRanges;\r
+UINTN                 mSmmCpuSmramRangeCount;\r
 \r
-UINT8                    mPhysicalAddressBits;\r
+UINT8  mPhysicalAddressBits;\r
 \r
 //\r
 // Control register contents saved for SMM S3 resume state initialization.\r
 //\r
-UINT32                   mSmmCr0;\r
-UINT32                   mSmmCr4;\r
+UINT32  mSmmCr0;\r
+UINT32  mSmmCr4;\r
 \r
 /**\r
   Initialize IDT to setup exception handlers for SMM.\r
@@ -139,19 +141,19 @@ InitializeSmmIdt (
   VOID\r
   )\r
 {\r
-  EFI_STATUS               Status;\r
-  BOOLEAN                  InterruptState;\r
-  IA32_DESCRIPTOR          DxeIdtr;\r
+  EFI_STATUS       Status;\r
+  BOOLEAN          InterruptState;\r
+  IA32_DESCRIPTOR  DxeIdtr;\r
 \r
   //\r
   // There are 32 (not 255) entries in it since only processor\r
   // generated exceptions will be handled.\r
   //\r
-  gcSmiIdtr.Limit = (sizeof(IA32_IDT_GATE_DESCRIPTOR) * 32) - 1;\r
+  gcSmiIdtr.Limit = (sizeof (IA32_IDT_GATE_DESCRIPTOR) * 32) - 1;\r
   //\r
   // Allocate page aligned IDT, because it might be set as read only.\r
   //\r
-  gcSmiIdtr.Base = (UINTN)AllocateCodePages (EFI_SIZE_TO_PAGES(gcSmiIdtr.Limit + 1));\r
+  gcSmiIdtr.Base = (UINTN)AllocateCodePages (EFI_SIZE_TO_PAGES (gcSmiIdtr.Limit + 1));\r
   ASSERT (gcSmiIdtr.Base != 0);\r
   ZeroMem ((VOID *)gcSmiIdtr.Base, gcSmiIdtr.Limit + 1);\r
 \r
@@ -173,7 +175,7 @@ InitializeSmmIdt (
   //\r
   // Restore DXE IDT table and CPU interrupt\r
   //\r
-  AsmWriteIdtr ((IA32_DESCRIPTOR *) &DxeIdtr);\r
+  AsmWriteIdtr ((IA32_DESCRIPTOR *)&DxeIdtr);\r
   SetInterruptState (InterruptState);\r
 }\r
 \r
@@ -185,19 +187,19 @@ InitializeSmmIdt (
 **/\r
 VOID\r
 DumpModuleInfoByIp (\r
-  IN  UINTN              CallerIpAddress\r
+  IN  UINTN  CallerIpAddress\r
   )\r
 {\r
-  UINTN                                Pe32Data;\r
-  VOID                                 *PdbPointer;\r
+  UINTN  Pe32Data;\r
+  VOID   *PdbPointer;\r
 \r
   //\r
   // Find Image Base\r
   //\r
   Pe32Data = PeCoffSearchImageBase (CallerIpAddress);\r
   if (Pe32Data != 0) {\r
-    DEBUG ((DEBUG_ERROR, "It is invoked from the instruction before IP(0x%p)", (VOID *) CallerIpAddress));\r
-    PdbPointer = PeCoffLoaderGetPdbPointer ((VOID *) Pe32Data);\r
+    DEBUG ((DEBUG_ERROR, "It is invoked from the instruction before IP(0x%p)", (VOID *)CallerIpAddress));\r
+    PdbPointer = PeCoffLoaderGetPdbPointer ((VOID *)Pe32Data);\r
     if (PdbPointer != NULL) {\r
       DEBUG ((DEBUG_ERROR, " in module (%a)\n", PdbPointer));\r
     }\r
@@ -221,11 +223,11 @@ DumpModuleInfoByIp (
 EFI_STATUS\r
 EFIAPI\r
 SmmReadSaveState (\r
-  IN CONST EFI_SMM_CPU_PROTOCOL         *This,\r
-  IN UINTN                              Width,\r
-  IN EFI_SMM_SAVE_STATE_REGISTER        Register,\r
-  IN UINTN                              CpuIndex,\r
-  OUT VOID                              *Buffer\r
+  IN CONST EFI_SMM_CPU_PROTOCOL   *This,\r
+  IN UINTN                        Width,\r
+  IN EFI_SMM_SAVE_STATE_REGISTER  Register,\r
+  IN UINTN                        CpuIndex,\r
+  OUT VOID                        *Buffer\r
   )\r
 {\r
   EFI_STATUS  Status;\r
@@ -236,6 +238,7 @@ SmmReadSaveState (
   if ((CpuIndex >= gSmst->NumberOfCpus) || (Buffer == NULL)) {\r
     return EFI_INVALID_PARAMETER;\r
   }\r
+\r
   //\r
   // The SpeculationBarrier() call here is to ensure the above check for the\r
   // CpuIndex has been completed before the execution of subsequent codes.\r
@@ -252,6 +255,7 @@ SmmReadSaveState (
     if (Width != sizeof (UINT64)) {\r
       return EFI_INVALID_PARAMETER;\r
     }\r
+\r
     //\r
     // If the processor is in SMM at the time the SMI occurred,\r
     // the pseudo register value for EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID is returned in Buffer.\r
@@ -273,6 +277,7 @@ SmmReadSaveState (
   if (Status == EFI_UNSUPPORTED) {\r
     Status = ReadSaveStateRegister (CpuIndex, Register, Width, Buffer);\r
   }\r
+\r
   return Status;\r
 }\r
 \r
@@ -293,11 +298,11 @@ SmmReadSaveState (
 EFI_STATUS\r
 EFIAPI\r
 SmmWriteSaveState (\r
-  IN CONST EFI_SMM_CPU_PROTOCOL         *This,\r
-  IN UINTN                              Width,\r
-  IN EFI_SMM_SAVE_STATE_REGISTER        Register,\r
-  IN UINTN                              CpuIndex,\r
-  IN CONST VOID                         *Buffer\r
+  IN CONST EFI_SMM_CPU_PROTOCOL   *This,\r
+  IN UINTN                        Width,\r
+  IN EFI_SMM_SAVE_STATE_REGISTER  Register,\r
+  IN UINTN                        CpuIndex,\r
+  IN CONST VOID                   *Buffer\r
   )\r
 {\r
   EFI_STATUS  Status;\r
@@ -324,10 +329,10 @@ SmmWriteSaveState (
   if (Status == EFI_UNSUPPORTED) {\r
     Status = WriteSaveStateRegister (CpuIndex, Register, Width, Buffer);\r
   }\r
+\r
   return Status;\r
 }\r
 \r
-\r
 /**\r
   C function for SMI handler. To change all processor's SMMBase Register.\r
 \r
@@ -338,8 +343,8 @@ SmmInitHandler (
   VOID\r
   )\r
 {\r
-  UINT32                            ApicId;\r
-  UINTN                             Index;\r
+  UINT32  ApicId;\r
+  UINTN   Index;\r
 \r
   //\r
   // Update SMM IDT entries' code segment and load IDT\r
@@ -384,6 +389,7 @@ SmmInitHandler (
       return;\r
     }\r
   }\r
+\r
   ASSERT (FALSE);\r
 }\r
 \r
@@ -427,7 +433,7 @@ SmmRelocateBases (
   gcSmiInitGdtr.Base  = gcSmiGdtr.Base;\r
   gcSmiInitGdtr.Limit = gcSmiGdtr.Limit;\r
 \r
-  U8Ptr = (UINT8*)(UINTN)(SMM_DEFAULT_SMBASE + SMM_HANDLER_OFFSET);\r
+  U8Ptr       = (UINT8 *)(UINTN)(SMM_DEFAULT_SMBASE + SMM_HANDLER_OFFSET);\r
   CpuStatePtr = (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET);\r
 \r
   //\r
@@ -459,7 +465,8 @@ SmmRelocateBases (
       //\r
       // Wait for this AP to finish its 1st SMI\r
       //\r
-      while (!mRebased[Index]);\r
+      while (!mRebased[Index]) {\r
+      }\r
     } else {\r
       //\r
       // BSP will be Relocated later\r
@@ -477,7 +484,8 @@ SmmRelocateBases (
   //\r
   // Wait for the BSP to finish its 1st SMI\r
   //\r
-  while (!mRebased[BspIndex]);\r
+  while (!mRebased[BspIndex]) {\r
+  }\r
 \r
   //\r
   // Restore contents at address 0x38000\r
@@ -537,24 +545,24 @@ PiCpuSmmEntry (
   IN EFI_SYSTEM_TABLE  *SystemTable\r
   )\r
 {\r
-  EFI_STATUS                 Status;\r
-  EFI_MP_SERVICES_PROTOCOL   *MpServices;\r
-  UINTN                      NumberOfEnabledProcessors;\r
-  UINTN                      Index;\r
-  VOID                       *Buffer;\r
-  UINTN                      BufferPages;\r
-  UINTN                      TileCodeSize;\r
-  UINTN                      TileDataSize;\r
-  UINTN                      TileSize;\r
-  UINT8                      *Stacks;\r
-  VOID                       *Registration;\r
-  UINT32                     RegEax;\r
-  UINT32                     RegEbx;\r
-  UINT32                     RegEcx;\r
-  UINT32                     RegEdx;\r
-  UINTN                      FamilyId;\r
-  UINTN                      ModelId;\r
-  UINT32                     Cr3;\r
+  EFI_STATUS                Status;\r
+  EFI_MP_SERVICES_PROTOCOL  *MpServices;\r
+  UINTN                     NumberOfEnabledProcessors;\r
+  UINTN                     Index;\r
+  VOID                      *Buffer;\r
+  UINTN                     BufferPages;\r
+  UINTN                     TileCodeSize;\r
+  UINTN                     TileDataSize;\r
+  UINTN                     TileSize;\r
+  UINT8                     *Stacks;\r
+  VOID                      *Registration;\r
+  UINT32                    RegEax;\r
+  UINT32                    RegEbx;\r
+  UINT32                    RegEcx;\r
+  UINT32                    RegEdx;\r
+  UINTN                     FamilyId;\r
+  UINTN                     ModelId;\r
+  UINT32                    Cr3;\r
 \r
   //\r
   // Initialize address fixup\r
@@ -598,10 +606,10 @@ PiCpuSmmEntry (
   // A constant BSP index makes no sense because it may be hot removed.\r
   //\r
   DEBUG_CODE_BEGIN ();\r
-    if (FeaturePcdGet (PcdCpuHotPlugSupport)) {\r
+  if (FeaturePcdGet (PcdCpuHotPlugSupport)) {\r
+    ASSERT (FeaturePcdGet (PcdCpuSmmEnableBspElection));\r
+  }\r
 \r
-      ASSERT (FeaturePcdGet (PcdCpuSmmEnableBspElection));\r
-    }\r
   DEBUG_CODE_END ();\r
 \r
   //\r
@@ -625,6 +633,7 @@ PiCpuSmmEntry (
   } else {\r
     mMaxNumberOfCpus = mNumberOfCpus;\r
   }\r
+\r
   gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus = mMaxNumberOfCpus;\r
 \r
   //\r
@@ -702,8 +711,8 @@ PiCpuSmmEntry (
   //\r
   AsmCpuid (CPUID_VERSION_INFO, &RegEax, NULL, NULL, NULL);\r
   FamilyId = (RegEax >> 8) & 0xf;\r
-  ModelId = (RegEax >> 4) & 0xf;\r
-  if (FamilyId == 0x06 || FamilyId == 0x0f) {\r
+  ModelId  = (RegEax >> 4) & 0xf;\r
+  if ((FamilyId == 0x06) || (FamilyId == 0x0f)) {\r
     ModelId = ModelId | ((RegEax >> 12) & 0xf0);\r
   }\r
 \r
@@ -712,6 +721,7 @@ PiCpuSmmEntry (
   if (RegEax >= CPUID_EXTENDED_CPU_SIG) {\r
     AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, NULL, &RegEdx);\r
   }\r
+\r
   //\r
   // Determine the mode of the CPU at the time an SMI occurs\r
   //   Intel(R) 64 and IA-32 Architectures Software Developer's Manual\r
@@ -721,8 +731,9 @@ PiCpuSmmEntry (
   if ((RegEdx & BIT29) != 0) {\r
     mSmmSaveStateRegisterLma = EFI_SMM_SAVE_STATE_REGISTER_LMA_64BIT;\r
   }\r
+\r
   if (FamilyId == 0x06) {\r
-    if (ModelId == 0x17 || ModelId == 0x0f || ModelId == 0x1c) {\r
+    if ((ModelId == 0x17) || (ModelId == 0x0f) || (ModelId == 0x1c)) {\r
       mSmmSaveStateRegisterLma = EFI_SMM_SAVE_STATE_REGISTER_LMA_64BIT;\r
     }\r
   }\r
@@ -739,17 +750,18 @@ PiCpuSmmEntry (
         mCetSupported = FALSE;\r
         PatchInstructionX86 (mPatchCetSupported, mCetSupported, 1);\r
       }\r
+\r
       if (mCetSupported) {\r
         AsmCpuidEx (CPUID_EXTENDED_STATE, CPUID_EXTENDED_STATE_SUB_LEAF, NULL, &RegEbx, &RegEcx, NULL);\r
         DEBUG ((DEBUG_INFO, "CPUID[D/1] EBX - 0x%08x, ECX - 0x%08x\n", RegEbx, RegEcx));\r
         AsmCpuidEx (CPUID_EXTENDED_STATE, 11, &RegEax, NULL, &RegEcx, NULL);\r
         DEBUG ((DEBUG_INFO, "CPUID[D/11] EAX - 0x%08x, ECX - 0x%08x\n", RegEax, RegEcx));\r
-        AsmCpuidEx(CPUID_EXTENDED_STATE, 12, &RegEax, NULL, &RegEcx, NULL);\r
+        AsmCpuidEx (CPUID_EXTENDED_STATE, 12, &RegEax, NULL, &RegEcx, NULL);\r
         DEBUG ((DEBUG_INFO, "CPUID[D/12] EAX - 0x%08x, ECX - 0x%08x\n", RegEax, RegEcx));\r
       }\r
     } else {\r
       mCetSupported = FALSE;\r
-      PatchInstructionX86(mPatchCetSupported, mCetSupported, 1);\r
+      PatchInstructionX86 (mPatchCetSupported, mCetSupported, 1);\r
     }\r
   } else {\r
     mCetSupported = FALSE;\r
@@ -762,11 +774,11 @@ PiCpuSmmEntry (
   // This size is rounded up to nearest power of 2.\r
   //\r
   TileCodeSize = GetSmiHandlerSize ();\r
-  TileCodeSize = ALIGN_VALUE(TileCodeSize, SIZE_4KB);\r
+  TileCodeSize = ALIGN_VALUE (TileCodeSize, SIZE_4KB);\r
   TileDataSize = (SMRAM_SAVE_STATE_MAP_OFFSET - SMM_PSD_OFFSET) + sizeof (SMRAM_SAVE_STATE_MAP);\r
-  TileDataSize = ALIGN_VALUE(TileDataSize, SIZE_4KB);\r
-  TileSize = TileDataSize + TileCodeSize - 1;\r
-  TileSize = 2 * GetPowerOfTwo32 ((UINT32)TileSize);\r
+  TileDataSize = ALIGN_VALUE (TileDataSize, SIZE_4KB);\r
+  TileSize     = TileDataSize + TileCodeSize - 1;\r
+  TileSize     = 2 * GetPowerOfTwo32 ((UINT32)TileSize);\r
   DEBUG ((DEBUG_INFO, "SMRAM TileSize = 0x%08x (0x%08x, 0x%08x)\n", TileSize, TileCodeSize, TileDataSize));\r
 \r
   //\r
@@ -796,8 +808,9 @@ PiCpuSmmEntry (
   } else {\r
     Buffer = AllocateAlignedCodePages (BufferPages, SIZE_4KB);\r
   }\r
+\r
   ASSERT (Buffer != NULL);\r
-  DEBUG ((DEBUG_INFO, "SMRAM SaveState Buffer (0x%08x, 0x%08x)\n", Buffer, EFI_PAGES_TO_SIZE(BufferPages)));\r
+  DEBUG ((DEBUG_INFO, "SMRAM SaveState Buffer (0x%08x, 0x%08x)\n", Buffer, EFI_PAGES_TO_SIZE (BufferPages)));\r
 \r
   //\r
   // Allocate buffer for pointers to array in  SMM_CPU_PRIVATE_DATA.\r
@@ -832,17 +845,19 @@ PiCpuSmmEntry (
   // size for each CPU in the platform\r
   //\r
   for (Index = 0; Index < mMaxNumberOfCpus; Index++) {\r
-    mCpuHotPlugData.SmBase[Index]          = (UINTN)Buffer + Index * TileSize - SMM_HANDLER_OFFSET;\r
-    gSmmCpuPrivate->CpuSaveStateSize[Index] = sizeof(SMRAM_SAVE_STATE_MAP);\r
+    mCpuHotPlugData.SmBase[Index]           = (UINTN)Buffer + Index * TileSize - SMM_HANDLER_OFFSET;\r
+    gSmmCpuPrivate->CpuSaveStateSize[Index] = sizeof (SMRAM_SAVE_STATE_MAP);\r
     gSmmCpuPrivate->CpuSaveState[Index]     = (VOID *)(mCpuHotPlugData.SmBase[Index] + SMRAM_SAVE_STATE_MAP_OFFSET);\r
-    gSmmCpuPrivate->Operation[Index] = SmmCpuNone;\r
+    gSmmCpuPrivate->Operation[Index]        = SmmCpuNone;\r
 \r
     if (Index < mNumberOfCpus) {\r
       Status = MpServices->GetProcessorInfo (MpServices, Index, &gSmmCpuPrivate->ProcessorInfo[Index]);\r
       ASSERT_EFI_ERROR (Status);\r
       mCpuHotPlugData.ApicId[Index] = gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId;\r
 \r
-      DEBUG ((DEBUG_INFO, "CPU[%03x]  APIC ID=%04x  SMBASE=%08x  SaveState=%08x  Size=%08x\n",\r
+      DEBUG ((\r
+        DEBUG_INFO,\r
+        "CPU[%03x]  APIC ID=%04x  SMBASE=%08x  SaveState=%08x  Size=%08x\n",\r
         Index,\r
         (UINT32)gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId,\r
         mCpuHotPlugData.SmBase[Index],\r
@@ -851,7 +866,7 @@ PiCpuSmmEntry (
         ));\r
     } else {\r
       gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId = INVALID_APIC_ID;\r
-      mCpuHotPlugData.ApicId[Index] = INVALID_APIC_ID;\r
+      mCpuHotPlugData.ApicId[Index]                    = INVALID_APIC_ID;\r
     }\r
   }\r
 \r
@@ -916,10 +931,10 @@ PiCpuSmmEntry (
     }\r
   }\r
 \r
-  Stacks = (UINT8 *) AllocatePages (gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus * (EFI_SIZE_TO_PAGES (mSmmStackSize + mSmmShadowStackSize)));\r
+  Stacks = (UINT8 *)AllocatePages (gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus * (EFI_SIZE_TO_PAGES (mSmmStackSize + mSmmShadowStackSize)));\r
   ASSERT (Stacks != NULL);\r
   mSmmStackArrayBase = (UINTN)Stacks;\r
-  mSmmStackArrayEnd = mSmmStackArrayBase + gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus * (mSmmStackSize + mSmmShadowStackSize) - 1;\r
+  mSmmStackArrayEnd  = mSmmStackArrayBase + gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus * (mSmmStackSize + mSmmShadowStackSize) - 1;\r
 \r
   DEBUG ((DEBUG_INFO, "Stacks                   - 0x%x\n", Stacks));\r
   DEBUG ((DEBUG_INFO, "mSmmStackSize            - 0x%x\n", mSmmStackSize));\r
@@ -933,7 +948,7 @@ PiCpuSmmEntry (
   //\r
   PatchInstructionX86 (\r
     gPatchSmmInitStack,\r
-    (UINTN) (Stacks + mSmmStackSize - sizeof (UINTN)),\r
+    (UINTN)(Stacks + mSmmStackSize - sizeof (UINTN)),\r
     sizeof (UINTN)\r
     );\r
 \r
@@ -977,8 +992,8 @@ PiCpuSmmEntry (
       if (FeaturePcdGet (PcdCpuSmmStackGuard)) {\r
         SetNotPresentPage (\r
           Cr3,\r
-          (EFI_PHYSICAL_ADDRESS)(UINTN)Stacks + mSmmStackSize + EFI_PAGES_TO_SIZE(1) + (mSmmStackSize + mSmmShadowStackSize) * Index,\r
-          EFI_PAGES_TO_SIZE(1)\r
+          (EFI_PHYSICAL_ADDRESS)(UINTN)Stacks + mSmmStackSize + EFI_PAGES_TO_SIZE (1) + (mSmmStackSize + mSmmShadowStackSize) * Index,\r
+          EFI_PAGES_TO_SIZE (1)\r
           );\r
       }\r
     }\r
@@ -997,7 +1012,8 @@ PiCpuSmmEntry (
   //\r
   Status = SystemTable->BootServices->InstallMultipleProtocolInterfaces (\r
                                         &gSmmCpuPrivate->SmmCpuHandle,\r
-                                        &gEfiSmmConfigurationProtocolGuid, &gSmmCpuPrivate->SmmConfiguration,\r
+                                        &gEfiSmmConfigurationProtocolGuid,\r
+                                        &gSmmCpuPrivate->SmmConfiguration,\r
                                         NULL\r
                                         );\r
   ASSERT_EFI_ERROR (Status);\r
@@ -1087,17 +1103,17 @@ PiCpuSmmEntry (
 **/\r
 VOID\r
 FindSmramInfo (\r
-  OUT UINT32   *SmrrBase,\r
-  OUT UINT32   *SmrrSize\r
+  OUT UINT32  *SmrrBase,\r
+  OUT UINT32  *SmrrSize\r
   )\r
 {\r
-  EFI_STATUS                        Status;\r
-  UINTN                             Size;\r
-  EFI_SMM_ACCESS2_PROTOCOL          *SmmAccess;\r
-  EFI_SMRAM_DESCRIPTOR              *CurrentSmramRange;\r
-  UINTN                             Index;\r
-  UINT64                            MaxSize;\r
-  BOOLEAN                           Found;\r
+  EFI_STATUS                Status;\r
+  UINTN                     Size;\r
+  EFI_SMM_ACCESS2_PROTOCOL  *SmmAccess;\r
+  EFI_SMRAM_DESCRIPTOR      *CurrentSmramRange;\r
+  UINTN                     Index;\r
+  UINT64                    MaxSize;\r
+  BOOLEAN                   Found;\r
 \r
   //\r
   // Get SMM Access Protocol\r
@@ -1108,7 +1124,7 @@ FindSmramInfo (
   //\r
   // Get SMRAM information\r
   //\r
-  Size = 0;\r
+  Size   = 0;\r
   Status = SmmAccess->GetCapabilities (SmmAccess, &Size, NULL);\r
   ASSERT (Status == EFI_BUFFER_TOO_SMALL);\r
 \r
@@ -1135,7 +1151,7 @@ FindSmramInfo (
     if (mSmmCpuSmramRanges[Index].CpuStart >= BASE_1MB) {\r
       if ((mSmmCpuSmramRanges[Index].CpuStart + mSmmCpuSmramRanges[Index].PhysicalSize) <= SMRR_MAX_ADDRESS) {\r
         if (mSmmCpuSmramRanges[Index].PhysicalSize >= MaxSize) {\r
-          MaxSize = mSmmCpuSmramRanges[Index].PhysicalSize;\r
+          MaxSize           = mSmmCpuSmramRanges[Index].PhysicalSize;\r
           CurrentSmramRange = &mSmmCpuSmramRanges[Index];\r
         }\r
       }\r
@@ -1150,14 +1166,15 @@ FindSmramInfo (
   do {\r
     Found = FALSE;\r
     for (Index = 0; Index < mSmmCpuSmramRangeCount; Index++) {\r
-      if (mSmmCpuSmramRanges[Index].CpuStart < *SmrrBase &&\r
-          *SmrrBase == (mSmmCpuSmramRanges[Index].CpuStart + mSmmCpuSmramRanges[Index].PhysicalSize)) {\r
+      if ((mSmmCpuSmramRanges[Index].CpuStart < *SmrrBase) &&\r
+          (*SmrrBase == (mSmmCpuSmramRanges[Index].CpuStart + mSmmCpuSmramRanges[Index].PhysicalSize)))\r
+      {\r
         *SmrrBase = (UINT32)mSmmCpuSmramRanges[Index].CpuStart;\r
         *SmrrSize = (UINT32)(*SmrrSize + mSmmCpuSmramRanges[Index].PhysicalSize);\r
-        Found = TRUE;\r
-      } else if ((*SmrrBase + *SmrrSize) == mSmmCpuSmramRanges[Index].CpuStart && mSmmCpuSmramRanges[Index].PhysicalSize > 0) {\r
+        Found     = TRUE;\r
+      } else if (((*SmrrBase + *SmrrSize) == mSmmCpuSmramRanges[Index].CpuStart) && (mSmmCpuSmramRanges[Index].PhysicalSize > 0)) {\r
         *SmrrSize = (UINT32)(*SmrrSize + mSmmCpuSmramRanges[Index].PhysicalSize);\r
-        Found = TRUE;\r
+        Found     = TRUE;\r
       }\r
     }\r
   } while (Found);\r
@@ -1272,6 +1289,7 @@ ConfigSmmCodeAccessCheck (
         //\r
         continue;\r
       }\r
+\r
       //\r
       // Acquire Config SMM Code Access Check spin lock.  The AP will release the\r
       // spin lock when it is done executing ConfigSmmCodeAccessCheckOnCurrentProcessor().\r
@@ -1316,7 +1334,7 @@ ConfigSmmCodeAccessCheck (
 **/\r
 VOID *\r
 AllocatePageTableMemory (\r
-  IN UINTN           Pages\r
+  IN UINTN  Pages\r
   )\r
 {\r
   VOID  *Buffer;\r
@@ -1325,6 +1343,7 @@ AllocatePageTableMemory (
   if (Buffer != NULL) {\r
     return Buffer;\r
   }\r
+\r
   return AllocatePages (Pages);\r
 }\r
 \r
@@ -1337,7 +1356,7 @@ AllocatePageTableMemory (
 **/\r
 VOID *\r
 AllocateCodePages (\r
-  IN UINTN           Pages\r
+  IN UINTN  Pages\r
   )\r
 {\r
   EFI_STATUS            Status;\r
@@ -1351,7 +1370,8 @@ AllocateCodePages (
   if (EFI_ERROR (Status)) {\r
     return NULL;\r
   }\r
-  return (VOID *) (UINTN) Memory;\r
+\r
+  return (VOID *)(UINTN)Memory;\r
 }\r
 \r
 /**\r
@@ -1366,8 +1386,8 @@ AllocateCodePages (
 **/\r
 VOID *\r
 AllocateAlignedCodePages (\r
-  IN UINTN            Pages,\r
-  IN UINTN            Alignment\r
+  IN UINTN  Pages,\r
+  IN UINTN  Alignment\r
   )\r
 {\r
   EFI_STATUS            Status;\r
@@ -1385,23 +1405,25 @@ AllocateAlignedCodePages (
   if (Pages == 0) {\r
     return NULL;\r
   }\r
+\r
   if (Alignment > EFI_PAGE_SIZE) {\r
     //\r
     // Calculate the total number of pages since alignment is larger than page size.\r
     //\r
-    AlignmentMask  = Alignment - 1;\r
-    RealPages      = Pages + EFI_SIZE_TO_PAGES (Alignment);\r
+    AlignmentMask = Alignment - 1;\r
+    RealPages     = Pages + EFI_SIZE_TO_PAGES (Alignment);\r
     //\r
     // Make sure that Pages plus EFI_SIZE_TO_PAGES (Alignment) does not overflow.\r
     //\r
     ASSERT (RealPages > Pages);\r
 \r
-    Status         = gSmst->SmmAllocatePages (AllocateAnyPages, EfiRuntimeServicesCode, RealPages, &Memory);\r
+    Status = gSmst->SmmAllocatePages (AllocateAnyPages, EfiRuntimeServicesCode, RealPages, &Memory);\r
     if (EFI_ERROR (Status)) {\r
       return NULL;\r
     }\r
-    AlignedMemory  = ((UINTN) Memory + AlignmentMask) & ~AlignmentMask;\r
-    UnalignedPages = EFI_SIZE_TO_PAGES (AlignedMemory - (UINTN) Memory);\r
+\r
+    AlignedMemory  = ((UINTN)Memory + AlignmentMask) & ~AlignmentMask;\r
+    UnalignedPages = EFI_SIZE_TO_PAGES (AlignedMemory - (UINTN)Memory);\r
     if (UnalignedPages > 0) {\r
       //\r
       // Free first unaligned page(s).\r
@@ -1409,6 +1431,7 @@ AllocateAlignedCodePages (
       Status = gSmst->SmmFreePages (Memory, UnalignedPages);\r
       ASSERT_EFI_ERROR (Status);\r
     }\r
+\r
     Memory         = AlignedMemory + EFI_PAGES_TO_SIZE (Pages);\r
     UnalignedPages = RealPages - Pages - UnalignedPages;\r
     if (UnalignedPages > 0) {\r
@@ -1426,9 +1449,11 @@ AllocateAlignedCodePages (
     if (EFI_ERROR (Status)) {\r
       return NULL;\r
     }\r
-    AlignedMemory  = (UINTN) Memory;\r
+\r
+    AlignedMemory = (UINTN)Memory;\r
   }\r
-  return (VOID *) AlignedMemory;\r
+\r
+  return (VOID *)AlignedMemory;\r
 }\r
 \r
 /**\r
@@ -1447,6 +1472,7 @@ PerformRemainingTasks (
     if (FeaturePcdGet (PcdCpuSmmProfileEnable)) {\r
       SmmProfileStart ();\r
     }\r
+\r
     //\r
     // Create a mix of 2MB and 4KB page table. Update some memory ranges absent and execute-disable.\r
     //\r

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
index fc9b748948617aa9c6ee48cc87abec80374619ab..26d07c5b5ea0bcb5f7761d3beb14fb1c82533f1a 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
@@ -74,69 +74,69 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
 typedef union {\r
   struct {\r
     // enable shadow stacks\r
-    UINT32  SH_STK_ENP:1;\r
+    UINT32    SH_STK_ENP              : 1;\r
     // enable the WRSS{D,Q}W instructions.\r
-    UINT32  WR_SHSTK_EN:1;\r
+    UINT32    WR_SHSTK_EN             : 1;\r
     // enable tracking of indirect call/jmp targets to be ENDBRANCH instruction.\r
-    UINT32  ENDBR_EN:1;\r
+    UINT32    ENDBR_EN                : 1;\r
     // enable legacy compatibility treatment for indirect call/jmp tracking.\r
-    UINT32  LEG_IW_EN:1;\r
+    UINT32    LEG_IW_EN               : 1;\r
     // enable use of no-track prefix on indirect call/jmp.\r
-    UINT32  NO_TRACK_EN:1;\r
+    UINT32    NO_TRACK_EN             : 1;\r
     // disable suppression of CET indirect branch tracking on legacy compatibility.\r
-    UINT32  SUPPRESS_DIS:1;\r
-    UINT32  RSVD:4;\r
+    UINT32    SUPPRESS_DIS            : 1;\r
+    UINT32    RSVD                    : 4;\r
     // indirect branch tracking is suppressed.\r
     // This bit can be written to 1 only if TRACKER is written as IDLE.\r
-    UINT32  SUPPRESS:1;\r
+    UINT32    SUPPRESS                : 1;\r
     // Value of the endbranch state machine\r
     // Values: IDLE (0), WAIT_FOR_ENDBRANCH(1).\r
-    UINT32  TRACKER:1;\r
+    UINT32    TRACKER                 : 1;\r
     // linear address of a bitmap in memory indicating valid\r
     // pages as target of CALL/JMP_indirect that do not land on ENDBRANCH when CET is enabled\r
     // and not suppressed. Valid when ENDBR_EN is 1. Must be machine canonical when written on\r
     // parts that support 64 bit mode. On parts that do not support 64 bit mode, the bits 63:32 are\r
     // reserved and must be 0. This value is extended by 12 bits at the low end to form the base address\r
     // (this automatically aligns the address on a 4-Kbyte boundary).\r
-    UINT32  EB_LEG_BITMAP_BASE_low:12;\r
-    UINT32  EB_LEG_BITMAP_BASE_high:32;\r
+    UINT32    EB_LEG_BITMAP_BASE_low  : 12;\r
+    UINT32    EB_LEG_BITMAP_BASE_high : 32;\r
   } Bits;\r
-  UINT64   Uint64;\r
+  UINT64    Uint64;\r
 } MSR_IA32_CET;\r
 \r
 //\r
 // MSRs required for configuration of SMM Code Access Check\r
 //\r
-#define EFI_MSR_SMM_MCA_CAP                    0x17D\r
-#define  SMM_CODE_ACCESS_CHK_BIT               BIT58\r
+#define EFI_MSR_SMM_MCA_CAP       0x17D\r
+#define  SMM_CODE_ACCESS_CHK_BIT  BIT58\r
 \r
-#define  SMM_FEATURE_CONTROL_LOCK_BIT          BIT0\r
-#define  SMM_CODE_CHK_EN_BIT                   BIT2\r
+#define  SMM_FEATURE_CONTROL_LOCK_BIT  BIT0\r
+#define  SMM_CODE_CHK_EN_BIT           BIT2\r
 \r
 ///\r
 /// Page Table Entry\r
 ///\r
-#define IA32_PG_P                   BIT0\r
-#define IA32_PG_RW                  BIT1\r
-#define IA32_PG_U                   BIT2\r
-#define IA32_PG_WT                  BIT3\r
-#define IA32_PG_CD                  BIT4\r
-#define IA32_PG_A                   BIT5\r
-#define IA32_PG_D                   BIT6\r
-#define IA32_PG_PS                  BIT7\r
-#define IA32_PG_PAT_2M              BIT12\r
-#define IA32_PG_PAT_4K              IA32_PG_PS\r
-#define IA32_PG_PMNT                BIT62\r
-#define IA32_PG_NX                  BIT63\r
-\r
-#define PAGE_ATTRIBUTE_BITS         (IA32_PG_D | IA32_PG_A | IA32_PG_U | IA32_PG_RW | IA32_PG_P)\r
+#define IA32_PG_P       BIT0\r
+#define IA32_PG_RW      BIT1\r
+#define IA32_PG_U       BIT2\r
+#define IA32_PG_WT      BIT3\r
+#define IA32_PG_CD      BIT4\r
+#define IA32_PG_A       BIT5\r
+#define IA32_PG_D       BIT6\r
+#define IA32_PG_PS      BIT7\r
+#define IA32_PG_PAT_2M  BIT12\r
+#define IA32_PG_PAT_4K  IA32_PG_PS\r
+#define IA32_PG_PMNT    BIT62\r
+#define IA32_PG_NX      BIT63\r
+\r
+#define PAGE_ATTRIBUTE_BITS  (IA32_PG_D | IA32_PG_A | IA32_PG_U | IA32_PG_RW | IA32_PG_P)\r
 //\r
 // Bits 1, 2, 5, 6 are reserved in the IA32 PAE PDPTE\r
 // X64 PAE PDPTE does not have such restriction\r
 //\r
-#define IA32_PAE_PDPTE_ATTRIBUTE_BITS    (IA32_PG_P)\r
+#define IA32_PAE_PDPTE_ATTRIBUTE_BITS  (IA32_PG_P)\r
 \r
-#define PAGE_PROGATE_BITS           (IA32_PG_NX | PAGE_ATTRIBUTE_BITS)\r
+#define PAGE_PROGATE_BITS  (IA32_PG_NX | PAGE_ATTRIBUTE_BITS)\r
 \r
 #define PAGING_4K_MASK  0xFFF\r
 #define PAGING_2M_MASK  0x1FFFFF\r
@@ -144,11 +144,11 @@ typedef union {
 \r
 #define PAGING_PAE_INDEX_MASK  0x1FF\r
 \r
-#define PAGING_4K_ADDRESS_MASK_64 0x000FFFFFFFFFF000ull\r
-#define PAGING_2M_ADDRESS_MASK_64 0x000FFFFFFFE00000ull\r
-#define PAGING_1G_ADDRESS_MASK_64 0x000FFFFFC0000000ull\r
+#define PAGING_4K_ADDRESS_MASK_64  0x000FFFFFFFFFF000ull\r
+#define PAGING_2M_ADDRESS_MASK_64  0x000FFFFFFFE00000ull\r
+#define PAGING_1G_ADDRESS_MASK_64  0x000FFFFFC0000000ull\r
 \r
-#define SMRR_MAX_ADDRESS       BASE_4GB\r
+#define SMRR_MAX_ADDRESS  BASE_4GB\r
 \r
 typedef enum {\r
   PageNone,\r
@@ -158,28 +158,28 @@ typedef enum {
 } PAGE_ATTRIBUTE;\r
 \r
 typedef struct {\r
-  PAGE_ATTRIBUTE   Attribute;\r
-  UINT64           Length;\r
-  UINT64           AddressMask;\r
+  PAGE_ATTRIBUTE    Attribute;\r
+  UINT64            Length;\r
+  UINT64            AddressMask;\r
 } PAGE_ATTRIBUTE_TABLE;\r
 \r
 //\r
 // Size of Task-State Segment defined in IA32 Manual\r
 //\r
-#define TSS_SIZE              104\r
-#define EXCEPTION_TSS_SIZE    (TSS_SIZE + 4) // Add 4 bytes SSP\r
-#define TSS_X64_IST1_OFFSET   36\r
-#define TSS_IA32_CR3_OFFSET   28\r
-#define TSS_IA32_ESP_OFFSET   56\r
-#define TSS_IA32_SSP_OFFSET   104\r
+#define TSS_SIZE             104\r
+#define EXCEPTION_TSS_SIZE   (TSS_SIZE + 4)  // Add 4 bytes SSP\r
+#define TSS_X64_IST1_OFFSET  36\r
+#define TSS_IA32_CR3_OFFSET  28\r
+#define TSS_IA32_ESP_OFFSET  56\r
+#define TSS_IA32_SSP_OFFSET  104\r
 \r
-#define CR0_WP                BIT16\r
+#define CR0_WP  BIT16\r
 \r
 //\r
 // Code select value\r
 //\r
-#define PROTECT_MODE_CODE_SEGMENT          0x08\r
-#define LONG_MODE_CODE_SEGMENT             0x38\r
+#define PROTECT_MODE_CODE_SEGMENT  0x08\r
+#define LONG_MODE_CODE_SEGMENT     0x38\r
 \r
 //\r
 // The size 0x20 must be bigger than\r
@@ -189,31 +189,31 @@ typedef struct {
 //\r
 #define BACK_BUF_SIZE  0x20\r
 \r
-#define EXCEPTION_VECTOR_NUMBER     0x20\r
+#define EXCEPTION_VECTOR_NUMBER  0x20\r
 \r
-#define INVALID_APIC_ID 0xFFFFFFFFFFFFFFFFULL\r
+#define INVALID_APIC_ID  0xFFFFFFFFFFFFFFFFULL\r
 \r
-typedef UINT32                              SMM_CPU_ARRIVAL_EXCEPTIONS;\r
-#define ARRIVAL_EXCEPTION_BLOCKED           0x1\r
-#define ARRIVAL_EXCEPTION_DELAYED           0x2\r
-#define ARRIVAL_EXCEPTION_SMI_DISABLED      0x4\r
+typedef UINT32 SMM_CPU_ARRIVAL_EXCEPTIONS;\r
+#define ARRIVAL_EXCEPTION_BLOCKED       0x1\r
+#define ARRIVAL_EXCEPTION_DELAYED       0x2\r
+#define ARRIVAL_EXCEPTION_SMI_DISABLED  0x4\r
 \r
 //\r
 // Wrapper used to convert EFI_AP_PROCEDURE2 and EFI_AP_PROCEDURE.\r
 //\r
 typedef struct {\r
-  EFI_AP_PROCEDURE  Procedure;\r
-  VOID              *ProcedureArgument;\r
+  EFI_AP_PROCEDURE    Procedure;\r
+  VOID                *ProcedureArgument;\r
 } PROCEDURE_WRAPPER;\r
 \r
 #define PROCEDURE_TOKEN_SIGNATURE  SIGNATURE_32 ('P', 'R', 'T', 'S')\r
 \r
 typedef struct {\r
-  UINTN                   Signature;\r
-  LIST_ENTRY              Link;\r
+  UINTN              Signature;\r
+  LIST_ENTRY         Link;\r
 \r
-  SPIN_LOCK               *SpinLock;\r
-  volatile UINT32         RunningApCount;\r
+  SPIN_LOCK          *SpinLock;\r
+  volatile UINT32    RunningApCount;\r
 } PROCEDURE_TOKEN;\r
 \r
 #define PROCEDURE_TOKEN_FROM_LINK(a)  CR (a, PROCEDURE_TOKEN, Link, PROCEDURE_TOKEN_SIGNATURE)\r
@@ -221,10 +221,10 @@ typedef struct {
 #define TOKEN_BUFFER_SIGNATURE  SIGNATURE_32 ('T', 'K', 'B', 'S')\r
 \r
 typedef struct {\r
-  UINTN                   Signature;\r
-  LIST_ENTRY              Link;\r
+  UINTN         Signature;\r
+  LIST_ENTRY    Link;\r
 \r
-  UINT8                   *Buffer;\r
+  UINT8         *Buffer;\r
 } TOKEN_BUFFER;\r
 \r
 #define TOKEN_BUFFER_FROM_LINK(a)  CR (a, TOKEN_BUFFER, Link, TOKEN_BUFFER_SIGNATURE)\r
@@ -237,33 +237,33 @@ typedef struct {
 #define SMM_CPU_PRIVATE_DATA_SIGNATURE  SIGNATURE_32 ('s', 'c', 'p', 'u')\r
 \r
 typedef struct {\r
-  UINTN                           Signature;\r
+  UINTN                             Signature;\r
 \r
-  EFI_HANDLE                      SmmCpuHandle;\r
+  EFI_HANDLE                        SmmCpuHandle;\r
 \r
-  EFI_PROCESSOR_INFORMATION       *ProcessorInfo;\r
-  SMM_CPU_OPERATION               *Operation;\r
-  UINTN                           *CpuSaveStateSize;\r
-  VOID                            **CpuSaveState;\r
+  EFI_PROCESSOR_INFORMATION         *ProcessorInfo;\r
+  SMM_CPU_OPERATION                 *Operation;\r
+  UINTN                             *CpuSaveStateSize;\r
+  VOID                              **CpuSaveState;\r
 \r
-  EFI_SMM_RESERVED_SMRAM_REGION   SmmReservedSmramRegion[1];\r
-  EFI_SMM_ENTRY_CONTEXT           SmmCoreEntryContext;\r
-  EFI_SMM_ENTRY_POINT             SmmCoreEntry;\r
+  EFI_SMM_RESERVED_SMRAM_REGION     SmmReservedSmramRegion[1];\r
+  EFI_SMM_ENTRY_CONTEXT             SmmCoreEntryContext;\r
+  EFI_SMM_ENTRY_POINT               SmmCoreEntry;\r
 \r
-  EFI_SMM_CONFIGURATION_PROTOCOL  SmmConfiguration;\r
+  EFI_SMM_CONFIGURATION_PROTOCOL    SmmConfiguration;\r
 \r
-  PROCEDURE_WRAPPER               *ApWrapperFunc;\r
-  LIST_ENTRY                      TokenList;\r
-  LIST_ENTRY                      *FirstFreeToken;\r
+  PROCEDURE_WRAPPER                 *ApWrapperFunc;\r
+  LIST_ENTRY                        TokenList;\r
+  LIST_ENTRY                        *FirstFreeToken;\r
 } SMM_CPU_PRIVATE_DATA;\r
 \r
 extern SMM_CPU_PRIVATE_DATA  *gSmmCpuPrivate;\r
-extern CPU_HOT_PLUG_DATA      mCpuHotPlugData;\r
-extern UINTN                  mMaxNumberOfCpus;\r
-extern UINTN                  mNumberOfCpus;\r
-extern EFI_SMM_CPU_PROTOCOL   mSmmCpu;\r
-extern EFI_MM_MP_PROTOCOL     mSmmMp;\r
-extern UINTN                  mInternalCr3;\r
+extern CPU_HOT_PLUG_DATA     mCpuHotPlugData;\r
+extern UINTN                 mMaxNumberOfCpus;\r
+extern UINTN                 mNumberOfCpus;\r
+extern EFI_SMM_CPU_PROTOCOL  mSmmCpu;\r
+extern EFI_MM_MP_PROTOCOL    mSmmMp;\r
+extern UINTN                 mInternalCr3;\r
 \r
 ///\r
 /// The mode of the CPU at the time an SMI occurs\r
@@ -291,11 +291,11 @@ extern UINT8  mSmmSaveStateRegisterLma;
 EFI_STATUS\r
 EFIAPI\r
 SmmReadSaveState (\r
-  IN CONST EFI_SMM_CPU_PROTOCOL         *This,\r
-  IN UINTN                              Width,\r
-  IN EFI_SMM_SAVE_STATE_REGISTER        Register,\r
-  IN UINTN                              CpuIndex,\r
-  OUT VOID                              *Buffer\r
+  IN CONST EFI_SMM_CPU_PROTOCOL   *This,\r
+  IN UINTN                        Width,\r
+  IN EFI_SMM_SAVE_STATE_REGISTER  Register,\r
+  IN UINTN                        CpuIndex,\r
+  OUT VOID                        *Buffer\r
   );\r
 \r
 /**\r
@@ -315,11 +315,11 @@ SmmReadSaveState (
 EFI_STATUS\r
 EFIAPI\r
 SmmWriteSaveState (\r
-  IN CONST EFI_SMM_CPU_PROTOCOL         *This,\r
-  IN UINTN                              Width,\r
-  IN EFI_SMM_SAVE_STATE_REGISTER        Register,\r
-  IN UINTN                              CpuIndex,\r
-  IN CONST VOID                         *Buffer\r
+  IN CONST EFI_SMM_CPU_PROTOCOL   *This,\r
+  IN UINTN                        Width,\r
+  IN EFI_SMM_SAVE_STATE_REGISTER  Register,\r
+  IN UINTN                        CpuIndex,\r
+  IN CONST VOID                   *Buffer\r
   );\r
 \r
 /**\r
@@ -376,16 +376,16 @@ WriteSaveStateRegister (
   IN CONST VOID                   *Buffer\r
   );\r
 \r
-extern CONST UINT8                  gcSmmInitTemplate[];\r
-extern CONST UINT16                 gcSmmInitSize;\r
-X86_ASSEMBLY_PATCH_LABEL            gPatchSmmCr0;\r
-extern UINT32                       mSmmCr0;\r
-X86_ASSEMBLY_PATCH_LABEL            gPatchSmmCr3;\r
-extern UINT32                       mSmmCr4;\r
-X86_ASSEMBLY_PATCH_LABEL            gPatchSmmCr4;\r
-X86_ASSEMBLY_PATCH_LABEL            gPatchSmmInitStack;\r
-X86_ASSEMBLY_PATCH_LABEL            mPatchCetSupported;\r
-extern BOOLEAN                      mCetSupported;\r
+extern CONST UINT8        gcSmmInitTemplate[];\r
+extern CONST UINT16       gcSmmInitSize;\r
+X86_ASSEMBLY_PATCH_LABEL  gPatchSmmCr0;\r
+extern UINT32             mSmmCr0;\r
+X86_ASSEMBLY_PATCH_LABEL  gPatchSmmCr3;\r
+extern UINT32             mSmmCr4;\r
+X86_ASSEMBLY_PATCH_LABEL  gPatchSmmCr4;\r
+X86_ASSEMBLY_PATCH_LABEL  gPatchSmmInitStack;\r
+X86_ASSEMBLY_PATCH_LABEL  mPatchCetSupported;\r
+extern BOOLEAN            mCetSupported;\r
 \r
 /**\r
   Semaphore operation for all processor relocate SMMBase.\r
@@ -400,13 +400,13 @@ SmmRelocationSemaphoreComplete (
 /// The type of SMM CPU Information\r
 ///\r
 typedef struct {\r
-  SPIN_LOCK                         *Busy;\r
-  volatile EFI_AP_PROCEDURE2        Procedure;\r
-  volatile VOID                     *Parameter;\r
-  volatile UINT32                   *Run;\r
-  volatile BOOLEAN                  *Present;\r
-  PROCEDURE_TOKEN                   *Token;\r
-  EFI_STATUS                        *Status;\r
+  SPIN_LOCK                     *Busy;\r
+  volatile EFI_AP_PROCEDURE2    Procedure;\r
+  volatile VOID                 *Parameter;\r
+  volatile UINT32               *Run;\r
+  volatile BOOLEAN              *Present;\r
+  PROCEDURE_TOKEN               *Token;\r
+  EFI_STATUS                    *Status;\r
 } SMM_CPU_DATA_BLOCK;\r
 \r
 typedef enum {\r
@@ -432,56 +432,56 @@ typedef struct {
   VOID                          *StartupProcArgs;\r
 } SMM_DISPATCHER_MP_SYNC_DATA;\r
 \r
-#define SMM_PSD_OFFSET              0xfb00\r
+#define SMM_PSD_OFFSET  0xfb00\r
 \r
 ///\r
 /// All global semaphores' pointer\r
 ///\r
 typedef struct {\r
-  volatile UINT32      *Counter;\r
-  volatile BOOLEAN     *InsideSmm;\r
-  volatile BOOLEAN     *AllCpusInSync;\r
-  SPIN_LOCK            *PFLock;\r
-  SPIN_LOCK            *CodeAccessCheckLock;\r
+  volatile UINT32     *Counter;\r
+  volatile BOOLEAN    *InsideSmm;\r
+  volatile BOOLEAN    *AllCpusInSync;\r
+  SPIN_LOCK           *PFLock;\r
+  SPIN_LOCK           *CodeAccessCheckLock;\r
 } SMM_CPU_SEMAPHORE_GLOBAL;\r
 \r
 ///\r
 /// All semaphores for each processor\r
 ///\r
 typedef struct {\r
-  SPIN_LOCK                         *Busy;\r
-  volatile UINT32                   *Run;\r
-  volatile BOOLEAN                  *Present;\r
-  SPIN_LOCK                         *Token;\r
+  SPIN_LOCK           *Busy;\r
+  volatile UINT32     *Run;\r
+  volatile BOOLEAN    *Present;\r
+  SPIN_LOCK           *Token;\r
 } SMM_CPU_SEMAPHORE_CPU;\r
 \r
 ///\r
 /// All semaphores' information\r
 ///\r
 typedef struct {\r
-  SMM_CPU_SEMAPHORE_GLOBAL          SemaphoreGlobal;\r
-  SMM_CPU_SEMAPHORE_CPU             SemaphoreCpu;\r
+  SMM_CPU_SEMAPHORE_GLOBAL    SemaphoreGlobal;\r
+  SMM_CPU_SEMAPHORE_CPU       SemaphoreCpu;\r
 } SMM_CPU_SEMAPHORES;\r
 \r
-extern IA32_DESCRIPTOR                     gcSmiGdtr;\r
-extern EFI_PHYSICAL_ADDRESS                mGdtBuffer;\r
-extern UINTN                               mGdtBufferSize;\r
-extern IA32_DESCRIPTOR                     gcSmiIdtr;\r
-extern VOID                                *gcSmiIdtrPtr;\r
-extern UINT64                              gPhyMask;\r
-extern SMM_DISPATCHER_MP_SYNC_DATA         *mSmmMpSyncData;\r
-extern UINTN                               mSmmStackArrayBase;\r
-extern UINTN                               mSmmStackArrayEnd;\r
-extern UINTN                               mSmmStackSize;\r
-extern EFI_SMM_CPU_SERVICE_PROTOCOL        mSmmCpuService;\r
-extern IA32_DESCRIPTOR                     gcSmiInitGdtr;\r
-extern SMM_CPU_SEMAPHORES                  mSmmCpuSemaphores;\r
-extern UINTN                               mSemaphoreSize;\r
-extern SPIN_LOCK                           *mPFLock;\r
-extern SPIN_LOCK                           *mConfigSmmCodeAccessCheckLock;\r
-extern EFI_SMRAM_DESCRIPTOR                *mSmmCpuSmramRanges;\r
-extern UINTN                               mSmmCpuSmramRangeCount;\r
-extern UINT8                               mPhysicalAddressBits;\r
+extern IA32_DESCRIPTOR               gcSmiGdtr;\r
+extern EFI_PHYSICAL_ADDRESS          mGdtBuffer;\r
+extern UINTN                         mGdtBufferSize;\r
+extern IA32_DESCRIPTOR               gcSmiIdtr;\r
+extern VOID                          *gcSmiIdtrPtr;\r
+extern UINT64                        gPhyMask;\r
+extern SMM_DISPATCHER_MP_SYNC_DATA   *mSmmMpSyncData;\r
+extern UINTN                         mSmmStackArrayBase;\r
+extern UINTN                         mSmmStackArrayEnd;\r
+extern UINTN                         mSmmStackSize;\r
+extern EFI_SMM_CPU_SERVICE_PROTOCOL  mSmmCpuService;\r
+extern IA32_DESCRIPTOR               gcSmiInitGdtr;\r
+extern SMM_CPU_SEMAPHORES            mSmmCpuSemaphores;\r
+extern UINTN                         mSemaphoreSize;\r
+extern SPIN_LOCK                     *mPFLock;\r
+extern SPIN_LOCK                     *mConfigSmmCodeAccessCheckLock;\r
+extern EFI_SMRAM_DESCRIPTOR          *mSmmCpuSmramRanges;\r
+extern UINTN                         mSmmCpuSmramRangeCount;\r
+extern UINT8                         mPhysicalAddressBits;\r
 \r
 //\r
 // Copy of the PcdPteMemoryEncryptionAddressOrMask\r
@@ -497,10 +497,9 @@ extern UINT64  mAddressEncMask;
 **/\r
 UINT32\r
 Gen4GPageTable (\r
-  IN      BOOLEAN                   Is32BitPageTable\r
+  IN      BOOLEAN  Is32BitPageTable\r
   );\r
 \r
-\r
 /**\r
   Initialize global data for MP synchronization.\r
 \r
@@ -511,9 +510,9 @@ Gen4GPageTable (
 **/\r
 UINT32\r
 InitializeMpServiceData (\r
-  IN VOID        *Stacks,\r
-  IN UINTN       StackSize,\r
-  IN UINTN       ShadowStackSize\r
+  IN VOID   *Stacks,\r
+  IN UINTN  StackSize,\r
+  IN UINTN  ShadowStackSize\r
   );\r
 \r
 /**\r
@@ -544,7 +543,7 @@ StartSyncTimer (
 BOOLEAN\r
 EFIAPI\r
 IsSyncTimerTimeout (\r
-  IN      UINT64                    Timer\r
+  IN      UINT64  Timer\r
   );\r
 \r
 /**\r
@@ -567,8 +566,8 @@ InitializeIDTSmmStackGuard (
 VOID\r
 EFIAPI\r
 InitializeIdtIst (\r
-  IN EFI_EXCEPTION_TYPE            ExceptionType,\r
-  IN UINT8                         Ist\r
+  IN EFI_EXCEPTION_TYPE  ExceptionType,\r
+  IN UINT8               Ist\r
   );\r
 \r
 /**\r
@@ -631,9 +630,9 @@ SmmInitPageTable (
 EFI_STATUS\r
 EFIAPI\r
 SmmStartupThisAp (\r
-  IN      EFI_AP_PROCEDURE          Procedure,\r
-  IN      UINTN                     CpuIndex,\r
-  IN OUT  VOID                      *ProcArguments OPTIONAL\r
+  IN      EFI_AP_PROCEDURE  Procedure,\r
+  IN      UINTN             CpuIndex,\r
+  IN OUT  VOID              *ProcArguments OPTIONAL\r
   );\r
 \r
 /**\r
@@ -653,9 +652,9 @@ SmmStartupThisAp (
 EFI_STATUS\r
 EFIAPI\r
 SmmBlockingStartupThisAp (\r
-  IN      EFI_AP_PROCEDURE          Procedure,\r
-  IN      UINTN                     CpuIndex,\r
-  IN OUT  VOID                      *ProcArguments OPTIONAL\r
+  IN      EFI_AP_PROCEDURE  Procedure,\r
+  IN      UINTN             CpuIndex,\r
+  IN OUT  VOID              *ProcArguments OPTIONAL\r
   );\r
 \r
 /**\r
@@ -683,9 +682,9 @@ SmmBlockingStartupThisAp (
 EFI_STATUS\r
 EFIAPI\r
 SmmSetMemoryAttributes (\r
-  IN  EFI_PHYSICAL_ADDRESS                       BaseAddress,\r
-  IN  UINT64                                     Length,\r
-  IN  UINT64                                     Attributes\r
+  IN  EFI_PHYSICAL_ADDRESS  BaseAddress,\r
+  IN  UINT64                Length,\r
+  IN  UINT64                Attributes\r
   );\r
 \r
 /**\r
@@ -713,9 +712,9 @@ SmmSetMemoryAttributes (
 EFI_STATUS\r
 EFIAPI\r
 SmmClearMemoryAttributes (\r
-  IN  EFI_PHYSICAL_ADDRESS                       BaseAddress,\r
-  IN  UINT64                                     Length,\r
-  IN  UINT64                                     Attributes\r
+  IN  EFI_PHYSICAL_ADDRESS  BaseAddress,\r
+  IN  UINT64                Length,\r
+  IN  UINT64                Attributes\r
   );\r
 \r
 /**\r
@@ -738,8 +737,8 @@ InitializeMpSyncData (
 **/\r
 VOID\r
 FindSmramInfo (\r
-  OUT UINT32   *SmrrBase,\r
-  OUT UINT32   *SmrrSize\r
+  OUT UINT32  *SmrrBase,\r
+  OUT UINT32  *SmrrSize\r
   );\r
 \r
 /**\r
@@ -765,8 +764,8 @@ SmmRelocateBases (
 VOID\r
 EFIAPI\r
 SmiPFHandler (\r
-  IN EFI_EXCEPTION_TYPE   InterruptType,\r
-  IN EFI_SYSTEM_CONTEXT   SystemContext\r
+  IN EFI_EXCEPTION_TYPE  InterruptType,\r
+  IN EFI_SYSTEM_CONTEXT  SystemContext\r
   );\r
 \r
 /**\r
@@ -795,7 +794,7 @@ PerformPreTasks (
 **/\r
 VOID\r
 InitMsrSpinLockByIndex (\r
-  IN UINT32      MsrIndex\r
+  IN UINT32  MsrIndex\r
   );\r
 \r
 /**\r
@@ -908,7 +907,7 @@ InstallSmiHandler (
 **/\r
 VOID\r
 DumpModuleInfoByIp (\r
-  IN  UINTN              CallerIpAddress\r
+  IN  UINTN  CallerIpAddress\r
   );\r
 \r
 /**\r
@@ -964,8 +963,8 @@ SetPageTableAttributes (
 **/\r
 VOID\r
 GetPageTable (\r
-  OUT UINTN   *Base,\r
-  OUT BOOLEAN *FiveLevels OPTIONAL\r
+  OUT UINTN    *Base,\r
+  OUT BOOLEAN  *FiveLevels OPTIONAL\r
   );\r
 \r
 /**\r
@@ -994,10 +993,10 @@ GetPageTable (
 EFI_STATUS\r
 EFIAPI\r
 SmmSetMemoryAttributesEx (\r
-  IN  EFI_PHYSICAL_ADDRESS                       BaseAddress,\r
-  IN  UINT64                                     Length,\r
-  IN  UINT64                                     Attributes,\r
-  OUT BOOLEAN                                    *IsSplitted  OPTIONAL\r
+  IN  EFI_PHYSICAL_ADDRESS  BaseAddress,\r
+  IN  UINT64                Length,\r
+  IN  UINT64                Attributes,\r
+  OUT BOOLEAN               *IsSplitted  OPTIONAL\r
   );\r
 \r
 /**\r
@@ -1026,10 +1025,10 @@ SmmSetMemoryAttributesEx (
 EFI_STATUS\r
 EFIAPI\r
 SmmClearMemoryAttributesEx (\r
-  IN  EFI_PHYSICAL_ADDRESS                       BaseAddress,\r
-  IN  UINT64                                     Length,\r
-  IN  UINT64                                     Attributes,\r
-  OUT BOOLEAN                                    *IsSplitted  OPTIONAL\r
+  IN  EFI_PHYSICAL_ADDRESS  BaseAddress,\r
+  IN  UINT64                Length,\r
+  IN  UINT64                Attributes,\r
+  OUT BOOLEAN               *IsSplitted  OPTIONAL\r
   );\r
 \r
 /**\r
@@ -1049,7 +1048,7 @@ SmmClearMemoryAttributesEx (
 **/\r
 VOID *\r
 AllocatePageTableMemory (\r
-  IN UINTN           Pages\r
+  IN UINTN  Pages\r
   );\r
 \r
 /**\r
@@ -1061,7 +1060,7 @@ AllocatePageTableMemory (
 **/\r
 VOID *\r
 AllocateCodePages (\r
-  IN UINTN           Pages\r
+  IN UINTN  Pages\r
   );\r
 \r
 /**\r
@@ -1076,16 +1075,15 @@ AllocateCodePages (
 **/\r
 VOID *\r
 AllocateAlignedCodePages (\r
-  IN UINTN            Pages,\r
-  IN UINTN            Alignment\r
+  IN UINTN  Pages,\r
+  IN UINTN  Alignment\r
   );\r
 \r
-\r
 //\r
 // S3 related global variable and function prototype.\r
 //\r
 \r
-extern BOOLEAN                mSmmS3Flag;\r
+extern BOOLEAN  mSmmS3Flag;\r
 \r
 /**\r
   Initialize SMM S3 resume state structure used during S3 Resume.\r
@@ -1151,9 +1149,9 @@ TransferApToSafeState (
 **/\r
 EFI_STATUS\r
 SetShadowStack (\r
-  IN  UINTN                                      Cr3,\r
-  IN  EFI_PHYSICAL_ADDRESS                       BaseAddress,\r
-  IN  UINT64                                     Length\r
+  IN  UINTN                 Cr3,\r
+  IN  EFI_PHYSICAL_ADDRESS  BaseAddress,\r
+  IN  UINT64                Length\r
   );\r
 \r
 /**\r
@@ -1167,9 +1165,9 @@ SetShadowStack (
 **/\r
 EFI_STATUS\r
 SetNotPresentPage (\r
-  IN  UINTN                                      Cr3,\r
-  IN  EFI_PHYSICAL_ADDRESS                       BaseAddress,\r
-  IN  UINT64                                     Length\r
+  IN  UINTN                 Cr3,\r
+  IN  EFI_PHYSICAL_ADDRESS  BaseAddress,\r
+  IN  UINT64                Length\r
   );\r
 \r
 /**\r
@@ -1210,10 +1208,10 @@ InitShadowStack (
 EFI_STATUS\r
 EFIAPI\r
 EdkiiSmmSetMemoryAttributes (\r
-  IN  EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL   *This,\r
-  IN  EFI_PHYSICAL_ADDRESS                  BaseAddress,\r
-  IN  UINT64                                Length,\r
-  IN  UINT64                                Attributes\r
+  IN  EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL  *This,\r
+  IN  EFI_PHYSICAL_ADDRESS                 BaseAddress,\r
+  IN  UINT64                               Length,\r
+  IN  UINT64                               Attributes\r
   );\r
 \r
 /**\r
@@ -1242,10 +1240,10 @@ EdkiiSmmSetMemoryAttributes (
 EFI_STATUS\r
 EFIAPI\r
 EdkiiSmmClearMemoryAttributes (\r
-  IN  EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL   *This,\r
-  IN  EFI_PHYSICAL_ADDRESS                  BaseAddress,\r
-  IN  UINT64                                Length,\r
-  IN  UINT64                                Attributes\r
+  IN  EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL  *This,\r
+  IN  EFI_PHYSICAL_ADDRESS                 BaseAddress,\r
+  IN  UINT64                               Length,\r
+  IN  UINT64                               Attributes\r
   );\r
 \r
 /**\r
@@ -1272,10 +1270,10 @@ EdkiiSmmClearMemoryAttributes (
 EFI_STATUS\r
 EFIAPI\r
 EdkiiSmmGetMemoryAttributes (\r
-  IN  EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL   *This,\r
-  IN  EFI_PHYSICAL_ADDRESS                  BaseAddress,\r
-  IN  UINT64                                Length,\r
-  IN  UINT64                                *Attributes\r
+  IN  EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL  *This,\r
+  IN  EFI_PHYSICAL_ADDRESS                 BaseAddress,\r
+  IN  UINT64                               Length,\r
+  IN  UINT64                               *Attributes\r
   );\r
 \r
 /**\r
@@ -1285,7 +1283,7 @@ EdkiiSmmGetMemoryAttributes (
 VOID\r
 EFIAPI\r
 PiSmmCpuSmmInitFixupAddress (\r
- );\r
+  );\r
 \r
 /**\r
   This function fixes up the address of the global variable or function\r
@@ -1294,7 +1292,7 @@ PiSmmCpuSmmInitFixupAddress (
 VOID\r
 EFIAPI\r
 PiSmmCpuSmiEntryFixupAddress (\r
- );\r
+  );\r
 \r
 /**\r
   This function reads CR2 register when on-demand paging is enabled\r
@@ -1355,12 +1353,12 @@ RestoreCr2 (
 **/\r
 EFI_STATUS\r
 InternalSmmStartupThisAp (\r
-  IN      EFI_AP_PROCEDURE2              Procedure,\r
-  IN      UINTN                          CpuIndex,\r
-  IN OUT  VOID                           *ProcArguments OPTIONAL,\r
-  IN OUT  MM_COMPLETION                  *Token,\r
-  IN      UINTN                          TimeoutInMicroseconds,\r
-  IN OUT  EFI_STATUS                     *CpuStatus\r
+  IN      EFI_AP_PROCEDURE2  Procedure,\r
+  IN      UINTN              CpuIndex,\r
+  IN OUT  VOID               *ProcArguments OPTIONAL,\r
+  IN OUT  MM_COMPLETION      *Token,\r
+  IN      UINTN              TimeoutInMicroseconds,\r
+  IN OUT  EFI_STATUS         *CpuStatus\r
   );\r
 \r
 /**\r
@@ -1374,7 +1372,7 @@ InternalSmmStartupThisAp (
 **/\r
 BOOLEAN\r
 IsTokenInUse (\r
-  IN SPIN_LOCK           *Token\r
+  IN SPIN_LOCK  *Token\r
   );\r
 \r
 /**\r
@@ -1405,7 +1403,7 @@ IsApReady (
 **/\r
 BOOLEAN\r
 IsPresentAp (\r
-  IN UINTN        CpuIndex\r
+  IN UINTN  CpuIndex\r
   );\r
 \r
 /**\r
@@ -1439,11 +1437,11 @@ IsPresentAp (
 **/\r
 EFI_STATUS\r
 InternalSmmStartupAllAPs (\r
-  IN       EFI_AP_PROCEDURE2             Procedure,\r
-  IN       UINTN                         TimeoutInMicroseconds,\r
-  IN OUT   VOID                          *ProcedureArguments OPTIONAL,\r
-  IN OUT   MM_COMPLETION                 *Token,\r
-  IN OUT   EFI_STATUS                    *CPUStatus\r
+  IN       EFI_AP_PROCEDURE2  Procedure,\r
+  IN       UINTN              TimeoutInMicroseconds,\r
+  IN OUT   VOID               *ProcedureArguments OPTIONAL,\r
+  IN OUT   MM_COMPLETION      *Token,\r
+  IN OUT   EFI_STATUS         *CPUStatus\r
   );\r
 \r
 /**\r
@@ -1466,8 +1464,8 @@ InternalSmmStartupAllAPs (
 **/\r
 EFI_STATUS\r
 RegisterStartupProcedure (\r
-  IN     EFI_AP_PROCEDURE    Procedure,\r
-  IN OUT VOID                *ProcedureArguments OPTIONAL\r
+  IN     EFI_AP_PROCEDURE  Procedure,\r
+  IN OUT VOID              *ProcedureArguments OPTIONAL\r
   );\r
 \r
 /**\r

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c
index 12dde85cf1d96d72ef4e139c6917be9a0ee2224c..1f7cc15727cd1e93ec2a3c547cc77392ef175c10 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c
@@ -17,19 +17,19 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
 #define PREVIOUS_MEMORY_DESCRIPTOR(MemoryDescriptor, Size) \\r
   ((EFI_MEMORY_DESCRIPTOR *)((UINT8 *)(MemoryDescriptor) - (Size)))\r
 \r
-EFI_MEMORY_DESCRIPTOR *mUefiMemoryMap;\r
-UINTN                 mUefiMemoryMapSize;\r
-UINTN                 mUefiDescriptorSize;\r
+EFI_MEMORY_DESCRIPTOR  *mUefiMemoryMap;\r
+UINTN                  mUefiMemoryMapSize;\r
+UINTN                  mUefiDescriptorSize;\r
 \r
-EFI_GCD_MEMORY_SPACE_DESCRIPTOR   *mGcdMemSpace       = NULL;\r
-UINTN                             mGcdMemNumberOfDesc = 0;\r
+EFI_GCD_MEMORY_SPACE_DESCRIPTOR  *mGcdMemSpace       = NULL;\r
+UINTN                            mGcdMemNumberOfDesc = 0;\r
 \r
 EFI_MEMORY_ATTRIBUTES_TABLE  *mUefiMemoryAttributesTable = NULL;\r
 \r
-PAGE_ATTRIBUTE_TABLE mPageAttributeTable[] = {\r
-  {Page4K,  SIZE_4KB, PAGING_4K_ADDRESS_MASK_64},\r
-  {Page2M,  SIZE_2MB, PAGING_2M_ADDRESS_MASK_64},\r
-  {Page1G,  SIZE_1GB, PAGING_1G_ADDRESS_MASK_64},\r
+PAGE_ATTRIBUTE_TABLE  mPageAttributeTable[] = {\r
+  { Page4K, SIZE_4KB, PAGING_4K_ADDRESS_MASK_64 },\r
+  { Page2M, SIZE_2MB, PAGING_2M_ADDRESS_MASK_64 },\r
+  { Page1G, SIZE_1GB, PAGING_1G_ADDRESS_MASK_64 },\r
 };\r
 \r
 UINTN  mInternalCr3;\r
@@ -43,7 +43,7 @@ UINTN  mInternalCr3;
 **/\r
 VOID\r
 SetPageTableBase (\r
-  IN UINTN   Cr3\r
+  IN UINTN  Cr3\r
   )\r
 {\r
   mInternalCr3 = Cr3;\r
@@ -62,11 +62,13 @@ PageAttributeToLength (
   )\r
 {\r
   UINTN  Index;\r
-  for (Index = 0; Index < sizeof(mPageAttributeTable)/sizeof(mPageAttributeTable[0]); Index++) {\r
+\r
+  for (Index = 0; Index < sizeof (mPageAttributeTable)/sizeof (mPageAttributeTable[0]); Index++) {\r
     if (PageAttribute == mPageAttributeTable[Index].Attribute) {\r
       return (UINTN)mPageAttributeTable[Index].Length;\r
     }\r
   }\r
+\r
   return 0;\r
 }\r
 \r
@@ -83,11 +85,13 @@ PageAttributeToMask (
   )\r
 {\r
   UINTN  Index;\r
-  for (Index = 0; Index < sizeof(mPageAttributeTable)/sizeof(mPageAttributeTable[0]); Index++) {\r
+\r
+  for (Index = 0; Index < sizeof (mPageAttributeTable)/sizeof (mPageAttributeTable[0]); Index++) {\r
     if (PageAttribute == mPageAttributeTable[Index].Attribute) {\r
       return (UINTN)mPageAttributeTable[Index].AddressMask;\r
     }\r
   }\r
+\r
   return 0;\r
 }\r
 \r
@@ -101,22 +105,22 @@ PageAttributeToMask (
 **/\r
 VOID *\r
 GetPageTableEntry (\r
-  IN  PHYSICAL_ADDRESS                  Address,\r
-  OUT PAGE_ATTRIBUTE                    *PageAttribute\r
+  IN  PHYSICAL_ADDRESS  Address,\r
+  OUT PAGE_ATTRIBUTE    *PageAttribute\r
   )\r
 {\r
-  UINTN                 Index1;\r
-  UINTN                 Index2;\r
-  UINTN                 Index3;\r
-  UINTN                 Index4;\r
-  UINTN                 Index5;\r
-  UINT64                *L1PageTable;\r
-  UINT64                *L2PageTable;\r
-  UINT64                *L3PageTable;\r
-  UINT64                *L4PageTable;\r
-  UINT64                *L5PageTable;\r
-  UINTN                 PageTableBase;\r
-  BOOLEAN               Enable5LevelPaging;\r
+  UINTN    Index1;\r
+  UINTN    Index2;\r
+  UINTN    Index3;\r
+  UINTN    Index4;\r
+  UINTN    Index5;\r
+  UINT64   *L1PageTable;\r
+  UINT64   *L2PageTable;\r
+  UINT64   *L3PageTable;\r
+  UINT64   *L4PageTable;\r
+  UINT64   *L5PageTable;\r
+  UINTN    PageTableBase;\r
+  BOOLEAN  Enable5LevelPaging;\r
 \r
   GetPageTable (&PageTableBase, &Enable5LevelPaging);\r
 \r
@@ -126,7 +130,7 @@ GetPageTableEntry (
   Index2 = ((UINTN)Address >> 21) & PAGING_PAE_INDEX_MASK;\r
   Index1 = ((UINTN)Address >> 12) & PAGING_PAE_INDEX_MASK;\r
 \r
-  if (sizeof(UINTN) == sizeof(UINT64)) {\r
+  if (sizeof (UINTN) == sizeof (UINT64)) {\r
     if (Enable5LevelPaging) {\r
       L5PageTable = (UINT64 *)PageTableBase;\r
       if (L5PageTable[Index5] == 0) {\r
@@ -138,6 +142,7 @@ GetPageTableEntry (
     } else {\r
       L4PageTable = (UINT64 *)PageTableBase;\r
     }\r
+\r
     if (L4PageTable[Index4] == 0) {\r
       *PageAttribute = PageNone;\r
       return NULL;\r
@@ -147,10 +152,12 @@ GetPageTableEntry (
   } else {\r
     L3PageTable = (UINT64 *)PageTableBase;\r
   }\r
+\r
   if (L3PageTable[Index3] == 0) {\r
     *PageAttribute = PageNone;\r
     return NULL;\r
   }\r
+\r
   if ((L3PageTable[Index3] & IA32_PG_PS) != 0) {\r
     // 1G\r
     *PageAttribute = Page1G;\r
@@ -162,6 +169,7 @@ GetPageTableEntry (
     *PageAttribute = PageNone;\r
     return NULL;\r
   }\r
+\r
   if ((L2PageTable[Index2] & IA32_PG_PS) != 0) {\r
     // 2M\r
     *PageAttribute = Page2M;\r
@@ -174,6 +182,7 @@ GetPageTableEntry (
     *PageAttribute = PageNone;\r
     return NULL;\r
   }\r
+\r
   *PageAttribute = Page4K;\r
   return &L1PageTable[Index1];\r
 }\r
@@ -187,20 +196,24 @@ GetPageTableEntry (
 **/\r
 UINT64\r
 GetAttributesFromPageEntry (\r
-  IN  UINT64                            *PageEntry\r
+  IN  UINT64  *PageEntry\r
   )\r
 {\r
   UINT64  Attributes;\r
+\r
   Attributes = 0;\r
   if ((*PageEntry & IA32_PG_P) == 0) {\r
     Attributes |= EFI_MEMORY_RP;\r
   }\r
+\r
   if ((*PageEntry & IA32_PG_RW) == 0) {\r
     Attributes |= EFI_MEMORY_RO;\r
   }\r
+\r
   if ((*PageEntry & IA32_PG_NX) != 0) {\r
     Attributes |= EFI_MEMORY_XP;\r
   }\r
+\r
   return Attributes;\r
 }\r
 \r
@@ -214,17 +227,17 @@ GetAttributesFromPageEntry (
 **/\r
 VOID\r
 ConvertPageEntryAttribute (\r
-  IN  UINT64                            *PageEntry,\r
-  IN  UINT64                            Attributes,\r
-  IN  BOOLEAN                           IsSet,\r
-  OUT BOOLEAN                           *IsModified\r
+  IN  UINT64   *PageEntry,\r
+  IN  UINT64   Attributes,\r
+  IN  BOOLEAN  IsSet,\r
+  OUT BOOLEAN  *IsModified\r
   )\r
 {\r
   UINT64  CurrentPageEntry;\r
   UINT64  NewPageEntry;\r
 \r
   CurrentPageEntry = *PageEntry;\r
-  NewPageEntry = CurrentPageEntry;\r
+  NewPageEntry     = CurrentPageEntry;\r
   if ((Attributes & EFI_MEMORY_RP) != 0) {\r
     if (IsSet) {\r
       NewPageEntry &= ~(UINT64)IA32_PG_P;\r
@@ -232,6 +245,7 @@ ConvertPageEntryAttribute (
       NewPageEntry |= IA32_PG_P;\r
     }\r
   }\r
+\r
   if ((Attributes & EFI_MEMORY_RO) != 0) {\r
     if (IsSet) {\r
       NewPageEntry &= ~(UINT64)IA32_PG_RW;\r
@@ -250,6 +264,7 @@ ConvertPageEntryAttribute (
       NewPageEntry |= IA32_PG_RW;\r
     }\r
   }\r
+\r
   if ((Attributes & EFI_MEMORY_XP) != 0) {\r
     if (mXdSupported) {\r
       if (IsSet) {\r
@@ -259,6 +274,7 @@ ConvertPageEntryAttribute (
       }\r
     }\r
   }\r
+\r
   *PageEntry = NewPageEntry;\r
   if (CurrentPageEntry != NewPageEntry) {\r
     *IsModified = TRUE;\r
@@ -281,13 +297,13 @@ ConvertPageEntryAttribute (
 **/\r
 PAGE_ATTRIBUTE\r
 NeedSplitPage (\r
-  IN  PHYSICAL_ADDRESS                  BaseAddress,\r
-  IN  UINT64                            Length,\r
-  IN  UINT64                            *PageEntry,\r
-  IN  PAGE_ATTRIBUTE                    PageAttribute\r
+  IN  PHYSICAL_ADDRESS  BaseAddress,\r
+  IN  UINT64            Length,\r
+  IN  UINT64            *PageEntry,\r
+  IN  PAGE_ATTRIBUTE    PageAttribute\r
   )\r
 {\r
-  UINT64                PageEntryLength;\r
+  UINT64  PageEntryLength;\r
 \r
   PageEntryLength = PageAttributeToLength (PageAttribute);\r
 \r
@@ -315,14 +331,14 @@ NeedSplitPage (
 **/\r
 RETURN_STATUS\r
 SplitPage (\r
-  IN  UINT64                            *PageEntry,\r
-  IN  PAGE_ATTRIBUTE                    PageAttribute,\r
-  IN  PAGE_ATTRIBUTE                    SplitAttribute\r
+  IN  UINT64          *PageEntry,\r
+  IN  PAGE_ATTRIBUTE  PageAttribute,\r
+  IN  PAGE_ATTRIBUTE  SplitAttribute\r
   )\r
 {\r
-  UINT64   BaseAddress;\r
-  UINT64   *NewPageEntry;\r
-  UINTN    Index;\r
+  UINT64  BaseAddress;\r
+  UINT64  *NewPageEntry;\r
+  UINTN   Index;\r
 \r
   ASSERT (PageAttribute == Page2M || PageAttribute == Page1G);\r
 \r
@@ -337,10 +353,12 @@ SplitPage (
       if (NewPageEntry == NULL) {\r
         return RETURN_OUT_OF_RESOURCES;\r
       }\r
+\r
       BaseAddress = *PageEntry & PAGING_2M_ADDRESS_MASK_64;\r
-      for (Index = 0; Index < SIZE_4KB / sizeof(UINT64); Index++) {\r
+      for (Index = 0; Index < SIZE_4KB / sizeof (UINT64); Index++) {\r
         NewPageEntry[Index] = (BaseAddress + SIZE_4KB * Index) | mAddressEncMask | ((*PageEntry) & PAGE_PROGATE_BITS);\r
       }\r
+\r
       (*PageEntry) = (UINT64)(UINTN)NewPageEntry | mAddressEncMask | PAGE_ATTRIBUTE_BITS;\r
       return RETURN_SUCCESS;\r
     } else {\r
@@ -352,16 +370,18 @@ SplitPage (
     // No need support 1G->4K directly, we should use 1G->2M, then 2M->4K to get more compact page table.\r
     //\r
     ASSERT (SplitAttribute == Page2M || SplitAttribute == Page4K);\r
-    if ((SplitAttribute == Page2M || SplitAttribute == Page4K)) {\r
+    if (((SplitAttribute == Page2M) || (SplitAttribute == Page4K))) {\r
       NewPageEntry = AllocatePageTableMemory (1);\r
       DEBUG ((DEBUG_VERBOSE, "Split - 0x%x\n", NewPageEntry));\r
       if (NewPageEntry == NULL) {\r
         return RETURN_OUT_OF_RESOURCES;\r
       }\r
+\r
       BaseAddress = *PageEntry & PAGING_1G_ADDRESS_MASK_64;\r
-      for (Index = 0; Index < SIZE_4KB / sizeof(UINT64); Index++) {\r
+      for (Index = 0; Index < SIZE_4KB / sizeof (UINT64); Index++) {\r
         NewPageEntry[Index] = (BaseAddress + SIZE_2MB * Index) | mAddressEncMask | IA32_PG_PS | ((*PageEntry) & PAGE_PROGATE_BITS);\r
       }\r
+\r
       (*PageEntry) = (UINT64)(UINTN)NewPageEntry | mAddressEncMask | PAGE_ATTRIBUTE_BITS;\r
       return RETURN_SUCCESS;\r
     } else {\r
@@ -401,21 +421,21 @@ SplitPage (
 RETURN_STATUS\r
 EFIAPI\r
 ConvertMemoryPageAttributes (\r
-  IN  PHYSICAL_ADDRESS                  BaseAddress,\r
-  IN  UINT64                            Length,\r
-  IN  UINT64                            Attributes,\r
-  IN  BOOLEAN                           IsSet,\r
-  OUT BOOLEAN                           *IsSplitted   OPTIONAL,\r
-  OUT BOOLEAN                           *IsModified   OPTIONAL\r
+  IN  PHYSICAL_ADDRESS  BaseAddress,\r
+  IN  UINT64            Length,\r
+  IN  UINT64            Attributes,\r
+  IN  BOOLEAN           IsSet,\r
+  OUT BOOLEAN           *IsSplitted   OPTIONAL,\r
+  OUT BOOLEAN           *IsModified   OPTIONAL\r
   )\r
 {\r
-  UINT64                            *PageEntry;\r
-  PAGE_ATTRIBUTE                    PageAttribute;\r
-  UINTN                             PageEntryLength;\r
-  PAGE_ATTRIBUTE                    SplitAttribute;\r
-  RETURN_STATUS                     Status;\r
-  BOOLEAN                           IsEntryModified;\r
-  EFI_PHYSICAL_ADDRESS              MaximumSupportMemAddress;\r
+  UINT64                *PageEntry;\r
+  PAGE_ATTRIBUTE        PageAttribute;\r
+  UINTN                 PageEntryLength;\r
+  PAGE_ATTRIBUTE        SplitAttribute;\r
+  RETURN_STATUS         Status;\r
+  BOOLEAN               IsEntryModified;\r
+  EFI_PHYSICAL_ADDRESS  MaximumSupportMemAddress;\r
 \r
   ASSERT (Attributes != 0);\r
   ASSERT ((Attributes & ~EFI_MEMORY_ATTRIBUTE_MASK) == 0);\r
@@ -431,18 +451,21 @@ ConvertMemoryPageAttributes (
   if (BaseAddress > MaximumSupportMemAddress) {\r
     return RETURN_UNSUPPORTED;\r
   }\r
+\r
   if (Length > MaximumSupportMemAddress) {\r
     return RETURN_UNSUPPORTED;\r
   }\r
+\r
   if ((Length != 0) && (BaseAddress > MaximumSupportMemAddress - (Length - 1))) {\r
     return RETURN_UNSUPPORTED;\r
   }\r
 \r
-//  DEBUG ((DEBUG_ERROR, "ConvertMemoryPageAttributes(%x) - %016lx, %016lx, %02lx\n", IsSet, BaseAddress, Length, Attributes));\r
+  //  DEBUG ((DEBUG_ERROR, "ConvertMemoryPageAttributes(%x) - %016lx, %016lx, %02lx\n", IsSet, BaseAddress, Length, Attributes));\r
 \r
   if (IsSplitted != NULL) {\r
     *IsSplitted = FALSE;\r
   }\r
+\r
   if (IsModified != NULL) {\r
     *IsModified = FALSE;\r
   }\r
@@ -455,8 +478,9 @@ ConvertMemoryPageAttributes (
     if (PageEntry == NULL) {\r
       return RETURN_UNSUPPORTED;\r
     }\r
+\r
     PageEntryLength = PageAttributeToLength (PageAttribute);\r
-    SplitAttribute = NeedSplitPage (BaseAddress, Length, PageEntry, PageAttribute);\r
+    SplitAttribute  = NeedSplitPage (BaseAddress, Length, PageEntry, PageAttribute);\r
     if (SplitAttribute == PageNone) {\r
       ConvertPageEntryAttribute (PageEntry, Attributes, IsSet, &IsEntryModified);\r
       if (IsEntryModified) {\r
@@ -464,22 +488,26 @@ ConvertMemoryPageAttributes (
           *IsModified = TRUE;\r
         }\r
       }\r
+\r
       //\r
       // Convert success, move to next\r
       //\r
       BaseAddress += PageEntryLength;\r
-      Length -= PageEntryLength;\r
+      Length      -= PageEntryLength;\r
     } else {\r
       Status = SplitPage (PageEntry, PageAttribute, SplitAttribute);\r
       if (RETURN_ERROR (Status)) {\r
         return RETURN_UNSUPPORTED;\r
       }\r
+\r
       if (IsSplitted != NULL) {\r
         *IsSplitted = TRUE;\r
       }\r
+\r
       if (IsModified != NULL) {\r
         *IsModified = TRUE;\r
       }\r
+\r
       //\r
       // Just split current page\r
       // Convert success in next around\r
@@ -512,7 +540,7 @@ FlushTlbForAll (
   VOID\r
   )\r
 {\r
-  UINTN       Index;\r
+  UINTN  Index;\r
 \r
   FlushTlbOnCurrentProcessor (NULL);\r
 \r
@@ -551,22 +579,22 @@ FlushTlbForAll (
 EFI_STATUS\r
 EFIAPI\r
 SmmSetMemoryAttributesEx (\r
-  IN  EFI_PHYSICAL_ADDRESS                       BaseAddress,\r
-  IN  UINT64                                     Length,\r
-  IN  UINT64                                     Attributes,\r
-  OUT BOOLEAN                                    *IsSplitted  OPTIONAL\r
+  IN  EFI_PHYSICAL_ADDRESS  BaseAddress,\r
+  IN  UINT64                Length,\r
+  IN  UINT64                Attributes,\r
+  OUT BOOLEAN               *IsSplitted  OPTIONAL\r
   )\r
 {\r
   EFI_STATUS  Status;\r
   BOOLEAN     IsModified;\r
 \r
   Status = ConvertMemoryPageAttributes (BaseAddress, Length, Attributes, TRUE, IsSplitted, &IsModified);\r
-  if (!EFI_ERROR(Status)) {\r
+  if (!EFI_ERROR (Status)) {\r
     if (IsModified) {\r
       //\r
       // Flush TLB as last step\r
       //\r
-      FlushTlbForAll();\r
+      FlushTlbForAll ();\r
     }\r
   }\r
 \r
@@ -599,22 +627,22 @@ SmmSetMemoryAttributesEx (
 EFI_STATUS\r
 EFIAPI\r
 SmmClearMemoryAttributesEx (\r
-  IN  EFI_PHYSICAL_ADDRESS                       BaseAddress,\r
-  IN  UINT64                                     Length,\r
-  IN  UINT64                                     Attributes,\r
-  OUT BOOLEAN                                    *IsSplitted  OPTIONAL\r
+  IN  EFI_PHYSICAL_ADDRESS  BaseAddress,\r
+  IN  UINT64                Length,\r
+  IN  UINT64                Attributes,\r
+  OUT BOOLEAN               *IsSplitted  OPTIONAL\r
   )\r
 {\r
   EFI_STATUS  Status;\r
   BOOLEAN     IsModified;\r
 \r
   Status = ConvertMemoryPageAttributes (BaseAddress, Length, Attributes, FALSE, IsSplitted, &IsModified);\r
-  if (!EFI_ERROR(Status)) {\r
+  if (!EFI_ERROR (Status)) {\r
     if (IsModified) {\r
       //\r
       // Flush TLB as last step\r
       //\r
-      FlushTlbForAll();\r
+      FlushTlbForAll ();\r
     }\r
   }\r
 \r
@@ -646,9 +674,9 @@ SmmClearMemoryAttributesEx (
 EFI_STATUS\r
 EFIAPI\r
 SmmSetMemoryAttributes (\r
-  IN  EFI_PHYSICAL_ADDRESS                       BaseAddress,\r
-  IN  UINT64                                     Length,\r
-  IN  UINT64                                     Attributes\r
+  IN  EFI_PHYSICAL_ADDRESS  BaseAddress,\r
+  IN  UINT64                Length,\r
+  IN  UINT64                Attributes\r
   )\r
 {\r
   return SmmSetMemoryAttributesEx (BaseAddress, Length, Attributes, NULL);\r
@@ -679,9 +707,9 @@ SmmSetMemoryAttributes (
 EFI_STATUS\r
 EFIAPI\r
 SmmClearMemoryAttributes (\r
-  IN  EFI_PHYSICAL_ADDRESS                       BaseAddress,\r
-  IN  UINT64                                     Length,\r
-  IN  UINT64                                     Attributes\r
+  IN  EFI_PHYSICAL_ADDRESS  BaseAddress,\r
+  IN  UINT64                Length,\r
+  IN  UINT64                Attributes\r
   )\r
 {\r
   return SmmClearMemoryAttributesEx (BaseAddress, Length, Attributes, NULL);\r
@@ -698,9 +726,9 @@ SmmClearMemoryAttributes (
 **/\r
 EFI_STATUS\r
 SetShadowStack (\r
-  IN  UINTN                                      Cr3,\r
-  IN  EFI_PHYSICAL_ADDRESS                       BaseAddress,\r
-  IN  UINT64                                     Length\r
+  IN  UINTN                 Cr3,\r
+  IN  EFI_PHYSICAL_ADDRESS  BaseAddress,\r
+  IN  UINT64                Length\r
   )\r
 {\r
   EFI_STATUS  Status;\r
@@ -725,9 +753,9 @@ SetShadowStack (
 **/\r
 EFI_STATUS\r
 SetNotPresentPage (\r
-  IN  UINTN                                      Cr3,\r
-  IN  EFI_PHYSICAL_ADDRESS                       BaseAddress,\r
-  IN  UINT64                                     Length\r
+  IN  UINTN                 Cr3,\r
+  IN  EFI_PHYSICAL_ADDRESS  BaseAddress,\r
+  IN  UINT64                Length\r
   )\r
 {\r
   EFI_STATUS  Status;\r
@@ -759,7 +787,7 @@ SmmGetSystemConfigurationTable (
   OUT VOID      **Table\r
   )\r
 {\r
-  UINTN             Index;\r
+  UINTN  Index;\r
 \r
   ASSERT (TableGuid != NULL);\r
   ASSERT (Table != NULL);\r
@@ -789,11 +817,11 @@ PatchSmmSaveStateMap (
   UINTN  TileSize;\r
 \r
   TileCodeSize = GetSmiHandlerSize ();\r
-  TileCodeSize = ALIGN_VALUE(TileCodeSize, SIZE_4KB);\r
+  TileCodeSize = ALIGN_VALUE (TileCodeSize, SIZE_4KB);\r
   TileDataSize = (SMRAM_SAVE_STATE_MAP_OFFSET - SMM_PSD_OFFSET) + sizeof (SMRAM_SAVE_STATE_MAP);\r
-  TileDataSize = ALIGN_VALUE(TileDataSize, SIZE_4KB);\r
-  TileSize = TileDataSize + TileCodeSize - 1;\r
-  TileSize = 2 * GetPowerOfTwo32 ((UINT32)TileSize);\r
+  TileDataSize = ALIGN_VALUE (TileDataSize, SIZE_4KB);\r
+  TileSize     = TileDataSize + TileCodeSize - 1;\r
+  TileSize     = 2 * GetPowerOfTwo32 ((UINT32)TileSize);\r
 \r
   DEBUG ((DEBUG_INFO, "PatchSmmSaveStateMap:\n"));\r
   for (Index = 0; Index < mMaxNumberOfCpus - 1; Index++) {\r
@@ -863,8 +891,8 @@ PatchGdtIdtMap (
   VOID\r
   )\r
 {\r
-  EFI_PHYSICAL_ADDRESS       BaseAddress;\r
-  UINTN                      Size;\r
+  EFI_PHYSICAL_ADDRESS  BaseAddress;\r
+  UINTN                 Size;\r
 \r
   //\r
   // GDT\r
@@ -872,7 +900,7 @@ PatchGdtIdtMap (
   DEBUG ((DEBUG_INFO, "PatchGdtIdtMap - GDT:\n"));\r
 \r
   BaseAddress = mGdtBuffer;\r
-  Size = ALIGN_VALUE(mGdtBufferSize, SIZE_4KB);\r
+  Size        = ALIGN_VALUE (mGdtBufferSize, SIZE_4KB);\r
   //\r
   // The range should have been set to RO\r
   // if it is allocated with EfiRuntimeServicesCode.\r
@@ -889,7 +917,7 @@ PatchGdtIdtMap (
   DEBUG ((DEBUG_INFO, "PatchGdtIdtMap - IDT:\n"));\r
 \r
   BaseAddress = gcSmiIdtr.Base;\r
-  Size = ALIGN_VALUE(gcSmiIdtr.Limit + 1, SIZE_4KB);\r
+  Size        = ALIGN_VALUE (gcSmiIdtr.Limit + 1, SIZE_4KB);\r
   //\r
   // The range should have been set to RO\r
   // if it is allocated with EfiRuntimeServicesCode.\r
@@ -909,17 +937,17 @@ SetMemMapAttributes (
   VOID\r
   )\r
 {\r
-  EFI_MEMORY_DESCRIPTOR                     *MemoryMap;\r
-  EFI_MEMORY_DESCRIPTOR                     *MemoryMapStart;\r
-  UINTN                                     MemoryMapEntryCount;\r
-  UINTN                                     DescriptorSize;\r
-  UINTN                                     Index;\r
-  EDKII_PI_SMM_MEMORY_ATTRIBUTES_TABLE      *MemoryAttributesTable;\r
+  EFI_MEMORY_DESCRIPTOR                 *MemoryMap;\r
+  EFI_MEMORY_DESCRIPTOR                 *MemoryMapStart;\r
+  UINTN                                 MemoryMapEntryCount;\r
+  UINTN                                 DescriptorSize;\r
+  UINTN                                 Index;\r
+  EDKII_PI_SMM_MEMORY_ATTRIBUTES_TABLE  *MemoryAttributesTable;\r
 \r
   SmmGetSystemConfigurationTable (&gEdkiiPiSmmMemoryAttributesTableGuid, (VOID **)&MemoryAttributesTable);\r
   if (MemoryAttributesTable == NULL) {\r
     DEBUG ((DEBUG_INFO, "MemoryAttributesTable - NULL\n"));\r
-    return ;\r
+    return;\r
   }\r
 \r
   DEBUG ((DEBUG_INFO, "MemoryAttributesTable:\n"));\r
@@ -928,9 +956,9 @@ SetMemMapAttributes (
   DEBUG ((DEBUG_INFO, "  DescriptorSize            - 0x%08x\n", MemoryAttributesTable->DescriptorSize));\r
 \r
   MemoryMapEntryCount = MemoryAttributesTable->NumberOfEntries;\r
-  DescriptorSize = MemoryAttributesTable->DescriptorSize;\r
-  MemoryMapStart = (EFI_MEMORY_DESCRIPTOR *)(MemoryAttributesTable + 1);\r
-  MemoryMap = MemoryMapStart;\r
+  DescriptorSize      = MemoryAttributesTable->DescriptorSize;\r
+  MemoryMapStart      = (EFI_MEMORY_DESCRIPTOR *)(MemoryAttributesTable + 1);\r
+  MemoryMap           = MemoryMapStart;\r
   for (Index = 0; Index < MemoryMapEntryCount; Index++) {\r
     DEBUG ((DEBUG_INFO, "Entry (0x%x)\n", MemoryMap));\r
     DEBUG ((DEBUG_INFO, "  Type              - 0x%x\n", MemoryMap->Type));\r
@@ -938,42 +966,43 @@ SetMemMapAttributes (
     DEBUG ((DEBUG_INFO, "  VirtualStart      - 0x%016lx\n", MemoryMap->VirtualStart));\r
     DEBUG ((DEBUG_INFO, "  NumberOfPages     - 0x%016lx\n", MemoryMap->NumberOfPages));\r
     DEBUG ((DEBUG_INFO, "  Attribute         - 0x%016lx\n", MemoryMap->Attribute));\r
-    MemoryMap = NEXT_MEMORY_DESCRIPTOR(MemoryMap, DescriptorSize);\r
+    MemoryMap = NEXT_MEMORY_DESCRIPTOR (MemoryMap, DescriptorSize);\r
   }\r
 \r
   MemoryMap = MemoryMapStart;\r
   for (Index = 0; Index < MemoryMapEntryCount; Index++) {\r
     DEBUG ((DEBUG_VERBOSE, "SetAttribute: Memory Entry - 0x%lx, 0x%x\n", MemoryMap->PhysicalStart, MemoryMap->NumberOfPages));\r
     switch (MemoryMap->Type) {\r
-    case EfiRuntimeServicesCode:\r
-      SmmSetMemoryAttributes (\r
-        MemoryMap->PhysicalStart,\r
-        EFI_PAGES_TO_SIZE((UINTN)MemoryMap->NumberOfPages),\r
-        EFI_MEMORY_RO\r
-        );\r
-      break;\r
-    case EfiRuntimeServicesData:\r
-      SmmSetMemoryAttributes (\r
-        MemoryMap->PhysicalStart,\r
-        EFI_PAGES_TO_SIZE((UINTN)MemoryMap->NumberOfPages),\r
-        EFI_MEMORY_XP\r
-        );\r
-      break;\r
-    default:\r
-      SmmSetMemoryAttributes (\r
-        MemoryMap->PhysicalStart,\r
-        EFI_PAGES_TO_SIZE((UINTN)MemoryMap->NumberOfPages),\r
-        EFI_MEMORY_XP\r
-        );\r
-      break;\r
+      case EfiRuntimeServicesCode:\r
+        SmmSetMemoryAttributes (\r
+          MemoryMap->PhysicalStart,\r
+          EFI_PAGES_TO_SIZE ((UINTN)MemoryMap->NumberOfPages),\r
+          EFI_MEMORY_RO\r
+          );\r
+        break;\r
+      case EfiRuntimeServicesData:\r
+        SmmSetMemoryAttributes (\r
+          MemoryMap->PhysicalStart,\r
+          EFI_PAGES_TO_SIZE ((UINTN)MemoryMap->NumberOfPages),\r
+          EFI_MEMORY_XP\r
+          );\r
+        break;\r
+      default:\r
+        SmmSetMemoryAttributes (\r
+          MemoryMap->PhysicalStart,\r
+          EFI_PAGES_TO_SIZE ((UINTN)MemoryMap->NumberOfPages),\r
+          EFI_MEMORY_XP\r
+          );\r
+        break;\r
     }\r
-    MemoryMap = NEXT_MEMORY_DESCRIPTOR(MemoryMap, DescriptorSize);\r
+\r
+    MemoryMap = NEXT_MEMORY_DESCRIPTOR (MemoryMap, DescriptorSize);\r
   }\r
 \r
   PatchSmmSaveStateMap ();\r
   PatchGdtIdtMap ();\r
 \r
-  return ;\r
+  return;\r
 }\r
 \r
 /**\r
@@ -992,27 +1021,27 @@ SortMemoryMap (
   IN UINTN                      DescriptorSize\r
   )\r
 {\r
-  EFI_MEMORY_DESCRIPTOR       *MemoryMapEntry;\r
-  EFI_MEMORY_DESCRIPTOR       *NextMemoryMapEntry;\r
-  EFI_MEMORY_DESCRIPTOR       *MemoryMapEnd;\r
-  EFI_MEMORY_DESCRIPTOR       TempMemoryMap;\r
+  EFI_MEMORY_DESCRIPTOR  *MemoryMapEntry;\r
+  EFI_MEMORY_DESCRIPTOR  *NextMemoryMapEntry;\r
+  EFI_MEMORY_DESCRIPTOR  *MemoryMapEnd;\r
+  EFI_MEMORY_DESCRIPTOR  TempMemoryMap;\r
 \r
-  MemoryMapEntry = MemoryMap;\r
+  MemoryMapEntry     = MemoryMap;\r
   NextMemoryMapEntry = NEXT_MEMORY_DESCRIPTOR (MemoryMapEntry, DescriptorSize);\r
-  MemoryMapEnd = (EFI_MEMORY_DESCRIPTOR *) ((UINT8 *) MemoryMap + MemoryMapSize);\r
+  MemoryMapEnd       = (EFI_MEMORY_DESCRIPTOR *)((UINT8 *)MemoryMap + MemoryMapSize);\r
   while (MemoryMapEntry < MemoryMapEnd) {\r
     while (NextMemoryMapEntry < MemoryMapEnd) {\r
       if (MemoryMapEntry->PhysicalStart > NextMemoryMapEntry->PhysicalStart) {\r
-        CopyMem (&TempMemoryMap, MemoryMapEntry, sizeof(EFI_MEMORY_DESCRIPTOR));\r
-        CopyMem (MemoryMapEntry, NextMemoryMapEntry, sizeof(EFI_MEMORY_DESCRIPTOR));\r
-        CopyMem (NextMemoryMapEntry, &TempMemoryMap, sizeof(EFI_MEMORY_DESCRIPTOR));\r
+        CopyMem (&TempMemoryMap, MemoryMapEntry, sizeof (EFI_MEMORY_DESCRIPTOR));\r
+        CopyMem (MemoryMapEntry, NextMemoryMapEntry, sizeof (EFI_MEMORY_DESCRIPTOR));\r
+        CopyMem (NextMemoryMapEntry, &TempMemoryMap, sizeof (EFI_MEMORY_DESCRIPTOR));\r
       }\r
 \r
       NextMemoryMapEntry = NEXT_MEMORY_DESCRIPTOR (NextMemoryMapEntry, DescriptorSize);\r
     }\r
 \r
-    MemoryMapEntry      = NEXT_MEMORY_DESCRIPTOR (MemoryMapEntry, DescriptorSize);\r
-    NextMemoryMapEntry  = NEXT_MEMORY_DESCRIPTOR (MemoryMapEntry, DescriptorSize);\r
+    MemoryMapEntry     = NEXT_MEMORY_DESCRIPTOR (MemoryMapEntry, DescriptorSize);\r
+    NextMemoryMapEntry = NEXT_MEMORY_DESCRIPTOR (MemoryMapEntry, DescriptorSize);\r
   }\r
 }\r
 \r
@@ -1034,16 +1063,16 @@ IsUefiPageNotPresent (
   )\r
 {\r
   switch (MemoryMap->Type) {\r
-  case EfiLoaderCode:\r
-  case EfiLoaderData:\r
-  case EfiBootServicesCode:\r
-  case EfiBootServicesData:\r
-  case EfiConventionalMemory:\r
-  case EfiUnusableMemory:\r
-  case EfiACPIReclaimMemory:\r
-    return TRUE;\r
-  default:\r
-    return FALSE;\r
+    case EfiLoaderCode:\r
+    case EfiLoaderData:\r
+    case EfiBootServicesCode:\r
+    case EfiBootServicesData:\r
+    case EfiConventionalMemory:\r
+    case EfiUnusableMemory:\r
+    case EfiACPIReclaimMemory:\r
+      return TRUE;\r
+    default:\r
+      return FALSE;\r
   }\r
 }\r
 \r
@@ -1069,24 +1098,25 @@ MergeMemoryMapForNotPresentEntry (
   IN UINTN                      DescriptorSize\r
   )\r
 {\r
-  EFI_MEMORY_DESCRIPTOR       *MemoryMapEntry;\r
-  EFI_MEMORY_DESCRIPTOR       *MemoryMapEnd;\r
-  UINT64                      MemoryBlockLength;\r
-  EFI_MEMORY_DESCRIPTOR       *NewMemoryMapEntry;\r
-  EFI_MEMORY_DESCRIPTOR       *NextMemoryMapEntry;\r
+  EFI_MEMORY_DESCRIPTOR  *MemoryMapEntry;\r
+  EFI_MEMORY_DESCRIPTOR  *MemoryMapEnd;\r
+  UINT64                 MemoryBlockLength;\r
+  EFI_MEMORY_DESCRIPTOR  *NewMemoryMapEntry;\r
+  EFI_MEMORY_DESCRIPTOR  *NextMemoryMapEntry;\r
 \r
-  MemoryMapEntry = MemoryMap;\r
+  MemoryMapEntry    = MemoryMap;\r
   NewMemoryMapEntry = MemoryMap;\r
-  MemoryMapEnd = (EFI_MEMORY_DESCRIPTOR *) ((UINT8 *) MemoryMap + *MemoryMapSize);\r
+  MemoryMapEnd      = (EFI_MEMORY_DESCRIPTOR *)((UINT8 *)MemoryMap + *MemoryMapSize);\r
   while ((UINTN)MemoryMapEntry < (UINTN)MemoryMapEnd) {\r
-    CopyMem (NewMemoryMapEntry, MemoryMapEntry, sizeof(EFI_MEMORY_DESCRIPTOR));\r
+    CopyMem (NewMemoryMapEntry, MemoryMapEntry, sizeof (EFI_MEMORY_DESCRIPTOR));\r
     NextMemoryMapEntry = NEXT_MEMORY_DESCRIPTOR (MemoryMapEntry, DescriptorSize);\r
 \r
     do {\r
-      MemoryBlockLength = (UINT64) (EFI_PAGES_TO_SIZE((UINTN)MemoryMapEntry->NumberOfPages));\r
+      MemoryBlockLength = (UINT64)(EFI_PAGES_TO_SIZE ((UINTN)MemoryMapEntry->NumberOfPages));\r
       if (((UINTN)NextMemoryMapEntry < (UINTN)MemoryMapEnd) &&\r
-          IsUefiPageNotPresent(MemoryMapEntry) && IsUefiPageNotPresent(NextMemoryMapEntry) &&\r
-          ((MemoryMapEntry->PhysicalStart + MemoryBlockLength) == NextMemoryMapEntry->PhysicalStart)) {\r
+          IsUefiPageNotPresent (MemoryMapEntry) && IsUefiPageNotPresent (NextMemoryMapEntry) &&\r
+          ((MemoryMapEntry->PhysicalStart + MemoryBlockLength) == NextMemoryMapEntry->PhysicalStart))\r
+      {\r
         MemoryMapEntry->NumberOfPages += NextMemoryMapEntry->NumberOfPages;\r
         if (NewMemoryMapEntry != MemoryMapEntry) {\r
           NewMemoryMapEntry->NumberOfPages += NextMemoryMapEntry->NumberOfPages;\r
@@ -1100,13 +1130,13 @@ MergeMemoryMapForNotPresentEntry (
       }\r
     } while (TRUE);\r
 \r
-    MemoryMapEntry = NEXT_MEMORY_DESCRIPTOR (MemoryMapEntry, DescriptorSize);\r
+    MemoryMapEntry    = NEXT_MEMORY_DESCRIPTOR (MemoryMapEntry, DescriptorSize);\r
     NewMemoryMapEntry = NEXT_MEMORY_DESCRIPTOR (NewMemoryMapEntry, DescriptorSize);\r
   }\r
 \r
   *MemoryMapSize = (UINTN)NewMemoryMapEntry - (UINTN)MemoryMap;\r
 \r
-  return ;\r
+  return;\r
 }\r
 \r
 /**\r
@@ -1124,15 +1154,16 @@ GetGcdMemoryMap (
 \r
   Status = gDS->GetMemorySpaceMap (&NumberOfDescriptors, &MemSpaceMap);\r
   if (EFI_ERROR (Status)) {\r
-    return ;\r
+    return;\r
   }\r
 \r
   mGcdMemNumberOfDesc = 0;\r
   for (Index = 0; Index < NumberOfDescriptors; Index++) {\r
-    if (MemSpaceMap[Index].GcdMemoryType == EfiGcdMemoryTypeReserved &&\r
-        (MemSpaceMap[Index].Capabilities & (EFI_MEMORY_PRESENT | EFI_MEMORY_INITIALIZED | EFI_MEMORY_TESTED)) ==\r
-          (EFI_MEMORY_PRESENT | EFI_MEMORY_INITIALIZED)\r
-          ) {\r
+    if ((MemSpaceMap[Index].GcdMemoryType == EfiGcdMemoryTypeReserved) &&\r
+        ((MemSpaceMap[Index].Capabilities & (EFI_MEMORY_PRESENT | EFI_MEMORY_INITIALIZED | EFI_MEMORY_TESTED)) ==\r
+         (EFI_MEMORY_PRESENT | EFI_MEMORY_INITIALIZED))\r
+        )\r
+    {\r
       mGcdMemNumberOfDesc++;\r
     }\r
   }\r
@@ -1142,19 +1173,20 @@ GetGcdMemoryMap (
   if (mGcdMemSpace == NULL) {\r
     mGcdMemNumberOfDesc = 0;\r
     gBS->FreePool (MemSpaceMap);\r
-    return ;\r
+    return;\r
   }\r
 \r
   mGcdMemNumberOfDesc = 0;\r
   for (Index = 0; Index < NumberOfDescriptors; Index++) {\r
-    if (MemSpaceMap[Index].GcdMemoryType == EfiGcdMemoryTypeReserved &&\r
-        (MemSpaceMap[Index].Capabilities & (EFI_MEMORY_PRESENT | EFI_MEMORY_INITIALIZED | EFI_MEMORY_TESTED)) ==\r
-          (EFI_MEMORY_PRESENT | EFI_MEMORY_INITIALIZED)\r
-          ) {\r
+    if ((MemSpaceMap[Index].GcdMemoryType == EfiGcdMemoryTypeReserved) &&\r
+        ((MemSpaceMap[Index].Capabilities & (EFI_MEMORY_PRESENT | EFI_MEMORY_INITIALIZED | EFI_MEMORY_TESTED)) ==\r
+         (EFI_MEMORY_PRESENT | EFI_MEMORY_INITIALIZED))\r
+        )\r
+    {\r
       CopyMem (\r
         &mGcdMemSpace[mGcdMemNumberOfDesc],\r
         &MemSpaceMap[Index],\r
-        sizeof(EFI_GCD_MEMORY_SPACE_DESCRIPTOR)\r
+        sizeof (EFI_GCD_MEMORY_SPACE_DESCRIPTOR)\r
         );\r
       mGcdMemNumberOfDesc++;\r
     }\r
@@ -1177,7 +1209,7 @@ GetUefiMemoryAttributesTable (
 \r
   Status = EfiGetSystemConfigurationTable (&gEfiMemoryAttributesTableGuid, (VOID **)&MemoryAttributesTable);\r
   if (!EFI_ERROR (Status) && (MemoryAttributesTable != NULL)) {\r
-    MemoryAttributesTableSize = sizeof(EFI_MEMORY_ATTRIBUTES_TABLE) + MemoryAttributesTable->DescriptorSize * MemoryAttributesTable->NumberOfEntries;\r
+    MemoryAttributesTableSize  = sizeof (EFI_MEMORY_ATTRIBUTES_TABLE) + MemoryAttributesTable->DescriptorSize * MemoryAttributesTable->NumberOfEntries;\r
     mUefiMemoryAttributesTable = AllocateCopyPool (MemoryAttributesTableSize, MemoryAttributesTable);\r
     ASSERT (mUefiMemoryAttributesTable != NULL);\r
   }\r
@@ -1191,30 +1223,30 @@ GetUefiMemoryMap (
   VOID\r
   )\r
 {\r
-  EFI_STATUS            Status;\r
-  UINTN                 MapKey;\r
-  UINT32                DescriptorVersion;\r
-  EFI_MEMORY_DESCRIPTOR *MemoryMap;\r
-  UINTN                 UefiMemoryMapSize;\r
+  EFI_STATUS             Status;\r
+  UINTN                  MapKey;\r
+  UINT32                 DescriptorVersion;\r
+  EFI_MEMORY_DESCRIPTOR  *MemoryMap;\r
+  UINTN                  UefiMemoryMapSize;\r
 \r
   DEBUG ((DEBUG_INFO, "GetUefiMemoryMap\n"));\r
 \r
   UefiMemoryMapSize = 0;\r
-  MemoryMap = NULL;\r
-  Status = gBS->GetMemoryMap (\r
-                  &UefiMemoryMapSize,\r
-                  MemoryMap,\r
-                  &MapKey,\r
-                  &mUefiDescriptorSize,\r
-                  &DescriptorVersion\r
-                  );\r
+  MemoryMap         = NULL;\r
+  Status            = gBS->GetMemoryMap (\r
+                             &UefiMemoryMapSize,\r
+                             MemoryMap,\r
+                             &MapKey,\r
+                             &mUefiDescriptorSize,\r
+                             &DescriptorVersion\r
+                             );\r
   ASSERT (Status == EFI_BUFFER_TOO_SMALL);\r
 \r
   do {\r
     Status = gBS->AllocatePool (EfiBootServicesData, UefiMemoryMapSize, (VOID **)&MemoryMap);\r
     ASSERT (MemoryMap != NULL);\r
     if (MemoryMap == NULL) {\r
-      return ;\r
+      return;\r
     }\r
 \r
     Status = gBS->GetMemoryMap (\r
@@ -1231,14 +1263,14 @@ GetUefiMemoryMap (
   } while (Status == EFI_BUFFER_TOO_SMALL);\r
 \r
   if (MemoryMap == NULL) {\r
-    return ;\r
+    return;\r
   }\r
 \r
   SortMemoryMap (MemoryMap, UefiMemoryMapSize, mUefiDescriptorSize);\r
   MergeMemoryMapForNotPresentEntry (MemoryMap, &UefiMemoryMapSize, mUefiDescriptorSize);\r
 \r
   mUefiMemoryMapSize = UefiMemoryMapSize;\r
-  mUefiMemoryMap = AllocateCopyPool (UefiMemoryMapSize, MemoryMap);\r
+  mUefiMemoryMap     = AllocateCopyPool (UefiMemoryMapSize, MemoryMap);\r
   ASSERT (mUefiMemoryMap != NULL);\r
 \r
   gBS->FreePool (MemoryMap);\r
@@ -1266,35 +1298,37 @@ SetUefiMemMapAttributes (
   VOID\r
   )\r
 {\r
-  EFI_STATUS            Status;\r
-  EFI_MEMORY_DESCRIPTOR *MemoryMap;\r
-  UINTN                 MemoryMapEntryCount;\r
-  UINTN                 Index;\r
-  EFI_MEMORY_DESCRIPTOR *Entry;\r
+  EFI_STATUS             Status;\r
+  EFI_MEMORY_DESCRIPTOR  *MemoryMap;\r
+  UINTN                  MemoryMapEntryCount;\r
+  UINTN                  Index;\r
+  EFI_MEMORY_DESCRIPTOR  *Entry;\r
 \r
   DEBUG ((DEBUG_INFO, "SetUefiMemMapAttributes\n"));\r
 \r
   if (mUefiMemoryMap != NULL) {\r
     MemoryMapEntryCount = mUefiMemoryMapSize/mUefiDescriptorSize;\r
-    MemoryMap = mUefiMemoryMap;\r
+    MemoryMap           = mUefiMemoryMap;\r
     for (Index = 0; Index < MemoryMapEntryCount; Index++) {\r
-      if (IsUefiPageNotPresent(MemoryMap)) {\r
+      if (IsUefiPageNotPresent (MemoryMap)) {\r
         Status = SmmSetMemoryAttributes (\r
                    MemoryMap->PhysicalStart,\r
-                   EFI_PAGES_TO_SIZE((UINTN)MemoryMap->NumberOfPages),\r
+                   EFI_PAGES_TO_SIZE ((UINTN)MemoryMap->NumberOfPages),\r
                    EFI_MEMORY_RP\r
                    );\r
         DEBUG ((\r
           DEBUG_INFO,\r
           "UefiMemory protection: 0x%lx - 0x%lx %r\n",\r
           MemoryMap->PhysicalStart,\r
-          MemoryMap->PhysicalStart + (UINT64)EFI_PAGES_TO_SIZE((UINTN)MemoryMap->NumberOfPages),\r
+          MemoryMap->PhysicalStart + (UINT64)EFI_PAGES_TO_SIZE ((UINTN)MemoryMap->NumberOfPages),\r
           Status\r
           ));\r
       }\r
-      MemoryMap = NEXT_MEMORY_DESCRIPTOR(MemoryMap, mUefiDescriptorSize);\r
+\r
+      MemoryMap = NEXT_MEMORY_DESCRIPTOR (MemoryMap, mUefiDescriptorSize);\r
     }\r
   }\r
+\r
   //\r
   // Do not free mUefiMemoryMap, it will be checked in IsSmmCommBufferForbiddenAddress().\r
   //\r
@@ -1318,6 +1352,7 @@ SetUefiMemMapAttributes (
         ));\r
     }\r
   }\r
+\r
   //\r
   // Do not free mGcdMemSpace, it will be checked in IsSmmCommBufferForbiddenAddress().\r
   //\r
@@ -1328,25 +1363,27 @@ SetUefiMemMapAttributes (
   if (mUefiMemoryAttributesTable != NULL) {\r
     Entry = (EFI_MEMORY_DESCRIPTOR *)(mUefiMemoryAttributesTable + 1);\r
     for (Index = 0; Index < mUefiMemoryAttributesTable->NumberOfEntries; Index++) {\r
-      if (Entry->Type == EfiRuntimeServicesCode || Entry->Type == EfiRuntimeServicesData) {\r
+      if ((Entry->Type == EfiRuntimeServicesCode) || (Entry->Type == EfiRuntimeServicesData)) {\r
         if ((Entry->Attribute & EFI_MEMORY_RO) != 0) {\r
           Status = SmmSetMemoryAttributes (\r
                      Entry->PhysicalStart,\r
-                     EFI_PAGES_TO_SIZE((UINTN)Entry->NumberOfPages),\r
+                     EFI_PAGES_TO_SIZE ((UINTN)Entry->NumberOfPages),\r
                      EFI_MEMORY_RP\r
                      );\r
           DEBUG ((\r
             DEBUG_INFO,\r
             "UefiMemoryAttribute protection: 0x%lx - 0x%lx %r\n",\r
             Entry->PhysicalStart,\r
-            Entry->PhysicalStart + (UINT64)EFI_PAGES_TO_SIZE((UINTN)Entry->NumberOfPages),\r
+            Entry->PhysicalStart + (UINT64)EFI_PAGES_TO_SIZE ((UINTN)Entry->NumberOfPages),\r
             Status\r
             ));\r
         }\r
       }\r
+\r
       Entry = NEXT_MEMORY_DESCRIPTOR (Entry, mUefiMemoryAttributesTable->DescriptorSize);\r
     }\r
   }\r
+\r
   //\r
   // Do not free mUefiMemoryAttributesTable, it will be checked in IsSmmCommBufferForbiddenAddress().\r
   //\r
@@ -1365,29 +1402,32 @@ IsSmmCommBufferForbiddenAddress (
   IN UINT64  Address\r
   )\r
 {\r
-  EFI_MEMORY_DESCRIPTOR *MemoryMap;\r
-  UINTN                 MemoryMapEntryCount;\r
-  UINTN                 Index;\r
-  EFI_MEMORY_DESCRIPTOR *Entry;\r
+  EFI_MEMORY_DESCRIPTOR  *MemoryMap;\r
+  UINTN                  MemoryMapEntryCount;\r
+  UINTN                  Index;\r
+  EFI_MEMORY_DESCRIPTOR  *Entry;\r
 \r
   if (mUefiMemoryMap != NULL) {\r
-    MemoryMap = mUefiMemoryMap;\r
+    MemoryMap           = mUefiMemoryMap;\r
     MemoryMapEntryCount = mUefiMemoryMapSize/mUefiDescriptorSize;\r
     for (Index = 0; Index < MemoryMapEntryCount; Index++) {\r
       if (IsUefiPageNotPresent (MemoryMap)) {\r
         if ((Address >= MemoryMap->PhysicalStart) &&\r
-            (Address < MemoryMap->PhysicalStart + EFI_PAGES_TO_SIZE((UINTN)MemoryMap->NumberOfPages)) ) {\r
+            (Address < MemoryMap->PhysicalStart + EFI_PAGES_TO_SIZE ((UINTN)MemoryMap->NumberOfPages)))\r
+        {\r
           return TRUE;\r
         }\r
       }\r
-      MemoryMap = NEXT_MEMORY_DESCRIPTOR(MemoryMap, mUefiDescriptorSize);\r
+\r
+      MemoryMap = NEXT_MEMORY_DESCRIPTOR (MemoryMap, mUefiDescriptorSize);\r
     }\r
   }\r
 \r
   if (mGcdMemSpace != NULL) {\r
     for (Index = 0; Index < mGcdMemNumberOfDesc; Index++) {\r
       if ((Address >= mGcdMemSpace[Index].BaseAddress) &&\r
-          (Address < mGcdMemSpace[Index].BaseAddress + mGcdMemSpace[Index].Length) ) {\r
+          (Address < mGcdMemSpace[Index].BaseAddress + mGcdMemSpace[Index].Length))\r
+      {\r
         return TRUE;\r
       }\r
     }\r
@@ -1396,17 +1436,20 @@ IsSmmCommBufferForbiddenAddress (
   if (mUefiMemoryAttributesTable != NULL) {\r
     Entry = (EFI_MEMORY_DESCRIPTOR *)(mUefiMemoryAttributesTable + 1);\r
     for (Index = 0; Index < mUefiMemoryAttributesTable->NumberOfEntries; Index++) {\r
-      if (Entry->Type == EfiRuntimeServicesCode || Entry->Type == EfiRuntimeServicesData) {\r
+      if ((Entry->Type == EfiRuntimeServicesCode) || (Entry->Type == EfiRuntimeServicesData)) {\r
         if ((Entry->Attribute & EFI_MEMORY_RO) != 0) {\r
           if ((Address >= Entry->PhysicalStart) &&\r
-              (Address < Entry->PhysicalStart + LShiftU64 (Entry->NumberOfPages, EFI_PAGE_SHIFT))) {\r
+              (Address < Entry->PhysicalStart + LShiftU64 (Entry->NumberOfPages, EFI_PAGE_SHIFT)))\r
+          {\r
             return TRUE;\r
           }\r
+\r
           Entry = NEXT_MEMORY_DESCRIPTOR (Entry, mUefiMemoryAttributesTable->DescriptorSize);\r
         }\r
       }\r
     }\r
   }\r
+\r
   return FALSE;\r
 }\r
 \r
@@ -1436,10 +1479,10 @@ IsSmmCommBufferForbiddenAddress (
 EFI_STATUS\r
 EFIAPI\r
 EdkiiSmmSetMemoryAttributes (\r
-  IN  EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL   *This,\r
-  IN  EFI_PHYSICAL_ADDRESS                  BaseAddress,\r
-  IN  UINT64                                Length,\r
-  IN  UINT64                                Attributes\r
+  IN  EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL  *This,\r
+  IN  EFI_PHYSICAL_ADDRESS                 BaseAddress,\r
+  IN  UINT64                               Length,\r
+  IN  UINT64                               Attributes\r
   )\r
 {\r
   return SmmSetMemoryAttributes (BaseAddress, Length, Attributes);\r
@@ -1471,10 +1514,10 @@ EdkiiSmmSetMemoryAttributes (
 EFI_STATUS\r
 EFIAPI\r
 EdkiiSmmClearMemoryAttributes (\r
-  IN  EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL   *This,\r
-  IN  EFI_PHYSICAL_ADDRESS                  BaseAddress,\r
-  IN  UINT64                                Length,\r
-  IN  UINT64                                Attributes\r
+  IN  EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL  *This,\r
+  IN  EFI_PHYSICAL_ADDRESS                 BaseAddress,\r
+  IN  UINT64                               Length,\r
+  IN  UINT64                               Attributes\r
   )\r
 {\r
   return SmmClearMemoryAttributes (BaseAddress, Length, Attributes);\r
@@ -1504,10 +1547,10 @@ EdkiiSmmClearMemoryAttributes (
 EFI_STATUS\r
 EFIAPI\r
 EdkiiSmmGetMemoryAttributes (\r
-  IN  EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL   *This,\r
-  IN  EFI_PHYSICAL_ADDRESS                  BaseAddress,\r
-  IN  UINT64                                Length,\r
-  OUT UINT64                                *Attributes\r
+  IN  EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL  *This,\r
+  IN  EFI_PHYSICAL_ADDRESS                 BaseAddress,\r
+  IN  UINT64                               Length,\r
+  OUT UINT64                               *Attributes\r
   )\r
 {\r
   EFI_PHYSICAL_ADDRESS  Address;\r
@@ -1516,17 +1559,16 @@ EdkiiSmmGetMemoryAttributes (
   PAGE_ATTRIBUTE        PageAttr;\r
   INT64                 Size;\r
 \r
-  if (Length < SIZE_4KB || Attributes == NULL) {\r
+  if ((Length < SIZE_4KB) || (Attributes == NULL)) {\r
     return EFI_INVALID_PARAMETER;\r
   }\r
 \r
-  Size = (INT64)Length;\r
+  Size    = (INT64)Length;\r
   MemAttr = (UINT64)-1;\r
 \r
   do {\r
-\r
     PageEntry = GetPageTableEntry (BaseAddress, &PageAttr);\r
-    if (PageEntry == NULL || PageAttr == PageNone) {\r
+    if ((PageEntry == NULL) || (PageAttr == PageNone)) {\r
       return EFI_UNSUPPORTED;\r
     }\r
 \r
@@ -1535,35 +1577,34 @@ EdkiiSmmGetMemoryAttributes (
     // share the same attribute. Return EFI_NO_MAPPING if not.\r
     //\r
     *Attributes = GetAttributesFromPageEntry (PageEntry);\r
-    if (MemAttr != (UINT64)-1 && *Attributes != MemAttr) {\r
+    if ((MemAttr != (UINT64)-1) && (*Attributes != MemAttr)) {\r
       return EFI_NO_MAPPING;\r
     }\r
 \r
     switch (PageAttr) {\r
-    case Page4K:\r
-      Address     = *PageEntry & ~mAddressEncMask & PAGING_4K_ADDRESS_MASK_64;\r
-      Size        -= (SIZE_4KB - (BaseAddress - Address));\r
-      BaseAddress += (SIZE_4KB - (BaseAddress - Address));\r
-      break;\r
-\r
-    case Page2M:\r
-      Address     = *PageEntry & ~mAddressEncMask & PAGING_2M_ADDRESS_MASK_64;\r
-      Size        -= SIZE_2MB - (BaseAddress - Address);\r
-      BaseAddress += SIZE_2MB - (BaseAddress - Address);\r
-      break;\r
-\r
-    case Page1G:\r
-      Address     = *PageEntry & ~mAddressEncMask & PAGING_1G_ADDRESS_MASK_64;\r
-      Size        -= SIZE_1GB - (BaseAddress - Address);\r
-      BaseAddress += SIZE_1GB - (BaseAddress - Address);\r
-      break;\r
+      case Page4K:\r
+        Address      = *PageEntry & ~mAddressEncMask & PAGING_4K_ADDRESS_MASK_64;\r
+        Size        -= (SIZE_4KB - (BaseAddress - Address));\r
+        BaseAddress += (SIZE_4KB - (BaseAddress - Address));\r
+        break;\r
 \r
-    default:\r
-      return EFI_UNSUPPORTED;\r
+      case Page2M:\r
+        Address      = *PageEntry & ~mAddressEncMask & PAGING_2M_ADDRESS_MASK_64;\r
+        Size        -= SIZE_2MB - (BaseAddress - Address);\r
+        BaseAddress += SIZE_2MB - (BaseAddress - Address);\r
+        break;\r
+\r
+      case Page1G:\r
+        Address      = *PageEntry & ~mAddressEncMask & PAGING_1G_ADDRESS_MASK_64;\r
+        Size        -= SIZE_1GB - (BaseAddress - Address);\r
+        BaseAddress += SIZE_1GB - (BaseAddress - Address);\r
+        break;\r
+\r
+      default:\r
+        return EFI_UNSUPPORTED;\r
     }\r
 \r
     MemAttr = *Attributes;\r
-\r
   } while (Size > 0);\r
 \r
   return EFI_SUCCESS;\r

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmMp.c b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmMp.c
index 9b2b191e038579a776c806b48faac8a0012a84ee..6cc5f016cace2a43df71f69f772c21dd193abb75 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmMp.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmMp.c
@@ -13,7 +13,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
 ///\r
 /// SMM MP Protocol instance\r
 ///\r
-EFI_MM_MP_PROTOCOL  mSmmMp  = {\r
+EFI_MM_MP_PROTOCOL  mSmmMp = {\r
   EFI_MM_MP_PROTOCOL_REVISION,\r
   0,\r
   SmmMpGetNumberOfProcessors,\r
@@ -37,8 +37,8 @@ EFI_MM_MP_PROTOCOL  mSmmMp  = {
 EFI_STATUS\r
 EFIAPI\r
 SmmMpGetNumberOfProcessors (\r
-  IN CONST EFI_MM_MP_PROTOCOL   *This,\r
-  OUT      UINTN                *NumberOfProcessors\r
+  IN CONST EFI_MM_MP_PROTOCOL  *This,\r
+  OUT      UINTN               *NumberOfProcessors\r
   )\r
 {\r
   if (NumberOfProcessors == NULL) {\r
@@ -114,23 +114,23 @@ SmmMpGetNumberOfProcessors (
 EFI_STATUS\r
 EFIAPI\r
 SmmMpDispatchProcedure (\r
-  IN CONST EFI_MM_MP_PROTOCOL            *This,\r
-  IN       EFI_AP_PROCEDURE2             Procedure,\r
-  IN       UINTN                         CpuNumber,\r
-  IN       UINTN                         TimeoutInMicroseconds,\r
-  IN OUT   VOID                          *ProcedureArguments OPTIONAL,\r
-  IN OUT   MM_COMPLETION                 *Token,\r
-  IN OUT   EFI_STATUS                    *CPUStatus\r
+  IN CONST EFI_MM_MP_PROTOCOL  *This,\r
+  IN       EFI_AP_PROCEDURE2   Procedure,\r
+  IN       UINTN               CpuNumber,\r
+  IN       UINTN               TimeoutInMicroseconds,\r
+  IN OUT   VOID                *ProcedureArguments OPTIONAL,\r
+  IN OUT   MM_COMPLETION       *Token,\r
+  IN OUT   EFI_STATUS          *CPUStatus\r
   )\r
 {\r
   return InternalSmmStartupThisAp (\r
-    Procedure,\r
-    CpuNumber,\r
-    ProcedureArguments,\r
-    Token,\r
-    TimeoutInMicroseconds,\r
-    CPUStatus\r
-    );\r
+           Procedure,\r
+           CpuNumber,\r
+           ProcedureArguments,\r
+           Token,\r
+           TimeoutInMicroseconds,\r
+           CPUStatus\r
+           );\r
 }\r
 \r
 /**\r
@@ -202,21 +202,21 @@ SmmMpDispatchProcedure (
 EFI_STATUS\r
 EFIAPI\r
 SmmMpBroadcastProcedure (\r
-  IN CONST EFI_MM_MP_PROTOCOL            *This,\r
-  IN       EFI_AP_PROCEDURE2             Procedure,\r
-  IN       UINTN                         TimeoutInMicroseconds,\r
-  IN OUT   VOID                          *ProcedureArguments OPTIONAL,\r
-  IN OUT   MM_COMPLETION                 *Token,\r
-  IN OUT   EFI_STATUS                    *CPUStatus\r
+  IN CONST EFI_MM_MP_PROTOCOL  *This,\r
+  IN       EFI_AP_PROCEDURE2   Procedure,\r
+  IN       UINTN               TimeoutInMicroseconds,\r
+  IN OUT   VOID                *ProcedureArguments OPTIONAL,\r
+  IN OUT   MM_COMPLETION       *Token,\r
+  IN OUT   EFI_STATUS          *CPUStatus\r
   )\r
 {\r
-  return InternalSmmStartupAllAPs(\r
-    Procedure,\r
-    TimeoutInMicroseconds,\r
-    ProcedureArguments,\r
-    Token,\r
-    CPUStatus\r
-    );\r
+  return InternalSmmStartupAllAPs (\r
+           Procedure,\r
+           TimeoutInMicroseconds,\r
+           ProcedureArguments,\r
+           Token,\r
+           CPUStatus\r
+           );\r
 }\r
 \r
 /**\r
@@ -286,8 +286,8 @@ SmmMpSetStartupProcedure (
 EFI_STATUS\r
 EFIAPI\r
 SmmMpCheckForProcedure (\r
-  IN CONST EFI_MM_MP_PROTOCOL            *This,\r
-  IN       MM_COMPLETION                 Token\r
+  IN CONST EFI_MM_MP_PROTOCOL  *This,\r
+  IN       MM_COMPLETION       Token\r
   )\r
 {\r
   if (Token == NULL) {\r
@@ -329,11 +329,11 @@ SmmMpCheckForProcedure (
 EFI_STATUS\r
 EFIAPI\r
 SmmMpWaitForProcedure (\r
-  IN CONST EFI_MM_MP_PROTOCOL            *This,\r
-  IN       MM_COMPLETION                 Token\r
+  IN CONST EFI_MM_MP_PROTOCOL  *This,\r
+  IN       MM_COMPLETION       Token\r
   )\r
 {\r
-  EFI_STATUS    Status;\r
+  EFI_STATUS  Status;\r
 \r
   do {\r
     Status = SmmMpCheckForProcedure (This, Token);\r
@@ -341,4 +341,3 @@ SmmMpWaitForProcedure (
 \r
   return Status;\r
 }\r
-\r

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmMp.h b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmMp.h
index b95ed8c6f836c20d355c40c5c207fcf54673210f..e2dac6c7d4de7fc5c15bee7cf6ec0f7f19d2a1f7 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmMp.h
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmMp.h
@@ -27,11 +27,10 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
 EFI_STATUS\r
 EFIAPI\r
 SmmMpGetNumberOfProcessors (\r
-  IN CONST EFI_MM_MP_PROTOCOL   *This,\r
-  OUT      UINTN                *NumberOfProcessors\r
+  IN CONST EFI_MM_MP_PROTOCOL  *This,\r
+  OUT      UINTN               *NumberOfProcessors\r
   );\r
 \r
-\r
 /**\r
   This service allows the caller to invoke a procedure one of the application processors (AP). This\r
   function uses an optional token parameter to support blocking and non-blocking modes. If the token\r
@@ -96,13 +95,13 @@ SmmMpGetNumberOfProcessors (
 EFI_STATUS\r
 EFIAPI\r
 SmmMpDispatchProcedure (\r
-  IN CONST EFI_MM_MP_PROTOCOL             *This,\r
-  IN       EFI_AP_PROCEDURE2              Procedure,\r
-  IN       UINTN                          CpuNumber,\r
-  IN       UINTN                          TimeoutInMicroseconds,\r
-  IN OUT   VOID                           *ProcedureArguments OPTIONAL,\r
-  IN OUT   MM_COMPLETION                  *Token,\r
-  IN OUT   EFI_STATUS                     *CPUStatus\r
+  IN CONST EFI_MM_MP_PROTOCOL  *This,\r
+  IN       EFI_AP_PROCEDURE2   Procedure,\r
+  IN       UINTN               CpuNumber,\r
+  IN       UINTN               TimeoutInMicroseconds,\r
+  IN OUT   VOID                *ProcedureArguments OPTIONAL,\r
+  IN OUT   MM_COMPLETION       *Token,\r
+  IN OUT   EFI_STATUS          *CPUStatus\r
   );\r
 \r
 /**\r
@@ -174,15 +173,14 @@ SmmMpDispatchProcedure (
 EFI_STATUS\r
 EFIAPI\r
 SmmMpBroadcastProcedure (\r
-  IN CONST EFI_MM_MP_PROTOCOL             *This,\r
-  IN       EFI_AP_PROCEDURE2              Procedure,\r
-  IN       UINTN                          TimeoutInMicroseconds,\r
-  IN OUT   VOID                           *ProcedureArguments OPTIONAL,\r
-  IN OUT   MM_COMPLETION                  *Token,\r
-  IN OUT   EFI_STATUS                     *CPUStatus\r
+  IN CONST EFI_MM_MP_PROTOCOL  *This,\r
+  IN       EFI_AP_PROCEDURE2   Procedure,\r
+  IN       UINTN               TimeoutInMicroseconds,\r
+  IN OUT   VOID                *ProcedureArguments OPTIONAL,\r
+  IN OUT   MM_COMPLETION       *Token,\r
+  IN OUT   EFI_STATUS          *CPUStatus\r
   );\r
 \r
-\r
 /**\r
   This service allows the caller to set a startup procedure that will be executed when an AP powers\r
   up from a state where core configuration and context is lost. The procedure is execution has the\r
@@ -246,8 +244,8 @@ SmmMpSetStartupProcedure (
 EFI_STATUS\r
 EFIAPI\r
 SmmMpCheckForProcedure (\r
-  IN CONST EFI_MM_MP_PROTOCOL             *This,\r
-  IN       MM_COMPLETION                  Token\r
+  IN CONST EFI_MM_MP_PROTOCOL  *This,\r
+  IN       MM_COMPLETION       Token\r
   );\r
 \r
 /**\r
@@ -278,8 +276,8 @@ SmmMpCheckForProcedure (
 EFI_STATUS\r
 EFIAPI\r
 SmmMpWaitForProcedure (\r
-  IN CONST EFI_MM_MP_PROTOCOL            *This,\r
-  IN       MM_COMPLETION                 Token\r
+  IN CONST EFI_MM_MP_PROTOCOL  *This,\r
+  IN       MM_COMPLETION       Token\r
   );\r
 \r
 #endif\r

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c
index c3f9794b9538dde2da524c2786cf87bea58b369c..c1efda7126054686df242199a45b6aafac65db20 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c
@@ -11,80 +11,84 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
 #include "PiSmmCpuDxeSmm.h"\r
 #include "SmmProfileInternal.h"\r
 \r
-UINT32                    mSmmProfileCr3;\r
+UINT32  mSmmProfileCr3;\r
 \r
-SMM_PROFILE_HEADER        *mSmmProfileBase;\r
-MSR_DS_AREA_STRUCT        *mMsrDsAreaBase;\r
+SMM_PROFILE_HEADER  *mSmmProfileBase;\r
+MSR_DS_AREA_STRUCT  *mMsrDsAreaBase;\r
 //\r
 // The buffer to store SMM profile data.\r
 //\r
-UINTN                     mSmmProfileSize;\r
+UINTN  mSmmProfileSize;\r
 \r
 //\r
 // The buffer to enable branch trace store.\r
 //\r
-UINTN                     mMsrDsAreaSize   = SMM_PROFILE_DTS_SIZE;\r
+UINTN  mMsrDsAreaSize = SMM_PROFILE_DTS_SIZE;\r
 \r
 //\r
 // The flag indicates if execute-disable is supported by processor.\r
 //\r
-BOOLEAN                   mXdSupported     = TRUE;\r
+BOOLEAN  mXdSupported = TRUE;\r
 \r
 //\r
 // The flag indicates if execute-disable is enabled on processor.\r
 //\r
-BOOLEAN                   mXdEnabled       = FALSE;\r
+BOOLEAN  mXdEnabled = FALSE;\r
 \r
 //\r
 // The flag indicates if BTS is supported by processor.\r
 //\r
-BOOLEAN                   mBtsSupported     = TRUE;\r
+BOOLEAN  mBtsSupported = TRUE;\r
 \r
 //\r
 // The flag indicates if SMM profile starts to record data.\r
 //\r
-BOOLEAN                   mSmmProfileStart = FALSE;\r
+BOOLEAN  mSmmProfileStart = FALSE;\r
 \r
 //\r
 // The flag indicates if #DB will be setup in #PF handler.\r
 //\r
-BOOLEAN                   mSetupDebugTrap = FALSE;\r
+BOOLEAN  mSetupDebugTrap = FALSE;\r
 \r
 //\r
 // Record the page fault exception count for one instruction execution.\r
 //\r
-UINTN                     *mPFEntryCount;\r
+UINTN  *mPFEntryCount;\r
 \r
-UINT64                    (*mLastPFEntryValue)[MAX_PF_ENTRY_COUNT];\r
+UINT64 (*mLastPFEntryValue)[MAX_PF_ENTRY_COUNT];\r
 UINT64                    *(*mLastPFEntryPointer)[MAX_PF_ENTRY_COUNT];\r
 \r
-MSR_DS_AREA_STRUCT        **mMsrDsArea;\r
-BRANCH_TRACE_RECORD       **mMsrBTSRecord;\r
-UINTN                     mBTSRecordNumber;\r
-PEBS_RECORD               **mMsrPEBSRecord;\r
+MSR_DS_AREA_STRUCT   **mMsrDsArea;\r
+BRANCH_TRACE_RECORD  **mMsrBTSRecord;\r
+UINTN                mBTSRecordNumber;\r
+PEBS_RECORD          **mMsrPEBSRecord;\r
 \r
 //\r
 // These memory ranges are always present, they does not generate the access type of page fault exception,\r
 // but they possibly generate instruction fetch type of page fault exception.\r
 //\r
-MEMORY_PROTECTION_RANGE   *mProtectionMemRange     = NULL;\r
-UINTN                     mProtectionMemRangeCount = 0;\r
+MEMORY_PROTECTION_RANGE  *mProtectionMemRange     = NULL;\r
+UINTN                    mProtectionMemRangeCount = 0;\r
 \r
 //\r
 // Some predefined memory ranges.\r
 //\r
-MEMORY_PROTECTION_RANGE mProtectionMemRangeTemplate[] = {\r
+MEMORY_PROTECTION_RANGE  mProtectionMemRangeTemplate[] = {\r
   //\r
   // SMRAM range (to be fixed in runtime).\r
   // It is always present and instruction fetches are allowed.\r
   //\r
-  {{0x00000000, 0x00000000},TRUE,FALSE},\r
+  {\r
+    { 0x00000000, 0x00000000 }, TRUE, FALSE\r
+  },\r
 \r
   //\r
   // SMM profile data range( to be fixed in runtime).\r
   // It is always present and instruction fetches are not allowed.\r
   //\r
-  {{0x00000000, 0x00000000},TRUE,TRUE},\r
+  {\r
+    { 0x00000000, 0x00000000 }, TRUE, TRUE\r
+  },\r
 \r
   //\r
   // SMRAM ranges not covered by mCpuHotPlugData.SmrrBase/mCpuHotPlugData.SmrrSiz (to be fixed in runtime).\r
@@ -105,13 +109,13 @@ MEMORY_PROTECTION_RANGE mProtectionMemRangeTemplate[] = {
 //\r
 // These memory ranges are mapped by 4KB-page instead of 2MB-page.\r
 //\r
-MEMORY_RANGE              *mSplitMemRange          = NULL;\r
-UINTN                     mSplitMemRangeCount      = 0;\r
+MEMORY_RANGE  *mSplitMemRange     = NULL;\r
+UINTN         mSplitMemRangeCount = 0;\r
 \r
 //\r
 // SMI command port.\r
 //\r
-UINT32                    mSmiCommandPort;\r
+UINT32  mSmiCommandPort;\r
 \r
 /**\r
   Disable branch trace store.\r
@@ -146,8 +150,8 @@ GetCpuIndex (
   VOID\r
   )\r
 {\r
-  UINTN     Index;\r
-  UINT32    ApicId;\r
+  UINTN   Index;\r
+  UINT32  ApicId;\r
 \r
   ApicId = GetApicId ();\r
 \r
@@ -156,6 +160,7 @@ GetCpuIndex (
       return Index;\r
     }\r
   }\r
+\r
   ASSERT (FALSE);\r
   return 0;\r
 }\r
@@ -169,8 +174,8 @@ GetCpuIndex (
 **/\r
 UINT64\r
 GetSourceFromDestinationOnBts (\r
-  UINTN  CpuIndex,\r
-  UINT64 DestinationIP\r
+  UINTN   CpuIndex,\r
+  UINT64  DestinationIP\r
   )\r
 {\r
   BRANCH_TRACE_RECORD  *CurrentBTSRecord;\r
@@ -186,8 +191,9 @@ GetSourceFromDestinationOnBts (
       // Underflow\r
       //\r
       CurrentBTSRecord = (BRANCH_TRACE_RECORD *)((UINTN)mMsrDsArea[CpuIndex]->BTSAbsoluteMaximum - 1);\r
-      CurrentBTSRecord --;\r
+      CurrentBTSRecord--;\r
     }\r
+\r
     if (CurrentBTSRecord->LastBranchTo == DestinationIP) {\r
       //\r
       // Good! find 1st one, then find 2nd one.\r
@@ -204,6 +210,7 @@ GetSourceFromDestinationOnBts (
         return CurrentBTSRecord->LastBranchFrom;\r
       }\r
     }\r
+\r
     CurrentBTSRecord--;\r
   }\r
 \r
@@ -221,8 +228,8 @@ GetSourceFromDestinationOnBts (
 VOID\r
 EFIAPI\r
 DebugExceptionHandler (\r
-    IN EFI_EXCEPTION_TYPE   InterruptType,\r
-    IN EFI_SYSTEM_CONTEXT   SystemContext\r
+  IN EFI_EXCEPTION_TYPE  InterruptType,\r
+  IN EFI_SYSTEM_CONTEXT  SystemContext\r
   )\r
 {\r
   UINTN  CpuIndex;\r
@@ -230,9 +237,11 @@ DebugExceptionHandler (
 \r
   if (!mSmmProfileStart &&\r
       !HEAP_GUARD_NONSTOP_MODE &&\r
-      !NULL_DETECTION_NONSTOP_MODE) {\r
+      !NULL_DETECTION_NONSTOP_MODE)\r
+  {\r
     return;\r
   }\r
+\r
   CpuIndex = GetCpuIndex ();\r
 \r
   //\r
@@ -268,7 +277,7 @@ DebugExceptionHandler (
 **/\r
 BOOLEAN\r
 IsInSmmRanges (\r
-  IN EFI_PHYSICAL_ADDRESS   Address\r
+  IN EFI_PHYSICAL_ADDRESS  Address\r
   )\r
 {\r
   UINTN  Index;\r
@@ -276,12 +285,15 @@ IsInSmmRanges (
   if ((Address >= mCpuHotPlugData.SmrrBase) && (Address < mCpuHotPlugData.SmrrBase + mCpuHotPlugData.SmrrSize)) {\r
     return TRUE;\r
   }\r
+\r
   for (Index = 0; Index < mSmmCpuSmramRangeCount; Index++) {\r
-    if (Address >= mSmmCpuSmramRanges[Index].CpuStart &&\r
-        Address < mSmmCpuSmramRanges[Index].CpuStart + mSmmCpuSmramRanges[Index].PhysicalSize) {\r
+    if ((Address >= mSmmCpuSmramRanges[Index].CpuStart) &&\r
+        (Address < mSmmCpuSmramRanges[Index].CpuStart + mSmmCpuSmramRanges[Index].PhysicalSize))\r
+    {\r
       return TRUE;\r
     }\r
   }\r
+\r
   return FALSE;\r
 }\r
 \r
@@ -294,8 +306,8 @@ IsInSmmRanges (
 **/\r
 BOOLEAN\r
 IsAddressValid (\r
-  IN EFI_PHYSICAL_ADDRESS   Address,\r
-  IN BOOLEAN                *Nx\r
+  IN EFI_PHYSICAL_ADDRESS  Address,\r
+  IN BOOLEAN               *Nx\r
   )\r
 {\r
   UINTN  Index;\r
@@ -310,14 +322,15 @@ IsAddressValid (
         return mProtectionMemRange[Index].Present;\r
       }\r
     }\r
+\r
     *Nx = TRUE;\r
     return FALSE;\r
-\r
   } else {\r
     *Nx = TRUE;\r
     if (IsInSmmRanges (Address)) {\r
       *Nx = FALSE;\r
     }\r
+\r
     return TRUE;\r
   }\r
 }\r
@@ -330,7 +343,7 @@ IsAddressValid (
 **/\r
 BOOLEAN\r
 IsAddressSplit (\r
-  IN EFI_PHYSICAL_ADDRESS   Address\r
+  IN EFI_PHYSICAL_ADDRESS  Address\r
   )\r
 {\r
   UINTN  Index;\r
@@ -349,12 +362,13 @@ IsAddressSplit (
       if ((mCpuHotPlugData.SmrrBase - Address) < BASE_2MB) {\r
         return TRUE;\r
       }\r
-    } else if (Address > (mCpuHotPlugData.SmrrBase + mCpuHotPlugData.SmrrSize - BASE_2MB))  {\r
+    } else if (Address > (mCpuHotPlugData.SmrrBase + mCpuHotPlugData.SmrrSize - BASE_2MB)) {\r
       if ((Address - (mCpuHotPlugData.SmrrBase + mCpuHotPlugData.SmrrSize - BASE_2MB)) < BASE_2MB) {\r
         return TRUE;\r
       }\r
     }\r
   }\r
+\r
   //\r
   // Return default\r
   //\r
@@ -393,9 +407,9 @@ InitProtectedMemRange (
   // Get MMIO ranges from GCD and add them into protected memory ranges.\r
   //\r
   gDS->GetMemorySpaceMap (\r
-       &NumberOfDescriptors,\r
-       &MemorySpaceMap\r
-       );\r
+         &NumberOfDescriptors,\r
+         &MemorySpaceMap\r
+         );\r
   for (Index = 0; Index < NumberOfDescriptors; Index++) {\r
     if (MemorySpaceMap[Index].GcdMemoryType == EfiGcdMemoryTypeMemoryMappedIo) {\r
       NumberOfAddedDescriptors++;\r
@@ -403,8 +417,8 @@ InitProtectedMemRange (
   }\r
 \r
   if (NumberOfAddedDescriptors != 0) {\r
-    TotalSize = NumberOfAddedDescriptors * sizeof (MEMORY_PROTECTION_RANGE) + sizeof (mProtectionMemRangeTemplate);\r
-    mProtectionMemRange = (MEMORY_PROTECTION_RANGE *) AllocateZeroPool (TotalSize);\r
+    TotalSize           = NumberOfAddedDescriptors * sizeof (MEMORY_PROTECTION_RANGE) + sizeof (mProtectionMemRangeTemplate);\r
+    mProtectionMemRange = (MEMORY_PROTECTION_RANGE *)AllocateZeroPool (TotalSize);\r
     ASSERT (mProtectionMemRange != NULL);\r
     mProtectionMemRangeCount = TotalSize / sizeof (MEMORY_PROTECTION_RANGE);\r
 \r
@@ -416,8 +430,8 @@ InitProtectedMemRange (
     //\r
     // Create split ranges which come from protected ranges.\r
     //\r
-    TotalSize = (TotalSize / sizeof (MEMORY_PROTECTION_RANGE)) * sizeof (MEMORY_RANGE);\r
-    mSplitMemRange = (MEMORY_RANGE *) AllocateZeroPool (TotalSize);\r
+    TotalSize      = (TotalSize / sizeof (MEMORY_PROTECTION_RANGE)) * sizeof (MEMORY_RANGE);\r
+    mSplitMemRange = (MEMORY_RANGE *)AllocateZeroPool (TotalSize);\r
     ASSERT (mSplitMemRange != NULL);\r
 \r
     //\r
@@ -425,13 +439,15 @@ InitProtectedMemRange (
     //\r
     NumberOfProtectRange = sizeof (mProtectionMemRangeTemplate) / sizeof (MEMORY_PROTECTION_RANGE);\r
     for (Index = 0; Index < mSmmCpuSmramRangeCount; Index++) {\r
-      if (mSmmCpuSmramRanges[Index].CpuStart >= mProtectionMemRange[0].Range.Base &&\r
-          mSmmCpuSmramRanges[Index].CpuStart + mSmmCpuSmramRanges[Index].PhysicalSize < mProtectionMemRange[0].Range.Top) {\r
+      if ((mSmmCpuSmramRanges[Index].CpuStart >= mProtectionMemRange[0].Range.Base) &&\r
+          (mSmmCpuSmramRanges[Index].CpuStart + mSmmCpuSmramRanges[Index].PhysicalSize < mProtectionMemRange[0].Range.Top))\r
+      {\r
         //\r
         // If the address have been already covered by mCpuHotPlugData.SmrrBase/mCpuHotPlugData.SmrrSiz\r
         //\r
         break;\r
       }\r
+\r
       mProtectionMemRange[NumberOfProtectRange].Range.Base = mSmmCpuSmramRanges[Index].CpuStart;\r
       mProtectionMemRange[NumberOfProtectRange].Range.Top  = mSmmCpuSmramRanges[Index].CpuStart + mSmmCpuSmramRanges[Index].PhysicalSize;\r
       mProtectionMemRange[NumberOfProtectRange].Present    = TRUE;\r
@@ -446,6 +462,7 @@ InitProtectedMemRange (
       if (MemorySpaceMap[Index].GcdMemoryType != EfiGcdMemoryTypeMemoryMappedIo) {\r
         continue;\r
       }\r
+\r
       mProtectionMemRange[NumberOfProtectRange].Range.Base = MemorySpaceMap[Index].BaseAddress;\r
       mProtectionMemRange[NumberOfProtectRange].Range.Top  = MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length;\r
       mProtectionMemRange[NumberOfProtectRange].Present    = TRUE;\r
@@ -479,7 +496,8 @@ InitProtectedMemRange (
       Top2MBAlignedAddress  = ProtectEndAddress & ~(SIZE_2MB - 1);\r
       Base2MBAlignedAddress = (ProtectBaseAddress + SIZE_2MB - 1) & ~(SIZE_2MB - 1);\r
       if ((Top2MBAlignedAddress > Base2MBAlignedAddress) &&\r
-          ((Top2MBAlignedAddress - Base2MBAlignedAddress) >= SIZE_2MB)) {\r
+          ((Top2MBAlignedAddress - Base2MBAlignedAddress) >= SIZE_2MB))\r
+      {\r
         //\r
         // There is an range which could be mapped by 2MB-page.\r
         //\r
@@ -493,6 +511,7 @@ InitProtectedMemRange (
           mSplitMemRange[NumberOfSpliteRange].Top  = (ProtectEndAddress + SIZE_2MB - 1) & ~(SIZE_2MB - 1);\r
           NumberOfSpliteRange++;\r
         }\r
+\r
         if (Low4KBPageSize != 0) {\r
           //\r
           // Add not 2MB-aligned range to be mapped by 4KB-page.\r
@@ -519,6 +538,7 @@ InitProtectedMemRange (
     DEBUG ((DEBUG_INFO, "mProtectionMemRange[%d].Base = %lx\n", Index, mProtectionMemRange[Index].Range.Base));\r
     DEBUG ((DEBUG_INFO, "mProtectionMemRange[%d].Top  = %lx\n", Index, mProtectionMemRange[Index].Range.Top));\r
   }\r
+\r
   for (Index = 0; Index < mSplitMemRangeCount; Index++) {\r
     DEBUG ((DEBUG_INFO, "mSplitMemRange[%d].Base = %lx\n", Index, mSplitMemRange[Index].Base));\r
     DEBUG ((DEBUG_INFO, "mSplitMemRange[%d].Top  = %lx\n", Index, mSplitMemRange[Index].Top));\r
@@ -534,64 +554,65 @@ InitPaging (
   VOID\r
   )\r
 {\r
-  UINT64                            Pml5Entry;\r
-  UINT64                            Pml4Entry;\r
-  UINT64                            *Pml5;\r
-  UINT64                            *Pml4;\r
-  UINT64                            *Pdpt;\r
-  UINT64                            *Pd;\r
-  UINT64                            *Pt;\r
-  UINTN                             Address;\r
-  UINTN                             Pml5Index;\r
-  UINTN                             Pml4Index;\r
-  UINTN                             PdptIndex;\r
-  UINTN                             PdIndex;\r
-  UINTN                             PtIndex;\r
-  UINTN                             NumberOfPdptEntries;\r
-  UINTN                             NumberOfPml4Entries;\r
-  UINTN                             NumberOfPml5Entries;\r
-  UINTN                             SizeOfMemorySpace;\r
-  BOOLEAN                           Nx;\r
-  IA32_CR4                          Cr4;\r
-  BOOLEAN                           Enable5LevelPaging;\r
-\r
-  Cr4.UintN = AsmReadCr4 ();\r
-  Enable5LevelPaging = (BOOLEAN) (Cr4.Bits.LA57 == 1);\r
+  UINT64    Pml5Entry;\r
+  UINT64    Pml4Entry;\r
+  UINT64    *Pml5;\r
+  UINT64    *Pml4;\r
+  UINT64    *Pdpt;\r
+  UINT64    *Pd;\r
+  UINT64    *Pt;\r
+  UINTN     Address;\r
+  UINTN     Pml5Index;\r
+  UINTN     Pml4Index;\r
+  UINTN     PdptIndex;\r
+  UINTN     PdIndex;\r
+  UINTN     PtIndex;\r
+  UINTN     NumberOfPdptEntries;\r
+  UINTN     NumberOfPml4Entries;\r
+  UINTN     NumberOfPml5Entries;\r
+  UINTN     SizeOfMemorySpace;\r
+  BOOLEAN   Nx;\r
+  IA32_CR4  Cr4;\r
+  BOOLEAN   Enable5LevelPaging;\r
+\r
+  Cr4.UintN          = AsmReadCr4 ();\r
+  Enable5LevelPaging = (BOOLEAN)(Cr4.Bits.LA57 == 1);\r
 \r
   if (sizeof (UINTN) == sizeof (UINT64)) {\r
     if (!Enable5LevelPaging) {\r
-      Pml5Entry = (UINTN) mSmmProfileCr3 | IA32_PG_P;\r
-      Pml5 = &Pml5Entry;\r
+      Pml5Entry = (UINTN)mSmmProfileCr3 | IA32_PG_P;\r
+      Pml5      = &Pml5Entry;\r
     } else {\r
-      Pml5 = (UINT64*) (UINTN) mSmmProfileCr3;\r
+      Pml5 = (UINT64 *)(UINTN)mSmmProfileCr3;\r
     }\r
+\r
     SizeOfMemorySpace = HighBitSet64 (gPhyMask) + 1;\r
     //\r
     // Calculate the table entries of PML4E and PDPTE.\r
     //\r
     NumberOfPml5Entries = 1;\r
     if (SizeOfMemorySpace > 48) {\r
-      NumberOfPml5Entries = (UINTN) LShiftU64 (1, SizeOfMemorySpace - 48);\r
-      SizeOfMemorySpace = 48;\r
+      NumberOfPml5Entries = (UINTN)LShiftU64 (1, SizeOfMemorySpace - 48);\r
+      SizeOfMemorySpace   = 48;\r
     }\r
 \r
     NumberOfPml4Entries = 1;\r
     if (SizeOfMemorySpace > 39) {\r
-      NumberOfPml4Entries = (UINTN) LShiftU64 (1, SizeOfMemorySpace - 39);\r
-      SizeOfMemorySpace = 39;\r
+      NumberOfPml4Entries = (UINTN)LShiftU64 (1, SizeOfMemorySpace - 39);\r
+      SizeOfMemorySpace   = 39;\r
     }\r
 \r
     NumberOfPdptEntries = 1;\r
     ASSERT (SizeOfMemorySpace > 30);\r
-    NumberOfPdptEntries = (UINTN) LShiftU64 (1, SizeOfMemorySpace - 30);\r
+    NumberOfPdptEntries = (UINTN)LShiftU64 (1, SizeOfMemorySpace - 30);\r
   } else {\r
-    Pml4Entry = (UINTN) mSmmProfileCr3 | IA32_PG_P;\r
-    Pml4 = &Pml4Entry;\r
-    Pml5Entry = (UINTN) Pml4 | IA32_PG_P;\r
-    Pml5 = &Pml5Entry;\r
-    NumberOfPml5Entries  = 1;\r
-    NumberOfPml4Entries  = 1;\r
-    NumberOfPdptEntries  = 4;\r
+    Pml4Entry           = (UINTN)mSmmProfileCr3 | IA32_PG_P;\r
+    Pml4                = &Pml4Entry;\r
+    Pml5Entry           = (UINTN)Pml4 | IA32_PG_P;\r
+    Pml5                = &Pml5Entry;\r
+    NumberOfPml5Entries = 1;\r
+    NumberOfPml4Entries = 1;\r
+    NumberOfPdptEntries = 4;\r
   }\r
 \r
   //\r
@@ -604,7 +625,8 @@ InitPaging (
       //\r
       continue;\r
     }\r
-    Pml4 = (UINT64 *) (UINTN) (Pml5[Pml5Index] & PHYSICAL_ADDRESS_MASK);\r
+\r
+    Pml4 = (UINT64 *)(UINTN)(Pml5[Pml5Index] & PHYSICAL_ADDRESS_MASK);\r
     for (Pml4Index = 0; Pml4Index < NumberOfPml4Entries; Pml4Index++) {\r
       if ((Pml4[Pml4Index] & IA32_PG_P) == 0) {\r
         //\r
@@ -612,6 +634,7 @@ InitPaging (
         //\r
         continue;\r
       }\r
+\r
       Pdpt = (UINT64 *)(UINTN)(Pml4[Pml4Index] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);\r
       for (PdptIndex = 0; PdptIndex < NumberOfPdptEntries; PdptIndex++, Pdpt++) {\r
         if ((*Pdpt & IA32_PG_P) == 0) {\r
@@ -620,16 +643,19 @@ InitPaging (
           //\r
           continue;\r
         }\r
+\r
         if ((*Pdpt & IA32_PG_PS) != 0) {\r
           //\r
           // This is 1G entry, skip it\r
           //\r
           continue;\r
         }\r
+\r
         Pd = (UINT64 *)(UINTN)(*Pdpt & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);\r
         if (Pd == 0) {\r
           continue;\r
         }\r
+\r
         for (PdIndex = 0; PdIndex < SIZE_4KB / sizeof (*Pd); PdIndex++, Pd++) {\r
           if ((*Pd & IA32_PG_P) == 0) {\r
             //\r
@@ -637,13 +663,14 @@ InitPaging (
             //\r
             continue;\r
           }\r
-          Address = (UINTN) LShiftU64 (\r
-                              LShiftU64 (\r
-                                LShiftU64 ((Pml5Index << 9) + Pml4Index, 9) + PdptIndex,\r
-                                9\r
-                                ) + PdIndex,\r
-                                21\r
-                              );\r
+\r
+          Address = (UINTN)LShiftU64 (\r
+                             LShiftU64 (\r
+                               LShiftU64 ((Pml5Index << 9) + Pml4Index, 9) + PdptIndex,\r
+                               9\r
+                               ) + PdIndex,\r
+                             21\r
+                             );\r
 \r
           //\r
           // If it is 2M page, check IsAddressSplit()\r
@@ -658,9 +685,10 @@ InitPaging (
             ASSERT (Pt != NULL);\r
 \r
             // Split it\r
-            for (PtIndex = 0; PtIndex < SIZE_4KB / sizeof(*Pt); PtIndex++) {\r
+            for (PtIndex = 0; PtIndex < SIZE_4KB / sizeof (*Pt); PtIndex++) {\r
               Pt[PtIndex] = Address + ((PtIndex << 12) | mAddressEncMask | PAGE_ATTRIBUTE_BITS);\r
             } // end for PT\r
+\r
             *Pd = (UINT64)(UINTN)Pt | mAddressEncMask | PAGE_ATTRIBUTE_BITS;\r
           } // end if IsAddressSplit\r
         } // end for PD\r
@@ -679,7 +707,8 @@ InitPaging (
       //\r
       continue;\r
     }\r
-    Pml4 = (UINT64 *) (UINTN) (Pml5[Pml5Index] & PHYSICAL_ADDRESS_MASK);\r
+\r
+    Pml4 = (UINT64 *)(UINTN)(Pml5[Pml5Index] & PHYSICAL_ADDRESS_MASK);\r
     for (Pml4Index = 0; Pml4Index < NumberOfPml4Entries; Pml4Index++) {\r
       if ((Pml4[Pml4Index] & IA32_PG_P) == 0) {\r
         //\r
@@ -687,6 +716,7 @@ InitPaging (
         //\r
         continue;\r
       }\r
+\r
       Pdpt = (UINT64 *)(UINTN)(Pml4[Pml4Index] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);\r
       for (PdptIndex = 0; PdptIndex < NumberOfPdptEntries; PdptIndex++, Pdpt++) {\r
         if ((*Pdpt & IA32_PG_P) == 0) {\r
@@ -695,6 +725,7 @@ InitPaging (
           //\r
           continue;\r
         }\r
+\r
         if ((*Pdpt & IA32_PG_PS) != 0) {\r
           //\r
           // This is 1G entry, set NX bit and skip it\r
@@ -702,12 +733,15 @@ InitPaging (
           if (mXdSupported) {\r
             *Pdpt = *Pdpt | IA32_PG_NX;\r
           }\r
+\r
           continue;\r
         }\r
+\r
         Pd = (UINT64 *)(UINTN)(*Pdpt & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);\r
         if (Pd == 0) {\r
           continue;\r
         }\r
+\r
         for (PdIndex = 0; PdIndex < SIZE_4KB / sizeof (*Pd); PdIndex++, Pd++) {\r
           if ((*Pd & IA32_PG_P) == 0) {\r
             //\r
@@ -715,13 +749,14 @@ InitPaging (
             //\r
             continue;\r
           }\r
-          Address = (UINTN) LShiftU64 (\r
-                              LShiftU64 (\r
-                                LShiftU64 ((Pml5Index << 9) + Pml4Index, 9) + PdptIndex,\r
-                                9\r
-                                ) + PdIndex,\r
-                                21\r
-                              );\r
+\r
+          Address = (UINTN)LShiftU64 (\r
+                             LShiftU64 (\r
+                               LShiftU64 ((Pml5Index << 9) + Pml4Index, 9) + PdptIndex,\r
+                               9\r
+                               ) + PdIndex,\r
+                             21\r
+                             );\r
 \r
           if ((*Pd & IA32_PG_PS) != 0) {\r
             // 2MB page\r
@@ -732,6 +767,7 @@ InitPaging (
               //\r
               *Pd = *Pd & (INTN)(INT32)(~PAGE_ATTRIBUTE_BITS);\r
             }\r
+\r
             if (Nx && mXdSupported) {\r
               *Pd = *Pd | IA32_PG_NX;\r
             }\r
@@ -741,13 +777,16 @@ InitPaging (
             if (Pt == 0) {\r
               continue;\r
             }\r
-            for (PtIndex = 0; PtIndex < SIZE_4KB / sizeof(*Pt); PtIndex++, Pt++) {\r
+\r
+            for (PtIndex = 0; PtIndex < SIZE_4KB / sizeof (*Pt); PtIndex++, Pt++) {\r
               if (!IsAddressValid (Address, &Nx)) {\r
                 *Pt = *Pt & (INTN)(INT32)(~PAGE_ATTRIBUTE_BITS);\r
               }\r
+\r
               if (Nx && mXdSupported) {\r
                 *Pt = *Pt | IA32_PG_NX;\r
               }\r
+\r
               Address += SIZE_4KB;\r
             } // end for PT\r
           } // end if PS\r
@@ -766,7 +805,7 @@ InitPaging (
   //\r
   mXdEnabled = TRUE;\r
 \r
-  return ;\r
+  return;\r
 }\r
 \r
 /**\r
@@ -778,11 +817,11 @@ GetSmiCommandPort (
   VOID\r
   )\r
 {\r
-  EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE *Fadt;\r
+  EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE  *Fadt;\r
 \r
-  Fadt = (EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE *) EfiLocateFirstAcpiTable (\r
-                                                         EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE\r
-                                                         );\r
+  Fadt = (EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE *)EfiLocateFirstAcpiTable (\r
+                                                        EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE\r
+                                                        );\r
   ASSERT (Fadt != NULL);\r
 \r
   mSmiCommandPort = Fadt->SmiCmd;\r
@@ -830,7 +869,7 @@ InitSmmProfileCallBack (
          SMM_PROFILE_NAME,\r
          &gEfiCallerIdGuid,\r
          EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS,\r
-         sizeof(mSmmProfileBase),\r
+         sizeof (mSmmProfileBase),\r
          &mSmmProfileBase\r
          );\r
 \r
@@ -856,20 +895,22 @@ InitSmmProfileInternal (
   VOID\r
   )\r
 {\r
-  EFI_STATUS                 Status;\r
-  EFI_PHYSICAL_ADDRESS       Base;\r
-  VOID                       *Registration;\r
-  UINTN                      Index;\r
-  UINTN                      MsrDsAreaSizePerCpu;\r
-  UINTN                      TotalSize;\r
+  EFI_STATUS            Status;\r
+  EFI_PHYSICAL_ADDRESS  Base;\r
+  VOID                  *Registration;\r
+  UINTN                 Index;\r
+  UINTN                 MsrDsAreaSizePerCpu;\r
+  UINTN                 TotalSize;\r
 \r
   mPFEntryCount = (UINTN *)AllocateZeroPool (sizeof (UINTN) * mMaxNumberOfCpus);\r
   ASSERT (mPFEntryCount != NULL);\r
-  mLastPFEntryValue = (UINT64  (*)[MAX_PF_ENTRY_COUNT])AllocateZeroPool (\r
-                                                         sizeof (mLastPFEntryValue[0]) * mMaxNumberOfCpus);\r
+  mLastPFEntryValue = (UINT64 (*)[MAX_PF_ENTRY_COUNT])AllocateZeroPool (\r
+                                                        sizeof (mLastPFEntryValue[0]) * mMaxNumberOfCpus\r
+                                                        );\r
   ASSERT (mLastPFEntryValue != NULL);\r
   mLastPFEntryPointer = (UINT64 *(*)[MAX_PF_ENTRY_COUNT])AllocateZeroPool (\r
-                                                           sizeof (mLastPFEntryPointer[0]) * mMaxNumberOfCpus);\r
+                                                           sizeof (mLastPFEntryPointer[0]) * mMaxNumberOfCpus\r
+                                                           );\r
   ASSERT (mLastPFEntryPointer != NULL);\r
 \r
   //\r
@@ -885,7 +926,7 @@ InitSmmProfileInternal (
     TotalSize = mSmmProfileSize;\r
   }\r
 \r
-  Base = 0xFFFFFFFF;\r
+  Base   = 0xFFFFFFFF;\r
   Status = gBS->AllocatePages (\r
                   AllocateMaxAddress,\r
                   EfiReservedMemoryType,\r
@@ -900,8 +941,8 @@ InitSmmProfileInternal (
   // Initialize SMM profile data header.\r
   //\r
   mSmmProfileBase->HeaderSize     = sizeof (SMM_PROFILE_HEADER);\r
-  mSmmProfileBase->MaxDataEntries = (UINT64)((mSmmProfileSize - sizeof(SMM_PROFILE_HEADER)) / sizeof (SMM_PROFILE_ENTRY));\r
-  mSmmProfileBase->MaxDataSize    = MultU64x64 (mSmmProfileBase->MaxDataEntries, sizeof(SMM_PROFILE_ENTRY));\r
+  mSmmProfileBase->MaxDataEntries = (UINT64)((mSmmProfileSize - sizeof (SMM_PROFILE_HEADER)) / sizeof (SMM_PROFILE_ENTRY));\r
+  mSmmProfileBase->MaxDataSize    = MultU64x64 (mSmmProfileBase->MaxDataEntries, sizeof (SMM_PROFILE_ENTRY));\r
   mSmmProfileBase->CurDataEntries = 0;\r
   mSmmProfileBase->CurDataSize    = 0;\r
   mSmmProfileBase->TsegStart      = mCpuHotPlugData.SmrrBase;\r
@@ -917,22 +958,22 @@ InitSmmProfileInternal (
     mMsrPEBSRecord = (PEBS_RECORD **)AllocateZeroPool (sizeof (PEBS_RECORD *) * mMaxNumberOfCpus);\r
     ASSERT (mMsrPEBSRecord != NULL);\r
 \r
-    mMsrDsAreaBase  = (MSR_DS_AREA_STRUCT *)((UINTN)Base + mSmmProfileSize);\r
+    mMsrDsAreaBase      = (MSR_DS_AREA_STRUCT *)((UINTN)Base + mSmmProfileSize);\r
     MsrDsAreaSizePerCpu = mMsrDsAreaSize / mMaxNumberOfCpus;\r
-    mBTSRecordNumber    = (MsrDsAreaSizePerCpu - sizeof(PEBS_RECORD) * PEBS_RECORD_NUMBER - sizeof(MSR_DS_AREA_STRUCT)) / sizeof(BRANCH_TRACE_RECORD);\r
+    mBTSRecordNumber    = (MsrDsAreaSizePerCpu - sizeof (PEBS_RECORD) * PEBS_RECORD_NUMBER - sizeof (MSR_DS_AREA_STRUCT)) / sizeof (BRANCH_TRACE_RECORD);\r
     for (Index = 0; Index < mMaxNumberOfCpus; Index++) {\r
       mMsrDsArea[Index]     = (MSR_DS_AREA_STRUCT *)((UINTN)mMsrDsAreaBase + MsrDsAreaSizePerCpu * Index);\r
-      mMsrBTSRecord[Index]  = (BRANCH_TRACE_RECORD *)((UINTN)mMsrDsArea[Index] + sizeof(MSR_DS_AREA_STRUCT));\r
-      mMsrPEBSRecord[Index] = (PEBS_RECORD *)((UINTN)mMsrDsArea[Index] + MsrDsAreaSizePerCpu - sizeof(PEBS_RECORD) * PEBS_RECORD_NUMBER);\r
+      mMsrBTSRecord[Index]  = (BRANCH_TRACE_RECORD *)((UINTN)mMsrDsArea[Index] + sizeof (MSR_DS_AREA_STRUCT));\r
+      mMsrPEBSRecord[Index] = (PEBS_RECORD *)((UINTN)mMsrDsArea[Index] + MsrDsAreaSizePerCpu - sizeof (PEBS_RECORD) * PEBS_RECORD_NUMBER);\r
 \r
-      mMsrDsArea[Index]->BTSBufferBase          = (UINTN)mMsrBTSRecord[Index];\r
-      mMsrDsArea[Index]->BTSIndex               = mMsrDsArea[Index]->BTSBufferBase;\r
-      mMsrDsArea[Index]->BTSAbsoluteMaximum     = mMsrDsArea[Index]->BTSBufferBase + mBTSRecordNumber * sizeof(BRANCH_TRACE_RECORD) + 1;\r
-      mMsrDsArea[Index]->BTSInterruptThreshold  = mMsrDsArea[Index]->BTSAbsoluteMaximum + 1;\r
+      mMsrDsArea[Index]->BTSBufferBase         = (UINTN)mMsrBTSRecord[Index];\r
+      mMsrDsArea[Index]->BTSIndex              = mMsrDsArea[Index]->BTSBufferBase;\r
+      mMsrDsArea[Index]->BTSAbsoluteMaximum    = mMsrDsArea[Index]->BTSBufferBase + mBTSRecordNumber * sizeof (BRANCH_TRACE_RECORD) + 1;\r
+      mMsrDsArea[Index]->BTSInterruptThreshold = mMsrDsArea[Index]->BTSAbsoluteMaximum + 1;\r
 \r
       mMsrDsArea[Index]->PEBSBufferBase         = (UINTN)mMsrPEBSRecord[Index];\r
       mMsrDsArea[Index]->PEBSIndex              = mMsrDsArea[Index]->PEBSBufferBase;\r
-      mMsrDsArea[Index]->PEBSAbsoluteMaximum    = mMsrDsArea[Index]->PEBSBufferBase + PEBS_RECORD_NUMBER * sizeof(PEBS_RECORD) + 1;\r
+      mMsrDsArea[Index]->PEBSAbsoluteMaximum    = mMsrDsArea[Index]->PEBSBufferBase + PEBS_RECORD_NUMBER * sizeof (PEBS_RECORD) + 1;\r
       mMsrDsArea[Index]->PEBSInterruptThreshold = mMsrDsArea[Index]->PEBSAbsoluteMaximum + 1;\r
     }\r
   }\r
@@ -967,7 +1008,7 @@ InitSmmProfileInternal (
                     );\r
   ASSERT_EFI_ERROR (Status);\r
 \r
-  return ;\r
+  return;\r
 }\r
 \r
 /**\r
@@ -1056,12 +1097,13 @@ ActivateSingleStepDB (
   VOID\r
   )\r
 {\r
-  UINTN    Dr6;\r
+  UINTN  Dr6;\r
 \r
   Dr6 = AsmReadDr6 ();\r
   if ((Dr6 & DR6_SINGLE_STEP) != 0) {\r
     return;\r
   }\r
+\r
   Dr6 |= DR6_SINGLE_STEP;\r
   AsmWriteDr6 (Dr6);\r
 }\r
@@ -1079,8 +1121,9 @@ ActivateLBR (
 \r
   DebugCtl = AsmReadMsr64 (MSR_DEBUG_CTL);\r
   if ((DebugCtl & MSR_DEBUG_CTL_LBR) != 0) {\r
-    return ;\r
+    return;\r
   }\r
+\r
   DebugCtl |= MSR_DEBUG_CTL_LBR;\r
   AsmWriteMsr64 (MSR_DEBUG_CTL, DebugCtl);\r
 }\r
@@ -1093,14 +1136,14 @@ ActivateLBR (
 **/\r
 VOID\r
 ActivateBTS (\r
-  IN      UINTN                     CpuIndex\r
+  IN      UINTN  CpuIndex\r
   )\r
 {\r
   UINT64  DebugCtl;\r
 \r
   DebugCtl = AsmReadMsr64 (MSR_DEBUG_CTL);\r
   if ((DebugCtl & MSR_DEBUG_CTL_BTS) != 0) {\r
-    return ;\r
+    return;\r
   }\r
 \r
   AsmWriteMsr64 (MSR_DS_AREA, (UINT64)(UINTN)mMsrDsArea[CpuIndex]);\r
@@ -1131,7 +1174,7 @@ SmmProfileRecordSmiNum (
 **/\r
 VOID\r
 ActivateSmmProfile (\r
-  IN UINTN CpuIndex\r
+  IN UINTN  CpuIndex\r
   )\r
 {\r
   //\r
@@ -1173,7 +1216,8 @@ InitSmmProfile (
   //\r
   if (!FeaturePcdGet (PcdCpuSmmProfileEnable) &&\r
       !HEAP_GUARD_NONSTOP_MODE &&\r
-      !NULL_DETECTION_NONSTOP_MODE) {\r
+      !NULL_DETECTION_NONSTOP_MODE)\r
+  {\r
     return;\r
   }\r
 \r
@@ -1206,19 +1250,19 @@ InitSmmProfile (
 **/\r
 VOID\r
 RestorePageTableBelow4G (\r
-  UINT64        *PageTable,\r
-  UINT64        PFAddress,\r
-  UINTN         CpuIndex,\r
-  UINTN         ErrorCode\r
+  UINT64  *PageTable,\r
+  UINT64  PFAddress,\r
+  UINTN   CpuIndex,\r
+  UINTN   ErrorCode\r
   )\r
 {\r
-  UINTN         PTIndex;\r
-  UINTN         PFIndex;\r
-  IA32_CR4      Cr4;\r
-  BOOLEAN       Enable5LevelPaging;\r
+  UINTN     PTIndex;\r
+  UINTN     PFIndex;\r
+  IA32_CR4  Cr4;\r
+  BOOLEAN   Enable5LevelPaging;\r
 \r
-  Cr4.UintN = AsmReadCr4 ();\r
-  Enable5LevelPaging = (BOOLEAN) (Cr4.Bits.LA57 == 1);\r
+  Cr4.UintN          = AsmReadCr4 ();\r
+  Enable5LevelPaging = (BOOLEAN)(Cr4.Bits.LA57 == 1);\r
 \r
   //\r
   // PML5\r
@@ -1226,16 +1270,16 @@ RestorePageTableBelow4G (
   if (Enable5LevelPaging) {\r
     PTIndex = (UINTN)BitFieldRead64 (PFAddress, 48, 56);\r
     ASSERT (PageTable[PTIndex] != 0);\r
-    PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & PHYSICAL_ADDRESS_MASK);\r
+    PageTable = (UINT64 *)(UINTN)(PageTable[PTIndex] & PHYSICAL_ADDRESS_MASK);\r
   }\r
 \r
   //\r
   // PML4\r
   //\r
-  if (sizeof(UINT64) == sizeof(UINTN)) {\r
+  if (sizeof (UINT64) == sizeof (UINTN)) {\r
     PTIndex = (UINTN)BitFieldRead64 (PFAddress, 39, 47);\r
     ASSERT (PageTable[PTIndex] != 0);\r
-    PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & PHYSICAL_ADDRESS_MASK);\r
+    PageTable = (UINT64 *)(UINTN)(PageTable[PTIndex] & PHYSICAL_ADDRESS_MASK);\r
   }\r
 \r
   //\r
@@ -1243,7 +1287,7 @@ RestorePageTableBelow4G (
   //\r
   PTIndex = (UINTN)BitFieldRead64 (PFAddress, 30, 38);\r
   ASSERT (PageTable[PTIndex] != 0);\r
-  PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & PHYSICAL_ADDRESS_MASK);\r
+  PageTable = (UINT64 *)(UINTN)(PageTable[PTIndex] & PHYSICAL_ADDRESS_MASK);\r
 \r
   //\r
   // PD\r
@@ -1261,7 +1305,7 @@ RestorePageTableBelow4G (
     //\r
     ASSERT (mPFEntryCount[CpuIndex] < MAX_PF_ENTRY_COUNT);\r
     if (mPFEntryCount[CpuIndex] < MAX_PF_ENTRY_COUNT) {\r
-      PFIndex = mPFEntryCount[CpuIndex];\r
+      PFIndex                                = mPFEntryCount[CpuIndex];\r
       mLastPFEntryValue[CpuIndex][PFIndex]   = PageTable[PTIndex];\r
       mLastPFEntryPointer[CpuIndex][PFIndex] = &PageTable[PTIndex];\r
       mPFEntryCount[CpuIndex]++;\r
@@ -1270,7 +1314,7 @@ RestorePageTableBelow4G (
     //\r
     // Set new entry\r
     //\r
-    PageTable[PTIndex] = (PFAddress & ~((1ull << 21) - 1));\r
+    PageTable[PTIndex]  = (PFAddress & ~((1ull << 21) - 1));\r
     PageTable[PTIndex] |= (UINT64)IA32_PG_PS;\r
     PageTable[PTIndex] |= (UINT64)PAGE_ATTRIBUTE_BITS;\r
     if ((ErrorCode & IA32_PF_EC_ID) != 0) {\r
@@ -1281,7 +1325,7 @@ RestorePageTableBelow4G (
     // Small page\r
     //\r
     ASSERT (PageTable[PTIndex] != 0);\r
-    PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & PHYSICAL_ADDRESS_MASK);\r
+    PageTable = (UINT64 *)(UINTN)(PageTable[PTIndex] & PHYSICAL_ADDRESS_MASK);\r
 \r
     //\r
     // 4K PTE\r
@@ -1295,7 +1339,7 @@ RestorePageTableBelow4G (
     //\r
     ASSERT (mPFEntryCount[CpuIndex] < MAX_PF_ENTRY_COUNT);\r
     if (mPFEntryCount[CpuIndex] < MAX_PF_ENTRY_COUNT) {\r
-      PFIndex = mPFEntryCount[CpuIndex];\r
+      PFIndex                                = mPFEntryCount[CpuIndex];\r
       mLastPFEntryValue[CpuIndex][PFIndex]   = PageTable[PTIndex];\r
       mLastPFEntryPointer[CpuIndex][PFIndex] = &PageTable[PTIndex];\r
       mPFEntryCount[CpuIndex]++;\r
@@ -1304,7 +1348,7 @@ RestorePageTableBelow4G (
     //\r
     // Set new entry\r
     //\r
-    PageTable[PTIndex] = (PFAddress & ~((1ull << 12) - 1));\r
+    PageTable[PTIndex]  = (PFAddress & ~((1ull << 12) - 1));\r
     PageTable[PTIndex] |= (UINT64)PAGE_ATTRIBUTE_BITS;\r
     if ((ErrorCode & IA32_PF_EC_ID) != 0) {\r
       PageTable[PTIndex] &= ~IA32_PG_NX;\r
@@ -1320,18 +1364,18 @@ RestorePageTableBelow4G (
 **/\r
 VOID\r
 GuardPagePFHandler (\r
-  UINTN ErrorCode\r
+  UINTN  ErrorCode\r
   )\r
 {\r
-  UINT64                *PageTable;\r
-  UINT64                PFAddress;\r
-  UINT64                RestoreAddress;\r
-  UINTN                 RestorePageNumber;\r
-  UINTN                 CpuIndex;\r
+  UINT64  *PageTable;\r
+  UINT64  PFAddress;\r
+  UINT64  RestoreAddress;\r
+  UINTN   RestorePageNumber;\r
+  UINTN   CpuIndex;\r
 \r
-  PageTable         = (UINT64 *)AsmReadCr3 ();\r
-  PFAddress         = AsmReadCr2 ();\r
-  CpuIndex          = GetCpuIndex ();\r
+  PageTable = (UINT64 *)AsmReadCr3 ();\r
+  PFAddress = AsmReadCr2 ();\r
+  CpuIndex  = GetCpuIndex ();\r
 \r
   //\r
   // Memory operation cross pages, like "rep mov" instruction, will cause\r
@@ -1339,7 +1383,7 @@ GuardPagePFHandler (
   // that current page and the page followed are both in PRESENT state.\r
   //\r
   RestorePageNumber = 2;\r
-  RestoreAddress = PFAddress;\r
+  RestoreAddress    = PFAddress;\r
   while (RestorePageNumber > 0) {\r
     RestorePageTableBelow4G (PageTable, RestoreAddress, CpuIndex, ErrorCode);\r
     RestoreAddress += EFI_PAGE_SIZE;\r
@@ -1361,25 +1405,25 @@ GuardPagePFHandler (
 **/\r
 VOID\r
 SmmProfilePFHandler (\r
-  UINTN Rip,\r
-  UINTN ErrorCode\r
+  UINTN  Rip,\r
+  UINTN  ErrorCode\r
   )\r
 {\r
-  UINT64                *PageTable;\r
-  UINT64                PFAddress;\r
-  UINT64                RestoreAddress;\r
-  UINTN                 RestorePageNumber;\r
-  UINTN                 CpuIndex;\r
-  UINTN                 Index;\r
-  UINT64                InstructionAddress;\r
-  UINTN                 MaxEntryNumber;\r
-  UINTN                 CurrentEntryNumber;\r
-  BOOLEAN               IsValidPFAddress;\r
-  SMM_PROFILE_ENTRY     *SmmProfileEntry;\r
-  UINT64                SmiCommand;\r
-  EFI_STATUS            Status;\r
-  UINT8                 SoftSmiValue;\r
-  EFI_SMM_SAVE_STATE_IO_INFO    IoInfo;\r
+  UINT64                      *PageTable;\r
+  UINT64                      PFAddress;\r
+  UINT64                      RestoreAddress;\r
+  UINTN                       RestorePageNumber;\r
+  UINTN                       CpuIndex;\r
+  UINTN                       Index;\r
+  UINT64                      InstructionAddress;\r
+  UINTN                       MaxEntryNumber;\r
+  UINTN                       CurrentEntryNumber;\r
+  BOOLEAN                     IsValidPFAddress;\r
+  SMM_PROFILE_ENTRY           *SmmProfileEntry;\r
+  UINT64                      SmiCommand;\r
+  EFI_STATUS                  Status;\r
+  UINT8                       SoftSmiValue;\r
+  EFI_SMM_SAVE_STATE_IO_INFO  IoInfo;\r
 \r
   if (!mSmmProfileStart) {\r
     //\r
@@ -1393,10 +1437,10 @@ SmmProfilePFHandler (
     DisableBTS ();\r
   }\r
 \r
-  IsValidPFAddress  = FALSE;\r
-  PageTable         = (UINT64 *)AsmReadCr3 ();\r
-  PFAddress         = AsmReadCr2 ();\r
-  CpuIndex          = GetCpuIndex ();\r
+  IsValidPFAddress = FALSE;\r
+  PageTable        = (UINT64 *)AsmReadCr3 ();\r
+  PFAddress        = AsmReadCr2 ();\r
+  CpuIndex         = GetCpuIndex ();\r
 \r
   //\r
   // Memory operation cross pages, like "rep mov" instruction, will cause\r
@@ -1404,20 +1448,21 @@ SmmProfilePFHandler (
   // that current page and the page followed are both in PRESENT state.\r
   //\r
   RestorePageNumber = 2;\r
-  RestoreAddress = PFAddress;\r
+  RestoreAddress    = PFAddress;\r
   while (RestorePageNumber > 0) {\r
     if (RestoreAddress <= 0xFFFFFFFF) {\r
       RestorePageTableBelow4G (PageTable, RestoreAddress, CpuIndex, ErrorCode);\r
     } else {\r
       RestorePageTableAbove4G (PageTable, RestoreAddress, CpuIndex, ErrorCode, &IsValidPFAddress);\r
     }\r
+\r
     RestoreAddress += EFI_PAGE_SIZE;\r
     RestorePageNumber--;\r
   }\r
 \r
   if (!IsValidPFAddress) {\r
     InstructionAddress = Rip;\r
-    if ((ErrorCode & IA32_PF_EC_ID) != 0 && (mBtsSupported)) {\r
+    if (((ErrorCode & IA32_PF_EC_ID) != 0) && (mBtsSupported)) {\r
       //\r
       // If it is instruction fetch failure, get the correct IP from BTS.\r
       //\r
@@ -1434,18 +1479,19 @@ SmmProfilePFHandler (
     //\r
     // Indicate it is not software SMI\r
     //\r
-    SmiCommand    = 0xFFFFFFFFFFFFFFFFULL;\r
+    SmiCommand = 0xFFFFFFFFFFFFFFFFULL;\r
     for (Index = 0; Index < gSmst->NumberOfCpus; Index++) {\r
-      Status = SmmReadSaveState(&mSmmCpu, sizeof(IoInfo), EFI_SMM_SAVE_STATE_REGISTER_IO, Index, &IoInfo);\r
+      Status = SmmReadSaveState (&mSmmCpu, sizeof (IoInfo), EFI_SMM_SAVE_STATE_REGISTER_IO, Index, &IoInfo);\r
       if (EFI_ERROR (Status)) {\r
         continue;\r
       }\r
+\r
       if (IoInfo.IoPort == mSmiCommandPort) {\r
         //\r
         // A software SMI triggered by SMI command port has been found, get SmiCommand from SMI command port.\r
         //\r
         SoftSmiValue = IoRead8 (mSmiCommandPort);\r
-        SmiCommand = (UINT64)SoftSmiValue;\r
+        SmiCommand   = (UINT64)SoftSmiValue;\r
         break;\r
       }\r
     }\r
@@ -1454,24 +1500,27 @@ SmmProfilePFHandler (
     //\r
     // Check if there is already a same entry in profile data.\r
     //\r
-    for (Index = 0; Index < (UINTN) mSmmProfileBase->CurDataEntries; Index++) {\r
+    for (Index = 0; Index < (UINTN)mSmmProfileBase->CurDataEntries; Index++) {\r
       if ((SmmProfileEntry[Index].ErrorCode   == (UINT64)ErrorCode) &&\r
           (SmmProfileEntry[Index].Address     == PFAddress) &&\r
           (SmmProfileEntry[Index].CpuNum      == (UINT64)CpuIndex) &&\r
           (SmmProfileEntry[Index].Instruction == InstructionAddress) &&\r
-          (SmmProfileEntry[Index].SmiCmd      == SmiCommand)) {\r
+          (SmmProfileEntry[Index].SmiCmd      == SmiCommand))\r
+      {\r
         //\r
         // Same record exist, need not save again.\r
         //\r
         break;\r
       }\r
     }\r
+\r
     if (Index == mSmmProfileBase->CurDataEntries) {\r
-      CurrentEntryNumber = (UINTN) mSmmProfileBase->CurDataEntries;\r
-      MaxEntryNumber     = (UINTN) mSmmProfileBase->MaxDataEntries;\r
+      CurrentEntryNumber = (UINTN)mSmmProfileBase->CurDataEntries;\r
+      MaxEntryNumber     = (UINTN)mSmmProfileBase->MaxDataEntries;\r
       if (FeaturePcdGet (PcdCpuSmmProfileRingBuffer)) {\r
         CurrentEntryNumber = CurrentEntryNumber % MaxEntryNumber;\r
       }\r
+\r
       if (CurrentEntryNumber < MaxEntryNumber) {\r
         //\r
         // Log the new entry\r
@@ -1491,6 +1540,7 @@ SmmProfilePFHandler (
       }\r
     }\r
   }\r
+\r
   //\r
   // Flush TLB\r
   //\r
@@ -1511,7 +1561,7 @@ InitIdtr (
   VOID\r
   )\r
 {\r
-  EFI_STATUS                        Status;\r
+  EFI_STATUS  Status;\r
 \r
   Status = SmmRegisterExceptionHandler (&mSmmCpuService, EXCEPT_IA32_DEBUG, DebugExceptionHandler);\r
   ASSERT_EFI_ERROR (Status);\r

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.h b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.h
index 484d81eb00e87794795338aa49448164bebbaadc..1a82ac05ce92192940ad5b00a53aea0c5aa8bfb2 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.h
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.h
@@ -23,7 +23,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
 **/\r
 VOID\r
 ActivateSmmProfile (\r
-  IN UINTN CpuIndex\r
+  IN UINTN  CpuIndex\r
   );\r
 \r
 /**\r
@@ -55,8 +55,8 @@ SmmProfileRecordSmiNum (
 **/\r
 VOID\r
 SmmProfilePFHandler (\r
-  UINTN Rip,\r
-  UINTN ErrorCode\r
+  UINTN  Rip,\r
+  UINTN  ErrorCode\r
   );\r
 \r
 /**\r
@@ -80,7 +80,6 @@ PageFaultIdtHandlerSmmProfile (
   VOID\r
   );\r
 \r
-\r
 /**\r
   Check if feature is supported by a processor.\r
 \r
@@ -116,20 +115,20 @@ GetCpuIndex (
 **/\r
 VOID\r
 GuardPagePFHandler (\r
-  UINTN ErrorCode\r
+  UINTN  ErrorCode\r
   );\r
 \r
 //\r
 // The flag indicates if execute-disable is supported by processor.\r
 //\r
-extern BOOLEAN    mXdSupported;\r
+extern BOOLEAN  mXdSupported;\r
 //\r
 // The flag indicates if execute-disable is enabled on processor.\r
 //\r
-extern BOOLEAN    mXdEnabled;\r
+extern BOOLEAN  mXdEnabled;\r
 //\r
 // The flag indicates if #DB will be setup in #PF handler.\r
 //\r
-extern BOOLEAN    mSetupDebugTrap;\r
+extern BOOLEAN  mSetupDebugTrap;\r
 \r
 #endif // _SMM_PROFILE_H_\r

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfileInternal.h b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfileInternal.h
index 993360a8a8c150739fe21b06ea4940045936639d..0e60509e20a8438fd74900630b0cdfb7da4d7d19 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfileInternal.h
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfileInternal.h
@@ -22,41 +22,41 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
 //\r
 // Configure the SMM_PROFILE DTS region size\r
 //\r
-#define SMM_PROFILE_DTS_SIZE       (4 * 1024 * 1024) // 4M\r
+#define SMM_PROFILE_DTS_SIZE  (4 * 1024 * 1024)      // 4M\r
 \r
-#define MAX_PF_PAGE_COUNT           0x2\r
+#define MAX_PF_PAGE_COUNT  0x2\r
 \r
-#define PEBS_RECORD_NUMBER          0x2\r
+#define PEBS_RECORD_NUMBER  0x2\r
 \r
-#define MAX_PF_ENTRY_COUNT          10\r
+#define MAX_PF_ENTRY_COUNT  10\r
 \r
 //\r
 // This MACRO just enable unit test for the profile\r
 // Please disable it.\r
 //\r
 \r
-#define IA32_PF_EC_ID               (1u << 4)\r
+#define IA32_PF_EC_ID  (1u << 4)\r
 \r
-#define SMM_PROFILE_NAME            L"SmmProfileData"\r
+#define SMM_PROFILE_NAME  L"SmmProfileData"\r
 \r
 //\r
 // CPU generic definition\r
 //\r
-#define   CPUID1_EDX_XD_SUPPORT      0x100000\r
-#define   MSR_EFER                   0xc0000080\r
-#define   MSR_EFER_XD                0x800\r
+#define   CPUID1_EDX_XD_SUPPORT  0x100000\r
+#define   MSR_EFER               0xc0000080\r
+#define   MSR_EFER_XD            0x800\r
 \r
-#define   CPUID1_EDX_BTS_AVAILABLE   0x200000\r
+#define   CPUID1_EDX_BTS_AVAILABLE  0x200000\r
 \r
-#define   DR6_SINGLE_STEP            0x4000\r
-#define   RFLAG_TF                   0x100\r
+#define   DR6_SINGLE_STEP  0x4000\r
+#define   RFLAG_TF         0x100\r
 \r
-#define MSR_DEBUG_CTL                0x1D9\r
-#define   MSR_DEBUG_CTL_LBR          0x1\r
-#define   MSR_DEBUG_CTL_TR           0x40\r
-#define   MSR_DEBUG_CTL_BTS          0x80\r
-#define   MSR_DEBUG_CTL_BTINT        0x100\r
-#define MSR_DS_AREA                  0x600\r
+#define MSR_DEBUG_CTL          0x1D9\r
+#define   MSR_DEBUG_CTL_LBR    0x1\r
+#define   MSR_DEBUG_CTL_TR     0x40\r
+#define   MSR_DEBUG_CTL_BTS    0x80\r
+#define   MSR_DEBUG_CTL_BTINT  0x100\r
+#define MSR_DS_AREA            0x600\r
 \r
 #define HEAP_GUARD_NONSTOP_MODE      \\r
         ((PcdGet8 (PcdHeapGuardPropertyMask) & (BIT6|BIT3|BIT2)) > BIT6)\r
@@ -65,45 +65,45 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
         ((PcdGet8 (PcdNullPointerDetectionPropertyMask) & (BIT6|BIT1)) > BIT6)\r
 \r
 typedef struct {\r
-  EFI_PHYSICAL_ADDRESS   Base;\r
-  EFI_PHYSICAL_ADDRESS   Top;\r
+  EFI_PHYSICAL_ADDRESS    Base;\r
+  EFI_PHYSICAL_ADDRESS    Top;\r
 } MEMORY_RANGE;\r
 \r
 typedef struct {\r
-  MEMORY_RANGE   Range;\r
-  BOOLEAN        Present;\r
-  BOOLEAN        Nx;\r
+  MEMORY_RANGE    Range;\r
+  BOOLEAN         Present;\r
+  BOOLEAN         Nx;\r
 } MEMORY_PROTECTION_RANGE;\r
 \r
 typedef struct {\r
-  UINT64  HeaderSize;\r
-  UINT64  MaxDataEntries;\r
-  UINT64  MaxDataSize;\r
-  UINT64  CurDataEntries;\r
-  UINT64  CurDataSize;\r
-  UINT64  TsegStart;\r
-  UINT64  TsegSize;\r
-  UINT64  NumSmis;\r
-  UINT64  NumCpus;\r
+  UINT64    HeaderSize;\r
+  UINT64    MaxDataEntries;\r
+  UINT64    MaxDataSize;\r
+  UINT64    CurDataEntries;\r
+  UINT64    CurDataSize;\r
+  UINT64    TsegStart;\r
+  UINT64    TsegSize;\r
+  UINT64    NumSmis;\r
+  UINT64    NumCpus;\r
 } SMM_PROFILE_HEADER;\r
 \r
 typedef struct {\r
-  UINT64  SmiNum;\r
-  UINT64  CpuNum;\r
-  UINT64  ApicId;\r
-  UINT64  ErrorCode;\r
-  UINT64  Instruction;\r
-  UINT64  Address;\r
-  UINT64  SmiCmd;\r
+  UINT64    SmiNum;\r
+  UINT64    CpuNum;\r
+  UINT64    ApicId;\r
+  UINT64    ErrorCode;\r
+  UINT64    Instruction;\r
+  UINT64    Address;\r
+  UINT64    SmiCmd;\r
 } SMM_PROFILE_ENTRY;\r
 \r
-extern SMM_S3_RESUME_STATE       *mSmmS3ResumeState;\r
-extern UINTN                     gSmiExceptionHandlers[];\r
-extern BOOLEAN                   mXdSupported;\r
-X86_ASSEMBLY_PATCH_LABEL         gPatchXdSupported;\r
-X86_ASSEMBLY_PATCH_LABEL         gPatchMsrIa32MiscEnableSupported;\r
-extern UINTN                     *mPFEntryCount;\r
-extern UINT64                    (*mLastPFEntryValue)[MAX_PF_ENTRY_COUNT];\r
+extern SMM_S3_RESUME_STATE  *mSmmS3ResumeState;\r
+extern UINTN                gSmiExceptionHandlers[];\r
+extern BOOLEAN              mXdSupported;\r
+X86_ASSEMBLY_PATCH_LABEL    gPatchXdSupported;\r
+X86_ASSEMBLY_PATCH_LABEL    gPatchMsrIa32MiscEnableSupported;\r
+extern UINTN                *mPFEntryCount;\r
+extern UINT64 (*mLastPFEntryValue)[MAX_PF_ENTRY_COUNT];\r
 extern UINT64                    *(*mLastPFEntryPointer)[MAX_PF_ENTRY_COUNT];\r
 \r
 //\r
@@ -127,7 +127,7 @@ InitIdtr (
 **/\r
 BOOLEAN\r
 IsAddressSplit (\r
-  IN EFI_PHYSICAL_ADDRESS   Address\r
+  IN EFI_PHYSICAL_ADDRESS  Address\r
   );\r
 \r
 /**\r
@@ -139,8 +139,8 @@ IsAddressSplit (
 **/\r
 BOOLEAN\r
 IsAddressValid (\r
-  IN EFI_PHYSICAL_ADDRESS   Address,\r
-  IN BOOLEAN                *Nx\r
+  IN EFI_PHYSICAL_ADDRESS  Address,\r
+  IN BOOLEAN               *Nx\r
   );\r
 \r
 /**\r
@@ -161,7 +161,7 @@ SmiDefaultPFHandler (
 **/\r
 VOID\r
 ClearTrapFlag (\r
-  IN OUT EFI_SYSTEM_CONTEXT   SystemContext\r
+  IN OUT EFI_SYSTEM_CONTEXT  SystemContext\r
   );\r
 \r
 #endif // _SMM_PROFILE_H_\r

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c b/UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c
index 518978c1d9680e0b0a3b09014ff480f87dfe460e..c8ddc6083df6f1b3673695959b3a390812651be7 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c
@@ -18,53 +18,53 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
 #include "PiSmmCpuDxeSmm.h"\r
 \r
 typedef struct {\r
-  UINT64                            Signature;              // Offset 0x00\r
-  UINT16                            Reserved1;              // Offset 0x08\r
-  UINT16                            Reserved2;              // Offset 0x0A\r
-  UINT16                            Reserved3;              // Offset 0x0C\r
-  UINT16                            SmmCs;                  // Offset 0x0E\r
-  UINT16                            SmmDs;                  // Offset 0x10\r
-  UINT16                            SmmSs;                  // Offset 0x12\r
-  UINT16                            SmmOtherSegment;        // Offset 0x14\r
-  UINT16                            Reserved4;              // Offset 0x16\r
-  UINT64                            Reserved5;              // Offset 0x18\r
-  UINT64                            Reserved6;              // Offset 0x20\r
-  UINT64                            Reserved7;              // Offset 0x28\r
-  UINT64                            SmmGdtPtr;              // Offset 0x30\r
-  UINT32                            SmmGdtSize;             // Offset 0x38\r
-  UINT32                            Reserved8;              // Offset 0x3C\r
-  UINT64                            Reserved9;              // Offset 0x40\r
-  UINT64                            Reserved10;             // Offset 0x48\r
-  UINT16                            Reserved11;             // Offset 0x50\r
-  UINT16                            Reserved12;             // Offset 0x52\r
-  UINT32                            Reserved13;             // Offset 0x54\r
-  UINT64                            Reserved14;             // Offset 0x58\r
+  UINT64    Signature;                                      // Offset 0x00\r
+  UINT16    Reserved1;                                      // Offset 0x08\r
+  UINT16    Reserved2;                                      // Offset 0x0A\r
+  UINT16    Reserved3;                                      // Offset 0x0C\r
+  UINT16    SmmCs;                                          // Offset 0x0E\r
+  UINT16    SmmDs;                                          // Offset 0x10\r
+  UINT16    SmmSs;                                          // Offset 0x12\r
+  UINT16    SmmOtherSegment;                                // Offset 0x14\r
+  UINT16    Reserved4;                                      // Offset 0x16\r
+  UINT64    Reserved5;                                      // Offset 0x18\r
+  UINT64    Reserved6;                                      // Offset 0x20\r
+  UINT64    Reserved7;                                      // Offset 0x28\r
+  UINT64    SmmGdtPtr;                                      // Offset 0x30\r
+  UINT32    SmmGdtSize;                                     // Offset 0x38\r
+  UINT32    Reserved8;                                      // Offset 0x3C\r
+  UINT64    Reserved9;                                      // Offset 0x40\r
+  UINT64    Reserved10;                                     // Offset 0x48\r
+  UINT16    Reserved11;                                     // Offset 0x50\r
+  UINT16    Reserved12;                                     // Offset 0x52\r
+  UINT32    Reserved13;                                     // Offset 0x54\r
+  UINT64    Reserved14;                                     // Offset 0x58\r
 } PROCESSOR_SMM_DESCRIPTOR;\r
 \r
-extern CONST PROCESSOR_SMM_DESCRIPTOR      gcPsd;\r
+extern CONST PROCESSOR_SMM_DESCRIPTOR  gcPsd;\r
 \r
 //\r
 // EFER register LMA bit\r
 //\r
-#define LMA BIT10\r
+#define LMA  BIT10\r
 \r
 ///\r
 /// Macro used to simplify the lookup table entries of type CPU_SMM_SAVE_STATE_LOOKUP_ENTRY\r
 ///\r
-#define SMM_CPU_OFFSET(Field) OFFSET_OF (SMRAM_SAVE_STATE_MAP, Field)\r
+#define SMM_CPU_OFFSET(Field)  OFFSET_OF (SMRAM_SAVE_STATE_MAP, Field)\r
 \r
 ///\r
 /// Macro used to simplify the lookup table entries of type CPU_SMM_SAVE_STATE_REGISTER_RANGE\r
 ///\r
-#define SMM_REGISTER_RANGE(Start, End) { Start, End, End - Start + 1 }\r
+#define SMM_REGISTER_RANGE(Start, End)  { Start, End, End - Start + 1 }\r
 \r
 ///\r
 /// Structure used to describe a range of registers\r
 ///\r
 typedef struct {\r
-  EFI_SMM_SAVE_STATE_REGISTER  Start;\r
-  EFI_SMM_SAVE_STATE_REGISTER  End;\r
-  UINTN                        Length;\r
+  EFI_SMM_SAVE_STATE_REGISTER    Start;\r
+  EFI_SMM_SAVE_STATE_REGISTER    End;\r
+  UINTN                          Length;\r
 } CPU_SMM_SAVE_STATE_REGISTER_RANGE;\r
 \r
 ///\r
@@ -72,36 +72,36 @@ typedef struct {
 /// associated with each supported EFI_SMM_SAVE_STATE_REGISTER value\r
 ///\r
 \r
-#define SMM_SAVE_STATE_REGISTER_SMMREVID_INDEX        1\r
-#define SMM_SAVE_STATE_REGISTER_IOMISC_INDEX          2\r
-#define SMM_SAVE_STATE_REGISTER_IOMEMADDR_INDEX       3\r
-#define SMM_SAVE_STATE_REGISTER_MAX_INDEX             4\r
+#define SMM_SAVE_STATE_REGISTER_SMMREVID_INDEX   1\r
+#define SMM_SAVE_STATE_REGISTER_IOMISC_INDEX     2\r
+#define SMM_SAVE_STATE_REGISTER_IOMEMADDR_INDEX  3\r
+#define SMM_SAVE_STATE_REGISTER_MAX_INDEX        4\r
 \r
 typedef struct {\r
-  UINT8   Width32;\r
-  UINT8   Width64;\r
-  UINT16  Offset32;\r
-  UINT16  Offset64Lo;\r
-  UINT16  Offset64Hi;\r
-  BOOLEAN Writeable;\r
+  UINT8      Width32;\r
+  UINT8      Width64;\r
+  UINT16     Offset32;\r
+  UINT16     Offset64Lo;\r
+  UINT16     Offset64Hi;\r
+  BOOLEAN    Writeable;\r
 } CPU_SMM_SAVE_STATE_LOOKUP_ENTRY;\r
 \r
 ///\r
 /// Structure used to build a lookup table for the IOMisc width information\r
 ///\r
 typedef struct {\r
-  UINT8                        Width;\r
-  EFI_SMM_SAVE_STATE_IO_WIDTH  IoWidth;\r
+  UINT8                          Width;\r
+  EFI_SMM_SAVE_STATE_IO_WIDTH    IoWidth;\r
 } CPU_SMM_SAVE_STATE_IO_WIDTH;\r
 \r
 ///\r
 /// Variables from SMI Handler\r
 ///\r
-X86_ASSEMBLY_PATCH_LABEL gPatchSmbase;\r
-X86_ASSEMBLY_PATCH_LABEL gPatchSmiStack;\r
-X86_ASSEMBLY_PATCH_LABEL gPatchSmiCr3;\r
-extern volatile UINT8    gcSmiHandlerTemplate[];\r
-extern CONST UINT16      gcSmiHandlerSize;\r
+X86_ASSEMBLY_PATCH_LABEL  gPatchSmbase;\r
+X86_ASSEMBLY_PATCH_LABEL  gPatchSmiStack;\r
+X86_ASSEMBLY_PATCH_LABEL  gPatchSmiCr3;\r
+extern volatile UINT8     gcSmiHandlerTemplate[];\r
+extern CONST UINT16       gcSmiHandlerSize;\r
 \r
 //\r
 // Variables used by SMI Handler\r
@@ -112,76 +112,76 @@ IA32_DESCRIPTOR  gSmiHandlerIdtr;
 /// Table used by GetRegisterIndex() to convert an EFI_SMM_SAVE_STATE_REGISTER\r
 /// value to an index into a table of type CPU_SMM_SAVE_STATE_LOOKUP_ENTRY\r
 ///\r
-CONST CPU_SMM_SAVE_STATE_REGISTER_RANGE mSmmCpuRegisterRanges[] = {\r
+CONST CPU_SMM_SAVE_STATE_REGISTER_RANGE  mSmmCpuRegisterRanges[] = {\r
   SMM_REGISTER_RANGE (EFI_SMM_SAVE_STATE_REGISTER_GDTBASE, EFI_SMM_SAVE_STATE_REGISTER_LDTINFO),\r
   SMM_REGISTER_RANGE (EFI_SMM_SAVE_STATE_REGISTER_ES,      EFI_SMM_SAVE_STATE_REGISTER_RIP),\r
   SMM_REGISTER_RANGE (EFI_SMM_SAVE_STATE_REGISTER_RFLAGS,  EFI_SMM_SAVE_STATE_REGISTER_CR4),\r
-  { (EFI_SMM_SAVE_STATE_REGISTER)0, (EFI_SMM_SAVE_STATE_REGISTER)0, 0 }\r
+  { (EFI_SMM_SAVE_STATE_REGISTER)0,                        (EFI_SMM_SAVE_STATE_REGISTER)0,      0}\r
 };\r
 \r
 ///\r
 /// Lookup table used to retrieve the widths and offsets associated with each\r
 /// supported EFI_SMM_SAVE_STATE_REGISTER value\r
 ///\r
-CONST CPU_SMM_SAVE_STATE_LOOKUP_ENTRY mSmmCpuWidthOffset[] = {\r
-  {0, 0, 0, 0, 0, FALSE},                                                                                                     //  Reserved\r
+CONST CPU_SMM_SAVE_STATE_LOOKUP_ENTRY  mSmmCpuWidthOffset[] = {\r
+  { 0, 0, 0,                              0,                                   0,                                   FALSE },  //  Reserved\r
 \r
   //\r
   // Internally defined CPU Save State Registers. Not defined in PI SMM CPU Protocol.\r
   //\r
-  {4, 4, SMM_CPU_OFFSET (x86.SMMRevId)  , SMM_CPU_OFFSET (x64.SMMRevId)  , 0                                 , FALSE}, // SMM_SAVE_STATE_REGISTER_SMMREVID_INDEX  = 1\r
-  {4, 4, SMM_CPU_OFFSET (x86.IOMisc)    , SMM_CPU_OFFSET (x64.IOMisc)    , 0                                 , FALSE}, // SMM_SAVE_STATE_REGISTER_IOMISC_INDEX    = 2\r
-  {4, 8, SMM_CPU_OFFSET (x86.IOMemAddr) , SMM_CPU_OFFSET (x64.IOMemAddr) , SMM_CPU_OFFSET (x64.IOMemAddr) + 4, FALSE}, // SMM_SAVE_STATE_REGISTER_IOMEMADDR_INDEX = 3\r
+  { 4, 4, SMM_CPU_OFFSET (x86.SMMRevId),  SMM_CPU_OFFSET (x64.SMMRevId),       0,                                   FALSE }, // SMM_SAVE_STATE_REGISTER_SMMREVID_INDEX  = 1\r
+  { 4, 4, SMM_CPU_OFFSET (x86.IOMisc),    SMM_CPU_OFFSET (x64.IOMisc),         0,                                   FALSE }, // SMM_SAVE_STATE_REGISTER_IOMISC_INDEX    = 2\r
+  { 4, 8, SMM_CPU_OFFSET (x86.IOMemAddr), SMM_CPU_OFFSET (x64.IOMemAddr),      SMM_CPU_OFFSET (x64.IOMemAddr) + 4,  FALSE }, // SMM_SAVE_STATE_REGISTER_IOMEMADDR_INDEX = 3\r
 \r
   //\r
   // CPU Save State registers defined in PI SMM CPU Protocol.\r
   //\r
-  {0, 8, 0                            , SMM_CPU_OFFSET (x64.GdtBaseLoDword) , SMM_CPU_OFFSET (x64.GdtBaseHiDword), FALSE},  //  EFI_SMM_SAVE_STATE_REGISTER_GDTBASE  = 4\r
-  {0, 8, 0                            , SMM_CPU_OFFSET (x64.IdtBaseLoDword) , SMM_CPU_OFFSET (x64.IdtBaseHiDword), FALSE},  //  EFI_SMM_SAVE_STATE_REGISTER_IDTBASE  = 5\r
-  {0, 8, 0                            , SMM_CPU_OFFSET (x64.LdtBaseLoDword) , SMM_CPU_OFFSET (x64.LdtBaseHiDword), FALSE},  //  EFI_SMM_SAVE_STATE_REGISTER_LDTBASE  = 6\r
-  {0, 0, 0                            , 0                                   , 0                                  , FALSE},  //  EFI_SMM_SAVE_STATE_REGISTER_GDTLIMIT = 7\r
-  {0, 0, 0                            , 0                                   , 0                                  , FALSE},  //  EFI_SMM_SAVE_STATE_REGISTER_IDTLIMIT = 8\r
-  {0, 0, 0                            , 0                                   , 0                                  , FALSE},  //  EFI_SMM_SAVE_STATE_REGISTER_LDTLIMIT = 9\r
-  {0, 0, 0                            , 0                                   , 0                                  , FALSE},  //  EFI_SMM_SAVE_STATE_REGISTER_LDTINFO  = 10\r
-\r
-  {4, 4, SMM_CPU_OFFSET (x86._ES)     , SMM_CPU_OFFSET (x64._ES)     , 0                               , FALSE},  //  EFI_SMM_SAVE_STATE_REGISTER_ES       = 20\r
-  {4, 4, SMM_CPU_OFFSET (x86._CS)     , SMM_CPU_OFFSET (x64._CS)     , 0                               , FALSE},  //  EFI_SMM_SAVE_STATE_REGISTER_CS       = 21\r
-  {4, 4, SMM_CPU_OFFSET (x86._SS)     , SMM_CPU_OFFSET (x64._SS)     , 0                               , FALSE},  //  EFI_SMM_SAVE_STATE_REGISTER_SS       = 22\r
-  {4, 4, SMM_CPU_OFFSET (x86._DS)     , SMM_CPU_OFFSET (x64._DS)     , 0                               , FALSE},  //  EFI_SMM_SAVE_STATE_REGISTER_DS       = 23\r
-  {4, 4, SMM_CPU_OFFSET (x86._FS)     , SMM_CPU_OFFSET (x64._FS)     , 0                               , FALSE},  //  EFI_SMM_SAVE_STATE_REGISTER_FS       = 24\r
-  {4, 4, SMM_CPU_OFFSET (x86._GS)     , SMM_CPU_OFFSET (x64._GS)     , 0                               , FALSE},  //  EFI_SMM_SAVE_STATE_REGISTER_GS       = 25\r
-  {0, 4, 0                            , SMM_CPU_OFFSET (x64._LDTR)   , 0                               , FALSE},  //  EFI_SMM_SAVE_STATE_REGISTER_LDTR_SEL = 26\r
-  {4, 4, SMM_CPU_OFFSET (x86._TR)     , SMM_CPU_OFFSET (x64._TR)     , 0                               , FALSE},  //  EFI_SMM_SAVE_STATE_REGISTER_TR_SEL   = 27\r
-  {4, 8, SMM_CPU_OFFSET (x86._DR7)    , SMM_CPU_OFFSET (x64._DR7)    , SMM_CPU_OFFSET (x64._DR7)    + 4, FALSE},  //  EFI_SMM_SAVE_STATE_REGISTER_DR7      = 28\r
-  {4, 8, SMM_CPU_OFFSET (x86._DR6)    , SMM_CPU_OFFSET (x64._DR6)    , SMM_CPU_OFFSET (x64._DR6)    + 4, FALSE},  //  EFI_SMM_SAVE_STATE_REGISTER_DR6      = 29\r
-  {0, 8, 0                            , SMM_CPU_OFFSET (x64._R8)     , SMM_CPU_OFFSET (x64._R8)     + 4, TRUE },  //  EFI_SMM_SAVE_STATE_REGISTER_R8       = 30\r
-  {0, 8, 0                            , SMM_CPU_OFFSET (x64._R9)     , SMM_CPU_OFFSET (x64._R9)     + 4, TRUE },  //  EFI_SMM_SAVE_STATE_REGISTER_R9       = 31\r
-  {0, 8, 0                            , SMM_CPU_OFFSET (x64._R10)    , SMM_CPU_OFFSET (x64._R10)    + 4, TRUE },  //  EFI_SMM_SAVE_STATE_REGISTER_R10      = 32\r
-  {0, 8, 0                            , SMM_CPU_OFFSET (x64._R11)    , SMM_CPU_OFFSET (x64._R11)    + 4, TRUE },  //  EFI_SMM_SAVE_STATE_REGISTER_R11      = 33\r
-  {0, 8, 0                            , SMM_CPU_OFFSET (x64._R12)    , SMM_CPU_OFFSET (x64._R12)    + 4, TRUE },  //  EFI_SMM_SAVE_STATE_REGISTER_R12      = 34\r
-  {0, 8, 0                            , SMM_CPU_OFFSET (x64._R13)    , SMM_CPU_OFFSET (x64._R13)    + 4, TRUE },  //  EFI_SMM_SAVE_STATE_REGISTER_R13      = 35\r
-  {0, 8, 0                            , SMM_CPU_OFFSET (x64._R14)    , SMM_CPU_OFFSET (x64._R14)    + 4, TRUE },  //  EFI_SMM_SAVE_STATE_REGISTER_R14      = 36\r
-  {0, 8, 0                            , SMM_CPU_OFFSET (x64._R15)    , SMM_CPU_OFFSET (x64._R15)    + 4, TRUE },  //  EFI_SMM_SAVE_STATE_REGISTER_R15      = 37\r
-  {4, 8, SMM_CPU_OFFSET (x86._EAX)    , SMM_CPU_OFFSET (x64._RAX)    , SMM_CPU_OFFSET (x64._RAX)    + 4, TRUE },  //  EFI_SMM_SAVE_STATE_REGISTER_RAX      = 38\r
-  {4, 8, SMM_CPU_OFFSET (x86._EBX)    , SMM_CPU_OFFSET (x64._RBX)    , SMM_CPU_OFFSET (x64._RBX)    + 4, TRUE },  //  EFI_SMM_SAVE_STATE_REGISTER_RBX      = 39\r
-  {4, 8, SMM_CPU_OFFSET (x86._ECX)    , SMM_CPU_OFFSET (x64._RCX)    , SMM_CPU_OFFSET (x64._RCX)    + 4, TRUE },  //  EFI_SMM_SAVE_STATE_REGISTER_RCX      = 40\r
-  {4, 8, SMM_CPU_OFFSET (x86._EDX)    , SMM_CPU_OFFSET (x64._RDX)    , SMM_CPU_OFFSET (x64._RDX)    + 4, TRUE },  //  EFI_SMM_SAVE_STATE_REGISTER_RDX      = 41\r
-  {4, 8, SMM_CPU_OFFSET (x86._ESP)    , SMM_CPU_OFFSET (x64._RSP)    , SMM_CPU_OFFSET (x64._RSP)    + 4, TRUE },  //  EFI_SMM_SAVE_STATE_REGISTER_RSP      = 42\r
-  {4, 8, SMM_CPU_OFFSET (x86._EBP)    , SMM_CPU_OFFSET (x64._RBP)    , SMM_CPU_OFFSET (x64._RBP)    + 4, TRUE },  //  EFI_SMM_SAVE_STATE_REGISTER_RBP      = 43\r
-  {4, 8, SMM_CPU_OFFSET (x86._ESI)    , SMM_CPU_OFFSET (x64._RSI)    , SMM_CPU_OFFSET (x64._RSI)    + 4, TRUE },  //  EFI_SMM_SAVE_STATE_REGISTER_RSI      = 44\r
-  {4, 8, SMM_CPU_OFFSET (x86._EDI)    , SMM_CPU_OFFSET (x64._RDI)    , SMM_CPU_OFFSET (x64._RDI)    + 4, TRUE },  //  EFI_SMM_SAVE_STATE_REGISTER_RDI      = 45\r
-  {4, 8, SMM_CPU_OFFSET (x86._EIP)    , SMM_CPU_OFFSET (x64._RIP)    , SMM_CPU_OFFSET (x64._RIP)    + 4, TRUE },  //  EFI_SMM_SAVE_STATE_REGISTER_RIP      = 46\r
-\r
-  {4, 8, SMM_CPU_OFFSET (x86._EFLAGS) , SMM_CPU_OFFSET (x64._RFLAGS) , SMM_CPU_OFFSET (x64._RFLAGS) + 4, TRUE },  //  EFI_SMM_SAVE_STATE_REGISTER_RFLAGS   = 51\r
-  {4, 8, SMM_CPU_OFFSET (x86._CR0)    , SMM_CPU_OFFSET (x64._CR0)    , SMM_CPU_OFFSET (x64._CR0)    + 4, FALSE},  //  EFI_SMM_SAVE_STATE_REGISTER_CR0      = 52\r
-  {4, 8, SMM_CPU_OFFSET (x86._CR3)    , SMM_CPU_OFFSET (x64._CR3)    , SMM_CPU_OFFSET (x64._CR3)    + 4, FALSE},  //  EFI_SMM_SAVE_STATE_REGISTER_CR3      = 53\r
-  {0, 4, 0                            , SMM_CPU_OFFSET (x64._CR4)    , 0                               , FALSE},  //  EFI_SMM_SAVE_STATE_REGISTER_CR4      = 54\r
+  { 0, 8, 0,                              SMM_CPU_OFFSET (x64.GdtBaseLoDword), SMM_CPU_OFFSET (x64.GdtBaseHiDword), FALSE }, //  EFI_SMM_SAVE_STATE_REGISTER_GDTBASE  = 4\r
+  { 0, 8, 0,                              SMM_CPU_OFFSET (x64.IdtBaseLoDword), SMM_CPU_OFFSET (x64.IdtBaseHiDword), FALSE }, //  EFI_SMM_SAVE_STATE_REGISTER_IDTBASE  = 5\r
+  { 0, 8, 0,                              SMM_CPU_OFFSET (x64.LdtBaseLoDword), SMM_CPU_OFFSET (x64.LdtBaseHiDword), FALSE }, //  EFI_SMM_SAVE_STATE_REGISTER_LDTBASE  = 6\r
+  { 0, 0, 0,                              0,                                   0,                                   FALSE }, //  EFI_SMM_SAVE_STATE_REGISTER_GDTLIMIT = 7\r
+  { 0, 0, 0,                              0,                                   0,                                   FALSE }, //  EFI_SMM_SAVE_STATE_REGISTER_IDTLIMIT = 8\r
+  { 0, 0, 0,                              0,                                   0,                                   FALSE }, //  EFI_SMM_SAVE_STATE_REGISTER_LDTLIMIT = 9\r
+  { 0, 0, 0,                              0,                                   0,                                   FALSE }, //  EFI_SMM_SAVE_STATE_REGISTER_LDTINFO  = 10\r
+\r
+  { 4, 4, SMM_CPU_OFFSET (x86._ES),       SMM_CPU_OFFSET (x64._ES),            0,                                   FALSE }, //  EFI_SMM_SAVE_STATE_REGISTER_ES       = 20\r
+  { 4, 4, SMM_CPU_OFFSET (x86._CS),       SMM_CPU_OFFSET (x64._CS),            0,                                   FALSE }, //  EFI_SMM_SAVE_STATE_REGISTER_CS       = 21\r
+  { 4, 4, SMM_CPU_OFFSET (x86._SS),       SMM_CPU_OFFSET (x64._SS),            0,                                   FALSE }, //  EFI_SMM_SAVE_STATE_REGISTER_SS       = 22\r
+  { 4, 4, SMM_CPU_OFFSET (x86._DS),       SMM_CPU_OFFSET (x64._DS),            0,                                   FALSE }, //  EFI_SMM_SAVE_STATE_REGISTER_DS       = 23\r
+  { 4, 4, SMM_CPU_OFFSET (x86._FS),       SMM_CPU_OFFSET (x64._FS),            0,                                   FALSE }, //  EFI_SMM_SAVE_STATE_REGISTER_FS       = 24\r
+  { 4, 4, SMM_CPU_OFFSET (x86._GS),       SMM_CPU_OFFSET (x64._GS),            0,                                   FALSE }, //  EFI_SMM_SAVE_STATE_REGISTER_GS       = 25\r
+  { 0, 4, 0,                              SMM_CPU_OFFSET (x64._LDTR),          0,                                   FALSE }, //  EFI_SMM_SAVE_STATE_REGISTER_LDTR_SEL = 26\r
+  { 4, 4, SMM_CPU_OFFSET (x86._TR),       SMM_CPU_OFFSET (x64._TR),            0,                                   FALSE }, //  EFI_SMM_SAVE_STATE_REGISTER_TR_SEL   = 27\r
+  { 4, 8, SMM_CPU_OFFSET (x86._DR7),      SMM_CPU_OFFSET (x64._DR7),           SMM_CPU_OFFSET (x64._DR7)    + 4,    FALSE }, //  EFI_SMM_SAVE_STATE_REGISTER_DR7      = 28\r
+  { 4, 8, SMM_CPU_OFFSET (x86._DR6),      SMM_CPU_OFFSET (x64._DR6),           SMM_CPU_OFFSET (x64._DR6)    + 4,    FALSE }, //  EFI_SMM_SAVE_STATE_REGISTER_DR6      = 29\r
+  { 0, 8, 0,                              SMM_CPU_OFFSET (x64._R8),            SMM_CPU_OFFSET (x64._R8)     + 4,    TRUE  }, //  EFI_SMM_SAVE_STATE_REGISTER_R8       = 30\r
+  { 0, 8, 0,                              SMM_CPU_OFFSET (x64._R9),            SMM_CPU_OFFSET (x64._R9)     + 4,    TRUE  }, //  EFI_SMM_SAVE_STATE_REGISTER_R9       = 31\r
+  { 0, 8, 0,                              SMM_CPU_OFFSET (x64._R10),           SMM_CPU_OFFSET (x64._R10)    + 4,    TRUE  }, //  EFI_SMM_SAVE_STATE_REGISTER_R10      = 32\r
+  { 0, 8, 0,                              SMM_CPU_OFFSET (x64._R11),           SMM_CPU_OFFSET (x64._R11)    + 4,    TRUE  }, //  EFI_SMM_SAVE_STATE_REGISTER_R11      = 33\r
+  { 0, 8, 0,                              SMM_CPU_OFFSET (x64._R12),           SMM_CPU_OFFSET (x64._R12)    + 4,    TRUE  }, //  EFI_SMM_SAVE_STATE_REGISTER_R12      = 34\r
+  { 0, 8, 0,                              SMM_CPU_OFFSET (x64._R13),           SMM_CPU_OFFSET (x64._R13)    + 4,    TRUE  }, //  EFI_SMM_SAVE_STATE_REGISTER_R13      = 35\r
+  { 0, 8, 0,                              SMM_CPU_OFFSET (x64._R14),           SMM_CPU_OFFSET (x64._R14)    + 4,    TRUE  }, //  EFI_SMM_SAVE_STATE_REGISTER_R14      = 36\r
+  { 0, 8, 0,                              SMM_CPU_OFFSET (x64._R15),           SMM_CPU_OFFSET (x64._R15)    + 4,    TRUE  }, //  EFI_SMM_SAVE_STATE_REGISTER_R15      = 37\r
+  { 4, 8, SMM_CPU_OFFSET (x86._EAX),      SMM_CPU_OFFSET (x64._RAX),           SMM_CPU_OFFSET (x64._RAX)    + 4,    TRUE  }, //  EFI_SMM_SAVE_STATE_REGISTER_RAX      = 38\r
+  { 4, 8, SMM_CPU_OFFSET (x86._EBX),      SMM_CPU_OFFSET (x64._RBX),           SMM_CPU_OFFSET (x64._RBX)    + 4,    TRUE  }, //  EFI_SMM_SAVE_STATE_REGISTER_RBX      = 39\r
+  { 4, 8, SMM_CPU_OFFSET (x86._ECX),      SMM_CPU_OFFSET (x64._RCX),           SMM_CPU_OFFSET (x64._RCX)    + 4,    TRUE  }, //  EFI_SMM_SAVE_STATE_REGISTER_RCX      = 40\r
+  { 4, 8, SMM_CPU_OFFSET (x86._EDX),      SMM_CPU_OFFSET (x64._RDX),           SMM_CPU_OFFSET (x64._RDX)    + 4,    TRUE  }, //  EFI_SMM_SAVE_STATE_REGISTER_RDX      = 41\r
+  { 4, 8, SMM_CPU_OFFSET (x86._ESP),      SMM_CPU_OFFSET (x64._RSP),           SMM_CPU_OFFSET (x64._RSP)    + 4,    TRUE  }, //  EFI_SMM_SAVE_STATE_REGISTER_RSP      = 42\r
+  { 4, 8, SMM_CPU_OFFSET (x86._EBP),      SMM_CPU_OFFSET (x64._RBP),           SMM_CPU_OFFSET (x64._RBP)    + 4,    TRUE  }, //  EFI_SMM_SAVE_STATE_REGISTER_RBP      = 43\r
+  { 4, 8, SMM_CPU_OFFSET (x86._ESI),      SMM_CPU_OFFSET (x64._RSI),           SMM_CPU_OFFSET (x64._RSI)    + 4,    TRUE  }, //  EFI_SMM_SAVE_STATE_REGISTER_RSI      = 44\r
+  { 4, 8, SMM_CPU_OFFSET (x86._EDI),      SMM_CPU_OFFSET (x64._RDI),           SMM_CPU_OFFSET (x64._RDI)    + 4,    TRUE  }, //  EFI_SMM_SAVE_STATE_REGISTER_RDI      = 45\r
+  { 4, 8, SMM_CPU_OFFSET (x86._EIP),      SMM_CPU_OFFSET (x64._RIP),           SMM_CPU_OFFSET (x64._RIP)    + 4,    TRUE  }, //  EFI_SMM_SAVE_STATE_REGISTER_RIP      = 46\r
+\r
+  { 4, 8, SMM_CPU_OFFSET (x86._EFLAGS),   SMM_CPU_OFFSET (x64._RFLAGS),        SMM_CPU_OFFSET (x64._RFLAGS) + 4,    TRUE  }, //  EFI_SMM_SAVE_STATE_REGISTER_RFLAGS   = 51\r
+  { 4, 8, SMM_CPU_OFFSET (x86._CR0),      SMM_CPU_OFFSET (x64._CR0),           SMM_CPU_OFFSET (x64._CR0)    + 4,    FALSE }, //  EFI_SMM_SAVE_STATE_REGISTER_CR0      = 52\r
+  { 4, 8, SMM_CPU_OFFSET (x86._CR3),      SMM_CPU_OFFSET (x64._CR3),           SMM_CPU_OFFSET (x64._CR3)    + 4,    FALSE }, //  EFI_SMM_SAVE_STATE_REGISTER_CR3      = 53\r
+  { 0, 4, 0,                              SMM_CPU_OFFSET (x64._CR4),           0,                                   FALSE }, //  EFI_SMM_SAVE_STATE_REGISTER_CR4      = 54\r
 };\r
 \r
 ///\r
 /// Lookup table for the IOMisc width information\r
 ///\r
-CONST CPU_SMM_SAVE_STATE_IO_WIDTH mSmmCpuIoWidth[] = {\r
+CONST CPU_SMM_SAVE_STATE_IO_WIDTH  mSmmCpuIoWidth[] = {\r
   { 0, EFI_SMM_SAVE_STATE_IO_WIDTH_UINT8  },  // Undefined           = 0\r
   { 1, EFI_SMM_SAVE_STATE_IO_WIDTH_UINT8  },  // SMM_IO_LENGTH_BYTE  = 1\r
   { 2, EFI_SMM_SAVE_STATE_IO_WIDTH_UINT16 },  // SMM_IO_LENGTH_WORD  = 2\r
@@ -195,7 +195,7 @@ CONST CPU_SMM_SAVE_STATE_IO_WIDTH mSmmCpuIoWidth[] = {
 ///\r
 /// Lookup table for the IOMisc type information\r
 ///\r
-CONST EFI_SMM_SAVE_STATE_IO_TYPE mSmmCpuIoType[] = {\r
+CONST EFI_SMM_SAVE_STATE_IO_TYPE  mSmmCpuIoType[] = {\r
   EFI_SMM_SAVE_STATE_IO_TYPE_OUTPUT,     // SMM_IO_TYPE_OUT_DX        = 0\r
   EFI_SMM_SAVE_STATE_IO_TYPE_INPUT,      // SMM_IO_TYPE_IN_DX         = 1\r
   EFI_SMM_SAVE_STATE_IO_TYPE_STRING,     // SMM_IO_TYPE_OUTS          = 2\r
@@ -237,11 +237,13 @@ GetRegisterIndex (
   UINTN  Offset;\r
 \r
   for (Index = 0, Offset = SMM_SAVE_STATE_REGISTER_MAX_INDEX; mSmmCpuRegisterRanges[Index].Length != 0; Index++) {\r
-    if (Register >= mSmmCpuRegisterRanges[Index].Start && Register <= mSmmCpuRegisterRanges[Index].End) {\r
+    if ((Register >= mSmmCpuRegisterRanges[Index].Start) && (Register <= mSmmCpuRegisterRanges[Index].End)) {\r
       return Register - mSmmCpuRegisterRanges[Index].Start + Offset;\r
     }\r
+\r
     Offset += mSmmCpuRegisterRanges[Index].Length;\r
   }\r
+\r
   return 0;\r
 }\r
 \r
@@ -265,10 +267,10 @@ GetRegisterIndex (
 **/\r
 EFI_STATUS\r
 ReadSaveStateRegisterByIndex (\r
-  IN UINTN   CpuIndex,\r
-  IN UINTN   RegisterIndex,\r
-  IN UINTN   Width,\r
-  OUT VOID   *Buffer\r
+  IN UINTN  CpuIndex,\r
+  IN UINTN  RegisterIndex,\r
+  IN UINTN  Width,\r
+  OUT VOID  *Buffer\r
   )\r
 {\r
   SMRAM_SAVE_STATE_MAP  *CpuSaveState;\r
@@ -297,8 +299,8 @@ ReadSaveStateRegisterByIndex (
     //\r
     // Write return buffer\r
     //\r
-    ASSERT(CpuSaveState != NULL);\r
-    CopyMem(Buffer, (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset32, Width);\r
+    ASSERT (CpuSaveState != NULL);\r
+    CopyMem (Buffer, (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset32, Width);\r
   } else {\r
     //\r
     // If 64-bit mode width is zero, then the specified register can not be accessed\r
@@ -317,14 +319,15 @@ ReadSaveStateRegisterByIndex (
     //\r
     // Write at most 4 of the lower bytes of the return buffer\r
     //\r
-    CopyMem(Buffer, (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Lo, MIN(4, Width));\r
+    CopyMem (Buffer, (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Lo, MIN (4, Width));\r
     if (Width > 4) {\r
       //\r
       // Write at most 4 of the upper bytes of the return buffer\r
       //\r
-      CopyMem((UINT8 *)Buffer + 4, (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Hi, Width - 4);\r
+      CopyMem ((UINT8 *)Buffer + 4, (UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Hi, Width - 4);\r
     }\r
   }\r
+\r
   return EFI_SUCCESS;\r
 }\r
 \r
@@ -382,7 +385,7 @@ ReadSaveStateRegister (
     //\r
     // Get SMM Revision ID\r
     //\r
-    ReadSaveStateRegisterByIndex (CpuIndex, SMM_SAVE_STATE_REGISTER_SMMREVID_INDEX, sizeof(SmmRevId), &SmmRevId);\r
+    ReadSaveStateRegisterByIndex (CpuIndex, SMM_SAVE_STATE_REGISTER_SMMREVID_INDEX, sizeof (SmmRevId), &SmmRevId);\r
 \r
     //\r
     // See if the CPU supports the IOMisc register in the save state\r
@@ -394,7 +397,7 @@ ReadSaveStateRegister (
     //\r
     // Get the IOMisc register value\r
     //\r
-    ReadSaveStateRegisterByIndex (CpuIndex, SMM_SAVE_STATE_REGISTER_IOMISC_INDEX, sizeof(IoMisc.Uint32), &IoMisc.Uint32);\r
+    ReadSaveStateRegisterByIndex (CpuIndex, SMM_SAVE_STATE_REGISTER_IOMISC_INDEX, sizeof (IoMisc.Uint32), &IoMisc.Uint32);\r
 \r
     //\r
     // Check for the SMI_FLAG in IOMisc\r
@@ -407,14 +410,15 @@ ReadSaveStateRegister (
     // Only support IN/OUT, but not INS/OUTS/REP INS/REP OUTS.\r
     //\r
     if ((mSmmCpuIoType[IoMisc.Bits.Type] != EFI_SMM_SAVE_STATE_IO_TYPE_INPUT) &&\r
-        (mSmmCpuIoType[IoMisc.Bits.Type] != EFI_SMM_SAVE_STATE_IO_TYPE_OUTPUT)) {\r
+        (mSmmCpuIoType[IoMisc.Bits.Type] != EFI_SMM_SAVE_STATE_IO_TYPE_OUTPUT))\r
+    {\r
       return EFI_NOT_FOUND;\r
     }\r
 \r
     //\r
     // Compute index for the I/O Length and I/O Type lookup tables\r
     //\r
-    if (mSmmCpuIoWidth[IoMisc.Bits.Length].Width == 0 || mSmmCpuIoType[IoMisc.Bits.Type] == 0) {\r
+    if ((mSmmCpuIoWidth[IoMisc.Bits.Length].Width == 0) || (mSmmCpuIoType[IoMisc.Bits.Type] == 0)) {\r
       return EFI_NOT_FOUND;\r
     }\r
 \r
@@ -429,14 +433,14 @@ ReadSaveStateRegister (
     // Zero the IoInfo structure that will be returned in Buffer\r
     //\r
     IoInfo = (EFI_SMM_SAVE_STATE_IO_INFO *)Buffer;\r
-    ZeroMem (IoInfo, sizeof(EFI_SMM_SAVE_STATE_IO_INFO));\r
+    ZeroMem (IoInfo, sizeof (EFI_SMM_SAVE_STATE_IO_INFO));\r
 \r
     //\r
     // Use lookup tables to help fill in all the fields of the IoInfo structure\r
     //\r
-    IoInfo->IoPort = (UINT16)IoMisc.Bits.Port;\r
+    IoInfo->IoPort  = (UINT16)IoMisc.Bits.Port;\r
     IoInfo->IoWidth = mSmmCpuIoWidth[IoMisc.Bits.Length].IoWidth;\r
-    IoInfo->IoType = mSmmCpuIoType[IoMisc.Bits.Type];\r
+    IoInfo->IoType  = mSmmCpuIoType[IoMisc.Bits.Type];\r
     ReadSaveStateRegister (CpuIndex, EFI_SMM_SAVE_STATE_REGISTER_RAX, mSmmCpuIoWidth[IoMisc.Bits.Length].Width, &IoInfo->IoData);\r
     return EFI_SUCCESS;\r
   }\r
@@ -525,11 +529,12 @@ WriteSaveStateRegister (
     if (Width > mSmmCpuWidthOffset[RegisterIndex].Width32) {\r
       return EFI_INVALID_PARAMETER;\r
     }\r
+\r
     //\r
     // Write SMM State register\r
     //\r
     ASSERT (CpuSaveState != NULL);\r
-    CopyMem((UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset32, Buffer, Width);\r
+    CopyMem ((UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset32, Buffer, Width);\r
   } else {\r
     //\r
     // If 64-bit mode width is zero, then the specified register can not be accessed\r
@@ -548,14 +553,15 @@ WriteSaveStateRegister (
     //\r
     // Write at most 4 of the lower bytes of SMM State register\r
     //\r
-    CopyMem((UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Lo, Buffer, MIN (4, Width));\r
+    CopyMem ((UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Lo, Buffer, MIN (4, Width));\r
     if (Width > 4) {\r
       //\r
       // Write at most 4 of the upper bytes of SMM State register\r
       //\r
-      CopyMem((UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Hi, (UINT8 *)Buffer + 4, Width - 4);\r
+      CopyMem ((UINT8 *)CpuSaveState + mSmmCpuWidthOffset[RegisterIndex].Offset64Hi, (UINT8 *)Buffer + 4, Width - 4);\r
     }\r
   }\r
+\r
   return EFI_SUCCESS;\r
 }\r
 \r
@@ -600,7 +606,7 @@ HookReturnFromSmm (
 \r
   if (mSmmSaveStateRegisterLma == EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT) {\r
     OriginalInstructionPointer = (UINT64)CpuState->x86._EIP;\r
-    CpuState->x86._EIP = (UINT32)NewInstructionPointer;\r
+    CpuState->x86._EIP         = (UINT32)NewInstructionPointer;\r
     //\r
     // Clear the auto HALT restart flag so the RSM instruction returns\r
     // program control to the instruction following the HLT instruction.\r
@@ -615,6 +621,7 @@ HookReturnFromSmm (
     } else {\r
       CpuState->x64._RIP = (UINT32)NewInstructionPointer;\r
     }\r
+\r
     //\r
     // Clear the auto HALT restart flag so the RSM instruction returns\r
     // program control to the instruction following the HLT instruction.\r
@@ -623,6 +630,7 @@ HookReturnFromSmm (
       CpuState->x64.AutoHALTRestart &= ~BIT0;\r
     }\r
   }\r
+\r
   return OriginalInstructionPointer;\r
 }\r
 \r
@@ -644,6 +652,7 @@ GetSmiHandlerSize (
   if (Size != 0) {\r
     return Size;\r
   }\r
+\r
   return gcSmiHandlerSize;\r
 }\r
 \r
@@ -693,7 +702,7 @@ InstallSmiHandler (
   //\r
   Psd = (PROCESSOR_SMM_DESCRIPTOR *)(VOID *)((UINTN)SmBase + SMM_PSD_OFFSET);\r
   CopyMem (Psd, &gcPsd, sizeof (gcPsd));\r
-  Psd->SmmGdtPtr = (UINT64)GdtBase;\r
+  Psd->SmmGdtPtr  = (UINT64)GdtBase;\r
   Psd->SmmGdtSize = (UINT32)GdtSize;\r
 \r
   if (SmmCpuFeaturesGetSmiHandlerSize () != 0) {\r
@@ -729,14 +738,14 @@ InstallSmiHandler (
   //\r
   // Set the value at the top of the CPU stack to the CPU Index\r
   //\r
-  *(UINTN*)(UINTN)CpuSmiStack = CpuIndex;\r
+  *(UINTN *)(UINTN)CpuSmiStack = CpuIndex;\r
 \r
   //\r
   // Copy template to CPU specific SMI handler location\r
   //\r
   CopyMem (\r
-    (VOID*)((UINTN)SmBase + SMM_HANDLER_OFFSET),\r
-    (VOID*)gcSmiHandlerTemplate,\r
+    (VOID *)((UINTN)SmBase + SMM_HANDLER_OFFSET),\r
+    (VOID *)gcSmiHandlerTemplate,\r
     gcSmiHandlerSize\r
     );\r
 }\r

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SyncTimer.c b/UefiCpuPkg/PiSmmCpuDxeSmm/SyncTimer.c
index 096ab323bbcf1ddabcc0a309f068219177b858d7..0c070c5736c6bfff9c9af244454f2e96313b8c52 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/SyncTimer.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SyncTimer.c
@@ -8,11 +8,11 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
 \r
 #include "PiSmmCpuDxeSmm.h"\r
 \r
-UINT64   mTimeoutTicker = 0;\r
+UINT64  mTimeoutTicker = 0;\r
 //\r
 //  Number of counts in a roll-over cycle of the performance counter.\r
 //\r
-UINT64   mCycle = 0;\r
+UINT64  mCycle = 0;\r
 //\r
 // Flag to indicate the performance counter is count-up or count-down.\r
 //\r
@@ -33,15 +33,15 @@ InitializeSmmTimer (
 \r
   TimerFrequency = GetPerformanceCounterProperties (&Start, &End);\r
   mTimeoutTicker = DivU64x32 (\r
-                     MultU64x64(TimerFrequency, PcdGet64 (PcdCpuSmmApSyncTimeout)),\r
+                     MultU64x64 (TimerFrequency, PcdGet64 (PcdCpuSmmApSyncTimeout)),\r
                      1000 * 1000\r
                      );\r
   if (End < Start) {\r
     mCountDown = TRUE;\r
-    mCycle = Start - End;\r
+    mCycle     = Start - End;\r
   } else {\r
     mCountDown = FALSE;\r
-    mCycle = End - Start;\r
+    mCycle     = End - Start;\r
   }\r
 }\r
 \r
@@ -58,7 +58,6 @@ StartSyncTimer (
   return GetPerformanceCounter ();\r
 }\r
 \r
-\r
 /**\r
   Check if the SMM AP Sync timer is timeout.\r
 \r
@@ -68,7 +67,7 @@ StartSyncTimer (
 BOOLEAN\r
 EFIAPI\r
 IsSyncTimerTimeout (\r
-  IN      UINT64                    Timer\r
+  IN      UINT64  Timer\r
   )\r
 {\r
   UINT64  CurrentTimer;\r
@@ -106,5 +105,5 @@ IsSyncTimerTimeout (
     }\r
   }\r
 \r
-  return (BOOLEAN) (Delta >= mTimeoutTicker);\r
+  return (BOOLEAN)(Delta >= mTimeoutTicker);\r
 }\r

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c
index 211a78b1c428c8b12b0923c2be1fc2979e1b5527..538394f2391050a132e34ebc97e8c233308ab15f 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c
@@ -10,16 +10,16 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
 \r
 #include "PiSmmCpuDxeSmm.h"\r
 \r
-#define PAGE_TABLE_PAGES            8\r
-#define ACC_MAX_BIT                 BIT3\r
+#define PAGE_TABLE_PAGES  8\r
+#define ACC_MAX_BIT       BIT3\r
 \r
-extern UINTN mSmmShadowStackSize;\r
+extern UINTN  mSmmShadowStackSize;\r
 \r
-LIST_ENTRY                          mPagePool = INITIALIZE_LIST_HEAD_VARIABLE (mPagePool);\r
-BOOLEAN                             m1GPageTableSupport = FALSE;\r
-BOOLEAN                             mCpuSmmRestrictedMemoryAccess;\r
-BOOLEAN                             m5LevelPagingNeeded;\r
-X86_ASSEMBLY_PATCH_LABEL            gPatch5LevelPagingNeeded;\r
+LIST_ENTRY                mPagePool           = INITIALIZE_LIST_HEAD_VARIABLE (mPagePool);\r
+BOOLEAN                   m1GPageTableSupport = FALSE;\r
+BOOLEAN                   mCpuSmmRestrictedMemoryAccess;\r
+BOOLEAN                   m5LevelPagingNeeded;\r
+X86_ASSEMBLY_PATCH_LABEL  gPatch5LevelPagingNeeded;\r
 \r
 /**\r
   Disable CET.\r
@@ -51,8 +51,8 @@ Is1GPageSupport (
   VOID\r
   )\r
 {\r
-  UINT32         RegEax;\r
-  UINT32         RegEdx;\r
+  UINT32  RegEax;\r
+  UINT32  RegEdx;\r
 \r
   AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);\r
   if (RegEax >= 0x80000001) {\r
@@ -61,6 +61,7 @@ Is1GPageSupport (
       return TRUE;\r
     }\r
   }\r
+\r
   return FALSE;\r
 }\r
 \r
@@ -78,9 +79,9 @@ Is5LevelPagingNeeded (
   VOID\r
   )\r
 {\r
-  CPUID_VIR_PHY_ADDRESS_SIZE_EAX              VirPhyAddressSize;\r
-  CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX ExtFeatureEcx;\r
-  UINT32                                      MaxExtendedFunctionId;\r
+  CPUID_VIR_PHY_ADDRESS_SIZE_EAX               VirPhyAddressSize;\r
+  CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX  ExtFeatureEcx;\r
+  UINT32                                       MaxExtendedFunctionId;\r
 \r
   AsmCpuid (CPUID_EXTENDED_FUNCTION, &MaxExtendedFunctionId, NULL, NULL, NULL);\r
   if (MaxExtendedFunctionId >= CPUID_VIR_PHY_ADDRESS_SIZE) {\r
@@ -88,14 +89,20 @@ Is5LevelPagingNeeded (
   } else {\r
     VirPhyAddressSize.Bits.PhysicalAddressBits = 36;\r
   }\r
+\r
   AsmCpuidEx (\r
     CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS,\r
     CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO,\r
-    NULL, NULL, &ExtFeatureEcx.Uint32, NULL\r
+    NULL,\r
+    NULL,\r
+    &ExtFeatureEcx.Uint32,\r
+    NULL\r
     );\r
   DEBUG ((\r
-    DEBUG_INFO, "PhysicalAddressBits = %d, 5LPageTable = %d.\n",\r
-    VirPhyAddressSize.Bits.PhysicalAddressBits, ExtFeatureEcx.Bits.FiveLevelPage\r
+    DEBUG_INFO,\r
+    "PhysicalAddressBits = %d, 5LPageTable = %d.\n",\r
+    VirPhyAddressSize.Bits.PhysicalAddressBits,\r
+    ExtFeatureEcx.Bits.FiveLevelPage\r
     ));\r
 \r
   if (VirPhyAddressSize.Bits.PhysicalAddressBits > 4 * 9 + 12) {\r
@@ -114,18 +121,19 @@ Is5LevelPagingNeeded (
 **/\r
 VOID\r
 GetPageTable (\r
-  OUT UINTN   *Base,\r
-  OUT BOOLEAN *FiveLevels OPTIONAL\r
+  OUT UINTN    *Base,\r
+  OUT BOOLEAN  *FiveLevels OPTIONAL\r
   )\r
 {\r
-  IA32_CR4 Cr4;\r
+  IA32_CR4  Cr4;\r
 \r
   if (mInternalCr3 == 0) {\r
     *Base = AsmReadCr3 () & PAGING_4K_ADDRESS_MASK_64;\r
     if (FiveLevels != NULL) {\r
-      Cr4.UintN = AsmReadCr4 ();\r
+      Cr4.UintN   = AsmReadCr4 ();\r
       *FiveLevels = (BOOLEAN)(Cr4.Bits.LA57 == 1);\r
     }\r
+\r
     return;\r
   }\r
 \r
@@ -146,8 +154,8 @@ GetPageTable (
 **/\r
 VOID\r
 SetSubEntriesNum (\r
-  IN OUT UINT64               *Entry,\r
-  IN     UINT64               SubEntryNum\r
+  IN OUT UINT64  *Entry,\r
+  IN     UINT64  SubEntryNum\r
   )\r
 {\r
   //\r
@@ -167,7 +175,7 @@ SetSubEntriesNum (
 **/\r
 UINT64\r
 GetSubEntriesNum (\r
-  IN UINT64            *Entry\r
+  IN UINT64  *Entry\r
   )\r
 {\r
   //\r
@@ -186,25 +194,26 @@ CalculateMaximumSupportAddress (
   VOID\r
   )\r
 {\r
-  UINT32                                        RegEax;\r
-  UINT8                                         PhysicalAddressBits;\r
-  VOID                                          *Hob;\r
+  UINT32  RegEax;\r
+  UINT8   PhysicalAddressBits;\r
+  VOID    *Hob;\r
 \r
   //\r
   // Get physical address bits supported.\r
   //\r
   Hob = GetFirstHob (EFI_HOB_TYPE_CPU);\r
   if (Hob != NULL) {\r
-    PhysicalAddressBits = ((EFI_HOB_CPU *) Hob)->SizeOfMemorySpace;\r
+    PhysicalAddressBits = ((EFI_HOB_CPU *)Hob)->SizeOfMemorySpace;\r
   } else {\r
     AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);\r
     if (RegEax >= 0x80000008) {\r
       AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);\r
-      PhysicalAddressBits = (UINT8) RegEax;\r
+      PhysicalAddressBits = (UINT8)RegEax;\r
     } else {\r
       PhysicalAddressBits = 36;\r
     }\r
   }\r
+\r
   return PhysicalAddressBits;\r
 }\r
 \r
@@ -216,54 +225,54 @@ CalculateMaximumSupportAddress (
 **/\r
 VOID\r
 SetStaticPageTable (\r
-  IN UINTN               PageTable,\r
-  IN UINT8               PhysicalAddressBits\r
+  IN UINTN  PageTable,\r
+  IN UINT8  PhysicalAddressBits\r
   )\r
 {\r
-  UINT64                                        PageAddress;\r
-  UINTN                                         NumberOfPml5EntriesNeeded;\r
-  UINTN                                         NumberOfPml4EntriesNeeded;\r
-  UINTN                                         NumberOfPdpEntriesNeeded;\r
-  UINTN                                         IndexOfPml5Entries;\r
-  UINTN                                         IndexOfPml4Entries;\r
-  UINTN                                         IndexOfPdpEntries;\r
-  UINTN                                         IndexOfPageDirectoryEntries;\r
-  UINT64                                        *PageMapLevel5Entry;\r
-  UINT64                                        *PageMapLevel4Entry;\r
-  UINT64                                        *PageMap;\r
-  UINT64                                        *PageDirectoryPointerEntry;\r
-  UINT64                                        *PageDirectory1GEntry;\r
-  UINT64                                        *PageDirectoryEntry;\r
+  UINT64  PageAddress;\r
+  UINTN   NumberOfPml5EntriesNeeded;\r
+  UINTN   NumberOfPml4EntriesNeeded;\r
+  UINTN   NumberOfPdpEntriesNeeded;\r
+  UINTN   IndexOfPml5Entries;\r
+  UINTN   IndexOfPml4Entries;\r
+  UINTN   IndexOfPdpEntries;\r
+  UINTN   IndexOfPageDirectoryEntries;\r
+  UINT64  *PageMapLevel5Entry;\r
+  UINT64  *PageMapLevel4Entry;\r
+  UINT64  *PageMap;\r
+  UINT64  *PageDirectoryPointerEntry;\r
+  UINT64  *PageDirectory1GEntry;\r
+  UINT64  *PageDirectoryEntry;\r
 \r
   //\r
   // IA-32e paging translates 48-bit linear addresses to 52-bit physical addresses\r
   //  when 5-Level Paging is disabled.\r
   //\r
   ASSERT (PhysicalAddressBits <= 52);\r
-  if (!m5LevelPagingNeeded && PhysicalAddressBits > 48) {\r
+  if (!m5LevelPagingNeeded && (PhysicalAddressBits > 48)) {\r
     PhysicalAddressBits = 48;\r
   }\r
 \r
   NumberOfPml5EntriesNeeded = 1;\r
   if (PhysicalAddressBits > 48) {\r
-    NumberOfPml5EntriesNeeded = (UINTN) LShiftU64 (1, PhysicalAddressBits - 48);\r
-    PhysicalAddressBits = 48;\r
+    NumberOfPml5EntriesNeeded = (UINTN)LShiftU64 (1, PhysicalAddressBits - 48);\r
+    PhysicalAddressBits       = 48;\r
   }\r
 \r
   NumberOfPml4EntriesNeeded = 1;\r
   if (PhysicalAddressBits > 39) {\r
-    NumberOfPml4EntriesNeeded = (UINTN) LShiftU64 (1, PhysicalAddressBits - 39);\r
-    PhysicalAddressBits = 39;\r
+    NumberOfPml4EntriesNeeded = (UINTN)LShiftU64 (1, PhysicalAddressBits - 39);\r
+    PhysicalAddressBits       = 39;\r
   }\r
 \r
   NumberOfPdpEntriesNeeded = 1;\r
   ASSERT (PhysicalAddressBits > 30);\r
-  NumberOfPdpEntriesNeeded = (UINTN) LShiftU64 (1, PhysicalAddressBits - 30);\r
+  NumberOfPdpEntriesNeeded = (UINTN)LShiftU64 (1, PhysicalAddressBits - 30);\r
 \r
   //\r
   // By architecture only one PageMapLevel4 exists - so lets allocate storage for it.\r
   //\r
-  PageMap         = (VOID *) PageTable;\r
+  PageMap = (VOID *)PageTable;\r
 \r
   PageMapLevel4Entry = PageMap;\r
   PageMapLevel5Entry = NULL;\r
@@ -273,22 +282,24 @@ SetStaticPageTable (
     //\r
     PageMapLevel5Entry = PageMap;\r
   }\r
-  PageAddress        = 0;\r
+\r
+  PageAddress = 0;\r
 \r
   for ( IndexOfPml5Entries = 0\r
-      ; IndexOfPml5Entries < NumberOfPml5EntriesNeeded\r
-      ; IndexOfPml5Entries++, PageMapLevel5Entry++) {\r
+        ; IndexOfPml5Entries < NumberOfPml5EntriesNeeded\r
+        ; IndexOfPml5Entries++, PageMapLevel5Entry++)\r
+  {\r
     //\r
     // Each PML5 entry points to a page of PML4 entires.\r
     // So lets allocate space for them and fill them in in the IndexOfPml4Entries loop.\r
     // When 5-Level Paging is disabled, below allocation happens only once.\r
     //\r
     if (m5LevelPagingNeeded) {\r
-      PageMapLevel4Entry = (UINT64 *) ((*PageMapLevel5Entry) & ~mAddressEncMask & gPhyMask);\r
+      PageMapLevel4Entry = (UINT64 *)((*PageMapLevel5Entry) & ~mAddressEncMask & gPhyMask);\r
       if (PageMapLevel4Entry == NULL) {\r
         PageMapLevel4Entry = AllocatePageTableMemory (1);\r
-        ASSERT(PageMapLevel4Entry != NULL);\r
-        ZeroMem (PageMapLevel4Entry, EFI_PAGES_TO_SIZE(1));\r
+        ASSERT (PageMapLevel4Entry != NULL);\r
+        ZeroMem (PageMapLevel4Entry, EFI_PAGES_TO_SIZE (1));\r
 \r
         *PageMapLevel5Entry = (UINT64)(UINTN)PageMapLevel4Entry | mAddressEncMask | PAGE_ATTRIBUTE_BITS;\r
       }\r
@@ -298,11 +309,11 @@ SetStaticPageTable (
       //\r
       // Each PML4 entry points to a page of Page Directory Pointer entries.\r
       //\r
-      PageDirectoryPointerEntry = (UINT64 *) ((*PageMapLevel4Entry) & ~mAddressEncMask & gPhyMask);\r
+      PageDirectoryPointerEntry = (UINT64 *)((*PageMapLevel4Entry) & ~mAddressEncMask & gPhyMask);\r
       if (PageDirectoryPointerEntry == NULL) {\r
         PageDirectoryPointerEntry = AllocatePageTableMemory (1);\r
-        ASSERT(PageDirectoryPointerEntry != NULL);\r
-        ZeroMem (PageDirectoryPointerEntry, EFI_PAGES_TO_SIZE(1));\r
+        ASSERT (PageDirectoryPointerEntry != NULL);\r
+        ZeroMem (PageDirectoryPointerEntry, EFI_PAGES_TO_SIZE (1));\r
 \r
         *PageMapLevel4Entry = (UINT64)(UINTN)PageDirectoryPointerEntry | mAddressEncMask | PAGE_ATTRIBUTE_BITS;\r
       }\r
@@ -310,12 +321,13 @@ SetStaticPageTable (
       if (m1GPageTableSupport) {\r
         PageDirectory1GEntry = PageDirectoryPointerEntry;\r
         for (IndexOfPageDirectoryEntries = 0; IndexOfPageDirectoryEntries < 512; IndexOfPageDirectoryEntries++, PageDirectory1GEntry++, PageAddress += SIZE_1GB) {\r
-          if (IndexOfPml4Entries == 0 && IndexOfPageDirectoryEntries < 4) {\r
+          if ((IndexOfPml4Entries == 0) && (IndexOfPageDirectoryEntries < 4)) {\r
             //\r
             // Skip the < 4G entries\r
             //\r
             continue;\r
           }\r
+\r
           //\r
           // Fill in the Page Directory entries\r
           //\r
@@ -324,21 +336,22 @@ SetStaticPageTable (
       } else {\r
         PageAddress = BASE_4GB;\r
         for (IndexOfPdpEntries = 0; IndexOfPdpEntries < (NumberOfPml4EntriesNeeded == 1 ? NumberOfPdpEntriesNeeded : 512); IndexOfPdpEntries++, PageDirectoryPointerEntry++) {\r
-          if (IndexOfPml4Entries == 0 && IndexOfPdpEntries < 4) {\r
+          if ((IndexOfPml4Entries == 0) && (IndexOfPdpEntries < 4)) {\r
             //\r
             // Skip the < 4G entries\r
             //\r
             continue;\r
           }\r
+\r
           //\r
           // Each Directory Pointer entries points to a page of Page Directory entires.\r
           // So allocate space for them and fill them in in the IndexOfPageDirectoryEntries loop.\r
           //\r
-          PageDirectoryEntry = (UINT64 *) ((*PageDirectoryPointerEntry) & ~mAddressEncMask & gPhyMask);\r
+          PageDirectoryEntry = (UINT64 *)((*PageDirectoryPointerEntry) & ~mAddressEncMask & gPhyMask);\r
           if (PageDirectoryEntry == NULL) {\r
             PageDirectoryEntry = AllocatePageTableMemory (1);\r
-            ASSERT(PageDirectoryEntry != NULL);\r
-            ZeroMem (PageDirectoryEntry, EFI_PAGES_TO_SIZE(1));\r
+            ASSERT (PageDirectoryEntry != NULL);\r
+            ZeroMem (PageDirectoryEntry, EFI_PAGES_TO_SIZE (1));\r
 \r
             //\r
             // Fill in a Page Directory Pointer Entries\r
@@ -369,15 +382,15 @@ SmmInitPageTable (
   VOID\r
   )\r
 {\r
-  EFI_PHYSICAL_ADDRESS              Pages;\r
-  UINT64                            *PTEntry;\r
-  LIST_ENTRY                        *FreePage;\r
-  UINTN                             Index;\r
-  UINTN                             PageFaultHandlerHookAddress;\r
-  IA32_IDT_GATE_DESCRIPTOR          *IdtEntry;\r
-  EFI_STATUS                        Status;\r
-  UINT64                            *Pml4Entry;\r
-  UINT64                            *Pml5Entry;\r
+  EFI_PHYSICAL_ADDRESS      Pages;\r
+  UINT64                    *PTEntry;\r
+  LIST_ENTRY                *FreePage;\r
+  UINTN                     Index;\r
+  UINTN                     PageFaultHandlerHookAddress;\r
+  IA32_IDT_GATE_DESCRIPTOR  *IdtEntry;\r
+  EFI_STATUS                Status;\r
+  UINT64                    *Pml4Entry;\r
+  UINT64                    *Pml5Entry;\r
 \r
   //\r
   // Initialize spin lock\r
@@ -401,7 +414,7 @@ SmmInitPageTable (
   //\r
   // Set IA32_PG_PMNT bit to mask this entry\r
   //\r
-  PTEntry = (UINT64*)(UINTN)Pages;\r
+  PTEntry = (UINT64 *)(UINTN)Pages;\r
   for (Index = 0; Index < 4; Index++) {\r
     PTEntry[Index] |= IA32_PG_PMNT;\r
   }\r
@@ -409,7 +422,7 @@ SmmInitPageTable (
   //\r
   // Fill Page-Table-Level4 (PML4) entry\r
   //\r
-  Pml4Entry = (UINT64*)AllocatePageTableMemory (1);\r
+  Pml4Entry = (UINT64 *)AllocatePageTableMemory (1);\r
   ASSERT (Pml4Entry != NULL);\r
   *Pml4Entry = Pages | mAddressEncMask | PAGE_ATTRIBUTE_BITS;\r
   ZeroMem (Pml4Entry + 1, EFI_PAGE_SIZE - sizeof (*Pml4Entry));\r
@@ -424,9 +437,9 @@ SmmInitPageTable (
     //\r
     // Fill PML5 entry\r
     //\r
-    Pml5Entry = (UINT64*)AllocatePageTableMemory (1);\r
+    Pml5Entry = (UINT64 *)AllocatePageTableMemory (1);\r
     ASSERT (Pml5Entry != NULL);\r
-    *Pml5Entry = (UINTN) Pml4Entry | mAddressEncMask | PAGE_ATTRIBUTE_BITS;\r
+    *Pml5Entry = (UINTN)Pml4Entry | mAddressEncMask | PAGE_ATTRIBUTE_BITS;\r
     ZeroMem (Pml5Entry + 1, EFI_PAGE_SIZE - sizeof (*Pml5Entry));\r
     //\r
     // Set sub-entries number\r
@@ -445,7 +458,7 @@ SmmInitPageTable (
     //\r
     // Add pages to page pool\r
     //\r
-    FreePage = (LIST_ENTRY*)AllocatePageTableMemory (PAGE_TABLE_PAGES);\r
+    FreePage = (LIST_ENTRY *)AllocatePageTableMemory (PAGE_TABLE_PAGES);\r
     ASSERT (FreePage != NULL);\r
     for (Index = 0; Index < PAGE_TABLE_PAGES; Index++) {\r
       InsertTailList (&mPagePool, FreePage);\r
@@ -455,20 +468,21 @@ SmmInitPageTable (
 \r
   if (FeaturePcdGet (PcdCpuSmmProfileEnable) ||\r
       HEAP_GUARD_NONSTOP_MODE ||\r
-      NULL_DETECTION_NONSTOP_MODE) {\r
+      NULL_DETECTION_NONSTOP_MODE)\r
+  {\r
     //\r
     // Set own Page Fault entry instead of the default one, because SMM Profile\r
     // feature depends on IRET instruction to do Single Step\r
     //\r
     PageFaultHandlerHookAddress = (UINTN)PageFaultIdtHandlerSmmProfile;\r
-    IdtEntry  = (IA32_IDT_GATE_DESCRIPTOR *) gcSmiIdtr.Base;\r
-    IdtEntry += EXCEPT_IA32_PAGE_FAULT;\r
-    IdtEntry->Bits.OffsetLow      = (UINT16)PageFaultHandlerHookAddress;\r
-    IdtEntry->Bits.Reserved_0     = 0;\r
-    IdtEntry->Bits.GateType       = IA32_IDT_GATE_TYPE_INTERRUPT_32;\r
-    IdtEntry->Bits.OffsetHigh     = (UINT16)(PageFaultHandlerHookAddress >> 16);\r
-    IdtEntry->Bits.OffsetUpper    = (UINT32)(PageFaultHandlerHookAddress >> 32);\r
-    IdtEntry->Bits.Reserved_1     = 0;\r
+    IdtEntry                    = (IA32_IDT_GATE_DESCRIPTOR *)gcSmiIdtr.Base;\r
+    IdtEntry                   += EXCEPT_IA32_PAGE_FAULT;\r
+    IdtEntry->Bits.OffsetLow    = (UINT16)PageFaultHandlerHookAddress;\r
+    IdtEntry->Bits.Reserved_0   = 0;\r
+    IdtEntry->Bits.GateType     = IA32_IDT_GATE_TYPE_INTERRUPT_32;\r
+    IdtEntry->Bits.OffsetHigh   = (UINT16)(PageFaultHandlerHookAddress >> 16);\r
+    IdtEntry->Bits.OffsetUpper  = (UINT32)(PageFaultHandlerHookAddress >> 32);\r
+    IdtEntry->Bits.Reserved_1   = 0;\r
   } else {\r
     //\r
     // Register Smm Page Fault Handler\r
@@ -509,8 +523,8 @@ SmmInitPageTable (
 **/\r
 VOID\r
 SetAccNum (\r
-  IN OUT UINT64               *Entry,\r
-  IN     UINT64               Acc\r
+  IN OUT UINT64  *Entry,\r
+  IN     UINT64  Acc\r
   )\r
 {\r
   //\r
@@ -529,7 +543,7 @@ SetAccNum (
 **/\r
 UINT64\r
 GetAccNum (\r
-  IN UINT64            *Entry\r
+  IN UINT64  *Entry\r
   )\r
 {\r
   //\r
@@ -548,10 +562,10 @@ GetAccNum (
 **/\r
 UINT64\r
 GetAndUpdateAccNum (\r
-  IN OUT UINT64      *Entry\r
+  IN OUT UINT64  *Entry\r
   )\r
 {\r
-  UINT64         Acc;\r
+  UINT64  Acc;\r
 \r
   Acc = GetAccNum (Entry);\r
   if ((*Entry & IA32_PG_A) != 0) {\r
@@ -570,6 +584,7 @@ GetAndUpdateAccNum (
       SetAccNum (Entry, Acc - 1);\r
     }\r
   }\r
+\r
   return Acc;\r
 }\r
 \r
@@ -587,84 +602,86 @@ ReclaimPages (
   VOID\r
   )\r
 {\r
-  UINT64                       Pml5Entry;\r
-  UINT64                       *Pml5;\r
-  UINT64                       *Pml4;\r
-  UINT64                       *Pdpt;\r
-  UINT64                       *Pdt;\r
-  UINTN                        Pml5Index;\r
-  UINTN                        Pml4Index;\r
-  UINTN                        PdptIndex;\r
-  UINTN                        PdtIndex;\r
-  UINTN                        MinPml5;\r
-  UINTN                        MinPml4;\r
-  UINTN                        MinPdpt;\r
-  UINTN                        MinPdt;\r
-  UINT64                       MinAcc;\r
-  UINT64                       Acc;\r
-  UINT64                       SubEntriesNum;\r
-  BOOLEAN                      PML4EIgnore;\r
-  BOOLEAN                      PDPTEIgnore;\r
-  UINT64                       *ReleasePageAddress;\r
-  IA32_CR4                     Cr4;\r
-  BOOLEAN                      Enable5LevelPaging;\r
-  UINT64                       PFAddress;\r
-  UINT64                       PFAddressPml5Index;\r
-  UINT64                       PFAddressPml4Index;\r
-  UINT64                       PFAddressPdptIndex;\r
-  UINT64                       PFAddressPdtIndex;\r
-\r
-  Pml4 = NULL;\r
-  Pdpt = NULL;\r
-  Pdt  = NULL;\r
-  MinAcc  = (UINT64)-1;\r
-  MinPml4 = (UINTN)-1;\r
-  MinPml5 = (UINTN)-1;\r
-  MinPdpt = (UINTN)-1;\r
-  MinPdt  = (UINTN)-1;\r
-  Acc     = 0;\r
+  UINT64    Pml5Entry;\r
+  UINT64    *Pml5;\r
+  UINT64    *Pml4;\r
+  UINT64    *Pdpt;\r
+  UINT64    *Pdt;\r
+  UINTN     Pml5Index;\r
+  UINTN     Pml4Index;\r
+  UINTN     PdptIndex;\r
+  UINTN     PdtIndex;\r
+  UINTN     MinPml5;\r
+  UINTN     MinPml4;\r
+  UINTN     MinPdpt;\r
+  UINTN     MinPdt;\r
+  UINT64    MinAcc;\r
+  UINT64    Acc;\r
+  UINT64    SubEntriesNum;\r
+  BOOLEAN   PML4EIgnore;\r
+  BOOLEAN   PDPTEIgnore;\r
+  UINT64    *ReleasePageAddress;\r
+  IA32_CR4  Cr4;\r
+  BOOLEAN   Enable5LevelPaging;\r
+  UINT64    PFAddress;\r
+  UINT64    PFAddressPml5Index;\r
+  UINT64    PFAddressPml4Index;\r
+  UINT64    PFAddressPdptIndex;\r
+  UINT64    PFAddressPdtIndex;\r
+\r
+  Pml4               = NULL;\r
+  Pdpt               = NULL;\r
+  Pdt                = NULL;\r
+  MinAcc             = (UINT64)-1;\r
+  MinPml4            = (UINTN)-1;\r
+  MinPml5            = (UINTN)-1;\r
+  MinPdpt            = (UINTN)-1;\r
+  MinPdt             = (UINTN)-1;\r
+  Acc                = 0;\r
   ReleasePageAddress = 0;\r
-  PFAddress = AsmReadCr2 ();\r
+  PFAddress          = AsmReadCr2 ();\r
   PFAddressPml5Index = BitFieldRead64 (PFAddress, 48, 48 + 8);\r
   PFAddressPml4Index = BitFieldRead64 (PFAddress, 39, 39 + 8);\r
   PFAddressPdptIndex = BitFieldRead64 (PFAddress, 30, 30 + 8);\r
-  PFAddressPdtIndex = BitFieldRead64 (PFAddress, 21, 21 + 8);\r
+  PFAddressPdtIndex  = BitFieldRead64 (PFAddress, 21, 21 + 8);\r
 \r
-  Cr4.UintN = AsmReadCr4 ();\r
-  Enable5LevelPaging = (BOOLEAN) (Cr4.Bits.LA57 == 1);\r
-  Pml5 = (UINT64*)(UINTN)(AsmReadCr3 () & gPhyMask);\r
+  Cr4.UintN          = AsmReadCr4 ();\r
+  Enable5LevelPaging = (BOOLEAN)(Cr4.Bits.LA57 == 1);\r
+  Pml5               = (UINT64 *)(UINTN)(AsmReadCr3 () & gPhyMask);\r
 \r
   if (!Enable5LevelPaging) {\r
     //\r
     // Create one fake PML5 entry for 4-Level Paging\r
     // so that the page table parsing logic only handles 5-Level page structure.\r
     //\r
-    Pml5Entry = (UINTN) Pml5 | IA32_PG_P;\r
-    Pml5 = &Pml5Entry;\r
+    Pml5Entry = (UINTN)Pml5 | IA32_PG_P;\r
+    Pml5      = &Pml5Entry;\r
   }\r
 \r
   //\r
   // First, find the leaf entry has the smallest access record value\r
   //\r
   for (Pml5Index = 0; Pml5Index < (Enable5LevelPaging ? (EFI_PAGE_SIZE / sizeof (*Pml4)) : 1); Pml5Index++) {\r
-    if ((Pml5[Pml5Index] & IA32_PG_P) == 0 || (Pml5[Pml5Index] & IA32_PG_PMNT) != 0) {\r
+    if (((Pml5[Pml5Index] & IA32_PG_P) == 0) || ((Pml5[Pml5Index] & IA32_PG_PMNT) != 0)) {\r
       //\r
       // If the PML5 entry is not present or is masked, skip it\r
       //\r
       continue;\r
     }\r
-    Pml4 = (UINT64*)(UINTN)(Pml5[Pml5Index] & gPhyMask);\r
+\r
+    Pml4 = (UINT64 *)(UINTN)(Pml5[Pml5Index] & gPhyMask);\r
     for (Pml4Index = 0; Pml4Index < EFI_PAGE_SIZE / sizeof (*Pml4); Pml4Index++) {\r
-      if ((Pml4[Pml4Index] & IA32_PG_P) == 0 || (Pml4[Pml4Index] & IA32_PG_PMNT) != 0) {\r
+      if (((Pml4[Pml4Index] & IA32_PG_P) == 0) || ((Pml4[Pml4Index] & IA32_PG_PMNT) != 0)) {\r
         //\r
         // If the PML4 entry is not present or is masked, skip it\r
         //\r
         continue;\r
       }\r
-      Pdpt = (UINT64*)(UINTN)(Pml4[Pml4Index] & ~mAddressEncMask & gPhyMask);\r
+\r
+      Pdpt        = (UINT64 *)(UINTN)(Pml4[Pml4Index] & ~mAddressEncMask & gPhyMask);\r
       PML4EIgnore = FALSE;\r
       for (PdptIndex = 0; PdptIndex < EFI_PAGE_SIZE / sizeof (*Pdpt); PdptIndex++) {\r
-        if ((Pdpt[PdptIndex] & IA32_PG_P) == 0 || (Pdpt[PdptIndex] & IA32_PG_PMNT) != 0) {\r
+        if (((Pdpt[PdptIndex] & IA32_PG_P) == 0) || ((Pdpt[PdptIndex] & IA32_PG_PMNT) != 0)) {\r
           //\r
           // If the PDPT entry is not present or is masked, skip it\r
           //\r
@@ -674,18 +691,20 @@ ReclaimPages (
             //\r
             PML4EIgnore = TRUE;\r
           }\r
+\r
           continue;\r
         }\r
+\r
         if ((Pdpt[PdptIndex] & IA32_PG_PS) == 0) {\r
           //\r
           // It's not 1-GByte pages entry, it should be a PDPT entry,\r
           // we will not check PML4 entry more\r
           //\r
           PML4EIgnore = TRUE;\r
-          Pdt = (UINT64*)(UINTN)(Pdpt[PdptIndex] & ~mAddressEncMask & gPhyMask);\r
+          Pdt         = (UINT64 *)(UINTN)(Pdpt[PdptIndex] & ~mAddressEncMask & gPhyMask);\r
           PDPTEIgnore = FALSE;\r
-          for (PdtIndex = 0; PdtIndex < EFI_PAGE_SIZE / sizeof(*Pdt); PdtIndex++) {\r
-            if ((Pdt[PdtIndex] & IA32_PG_P) == 0 || (Pdt[PdtIndex] & IA32_PG_PMNT) != 0) {\r
+          for (PdtIndex = 0; PdtIndex < EFI_PAGE_SIZE / sizeof (*Pdt); PdtIndex++) {\r
+            if (((Pdt[PdtIndex] & IA32_PG_P) == 0) || ((Pdt[PdtIndex] & IA32_PG_PMNT) != 0)) {\r
               //\r
               // If the PD entry is not present or is masked, skip it\r
               //\r
@@ -695,79 +714,86 @@ ReclaimPages (
                 //\r
                 PDPTEIgnore = TRUE;\r
               }\r
+\r
               continue;\r
             }\r
+\r
             if ((Pdt[PdtIndex] & IA32_PG_PS) == 0) {\r
               //\r
               // It's not 2 MByte page table entry, it should be PD entry\r
               // we will find the entry has the smallest access record value\r
               //\r
               PDPTEIgnore = TRUE;\r
-              if (PdtIndex != PFAddressPdtIndex || PdptIndex != PFAddressPdptIndex ||\r
-                  Pml4Index != PFAddressPml4Index || Pml5Index != PFAddressPml5Index) {\r
+              if ((PdtIndex != PFAddressPdtIndex) || (PdptIndex != PFAddressPdptIndex) ||\r
+                  (Pml4Index != PFAddressPml4Index) || (Pml5Index != PFAddressPml5Index))\r
+              {\r
                 Acc = GetAndUpdateAccNum (Pdt + PdtIndex);\r
                 if (Acc < MinAcc) {\r
                   //\r
                   // If the PD entry has the smallest access record value,\r
                   // save the Page address to be released\r
                   //\r
-                  MinAcc  = Acc;\r
-                  MinPml5 = Pml5Index;\r
-                  MinPml4 = Pml4Index;\r
-                  MinPdpt = PdptIndex;\r
-                  MinPdt  = PdtIndex;\r
+                  MinAcc             = Acc;\r
+                  MinPml5            = Pml5Index;\r
+                  MinPml4            = Pml4Index;\r
+                  MinPdpt            = PdptIndex;\r
+                  MinPdt             = PdtIndex;\r
                   ReleasePageAddress = Pdt + PdtIndex;\r
                 }\r
               }\r
             }\r
           }\r
+\r
           if (!PDPTEIgnore) {\r
             //\r
             // If this PDPT entry has no PDT entries pointer to 4 KByte pages,\r
             // it should only has the entries point to 2 MByte Pages\r
             //\r
-            if (PdptIndex != PFAddressPdptIndex || Pml4Index != PFAddressPml4Index ||\r
-                Pml5Index != PFAddressPml5Index) {\r
+            if ((PdptIndex != PFAddressPdptIndex) || (Pml4Index != PFAddressPml4Index) ||\r
+                (Pml5Index != PFAddressPml5Index))\r
+            {\r
               Acc = GetAndUpdateAccNum (Pdpt + PdptIndex);\r
               if (Acc < MinAcc) {\r
                 //\r
                 // If the PDPT entry has the smallest access record value,\r
                 // save the Page address to be released\r
                 //\r
-                MinAcc  = Acc;\r
-                MinPml5 = Pml5Index;\r
-                MinPml4 = Pml4Index;\r
-                MinPdpt = PdptIndex;\r
-                MinPdt  = (UINTN)-1;\r
+                MinAcc             = Acc;\r
+                MinPml5            = Pml5Index;\r
+                MinPml4            = Pml4Index;\r
+                MinPdpt            = PdptIndex;\r
+                MinPdt             = (UINTN)-1;\r
                 ReleasePageAddress = Pdpt + PdptIndex;\r
               }\r
             }\r
           }\r
         }\r
       }\r
+\r
       if (!PML4EIgnore) {\r
         //\r
         // If PML4 entry has no the PDPT entry pointer to 2 MByte pages,\r
         // it should only has the entries point to 1 GByte Pages\r
         //\r
-        if (Pml4Index != PFAddressPml4Index || Pml5Index != PFAddressPml5Index) {\r
+        if ((Pml4Index != PFAddressPml4Index) || (Pml5Index != PFAddressPml5Index)) {\r
           Acc = GetAndUpdateAccNum (Pml4 + Pml4Index);\r
           if (Acc < MinAcc) {\r
             //\r
             // If the PML4 entry has the smallest access record value,\r
             // save the Page address to be released\r
             //\r
-            MinAcc  = Acc;\r
-            MinPml5 = Pml5Index;\r
-            MinPml4 = Pml4Index;\r
-            MinPdpt = (UINTN)-1;\r
-            MinPdt  = (UINTN)-1;\r
+            MinAcc             = Acc;\r
+            MinPml5            = Pml5Index;\r
+            MinPml4            = Pml4Index;\r
+            MinPdpt            = (UINTN)-1;\r
+            MinPdt             = (UINTN)-1;\r
             ReleasePageAddress = Pml4 + Pml4Index;\r
           }\r
         }\r
       }\r
     }\r
   }\r
+\r
   //\r
   // Make sure one PML4/PDPT/PD entry is selected\r
   //\r
@@ -776,7 +802,7 @@ ReclaimPages (
   //\r
   // Secondly, insert the page pointed by this entry into page pool and clear this entry\r
   //\r
-  InsertTailList (&mPagePool, (LIST_ENTRY*)(UINTN)(*ReleasePageAddress & ~mAddressEncMask & gPhyMask));\r
+  InsertTailList (&mPagePool, (LIST_ENTRY *)(UINTN)(*ReleasePageAddress & ~mAddressEncMask & gPhyMask));\r
   *ReleasePageAddress = 0;\r
 \r
   //\r
@@ -788,16 +814,17 @@ ReclaimPages (
       //\r
       // If 4 KByte Page Table is released, check the PDPT entry\r
       //\r
-      Pml4 = (UINT64 *) (UINTN) (Pml5[MinPml5] & gPhyMask);\r
-      Pdpt = (UINT64*)(UINTN)(Pml4[MinPml4] & ~mAddressEncMask & gPhyMask);\r
-      SubEntriesNum = GetSubEntriesNum(Pdpt + MinPdpt);\r
-      if (SubEntriesNum == 0 &&\r
-          (MinPdpt != PFAddressPdptIndex || MinPml4 != PFAddressPml4Index || MinPml5 != PFAddressPml5Index)) {\r
+      Pml4          = (UINT64 *)(UINTN)(Pml5[MinPml5] & gPhyMask);\r
+      Pdpt          = (UINT64 *)(UINTN)(Pml4[MinPml4] & ~mAddressEncMask & gPhyMask);\r
+      SubEntriesNum = GetSubEntriesNum (Pdpt + MinPdpt);\r
+      if ((SubEntriesNum == 0) &&\r
+          ((MinPdpt != PFAddressPdptIndex) || (MinPml4 != PFAddressPml4Index) || (MinPml5 != PFAddressPml5Index)))\r
+      {\r
         //\r
         // Release the empty Page Directory table if there was no more 4 KByte Page Table entry\r
         // clear the Page directory entry\r
         //\r
-        InsertTailList (&mPagePool, (LIST_ENTRY*)(UINTN)(Pdpt[MinPdpt] & ~mAddressEncMask & gPhyMask));\r
+        InsertTailList (&mPagePool, (LIST_ENTRY *)(UINTN)(Pdpt[MinPdpt] & ~mAddressEncMask & gPhyMask));\r
         Pdpt[MinPdpt] = 0;\r
         //\r
         // Go on checking the PML4 table\r
@@ -805,33 +832,37 @@ ReclaimPages (
         MinPdt = (UINTN)-1;\r
         continue;\r
       }\r
+\r
       //\r
       // Update the sub-entries filed in PDPT entry and exit\r
       //\r
       SetSubEntriesNum (Pdpt + MinPdpt, (SubEntriesNum - 1) & 0x1FF);\r
       break;\r
     }\r
+\r
     if (MinPdpt != (UINTN)-1) {\r
       //\r
       // One 2MB Page Table is released or Page Directory table is released, check the PML4 entry\r
       //\r
       SubEntriesNum = GetSubEntriesNum (Pml4 + MinPml4);\r
-      if (SubEntriesNum == 0 && (MinPml4 != PFAddressPml4Index || MinPml5 != PFAddressPml5Index)) {\r
+      if ((SubEntriesNum == 0) && ((MinPml4 != PFAddressPml4Index) || (MinPml5 != PFAddressPml5Index))) {\r
         //\r
         // Release the empty PML4 table if there was no more 1G KByte Page Table entry\r
         // clear the Page directory entry\r
         //\r
-        InsertTailList (&mPagePool, (LIST_ENTRY*)(UINTN)(Pml4[MinPml4] & ~mAddressEncMask & gPhyMask));\r
+        InsertTailList (&mPagePool, (LIST_ENTRY *)(UINTN)(Pml4[MinPml4] & ~mAddressEncMask & gPhyMask));\r
         Pml4[MinPml4] = 0;\r
-        MinPdpt = (UINTN)-1;\r
+        MinPdpt       = (UINTN)-1;\r
         continue;\r
       }\r
+\r
       //\r
       // Update the sub-entries filed in PML4 entry and exit\r
       //\r
       SetSubEntriesNum (Pml4 + MinPml4, (SubEntriesNum - 1) & 0x1FF);\r
       break;\r
     }\r
+\r
     //\r
     // PLM4 table has been released before, exit it\r
     //\r
@@ -850,7 +881,7 @@ AllocPage (
   VOID\r
   )\r
 {\r
-  UINT64                            RetVal;\r
+  UINT64  RetVal;\r
 \r
   if (IsListEmpty (&mPagePool)) {\r
     //\r
@@ -867,7 +898,7 @@ AllocPage (
   //\r
   // Clean this page and return\r
   //\r
-  ZeroMem ((VOID*)(UINTN)RetVal, EFI_PAGE_SIZE);\r
+  ZeroMem ((VOID *)(UINTN)RetVal, EFI_PAGE_SIZE);\r
   return RetVal;\r
 }\r
 \r
@@ -880,78 +911,81 @@ SmiDefaultPFHandler (
   VOID\r
   )\r
 {\r
-  UINT64                            *PageTable;\r
-  UINT64                            *PageTableTop;\r
-  UINT64                            PFAddress;\r
-  UINTN                             StartBit;\r
-  UINTN                             EndBit;\r
-  UINT64                            PTIndex;\r
-  UINTN                             Index;\r
-  SMM_PAGE_SIZE_TYPE                PageSize;\r
-  UINTN                             NumOfPages;\r
-  UINTN                             PageAttribute;\r
-  EFI_STATUS                        Status;\r
-  UINT64                            *UpperEntry;\r
-  BOOLEAN                           Enable5LevelPaging;\r
-  IA32_CR4                          Cr4;\r
+  UINT64              *PageTable;\r
+  UINT64              *PageTableTop;\r
+  UINT64              PFAddress;\r
+  UINTN               StartBit;\r
+  UINTN               EndBit;\r
+  UINT64              PTIndex;\r
+  UINTN               Index;\r
+  SMM_PAGE_SIZE_TYPE  PageSize;\r
+  UINTN               NumOfPages;\r
+  UINTN               PageAttribute;\r
+  EFI_STATUS          Status;\r
+  UINT64              *UpperEntry;\r
+  BOOLEAN             Enable5LevelPaging;\r
+  IA32_CR4            Cr4;\r
 \r
   //\r
   // Set default SMM page attribute\r
   //\r
-  PageSize = SmmPageSize2M;\r
-  NumOfPages = 1;\r
+  PageSize      = SmmPageSize2M;\r
+  NumOfPages    = 1;\r
   PageAttribute = 0;\r
 \r
-  EndBit = 0;\r
-  PageTableTop = (UINT64*)(AsmReadCr3 () & gPhyMask);\r
-  PFAddress = AsmReadCr2 ();\r
+  EndBit       = 0;\r
+  PageTableTop = (UINT64 *)(AsmReadCr3 () & gPhyMask);\r
+  PFAddress    = AsmReadCr2 ();\r
 \r
-  Cr4.UintN = AsmReadCr4 ();\r
-  Enable5LevelPaging = (BOOLEAN) (Cr4.Bits.LA57 != 0);\r
+  Cr4.UintN          = AsmReadCr4 ();\r
+  Enable5LevelPaging = (BOOLEAN)(Cr4.Bits.LA57 != 0);\r
 \r
   Status = GetPlatformPageTableAttribute (PFAddress, &PageSize, &NumOfPages, &PageAttribute);\r
   //\r
   // If platform not support page table attribute, set default SMM page attribute\r
   //\r
   if (Status != EFI_SUCCESS) {\r
-    PageSize = SmmPageSize2M;\r
-    NumOfPages = 1;\r
+    PageSize      = SmmPageSize2M;\r
+    NumOfPages    = 1;\r
     PageAttribute = 0;\r
   }\r
+\r
   if (PageSize >= MaxSmmPageSizeType) {\r
     PageSize = SmmPageSize2M;\r
   }\r
+\r
   if (NumOfPages > 512) {\r
     NumOfPages = 512;\r
   }\r
 \r
   switch (PageSize) {\r
-  case SmmPageSize4K:\r
-    //\r
-    // BIT12 to BIT20 is Page Table index\r
-    //\r
-    EndBit = 12;\r
-    break;\r
-  case SmmPageSize2M:\r
-    //\r
-    // BIT21 to BIT29 is Page Directory index\r
-    //\r
-    EndBit = 21;\r
-    PageAttribute |= (UINTN)IA32_PG_PS;\r
-    break;\r
-  case SmmPageSize1G:\r
-    if (!m1GPageTableSupport) {\r
-      DEBUG ((DEBUG_ERROR, "1-GByte pages is not supported!"));\r
+    case SmmPageSize4K:\r
+      //\r
+      // BIT12 to BIT20 is Page Table index\r
+      //\r
+      EndBit = 12;\r
+      break;\r
+    case SmmPageSize2M:\r
+      //\r
+      // BIT21 to BIT29 is Page Directory index\r
+      //\r
+      EndBit         = 21;\r
+      PageAttribute |= (UINTN)IA32_PG_PS;\r
+      break;\r
+    case SmmPageSize1G:\r
+      if (!m1GPageTableSupport) {\r
+        DEBUG ((DEBUG_ERROR, "1-GByte pages is not supported!"));\r
+        ASSERT (FALSE);\r
+      }\r
+\r
+      //\r
+      // BIT30 to BIT38 is Page Directory Pointer Table index\r
+      //\r
+      EndBit         = 30;\r
+      PageAttribute |= (UINTN)IA32_PG_PS;\r
+      break;\r
+    default:\r
       ASSERT (FALSE);\r
-    }\r
-    //\r
-    // BIT30 to BIT38 is Page Directory Pointer Table index\r
-    //\r
-    EndBit = 30;\r
-    PageAttribute |= (UINTN)IA32_PG_PS;\r
-    break;\r
-  default:\r
-    ASSERT (FALSE);\r
   }\r
 \r
   //\r
@@ -977,13 +1011,14 @@ SmiDefaultPFHandler (
         //\r
         UpperEntry = PageTable + PTIndex;\r
       }\r
+\r
       //\r
       // BIT9 to BIT11 of entry is used to save access record,\r
       // initialize value is 7\r
       //\r
       PageTable[PTIndex] |= (UINT64)IA32_PG_A;\r
       SetAccNum (PageTable + PTIndex, 7);\r
-      PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask & gPhyMask);\r
+      PageTable = (UINT64 *)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask & gPhyMask);\r
     }\r
 \r
     PTIndex = BitFieldRead64 (PFAddress, StartBit, StartBit + 8);\r
@@ -996,6 +1031,7 @@ SmiDefaultPFHandler (
       DEBUG ((DEBUG_ERROR, "New page table overlapped with old page table!\n"));\r
       ASSERT (FALSE);\r
     }\r
+\r
     //\r
     // Fill the new entry\r
     //\r
@@ -1004,6 +1040,7 @@ SmiDefaultPFHandler (
     if (UpperEntry != NULL) {\r
       SetSubEntriesNum (UpperEntry, (GetSubEntriesNum (UpperEntry) + 1) & 0x1FF);\r
     }\r
+\r
     //\r
     // Get the next page address if we need to create more page tables\r
     //\r
@@ -1022,14 +1059,14 @@ SmiDefaultPFHandler (
 VOID\r
 EFIAPI\r
 SmiPFHandler (\r
-  IN EFI_EXCEPTION_TYPE   InterruptType,\r
-  IN EFI_SYSTEM_CONTEXT   SystemContext\r
+  IN EFI_EXCEPTION_TYPE  InterruptType,\r
+  IN EFI_SYSTEM_CONTEXT  SystemContext\r
   )\r
 {\r
-  UINTN             PFAddress;\r
-  UINTN             GuardPageAddress;\r
-  UINTN             ShadowStackGuardPageAddress;\r
-  UINTN             CpuIndex;\r
+  UINTN  PFAddress;\r
+  UINTN  GuardPageAddress;\r
+  UINTN  ShadowStackGuardPageAddress;\r
+  UINTN  CpuIndex;\r
 \r
   ASSERT (InterruptType == EXCEPT_IA32_PAGE_FAULT);\r
 \r
@@ -1049,31 +1086,34 @@ SmiPFHandler (
   // or SMM page protection violation.\r
   //\r
   if ((PFAddress >= mCpuHotPlugData.SmrrBase) &&\r
-      (PFAddress < (mCpuHotPlugData.SmrrBase + mCpuHotPlugData.SmrrSize))) {\r
+      (PFAddress < (mCpuHotPlugData.SmrrBase + mCpuHotPlugData.SmrrSize)))\r
+  {\r
     DumpCpuContext (InterruptType, SystemContext);\r
-    CpuIndex = GetCpuIndex ();\r
-    GuardPageAddress = (mSmmStackArrayBase + EFI_PAGE_SIZE + CpuIndex * (mSmmStackSize + mSmmShadowStackSize));\r
+    CpuIndex                    = GetCpuIndex ();\r
+    GuardPageAddress            = (mSmmStackArrayBase + EFI_PAGE_SIZE + CpuIndex * (mSmmStackSize + mSmmShadowStackSize));\r
     ShadowStackGuardPageAddress = (mSmmStackArrayBase + mSmmStackSize + EFI_PAGE_SIZE + CpuIndex * (mSmmStackSize + mSmmShadowStackSize));\r
     if ((FeaturePcdGet (PcdCpuSmmStackGuard)) &&\r
         (PFAddress >= GuardPageAddress) &&\r
-        (PFAddress < (GuardPageAddress + EFI_PAGE_SIZE))) {\r
+        (PFAddress < (GuardPageAddress + EFI_PAGE_SIZE)))\r
+    {\r
       DEBUG ((DEBUG_ERROR, "SMM stack overflow!\n"));\r
     } else if ((FeaturePcdGet (PcdCpuSmmStackGuard)) &&\r
-        (mSmmShadowStackSize > 0) &&\r
-        (PFAddress >= ShadowStackGuardPageAddress) &&\r
-        (PFAddress < (ShadowStackGuardPageAddress + EFI_PAGE_SIZE))) {\r
+               (mSmmShadowStackSize > 0) &&\r
+               (PFAddress >= ShadowStackGuardPageAddress) &&\r
+               (PFAddress < (ShadowStackGuardPageAddress + EFI_PAGE_SIZE)))\r
+    {\r
       DEBUG ((DEBUG_ERROR, "SMM shadow stack overflow!\n"));\r
     } else {\r
       if ((SystemContext.SystemContextX64->ExceptionData & IA32_PF_EC_ID) != 0) {\r
         DEBUG ((DEBUG_ERROR, "SMM exception at execution (0x%lx)\n", PFAddress));\r
         DEBUG_CODE (\r
           DumpModuleInfoByIp (*(UINTN *)(UINTN)SystemContext.SystemContextX64->Rsp);\r
-        );\r
+          );\r
       } else {\r
         DEBUG ((DEBUG_ERROR, "SMM exception at access (0x%lx)\n", PFAddress));\r
         DEBUG_CODE (\r
           DumpModuleInfoByIp ((UINTN)SystemContext.SystemContextX64->Rip);\r
-        );\r
+          );\r
       }\r
 \r
       if (HEAP_GUARD_NONSTOP_MODE) {\r
@@ -1081,6 +1121,7 @@ SmiPFHandler (
         goto Exit;\r
       }\r
     }\r
+\r
     CpuDeadLoop ();\r
     goto Exit;\r
   }\r
@@ -1089,13 +1130,14 @@ SmiPFHandler (
   // If a page fault occurs in non-SMRAM range.\r
   //\r
   if ((PFAddress < mCpuHotPlugData.SmrrBase) ||\r
-      (PFAddress >= mCpuHotPlugData.SmrrBase + mCpuHotPlugData.SmrrSize)) {\r
+      (PFAddress >= mCpuHotPlugData.SmrrBase + mCpuHotPlugData.SmrrSize))\r
+  {\r
     if ((SystemContext.SystemContextX64->ExceptionData & IA32_PF_EC_ID) != 0) {\r
       DumpCpuContext (InterruptType, SystemContext);\r
       DEBUG ((DEBUG_ERROR, "Code executed on IP(0x%lx) out of SMM range after SMM is locked!\n", PFAddress));\r
       DEBUG_CODE (\r
         DumpModuleInfoByIp (*(UINTN *)(UINTN)SystemContext.SystemContextX64->Rsp);\r
-      );\r
+        );\r
       CpuDeadLoop ();\r
       goto Exit;\r
     }\r
@@ -1103,13 +1145,14 @@ SmiPFHandler (
     //\r
     // If NULL pointer was just accessed\r
     //\r
-    if ((PcdGet8 (PcdNullPointerDetectionPropertyMask) & BIT1) != 0 &&\r
-        (PFAddress < EFI_PAGE_SIZE)) {\r
+    if (((PcdGet8 (PcdNullPointerDetectionPropertyMask) & BIT1) != 0) &&\r
+        (PFAddress < EFI_PAGE_SIZE))\r
+    {\r
       DumpCpuContext (InterruptType, SystemContext);\r
       DEBUG ((DEBUG_ERROR, "!!! NULL pointer access !!!\n"));\r
       DEBUG_CODE (\r
         DumpModuleInfoByIp ((UINTN)SystemContext.SystemContextX64->Rip);\r
-      );\r
+        );\r
 \r
       if (NULL_DETECTION_NONSTOP_MODE) {\r
         GuardPagePFHandler (SystemContext.SystemContextX64->ExceptionData);\r
@@ -1125,7 +1168,7 @@ SmiPFHandler (
       DEBUG ((DEBUG_ERROR, "Access SMM communication forbidden address (0x%lx)!\n", PFAddress));\r
       DEBUG_CODE (\r
         DumpModuleInfoByIp ((UINTN)SystemContext.SystemContextX64->Rip);\r
-      );\r
+        );\r
       CpuDeadLoop ();\r
       goto Exit;\r
     }\r
@@ -1152,20 +1195,20 @@ SetPageTableAttributes (
   VOID\r
   )\r
 {\r
-  UINTN                 Index2;\r
-  UINTN                 Index3;\r
-  UINTN                 Index4;\r
-  UINTN                 Index5;\r
-  UINT64                *L1PageTable;\r
-  UINT64                *L2PageTable;\r
-  UINT64                *L3PageTable;\r
-  UINT64                *L4PageTable;\r
-  UINT64                *L5PageTable;\r
-  UINTN                 PageTableBase;\r
-  BOOLEAN               IsSplitted;\r
-  BOOLEAN               PageTableSplitted;\r
-  BOOLEAN               CetEnabled;\r
-  BOOLEAN               Enable5LevelPaging;\r
+  UINTN    Index2;\r
+  UINTN    Index3;\r
+  UINTN    Index4;\r
+  UINTN    Index5;\r
+  UINT64   *L1PageTable;\r
+  UINT64   *L2PageTable;\r
+  UINT64   *L3PageTable;\r
+  UINT64   *L4PageTable;\r
+  UINT64   *L5PageTable;\r
+  UINTN    PageTableBase;\r
+  BOOLEAN  IsSplitted;\r
+  BOOLEAN  PageTableSplitted;\r
+  BOOLEAN  CetEnabled;\r
+  BOOLEAN  Enable5LevelPaging;\r
 \r
   //\r
   // Don't mark page table memory as read-only if\r
@@ -1177,18 +1220,21 @@ SetPageTableAttributes (
   //\r
   if (!mCpuSmmRestrictedMemoryAccess ||\r
       ((PcdGet8 (PcdHeapGuardPropertyMask) & (BIT3 | BIT2)) != 0) ||\r
-      FeaturePcdGet (PcdCpuSmmProfileEnable)) {\r
+      FeaturePcdGet (PcdCpuSmmProfileEnable))\r
+  {\r
     //\r
     // Restriction on access to non-SMRAM memory and heap guard could not be enabled at the same time.\r
     //\r
-    ASSERT (!(mCpuSmmRestrictedMemoryAccess &&\r
-              (PcdGet8 (PcdHeapGuardPropertyMask) & (BIT3 | BIT2)) != 0));\r
+    ASSERT (\r
+      !(mCpuSmmRestrictedMemoryAccess &&\r
+        (PcdGet8 (PcdHeapGuardPropertyMask) & (BIT3 | BIT2)) != 0)\r
+      );\r
 \r
     //\r
     // Restriction on access to non-SMRAM memory and SMM profile could not be enabled at the same time.\r
     //\r
     ASSERT (!(mCpuSmmRestrictedMemoryAccess && FeaturePcdGet (PcdCpuSmmProfileEnable)));\r
-    return ;\r
+    return;\r
   }\r
 \r
   DEBUG ((DEBUG_INFO, "SetPageTableAttributes\n"));\r
@@ -1197,19 +1243,20 @@ SetPageTableAttributes (
   // Disable write protection, because we need mark page table to be write protected.\r
   // We need *write* page table memory, to mark itself to be *read only*.\r
   //\r
-  CetEnabled = ((AsmReadCr4() & CR4_CET_ENABLE) != 0) ? TRUE : FALSE;\r
+  CetEnabled = ((AsmReadCr4 () & CR4_CET_ENABLE) != 0) ? TRUE : FALSE;\r
   if (CetEnabled) {\r
     //\r
     // CET must be disabled if WP is disabled.\r
     //\r
-    DisableCet();\r
+    DisableCet ();\r
   }\r
-  AsmWriteCr0 (AsmReadCr0() & ~CR0_WP);\r
+\r
+  AsmWriteCr0 (AsmReadCr0 () & ~CR0_WP);\r
 \r
   do {\r
     DEBUG ((DEBUG_INFO, "Start...\n"));\r
     PageTableSplitted = FALSE;\r
-    L5PageTable = NULL;\r
+    L5PageTable       = NULL;\r
 \r
     GetPageTable (&PageTableBase, &Enable5LevelPaging);\r
 \r
@@ -1219,7 +1266,7 @@ SetPageTableAttributes (
       PageTableSplitted = (PageTableSplitted || IsSplitted);\r
     }\r
 \r
-    for (Index5 = 0; Index5 < (Enable5LevelPaging ? SIZE_4KB/sizeof(UINT64) : 1); Index5++) {\r
+    for (Index5 = 0; Index5 < (Enable5LevelPaging ? SIZE_4KB/sizeof (UINT64) : 1); Index5++) {\r
       if (Enable5LevelPaging) {\r
         L4PageTable = (UINT64 *)(UINTN)(L5PageTable[Index5] & ~mAddressEncMask & PAGING_4K_ADDRESS_MASK_64);\r
         if (L4PageTable == NULL) {\r
@@ -1228,10 +1275,11 @@ SetPageTableAttributes (
       } else {\r
         L4PageTable = (UINT64 *)PageTableBase;\r
       }\r
+\r
       SmmSetMemoryAttributesEx ((EFI_PHYSICAL_ADDRESS)(UINTN)L4PageTable, SIZE_4KB, EFI_MEMORY_RO, &IsSplitted);\r
       PageTableSplitted = (PageTableSplitted || IsSplitted);\r
 \r
-      for (Index4 = 0; Index4 < SIZE_4KB/sizeof(UINT64); Index4++) {\r
+      for (Index4 = 0; Index4 < SIZE_4KB/sizeof (UINT64); Index4++) {\r
         L3PageTable = (UINT64 *)(UINTN)(L4PageTable[Index4] & ~mAddressEncMask & PAGING_4K_ADDRESS_MASK_64);\r
         if (L3PageTable == NULL) {\r
           continue;\r
@@ -1240,11 +1288,12 @@ SetPageTableAttributes (
         SmmSetMemoryAttributesEx ((EFI_PHYSICAL_ADDRESS)(UINTN)L3PageTable, SIZE_4KB, EFI_MEMORY_RO, &IsSplitted);\r
         PageTableSplitted = (PageTableSplitted || IsSplitted);\r
 \r
-        for (Index3 = 0; Index3 < SIZE_4KB/sizeof(UINT64); Index3++) {\r
+        for (Index3 = 0; Index3 < SIZE_4KB/sizeof (UINT64); Index3++) {\r
           if ((L3PageTable[Index3] & IA32_PG_PS) != 0) {\r
             // 1G\r
             continue;\r
           }\r
+\r
           L2PageTable = (UINT64 *)(UINTN)(L3PageTable[Index3] & ~mAddressEncMask & PAGING_4K_ADDRESS_MASK_64);\r
           if (L2PageTable == NULL) {\r
             continue;\r
@@ -1253,15 +1302,17 @@ SetPageTableAttributes (
           SmmSetMemoryAttributesEx ((EFI_PHYSICAL_ADDRESS)(UINTN)L2PageTable, SIZE_4KB, EFI_MEMORY_RO, &IsSplitted);\r
           PageTableSplitted = (PageTableSplitted || IsSplitted);\r
 \r
-          for (Index2 = 0; Index2 < SIZE_4KB/sizeof(UINT64); Index2++) {\r
+          for (Index2 = 0; Index2 < SIZE_4KB/sizeof (UINT64); Index2++) {\r
             if ((L2PageTable[Index2] & IA32_PG_PS) != 0) {\r
               // 2M\r
               continue;\r
             }\r
+\r
             L1PageTable = (UINT64 *)(UINTN)(L2PageTable[Index2] & ~mAddressEncMask & PAGING_4K_ADDRESS_MASK_64);\r
             if (L1PageTable == NULL) {\r
               continue;\r
             }\r
+\r
             SmmSetMemoryAttributesEx ((EFI_PHYSICAL_ADDRESS)(UINTN)L1PageTable, SIZE_4KB, EFI_MEMORY_RO, &IsSplitted);\r
             PageTableSplitted = (PageTableSplitted || IsSplitted);\r
           }\r
@@ -1273,15 +1324,15 @@ SetPageTableAttributes (
   //\r
   // Enable write protection, after page table updated.\r
   //\r
-  AsmWriteCr0 (AsmReadCr0() | CR0_WP);\r
+  AsmWriteCr0 (AsmReadCr0 () | CR0_WP);\r
   if (CetEnabled) {\r
     //\r
     // re-enable CET.\r
     //\r
-    EnableCet();\r
+    EnableCet ();\r
   }\r
 \r
-  return ;\r
+  return;\r
 }\r
 \r
 /**\r

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/Semaphore.c b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/Semaphore.c
index 8c9de1fdae70fa4df6ad275cb77bf25ba192ed5c..dafbc3390e2c68203ac6098da0bd94cc5443b4f5 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/Semaphore.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/Semaphore.c
@@ -9,8 +9,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
 \r
 #include "PiSmmCpuDxeSmm.h"\r
 \r
-X86_ASSEMBLY_PATCH_LABEL gPatchSmmRelocationOriginalAddressPtr32;\r
-X86_ASSEMBLY_PATCH_LABEL gPatchRebasedFlagAddr32;\r
+X86_ASSEMBLY_PATCH_LABEL  gPatchSmmRelocationOriginalAddressPtr32;\r
+X86_ASSEMBLY_PATCH_LABEL  gPatchRebasedFlagAddr32;\r
 \r
 UINTN             mSmmRelocationOriginalAddress;\r
 volatile BOOLEAN  *mRebasedFlag;\r
@@ -42,14 +42,14 @@ SemaphoreHook (
   SMRAM_SAVE_STATE_MAP  *CpuState;\r
   UINTN                 TempValue;\r
 \r
-  mRebasedFlag       = RebasedFlag;\r
+  mRebasedFlag = RebasedFlag;\r
   PatchInstructionX86 (\r
     gPatchRebasedFlagAddr32,\r
     (UINT32)(UINTN)mRebasedFlag,\r
     4\r
     );\r
 \r
-  CpuState = (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET);\r
+  CpuState                      = (SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET);\r
   mSmmRelocationOriginalAddress = HookReturnFromSmm (\r
                                     CpuIndex,\r
                                     CpuState,\r

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c
index ce7afce6d4dafc8f07bcf32331fb72e6ff8ec795..00a284c369dd74049c5dc66a070b39b333d10cf2 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c
@@ -8,18 +8,18 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
 \r
 #include "PiSmmCpuDxeSmm.h"\r
 \r
-EFI_PHYSICAL_ADDRESS                mGdtBuffer;\r
-UINTN                               mGdtBufferSize;\r
+EFI_PHYSICAL_ADDRESS  mGdtBuffer;\r
+UINTN                 mGdtBufferSize;\r
 \r
-extern BOOLEAN mCetSupported;\r
-extern UINTN mSmmShadowStackSize;\r
+extern BOOLEAN  mCetSupported;\r
+extern UINTN    mSmmShadowStackSize;\r
 \r
-X86_ASSEMBLY_PATCH_LABEL mPatchCetPl0Ssp;\r
-X86_ASSEMBLY_PATCH_LABEL mPatchCetInterruptSsp;\r
-X86_ASSEMBLY_PATCH_LABEL mPatchCetInterruptSspTable;\r
-UINT32 mCetPl0Ssp;\r
-UINT32 mCetInterruptSsp;\r
-UINT32 mCetInterruptSspTable;\r
+X86_ASSEMBLY_PATCH_LABEL  mPatchCetPl0Ssp;\r
+X86_ASSEMBLY_PATCH_LABEL  mPatchCetInterruptSsp;\r
+X86_ASSEMBLY_PATCH_LABEL  mPatchCetInterruptSspTable;\r
+UINT32                    mCetPl0Ssp;\r
+UINT32                    mCetInterruptSsp;\r
+UINT32                    mCetInterruptSspTable;\r
 \r
 UINTN  mSmmInterruptSspTables;\r
 \r
@@ -33,14 +33,14 @@ UINTN  mSmmInterruptSspTables;
 VOID\r
 EFIAPI\r
 InitializeIdtIst (\r
-  IN EFI_EXCEPTION_TYPE            ExceptionType,\r
-  IN UINT8                         Ist\r
+  IN EFI_EXCEPTION_TYPE  ExceptionType,\r
+  IN UINT8               Ist\r
   )\r
 {\r
   IA32_IDT_GATE_DESCRIPTOR  *IdtGate;\r
 \r
-  IdtGate = (IA32_IDT_GATE_DESCRIPTOR *)gcSmiIdtr.Base;\r
-  IdtGate += ExceptionType;\r
+  IdtGate                  = (IA32_IDT_GATE_DESCRIPTOR *)gcSmiIdtr.Base;\r
+  IdtGate                 += ExceptionType;\r
   IdtGate->Bits.Reserved_0 = Ist;\r
 }\r
 \r
@@ -59,34 +59,34 @@ InitGdt (
   OUT UINTN  *GdtStepSize\r
   )\r
 {\r
-  UINTN                     Index;\r
-  IA32_SEGMENT_DESCRIPTOR   *GdtDescriptor;\r
-  UINTN                     TssBase;\r
-  UINTN                     GdtTssTableSize;\r
-  UINT8                     *GdtTssTables;\r
-  UINTN                     GdtTableStepSize;\r
+  UINTN                    Index;\r
+  IA32_SEGMENT_DESCRIPTOR  *GdtDescriptor;\r
+  UINTN                    TssBase;\r
+  UINTN                    GdtTssTableSize;\r
+  UINT8                    *GdtTssTables;\r
+  UINTN                    GdtTableStepSize;\r
 \r
   //\r
   // For X64 SMM, we allocate separate GDT/TSS for each CPUs to avoid TSS load contention\r
   // on each SMI entry.\r
   //\r
   GdtTssTableSize = (gcSmiGdtr.Limit + 1 + TSS_SIZE + 7) & ~7; // 8 bytes aligned\r
-  mGdtBufferSize = GdtTssTableSize * gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus;\r
-  GdtTssTables = (UINT8*)AllocateCodePages (EFI_SIZE_TO_PAGES (mGdtBufferSize));\r
+  mGdtBufferSize  = GdtTssTableSize * gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus;\r
+  GdtTssTables    = (UINT8 *)AllocateCodePages (EFI_SIZE_TO_PAGES (mGdtBufferSize));\r
   ASSERT (GdtTssTables != NULL);\r
-  mGdtBuffer = (UINTN)GdtTssTables;\r
+  mGdtBuffer       = (UINTN)GdtTssTables;\r
   GdtTableStepSize = GdtTssTableSize;\r
 \r
   for (Index = 0; Index < gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus; Index++) {\r
-    CopyMem (GdtTssTables + GdtTableStepSize * Index, (VOID*)(UINTN)gcSmiGdtr.Base, gcSmiGdtr.Limit + 1 + TSS_SIZE);\r
+    CopyMem (GdtTssTables + GdtTableStepSize * Index, (VOID *)(UINTN)gcSmiGdtr.Base, gcSmiGdtr.Limit + 1 + TSS_SIZE);\r
 \r
     //\r
     // Fixup TSS descriptors\r
     //\r
-    TssBase = (UINTN)(GdtTssTables + GdtTableStepSize * Index + gcSmiGdtr.Limit + 1);\r
-    GdtDescriptor = (IA32_SEGMENT_DESCRIPTOR *)(TssBase) - 2;\r
-    GdtDescriptor->Bits.BaseLow = (UINT16)(UINTN)TssBase;\r
-    GdtDescriptor->Bits.BaseMid = (UINT8)((UINTN)TssBase >> 16);\r
+    TssBase                      = (UINTN)(GdtTssTables + GdtTableStepSize * Index + gcSmiGdtr.Limit + 1);\r
+    GdtDescriptor                = (IA32_SEGMENT_DESCRIPTOR *)(TssBase) - 2;\r
+    GdtDescriptor->Bits.BaseLow  = (UINT16)(UINTN)TssBase;\r
+    GdtDescriptor->Bits.BaseMid  = (UINT8)((UINTN)TssBase >> 16);\r
     GdtDescriptor->Bits.BaseHigh = (UINT8)((UINTN)TssBase >> 24);\r
 \r
     if ((FeaturePcdGet (PcdCpuSmmStackGuard)) || ((PcdGet32 (PcdControlFlowEnforcementPropertyMask) != 0) && mCetSupported)) {\r
@@ -118,15 +118,17 @@ GetProtectedModeCS (
 \r
   AsmReadGdtr (&GdtrDesc);\r
   GdtEntryCount = (GdtrDesc.Limit + 1) / sizeof (IA32_SEGMENT_DESCRIPTOR);\r
-  GdtEntry = (IA32_SEGMENT_DESCRIPTOR *) GdtrDesc.Base;\r
+  GdtEntry      = (IA32_SEGMENT_DESCRIPTOR *)GdtrDesc.Base;\r
   for (Index = 0; Index < GdtEntryCount; Index++) {\r
     if (GdtEntry->Bits.L == 0) {\r
-      if (GdtEntry->Bits.Type > 8 && GdtEntry->Bits.DB == 1) {\r
+      if ((GdtEntry->Bits.Type > 8) && (GdtEntry->Bits.DB == 1)) {\r
         break;\r
       }\r
     }\r
+\r
     GdtEntry++;\r
   }\r
+\r
   ASSERT (Index != GdtEntryCount);\r
   return Index * 8;\r
 }\r
@@ -171,9 +173,9 @@ InitShadowStack (
   IN VOID   *ShadowStack\r
   )\r
 {\r
-  UINTN       SmmShadowStackSize;\r
-  UINT64      *InterruptSspTable;\r
-  UINT32      InterruptSsp;\r
+  UINTN   SmmShadowStackSize;\r
+  UINT64  *InterruptSspTable;\r
+  UINT32  InterruptSsp;\r
 \r
   if ((PcdGet32 (PcdControlFlowEnforcementPropertyMask) != 0) && mCetSupported) {\r
     SmmShadowStackSize = EFI_PAGES_TO_SIZE (EFI_SIZE_TO_PAGES (PcdGet32 (PcdCpuSmmShadowStackSize)));\r
@@ -188,14 +190,15 @@ InitShadowStack (
       //\r
       SmmShadowStackSize += EFI_PAGES_TO_SIZE (1);\r
     }\r
-    mCetPl0Ssp = (UINT32)((UINTN)ShadowStack + SmmShadowStackSize - sizeof(UINT64));\r
+\r
+    mCetPl0Ssp = (UINT32)((UINTN)ShadowStack + SmmShadowStackSize - sizeof (UINT64));\r
     PatchInstructionX86 (mPatchCetPl0Ssp, mCetPl0Ssp, 4);\r
     DEBUG ((DEBUG_INFO, "mCetPl0Ssp - 0x%x\n", mCetPl0Ssp));\r
     DEBUG ((DEBUG_INFO, "ShadowStack - 0x%x\n", ShadowStack));\r
     DEBUG ((DEBUG_INFO, "  SmmShadowStackSize - 0x%x\n", SmmShadowStackSize));\r
 \r
     if (mSmmInterruptSspTables == 0) {\r
-      mSmmInterruptSspTables = (UINTN)AllocateZeroPool(sizeof(UINT64) * 8 * gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus);\r
+      mSmmInterruptSspTables = (UINTN)AllocateZeroPool (sizeof (UINT64) * 8 * gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus);\r
       ASSERT (mSmmInterruptSspTables != 0);\r
       DEBUG ((DEBUG_INFO, "mSmmInterruptSspTables - 0x%x\n", mSmmInterruptSspTables));\r
     }\r
@@ -209,17 +212,16 @@ InitShadowStack (
     // Please refer to UefiCpuPkg/Library/CpuExceptionHandlerLib/X64 for the full stack frame at runtime.\r
     // According to SDM (ver. 075 June 2021), shadow stack should be 32 bytes aligned.\r
     //\r
-    InterruptSsp = (UINT32)(((UINTN)ShadowStack + EFI_PAGES_TO_SIZE(1) - (sizeof(UINT64) * 4)) & ~0x1f);\r
-    *(UINT64 *)(UINTN)InterruptSsp = (InterruptSsp - sizeof(UINT64) * 4) | 0x2;\r
-    mCetInterruptSsp = InterruptSsp - sizeof(UINT64);\r
+    InterruptSsp                   = (UINT32)(((UINTN)ShadowStack + EFI_PAGES_TO_SIZE (1) - (sizeof (UINT64) * 4)) & ~0x1f);\r
+    *(UINT64 *)(UINTN)InterruptSsp = (InterruptSsp - sizeof (UINT64) * 4) | 0x2;\r
+    mCetInterruptSsp               = InterruptSsp - sizeof (UINT64);\r
 \r
-    mCetInterruptSspTable = (UINT32)(UINTN)(mSmmInterruptSspTables + sizeof(UINT64) * 8 * CpuIndex);\r
-    InterruptSspTable = (UINT64 *)(UINTN)mCetInterruptSspTable;\r
-    InterruptSspTable[1] = mCetInterruptSsp;\r
+    mCetInterruptSspTable = (UINT32)(UINTN)(mSmmInterruptSspTables + sizeof (UINT64) * 8 * CpuIndex);\r
+    InterruptSspTable     = (UINT64 *)(UINTN)mCetInterruptSspTable;\r
+    InterruptSspTable[1]  = mCetInterruptSsp;\r
     PatchInstructionX86 (mPatchCetInterruptSsp, mCetInterruptSsp, 4);\r
     PatchInstructionX86 (mPatchCetInterruptSspTable, mCetInterruptSspTable, 4);\r
     DEBUG ((DEBUG_INFO, "mCetInterruptSsp - 0x%x\n", mCetInterruptSsp));\r
     DEBUG ((DEBUG_INFO, "mCetInterruptSspTable - 0x%x\n", mCetInterruptSspTable));\r
   }\r
 }\r
-\r

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmProfileArch.c b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmProfileArch.c
index 63bae5a9137cbbff9cf2617b1f5825429a6eb141..cb7a69174530e6bccc2d26707caea2c45034bac2 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmProfileArch.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmProfileArch.c
@@ -14,17 +14,17 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
 //\r
 // Current page index.\r
 //\r
-UINTN                     mPFPageIndex;\r
+UINTN  mPFPageIndex;\r
 \r
 //\r
 // Pool for dynamically creating page table in page fault handler.\r
 //\r
-UINT64                    mPFPageBuffer;\r
+UINT64  mPFPageBuffer;\r
 \r
 //\r
 // Store the uplink information for each page being used.\r
 //\r
-UINT64                    *mPFPageUplink[MAX_PF_PAGE_COUNT];\r
+UINT64  *mPFPageUplink[MAX_PF_PAGE_COUNT];\r
 \r
 /**\r
   Create SMM page table for S3 path.\r
@@ -35,8 +35,8 @@ InitSmmS3Cr3 (
   VOID\r
   )\r
 {\r
-  EFI_PHYSICAL_ADDRESS              Pages;\r
-  UINT64                            *PTEntry;\r
+  EFI_PHYSICAL_ADDRESS  Pages;\r
+  UINT64                *PTEntry;\r
 \r
   //\r
   // Generate PAE page table for the first 4GB memory space\r
@@ -46,7 +46,7 @@ InitSmmS3Cr3 (
   //\r
   // Fill Page-Table-Level4 (PML4) entry\r
   //\r
-  PTEntry = (UINT64*)AllocatePageTableMemory (1);\r
+  PTEntry = (UINT64 *)AllocatePageTableMemory (1);\r
   ASSERT (PTEntry != NULL);\r
   *PTEntry = Pages | mAddressEncMask | PAGE_ATTRIBUTE_BITS;\r
   ZeroMem (PTEntry + 1, EFI_PAGE_SIZE - sizeof (*PTEntry));\r
@@ -56,7 +56,7 @@ InitSmmS3Cr3 (
   //\r
   mSmmS3ResumeState->SmmS3Cr3 = (UINT32)(UINTN)PTEntry;\r
 \r
-  return ;\r
+  return;\r
 }\r
 \r
 /**\r
@@ -68,7 +68,7 @@ InitPagesForPFHandler (
   VOID\r
   )\r
 {\r
-  VOID          *Address;\r
+  VOID  *Address;\r
 \r
   //\r
   // Pre-Allocate memory for page fault handler\r
@@ -77,9 +77,9 @@ InitPagesForPFHandler (
   Address = AllocatePages (MAX_PF_PAGE_COUNT);\r
   ASSERT (Address != NULL);\r
 \r
-  mPFPageBuffer =  (UINT64)(UINTN) Address;\r
-  mPFPageIndex = 0;\r
-  ZeroMem ((VOID *) (UINTN) mPFPageBuffer, EFI_PAGE_SIZE * MAX_PF_PAGE_COUNT);\r
+  mPFPageBuffer =  (UINT64)(UINTN)Address;\r
+  mPFPageIndex  = 0;\r
+  ZeroMem ((VOID *)(UINTN)mPFPageBuffer, EFI_PAGE_SIZE * MAX_PF_PAGE_COUNT);\r
   ZeroMem (mPFPageUplink, sizeof (mPFPageUplink));\r
 \r
   return;\r
@@ -93,16 +93,16 @@ InitPagesForPFHandler (
 **/\r
 VOID\r
 AcquirePage (\r
-  UINT64          *Uplink\r
+  UINT64  *Uplink\r
   )\r
 {\r
-  UINT64          Address;\r
+  UINT64  Address;\r
 \r
   //\r
   // Get the buffer\r
   //\r
   Address = mPFPageBuffer + EFI_PAGES_TO_SIZE (mPFPageIndex);\r
-  ZeroMem ((VOID *) (UINTN) Address, EFI_PAGE_SIZE);\r
+  ZeroMem ((VOID *)(UINTN)Address, EFI_PAGE_SIZE);\r
 \r
   //\r
   // Cut the previous uplink if it exists and wasn't overwritten\r
@@ -114,7 +114,7 @@ AcquirePage (
   //\r
   // Link & Record the current uplink\r
   //\r
-  *Uplink = Address | mAddressEncMask | PAGE_ATTRIBUTE_BITS;\r
+  *Uplink                     = Address | mAddressEncMask | PAGE_ATTRIBUTE_BITS;\r
   mPFPageUplink[mPFPageIndex] = Uplink;\r
 \r
   mPFPageIndex = (mPFPageIndex + 1) % MAX_PF_PAGE_COUNT;\r
@@ -134,26 +134,26 @@ AcquirePage (
 **/\r
 VOID\r
 RestorePageTableAbove4G (\r
-  UINT64        *PageTable,\r
-  UINT64        PFAddress,\r
-  UINTN         CpuIndex,\r
-  UINTN         ErrorCode,\r
-  BOOLEAN       *IsValidPFAddress\r
+  UINT64   *PageTable,\r
+  UINT64   PFAddress,\r
+  UINTN    CpuIndex,\r
+  UINTN    ErrorCode,\r
+  BOOLEAN  *IsValidPFAddress\r
   )\r
 {\r
-  UINTN         PTIndex;\r
-  UINT64        Address;\r
-  BOOLEAN       Nx;\r
-  BOOLEAN       Existed;\r
-  UINTN         Index;\r
-  UINTN         PFIndex;\r
-  IA32_CR4      Cr4;\r
-  BOOLEAN       Enable5LevelPaging;\r
+  UINTN     PTIndex;\r
+  UINT64    Address;\r
+  BOOLEAN   Nx;\r
+  BOOLEAN   Existed;\r
+  UINTN     Index;\r
+  UINTN     PFIndex;\r
+  IA32_CR4  Cr4;\r
+  BOOLEAN   Enable5LevelPaging;\r
 \r
   ASSERT ((PageTable != NULL) && (IsValidPFAddress != NULL));\r
 \r
-  Cr4.UintN = AsmReadCr4 ();\r
-  Enable5LevelPaging = (BOOLEAN) (Cr4.Bits.LA57 == 1);\r
+  Cr4.UintN          = AsmReadCr4 ();\r
+  Enable5LevelPaging = (BOOLEAN)(Cr4.Bits.LA57 == 1);\r
 \r
   //\r
   // If page fault address is 4GB above.\r
@@ -164,26 +164,28 @@ RestorePageTableAbove4G (
   // If it exists in page table but page fault is generated,\r
   // there are 2 possible reasons: 1. present flag is set to 0; 2. instruction fetch in protected memory range.\r
   //\r
-  Existed = FALSE;\r
-  PageTable = (UINT64*)(AsmReadCr3 () & PHYSICAL_ADDRESS_MASK);\r
-  PTIndex = 0;\r
+  Existed   = FALSE;\r
+  PageTable = (UINT64 *)(AsmReadCr3 () & PHYSICAL_ADDRESS_MASK);\r
+  PTIndex   = 0;\r
   if (Enable5LevelPaging) {\r
     PTIndex = BitFieldRead64 (PFAddress, 48, 56);\r
   }\r
+\r
   if ((!Enable5LevelPaging) || ((PageTable[PTIndex] & IA32_PG_P) != 0)) {\r
     // PML5E\r
     if (Enable5LevelPaging) {\r
-      PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);\r
+      PageTable = (UINT64 *)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);\r
     }\r
+\r
     PTIndex = BitFieldRead64 (PFAddress, 39, 47);\r
     if ((PageTable[PTIndex] & IA32_PG_P) != 0) {\r
       // PML4E\r
-      PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);\r
-      PTIndex = BitFieldRead64 (PFAddress, 30, 38);\r
+      PageTable = (UINT64 *)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);\r
+      PTIndex   = BitFieldRead64 (PFAddress, 30, 38);\r
       if ((PageTable[PTIndex] & IA32_PG_P) != 0) {\r
         // PDPTE\r
-        PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);\r
-        PTIndex = BitFieldRead64 (PFAddress, 21, 29);\r
+        PageTable = (UINT64 *)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);\r
+        PTIndex   = BitFieldRead64 (PFAddress, 21, 29);\r
         // PD\r
         if ((PageTable[PTIndex] & IA32_PG_PS) != 0) {\r
           //\r
@@ -197,7 +199,7 @@ RestorePageTableAbove4G (
           //\r
           // 4KB page\r
           //\r
-          PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask& PHYSICAL_ADDRESS_MASK);\r
+          PageTable = (UINT64 *)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask& PHYSICAL_ADDRESS_MASK);\r
           if (PageTable != 0) {\r
             //\r
             // When there is a valid entry to map to 4KB page, need not create a new entry to map 2MB.\r
@@ -217,7 +219,6 @@ RestorePageTableAbove4G (
   // If page entry does not existed in page table at all, create a new entry.\r
   //\r
   if (!Existed) {\r
-\r
     if (IsAddressValid (PFAddress, &Nx)) {\r
       //\r
       // If page fault address above 4GB is in protected range but it causes a page fault exception,\r
@@ -234,19 +235,20 @@ RestorePageTableAbove4G (
     //\r
     // Find the page table entry created just now.\r
     //\r
-    PageTable = (UINT64*)(AsmReadCr3 () & PHYSICAL_ADDRESS_MASK);\r
+    PageTable = (UINT64 *)(AsmReadCr3 () & PHYSICAL_ADDRESS_MASK);\r
     PFAddress = AsmReadCr2 ();\r
     // PML5E\r
     if (Enable5LevelPaging) {\r
-      PTIndex = BitFieldRead64 (PFAddress, 48, 56);\r
-      PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);\r
+      PTIndex   = BitFieldRead64 (PFAddress, 48, 56);\r
+      PageTable = (UINT64 *)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);\r
     }\r
+\r
     // PML4E\r
-    PTIndex = BitFieldRead64 (PFAddress, 39, 47);\r
-    PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);\r
+    PTIndex   = BitFieldRead64 (PFAddress, 39, 47);\r
+    PageTable = (UINT64 *)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);\r
     // PDPTE\r
-    PTIndex = BitFieldRead64 (PFAddress, 30, 38);\r
-    PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);\r
+    PTIndex   = BitFieldRead64 (PFAddress, 30, 38);\r
+    PageTable = (UINT64 *)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);\r
     // PD\r
     PTIndex = BitFieldRead64 (PFAddress, 21, 29);\r
     Address = PageTable[PTIndex] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK;\r
@@ -257,18 +259,21 @@ RestorePageTableAbove4G (
       AcquirePage (&PageTable[PTIndex]);\r
 \r
       // PTE\r
-      PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);\r
+      PageTable = (UINT64 *)(UINTN)(PageTable[PTIndex] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);\r
       for (Index = 0; Index < 512; Index++) {\r
         PageTable[Index] = Address | mAddressEncMask | PAGE_ATTRIBUTE_BITS;\r
         if (!IsAddressValid (Address, &Nx)) {\r
           PageTable[Index] = PageTable[Index] & (INTN)(INT32)(~PAGE_ATTRIBUTE_BITS);\r
         }\r
+\r
         if (Nx && mXdSupported) {\r
           PageTable[Index] = PageTable[Index] | IA32_PG_NX;\r
         }\r
+\r
         if (Address == (PFAddress & PHYSICAL_ADDRESS_MASK & ~((1ull << 12) - 1))) {\r
           PTIndex = Index;\r
         }\r
+\r
         Address += SIZE_4KB;\r
       } // end for PT\r
     } else {\r
@@ -281,6 +286,7 @@ RestorePageTableAbove4G (
         //\r
         PageTable[PTIndex] = PageTable[PTIndex] & (INTN)(INT32)(~PAGE_ATTRIBUTE_BITS);\r
       }\r
+\r
       //\r
       // Set XD bit to 1\r
       //\r
@@ -297,7 +303,7 @@ RestorePageTableAbove4G (
   //\r
   ASSERT (mPFEntryCount[CpuIndex] < MAX_PF_ENTRY_COUNT);\r
   if (mPFEntryCount[CpuIndex] < MAX_PF_ENTRY_COUNT) {\r
-    PFIndex = mPFEntryCount[CpuIndex];\r
+    PFIndex                                = mPFEntryCount[CpuIndex];\r
     mLastPFEntryValue[CpuIndex][PFIndex]   = PageTable[PTIndex];\r
     mLastPFEntryPointer[CpuIndex][PFIndex] = &PageTable[PTIndex];\r
     mPFEntryCount[CpuIndex]++;\r
@@ -326,7 +332,7 @@ RestorePageTableAbove4G (
 **/\r
 VOID\r
 ClearTrapFlag (\r
-  IN OUT EFI_SYSTEM_CONTEXT   SystemContext\r
+  IN OUT EFI_SYSTEM_CONTEXT  SystemContext\r
   )\r
 {\r
   SystemContext.SystemContextX64->Rflags &= (UINTN) ~BIT8;\r

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmProfileArch.h b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmProfileArch.h
index a857f587ebdaf43fa035a92f48bb6dfe14e2b1fa..80205c9b3e86f38ccd816cd2046cfbd4db4b2c87 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmProfileArch.h
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmProfileArch.h
@@ -12,50 +12,50 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
 #pragma pack (1)\r
 \r
 typedef struct _MSR_DS_AREA_STRUCT {\r
-  UINT64  BTSBufferBase;\r
-  UINT64  BTSIndex;\r
-  UINT64  BTSAbsoluteMaximum;\r
-  UINT64  BTSInterruptThreshold;\r
-  UINT64  PEBSBufferBase;\r
-  UINT64  PEBSIndex;\r
-  UINT64  PEBSAbsoluteMaximum;\r
-  UINT64  PEBSInterruptThreshold;\r
-  UINT64  PEBSCounterReset[2];\r
-  UINT64  Reserved;\r
+  UINT64    BTSBufferBase;\r
+  UINT64    BTSIndex;\r
+  UINT64    BTSAbsoluteMaximum;\r
+  UINT64    BTSInterruptThreshold;\r
+  UINT64    PEBSBufferBase;\r
+  UINT64    PEBSIndex;\r
+  UINT64    PEBSAbsoluteMaximum;\r
+  UINT64    PEBSInterruptThreshold;\r
+  UINT64    PEBSCounterReset[2];\r
+  UINT64    Reserved;\r
 } MSR_DS_AREA_STRUCT;\r
 \r
 typedef struct _BRANCH_TRACE_RECORD {\r
-  UINT64  LastBranchFrom;\r
-  UINT64  LastBranchTo;\r
-  UINT64  Rsvd0 : 4;\r
-  UINT64  BranchPredicted : 1;\r
-  UINT64  Rsvd1 : 59;\r
+  UINT64    LastBranchFrom;\r
+  UINT64    LastBranchTo;\r
+  UINT64    Rsvd0           : 4;\r
+  UINT64    BranchPredicted : 1;\r
+  UINT64    Rsvd1           : 59;\r
 } BRANCH_TRACE_RECORD;\r
 \r
 typedef struct _PEBS_RECORD {\r
-  UINT64  Rflags;\r
-  UINT64  LinearIP;\r
-  UINT64  Rax;\r
-  UINT64  Rbx;\r
-  UINT64  Rcx;\r
-  UINT64  Rdx;\r
-  UINT64  Rsi;\r
-  UINT64  Rdi;\r
-  UINT64  Rbp;\r
-  UINT64  Rsp;\r
-  UINT64  R8;\r
-  UINT64  R9;\r
-  UINT64  R10;\r
-  UINT64  R11;\r
-  UINT64  R12;\r
-  UINT64  R13;\r
-  UINT64  R14;\r
-  UINT64  R15;\r
+  UINT64    Rflags;\r
+  UINT64    LinearIP;\r
+  UINT64    Rax;\r
+  UINT64    Rbx;\r
+  UINT64    Rcx;\r
+  UINT64    Rdx;\r
+  UINT64    Rsi;\r
+  UINT64    Rdi;\r
+  UINT64    Rbp;\r
+  UINT64    Rsp;\r
+  UINT64    R8;\r
+  UINT64    R9;\r
+  UINT64    R10;\r
+  UINT64    R11;\r
+  UINT64    R12;\r
+  UINT64    R13;\r
+  UINT64    R14;\r
+  UINT64    R15;\r
 } PEBS_RECORD;\r
 \r
 #pragma pack ()\r
 \r
-#define PHYSICAL_ADDRESS_MASK       ((1ull << 52) - SIZE_4KB)\r
+#define PHYSICAL_ADDRESS_MASK  ((1ull << 52) - SIZE_4KB)\r
 \r
 /**\r
   Update page table to map the memory correctly in order to make the instruction\r
@@ -71,11 +71,11 @@ typedef struct _PEBS_RECORD {
 **/\r
 VOID\r
 RestorePageTableAbove4G (\r
-  UINT64        *PageTable,\r
-  UINT64        PFAddress,\r
-  UINTN         CpuIndex,\r
-  UINTN         ErrorCode,\r
-  BOOLEAN       *IsValidPFAddress\r
+  UINT64   *PageTable,\r
+  UINT64   PFAddress,\r
+  UINTN    CpuIndex,\r
+  UINTN    ErrorCode,\r
+  BOOLEAN  *IsValidPFAddress\r
   );\r
 \r
 /**\r

diff --git a/UefiCpuPkg/SecCore/FindPeiCore.c b/UefiCpuPkg/SecCore/FindPeiCore.c
index ee063a102080a73de7c73de5c4e9083cb89cc603..97adb68138896b41541cc89b224ef59f0944c9b5 100644 (file)
--- a/UefiCpuPkg/SecCore/FindPeiCore.c
+++ b/UefiCpuPkg/SecCore/FindPeiCore.c
@@ -21,35 +21,34 @@
 EFI_STATUS\r
 EFIAPI\r
 FindImageBase (\r
-  IN  EFI_FIRMWARE_VOLUME_HEADER       *FirmwareVolumePtr,\r
-  IN  EFI_FV_FILETYPE                  FileType,\r
-  OUT EFI_PHYSICAL_ADDRESS             *CoreImageBase\r
+  IN  EFI_FIRMWARE_VOLUME_HEADER  *FirmwareVolumePtr,\r
+  IN  EFI_FV_FILETYPE             FileType,\r
+  OUT EFI_PHYSICAL_ADDRESS        *CoreImageBase\r
   )\r
 {\r
-  EFI_PHYSICAL_ADDRESS        CurrentAddress;\r
-  EFI_PHYSICAL_ADDRESS        EndOfFirmwareVolume;\r
-  EFI_FFS_FILE_HEADER         *File;\r
-  UINT32                      Size;\r
-  EFI_PHYSICAL_ADDRESS        EndOfFile;\r
-  EFI_COMMON_SECTION_HEADER   *Section;\r
-  EFI_PHYSICAL_ADDRESS        EndOfSection;\r
+  EFI_PHYSICAL_ADDRESS       CurrentAddress;\r
+  EFI_PHYSICAL_ADDRESS       EndOfFirmwareVolume;\r
+  EFI_FFS_FILE_HEADER        *File;\r
+  UINT32                     Size;\r
+  EFI_PHYSICAL_ADDRESS       EndOfFile;\r
+  EFI_COMMON_SECTION_HEADER  *Section;\r
+  EFI_PHYSICAL_ADDRESS       EndOfSection;\r
 \r
   *CoreImageBase = 0;\r
 \r
-  CurrentAddress = (EFI_PHYSICAL_ADDRESS)(UINTN) FirmwareVolumePtr;\r
+  CurrentAddress      = (EFI_PHYSICAL_ADDRESS)(UINTN)FirmwareVolumePtr;\r
   EndOfFirmwareVolume = CurrentAddress + FirmwareVolumePtr->FvLength;\r
 \r
   //\r
   // Loop through the FFS files in the Boot Firmware Volume\r
   //\r
   for (EndOfFile = CurrentAddress + FirmwareVolumePtr->HeaderLength; ; ) {\r
-\r
     CurrentAddress = (EndOfFile + 7) & 0xfffffffffffffff8ULL;\r
     if (CurrentAddress > EndOfFirmwareVolume) {\r
       return EFI_NOT_FOUND;\r
     }\r
 \r
-    File = (EFI_FFS_FILE_HEADER*)(UINTN) CurrentAddress;\r
+    File = (EFI_FFS_FILE_HEADER *)(UINTN)CurrentAddress;\r
     if (IS_FFS_FILE2 (File)) {\r
       Size = FFS_FILE2_SIZE (File);\r
       if (Size <= 0x00FFFFFF) {\r
@@ -78,13 +77,14 @@ FindImageBase (
     // Loop through the FFS file sections within the FFS file\r
     //\r
     if (IS_FFS_FILE2 (File)) {\r
-      EndOfSection = (EFI_PHYSICAL_ADDRESS) (UINTN) ((UINT8 *) File + sizeof (EFI_FFS_FILE_HEADER2));\r
+      EndOfSection = (EFI_PHYSICAL_ADDRESS)(UINTN)((UINT8 *)File + sizeof (EFI_FFS_FILE_HEADER2));\r
     } else {\r
-      EndOfSection = (EFI_PHYSICAL_ADDRESS) (UINTN) ((UINT8 *) File + sizeof (EFI_FFS_FILE_HEADER));\r
+      EndOfSection = (EFI_PHYSICAL_ADDRESS)(UINTN)((UINT8 *)File + sizeof (EFI_FFS_FILE_HEADER));\r
     }\r
-    for (;;) {\r
+\r
+    for ( ; ;) {\r
       CurrentAddress = (EndOfSection + 3) & 0xfffffffffffffffcULL;\r
-      Section = (EFI_COMMON_SECTION_HEADER*)(UINTN) CurrentAddress;\r
+      Section        = (EFI_COMMON_SECTION_HEADER *)(UINTN)CurrentAddress;\r
 \r
       if (IS_SECTION2 (Section)) {\r
         Size = SECTION2_SIZE (Section);\r
@@ -106,14 +106,15 @@ FindImageBase (
       //\r
       // Look for executable sections\r
       //\r
-      if (Section->Type == EFI_SECTION_PE32 || Section->Type == EFI_SECTION_TE) {\r
+      if ((Section->Type == EFI_SECTION_PE32) || (Section->Type == EFI_SECTION_TE)) {\r
         if (File->Type == FileType) {\r
           if (IS_SECTION2 (Section)) {\r
-            *CoreImageBase = (PHYSICAL_ADDRESS) (UINTN) ((UINT8 *) Section + sizeof (EFI_COMMON_SECTION_HEADER2));\r
+            *CoreImageBase = (PHYSICAL_ADDRESS)(UINTN)((UINT8 *)Section + sizeof (EFI_COMMON_SECTION_HEADER2));\r
           } else {\r
-            *CoreImageBase = (PHYSICAL_ADDRESS) (UINTN) ((UINT8 *) Section + sizeof (EFI_COMMON_SECTION_HEADER));\r
+            *CoreImageBase = (PHYSICAL_ADDRESS)(UINTN)((UINT8 *)Section + sizeof (EFI_COMMON_SECTION_HEADER));\r
           }\r
         }\r
+\r
         break;\r
       }\r
     }\r
@@ -141,15 +142,15 @@ FindImageBase (
 VOID\r
 EFIAPI\r
 FindAndReportEntryPoints (\r
-  IN  EFI_FIRMWARE_VOLUME_HEADER       *SecCoreFirmwareVolumePtr,\r
-  IN  EFI_FIRMWARE_VOLUME_HEADER       *PeiCoreFirmwareVolumePtr,\r
-  OUT EFI_PEI_CORE_ENTRY_POINT         *PeiCoreEntryPoint\r
+  IN  EFI_FIRMWARE_VOLUME_HEADER  *SecCoreFirmwareVolumePtr,\r
+  IN  EFI_FIRMWARE_VOLUME_HEADER  *PeiCoreFirmwareVolumePtr,\r
+  OUT EFI_PEI_CORE_ENTRY_POINT    *PeiCoreEntryPoint\r
   )\r
 {\r
-  EFI_STATUS                       Status;\r
-  EFI_PHYSICAL_ADDRESS             SecCoreImageBase;\r
-  EFI_PHYSICAL_ADDRESS             PeiCoreImageBase;\r
-  PE_COFF_LOADER_IMAGE_CONTEXT     ImageContext;\r
+  EFI_STATUS                    Status;\r
+  EFI_PHYSICAL_ADDRESS          SecCoreImageBase;\r
+  EFI_PHYSICAL_ADDRESS          PeiCoreImageBase;\r
+  PE_COFF_LOADER_IMAGE_CONTEXT  ImageContext;\r
 \r
   //\r
   // Find SEC Core image base\r
@@ -157,12 +158,12 @@ FindAndReportEntryPoints (
   Status = FindImageBase (SecCoreFirmwareVolumePtr, EFI_FV_FILETYPE_SECURITY_CORE, &SecCoreImageBase);\r
   ASSERT_EFI_ERROR (Status);\r
 \r
-  ZeroMem ((VOID *) &ImageContext, sizeof (PE_COFF_LOADER_IMAGE_CONTEXT));\r
+  ZeroMem ((VOID *)&ImageContext, sizeof (PE_COFF_LOADER_IMAGE_CONTEXT));\r
   //\r
   // Report SEC Core debug information when remote debug is enabled\r
   //\r
   ImageContext.ImageAddress = SecCoreImageBase;\r
-  ImageContext.PdbPointer = PeCoffLoaderGetPdbPointer ((VOID*) (UINTN) ImageContext.ImageAddress);\r
+  ImageContext.PdbPointer   = PeCoffLoaderGetPdbPointer ((VOID *)(UINTN)ImageContext.ImageAddress);\r
   PeCoffLoaderRelocateImageExtraAction (&ImageContext);\r
 \r
   //\r
@@ -175,13 +176,13 @@ FindAndReportEntryPoints (
   // Report PEI Core debug information when remote debug is enabled\r
   //\r
   ImageContext.ImageAddress = PeiCoreImageBase;\r
-  ImageContext.PdbPointer = PeCoffLoaderGetPdbPointer ((VOID*) (UINTN) ImageContext.ImageAddress);\r
+  ImageContext.PdbPointer   = PeCoffLoaderGetPdbPointer ((VOID *)(UINTN)ImageContext.ImageAddress);\r
   PeCoffLoaderRelocateImageExtraAction (&ImageContext);\r
 \r
   //\r
   // Find PEI Core entry point\r
   //\r
-  Status = PeCoffLoaderGetEntryPoint ((VOID *) (UINTN) PeiCoreImageBase, (VOID**) PeiCoreEntryPoint);\r
+  Status = PeCoffLoaderGetEntryPoint ((VOID *)(UINTN)PeiCoreImageBase, (VOID **)PeiCoreEntryPoint);\r
   if (EFI_ERROR (Status)) {\r
     *PeiCoreEntryPoint = 0;\r
   }\r

diff --git a/UefiCpuPkg/SecCore/SecBist.c b/UefiCpuPkg/SecCore/SecBist.c
index 440140f5654c6c5e2f4969153d7a173ae08d778d..cd2e34017106436a0b00a087805d796e73a49046 100644 (file)
--- a/UefiCpuPkg/SecCore/SecBist.c
+++ b/UefiCpuPkg/SecCore/SecBist.c
@@ -8,21 +8,21 @@
 \r
 #include "SecMain.h"\r
 \r
-EFI_SEC_PLATFORM_INFORMATION_PPI mSecPlatformInformation = {\r
+EFI_SEC_PLATFORM_INFORMATION_PPI  mSecPlatformInformation = {\r
   SecPlatformInformationBist\r
 };\r
 \r
-EFI_PEI_PPI_DESCRIPTOR mPeiSecPlatformInformation = {\r
+EFI_PEI_PPI_DESCRIPTOR  mPeiSecPlatformInformation = {\r
   (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),\r
   &gEfiSecPlatformInformationPpiGuid,\r
   &mSecPlatformInformation\r
 };\r
 \r
-EFI_SEC_PLATFORM_INFORMATION2_PPI mSecPlatformInformation2 = {\r
+EFI_SEC_PLATFORM_INFORMATION2_PPI  mSecPlatformInformation2 = {\r
   SecPlatformInformation2Bist\r
 };\r
 \r
-EFI_PEI_PPI_DESCRIPTOR mPeiSecPlatformInformation2 = {\r
+EFI_PEI_PPI_DESCRIPTOR  mPeiSecPlatformInformation2 = {\r
   (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),\r
   &gEfiSecPlatformInformation2PpiGuid,\r
   &mSecPlatformInformation2\r
@@ -40,13 +40,13 @@ EFI_PEI_PPI_DESCRIPTOR mPeiSecPlatformInformation2 = {
 **/\r
 EFI_STATUS\r
 GetBistFromHob (\r
-  IN OUT UINT64           *StructureSize,\r
-  IN OUT VOID             *StructureBuffer\r
+  IN OUT UINT64  *StructureSize,\r
+  IN OUT VOID    *StructureBuffer\r
   )\r
 {\r
-  EFI_HOB_GUID_TYPE       *GuidHob;\r
-  VOID                    *DataInHob;\r
-  UINTN                   DataSize;\r
+  EFI_HOB_GUID_TYPE  *GuidHob;\r
+  VOID               *DataInHob;\r
+  UINTN              DataSize;\r
 \r
   GuidHob = GetFirstGuidHob (&gEfiCallerIdGuid);\r
   if (GuidHob == NULL) {\r
@@ -60,12 +60,12 @@ GetBistFromHob (
   //\r
   // return the information from BistHob\r
   //\r
-  if ((*StructureSize) < (UINT64) DataSize) {\r
-    *StructureSize = (UINT64) DataSize;\r
+  if ((*StructureSize) < (UINT64)DataSize) {\r
+    *StructureSize = (UINT64)DataSize;\r
     return EFI_BUFFER_TOO_SMALL;\r
   }\r
 \r
-  *StructureSize = (UINT64) DataSize;\r
+  *StructureSize = (UINT64)DataSize;\r
   CopyMem (StructureBuffer, DataInHob, DataSize);\r
   return EFI_SUCCESS;\r
 }\r
@@ -84,9 +84,9 @@ GetBistFromHob (
 EFI_STATUS\r
 EFIAPI\r
 SecPlatformInformationBist (\r
-  IN CONST EFI_PEI_SERVICES                  **PeiServices,\r
-  IN OUT UINT64                              *StructureSize,\r
-     OUT EFI_SEC_PLATFORM_INFORMATION_RECORD *PlatformInformationRecord\r
+  IN CONST EFI_PEI_SERVICES                **PeiServices,\r
+  IN OUT UINT64                            *StructureSize,\r
+  OUT EFI_SEC_PLATFORM_INFORMATION_RECORD  *PlatformInformationRecord\r
   )\r
 {\r
   return GetBistFromHob (StructureSize, PlatformInformationRecord);\r
@@ -107,9 +107,9 @@ SecPlatformInformationBist (
 EFI_STATUS\r
 EFIAPI\r
 SecPlatformInformation2Bist (\r
-  IN CONST EFI_PEI_SERVICES                   **PeiServices,\r
-  IN OUT UINT64                               *StructureSize,\r
-     OUT EFI_SEC_PLATFORM_INFORMATION_RECORD2 *PlatformInformationRecord2\r
+  IN CONST EFI_PEI_SERVICES                 **PeiServices,\r
+  IN OUT UINT64                             *StructureSize,\r
+  OUT EFI_SEC_PLATFORM_INFORMATION_RECORD2  *PlatformInformationRecord2\r
   )\r
 {\r
   return GetBistFromHob (StructureSize, PlatformInformationRecord2);\r
@@ -133,11 +133,11 @@ SecPlatformInformation2Bist (
 **/\r
 EFI_STATUS\r
 GetBistInfoFromPpi (\r
-  IN CONST EFI_PEI_SERVICES     **PeiServices,\r
-  IN CONST EFI_GUID             *Guid,\r
-     OUT EFI_PEI_PPI_DESCRIPTOR **PpiDescriptor,\r
-     OUT VOID                   **BistInformationData,\r
-     OUT UINT64                 *BistInformationSize OPTIONAL\r
+  IN CONST EFI_PEI_SERVICES   **PeiServices,\r
+  IN CONST EFI_GUID           *Guid,\r
+  OUT EFI_PEI_PPI_DESCRIPTOR  **PpiDescriptor,\r
+  OUT VOID                    **BistInformationData,\r
+  OUT UINT64                  *BistInformationSize OPTIONAL\r
   )\r
 {\r
   EFI_STATUS                            Status;\r
@@ -161,15 +161,15 @@ GetBistInfoFromPpi (
     //\r
     InformationSize         = 0;\r
     SecPlatformInformation2 = NULL;\r
-    Status = SecPlatformInformation2Ppi->PlatformInformation2 (\r
-                                           PeiServices,\r
-                                           &InformationSize,\r
-                                           SecPlatformInformation2\r
-                                           );\r
+    Status                  = SecPlatformInformation2Ppi->PlatformInformation2 (\r
+                                                            PeiServices,\r
+                                                            &InformationSize,\r
+                                                            SecPlatformInformation2\r
+                                                            );\r
     if (Status == EFI_BUFFER_TOO_SMALL) {\r
       Status = PeiServicesAllocatePool (\r
-                 (UINTN) InformationSize,\r
-                 (VOID **) &SecPlatformInformation2\r
+                 (UINTN)InformationSize,\r
+                 (VOID **)&SecPlatformInformation2\r
                  );\r
       if (Status == EFI_SUCCESS) {\r
         //\r
@@ -185,6 +185,7 @@ GetBistInfoFromPpi (
           if (BistInformationSize != NULL) {\r
             *BistInformationSize = InformationSize;\r
           }\r
+\r
           return EFI_SUCCESS;\r
         }\r
       }\r
@@ -203,25 +204,25 @@ RepublishSecPlatformInformationPpi (
   VOID\r
   )\r
 {\r
-  EFI_STATUS                            Status;\r
-  CONST EFI_PEI_SERVICES                **PeiServices;\r
-  UINT64                                BistInformationSize;\r
-  VOID                                  *BistInformationData;\r
-  EFI_PEI_PPI_DESCRIPTOR                *SecInformationDescriptor;\r
+  EFI_STATUS              Status;\r
+  CONST EFI_PEI_SERVICES  **PeiServices;\r
+  UINT64                  BistInformationSize;\r
+  VOID                    *BistInformationData;\r
+  EFI_PEI_PPI_DESCRIPTOR  *SecInformationDescriptor;\r
 \r
   PeiServices = GetPeiServicesTablePointer ();\r
-  Status = GetBistInfoFromPpi (\r
-             PeiServices,\r
-             &gEfiSecPlatformInformation2PpiGuid,\r
-             &SecInformationDescriptor,\r
-             &BistInformationData,\r
-             &BistInformationSize\r
-             );\r
+  Status      = GetBistInfoFromPpi (\r
+                  PeiServices,\r
+                  &gEfiSecPlatformInformation2PpiGuid,\r
+                  &SecInformationDescriptor,\r
+                  &BistInformationData,\r
+                  &BistInformationSize\r
+                  );\r
   if (Status == EFI_SUCCESS) {\r
     BuildGuidDataHob (\r
       &gEfiCallerIdGuid,\r
       BistInformationData,\r
-      (UINTN) BistInformationSize\r
+      (UINTN)BistInformationSize\r
       );\r
     //\r
     // The old SecPlatformInformation2 data is on temporary memory.\r
@@ -232,7 +233,9 @@ RepublishSecPlatformInformationPpi (
                SecInformationDescriptor,\r
                &mPeiSecPlatformInformation2\r
                );\r
-  } if (Status == EFI_NOT_FOUND) {\r
+  }\r
+\r
+  if (Status == EFI_NOT_FOUND) {\r
     Status = GetBistInfoFromPpi (\r
                PeiServices,\r
                &gEfiSecPlatformInformationPpiGuid,\r
@@ -244,7 +247,7 @@ RepublishSecPlatformInformationPpi (
       BuildGuidDataHob (\r
         &gEfiCallerIdGuid,\r
         BistInformationData,\r
-        (UINTN) BistInformationSize\r
+        (UINTN)BistInformationSize\r
         );\r
       //\r
       // The old SecPlatformInformation data is on temporary memory.\r
@@ -260,5 +263,5 @@ RepublishSecPlatformInformationPpi (
     }\r
   }\r
 \r
-  ASSERT_EFI_ERROR(Status);\r
+  ASSERT_EFI_ERROR (Status);\r
 }\r

diff --git a/UefiCpuPkg/SecCore/SecMain.c b/UefiCpuPkg/SecCore/SecMain.c
index 2416c4ce56b281ad66626ef95d4bbc6c64d8517e..a7526be9dd6eaf76b09d8fe0db5ee3321501e229 100644 (file)
--- a/UefiCpuPkg/SecCore/SecMain.c
+++ b/UefiCpuPkg/SecCore/SecMain.c
@@ -8,20 +8,20 @@
 \r
 #include "SecMain.h"\r
 \r
-EFI_PEI_TEMPORARY_RAM_DONE_PPI gSecTemporaryRamDonePpi = {\r
+EFI_PEI_TEMPORARY_RAM_DONE_PPI  gSecTemporaryRamDonePpi = {\r
   SecTemporaryRamDone\r
 };\r
 \r
 EFI_SEC_PLATFORM_INFORMATION_PPI  mSecPlatformInformationPpi = { SecPlatformInformation };\r
 \r
-EFI_PEI_PPI_DESCRIPTOR            mPeiSecPlatformInformationPpi[] = {\r
+EFI_PEI_PPI_DESCRIPTOR  mPeiSecPlatformInformationPpi[] = {\r
   {\r
     //\r
     // SecPerformance PPI notify descriptor.\r
     //\r
     EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK,\r
     &gPeiSecPerformancePpiGuid,\r
-    (VOID *) (UINTN) SecPerformancePpiCallBack\r
+    (VOID *)(UINTN)SecPerformancePpiCallBack\r
   },\r
   {\r
     EFI_PEI_PPI_DESCRIPTOR_PPI,\r
@@ -47,12 +47,12 @@ MigrateGdt (
   VOID\r
   )\r
 {\r
-  EFI_STATUS          Status;\r
-  UINTN               GdtBufferSize;\r
-  IA32_DESCRIPTOR     Gdtr;\r
-  VOID                *GdtBuffer;\r
+  EFI_STATUS       Status;\r
+  UINTN            GdtBufferSize;\r
+  IA32_DESCRIPTOR  Gdtr;\r
+  VOID             *GdtBuffer;\r
 \r
-  AsmReadGdtr ((IA32_DESCRIPTOR *) &Gdtr);\r
+  AsmReadGdtr ((IA32_DESCRIPTOR *)&Gdtr);\r
   GdtBufferSize = sizeof (IA32_SEGMENT_DESCRIPTOR) -1 + Gdtr.Limit + 1;\r
 \r
   Status =  PeiServicesAllocatePool (\r
@@ -65,8 +65,8 @@ MigrateGdt (
   }\r
 \r
   GdtBuffer = ALIGN_POINTER (GdtBuffer, sizeof (IA32_SEGMENT_DESCRIPTOR));\r
-  CopyMem (GdtBuffer, (VOID *) Gdtr.Base, Gdtr.Limit + 1);\r
-  Gdtr.Base = (UINTN) GdtBuffer;\r
+  CopyMem (GdtBuffer, (VOID *)Gdtr.Base, Gdtr.Limit + 1);\r
+  Gdtr.Base = (UINTN)GdtBuffer;\r
   AsmWriteGdtr (&Gdtr);\r
 \r
   return EFI_SUCCESS;\r
@@ -90,8 +90,8 @@ UINT64  mIdtEntryTemplate = 0xffff8e000010ffe4ULL;
 VOID\r
 NORETURN\r
 EFIAPI\r
-SecStartupPhase2(\r
-  IN VOID                     *Context\r
+SecStartupPhase2 (\r
+  IN VOID  *Context\r
   );\r
 \r
 /**\r
@@ -114,18 +114,18 @@ SecPerformancePpiCallBack (
   IN VOID                       *Ppi\r
   )\r
 {\r
-  EFI_STATUS                    Status;\r
-  PEI_SEC_PERFORMANCE_PPI       *SecPerf;\r
-  FIRMWARE_SEC_PERFORMANCE      Performance;\r
+  EFI_STATUS                Status;\r
+  PEI_SEC_PERFORMANCE_PPI   *SecPerf;\r
+  FIRMWARE_SEC_PERFORMANCE  Performance;\r
 \r
-  SecPerf = (PEI_SEC_PERFORMANCE_PPI *) Ppi;\r
-  Status = SecPerf->GetPerformance ((CONST EFI_PEI_SERVICES **) PeiServices, SecPerf, &Performance);\r
+  SecPerf = (PEI_SEC_PERFORMANCE_PPI *)Ppi;\r
+  Status  = SecPerf->GetPerformance ((CONST EFI_PEI_SERVICES **)PeiServices, SecPerf, &Performance);\r
   if (!EFI_ERROR (Status)) {\r
     BuildGuidDataHob (\r
       &gEfiFirmwarePerformanceGuid,\r
       &Performance,\r
       sizeof (FIRMWARE_SEC_PERFORMANCE)\r
-    );\r
+      );\r
     DEBUG ((DEBUG_INFO, "FPDT: SEC Performance Hob ResetEnd = %ld\n", Performance.ResetEnd));\r
   }\r
 \r
@@ -147,17 +147,17 @@ VOID
 NORETURN\r
 EFIAPI\r
 SecStartup (\r
-  IN UINT32                   SizeOfRam,\r
-  IN UINT32                   TempRamBase,\r
-  IN VOID                     *BootFirmwareVolume\r
+  IN UINT32  SizeOfRam,\r
+  IN UINT32  TempRamBase,\r
+  IN VOID    *BootFirmwareVolume\r
   )\r
 {\r
-  EFI_SEC_PEI_HAND_OFF        SecCoreData;\r
-  IA32_DESCRIPTOR             IdtDescriptor;\r
-  SEC_IDT_TABLE               IdtTableInStack;\r
-  UINT32                      Index;\r
-  UINT32                      PeiStackSize;\r
-  EFI_STATUS                  Status;\r
+  EFI_SEC_PEI_HAND_OFF  SecCoreData;\r
+  IA32_DESCRIPTOR       IdtDescriptor;\r
+  SEC_IDT_TABLE         IdtTableInStack;\r
+  UINT32                Index;\r
+  UINT32                PeiStackSize;\r
+  EFI_STATUS            Status;\r
 \r
   //\r
   // Report Status Code to indicate entering SEC core\r
@@ -201,11 +201,11 @@ SecStartup (
   // |-------------------|---->  TempRamBase\r
 \r
   IdtTableInStack.PeiService = 0;\r
-  for (Index = 0; Index < SEC_IDT_ENTRY_COUNT; Index ++) {\r
-    CopyMem ((VOID*)&IdtTableInStack.IdtTable[Index], (VOID*)&mIdtEntryTemplate, sizeof (UINT64));\r
+  for (Index = 0; Index < SEC_IDT_ENTRY_COUNT; Index++) {\r
+    CopyMem ((VOID *)&IdtTableInStack.IdtTable[Index], (VOID *)&mIdtEntryTemplate, sizeof (UINT64));\r
   }\r
 \r
-  IdtDescriptor.Base  = (UINTN) &IdtTableInStack.IdtTable;\r
+  IdtDescriptor.Base  = (UINTN)&IdtTableInStack.IdtTable;\r
   IdtDescriptor.Limit = (UINT16)(sizeof (IdtTableInStack.IdtTable) - 1);\r
 \r
   AsmWriteIdtr (&IdtDescriptor);\r
@@ -219,14 +219,14 @@ SecStartup (
   //\r
   // Update the base address and length of Pei temporary memory\r
   //\r
-  SecCoreData.DataSize               = (UINT16) sizeof (EFI_SEC_PEI_HAND_OFF);\r
+  SecCoreData.DataSize               = (UINT16)sizeof (EFI_SEC_PEI_HAND_OFF);\r
   SecCoreData.BootFirmwareVolumeBase = BootFirmwareVolume;\r
-  SecCoreData.BootFirmwareVolumeSize = (UINTN)((EFI_FIRMWARE_VOLUME_HEADER *) BootFirmwareVolume)->FvLength;\r
-  SecCoreData.TemporaryRamBase       = (VOID*)(UINTN) TempRamBase;\r
+  SecCoreData.BootFirmwareVolumeSize = (UINTN)((EFI_FIRMWARE_VOLUME_HEADER *)BootFirmwareVolume)->FvLength;\r
+  SecCoreData.TemporaryRamBase       = (VOID *)(UINTN)TempRamBase;\r
   SecCoreData.TemporaryRamSize       = SizeOfRam;\r
   SecCoreData.PeiTemporaryRamBase    = SecCoreData.TemporaryRamBase;\r
   SecCoreData.PeiTemporaryRamSize    = SizeOfRam - PeiStackSize;\r
-  SecCoreData.StackBase              = (VOID*)(UINTN)(TempRamBase + SecCoreData.PeiTemporaryRamSize);\r
+  SecCoreData.StackBase              = (VOID *)(UINTN)(TempRamBase + SecCoreData.PeiTemporaryRamSize);\r
   SecCoreData.StackSize              = PeiStackSize;\r
 \r
   //\r
@@ -253,18 +253,18 @@ SecStartup (
 VOID\r
 NORETURN\r
 EFIAPI\r
-SecStartupPhase2(\r
-  IN VOID                     *Context\r
+SecStartupPhase2 (\r
+  IN VOID  *Context\r
   )\r
 {\r
-  EFI_SEC_PEI_HAND_OFF        *SecCoreData;\r
-  EFI_PEI_PPI_DESCRIPTOR      *PpiList;\r
-  UINT32                      Index;\r
-  EFI_PEI_PPI_DESCRIPTOR      *AllSecPpiList;\r
-  EFI_PEI_CORE_ENTRY_POINT    PeiCoreEntryPoint;\r
+  EFI_SEC_PEI_HAND_OFF      *SecCoreData;\r
+  EFI_PEI_PPI_DESCRIPTOR    *PpiList;\r
+  UINT32                    Index;\r
+  EFI_PEI_PPI_DESCRIPTOR    *AllSecPpiList;\r
+  EFI_PEI_CORE_ENTRY_POINT  PeiCoreEntryPoint;\r
 \r
   PeiCoreEntryPoint = NULL;\r
-  SecCoreData   = (EFI_SEC_PEI_HAND_OFF *) Context;\r
+  SecCoreData       = (EFI_SEC_PEI_HAND_OFF *)Context;\r
 \r
   //\r
   // Perform platform specific initialization before entering PeiCore.\r
@@ -278,14 +278,15 @@ SecStartupPhase2(
     Index = 0;\r
     do {\r
       if (CompareGuid (PpiList[Index].Guid, &gEfiPeiCoreFvLocationPpiGuid) &&\r
-          (((EFI_PEI_CORE_FV_LOCATION_PPI *) PpiList[Index].Ppi)->PeiCoreFvLocation != 0)\r
-         ) {\r
+          (((EFI_PEI_CORE_FV_LOCATION_PPI *)PpiList[Index].Ppi)->PeiCoreFvLocation != 0)\r
+          )\r
+      {\r
         //\r
         // In this case, SecCore is in BFV but PeiCore is in another FV reported by PPI.\r
         //\r
         FindAndReportEntryPoints (\r
-          (EFI_FIRMWARE_VOLUME_HEADER *) SecCoreData->BootFirmwareVolumeBase,\r
-          (EFI_FIRMWARE_VOLUME_HEADER *) ((EFI_PEI_CORE_FV_LOCATION_PPI *) PpiList[Index].Ppi)->PeiCoreFvLocation,\r
+          (EFI_FIRMWARE_VOLUME_HEADER *)SecCoreData->BootFirmwareVolumeBase,\r
+          (EFI_FIRMWARE_VOLUME_HEADER *)((EFI_PEI_CORE_FV_LOCATION_PPI *)PpiList[Index].Ppi)->PeiCoreFvLocation,\r
           &PeiCoreEntryPoint\r
           );\r
         if (PeiCoreEntryPoint != NULL) {\r
@@ -299,6 +300,7 @@ SecStartupPhase2(
       }\r
     } while ((PpiList[Index++].Flags & EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST) != EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST);\r
   }\r
+\r
   //\r
   // If EFI_PEI_CORE_FV_LOCATION_PPI not found, try to locate PeiCore from BFV.\r
   //\r
@@ -307,8 +309,8 @@ SecStartupPhase2(
     // Both SecCore and PeiCore are in BFV.\r
     //\r
     FindAndReportEntryPoints (\r
-      (EFI_FIRMWARE_VOLUME_HEADER *) SecCoreData->BootFirmwareVolumeBase,\r
-      (EFI_FIRMWARE_VOLUME_HEADER *) SecCoreData->BootFirmwareVolumeBase,\r
+      (EFI_FIRMWARE_VOLUME_HEADER *)SecCoreData->BootFirmwareVolumeBase,\r
+      (EFI_FIRMWARE_VOLUME_HEADER *)SecCoreData->BootFirmwareVolumeBase,\r
       &PeiCoreEntryPoint\r
       );\r
     if (PeiCoreEntryPoint == NULL) {\r
@@ -317,13 +319,13 @@ SecStartupPhase2(
   }\r
 \r
   if (PpiList != NULL) {\r
-    AllSecPpiList = (EFI_PEI_PPI_DESCRIPTOR *) SecCoreData->PeiTemporaryRamBase;\r
+    AllSecPpiList = (EFI_PEI_PPI_DESCRIPTOR *)SecCoreData->PeiTemporaryRamBase;\r
 \r
     //\r
     // Remove the terminal flag from the terminal PPI\r
     //\r
     CopyMem (AllSecPpiList, mPeiSecPlatformInformationPpi, sizeof (mPeiSecPlatformInformationPpi));\r
-    Index = sizeof (mPeiSecPlatformInformationPpi) / sizeof (EFI_PEI_PPI_DESCRIPTOR) - 1;\r
+    Index                      = sizeof (mPeiSecPlatformInformationPpi) / sizeof (EFI_PEI_PPI_DESCRIPTOR) - 1;\r
     AllSecPpiList[Index].Flags = AllSecPpiList[Index].Flags & (~EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST);\r
 \r
     //\r
@@ -339,7 +341,7 @@ SecStartupPhase2(
     //\r
     // Add the terminal PPI\r
     //\r
-    CopyMem (&AllSecPpiList[Index ++], PpiList, sizeof (EFI_PEI_PPI_DESCRIPTOR));\r
+    CopyMem (&AllSecPpiList[Index++], PpiList, sizeof (EFI_PEI_PPI_DESCRIPTOR));\r
 \r
     //\r
     // Set PpiList to the total PPI\r
@@ -350,13 +352,13 @@ SecStartupPhase2(
     // Adjust PEI TEMP RAM Range.\r
     //\r
     ASSERT (SecCoreData->PeiTemporaryRamSize > Index * sizeof (EFI_PEI_PPI_DESCRIPTOR));\r
-    SecCoreData->PeiTemporaryRamBase = (VOID *)((UINTN) SecCoreData->PeiTemporaryRamBase + Index * sizeof (EFI_PEI_PPI_DESCRIPTOR));\r
+    SecCoreData->PeiTemporaryRamBase = (VOID *)((UINTN)SecCoreData->PeiTemporaryRamBase + Index * sizeof (EFI_PEI_PPI_DESCRIPTOR));\r
     SecCoreData->PeiTemporaryRamSize = SecCoreData->PeiTemporaryRamSize - Index * sizeof (EFI_PEI_PPI_DESCRIPTOR);\r
     //\r
     // Adjust the Base and Size to be 8-byte aligned as HOB which has 8byte aligned requirement\r
     // will be built based on them in PEI phase.\r
     //\r
-    SecCoreData->PeiTemporaryRamBase = (VOID *)(((UINTN)SecCoreData->PeiTemporaryRamBase + 7) & ~0x07);\r
+    SecCoreData->PeiTemporaryRamBase  = (VOID *)(((UINTN)SecCoreData->PeiTemporaryRamBase + 7) & ~0x07);\r
     SecCoreData->PeiTemporaryRamSize &= ~(UINTN)0x07;\r
   } else {\r
     //\r
@@ -370,7 +372,7 @@ SecStartupPhase2(
     "%a() Stack Base: 0x%p, Stack Size: 0x%x\n",\r
     __FUNCTION__,\r
     SecCoreData->StackBase,\r
-    (UINT32) SecCoreData->StackSize\r
+    (UINT32)SecCoreData->StackSize\r
     ));\r
 \r
   //\r
@@ -385,7 +387,7 @@ SecStartupPhase2(
   // Transfer the control to the PEI core\r
   //\r
   ASSERT (PeiCoreEntryPoint != NULL);\r
-  (*PeiCoreEntryPoint) (SecCoreData, PpiList);\r
+  (*PeiCoreEntryPoint)(SecCoreData, PpiList);\r
 \r
   //\r
   // Should not come here.\r
@@ -407,12 +409,12 @@ SecTemporaryRamDone (
   VOID\r
   )\r
 {\r
-  EFI_STATUS                    Status;\r
-  EFI_STATUS                    Status2;\r
-  UINTN                         Index;\r
-  BOOLEAN                       State;\r
-  EFI_PEI_PPI_DESCRIPTOR        *PeiPpiDescriptor;\r
-  REPUBLISH_SEC_PPI_PPI         *RepublishSecPpiPpi;\r
+  EFI_STATUS              Status;\r
+  EFI_STATUS              Status2;\r
+  UINTN                   Index;\r
+  BOOLEAN                 State;\r
+  EFI_PEI_PPI_DESCRIPTOR  *PeiPpiDescriptor;\r
+  REPUBLISH_SEC_PPI_PPI   *RepublishSecPpiPpi;\r
 \r
   //\r
   // Republish Sec Platform Information(2) PPI\r
@@ -427,7 +429,7 @@ SecTemporaryRamDone (
                &gRepublishSecPpiPpiGuid,\r
                Index,\r
                &PeiPpiDescriptor,\r
-               (VOID **) &RepublishSecPpiPpi\r
+               (VOID **)&RepublishSecPpiPpi\r
                );\r
     if (!EFI_ERROR (Status)) {\r
       DEBUG ((DEBUG_INFO, "Calling RepublishSecPpi instance %d.\n", Index));\r

diff --git a/UefiCpuPkg/SecCore/SecMain.h b/UefiCpuPkg/SecCore/SecMain.h
index e20bcf86532c483bfbd9f372e60e93d21b8492e7..029bee3e7e405104f9db1490d6c1d1c7dbb08c30 100644 (file)
--- a/UefiCpuPkg/SecCore/SecMain.h
+++ b/UefiCpuPkg/SecCore/SecMain.h
@@ -42,8 +42,8 @@ typedef struct _SEC_IDT_TABLE {
   // Note: For IA32, only the 4 bytes immediately preceding IDT is used to store\r
   // EFI_PEI_SERVICES**\r
   //\r
-  UINT64            PeiService;\r
-  UINT64            IdtTable[SEC_IDT_ENTRY_COUNT];\r
+  UINT64    PeiService;\r
+  UINT64    IdtTable[SEC_IDT_ENTRY_COUNT];\r
 } SEC_IDT_TABLE;\r
 \r
 /**\r
@@ -73,9 +73,9 @@ VOID
 NORETURN\r
 EFIAPI\r
 SecStartup (\r
-  IN UINT32                   SizeOfRam,\r
-  IN UINT32                   TempRamBase,\r
-  IN VOID                     *BootFirmwareVolume\r
+  IN UINT32  SizeOfRam,\r
+  IN UINT32  TempRamBase,\r
+  IN VOID    *BootFirmwareVolume\r
   );\r
 \r
 /**\r
@@ -92,9 +92,9 @@ SecStartup (
 VOID\r
 EFIAPI\r
 FindAndReportEntryPoints (\r
-  IN  EFI_FIRMWARE_VOLUME_HEADER       *SecCoreFirmwareVolumePtr,\r
-  IN  EFI_FIRMWARE_VOLUME_HEADER       *PeiCoreFirmwareVolumePtr,\r
-  OUT EFI_PEI_CORE_ENTRY_POINT         *PeiCoreEntryPoint\r
+  IN  EFI_FIRMWARE_VOLUME_HEADER  *SecCoreFirmwareVolumePtr,\r
+  IN  EFI_FIRMWARE_VOLUME_HEADER  *PeiCoreFirmwareVolumePtr,\r
+  OUT EFI_PEI_CORE_ENTRY_POINT    *PeiCoreEntryPoint\r
   );\r
 \r
 /**\r
@@ -123,9 +123,9 @@ ProcessLibraryConstructorList (
 EFI_STATUS\r
 EFIAPI\r
 SecPlatformInformationBist (\r
-  IN CONST EFI_PEI_SERVICES                  **PeiServices,\r
-  IN OUT UINT64                              *StructureSize,\r
-     OUT EFI_SEC_PLATFORM_INFORMATION_RECORD *PlatformInformationRecord\r
+  IN CONST EFI_PEI_SERVICES                **PeiServices,\r
+  IN OUT UINT64                            *StructureSize,\r
+  OUT EFI_SEC_PLATFORM_INFORMATION_RECORD  *PlatformInformationRecord\r
   );\r
 \r
 /**\r
@@ -143,9 +143,9 @@ SecPlatformInformationBist (
 EFI_STATUS\r
 EFIAPI\r
 SecPlatformInformation2Bist (\r
-  IN CONST EFI_PEI_SERVICES                   **PeiServices,\r
-  IN OUT UINT64                               *StructureSize,\r
-     OUT EFI_SEC_PLATFORM_INFORMATION_RECORD2 *PlatformInformationRecord2\r
+  IN CONST EFI_PEI_SERVICES                 **PeiServices,\r
+  IN OUT UINT64                             *StructureSize,\r
+  OUT EFI_SEC_PLATFORM_INFORMATION_RECORD2  *PlatformInformationRecord2\r
   );\r
 \r
 /**\r

diff --git a/UefiCpuPkg/SecMigrationPei/SecMigrationPei.c b/UefiCpuPkg/SecMigrationPei/SecMigrationPei.c
index 4813a06f13fd213f909e809bf3dff4ce0ecccecd..363d44b8ff4c42d0fe34e8e37a77681f38e4f272 100644 (file)
--- a/UefiCpuPkg/SecMigrationPei/SecMigrationPei.c
+++ b/UefiCpuPkg/SecMigrationPei/SecMigrationPei.c
@@ -19,55 +19,54 @@
 #include "SecMigrationPei.h"\r
 \r
 STATIC REPUBLISH_SEC_PPI_PPI  mEdkiiRepublishSecPpiPpi = {\r
-                                RepublishSecPpis\r
-                                };\r
+  RepublishSecPpis\r
+};\r
 \r
 GLOBAL_REMOVE_IF_UNREFERENCED EFI_SEC_PLATFORM_INFORMATION_PPI  mSecPlatformInformationPostMemoryPpi = {\r
-                                                                  SecPlatformInformationPostMemory\r
-                                                                  };\r
+  SecPlatformInformationPostMemory\r
+};\r
 \r
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_PEI_TEMPORARY_RAM_DONE_PPI  mSecTemporaryRamDonePostMemoryPpi = {\r
+  SecTemporaryRamDonePostMemory\r
+};\r
 \r
-GLOBAL_REMOVE_IF_UNREFERENCED EFI_PEI_TEMPORARY_RAM_DONE_PPI mSecTemporaryRamDonePostMemoryPpi = {\r
-                                                               SecTemporaryRamDonePostMemory\r
-                                                               };\r
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_PEI_TEMPORARY_RAM_SUPPORT_PPI  mSecTemporaryRamSupportPostMemoryPpi = {\r
+  SecTemporaryRamSupportPostMemory\r
+};\r
 \r
-GLOBAL_REMOVE_IF_UNREFERENCED EFI_PEI_TEMPORARY_RAM_SUPPORT_PPI mSecTemporaryRamSupportPostMemoryPpi = {\r
-                                                                  SecTemporaryRamSupportPostMemory\r
-                                                                  };\r
+GLOBAL_REMOVE_IF_UNREFERENCED PEI_SEC_PERFORMANCE_PPI  mSecPerformancePpi = {\r
+  GetPerformancePostMemory\r
+};\r
 \r
-GLOBAL_REMOVE_IF_UNREFERENCED PEI_SEC_PERFORMANCE_PPI mSecPerformancePpi = {\r
-                                                        GetPerformancePostMemory\r
-                                                        };\r
-\r
-STATIC EFI_PEI_PPI_DESCRIPTOR mEdkiiRepublishSecPpiDescriptor = {\r
+STATIC EFI_PEI_PPI_DESCRIPTOR  mEdkiiRepublishSecPpiDescriptor = {\r
   (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),\r
   &gRepublishSecPpiPpiGuid,\r
   &mEdkiiRepublishSecPpiPpi\r
-  };\r
+};\r
 \r
-GLOBAL_REMOVE_IF_UNREFERENCED EFI_PEI_PPI_DESCRIPTOR mSecPlatformInformationPostMemoryDescriptor = {\r
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_PEI_PPI_DESCRIPTOR  mSecPlatformInformationPostMemoryDescriptor = {\r
   (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),\r
   &gEfiSecPlatformInformationPpiGuid,\r
   &mSecPlatformInformationPostMemoryPpi\r
-  };\r
+};\r
 \r
-GLOBAL_REMOVE_IF_UNREFERENCED EFI_PEI_PPI_DESCRIPTOR mSecTemporaryRamDonePostMemoryDescriptor = {\r
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_PEI_PPI_DESCRIPTOR  mSecTemporaryRamDonePostMemoryDescriptor = {\r
   (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),\r
   &gEfiTemporaryRamDonePpiGuid,\r
   &mSecTemporaryRamDonePostMemoryPpi\r
-  };\r
+};\r
 \r
-GLOBAL_REMOVE_IF_UNREFERENCED EFI_PEI_PPI_DESCRIPTOR mSecTemporaryRamSupportPostMemoryDescriptor = {\r
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_PEI_PPI_DESCRIPTOR  mSecTemporaryRamSupportPostMemoryDescriptor = {\r
   (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),\r
   &gEfiTemporaryRamSupportPpiGuid,\r
   &mSecTemporaryRamSupportPostMemoryPpi\r
-  };\r
+};\r
 \r
-GLOBAL_REMOVE_IF_UNREFERENCED EFI_PEI_PPI_DESCRIPTOR mSecPerformancePpiDescriptor = {\r
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_PEI_PPI_DESCRIPTOR  mSecPerformancePpiDescriptor = {\r
   (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),\r
   &gPeiSecPerformancePpiGuid,\r
   &mSecPerformancePpi\r
-  };\r
+};\r
 \r
 /**\r
   Disables the use of Temporary RAM.\r
@@ -110,10 +109,10 @@ SecTemporaryRamDonePostMemory (
 EFI_STATUS\r
 EFIAPI\r
 SecTemporaryRamSupportPostMemory (\r
-  IN CONST EFI_PEI_SERVICES   **PeiServices,\r
-  IN EFI_PHYSICAL_ADDRESS     TemporaryMemoryBase,\r
-  IN EFI_PHYSICAL_ADDRESS     PermanentMemoryBase,\r
-  IN UINTN                    CopySize\r
+  IN CONST EFI_PEI_SERVICES  **PeiServices,\r
+  IN EFI_PHYSICAL_ADDRESS    TemporaryMemoryBase,\r
+  IN EFI_PHYSICAL_ADDRESS    PermanentMemoryBase,\r
+  IN UINTN                   CopySize\r
   )\r
 {\r
   //\r
@@ -151,7 +150,7 @@ GetPerformancePostMemory (
 {\r
   SEC_PLATFORM_INFORMATION_CONTEXT_HOB  *SecPlatformInformationContexHob;\r
 \r
-  if (This == NULL || Performance == NULL) {\r
+  if ((This == NULL) || (Performance == NULL)) {\r
     return EFI_INVALID_PARAMETER;\r
   }\r
 \r
@@ -182,9 +181,9 @@ GetPerformancePostMemory (
 EFI_STATUS\r
 EFIAPI\r
 SecPlatformInformationPostMemory (\r
-  IN CONST EFI_PEI_SERVICES                     **PeiServices,\r
-  IN OUT   UINT64                               *StructureSize,\r
-     OUT   EFI_SEC_PLATFORM_INFORMATION_RECORD  *PlatformInformationRecord\r
+  IN CONST EFI_PEI_SERVICES                  **PeiServices,\r
+  IN OUT   UINT64                            *StructureSize,\r
+  OUT   EFI_SEC_PLATFORM_INFORMATION_RECORD  *PlatformInformationRecord\r
   )\r
 {\r
   SEC_PLATFORM_INFORMATION_CONTEXT_HOB  *SecPlatformInformationContexHob;\r
@@ -209,9 +208,9 @@ SecPlatformInformationPostMemory (
 \r
   *StructureSize = SecPlatformInformationContexHob->Context.StructureSize;\r
   CopyMem (\r
-    (VOID *) PlatformInformationRecord,\r
-    (VOID *) SecPlatformInformationContexHob->Context.PlatformInformationRecord,\r
-    (UINTN) SecPlatformInformationContexHob->Context.StructureSize\r
+    (VOID *)PlatformInformationRecord,\r
+    (VOID *)SecPlatformInformationContexHob->Context.PlatformInformationRecord,\r
+    (UINTN)SecPlatformInformationContexHob->Context.StructureSize\r
     );\r
 \r
   return EFI_SUCCESS;\r
@@ -241,13 +240,13 @@ RepublishSecPpis (
   UINT64                                SecStructureSize;\r
 \r
   SecPlatformInformationPtr = NULL;\r
-  SecStructureSize = 0;\r
+  SecStructureSize          = 0;\r
 \r
   Status = PeiServicesLocatePpi (\r
              &gEfiTemporaryRamDonePpiGuid,\r
              0,\r
              &PeiPpiDescriptor,\r
-             (VOID **) &PeiPpi\r
+             (VOID **)&PeiPpi\r
              );\r
   if (!EFI_ERROR (Status)) {\r
     Status = PeiServicesReInstallPpi (\r
@@ -261,7 +260,7 @@ RepublishSecPpis (
              &gEfiTemporaryRamSupportPpiGuid,\r
              0,\r
              &PeiPpiDescriptor,\r
-             (VOID **) &PeiPpi\r
+             (VOID **)&PeiPpi\r
              );\r
   if (!EFI_ERROR (Status)) {\r
     Status = PeiServicesReInstallPpi (\r
@@ -274,7 +273,7 @@ RepublishSecPpis (
   Status = PeiServicesCreateHob (\r
              EFI_HOB_TYPE_GUID_EXTENSION,\r
              sizeof (SEC_PLATFORM_INFORMATION_CONTEXT_HOB),\r
-             (VOID **) &SecPlatformInformationContextHob\r
+             (VOID **)&SecPlatformInformationContextHob\r
              );\r
   ASSERT_EFI_ERROR (Status);\r
   if (EFI_ERROR (Status)) {\r
@@ -289,14 +288,14 @@ RepublishSecPpis (
              &gPeiSecPerformancePpiGuid,\r
              0,\r
              &PeiPpiDescriptor,\r
-             (VOID **) &PeiPpi\r
+             (VOID **)&PeiPpi\r
              );\r
   if (!EFI_ERROR (Status)) {\r
-    Status = ((PEI_SEC_PERFORMANCE_PPI *) PeiPpi)->GetPerformance (\r
-                                                     GetPeiServicesTablePointer (),\r
-                                                     (PEI_SEC_PERFORMANCE_PPI *) PeiPpi,\r
-                                                     &SecPlatformInformationContextHob->FirmwareSecPerformance\r
-                                                     );\r
+    Status = ((PEI_SEC_PERFORMANCE_PPI *)PeiPpi)->GetPerformance (\r
+                                                    GetPeiServicesTablePointer (),\r
+                                                    (PEI_SEC_PERFORMANCE_PPI *)PeiPpi,\r
+                                                    &SecPlatformInformationContextHob->FirmwareSecPerformance\r
+                                                    );\r
     ASSERT_EFI_ERROR (Status);\r
     if (!EFI_ERROR (Status)) {\r
       Status = PeiServicesReInstallPpi (\r
@@ -311,32 +310,33 @@ RepublishSecPpis (
              &gEfiSecPlatformInformationPpiGuid,\r
              0,\r
              &PeiPpiDescriptor,\r
-             (VOID **) &PeiPpi\r
+             (VOID **)&PeiPpi\r
              );\r
   if (!EFI_ERROR (Status)) {\r
-    Status = ((EFI_SEC_PLATFORM_INFORMATION_PPI *) PeiPpi)->PlatformInformation (\r
-                                                              GetPeiServicesTablePointer (),\r
-                                                              &SecStructureSize,\r
-                                                              SecPlatformInformationPtr\r
-                                                              );\r
+    Status = ((EFI_SEC_PLATFORM_INFORMATION_PPI *)PeiPpi)->PlatformInformation (\r
+                                                             GetPeiServicesTablePointer (),\r
+                                                             &SecStructureSize,\r
+                                                             SecPlatformInformationPtr\r
+                                                             );\r
     ASSERT (Status == EFI_BUFFER_TOO_SMALL);\r
     if (Status != EFI_BUFFER_TOO_SMALL) {\r
       return EFI_NOT_FOUND;\r
     }\r
 \r
-    ZeroMem ((VOID *) &(SecPlatformInformationContextHob->Context), sizeof (SEC_PLATFORM_INFORMATION_CONTEXT));\r
-    SecPlatformInformationContextHob->Context.PlatformInformationRecord = AllocatePool ((UINTN) SecStructureSize);\r
+    ZeroMem ((VOID *)&(SecPlatformInformationContextHob->Context), sizeof (SEC_PLATFORM_INFORMATION_CONTEXT));\r
+    SecPlatformInformationContextHob->Context.PlatformInformationRecord = AllocatePool ((UINTN)SecStructureSize);\r
     ASSERT (SecPlatformInformationContextHob->Context.PlatformInformationRecord != NULL);\r
     if (SecPlatformInformationContextHob->Context.PlatformInformationRecord == NULL) {\r
       return EFI_OUT_OF_RESOURCES;\r
     }\r
+\r
     SecPlatformInformationContextHob->Context.StructureSize = SecStructureSize;\r
 \r
-    Status = ((EFI_SEC_PLATFORM_INFORMATION_PPI *) PeiPpi)->PlatformInformation (\r
-                                                              GetPeiServicesTablePointer (),\r
-                                                              &(SecPlatformInformationContextHob->Context.StructureSize),\r
-                                                              SecPlatformInformationContextHob->Context.PlatformInformationRecord\r
-                                                              );\r
+    Status = ((EFI_SEC_PLATFORM_INFORMATION_PPI *)PeiPpi)->PlatformInformation (\r
+                                                             GetPeiServicesTablePointer (),\r
+                                                             &(SecPlatformInformationContextHob->Context.StructureSize),\r
+                                                             SecPlatformInformationContextHob->Context.PlatformInformationRecord\r
+                                                             );\r
     ASSERT_EFI_ERROR (Status);\r
     if (!EFI_ERROR (Status)) {\r
       Status = PeiServicesReInstallPpi (\r

diff --git a/UefiCpuPkg/SecMigrationPei/SecMigrationPei.h b/UefiCpuPkg/SecMigrationPei/SecMigrationPei.h
index 2d28490d9eb83f4927e5037c2fd84540a027b7b6..9919c8af767309a3cce3b5ecf828307b5e9348da 100644 (file)
--- a/UefiCpuPkg/SecMigrationPei/SecMigrationPei.h
+++ b/UefiCpuPkg/SecMigrationPei/SecMigrationPei.h
@@ -36,9 +36,9 @@
 EFI_STATUS\r
 EFIAPI\r
 SecPlatformInformationPostMemory (\r
-  IN CONST EFI_PEI_SERVICES                     **PeiServices,\r
-  IN OUT   UINT64                               *StructureSize,\r
-     OUT   EFI_SEC_PLATFORM_INFORMATION_RECORD  *PlatformInformationRecord\r
+  IN CONST EFI_PEI_SERVICES                  **PeiServices,\r
+  IN OUT   UINT64                            *StructureSize,\r
+  OUT   EFI_SEC_PLATFORM_INFORMATION_RECORD  *PlatformInformationRecord\r
   );\r
 \r
 /**\r
@@ -55,9 +55,9 @@ SecPlatformInformationPostMemory (
 EFI_STATUS\r
 EFIAPI\r
 SecPlatformInformationPpiNotifyCallback (\r
-  IN EFI_PEI_SERVICES              **PeiServices,\r
-  IN EFI_PEI_NOTIFY_DESCRIPTOR     *NotifyDescriptor,\r
-  IN VOID                          *Ppi\r
+  IN EFI_PEI_SERVICES           **PeiServices,\r
+  IN EFI_PEI_NOTIFY_DESCRIPTOR  *NotifyDescriptor,\r
+  IN VOID                       *Ppi\r
   );\r
 \r
 /**\r
@@ -110,10 +110,10 @@ SecTemporaryRamDonePostMemory (
 EFI_STATUS\r
 EFIAPI\r
 SecTemporaryRamSupportPostMemory (\r
-  IN CONST EFI_PEI_SERVICES   **PeiServices,\r
-  IN EFI_PHYSICAL_ADDRESS     TemporaryMemoryBase,\r
-  IN EFI_PHYSICAL_ADDRESS     PermanentMemoryBase,\r
-  IN UINTN                    CopySize\r
+  IN CONST EFI_PEI_SERVICES  **PeiServices,\r
+  IN EFI_PHYSICAL_ADDRESS    TemporaryMemoryBase,\r
+  IN EFI_PHYSICAL_ADDRESS    PermanentMemoryBase,\r
+  IN UINTN                   CopySize\r
   );\r
 \r
 /**\r
@@ -143,16 +143,16 @@ GetPerformancePostMemory (
   );\r
 \r
 typedef struct {\r
-  UINT64                                StructureSize;\r
-  EFI_SEC_PLATFORM_INFORMATION_RECORD   *PlatformInformationRecord;\r
+  UINT64                                 StructureSize;\r
+  EFI_SEC_PLATFORM_INFORMATION_RECORD    *PlatformInformationRecord;\r
 } SEC_PLATFORM_INFORMATION_CONTEXT;\r
 \r
 typedef struct {\r
-  EFI_HOB_GUID_TYPE                     Header;\r
-  UINT8                                 Revision;\r
-  UINT8                                 Reserved[3];\r
-  FIRMWARE_SEC_PERFORMANCE              FirmwareSecPerformance;\r
-  SEC_PLATFORM_INFORMATION_CONTEXT      Context;\r
+  EFI_HOB_GUID_TYPE                   Header;\r
+  UINT8                               Revision;\r
+  UINT8                               Reserved[3];\r
+  FIRMWARE_SEC_PERFORMANCE            FirmwareSecPerformance;\r
+  SEC_PLATFORM_INFORMATION_CONTEXT    Context;\r
 } SEC_PLATFORM_INFORMATION_CONTEXT_HOB;\r
 \r
 #endif\r

diff --git a/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c b/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c
index 6fa907161a9079def8834cf1c0873fd20c281e35..8419a4e32acbde9fc3ece2f33a08f5a6901f4830 100644 (file)
--- a/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c
+++ b/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c
@@ -58,21 +58,21 @@
 #pragma pack(1)\r
 typedef union {\r
   struct {\r
-    UINT32  LimitLow    : 16;\r
-    UINT32  BaseLow     : 16;\r
-    UINT32  BaseMid     : 8;\r
-    UINT32  Type        : 4;\r
-    UINT32  System      : 1;\r
-    UINT32  Dpl         : 2;\r
-    UINT32  Present     : 1;\r
-    UINT32  LimitHigh   : 4;\r
-    UINT32  Software    : 1;\r
-    UINT32  Reserved    : 1;\r
-    UINT32  DefaultSize : 1;\r
-    UINT32  Granularity : 1;\r
-    UINT32  BaseHigh    : 8;\r
+    UINT32    LimitLow    : 16;\r
+    UINT32    BaseLow     : 16;\r
+    UINT32    BaseMid     : 8;\r
+    UINT32    Type        : 4;\r
+    UINT32    System      : 1;\r
+    UINT32    Dpl         : 2;\r
+    UINT32    Present     : 1;\r
+    UINT32    LimitHigh   : 4;\r
+    UINT32    Software    : 1;\r
+    UINT32    Reserved    : 1;\r
+    UINT32    DefaultSize : 1;\r
+    UINT32    Granularity : 1;\r
+    UINT32    BaseHigh    : 8;\r
   } Bits;\r
-  UINT64  Uint64;\r
+  UINT64    Uint64;\r
 } IA32_GDT;\r
 \r
 //\r
@@ -81,18 +81,18 @@ typedef union {
 //\r
 typedef union {\r
   struct {\r
-    UINT64  Present:1;                // 0 = Not present in memory, 1 = Present in memory\r
-    UINT64  ReadWrite:1;              // 0 = Read-Only, 1= Read/Write\r
-    UINT64  UserSupervisor:1;         // 0 = Supervisor, 1=User\r
-    UINT64  WriteThrough:1;           // 0 = Write-Back caching, 1=Write-Through caching\r
-    UINT64  CacheDisabled:1;          // 0 = Cached, 1=Non-Cached\r
-    UINT64  Accessed:1;               // 0 = Not accessed, 1 = Accessed (set by CPU)\r
-    UINT64  Reserved:1;               // Reserved\r
-    UINT64  MustBeZero:2;             // Must Be Zero\r
-    UINT64  Available:3;              // Available for use by system software\r
-    UINT64  PageTableBaseAddress:40;  // Page Table Base Address\r
-    UINT64  AvabilableHigh:11;        // Available for use by system software\r
-    UINT64  Nx:1;                     // No Execute bit\r
+    UINT64    Present              : 1;  // 0 = Not present in memory, 1 = Present in memory\r
+    UINT64    ReadWrite            : 1;  // 0 = Read-Only, 1= Read/Write\r
+    UINT64    UserSupervisor       : 1;  // 0 = Supervisor, 1=User\r
+    UINT64    WriteThrough         : 1;  // 0 = Write-Back caching, 1=Write-Through caching\r
+    UINT64    CacheDisabled        : 1;  // 0 = Cached, 1=Non-Cached\r
+    UINT64    Accessed             : 1;  // 0 = Not accessed, 1 = Accessed (set by CPU)\r
+    UINT64    Reserved             : 1;  // Reserved\r
+    UINT64    MustBeZero           : 2;  // Must Be Zero\r
+    UINT64    Available            : 3;  // Available for use by system software\r
+    UINT64    PageTableBaseAddress : 40; // Page Table Base Address\r
+    UINT64    AvabilableHigh       : 11; // Available for use by system software\r
+    UINT64    Nx                   : 1;  // No Execute bit\r
   } Bits;\r
   UINT64    Uint64;\r
 } PAGE_MAP_AND_DIRECTORY_POINTER;\r
@@ -102,21 +102,21 @@ typedef union {
 //\r
 typedef union {\r
   struct {\r
-    UINT64  Present:1;                // 0 = Not present in memory, 1 = Present in memory\r
-    UINT64  ReadWrite:1;              // 0 = Read-Only, 1= Read/Write\r
-    UINT64  UserSupervisor:1;         // 0 = Supervisor, 1=User\r
-    UINT64  WriteThrough:1;           // 0 = Write-Back caching, 1=Write-Through caching\r
-    UINT64  CacheDisabled:1;          // 0 = Cached, 1=Non-Cached\r
-    UINT64  Accessed:1;               // 0 = Not accessed, 1 = Accessed (set by CPU)\r
-    UINT64  Dirty:1;                  // 0 = Not Dirty, 1 = written by processor on access to page\r
-    UINT64  MustBe1:1;                // Must be 1\r
-    UINT64  Global:1;                 // 0 = Not global page, 1 = global page TLB not cleared on CR3 write\r
-    UINT64  Available:3;              // Available for use by system software\r
-    UINT64  PAT:1;                    //\r
-    UINT64  MustBeZero:8;             // Must be zero;\r
-    UINT64  PageTableBaseAddress:31;  // Page Table Base Address\r
-    UINT64  AvabilableHigh:11;        // Available for use by system software\r
-    UINT64  Nx:1;                     // 0 = Execute Code, 1 = No Code Execution\r
+    UINT64    Present              : 1;  // 0 = Not present in memory, 1 = Present in memory\r
+    UINT64    ReadWrite            : 1;  // 0 = Read-Only, 1= Read/Write\r
+    UINT64    UserSupervisor       : 1;  // 0 = Supervisor, 1=User\r
+    UINT64    WriteThrough         : 1;  // 0 = Write-Back caching, 1=Write-Through caching\r
+    UINT64    CacheDisabled        : 1;  // 0 = Cached, 1=Non-Cached\r
+    UINT64    Accessed             : 1;  // 0 = Not accessed, 1 = Accessed (set by CPU)\r
+    UINT64    Dirty                : 1;  // 0 = Not Dirty, 1 = written by processor on access to page\r
+    UINT64    MustBe1              : 1;  // Must be 1\r
+    UINT64    Global               : 1;  // 0 = Not global page, 1 = global page TLB not cleared on CR3 write\r
+    UINT64    Available            : 3;  // Available for use by system software\r
+    UINT64    PAT                  : 1;  //\r
+    UINT64    MustBeZero           : 8;  // Must be zero;\r
+    UINT64    PageTableBaseAddress : 31; // Page Table Base Address\r
+    UINT64    AvabilableHigh       : 11; // Available for use by system software\r
+    UINT64    Nx                   : 1;  // 0 = Execute Code, 1 = No Code Execution\r
   } Bits;\r
   UINT64    Uint64;\r
 } PAGE_TABLE_ENTRY;\r
@@ -126,21 +126,21 @@ typedef union {
 //\r
 typedef union {\r
   struct {\r
-    UINT64  Present:1;                // 0 = Not present in memory, 1 = Present in memory\r
-    UINT64  ReadWrite:1;              // 0 = Read-Only, 1= Read/Write\r
-    UINT64  UserSupervisor:1;         // 0 = Supervisor, 1=User\r
-    UINT64  WriteThrough:1;           // 0 = Write-Back caching, 1=Write-Through caching\r
-    UINT64  CacheDisabled:1;          // 0 = Cached, 1=Non-Cached\r
-    UINT64  Accessed:1;               // 0 = Not accessed, 1 = Accessed (set by CPU)\r
-    UINT64  Dirty:1;                  // 0 = Not Dirty, 1 = written by processor on access to page\r
-    UINT64  MustBe1:1;                // Must be 1\r
-    UINT64  Global:1;                 // 0 = Not global page, 1 = global page TLB not cleared on CR3 write\r
-    UINT64  Available:3;              // Available for use by system software\r
-    UINT64  PAT:1;                    //\r
-    UINT64  MustBeZero:17;            // Must be zero;\r
-    UINT64  PageTableBaseAddress:22;  // Page Table Base Address\r
-    UINT64  AvabilableHigh:11;        // Available for use by system software\r
-    UINT64  Nx:1;                     // 0 = Execute Code, 1 = No Code Execution\r
+    UINT64    Present              : 1;  // 0 = Not present in memory, 1 = Present in memory\r
+    UINT64    ReadWrite            : 1;  // 0 = Read-Only, 1= Read/Write\r
+    UINT64    UserSupervisor       : 1;  // 0 = Supervisor, 1=User\r
+    UINT64    WriteThrough         : 1;  // 0 = Write-Back caching, 1=Write-Through caching\r
+    UINT64    CacheDisabled        : 1;  // 0 = Cached, 1=Non-Cached\r
+    UINT64    Accessed             : 1;  // 0 = Not accessed, 1 = Accessed (set by CPU)\r
+    UINT64    Dirty                : 1;  // 0 = Not Dirty, 1 = written by processor on access to page\r
+    UINT64    MustBe1              : 1;  // Must be 1\r
+    UINT64    Global               : 1;  // 0 = Not global page, 1 = global page TLB not cleared on CR3 write\r
+    UINT64    Available            : 3;  // Available for use by system software\r
+    UINT64    PAT                  : 1;  //\r
+    UINT64    MustBeZero           : 17; // Must be zero;\r
+    UINT64    PageTableBaseAddress : 22; // Page Table Base Address\r
+    UINT64    AvabilableHigh       : 11; // Available for use by system software\r
+    UINT64    Nx                   : 1;  // 0 = Execute Code, 1 = No Code Execution\r
   } Bits;\r
   UINT64    Uint64;\r
 } PAGE_TABLE_1G_ENTRY;\r
@@ -150,15 +150,15 @@ typedef union {
 // One for 32 bits PEI + 64 bits DXE, the other for 32 bits PEI + 32 bits DXE case.\r
 //\r
 typedef struct {\r
-  EFI_GUID  HeaderGuid;\r
-  UINT32    MessageLength;\r
-  UINT8     Data[1];\r
+  EFI_GUID    HeaderGuid;\r
+  UINT32      MessageLength;\r
+  UINT8       Data[1];\r
 } SMM_COMMUNICATE_HEADER_32;\r
 \r
 typedef struct {\r
-  EFI_GUID  HeaderGuid;\r
-  UINT64    MessageLength;\r
-  UINT8     Data[1];\r
+  EFI_GUID    HeaderGuid;\r
+  UINT64      MessageLength;\r
+  UINT8       Data[1];\r
 } SMM_COMMUNICATE_HEADER_64;\r
 \r
 #pragma pack()\r
@@ -166,6 +166,7 @@ typedef struct {
 //\r
 // Function prototypes\r
 //\r
+\r
 /**\r
   a ASM function to transfer control to OS.\r
 \r
@@ -174,7 +175,7 @@ typedef struct {
 **/\r
 typedef\r
 VOID\r
-(EFIAPI *ASM_TRANSFER_CONTROL) (\r
+(EFIAPI *ASM_TRANSFER_CONTROL)(\r
   IN   UINT32           S3WakingVector,\r
   IN   UINT32           AcpiLowMemoryBase\r
   );\r
@@ -225,33 +226,33 @@ S3RestoreConfig2 (
 VOID\r
 EFIAPI\r
 AsmSetDataSelectors (\r
-  IN UINT16   SelectorValue\r
+  IN UINT16  SelectorValue\r
   );\r
 \r
 //\r
 // Globals\r
 //\r
-EFI_PEI_S3_RESUME2_PPI      mS3ResumePpi = { S3RestoreConfig2 };\r
+EFI_PEI_S3_RESUME2_PPI  mS3ResumePpi = { S3RestoreConfig2 };\r
 \r
-EFI_PEI_PPI_DESCRIPTOR mPpiList = {\r
+EFI_PEI_PPI_DESCRIPTOR  mPpiList = {\r
   (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),\r
   &gEfiPeiS3Resume2PpiGuid,\r
   &mS3ResumePpi\r
 };\r
 \r
-EFI_PEI_PPI_DESCRIPTOR mPpiListPostScriptTable = {\r
+EFI_PEI_PPI_DESCRIPTOR  mPpiListPostScriptTable = {\r
   (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),\r
   &gPeiPostScriptTablePpiGuid,\r
   0\r
 };\r
 \r
-EFI_PEI_PPI_DESCRIPTOR mPpiListEndOfPeiTable = {\r
+EFI_PEI_PPI_DESCRIPTOR  mPpiListEndOfPeiTable = {\r
   (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),\r
   &gEfiEndOfPeiSignalPpiGuid,\r
   0\r
 };\r
 \r
-EFI_PEI_PPI_DESCRIPTOR mPpiListS3SmmInitDoneTable = {\r
+EFI_PEI_PPI_DESCRIPTOR  mPpiListS3SmmInitDoneTable = {\r
   (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),\r
   &gEdkiiS3SmmInitDoneGuid,\r
   0\r
@@ -260,29 +261,46 @@ EFI_PEI_PPI_DESCRIPTOR mPpiListS3SmmInitDoneTable = {
 //\r
 // Global Descriptor Table (GDT)\r
 //\r
-GLOBAL_REMOVE_IF_UNREFERENCED IA32_GDT mGdtEntries[] = {\r
-/* selector { Global Segment Descriptor                              } */\r
-/* 0x00 */  {{0,      0,  0,  0,    0,  0,  0,  0,    0,  0, 0,  0,  0}},\r
-/* 0x08 */  {{0,      0,  0,  0,    0,  0,  0,  0,    0,  0, 0,  0,  0}},\r
-/* 0x10 */  {{0xFFFF, 0,  0,  0xB,  1,  0,  1,  0xF,  0,  0, 1,  1,  0}},\r
-/* 0x18 */  {{0xFFFF, 0,  0,  0x3,  1,  0,  1,  0xF,  0,  0, 1,  1,  0}},\r
-/* 0x20 */  {{0,      0,  0,  0,    0,  0,  0,  0,    0,  0, 0,  0,  0}},\r
-/* 0x28 */  {{0xFFFF, 0,  0,  0xB,  1,  0,  1,  0xF,  0,  0, 0,  1,  0}},\r
-/* 0x30 */  {{0xFFFF, 0,  0,  0x3,  1,  0,  1,  0xF,  0,  0, 0,  1,  0}},\r
-/* 0x38 */  {{0xFFFF, 0,  0,  0xB,  1,  0,  1,  0xF,  0,  1, 0,  1,  0}},\r
-/* 0x40 */  {{0,      0,  0,  0,    0,  0,  0,  0,    0,  0, 0,  0,  0}},\r
+GLOBAL_REMOVE_IF_UNREFERENCED IA32_GDT  mGdtEntries[] = {\r
+  /* selector { Global Segment Descriptor                              } */\r
+  /* 0x00 */ {\r
+    { 0,      0, 0, 0,   0, 0, 0, 0,   0, 0, 0, 0, 0 }\r
+  },\r
+  /* 0x08 */ {\r
+    { 0,      0, 0, 0,   0, 0, 0, 0,   0, 0, 0, 0, 0 }\r
+  },\r
+  /* 0x10 */ {\r
+    { 0xFFFF, 0, 0, 0xB, 1, 0, 1, 0xF, 0, 0, 1, 1, 0 }\r
+  },\r
+  /* 0x18 */ {\r
+    { 0xFFFF, 0, 0, 0x3, 1, 0, 1, 0xF, 0, 0, 1, 1, 0 }\r
+  },\r
+  /* 0x20 */ {\r
+    { 0,      0, 0, 0,   0, 0, 0, 0,   0, 0, 0, 0, 0 }\r
+  },\r
+  /* 0x28 */ {\r
+    { 0xFFFF, 0, 0, 0xB, 1, 0, 1, 0xF, 0, 0, 0, 1, 0 }\r
+  },\r
+  /* 0x30 */ {\r
+    { 0xFFFF, 0, 0, 0x3, 1, 0, 1, 0xF, 0, 0, 0, 1, 0 }\r
+  },\r
+  /* 0x38 */ {\r
+    { 0xFFFF, 0, 0, 0xB, 1, 0, 1, 0xF, 0, 1, 0, 1, 0 }\r
+  },\r
+  /* 0x40 */ {\r
+    { 0,      0, 0, 0,   0, 0, 0, 0,   0, 0, 0, 0, 0 }\r
+  },\r
 };\r
 \r
-#define DATA_SEGEMENT_SELECTOR        0x18\r
+#define DATA_SEGEMENT_SELECTOR  0x18\r
 \r
 //\r
 // IA32 Gdt register\r
 //\r
-GLOBAL_REMOVE_IF_UNREFERENCED CONST IA32_DESCRIPTOR mGdt = {\r
+GLOBAL_REMOVE_IF_UNREFERENCED CONST IA32_DESCRIPTOR  mGdt = {\r
   sizeof (mGdtEntries) - 1,\r
-  (UINTN) mGdtEntries\r
-  };\r
-\r
+  (UINTN)mGdtEntries\r
+};\r
 \r
 /**\r
   The function will check if current waking vector is long mode.\r
@@ -294,28 +312,32 @@ GLOBAL_REMOVE_IF_UNREFERENCED CONST IA32_DESCRIPTOR mGdt = {
 **/\r
 BOOLEAN\r
 IsLongModeWakingVector (\r
-  IN ACPI_S3_CONTEXT                *AcpiS3Context\r
+  IN ACPI_S3_CONTEXT  *AcpiS3Context\r
   )\r
 {\r
   EFI_ACPI_4_0_FIRMWARE_ACPI_CONTROL_STRUCTURE  *Facs;\r
 \r
-  Facs = (EFI_ACPI_4_0_FIRMWARE_ACPI_CONTROL_STRUCTURE *) ((UINTN) (AcpiS3Context->AcpiFacsTable));\r
+  Facs = (EFI_ACPI_4_0_FIRMWARE_ACPI_CONTROL_STRUCTURE *)((UINTN)(AcpiS3Context->AcpiFacsTable));\r
   if ((Facs == NULL) ||\r
       (Facs->Signature != EFI_ACPI_4_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE) ||\r
-      ((Facs->FirmwareWakingVector == 0) && (Facs->XFirmwareWakingVector == 0)) ) {\r
+      ((Facs->FirmwareWakingVector == 0) && (Facs->XFirmwareWakingVector == 0)))\r
+  {\r
     // Something wrong with FACS\r
     return FALSE;\r
   }\r
+\r
   if (Facs->XFirmwareWakingVector != 0) {\r
     if ((Facs->Version == EFI_ACPI_4_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION) &&\r
         ((Facs->Flags & EFI_ACPI_4_0_64BIT_WAKE_SUPPORTED_F) != 0) &&\r
-        ((Facs->OspmFlags & EFI_ACPI_4_0_OSPM_64BIT_WAKE__F) != 0)) {\r
+        ((Facs->OspmFlags & EFI_ACPI_4_0_OSPM_64BIT_WAKE__F) != 0))\r
+    {\r
       // Both BIOS and OS wants 64bit vector\r
       if (FeaturePcdGet (PcdDxeIplSwitchToLongMode)) {\r
         return TRUE;\r
       }\r
     }\r
   }\r
+\r
   return FALSE;\r
 }\r
 \r
@@ -327,15 +349,15 @@ IsLongModeWakingVector (
 **/\r
 VOID\r
 SignalToSmmByCommunication (\r
-  IN EFI_GUID   *HandlerType\r
+  IN EFI_GUID  *HandlerType\r
   )\r
 {\r
-  EFI_STATUS                         Status;\r
-  EFI_PEI_SMM_COMMUNICATION_PPI      *SmmCommunicationPpi;\r
-  UINTN                              CommSize;\r
-  SMM_COMMUNICATE_HEADER_32          Header32;\r
-  SMM_COMMUNICATE_HEADER_64          Header64;\r
-  VOID                               *CommBuffer;\r
+  EFI_STATUS                     Status;\r
+  EFI_PEI_SMM_COMMUNICATION_PPI  *SmmCommunicationPpi;\r
+  UINTN                          CommSize;\r
+  SMM_COMMUNICATE_HEADER_32      Header32;\r
+  SMM_COMMUNICATE_HEADER_64      Header64;\r
+  VOID                           *CommBuffer;\r
 \r
   DEBUG ((DEBUG_INFO, "Signal %g to SMM - Enter\n", HandlerType));\r
 \r
@@ -345,15 +367,16 @@ SignalToSmmByCommunication (
   // if (sizeof(UINTN) == sizeof(UINT64), PEI already 64 bits, assume DXE also 64 bits.\r
   // or (FeaturePcdGet (PcdDxeIplSwitchToLongMode)), DXE will switch to 64 bits.\r
   //\r
-  if ((sizeof(UINTN) == sizeof(UINT64)) || (FeaturePcdGet (PcdDxeIplSwitchToLongMode))) {\r
-    CommBuffer = &Header64;\r
+  if ((sizeof (UINTN) == sizeof (UINT64)) || (FeaturePcdGet (PcdDxeIplSwitchToLongMode))) {\r
+    CommBuffer             = &Header64;\r
     Header64.MessageLength = 0;\r
-    CommSize = OFFSET_OF (SMM_COMMUNICATE_HEADER_64, Data);\r
+    CommSize               = OFFSET_OF (SMM_COMMUNICATE_HEADER_64, Data);\r
   } else {\r
-    CommBuffer = &Header32;\r
+    CommBuffer             = &Header32;\r
     Header32.MessageLength = 0;\r
-    CommSize = OFFSET_OF (SMM_COMMUNICATE_HEADER_32, Data);\r
+    CommSize               = OFFSET_OF (SMM_COMMUNICATE_HEADER_32, Data);\r
   }\r
+\r
   CopyGuid (CommBuffer, HandlerType);\r
 \r
   Status = PeiServicesLocatePpi (\r
@@ -390,8 +413,8 @@ SignalToSmmByCommunication (
 VOID\r
 EFIAPI\r
 S3ResumeBootOs (\r
-  IN ACPI_S3_CONTEXT                *AcpiS3Context,\r
-  IN PEI_S3_RESUME_STATE            *PeiS3ResumeState\r
+  IN ACPI_S3_CONTEXT      *AcpiS3Context,\r
+  IN PEI_S3_RESUME_STATE  *PeiS3ResumeState\r
   )\r
 {\r
   EFI_STATUS                                    Status;\r
@@ -436,11 +459,12 @@ S3ResumeBootOs (
   //\r
   // Get ACPI Table Address\r
   //\r
-  Facs = (EFI_ACPI_4_0_FIRMWARE_ACPI_CONTROL_STRUCTURE *) ((UINTN) (AcpiS3Context->AcpiFacsTable));\r
+  Facs = (EFI_ACPI_4_0_FIRMWARE_ACPI_CONTROL_STRUCTURE *)((UINTN)(AcpiS3Context->AcpiFacsTable));\r
 \r
   if ((Facs == NULL) ||\r
       (Facs->Signature != EFI_ACPI_4_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE) ||\r
-      ((Facs->FirmwareWakingVector == 0) && (Facs->XFirmwareWakingVector == 0)) ) {\r
+      ((Facs->FirmwareWakingVector == 0) && (Facs->XFirmwareWakingVector == 0)))\r
+  {\r
     //\r
     // Report Status code that no valid vector is found\r
     //\r
@@ -449,20 +473,20 @@ S3ResumeBootOs (
       (EFI_SOFTWARE_PEI_MODULE | EFI_SW_PEI_EC_S3_OS_WAKE_ERROR)\r
       );\r
     CpuDeadLoop ();\r
-    return ;\r
+    return;\r
   }\r
 \r
   //\r
   // Install EndOfPeiPpi\r
   //\r
-  PERF_INMODULE_BEGIN("EndOfPeiPpi");\r
+  PERF_INMODULE_BEGIN ("EndOfPeiPpi");\r
 \r
   Status = PeiServicesInstallPpi (&mPpiListEndOfPeiTable);\r
   ASSERT_EFI_ERROR (Status);\r
 \r
-  PERF_INMODULE_END("EndOfPeiPpi");\r
+  PERF_INMODULE_END ("EndOfPeiPpi");\r
 \r
-  PERF_INMODULE_BEGIN("EndOfS3Resume");\r
+  PERF_INMODULE_BEGIN ("EndOfS3Resume");\r
 \r
   DEBUG ((DEBUG_INFO, "Signal EndOfS3Resume\n"));\r
   //\r
@@ -482,7 +506,7 @@ S3ResumeBootOs (
     //\r
     // Switch to native waking vector\r
     //\r
-    TempStackTop = (UINTN)&TempStack + sizeof(TempStack);\r
+    TempStackTop = (UINTN)&TempStack + sizeof (TempStack);\r
     DEBUG ((\r
       DEBUG_INFO,\r
       "%a() Stack Base: 0x%x, Stack Size: 0x%x\n",\r
@@ -492,7 +516,8 @@ S3ResumeBootOs (
       ));\r
     if ((Facs->Version == EFI_ACPI_4_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION) &&\r
         ((Facs->Flags & EFI_ACPI_4_0_64BIT_WAKE_SUPPORTED_F) != 0) &&\r
-        ((Facs->OspmFlags & EFI_ACPI_4_0_OSPM_64BIT_WAKE__F) != 0)) {\r
+        ((Facs->OspmFlags & EFI_ACPI_4_0_OSPM_64BIT_WAKE__F) != 0))\r
+    {\r
       //\r
       // X64 long mode waking vector\r
       //\r
@@ -513,10 +538,10 @@ S3ResumeBootOs (
           EFI_ERROR_CODE | EFI_ERROR_MAJOR,\r
           (EFI_SOFTWARE_PEI_MODULE | EFI_SW_PEI_EC_S3_OS_WAKE_ERROR)\r
           );\r
-        DEBUG (( DEBUG_ERROR, "Unsupported for 32bit DXE transfer to 64bit OS waking vector!\r\n"));\r
+        DEBUG ((DEBUG_ERROR, "Unsupported for 32bit DXE transfer to 64bit OS waking vector!\r\n"));\r
         ASSERT (FALSE);\r
         CpuDeadLoop ();\r
-        return ;\r
+        return;\r
       }\r
     } else {\r
       //\r
@@ -524,7 +549,7 @@ S3ResumeBootOs (
       //\r
       DEBUG ((DEBUG_INFO, "Transfer to 32bit OS waking vector - %x\r\n", (UINTN)Facs->XFirmwareWakingVector));\r
       SwitchStack (\r
-        (SWITCH_STACK_ENTRY_POINT) (UINTN) Facs->XFirmwareWakingVector,\r
+        (SWITCH_STACK_ENTRY_POINT)(UINTN)Facs->XFirmwareWakingVector,\r
         NULL,\r
         NULL,\r
         (VOID *)(UINTN)TempStackTop\r
@@ -549,7 +574,7 @@ S3ResumeBootOs (
   //\r
   // Never run to here\r
   //\r
-  CpuDeadLoop();\r
+  CpuDeadLoop ();\r
 }\r
 \r
 /**\r
@@ -561,28 +586,28 @@ S3ResumeBootOs (
 **/\r
 VOID\r
 RestoreS3PageTables (\r
-  IN UINTN                                         S3NvsPageTableAddress,\r
-  IN BOOLEAN                                       Build4GPageTableOnly\r
+  IN UINTN    S3NvsPageTableAddress,\r
+  IN BOOLEAN  Build4GPageTableOnly\r
   )\r
 {\r
   if (FeaturePcdGet (PcdDxeIplSwitchToLongMode)) {\r
-    UINT32                                        RegEax;\r
-    UINT32                                        RegEdx;\r
-    UINT8                                         PhysicalAddressBits;\r
-    EFI_PHYSICAL_ADDRESS                          PageAddress;\r
-    UINTN                                         IndexOfPml4Entries;\r
-    UINTN                                         IndexOfPdpEntries;\r
-    UINTN                                         IndexOfPageDirectoryEntries;\r
-    UINT32                                        NumberOfPml4EntriesNeeded;\r
-    UINT32                                        NumberOfPdpEntriesNeeded;\r
-    PAGE_MAP_AND_DIRECTORY_POINTER                *PageMapLevel4Entry;\r
-    PAGE_MAP_AND_DIRECTORY_POINTER                *PageMap;\r
-    PAGE_MAP_AND_DIRECTORY_POINTER                *PageDirectoryPointerEntry;\r
-    PAGE_TABLE_ENTRY                              *PageDirectoryEntry;\r
-    VOID                                          *Hob;\r
-    BOOLEAN                                       Page1GSupport;\r
-    PAGE_TABLE_1G_ENTRY                           *PageDirectory1GEntry;\r
-    UINT64                                        AddressEncMask;\r
+    UINT32                          RegEax;\r
+    UINT32                          RegEdx;\r
+    UINT8                           PhysicalAddressBits;\r
+    EFI_PHYSICAL_ADDRESS            PageAddress;\r
+    UINTN                           IndexOfPml4Entries;\r
+    UINTN                           IndexOfPdpEntries;\r
+    UINTN                           IndexOfPageDirectoryEntries;\r
+    UINT32                          NumberOfPml4EntriesNeeded;\r
+    UINT32                          NumberOfPdpEntriesNeeded;\r
+    PAGE_MAP_AND_DIRECTORY_POINTER  *PageMapLevel4Entry;\r
+    PAGE_MAP_AND_DIRECTORY_POINTER  *PageMap;\r
+    PAGE_MAP_AND_DIRECTORY_POINTER  *PageDirectoryPointerEntry;\r
+    PAGE_TABLE_ENTRY                *PageDirectoryEntry;\r
+    VOID                            *Hob;\r
+    BOOLEAN                         Page1GSupport;\r
+    PAGE_TABLE_1G_ENTRY             *PageDirectory1GEntry;\r
+    UINT64                          AddressEncMask;\r
 \r
     //\r
     // Make sure AddressEncMask is contained to smallest supported address field\r
@@ -600,11 +625,11 @@ RestoreS3PageTables (
     //\r
     // By architecture only one PageMapLevel4 exists - so lets allocate storage for it.\r
     //\r
-    PageMap = (PAGE_MAP_AND_DIRECTORY_POINTER *)S3NvsPageTableAddress;\r
+    PageMap                = (PAGE_MAP_AND_DIRECTORY_POINTER *)S3NvsPageTableAddress;\r
     S3NvsPageTableAddress += SIZE_4KB;\r
 \r
     Page1GSupport = FALSE;\r
-    if (PcdGetBool(PcdUse1GPageTable)) {\r
+    if (PcdGetBool (PcdUse1GPageTable)) {\r
       AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);\r
       if (RegEax >= 0x80000001) {\r
         AsmCpuid (0x80000001, NULL, NULL, NULL, &RegEdx);\r
@@ -619,12 +644,12 @@ RestoreS3PageTables (
     //\r
     Hob = GetFirstHob (EFI_HOB_TYPE_CPU);\r
     if (Hob != NULL) {\r
-      PhysicalAddressBits = ((EFI_HOB_CPU *) Hob)->SizeOfMemorySpace;\r
+      PhysicalAddressBits = ((EFI_HOB_CPU *)Hob)->SizeOfMemorySpace;\r
     } else {\r
       AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);\r
       if (RegEax >= 0x80000008) {\r
         AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);\r
-        PhysicalAddressBits = (UINT8) RegEax;\r
+        PhysicalAddressBits = (UINT8)RegEax;\r
       } else {\r
         PhysicalAddressBits = 36;\r
       }\r
@@ -644,17 +669,18 @@ RestoreS3PageTables (
     //\r
     if (Build4GPageTableOnly) {\r
       PhysicalAddressBits = 32;\r
-      ZeroMem (PageMap, EFI_PAGES_TO_SIZE(2));\r
+      ZeroMem (PageMap, EFI_PAGES_TO_SIZE (2));\r
     }\r
+\r
     //\r
     // Calculate the table entries needed.\r
     //\r
     if (PhysicalAddressBits <= 39) {\r
       NumberOfPml4EntriesNeeded = 1;\r
-      NumberOfPdpEntriesNeeded = (UINT32)LShiftU64 (1, (PhysicalAddressBits - 30));\r
+      NumberOfPdpEntriesNeeded  = (UINT32)LShiftU64 (1, (PhysicalAddressBits - 30));\r
     } else {\r
       NumberOfPml4EntriesNeeded = (UINT32)LShiftU64 (1, (PhysicalAddressBits - 39));\r
-      NumberOfPdpEntriesNeeded = 512;\r
+      NumberOfPdpEntriesNeeded  = 512;\r
     }\r
 \r
     PageMapLevel4Entry = PageMap;\r
@@ -665,26 +691,26 @@ RestoreS3PageTables (
       // So lets allocate space for them and fill them in in the IndexOfPdpEntries loop.\r
       //\r
       PageDirectoryPointerEntry = (PAGE_MAP_AND_DIRECTORY_POINTER *)S3NvsPageTableAddress;\r
-      S3NvsPageTableAddress += SIZE_4KB;\r
+      S3NvsPageTableAddress    += SIZE_4KB;\r
 \r
       //\r
       // Make a PML4 Entry\r
       //\r
-      PageMapLevel4Entry->Uint64 = (UINT64)(UINTN)PageDirectoryPointerEntry | AddressEncMask;\r
+      PageMapLevel4Entry->Uint64         = (UINT64)(UINTN)PageDirectoryPointerEntry | AddressEncMask;\r
       PageMapLevel4Entry->Bits.ReadWrite = 1;\r
-      PageMapLevel4Entry->Bits.Present = 1;\r
+      PageMapLevel4Entry->Bits.Present   = 1;\r
 \r
       if (Page1GSupport) {\r
-        PageDirectory1GEntry = (VOID *) PageDirectoryPointerEntry;\r
+        PageDirectory1GEntry = (VOID *)PageDirectoryPointerEntry;\r
 \r
         for (IndexOfPageDirectoryEntries = 0; IndexOfPageDirectoryEntries < 512; IndexOfPageDirectoryEntries++, PageDirectory1GEntry++, PageAddress += SIZE_1GB) {\r
           //\r
           // Fill in the Page Directory entries\r
           //\r
-          PageDirectory1GEntry->Uint64 = (UINT64)PageAddress | AddressEncMask;\r
+          PageDirectory1GEntry->Uint64         = (UINT64)PageAddress | AddressEncMask;\r
           PageDirectory1GEntry->Bits.ReadWrite = 1;\r
-          PageDirectory1GEntry->Bits.Present = 1;\r
-          PageDirectory1GEntry->Bits.MustBe1 = 1;\r
+          PageDirectory1GEntry->Bits.Present   = 1;\r
+          PageDirectory1GEntry->Bits.MustBe1   = 1;\r
         }\r
       } else {\r
         for (IndexOfPdpEntries = 0; IndexOfPdpEntries < NumberOfPdpEntriesNeeded; IndexOfPdpEntries++, PageDirectoryPointerEntry++) {\r
@@ -692,34 +718,35 @@ RestoreS3PageTables (
           // Each Directory Pointer entries points to a page of Page Directory entires.\r
           // So allocate space for them and fill them in in the IndexOfPageDirectoryEntries loop.\r
           //\r
-          PageDirectoryEntry = (PAGE_TABLE_ENTRY *)S3NvsPageTableAddress;\r
+          PageDirectoryEntry     = (PAGE_TABLE_ENTRY *)S3NvsPageTableAddress;\r
           S3NvsPageTableAddress += SIZE_4KB;\r
 \r
           //\r
           // Fill in a Page Directory Pointer Entries\r
           //\r
-          PageDirectoryPointerEntry->Uint64 = (UINT64)(UINTN)PageDirectoryEntry | AddressEncMask;\r
+          PageDirectoryPointerEntry->Uint64         = (UINT64)(UINTN)PageDirectoryEntry | AddressEncMask;\r
           PageDirectoryPointerEntry->Bits.ReadWrite = 1;\r
-          PageDirectoryPointerEntry->Bits.Present = 1;\r
+          PageDirectoryPointerEntry->Bits.Present   = 1;\r
 \r
           for (IndexOfPageDirectoryEntries = 0; IndexOfPageDirectoryEntries < 512; IndexOfPageDirectoryEntries++, PageDirectoryEntry++, PageAddress += SIZE_2MB) {\r
             //\r
             // Fill in the Page Directory entries\r
             //\r
-            PageDirectoryEntry->Uint64 = (UINT64)PageAddress | AddressEncMask;\r
+            PageDirectoryEntry->Uint64         = (UINT64)PageAddress | AddressEncMask;\r
             PageDirectoryEntry->Bits.ReadWrite = 1;\r
-            PageDirectoryEntry->Bits.Present = 1;\r
-            PageDirectoryEntry->Bits.MustBe1 = 1;\r
+            PageDirectoryEntry->Bits.Present   = 1;\r
+            PageDirectoryEntry->Bits.MustBe1   = 1;\r
           }\r
         }\r
       }\r
     }\r
-    return ;\r
+\r
+    return;\r
   } else {\r
     //\r
     // If DXE is running 32-bit mode, no need to establish page table.\r
     //\r
-    return ;\r
+    return;\r
   }\r
 }\r
 \r
@@ -739,12 +766,12 @@ S3ResumeExecuteBootScript (
   IN BOOT_SCRIPT_EXECUTOR_VARIABLE  *EfiBootScriptExecutorVariable\r
   )\r
 {\r
-  EFI_STATUS                 Status;\r
-  PEI_SMM_ACCESS_PPI         *SmmAccess;\r
-  UINTN                      Index;\r
-  VOID                       *GuidHob;\r
-  PEI_S3_RESUME_STATE        *PeiS3ResumeState;\r
-  BOOLEAN                    InterruptStatus;\r
+  EFI_STATUS           Status;\r
+  PEI_SMM_ACCESS_PPI   *SmmAccess;\r
+  UINTN                Index;\r
+  VOID                 *GuidHob;\r
+  PEI_S3_RESUME_STATE  *PeiS3ResumeState;\r
+  BOOLEAN              InterruptStatus;\r
 \r
   DEBUG ((DEBUG_INFO, "S3ResumeExecuteBootScript()\n"));\r
 \r
@@ -767,11 +794,11 @@ S3ResumeExecuteBootScript (
     SendSmiIpi (GetApicId ());\r
 \r
     Status = PeiServicesLocatePpi (\r
-                              &gPeiSmmAccessPpiGuid,\r
-                              0,\r
-                              NULL,\r
-                              (VOID **) &SmmAccess\r
-                              );\r
+               &gPeiSmmAccessPpiGuid,\r
+               0,\r
+               NULL,\r
+               (VOID **)&SmmAccess\r
+               );\r
     if (!EFI_ERROR (Status)) {\r
       DEBUG ((DEBUG_INFO, "Close all SMRAM regions before executing boot script\n"));\r
 \r
@@ -819,7 +846,7 @@ S3ResumeExecuteBootScript (
   //\r
   // Prepare data for return back\r
   //\r
-  PeiS3ResumeState = AllocatePool (sizeof(*PeiS3ResumeState));\r
+  PeiS3ResumeState = AllocatePool (sizeof (*PeiS3ResumeState));\r
   if (PeiS3ResumeState == NULL) {\r
     REPORT_STATUS_CODE (\r
       EFI_ERROR_CODE | EFI_ERROR_MAJOR,\r
@@ -827,6 +854,7 @@ S3ResumeExecuteBootScript (
       );\r
     ASSERT (FALSE);\r
   }\r
+\r
   DEBUG ((DEBUG_INFO, "PeiS3ResumeState - %x\r\n", PeiS3ResumeState));\r
   PeiS3ResumeState->ReturnCs           = 0x10;\r
   PeiS3ResumeState->ReturnEntryPoint   = (EFI_PHYSICAL_ADDRESS)(UINTN)S3ResumeBootOs;\r
@@ -865,7 +893,7 @@ S3ResumeExecuteBootScript (
     //\r
     DEBUG ((DEBUG_INFO, "transfer control to Standalone Boot Script Executor\r\n"));\r
     SwitchStack (\r
-      (SWITCH_STACK_ENTRY_POINT) (UINTN) EfiBootScriptExecutorVariable->BootScriptExecutorEntrypoint,\r
+      (SWITCH_STACK_ENTRY_POINT)(UINTN)EfiBootScriptExecutorVariable->BootScriptExecutorEntrypoint,\r
       (VOID *)AcpiS3Context,\r
       (VOID *)PeiS3ResumeState,\r
       (VOID *)(UINTN)(AcpiS3Context->BootScriptStackBase + AcpiS3Context->BootScriptStackSize)\r
@@ -875,8 +903,9 @@ S3ResumeExecuteBootScript (
   //\r
   // Never run to here\r
   //\r
-  CpuDeadLoop();\r
+  CpuDeadLoop ();\r
 }\r
+\r
 /**\r
   Restores the platform to its preboot configuration for an S3 resume and\r
   jumps to the OS waking vector.\r
@@ -914,32 +943,32 @@ S3RestoreConfig2 (
   IN EFI_PEI_S3_RESUME2_PPI  *This\r
   )\r
 {\r
-  EFI_STATUS                                    Status;\r
-  PEI_SMM_ACCESS_PPI                            *SmmAccess;\r
-  UINTN                                         Index;\r
-  ACPI_S3_CONTEXT                               *AcpiS3Context;\r
-  EFI_PHYSICAL_ADDRESS                          TempEfiBootScriptExecutorVariable;\r
-  EFI_PHYSICAL_ADDRESS                          TempAcpiS3Context;\r
-  BOOT_SCRIPT_EXECUTOR_VARIABLE                 *EfiBootScriptExecutorVariable;\r
-  UINTN                                         VarSize;\r
-  EFI_SMRAM_DESCRIPTOR                          *SmramDescriptor;\r
-  SMM_S3_RESUME_STATE                           *SmmS3ResumeState;\r
-  VOID                                          *GuidHob;\r
-  BOOLEAN                                       Build4GPageTableOnly;\r
-  BOOLEAN                                       InterruptStatus;\r
-  IA32_CR0                                      Cr0;\r
-\r
-  TempAcpiS3Context = 0;\r
+  EFI_STATUS                     Status;\r
+  PEI_SMM_ACCESS_PPI             *SmmAccess;\r
+  UINTN                          Index;\r
+  ACPI_S3_CONTEXT                *AcpiS3Context;\r
+  EFI_PHYSICAL_ADDRESS           TempEfiBootScriptExecutorVariable;\r
+  EFI_PHYSICAL_ADDRESS           TempAcpiS3Context;\r
+  BOOT_SCRIPT_EXECUTOR_VARIABLE  *EfiBootScriptExecutorVariable;\r
+  UINTN                          VarSize;\r
+  EFI_SMRAM_DESCRIPTOR           *SmramDescriptor;\r
+  SMM_S3_RESUME_STATE            *SmmS3ResumeState;\r
+  VOID                           *GuidHob;\r
+  BOOLEAN                        Build4GPageTableOnly;\r
+  BOOLEAN                        InterruptStatus;\r
+  IA32_CR0                       Cr0;\r
+\r
+  TempAcpiS3Context                 = 0;\r
   TempEfiBootScriptExecutorVariable = 0;\r
 \r
   DEBUG ((DEBUG_INFO, "Enter S3 PEIM\r\n"));\r
 \r
   VarSize = sizeof (EFI_PHYSICAL_ADDRESS);\r
-  Status = RestoreLockBox (\r
-             &gEfiAcpiVariableGuid,\r
-             &TempAcpiS3Context,\r
-             &VarSize\r
-             );\r
+  Status  = RestoreLockBox (\r
+              &gEfiAcpiVariableGuid,\r
+              &TempAcpiS3Context,\r
+              &VarSize\r
+              );\r
   ASSERT_EFI_ERROR (Status);\r
 \r
   Status = RestoreLockBox (\r
@@ -952,12 +981,12 @@ S3RestoreConfig2 (
   AcpiS3Context = (ACPI_S3_CONTEXT *)(UINTN)TempAcpiS3Context;\r
   ASSERT (AcpiS3Context != NULL);\r
 \r
-  VarSize   = sizeof (EFI_PHYSICAL_ADDRESS);\r
-  Status = RestoreLockBox (\r
-             &gEfiBootScriptExecutorVariableGuid,\r
-             &TempEfiBootScriptExecutorVariable,\r
-             &VarSize\r
-             );\r
+  VarSize = sizeof (EFI_PHYSICAL_ADDRESS);\r
+  Status  = RestoreLockBox (\r
+              &gEfiBootScriptExecutorVariableGuid,\r
+              &TempEfiBootScriptExecutorVariable,\r
+              &VarSize\r
+              );\r
   ASSERT_EFI_ERROR (Status);\r
 \r
   Status = RestoreLockBox (\r
@@ -967,18 +996,18 @@ S3RestoreConfig2 (
              );\r
   ASSERT_EFI_ERROR (Status);\r
 \r
-  EfiBootScriptExecutorVariable = (BOOT_SCRIPT_EXECUTOR_VARIABLE *) (UINTN) TempEfiBootScriptExecutorVariable;\r
+  EfiBootScriptExecutorVariable = (BOOT_SCRIPT_EXECUTOR_VARIABLE *)(UINTN)TempEfiBootScriptExecutorVariable;\r
   ASSERT (EfiBootScriptExecutorVariable != NULL);\r
 \r
-  DEBUG (( DEBUG_INFO, "AcpiS3Context = %x\n", AcpiS3Context));\r
-  DEBUG (( DEBUG_INFO, "Waking Vector = %x\n", ((EFI_ACPI_2_0_FIRMWARE_ACPI_CONTROL_STRUCTURE *) ((UINTN) (AcpiS3Context->AcpiFacsTable)))->FirmwareWakingVector));\r
-  DEBUG (( DEBUG_INFO, "AcpiS3Context->AcpiFacsTable = %x\n", AcpiS3Context->AcpiFacsTable));\r
-  DEBUG (( DEBUG_INFO, "AcpiS3Context->IdtrProfile = %x\n", AcpiS3Context->IdtrProfile));\r
-  DEBUG (( DEBUG_INFO, "AcpiS3Context->S3NvsPageTableAddress = %x\n", AcpiS3Context->S3NvsPageTableAddress));\r
-  DEBUG (( DEBUG_INFO, "AcpiS3Context->S3DebugBufferAddress = %x\n", AcpiS3Context->S3DebugBufferAddress));\r
-  DEBUG (( DEBUG_INFO, "AcpiS3Context->BootScriptStackBase = %x\n", AcpiS3Context->BootScriptStackBase));\r
-  DEBUG (( DEBUG_INFO, "AcpiS3Context->BootScriptStackSize = %x\n", AcpiS3Context->BootScriptStackSize));\r
-  DEBUG (( DEBUG_INFO, "EfiBootScriptExecutorVariable->BootScriptExecutorEntrypoint = %x\n", EfiBootScriptExecutorVariable->BootScriptExecutorEntrypoint));\r
+  DEBUG ((DEBUG_INFO, "AcpiS3Context = %x\n", AcpiS3Context));\r
+  DEBUG ((DEBUG_INFO, "Waking Vector = %x\n", ((EFI_ACPI_2_0_FIRMWARE_ACPI_CONTROL_STRUCTURE *)((UINTN)(AcpiS3Context->AcpiFacsTable)))->FirmwareWakingVector));\r
+  DEBUG ((DEBUG_INFO, "AcpiS3Context->AcpiFacsTable = %x\n", AcpiS3Context->AcpiFacsTable));\r
+  DEBUG ((DEBUG_INFO, "AcpiS3Context->IdtrProfile = %x\n", AcpiS3Context->IdtrProfile));\r
+  DEBUG ((DEBUG_INFO, "AcpiS3Context->S3NvsPageTableAddress = %x\n", AcpiS3Context->S3NvsPageTableAddress));\r
+  DEBUG ((DEBUG_INFO, "AcpiS3Context->S3DebugBufferAddress = %x\n", AcpiS3Context->S3DebugBufferAddress));\r
+  DEBUG ((DEBUG_INFO, "AcpiS3Context->BootScriptStackBase = %x\n", AcpiS3Context->BootScriptStackBase));\r
+  DEBUG ((DEBUG_INFO, "AcpiS3Context->BootScriptStackSize = %x\n", AcpiS3Context->BootScriptStackSize));\r
+  DEBUG ((DEBUG_INFO, "EfiBootScriptExecutorVariable->BootScriptExecutorEntrypoint = %x\n", EfiBootScriptExecutorVariable->BootScriptExecutorEntrypoint));\r
 \r
   //\r
   // Additional step for BootScript integrity - we only handle BootScript and BootScriptExecutor.\r
@@ -1001,6 +1030,7 @@ S3RestoreConfig2 (
     } else {\r
       Build4GPageTableOnly = TRUE;\r
     }\r
+\r
     RestoreS3PageTables ((UINTN)AcpiS3Context->S3NvsPageTableAddress, Build4GPageTableOnly);\r
   }\r
 \r
@@ -1014,19 +1044,19 @@ S3RestoreConfig2 (
     // assumption that it's in 32 bits mode now.\r
     // Add ASSERT code to indicate this assumption.\r
     //\r
-    ASSERT(sizeof (UINTN) == sizeof (UINT32));\r
+    ASSERT (sizeof (UINTN) == sizeof (UINT32));\r
 \r
     Status = PeiServicesLocatePpi (\r
-                              &gPeiSmmAccessPpiGuid,\r
-                              0,\r
-                              NULL,\r
-                              (VOID **) &SmmAccess\r
-                              );\r
+               &gPeiSmmAccessPpiGuid,\r
+               0,\r
+               NULL,\r
+               (VOID **)&SmmAccess\r
+               );\r
     for (Index = 0; !EFI_ERROR (Status); Index++) {\r
       Status = SmmAccess->Open ((EFI_PEI_SERVICES **)GetPeiServicesTablePointer (), SmmAccess, Index);\r
     }\r
 \r
-    SmramDescriptor = (EFI_SMRAM_DESCRIPTOR *) GET_GUID_HOB_DATA (GuidHob);\r
+    SmramDescriptor  = (EFI_SMRAM_DESCRIPTOR *)GET_GUID_HOB_DATA (GuidHob);\r
     SmmS3ResumeState = (SMM_S3_RESUME_STATE *)(UINTN)SmramDescriptor->CpuStart;\r
 \r
     SmmS3ResumeState->ReturnCs           = AsmReadCs ();\r
@@ -1035,19 +1065,19 @@ S3RestoreConfig2 (
     SmmS3ResumeState->ReturnContext2     = (EFI_PHYSICAL_ADDRESS)(UINTN)EfiBootScriptExecutorVariable;\r
     SmmS3ResumeState->ReturnStackPointer = (EFI_PHYSICAL_ADDRESS)STACK_ALIGN_DOWN (&Status);\r
 \r
-    DEBUG (( DEBUG_INFO, "SMM S3 Signature                = %x\n", SmmS3ResumeState->Signature));\r
-    DEBUG (( DEBUG_INFO, "SMM S3 Stack Base               = %x\n", SmmS3ResumeState->SmmS3StackBase));\r
-    DEBUG (( DEBUG_INFO, "SMM S3 Stack Size               = %x\n", SmmS3ResumeState->SmmS3StackSize));\r
-    DEBUG (( DEBUG_INFO, "SMM S3 Resume Entry Point       = %x\n", SmmS3ResumeState->SmmS3ResumeEntryPoint));\r
-    DEBUG (( DEBUG_INFO, "SMM S3 CR0                      = %x\n", SmmS3ResumeState->SmmS3Cr0));\r
-    DEBUG (( DEBUG_INFO, "SMM S3 CR3                      = %x\n", SmmS3ResumeState->SmmS3Cr3));\r
-    DEBUG (( DEBUG_INFO, "SMM S3 CR4                      = %x\n", SmmS3ResumeState->SmmS3Cr4));\r
-    DEBUG (( DEBUG_INFO, "SMM S3 Return CS                = %x\n", SmmS3ResumeState->ReturnCs));\r
-    DEBUG (( DEBUG_INFO, "SMM S3 Return Entry Point       = %x\n", SmmS3ResumeState->ReturnEntryPoint));\r
-    DEBUG (( DEBUG_INFO, "SMM S3 Return Context1          = %x\n", SmmS3ResumeState->ReturnContext1));\r
-    DEBUG (( DEBUG_INFO, "SMM S3 Return Context2          = %x\n", SmmS3ResumeState->ReturnContext2));\r
-    DEBUG (( DEBUG_INFO, "SMM S3 Return Stack Pointer     = %x\n", SmmS3ResumeState->ReturnStackPointer));\r
-    DEBUG (( DEBUG_INFO, "SMM S3 Smst                     = %x\n", SmmS3ResumeState->Smst));\r
+    DEBUG ((DEBUG_INFO, "SMM S3 Signature                = %x\n", SmmS3ResumeState->Signature));\r
+    DEBUG ((DEBUG_INFO, "SMM S3 Stack Base               = %x\n", SmmS3ResumeState->SmmS3StackBase));\r
+    DEBUG ((DEBUG_INFO, "SMM S3 Stack Size               = %x\n", SmmS3ResumeState->SmmS3StackSize));\r
+    DEBUG ((DEBUG_INFO, "SMM S3 Resume Entry Point       = %x\n", SmmS3ResumeState->SmmS3ResumeEntryPoint));\r
+    DEBUG ((DEBUG_INFO, "SMM S3 CR0                      = %x\n", SmmS3ResumeState->SmmS3Cr0));\r
+    DEBUG ((DEBUG_INFO, "SMM S3 CR3                      = %x\n", SmmS3ResumeState->SmmS3Cr3));\r
+    DEBUG ((DEBUG_INFO, "SMM S3 CR4                      = %x\n", SmmS3ResumeState->SmmS3Cr4));\r
+    DEBUG ((DEBUG_INFO, "SMM S3 Return CS                = %x\n", SmmS3ResumeState->ReturnCs));\r
+    DEBUG ((DEBUG_INFO, "SMM S3 Return Entry Point       = %x\n", SmmS3ResumeState->ReturnEntryPoint));\r
+    DEBUG ((DEBUG_INFO, "SMM S3 Return Context1          = %x\n", SmmS3ResumeState->ReturnContext1));\r
+    DEBUG ((DEBUG_INFO, "SMM S3 Return Context2          = %x\n", SmmS3ResumeState->ReturnContext2));\r
+    DEBUG ((DEBUG_INFO, "SMM S3 Return Stack Pointer     = %x\n", SmmS3ResumeState->ReturnStackPointer));\r
+    DEBUG ((DEBUG_INFO, "SMM S3 Smst                     = %x\n", SmmS3ResumeState->Smst));\r
 \r
     if (SmmS3ResumeState->Signature == SMM_S3_RESUME_SMM_32) {\r
       SwitchStack (\r
@@ -1057,6 +1087,7 @@ S3RestoreConfig2 (
         (VOID *)(UINTN)(SmmS3ResumeState->SmmS3StackBase + SmmS3ResumeState->SmmS3StackSize)\r
         );\r
     }\r
+\r
     if (SmmS3ResumeState->Signature == SMM_S3_RESUME_SMM_64) {\r
       //\r
       // Switch to long mode to complete resume.\r
@@ -1085,6 +1116,7 @@ S3RestoreConfig2 (
         Cr0.Bits.PG = 0;\r
         AsmWriteCr0 (Cr0.UintN);\r
       }\r
+\r
       AsmWriteCr3 ((UINTN)SmmS3ResumeState->SmmS3Cr3);\r
 \r
       //\r
@@ -1102,12 +1134,12 @@ S3RestoreConfig2 (
         SmmS3ResumeState->SmmS3StackBase + SmmS3ResumeState->SmmS3StackSize\r
         );\r
     }\r
-\r
   }\r
 \r
-  S3ResumeExecuteBootScript (AcpiS3Context, EfiBootScriptExecutorVariable );\r
+  S3ResumeExecuteBootScript (AcpiS3Context, EfiBootScriptExecutorVariable);\r
   return EFI_SUCCESS;\r
 }\r
+\r
 /**\r
   Main entry for S3 Resume PEIM.\r
 \r
@@ -1122,8 +1154,8 @@ S3RestoreConfig2 (
 EFI_STATUS\r
 EFIAPI\r
 PeimS3ResumeEntryPoint (\r
-  IN EFI_PEI_FILE_HANDLE       FileHandle,\r
-  IN CONST EFI_PEI_SERVICES    **PeiServices\r
+  IN EFI_PEI_FILE_HANDLE     FileHandle,\r
+  IN CONST EFI_PEI_SERVICES  **PeiServices\r
   )\r
 {\r
   EFI_STATUS  Status;\r