2 Architectural MSR Definitions.
4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures
5 are provided for MSRs that contain one or more bit fields. If the MSR value
6 returned is a single 32-bit or 64-bit value, then a data structure is not
9 Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
10 This program and the accompanying materials
11 are licensed and made available under the terms and conditions of the BSD License
12 which accompanies this distribution. The full text of the license may be found at
13 http://opensource.org/licenses/bsd-license.php
15 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
16 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 @par Specification Reference:
19 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,
20 May 2018, Volume 4: Model-Specific-Registers (MSR)
24 #ifndef __ARCHITECTURAL_MSR_H__
25 #define __ARCHITECTURAL_MSR_H__
28 See Section 2.22, "MSRs in Pentium Processors.". Pentium Processor (05_01H).
30 @param ECX MSR_IA32_P5_MC_ADDR (0x00000000)
31 @param EAX Lower 32-bits of MSR value.
32 @param EDX Upper 32-bits of MSR value.
38 Msr = AsmReadMsr64 (MSR_IA32_P5_MC_ADDR);
39 AsmWriteMsr64 (MSR_IA32_P5_MC_ADDR, Msr);
41 @note MSR_IA32_P5_MC_ADDR is defined as IA32_P5_MC_ADDR in SDM.
43 #define MSR_IA32_P5_MC_ADDR 0x00000000
47 See Section 2.22, "MSRs in Pentium Processors.". DF_DM = 05_01H.
49 @param ECX MSR_IA32_P5_MC_TYPE (0x00000001)
50 @param EAX Lower 32-bits of MSR value.
51 @param EDX Upper 32-bits of MSR value.
57 Msr = AsmReadMsr64 (MSR_IA32_P5_MC_TYPE);
58 AsmWriteMsr64 (MSR_IA32_P5_MC_TYPE, Msr);
60 @note MSR_IA32_P5_MC_TYPE is defined as IA32_P5_MC_TYPE in SDM.
62 #define MSR_IA32_P5_MC_TYPE 0x00000001
66 See Section 8.10.5, "Monitor/Mwait Address Range Determination.". Introduced
67 at Display Family / Display Model 0F_03H.
69 @param ECX MSR_IA32_MONITOR_FILTER_SIZE (0x00000006)
70 @param EAX Lower 32-bits of MSR value.
71 @param EDX Upper 32-bits of MSR value.
77 Msr = AsmReadMsr64 (MSR_IA32_MONITOR_FILTER_SIZE);
78 AsmWriteMsr64 (MSR_IA32_MONITOR_FILTER_SIZE, Msr);
80 @note MSR_IA32_MONITOR_FILTER_SIZE is defined as IA32_MONITOR_FILTER_SIZE in SDM.
82 #define MSR_IA32_MONITOR_FILTER_SIZE 0x00000006
86 See Section 17.17, "Time-Stamp Counter.". Introduced at Display Family /
89 @param ECX MSR_IA32_TIME_STAMP_COUNTER (0x00000010)
90 @param EAX Lower 32-bits of MSR value.
91 @param EDX Upper 32-bits of MSR value.
97 Msr = AsmReadMsr64 (MSR_IA32_TIME_STAMP_COUNTER);
98 AsmWriteMsr64 (MSR_IA32_TIME_STAMP_COUNTER, Msr);
100 @note MSR_IA32_TIME_STAMP_COUNTER is defined as IA32_TIME_STAMP_COUNTER in SDM.
102 #define MSR_IA32_TIME_STAMP_COUNTER 0x00000010
106 Platform ID (RO) The operating system can use this MSR to determine "slot"
107 information for the processor and the proper microcode update to load.
108 Introduced at Display Family / Display Model 06_01H.
110 @param ECX MSR_IA32_PLATFORM_ID (0x00000017)
111 @param EAX Lower 32-bits of MSR value.
112 Described by the type MSR_IA32_PLATFORM_ID_REGISTER.
113 @param EDX Upper 32-bits of MSR value.
114 Described by the type MSR_IA32_PLATFORM_ID_REGISTER.
118 MSR_IA32_PLATFORM_ID_REGISTER Msr;
120 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PLATFORM_ID);
122 @note MSR_IA32_PLATFORM_ID is defined as IA32_PLATFORM_ID in SDM.
124 #define MSR_IA32_PLATFORM_ID 0x00000017
127 MSR information returned for MSR index #MSR_IA32_PLATFORM_ID
131 /// Individual bit fields
137 /// [Bits 52:50] Platform Id (RO) Contains information concerning the
138 /// intended platform for the processor.
141 /// 0 0 0 Processor Flag 0.
142 /// 0 0 1 Processor Flag 1
143 /// 0 1 0 Processor Flag 2
144 /// 0 1 1 Processor Flag 3
145 /// 1 0 0 Processor Flag 4
146 /// 1 0 1 Processor Flag 5
147 /// 1 1 0 Processor Flag 6
148 /// 1 1 1 Processor Flag 7
154 /// All bit fields as a 64-bit value
157 } MSR_IA32_PLATFORM_ID_REGISTER
;
163 @param ECX MSR_IA32_APIC_BASE (0x0000001B)
164 @param EAX Lower 32-bits of MSR value.
165 Described by the type MSR_IA32_APIC_BASE_REGISTER.
166 @param EDX Upper 32-bits of MSR value.
167 Described by the type MSR_IA32_APIC_BASE_REGISTER.
171 MSR_IA32_APIC_BASE_REGISTER Msr;
173 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
174 AsmWriteMsr64 (MSR_IA32_APIC_BASE, Msr.Uint64);
176 @note MSR_IA32_APIC_BASE is defined as IA32_APIC_BASE in SDM.
178 #define MSR_IA32_APIC_BASE 0x0000001B
181 MSR information returned for MSR index #MSR_IA32_APIC_BASE
185 /// Individual bit fields
190 /// [Bit 8] BSP flag (R/W).
195 /// [Bit 10] Enable x2APIC mode. Introduced at Display Family / Display
200 /// [Bit 11] APIC Global Enable (R/W).
204 /// [Bits 31:12] APIC Base (R/W).
208 /// [Bits 63:32] APIC Base (R/W).
210 UINT32 ApicBaseHi
:32;
213 /// All bit fields as a 64-bit value
216 } MSR_IA32_APIC_BASE_REGISTER
;
220 Control Features in Intel 64 Processor (R/W). If any one enumeration
221 condition for defined bit field holds.
223 @param ECX MSR_IA32_FEATURE_CONTROL (0x0000003A)
224 @param EAX Lower 32-bits of MSR value.
225 Described by the type MSR_IA32_FEATURE_CONTROL_REGISTER.
226 @param EDX Upper 32-bits of MSR value.
227 Described by the type MSR_IA32_FEATURE_CONTROL_REGISTER.
231 MSR_IA32_FEATURE_CONTROL_REGISTER Msr;
233 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_FEATURE_CONTROL);
234 AsmWriteMsr64 (MSR_IA32_FEATURE_CONTROL, Msr.Uint64);
236 @note MSR_IA32_FEATURE_CONTROL is defined as IA32_FEATURE_CONTROL in SDM.
238 #define MSR_IA32_FEATURE_CONTROL 0x0000003A
241 MSR information returned for MSR index #MSR_IA32_FEATURE_CONTROL
245 /// Individual bit fields
249 /// [Bit 0] Lock bit (R/WO): (1 = locked). When set, locks this MSR from
250 /// being written, writes to this bit will result in GP(0). Note: Once the
251 /// Lock bit is set, the contents of this register cannot be modified.
252 /// Therefore the lock bit must be set after configuring support for Intel
253 /// Virtualization Technology and prior to transferring control to an
254 /// option ROM or the OS. Hence, once the Lock bit is set, the entire
255 /// IA32_FEATURE_CONTROL contents are preserved across RESET when PWRGOOD
256 /// is not deasserted. If any one enumeration condition for defined bit
257 /// field position greater than bit 0 holds.
261 /// [Bit 1] Enable VMX inside SMX operation (R/WL): This bit enables a
262 /// system executive to use VMX in conjunction with SMX to support
263 /// Intel(R) Trusted Execution Technology. BIOS must set this bit only
264 /// when the CPUID function 1 returns VMX feature flag and SMX feature
265 /// flag set (ECX bits 5 and 6 respectively). If CPUID.01H:ECX[5] = 1 &&
266 /// CPUID.01H:ECX[6] = 1.
268 UINT32 EnableVmxInsideSmx
:1;
270 /// [Bit 2] Enable VMX outside SMX operation (R/WL): This bit enables VMX
271 /// for system executive that do not require SMX. BIOS must set this bit
272 /// only when the CPUID function 1 returns VMX feature flag set (ECX bit
273 /// 5). If CPUID.01H:ECX[5] = 1.
275 UINT32 EnableVmxOutsideSmx
:1;
278 /// [Bits 14:8] SENTER Local Function Enables (R/WL): When set, each bit
279 /// in the field represents an enable control for a corresponding SENTER
280 /// function. This bit is supported only if CPUID.1:ECX.[bit 6] is set. If
281 /// CPUID.01H:ECX[6] = 1.
283 UINT32 SenterLocalFunctionEnables
:7;
285 /// [Bit 15] SENTER Global Enable (R/WL): This bit must be set to enable
286 /// SENTER leaf functions. This bit is supported only if CPUID.1:ECX.[bit
287 /// 6] is set. If CPUID.01H:ECX[6] = 1.
289 UINT32 SenterGlobalEnable
:1;
292 /// [Bit 17] SGX Launch Control Enable (R/WL): This bit must be set to
293 /// enable runtime reconfiguration of SGX Launch Control via
294 /// IA32_SGXLEPUBKEYHASHn MSR. If CPUID.(EAX=07H, ECX=0H): ECX[30] = 1.
296 UINT32 SgxLaunchControlEnable
:1;
298 /// [Bit 18] SGX Global Enable (R/WL): This bit must be set to enable SGX
299 /// leaf functions. If CPUID.(EAX=07H, ECX=0H): EBX[2] = 1.
304 /// [Bit 20] LMCE On (R/WL): When set, system software can program the
305 /// MSRs associated with LMCE to configure delivery of some machine check
306 /// exceptions to a single logical processor. If IA32_MCG_CAP[27] = 1.
313 /// All bit fields as a 32-bit value
317 /// All bit fields as a 64-bit value
320 } MSR_IA32_FEATURE_CONTROL_REGISTER
;
324 Per Logical Processor TSC Adjust (R/Write to clear). If CPUID.(EAX=07H,
325 ECX=0H): EBX[1] = 1. THREAD_ADJUST: Local offset value of the IA32_TSC for
326 a logical processor. Reset value is Zero. A write to IA32_TSC will modify
327 the local offset in IA32_TSC_ADJUST and the content of IA32_TSC, but does
328 not affect the internal invariant TSC hardware.
330 @param ECX MSR_IA32_TSC_ADJUST (0x0000003B)
331 @param EAX Lower 32-bits of MSR value.
332 @param EDX Upper 32-bits of MSR value.
338 Msr = AsmReadMsr64 (MSR_IA32_TSC_ADJUST);
339 AsmWriteMsr64 (MSR_IA32_TSC_ADJUST, Msr);
341 @note MSR_IA32_TSC_ADJUST is defined as IA32_TSC_ADJUST in SDM.
343 #define MSR_IA32_TSC_ADJUST 0x0000003B
347 BIOS Update Trigger (W) Executing a WRMSR instruction to this MSR causes a
348 microcode update to be loaded into the processor. See Section 9.11.6,
349 "Microcode Update Loader." A processor may prevent writing to this MSR when
350 loading guest states on VM entries or saving guest states on VM exits.
351 Introduced at Display Family / Display Model 06_01H.
353 @param ECX MSR_IA32_BIOS_UPDT_TRIG (0x00000079)
354 @param EAX Lower 32-bits of MSR value.
355 @param EDX Upper 32-bits of MSR value.
362 AsmWriteMsr64 (MSR_IA32_BIOS_UPDT_TRIG, Msr);
364 @note MSR_IA32_BIOS_UPDT_TRIG is defined as IA32_BIOS_UPDT_TRIG in SDM.
366 #define MSR_IA32_BIOS_UPDT_TRIG 0x00000079
370 BIOS Update Signature (RO) Returns the microcode update signature following
371 the execution of CPUID.01H. A processor may prevent writing to this MSR when
372 loading guest states on VM entries or saving guest states on VM exits.
373 Introduced at Display Family / Display Model 06_01H.
375 @param ECX MSR_IA32_BIOS_SIGN_ID (0x0000008B)
376 @param EAX Lower 32-bits of MSR value.
377 Described by the type MSR_IA32_BIOS_SIGN_ID_REGISTER.
378 @param EDX Upper 32-bits of MSR value.
379 Described by the type MSR_IA32_BIOS_SIGN_ID_REGISTER.
383 MSR_IA32_BIOS_SIGN_ID_REGISTER Msr;
385 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_BIOS_SIGN_ID);
387 @note MSR_IA32_BIOS_SIGN_ID is defined as IA32_BIOS_SIGN_ID in SDM.
389 #define MSR_IA32_BIOS_SIGN_ID 0x0000008B
392 MSR information returned for MSR index #MSR_IA32_BIOS_SIGN_ID
396 /// Individual bit fields
401 /// [Bits 63:32] Microcode update signature. This field contains the
402 /// signature of the currently loaded microcode update when read following
403 /// the execution of the CPUID instruction, function 1. It is required
404 /// that this register field be pre-loaded with zero prior to executing
405 /// the CPUID, function 1. If the field remains equal to zero, then there
406 /// is no microcode update loaded. Another nonzero value will be the
409 UINT32 MicrocodeUpdateSignature
:32;
412 /// All bit fields as a 64-bit value
415 } MSR_IA32_BIOS_SIGN_ID_REGISTER
;
419 IA32_SGXLEPUBKEYHASH[(64*n+63):(64*n)] (R/W) Bits (64*n+63):(64*n) of the
420 SHA256 digest of the SIGSTRUCT.MODULUS for SGX Launch Enclave. On reset, the
421 default value is the digest of Intel's signing key. Read permitted If
422 CPUID.(EAX=12H,ECX=0H):EAX[0]=1, Write permitted if CPUID.(EAX=12H,ECX=0H):
423 EAX[0]=1 && IA32_FEATURE_CONTROL[17] = 1 && IA32_FEATURE_CONTROL[0] = 1.
425 @param ECX MSR_IA32_SGXLEPUBKEYHASHn
426 @param EAX Lower 32-bits of MSR value.
427 @param EDX Upper 32-bits of MSR value.
433 Msr = AsmReadMsr64 (MSR_IA32_SGXLEPUBKEYHASHn);
434 AsmWriteMsr64 (MSR_IA32_SGXLEPUBKEYHASHn, Msr);
436 @note MSR_IA32_SGXLEPUBKEYHASH0 is defined as IA32_SGXLEPUBKEYHASH0 in SDM.
437 MSR_IA32_SGXLEPUBKEYHASH1 is defined as IA32_SGXLEPUBKEYHASH1 in SDM.
438 MSR_IA32_SGXLEPUBKEYHASH2 is defined as IA32_SGXLEPUBKEYHASH2 in SDM.
439 MSR_IA32_SGXLEPUBKEYHASH3 is defined as IA32_SGXLEPUBKEYHASH3 in SDM.
442 #define MSR_IA32_SGXLEPUBKEYHASH0 0x0000008C
443 #define MSR_IA32_SGXLEPUBKEYHASH1 0x0000008D
444 #define MSR_IA32_SGXLEPUBKEYHASH2 0x0000008E
445 #define MSR_IA32_SGXLEPUBKEYHASH3 0x0000008F
450 SMM Monitor Configuration (R/W). If CPUID.01H: ECX[5]=1 or CPUID.01H: ECX[6] =
453 @param ECX MSR_IA32_SMM_MONITOR_CTL (0x0000009B)
454 @param EAX Lower 32-bits of MSR value.
455 Described by the type MSR_IA32_SMM_MONITOR_CTL_REGISTER.
456 @param EDX Upper 32-bits of MSR value.
457 Described by the type MSR_IA32_SMM_MONITOR_CTL_REGISTER.
461 MSR_IA32_SMM_MONITOR_CTL_REGISTER Msr;
463 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SMM_MONITOR_CTL);
464 AsmWriteMsr64 (MSR_IA32_SMM_MONITOR_CTL, Msr.Uint64);
466 @note MSR_IA32_SMM_MONITOR_CTL is defined as IA32_SMM_MONITOR_CTL in SDM.
468 #define MSR_IA32_SMM_MONITOR_CTL 0x0000009B
471 MSR information returned for MSR index #MSR_IA32_SMM_MONITOR_CTL
475 /// Individual bit fields
479 /// [Bit 0] Valid (R/W). The STM may be invoked using VMCALL only if this
480 /// bit is 1. Because VMCALL is used to activate the dual-monitor treatment
481 /// (see Section 34.15.6), the dual-monitor treatment cannot be activated
482 /// if the bit is 0. This bit is cleared when the logical processor is
488 /// [Bit 2] Controls SMI unblocking by VMXOFF (see Section 34.14.4). If
489 /// IA32_VMX_MISC[28].
494 /// [Bits 31:12] MSEG Base (R/W).
500 /// All bit fields as a 32-bit value
504 /// All bit fields as a 64-bit value
507 } MSR_IA32_SMM_MONITOR_CTL_REGISTER
;
510 MSEG header that is located at the physical address specified by the MsegBase
511 field of #MSR_IA32_SMM_MONITOR_CTL_REGISTER.
515 /// Different processors may use different MSEG revision identifiers. These
516 /// identifiers enable software to avoid using an MSEG header formatted for
517 /// one processor on a processor that uses a different format. Software can
518 /// discover the MSEG revision identifier that a processor uses by reading
519 /// the VMX capability MSR IA32_VMX_MISC.
521 UINT32 MsegHeaderRevision
;
523 /// Bits 31:1 of this field are reserved and must be zero. Bit 0 of the field
524 /// is the IA-32e mode SMM feature bit. It indicates whether the logical
525 /// processor will be in IA-32e mode after the STM is activated.
527 UINT32 MonitorFeatures
;
529 UINT32 GdtrBaseOffset
;
535 /// Pad header so total size is 2KB
537 UINT8 Reserved
[SIZE_2KB
- 8 * sizeof (UINT32
)];
541 /// @{ Define values for the MonitorFeatures field of #MSEG_HEADER
543 #define STM_FEATURES_IA32E 0x1
549 Base address of the logical processor's SMRAM image (RO, SMM only). If
552 @param ECX MSR_IA32_SMBASE (0x0000009E)
553 @param EAX Lower 32-bits of MSR value.
554 @param EDX Upper 32-bits of MSR value.
560 Msr = AsmReadMsr64 (MSR_IA32_SMBASE);
562 @note MSR_IA32_SMBASE is defined as IA32_SMBASE in SDM.
564 #define MSR_IA32_SMBASE 0x0000009E
568 General Performance Counters (R/W).
569 MSR_IA32_PMCn is supported if CPUID.0AH: EAX[15:8] > n.
571 @param ECX MSR_IA32_PMCn
572 @param EAX Lower 32-bits of MSR value.
573 @param EDX Upper 32-bits of MSR value.
579 Msr = AsmReadMsr64 (MSR_IA32_PMC0);
580 AsmWriteMsr64 (MSR_IA32_PMC0, Msr);
582 @note MSR_IA32_PMC0 is defined as IA32_PMC0 in SDM.
583 MSR_IA32_PMC1 is defined as IA32_PMC1 in SDM.
584 MSR_IA32_PMC2 is defined as IA32_PMC2 in SDM.
585 MSR_IA32_PMC3 is defined as IA32_PMC3 in SDM.
586 MSR_IA32_PMC4 is defined as IA32_PMC4 in SDM.
587 MSR_IA32_PMC5 is defined as IA32_PMC5 in SDM.
588 MSR_IA32_PMC6 is defined as IA32_PMC6 in SDM.
589 MSR_IA32_PMC7 is defined as IA32_PMC7 in SDM.
592 #define MSR_IA32_PMC0 0x000000C1
593 #define MSR_IA32_PMC1 0x000000C2
594 #define MSR_IA32_PMC2 0x000000C3
595 #define MSR_IA32_PMC3 0x000000C4
596 #define MSR_IA32_PMC4 0x000000C5
597 #define MSR_IA32_PMC5 0x000000C6
598 #define MSR_IA32_PMC6 0x000000C7
599 #define MSR_IA32_PMC7 0x000000C8
604 TSC Frequency Clock Counter (R/Write to clear). If CPUID.06H: ECX[0] = 1.
605 C0_MCNT: C0 TSC Frequency Clock Count Increments at fixed interval (relative
606 to TSC freq.) when the logical processor is in C0. Cleared upon overflow /
607 wrap-around of IA32_APERF.
609 @param ECX MSR_IA32_MPERF (0x000000E7)
610 @param EAX Lower 32-bits of MSR value.
611 @param EDX Upper 32-bits of MSR value.
617 Msr = AsmReadMsr64 (MSR_IA32_MPERF);
618 AsmWriteMsr64 (MSR_IA32_MPERF, Msr);
620 @note MSR_IA32_MPERF is defined as IA32_MPERF in SDM.
622 #define MSR_IA32_MPERF 0x000000E7
626 Actual Performance Clock Counter (R/Write to clear). If CPUID.06H: ECX[0] =
627 1. C0_ACNT: C0 Actual Frequency Clock Count Accumulates core clock counts at
628 the coordinated clock frequency, when the logical processor is in C0.
629 Cleared upon overflow / wrap-around of IA32_MPERF.
631 @param ECX MSR_IA32_APERF (0x000000E8)
632 @param EAX Lower 32-bits of MSR value.
633 @param EDX Upper 32-bits of MSR value.
639 Msr = AsmReadMsr64 (MSR_IA32_APERF);
640 AsmWriteMsr64 (MSR_IA32_APERF, Msr);
642 @note MSR_IA32_APERF is defined as IA32_APERF in SDM.
644 #define MSR_IA32_APERF 0x000000E8
648 MTRR Capability (RO) Section 11.11.2.1, "IA32_MTRR_DEF_TYPE MSR.".
649 Introduced at Display Family / Display Model 06_01H.
651 @param ECX MSR_IA32_MTRRCAP (0x000000FE)
652 @param EAX Lower 32-bits of MSR value.
653 Described by the type MSR_IA32_MTRRCAP_REGISTER.
654 @param EDX Upper 32-bits of MSR value.
655 Described by the type MSR_IA32_MTRRCAP_REGISTER.
659 MSR_IA32_MTRRCAP_REGISTER Msr;
661 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRRCAP);
663 @note MSR_IA32_MTRRCAP is defined as IA32_MTRRCAP in SDM.
665 #define MSR_IA32_MTRRCAP 0x000000FE
668 MSR information returned for MSR index #MSR_IA32_MTRRCAP
672 /// Individual bit fields
676 /// [Bits 7:0] VCNT: The number of variable memory type ranges in the
681 /// [Bit 8] Fixed range MTRRs are supported when set.
686 /// [Bit 10] WC Supported when set.
690 /// [Bit 11] SMRR Supported when set.
697 /// All bit fields as a 32-bit value
701 /// All bit fields as a 64-bit value
704 } MSR_IA32_MTRRCAP_REGISTER
;
708 SYSENTER_CS_MSR (R/W). Introduced at Display Family / Display Model 06_01H.
710 @param ECX MSR_IA32_SYSENTER_CS (0x00000174)
711 @param EAX Lower 32-bits of MSR value.
712 Described by the type MSR_IA32_SYSENTER_CS_REGISTER.
713 @param EDX Upper 32-bits of MSR value.
714 Described by the type MSR_IA32_SYSENTER_CS_REGISTER.
718 MSR_IA32_SYSENTER_CS_REGISTER Msr;
720 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SYSENTER_CS);
721 AsmWriteMsr64 (MSR_IA32_SYSENTER_CS, Msr.Uint64);
723 @note MSR_IA32_SYSENTER_CS is defined as IA32_SYSENTER_CS in SDM.
725 #define MSR_IA32_SYSENTER_CS 0x00000174
728 MSR information returned for MSR index #MSR_IA32_SYSENTER_CS
732 /// Individual bit fields
736 /// [Bits 15:0] CS Selector.
743 /// All bit fields as a 32-bit value
747 /// All bit fields as a 64-bit value
750 } MSR_IA32_SYSENTER_CS_REGISTER
;
754 SYSENTER_ESP_MSR (R/W). Introduced at Display Family / Display Model 06_01H.
756 @param ECX MSR_IA32_SYSENTER_ESP (0x00000175)
757 @param EAX Lower 32-bits of MSR value.
758 @param EDX Upper 32-bits of MSR value.
764 Msr = AsmReadMsr64 (MSR_IA32_SYSENTER_ESP);
765 AsmWriteMsr64 (MSR_IA32_SYSENTER_ESP, Msr);
767 @note MSR_IA32_SYSENTER_ESP is defined as IA32_SYSENTER_ESP in SDM.
769 #define MSR_IA32_SYSENTER_ESP 0x00000175
773 SYSENTER_EIP_MSR (R/W). Introduced at Display Family / Display Model 06_01H.
775 @param ECX MSR_IA32_SYSENTER_EIP (0x00000176)
776 @param EAX Lower 32-bits of MSR value.
777 @param EDX Upper 32-bits of MSR value.
783 Msr = AsmReadMsr64 (MSR_IA32_SYSENTER_EIP);
784 AsmWriteMsr64 (MSR_IA32_SYSENTER_EIP, Msr);
786 @note MSR_IA32_SYSENTER_EIP is defined as IA32_SYSENTER_EIP in SDM.
788 #define MSR_IA32_SYSENTER_EIP 0x00000176
792 Global Machine Check Capability (RO). Introduced at Display Family / Display
795 @param ECX MSR_IA32_MCG_CAP (0x00000179)
796 @param EAX Lower 32-bits of MSR value.
797 Described by the type MSR_IA32_MCG_CAP_REGISTER.
798 @param EDX Upper 32-bits of MSR value.
799 Described by the type MSR_IA32_MCG_CAP_REGISTER.
803 MSR_IA32_MCG_CAP_REGISTER Msr;
805 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_CAP);
807 @note MSR_IA32_MCG_CAP is defined as IA32_MCG_CAP in SDM.
809 #define MSR_IA32_MCG_CAP 0x00000179
812 MSR information returned for MSR index #MSR_IA32_MCG_CAP
816 /// Individual bit fields
820 /// [Bits 7:0] Count: Number of reporting banks.
824 /// [Bit 8] MCG_CTL_P: IA32_MCG_CTL is present if this bit is set.
828 /// [Bit 9] MCG_EXT_P: Extended machine check state registers are present
829 /// if this bit is set.
833 /// [Bit 10] MCP_CMCI_P: Support for corrected MC error event is present.
834 /// Introduced at Display Family / Display Model 06_01H.
838 /// [Bit 11] MCG_TES_P: Threshold-based error status register are present
839 /// if this bit is set.
844 /// [Bits 23:16] MCG_EXT_CNT: Number of extended machine check state
845 /// registers present.
847 UINT32 MCG_EXT_CNT
:8;
849 /// [Bit 24] MCG_SER_P: The processor supports software error recovery if
855 /// [Bit 26] MCG_ELOG_P: Indicates that the processor allows platform
856 /// firmware to be invoked when an error is detected so that it may
857 /// provide additional platform specific information in an ACPI format
858 /// "Generic Error Data Entry" that augments the data included in machine
859 /// check bank registers. Introduced at Display Family / Display Model
864 /// [Bit 27] MCG_LMCE_P: Indicates that the processor support extended
865 /// state in IA32_MCG_STATUS and associated MSR necessary to configure
866 /// Local Machine Check Exception (LMCE). Introduced at Display Family /
867 /// Display Model 06_3EH.
874 /// All bit fields as a 32-bit value
878 /// All bit fields as a 64-bit value
881 } MSR_IA32_MCG_CAP_REGISTER
;
885 Global Machine Check Status (R/W0). Introduced at Display Family / Display
888 @param ECX MSR_IA32_MCG_STATUS (0x0000017A)
889 @param EAX Lower 32-bits of MSR value.
890 Described by the type MSR_IA32_MCG_STATUS_REGISTER.
891 @param EDX Upper 32-bits of MSR value.
892 Described by the type MSR_IA32_MCG_STATUS_REGISTER.
896 MSR_IA32_MCG_STATUS_REGISTER Msr;
898 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_STATUS);
899 AsmWriteMsr64 (MSR_IA32_MCG_STATUS, Msr.Uint64);
901 @note MSR_IA32_MCG_STATUS is defined as IA32_MCG_STATUS in SDM.
903 #define MSR_IA32_MCG_STATUS 0x0000017A
906 MSR information returned for MSR index #MSR_IA32_MCG_STATUS
910 /// Individual bit fields
914 /// [Bit 0] RIPV. Restart IP valid. Introduced at Display Family / Display
919 /// [Bit 1] EIPV. Error IP valid. Introduced at Display Family / Display
924 /// [Bit 2] MCIP. Machine check in progress. Introduced at Display Family
925 /// / Display Model 06_01H.
929 /// [Bit 3] LMCE_S. If IA32_MCG_CAP.LMCE_P[2 7] =1.
936 /// All bit fields as a 32-bit value
940 /// All bit fields as a 64-bit value
943 } MSR_IA32_MCG_STATUS_REGISTER
;
947 Global Machine Check Control (R/W). If IA32_MCG_CAP.CTL_P[8] =1.
949 @param ECX MSR_IA32_MCG_CTL (0x0000017B)
950 @param EAX Lower 32-bits of MSR value.
951 @param EDX Upper 32-bits of MSR value.
957 Msr = AsmReadMsr64 (MSR_IA32_MCG_CTL);
958 AsmWriteMsr64 (MSR_IA32_MCG_CTL, Msr);
960 @note MSR_IA32_MCG_CTL is defined as IA32_MCG_CTL in SDM.
962 #define MSR_IA32_MCG_CTL 0x0000017B
966 Performance Event Select Register n (R/W). If CPUID.0AH: EAX[15:8] > n.
968 @param ECX MSR_IA32_PERFEVTSELn
969 @param EAX Lower 32-bits of MSR value.
970 Described by the type MSR_IA32_PERFEVTSEL_REGISTER.
971 @param EDX Upper 32-bits of MSR value.
972 Described by the type MSR_IA32_PERFEVTSEL_REGISTER.
976 MSR_IA32_PERFEVTSEL_REGISTER Msr;
978 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERFEVTSEL0);
979 AsmWriteMsr64 (MSR_IA32_PERFEVTSEL0, Msr.Uint64);
981 @note MSR_IA32_PERFEVTSEL0 is defined as IA32_PERFEVTSEL0 in SDM.
982 MSR_IA32_PERFEVTSEL1 is defined as IA32_PERFEVTSEL1 in SDM.
983 MSR_IA32_PERFEVTSEL2 is defined as IA32_PERFEVTSEL2 in SDM.
984 MSR_IA32_PERFEVTSEL3 is defined as IA32_PERFEVTSEL3 in SDM.
987 #define MSR_IA32_PERFEVTSEL0 0x00000186
988 #define MSR_IA32_PERFEVTSEL1 0x00000187
989 #define MSR_IA32_PERFEVTSEL2 0x00000188
990 #define MSR_IA32_PERFEVTSEL3 0x00000189
994 MSR information returned for MSR indexes #MSR_IA32_PERFEVTSEL0 to
995 #MSR_IA32_PERFEVTSEL3
999 /// Individual bit fields
1003 /// [Bits 7:0] Event Select: Selects a performance event logic unit.
1005 UINT32 EventSelect
:8;
1007 /// [Bits 15:8] UMask: Qualifies the microarchitectural condition to
1008 /// detect on the selected event logic.
1012 /// [Bit 16] USR: Counts while in privilege level is not ring 0.
1016 /// [Bit 17] OS: Counts while in privilege level is ring 0.
1020 /// [Bit 18] Edge: Enables edge detection if set.
1024 /// [Bit 19] PC: enables pin control.
1028 /// [Bit 20] INT: enables interrupt on counter overflow.
1032 /// [Bit 21] AnyThread: When set to 1, it enables counting the associated
1033 /// event conditions occurring across all logical processors sharing a
1034 /// processor core. When set to 0, the counter only increments the
1035 /// associated event conditions occurring in the logical processor which
1036 /// programmed the MSR.
1040 /// [Bit 22] EN: enables the corresponding performance counter to commence
1041 /// counting when this bit is set.
1045 /// [Bit 23] INV: invert the CMASK.
1049 /// [Bits 31:24] CMASK: When CMASK is not zero, the corresponding
1050 /// performance counter increments each cycle if the event count is
1051 /// greater than or equal to the CMASK.
1057 /// All bit fields as a 32-bit value
1061 /// All bit fields as a 64-bit value
1064 } MSR_IA32_PERFEVTSEL_REGISTER
;
1068 Current performance state(P-State) operating point (RO). Introduced at
1069 Display Family / Display Model 0F_03H.
1071 @param ECX MSR_IA32_PERF_STATUS (0x00000198)
1072 @param EAX Lower 32-bits of MSR value.
1073 Described by the type MSR_IA32_PERF_STATUS_REGISTER.
1074 @param EDX Upper 32-bits of MSR value.
1075 Described by the type MSR_IA32_PERF_STATUS_REGISTER.
1077 <b>Example usage</b>
1079 MSR_IA32_PERF_STATUS_REGISTER Msr;
1081 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_STATUS);
1083 @note MSR_IA32_PERF_STATUS is defined as IA32_PERF_STATUS in SDM.
1085 #define MSR_IA32_PERF_STATUS 0x00000198
1088 MSR information returned for MSR index #MSR_IA32_PERF_STATUS
1092 /// Individual bit fields
1096 /// [Bits 15:0] Current performance State Value.
1099 UINT32 Reserved1
:16;
1100 UINT32 Reserved2
:32;
1103 /// All bit fields as a 32-bit value
1107 /// All bit fields as a 64-bit value
1110 } MSR_IA32_PERF_STATUS_REGISTER
;
1114 (R/W). Introduced at Display Family / Display Model 0F_03H.
1116 @param ECX MSR_IA32_PERF_CTL (0x00000199)
1117 @param EAX Lower 32-bits of MSR value.
1118 Described by the type MSR_IA32_PERF_CTL_REGISTER.
1119 @param EDX Upper 32-bits of MSR value.
1120 Described by the type MSR_IA32_PERF_CTL_REGISTER.
1122 <b>Example usage</b>
1124 MSR_IA32_PERF_CTL_REGISTER Msr;
1126 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_CTL);
1127 AsmWriteMsr64 (MSR_IA32_PERF_CTL, Msr.Uint64);
1129 @note MSR_IA32_PERF_CTL is defined as IA32_PERF_CTL in SDM.
1131 #define MSR_IA32_PERF_CTL 0x00000199
1134 MSR information returned for MSR index #MSR_IA32_PERF_CTL
1138 /// Individual bit fields
1142 /// [Bits 15:0] Target performance State Value.
1144 UINT32 TargetState
:16;
1145 UINT32 Reserved1
:16;
1147 /// [Bit 32] IDA Engage. (R/W) When set to 1: disengages IDA. 06_0FH
1151 UINT32 Reserved2
:31;
1154 /// All bit fields as a 64-bit value
1157 } MSR_IA32_PERF_CTL_REGISTER
;
1161 Clock Modulation Control (R/W) See Section 14.7.3, "Software Controlled
1162 Clock Modulation.". If CPUID.01H:EDX[22] = 1.
1164 @param ECX MSR_IA32_CLOCK_MODULATION (0x0000019A)
1165 @param EAX Lower 32-bits of MSR value.
1166 Described by the type MSR_IA32_CLOCK_MODULATION_REGISTER.
1167 @param EDX Upper 32-bits of MSR value.
1168 Described by the type MSR_IA32_CLOCK_MODULATION_REGISTER.
1170 <b>Example usage</b>
1172 MSR_IA32_CLOCK_MODULATION_REGISTER Msr;
1174 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_CLOCK_MODULATION);
1175 AsmWriteMsr64 (MSR_IA32_CLOCK_MODULATION, Msr.Uint64);
1177 @note MSR_IA32_CLOCK_MODULATION is defined as IA32_CLOCK_MODULATION in SDM.
1179 #define MSR_IA32_CLOCK_MODULATION 0x0000019A
1182 MSR information returned for MSR index #MSR_IA32_CLOCK_MODULATION
1186 /// Individual bit fields
1190 /// [Bit 0] Extended On-Demand Clock Modulation Duty Cycle:. If
1191 /// CPUID.06H:EAX[5] = 1.
1193 UINT32 ExtendedOnDemandClockModulationDutyCycle
:1;
1195 /// [Bits 3:1] On-Demand Clock Modulation Duty Cycle: Specific encoded
1196 /// values for target duty cycle modulation. If CPUID.01H:EDX[22] = 1.
1198 UINT32 OnDemandClockModulationDutyCycle
:3;
1200 /// [Bit 4] On-Demand Clock Modulation Enable: Set 1 to enable modulation.
1201 /// If CPUID.01H:EDX[22] = 1.
1203 UINT32 OnDemandClockModulationEnable
:1;
1204 UINT32 Reserved1
:27;
1205 UINT32 Reserved2
:32;
1208 /// All bit fields as a 32-bit value
1212 /// All bit fields as a 64-bit value
1215 } MSR_IA32_CLOCK_MODULATION_REGISTER
;
1219 Thermal Interrupt Control (R/W) Enables and disables the generation of an
1220 interrupt on temperature transitions detected with the processor's thermal
1221 sensors and thermal monitor. See Section 14.7.2, "Thermal Monitor.".
1222 If CPUID.01H:EDX[22] = 1
1224 @param ECX MSR_IA32_THERM_INTERRUPT (0x0000019B)
1225 @param EAX Lower 32-bits of MSR value.
1226 Described by the type MSR_IA32_THERM_INTERRUPT_REGISTER.
1227 @param EDX Upper 32-bits of MSR value.
1228 Described by the type MSR_IA32_THERM_INTERRUPT_REGISTER.
1230 <b>Example usage</b>
1232 MSR_IA32_THERM_INTERRUPT_REGISTER Msr;
1234 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_THERM_INTERRUPT);
1235 AsmWriteMsr64 (MSR_IA32_THERM_INTERRUPT, Msr.Uint64);
1237 @note MSR_IA32_THERM_INTERRUPT is defined as IA32_THERM_INTERRUPT in SDM.
1239 #define MSR_IA32_THERM_INTERRUPT 0x0000019B
1242 MSR information returned for MSR index #MSR_IA32_THERM_INTERRUPT
1246 /// Individual bit fields
1250 /// [Bit 0] High-Temperature Interrupt Enable. If CPUID.01H:EDX[22] = 1.
1252 UINT32 HighTempEnable
:1;
1254 /// [Bit 1] Low-Temperature Interrupt Enable. If CPUID.01H:EDX[22] = 1.
1256 UINT32 LowTempEnable
:1;
1258 /// [Bit 2] PROCHOT# Interrupt Enable. If CPUID.01H:EDX[22] = 1.
1260 UINT32 PROCHOT_Enable
:1;
1262 /// [Bit 3] FORCEPR# Interrupt Enable. If CPUID.01H:EDX[22] = 1.
1264 UINT32 FORCEPR_Enable
:1;
1266 /// [Bit 4] Critical Temperature Interrupt Enable.
1267 /// If CPUID.01H:EDX[22] = 1.
1269 UINT32 CriticalTempEnable
:1;
1272 /// [Bits 14:8] Threshold #1 Value. If CPUID.01H:EDX[22] = 1.
1274 UINT32 Threshold1
:7;
1276 /// [Bit 15] Threshold #1 Interrupt Enable. If CPUID.01H:EDX[22] = 1.
1278 UINT32 Threshold1Enable
:1;
1280 /// [Bits 22:16] Threshold #2 Value. If CPUID.01H:EDX[22] = 1.
1282 UINT32 Threshold2
:7;
1284 /// [Bit 23] Threshold #2 Interrupt Enable. If CPUID.01H:EDX[22] = 1.
1286 UINT32 Threshold2Enable
:1;
1288 /// [Bit 24] Power Limit Notification Enable. If CPUID.06H:EAX[4] = 1.
1290 UINT32 PowerLimitNotificationEnable
:1;
1292 UINT32 Reserved3
:32;
1295 /// All bit fields as a 32-bit value
1299 /// All bit fields as a 64-bit value
1302 } MSR_IA32_THERM_INTERRUPT_REGISTER
;
1306 Thermal Status Information (RO) Contains status information about the
1307 processor's thermal sensor and automatic thermal monitoring facilities. See
1308 Section 14.7.2, "Thermal Monitor". If CPUID.01H:EDX[22] = 1.
1310 @param ECX MSR_IA32_THERM_STATUS (0x0000019C)
1311 @param EAX Lower 32-bits of MSR value.
1312 Described by the type MSR_IA32_THERM_STATUS_REGISTER.
1313 @param EDX Upper 32-bits of MSR value.
1314 Described by the type MSR_IA32_THERM_STATUS_REGISTER.
1316 <b>Example usage</b>
1318 MSR_IA32_THERM_STATUS_REGISTER Msr;
1320 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_THERM_STATUS);
1322 @note MSR_IA32_THERM_STATUS is defined as IA32_THERM_STATUS in SDM.
1324 #define MSR_IA32_THERM_STATUS 0x0000019C
1327 MSR information returned for MSR index #MSR_IA32_THERM_STATUS
1331 /// Individual bit fields
1335 /// [Bit 0] Thermal Status (RO):. If CPUID.01H:EDX[22] = 1.
1337 UINT32 ThermalStatus
:1;
1339 /// [Bit 1] Thermal Status Log (R/W):. If CPUID.01H:EDX[22] = 1.
1341 UINT32 ThermalStatusLog
:1;
1343 /// [Bit 2] PROCHOT # or FORCEPR# event (RO). If CPUID.01H:EDX[22] = 1.
1345 UINT32 PROCHOT_FORCEPR_Event
:1;
1347 /// [Bit 3] PROCHOT # or FORCEPR# log (R/WC0). If CPUID.01H:EDX[22] = 1.
1349 UINT32 PROCHOT_FORCEPR_Log
:1;
1351 /// [Bit 4] Critical Temperature Status (RO). If CPUID.01H:EDX[22] = 1.
1353 UINT32 CriticalTempStatus
:1;
1355 /// [Bit 5] Critical Temperature Status log (R/WC0).
1356 /// If CPUID.01H:EDX[22] = 1.
1358 UINT32 CriticalTempStatusLog
:1;
1360 /// [Bit 6] Thermal Threshold #1 Status (RO). If CPUID.01H:ECX[8] = 1.
1362 UINT32 ThermalThreshold1Status
:1;
1364 /// [Bit 7] Thermal Threshold #1 log (R/WC0). If CPUID.01H:ECX[8] = 1.
1366 UINT32 ThermalThreshold1Log
:1;
1368 /// [Bit 8] Thermal Threshold #2 Status (RO). If CPUID.01H:ECX[8] = 1.
1370 UINT32 ThermalThreshold2Status
:1;
1372 /// [Bit 9] Thermal Threshold #2 log (R/WC0). If CPUID.01H:ECX[8] = 1.
1374 UINT32 ThermalThreshold2Log
:1;
1376 /// [Bit 10] Power Limitation Status (RO). If CPUID.06H:EAX[4] = 1.
1378 UINT32 PowerLimitStatus
:1;
1380 /// [Bit 11] Power Limitation log (R/WC0). If CPUID.06H:EAX[4] = 1.
1382 UINT32 PowerLimitLog
:1;
1384 /// [Bit 12] Current Limit Status (RO). If CPUID.06H:EAX[7] = 1.
1386 UINT32 CurrentLimitStatus
:1;
1388 /// [Bit 13] Current Limit log (R/WC0). If CPUID.06H:EAX[7] = 1.
1390 UINT32 CurrentLimitLog
:1;
1392 /// [Bit 14] Cross Domain Limit Status (RO). If CPUID.06H:EAX[7] = 1.
1394 UINT32 CrossDomainLimitStatus
:1;
1396 /// [Bit 15] Cross Domain Limit log (R/WC0). If CPUID.06H:EAX[7] = 1.
1398 UINT32 CrossDomainLimitLog
:1;
1400 /// [Bits 22:16] Digital Readout (RO). If CPUID.06H:EAX[0] = 1.
1402 UINT32 DigitalReadout
:7;
1405 /// [Bits 30:27] Resolution in Degrees Celsius (RO). If CPUID.06H:EAX[0] =
1408 UINT32 ResolutionInDegreesCelsius
:4;
1410 /// [Bit 31] Reading Valid (RO). If CPUID.06H:EAX[0] = 1.
1412 UINT32 ReadingValid
:1;
1413 UINT32 Reserved2
:32;
1416 /// All bit fields as a 32-bit value
1420 /// All bit fields as a 64-bit value
1423 } MSR_IA32_THERM_STATUS_REGISTER
;
1427 Enable Misc. Processor Features (R/W) Allows a variety of processor
1428 functions to be enabled and disabled.
1430 @param ECX MSR_IA32_MISC_ENABLE (0x000001A0)
1431 @param EAX Lower 32-bits of MSR value.
1432 Described by the type MSR_IA32_MISC_ENABLE_REGISTER.
1433 @param EDX Upper 32-bits of MSR value.
1434 Described by the type MSR_IA32_MISC_ENABLE_REGISTER.
1436 <b>Example usage</b>
1438 MSR_IA32_MISC_ENABLE_REGISTER Msr;
1440 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MISC_ENABLE);
1441 AsmWriteMsr64 (MSR_IA32_MISC_ENABLE, Msr.Uint64);
1443 @note MSR_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.
1445 #define MSR_IA32_MISC_ENABLE 0x000001A0
1448 MSR information returned for MSR index #MSR_IA32_MISC_ENABLE
1452 /// Individual bit fields
1456 /// [Bit 0] Fast-Strings Enable When set, the fast-strings feature (for
1457 /// REP MOVS and REP STORS) is enabled (default); when clear, fast-strings
1458 /// are disabled. Introduced at Display Family / Display Model 0F_0H.
1460 UINT32 FastStrings
:1;
1463 /// [Bit 3] Automatic Thermal Control Circuit Enable (R/W) 1 = Setting
1464 /// this bit enables the thermal control circuit (TCC) portion of the
1465 /// Intel Thermal Monitor feature. This allows the processor to
1466 /// automatically reduce power consumption in response to TCC activation.
1467 /// 0 = Disabled. Note: In some products clearing this bit might be
1468 /// ignored in critical thermal conditions, and TM1, TM2 and adaptive
1469 /// thermal throttling will still be activated. The default value of this
1470 /// field varies with product. See respective tables where default value is
1471 /// listed. Introduced at Display Family / Display Model 0F_0H.
1473 UINT32 AutomaticThermalControlCircuit
:1;
1476 /// [Bit 7] Performance Monitoring Available (R) 1 = Performance
1477 /// monitoring enabled 0 = Performance monitoring disabled. Introduced at
1478 /// Display Family / Display Model 0F_0H.
1480 UINT32 PerformanceMonitoring
:1;
1483 /// [Bit 11] Branch Trace Storage Unavailable (RO) 1 = Processor doesn't
1484 /// support branch trace storage (BTS) 0 = BTS is supported. Introduced at
1485 /// Display Family / Display Model 0F_0H.
1489 /// [Bit 12] Processor Event Based Sampling (PEBS) Unavailable (RO) 1 =
1490 /// PEBS is not supported; 0 = PEBS is supported. Introduced at Display
1491 /// Family / Display Model 06_0FH.
1496 /// [Bit 16] Enhanced Intel SpeedStep Technology Enable (R/W) 0= Enhanced
1497 /// Intel SpeedStep Technology disabled 1 = Enhanced Intel SpeedStep
1498 /// Technology enabled. If CPUID.01H: ECX[7] =1.
1503 /// [Bit 18] ENABLE MONITOR FSM (R/W) When this bit is set to 0, the
1504 /// MONITOR feature flag is not set (CPUID.01H:ECX[bit 3] = 0). This
1505 /// indicates that MONITOR/MWAIT are not supported. Software attempts to
1506 /// execute MONITOR/MWAIT will cause #UD when this bit is 0. When this bit
1507 /// is set to 1 (default), MONITOR/MWAIT are supported (CPUID.01H:ECX[bit
1508 /// 3] = 1). If the SSE3 feature flag ECX[0] is not set (CPUID.01H:ECX[bit
1509 /// 0] = 0), the OS must not attempt to alter this bit. BIOS must leave it
1510 /// in the default state. Writing this bit when the SSE3 feature flag is
1511 /// set to 0 may generate a #GP exception. Introduced at Display Family /
1512 /// Display Model 0F_03H.
1517 /// [Bit 22] Limit CPUID Maxval (R/W) When this bit is set to 1, CPUID.00H
1518 /// returns a maximum value in EAX[7:0] of 2. BIOS should contain a setup
1519 /// question that allows users to specify when the installed OS does not
1520 /// support CPUID functions greater than 2. Before setting this bit, BIOS
1521 /// must execute the CPUID.0H and examine the maximum value returned in
1522 /// EAX[7:0]. If the maximum value is greater than 2, this bit is
1523 /// supported. Otherwise, this bit is not supported. Setting this bit when
1524 /// the maximum value is not greater than 2 may generate a #GP exception.
1525 /// Setting this bit may cause unexpected behavior in software that
1526 /// depends on the availability of CPUID leaves greater than 2. Introduced
1527 /// at Display Family / Display Model 0F_03H.
1529 UINT32 LimitCpuidMaxval
:1;
1531 /// [Bit 23] xTPR Message Disable (R/W) When set to 1, xTPR messages are
1532 /// disabled. xTPR messages are optional messages that allow the processor
1533 /// to inform the chipset of its priority. if CPUID.01H:ECX[14] = 1.
1535 UINT32 xTPR_Message_Disable
:1;
1539 /// [Bit 34] XD Bit Disable (R/W) When set to 1, the Execute Disable Bit
1540 /// feature (XD Bit) is disabled and the XD Bit extended feature flag will
1541 /// be clear (CPUID.80000001H: EDX[20]=0). When set to a 0 (default), the
1542 /// Execute Disable Bit feature (if available) allows the OS to enable PAE
1543 /// paging and take advantage of data only pages. BIOS must not alter the
1544 /// contents of this bit location, if XD bit is not supported. Writing
1545 /// this bit to 1 when the XD Bit extended feature flag is set to 0 may
1546 /// generate a #GP exception. if CPUID.80000001H:EDX[2 0] = 1.
1549 UINT32 Reserved9
:29;
1552 /// All bit fields as a 64-bit value
1555 } MSR_IA32_MISC_ENABLE_REGISTER
;
1559 Performance Energy Bias Hint (R/W). if CPUID.6H:ECX[3] = 1.
1561 @param ECX MSR_IA32_ENERGY_PERF_BIAS (0x000001B0)
1562 @param EAX Lower 32-bits of MSR value.
1563 Described by the type MSR_IA32_ENERGY_PERF_BIAS_REGISTER.
1564 @param EDX Upper 32-bits of MSR value.
1565 Described by the type MSR_IA32_ENERGY_PERF_BIAS_REGISTER.
1567 <b>Example usage</b>
1569 MSR_IA32_ENERGY_PERF_BIAS_REGISTER Msr;
1571 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_ENERGY_PERF_BIAS);
1572 AsmWriteMsr64 (MSR_IA32_ENERGY_PERF_BIAS, Msr.Uint64);
1574 @note MSR_IA32_ENERGY_PERF_BIAS is defined as IA32_ENERGY_PERF_BIAS in SDM.
1576 #define MSR_IA32_ENERGY_PERF_BIAS 0x000001B0
1579 MSR information returned for MSR index #MSR_IA32_ENERGY_PERF_BIAS
1583 /// Individual bit fields
1587 /// [Bits 3:0] Power Policy Preference: 0 indicates preference to highest
1588 /// performance. 15 indicates preference to maximize energy saving.
1590 UINT32 PowerPolicyPreference
:4;
1591 UINT32 Reserved1
:28;
1592 UINT32 Reserved2
:32;
1595 /// All bit fields as a 32-bit value
1599 /// All bit fields as a 64-bit value
1602 } MSR_IA32_ENERGY_PERF_BIAS_REGISTER
;
1606 Package Thermal Status Information (RO) Contains status information about
1607 the package's thermal sensor. See Section 14.8, "Package Level Thermal
1608 Management.". If CPUID.06H: EAX[6] = 1.
1610 @param ECX MSR_IA32_PACKAGE_THERM_STATUS (0x000001B1)
1611 @param EAX Lower 32-bits of MSR value.
1612 Described by the type MSR_IA32_PACKAGE_THERM_STATUS_REGISTER.
1613 @param EDX Upper 32-bits of MSR value.
1614 Described by the type MSR_IA32_PACKAGE_THERM_STATUS_REGISTER.
1616 <b>Example usage</b>
1618 MSR_IA32_PACKAGE_THERM_STATUS_REGISTER Msr;
1620 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PACKAGE_THERM_STATUS);
1622 @note MSR_IA32_PACKAGE_THERM_STATUS is defined as IA32_PACKAGE_THERM_STATUS in SDM.
1624 #define MSR_IA32_PACKAGE_THERM_STATUS 0x000001B1
1627 MSR information returned for MSR index #MSR_IA32_PACKAGE_THERM_STATUS
1631 /// Individual bit fields
1635 /// [Bit 0] Pkg Thermal Status (RO):.
1637 UINT32 ThermalStatus
:1;
1639 /// [Bit 1] Pkg Thermal Status Log (R/W):.
1641 UINT32 ThermalStatusLog
:1;
1643 /// [Bit 2] Pkg PROCHOT # event (RO).
1645 UINT32 PROCHOT_Event
:1;
1647 /// [Bit 3] Pkg PROCHOT # log (R/WC0).
1649 UINT32 PROCHOT_Log
:1;
1651 /// [Bit 4] Pkg Critical Temperature Status (RO).
1653 UINT32 CriticalTempStatus
:1;
1655 /// [Bit 5] Pkg Critical Temperature Status log (R/WC0).
1657 UINT32 CriticalTempStatusLog
:1;
1659 /// [Bit 6] Pkg Thermal Threshold #1 Status (RO).
1661 UINT32 ThermalThreshold1Status
:1;
1663 /// [Bit 7] Pkg Thermal Threshold #1 log (R/WC0).
1665 UINT32 ThermalThreshold1Log
:1;
1667 /// [Bit 8] Pkg Thermal Threshold #2 Status (RO).
1669 UINT32 ThermalThreshold2Status
:1;
1671 /// [Bit 9] Pkg Thermal Threshold #1 log (R/WC0).
1673 UINT32 ThermalThreshold2Log
:1;
1675 /// [Bit 10] Pkg Power Limitation Status (RO).
1677 UINT32 PowerLimitStatus
:1;
1679 /// [Bit 11] Pkg Power Limitation log (R/WC0).
1681 UINT32 PowerLimitLog
:1;
1684 /// [Bits 22:16] Pkg Digital Readout (RO).
1686 UINT32 DigitalReadout
:7;
1688 UINT32 Reserved3
:32;
1691 /// All bit fields as a 32-bit value
1695 /// All bit fields as a 64-bit value
1698 } MSR_IA32_PACKAGE_THERM_STATUS_REGISTER
;
1702 Pkg Thermal Interrupt Control (R/W) Enables and disables the generation of
1703 an interrupt on temperature transitions detected with the package's thermal
1704 sensor. See Section 14.8, "Package Level Thermal Management.". If CPUID.06H:
1707 @param ECX MSR_IA32_PACKAGE_THERM_INTERRUPT (0x000001B2)
1708 @param EAX Lower 32-bits of MSR value.
1709 Described by the type MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER.
1710 @param EDX Upper 32-bits of MSR value.
1711 Described by the type MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER.
1713 <b>Example usage</b>
1715 MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER Msr;
1717 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PACKAGE_THERM_INTERRUPT);
1718 AsmWriteMsr64 (MSR_IA32_PACKAGE_THERM_INTERRUPT, Msr.Uint64);
1720 @note MSR_IA32_PACKAGE_THERM_INTERRUPT is defined as IA32_PACKAGE_THERM_INTERRUPT in SDM.
1722 #define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001B2
1725 MSR information returned for MSR index #MSR_IA32_PACKAGE_THERM_INTERRUPT
1729 /// Individual bit fields
1733 /// [Bit 0] Pkg High-Temperature Interrupt Enable.
1735 UINT32 HighTempEnable
:1;
1737 /// [Bit 1] Pkg Low-Temperature Interrupt Enable.
1739 UINT32 LowTempEnable
:1;
1741 /// [Bit 2] Pkg PROCHOT# Interrupt Enable.
1743 UINT32 PROCHOT_Enable
:1;
1746 /// [Bit 4] Pkg Overheat Interrupt Enable.
1748 UINT32 OverheatEnable
:1;
1751 /// [Bits 14:8] Pkg Threshold #1 Value.
1753 UINT32 Threshold1
:7;
1755 /// [Bit 15] Pkg Threshold #1 Interrupt Enable.
1757 UINT32 Threshold1Enable
:1;
1759 /// [Bits 22:16] Pkg Threshold #2 Value.
1761 UINT32 Threshold2
:7;
1763 /// [Bit 23] Pkg Threshold #2 Interrupt Enable.
1765 UINT32 Threshold2Enable
:1;
1767 /// [Bit 24] Pkg Power Limit Notification Enable.
1769 UINT32 PowerLimitNotificationEnable
:1;
1771 UINT32 Reserved4
:32;
1774 /// All bit fields as a 32-bit value
1778 /// All bit fields as a 64-bit value
1781 } MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER
;
1785 Trace/Profile Resource Control (R/W). Introduced at Display Family / Display
1788 @param ECX MSR_IA32_DEBUGCTL (0x000001D9)
1789 @param EAX Lower 32-bits of MSR value.
1790 Described by the type MSR_IA32_DEBUGCTL_REGISTER.
1791 @param EDX Upper 32-bits of MSR value.
1792 Described by the type MSR_IA32_DEBUGCTL_REGISTER.
1794 <b>Example usage</b>
1796 MSR_IA32_DEBUGCTL_REGISTER Msr;
1798 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_DEBUGCTL);
1799 AsmWriteMsr64 (MSR_IA32_DEBUGCTL, Msr.Uint64);
1801 @note MSR_IA32_DEBUGCTL is defined as IA32_DEBUGCTL in SDM.
1803 #define MSR_IA32_DEBUGCTL 0x000001D9
1806 MSR information returned for MSR index #MSR_IA32_DEBUGCTL
1810 /// Individual bit fields
1814 /// [Bit 0] LBR: Setting this bit to 1 enables the processor to record a
1815 /// running trace of the most recent branches taken by the processor in
1816 /// the LBR stack. Introduced at Display Family / Display Model 06_01H.
1820 /// [Bit 1] BTF: Setting this bit to 1 enables the processor to treat
1821 /// EFLAGS.TF as single-step on branches instead of single-step on
1822 /// instructions. Introduced at Display Family / Display Model 06_01H.
1827 /// [Bit 6] TR: Setting this bit to 1 enables branch trace messages to be
1828 /// sent. Introduced at Display Family / Display Model 06_0EH.
1832 /// [Bit 7] BTS: Setting this bit enables branch trace messages (BTMs) to
1833 /// be logged in a BTS buffer. Introduced at Display Family / Display
1838 /// [Bit 8] BTINT: When clear, BTMs are logged in a BTS buffer in circular
1839 /// fashion. When this bit is set, an interrupt is generated by the BTS
1840 /// facility when the BTS buffer is full. Introduced at Display Family /
1841 /// Display Model 06_0EH.
1845 /// [Bit 9] BTS_OFF_OS: When set, BTS or BTM is skipped if CPL = 0.
1846 /// Introduced at Display Family / Display Model 06_0FH.
1848 UINT32 BTS_OFF_OS
:1;
1850 /// [Bit 10] BTS_OFF_USR: When set, BTS or BTM is skipped if CPL > 0.
1851 /// Introduced at Display Family / Display Model 06_0FH.
1853 UINT32 BTS_OFF_USR
:1;
1855 /// [Bit 11] FREEZE_LBRS_ON_PMI: When set, the LBR stack is frozen on a
1856 /// PMI request. If CPUID.01H: ECX[15] = 1 && CPUID.0AH: EAX[7:0] > 1.
1858 UINT32 FREEZE_LBRS_ON_PMI
:1;
1860 /// [Bit 12] FREEZE_PERFMON_ON_PMI: When set, each ENABLE bit of the
1861 /// global counter control MSR are frozen (address 38FH) on a PMI request.
1862 /// If CPUID.01H: ECX[15] = 1 && CPUID.0AH: EAX[7:0] > 1.
1864 UINT32 FREEZE_PERFMON_ON_PMI
:1;
1866 /// [Bit 13] ENABLE_UNCORE_PMI: When set, enables the logical processor to
1867 /// receive and generate PMI on behalf of the uncore. Introduced at
1868 /// Display Family / Display Model 06_1AH.
1870 UINT32 ENABLE_UNCORE_PMI
:1;
1872 /// [Bit 14] FREEZE_WHILE_SMM: When set, freezes perfmon and trace
1873 /// messages while in SMM. If IA32_PERF_CAPABILITIES[ 12] = 1.
1875 UINT32 FREEZE_WHILE_SMM
:1;
1877 /// [Bit 15] RTM_DEBUG: When set, enables DR7 debug bit on XBEGIN. If
1878 /// (CPUID.(EAX=07H, ECX=0):EBX[11] = 1).
1881 UINT32 Reserved2
:16;
1882 UINT32 Reserved3
:32;
1885 /// All bit fields as a 32-bit value
1889 /// All bit fields as a 64-bit value
1892 } MSR_IA32_DEBUGCTL_REGISTER
;
1896 SMRR Base Address (Writeable only in SMM) Base address of SMM memory range.
1897 If IA32_MTRRCAP.SMRR[11] = 1.
1899 @param ECX MSR_IA32_SMRR_PHYSBASE (0x000001F2)
1900 @param EAX Lower 32-bits of MSR value.
1901 Described by the type MSR_IA32_SMRR_PHYSBASE_REGISTER.
1902 @param EDX Upper 32-bits of MSR value.
1903 Described by the type MSR_IA32_SMRR_PHYSBASE_REGISTER.
1905 <b>Example usage</b>
1907 MSR_IA32_SMRR_PHYSBASE_REGISTER Msr;
1909 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SMRR_PHYSBASE);
1910 AsmWriteMsr64 (MSR_IA32_SMRR_PHYSBASE, Msr.Uint64);
1912 @note MSR_IA32_SMRR_PHYSBASE is defined as IA32_SMRR_PHYSBASE in SDM.
1914 #define MSR_IA32_SMRR_PHYSBASE 0x000001F2
1917 MSR information returned for MSR index #MSR_IA32_SMRR_PHYSBASE
1921 /// Individual bit fields
1925 /// [Bits 7:0] Type. Specifies memory type of the range.
1930 /// [Bits 31:12] PhysBase. SMRR physical Base Address.
1933 UINT32 Reserved2
:32;
1936 /// All bit fields as a 32-bit value
1940 /// All bit fields as a 64-bit value
1943 } MSR_IA32_SMRR_PHYSBASE_REGISTER
;
1947 SMRR Range Mask (Writeable only in SMM) Range Mask of SMM memory range. If
1948 IA32_MTRRCAP[SMRR] = 1.
1950 @param ECX MSR_IA32_SMRR_PHYSMASK (0x000001F3)
1951 @param EAX Lower 32-bits of MSR value.
1952 Described by the type MSR_IA32_SMRR_PHYSMASK_REGISTER.
1953 @param EDX Upper 32-bits of MSR value.
1954 Described by the type MSR_IA32_SMRR_PHYSMASK_REGISTER.
1956 <b>Example usage</b>
1958 MSR_IA32_SMRR_PHYSMASK_REGISTER Msr;
1960 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SMRR_PHYSMASK);
1961 AsmWriteMsr64 (MSR_IA32_SMRR_PHYSMASK, Msr.Uint64);
1963 @note MSR_IA32_SMRR_PHYSMASK is defined as IA32_SMRR_PHYSMASK in SDM.
1965 #define MSR_IA32_SMRR_PHYSMASK 0x000001F3
1968 MSR information returned for MSR index #MSR_IA32_SMRR_PHYSMASK
1972 /// Individual bit fields
1975 UINT32 Reserved1
:11;
1977 /// [Bit 11] Valid Enable range mask.
1981 /// [Bits 31:12] PhysMask SMRR address range mask.
1984 UINT32 Reserved2
:32;
1987 /// All bit fields as a 32-bit value
1991 /// All bit fields as a 64-bit value
1994 } MSR_IA32_SMRR_PHYSMASK_REGISTER
;
1998 DCA Capability (R). If CPUID.01H: ECX[18] = 1.
2000 @param ECX MSR_IA32_PLATFORM_DCA_CAP (0x000001F8)
2001 @param EAX Lower 32-bits of MSR value.
2002 @param EDX Upper 32-bits of MSR value.
2004 <b>Example usage</b>
2008 Msr = AsmReadMsr64 (MSR_IA32_PLATFORM_DCA_CAP);
2010 @note MSR_IA32_PLATFORM_DCA_CAP is defined as IA32_PLATFORM_DCA_CAP in SDM.
2012 #define MSR_IA32_PLATFORM_DCA_CAP 0x000001F8
2016 If set, CPU supports Prefetch-Hint type. If CPUID.01H: ECX[18] = 1.
2018 @param ECX MSR_IA32_CPU_DCA_CAP (0x000001F9)
2019 @param EAX Lower 32-bits of MSR value.
2020 @param EDX Upper 32-bits of MSR value.
2022 <b>Example usage</b>
2026 Msr = AsmReadMsr64 (MSR_IA32_CPU_DCA_CAP);
2027 AsmWriteMsr64 (MSR_IA32_CPU_DCA_CAP, Msr);
2029 @note MSR_IA32_CPU_DCA_CAP is defined as IA32_CPU_DCA_CAP in SDM.
2031 #define MSR_IA32_CPU_DCA_CAP 0x000001F9
2035 DCA type 0 Status and Control register. If CPUID.01H: ECX[18] = 1.
2037 @param ECX MSR_IA32_DCA_0_CAP (0x000001FA)
2038 @param EAX Lower 32-bits of MSR value.
2039 Described by the type MSR_IA32_DCA_0_CAP_REGISTER.
2040 @param EDX Upper 32-bits of MSR value.
2041 Described by the type MSR_IA32_DCA_0_CAP_REGISTER.
2043 <b>Example usage</b>
2045 MSR_IA32_DCA_0_CAP_REGISTER Msr;
2047 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_DCA_0_CAP);
2048 AsmWriteMsr64 (MSR_IA32_DCA_0_CAP, Msr.Uint64);
2050 @note MSR_IA32_DCA_0_CAP is defined as IA32_DCA_0_CAP in SDM.
2052 #define MSR_IA32_DCA_0_CAP 0x000001FA
2055 MSR information returned for MSR index #MSR_IA32_DCA_0_CAP
2059 /// Individual bit fields
2063 /// [Bit 0] DCA_ACTIVE: Set by HW when DCA is fuseenabled and no
2064 /// defeatures are set.
2066 UINT32 DCA_ACTIVE
:1;
2068 /// [Bits 2:1] TRANSACTION.
2070 UINT32 TRANSACTION
:2;
2072 /// [Bits 6:3] DCA_TYPE.
2076 /// [Bits 10:7] DCA_QUEUE_SIZE.
2078 UINT32 DCA_QUEUE_SIZE
:4;
2081 /// [Bits 16:13] DCA_DELAY: Writes will update the register but have no HW
2087 /// [Bit 24] SW_BLOCK: SW can request DCA block by setting this bit.
2092 /// [Bit 26] HW_BLOCK: Set when DCA is blocked by HW (e.g. CR0.CD = 1).
2096 UINT32 Reserved5
:32;
2099 /// All bit fields as a 32-bit value
2103 /// All bit fields as a 64-bit value
2106 } MSR_IA32_DCA_0_CAP_REGISTER
;
2110 MTRRphysBasen. See Section 11.11.2.3, "Variable Range MTRRs".
2111 If CPUID.01H: EDX.MTRR[12] = 1 and IA32_MTRRCAP[7:0] > n.
2113 @param ECX MSR_IA32_MTRR_PHYSBASEn
2114 @param EAX Lower 32-bits of MSR value.
2115 Described by the type MSR_IA32_MTRR_PHYSBASE_REGISTER.
2116 @param EDX Upper 32-bits of MSR value.
2117 Described by the type MSR_IA32_MTRR_PHYSBASE_REGISTER.
2119 <b>Example usage</b>
2121 MSR_IA32_MTRR_PHYSBASE_REGISTER Msr;
2123 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_PHYSBASE0);
2124 AsmWriteMsr64 (MSR_IA32_MTRR_PHYSBASE0, Msr.Uint64);
2126 @note MSR_IA32_MTRR_PHYSBASE0 is defined as IA32_MTRR_PHYSBASE0 in SDM.
2127 MSR_IA32_MTRR_PHYSBASE1 is defined as IA32_MTRR_PHYSBASE1 in SDM.
2128 MSR_IA32_MTRR_PHYSBASE2 is defined as IA32_MTRR_PHYSBASE2 in SDM.
2129 MSR_IA32_MTRR_PHYSBASE3 is defined as IA32_MTRR_PHYSBASE3 in SDM.
2130 MSR_IA32_MTRR_PHYSBASE4 is defined as IA32_MTRR_PHYSBASE4 in SDM.
2131 MSR_IA32_MTRR_PHYSBASE5 is defined as IA32_MTRR_PHYSBASE5 in SDM.
2132 MSR_IA32_MTRR_PHYSBASE6 is defined as IA32_MTRR_PHYSBASE6 in SDM.
2133 MSR_IA32_MTRR_PHYSBASE7 is defined as IA32_MTRR_PHYSBASE7 in SDM.
2134 MSR_IA32_MTRR_PHYSBASE8 is defined as IA32_MTRR_PHYSBASE8 in SDM.
2135 MSR_IA32_MTRR_PHYSBASE9 is defined as IA32_MTRR_PHYSBASE9 in SDM.
2138 #define MSR_IA32_MTRR_PHYSBASE0 0x00000200
2139 #define MSR_IA32_MTRR_PHYSBASE1 0x00000202
2140 #define MSR_IA32_MTRR_PHYSBASE2 0x00000204
2141 #define MSR_IA32_MTRR_PHYSBASE3 0x00000206
2142 #define MSR_IA32_MTRR_PHYSBASE4 0x00000208
2143 #define MSR_IA32_MTRR_PHYSBASE5 0x0000020A
2144 #define MSR_IA32_MTRR_PHYSBASE6 0x0000020C
2145 #define MSR_IA32_MTRR_PHYSBASE7 0x0000020E
2146 #define MSR_IA32_MTRR_PHYSBASE8 0x00000210
2147 #define MSR_IA32_MTRR_PHYSBASE9 0x00000212
2151 MSR information returned for MSR indexes #MSR_IA32_MTRR_PHYSBASE0 to
2152 #MSR_IA32_MTRR_PHYSBASE9
2156 /// Individual bit fields
2160 /// [Bits 7:0] Type. Specifies memory type of the range.
2165 /// [Bits 31:12] PhysBase. MTRR physical Base Address.
2169 /// [Bits MAXPHYSADDR:32] PhysBase. Upper bits of MTRR physical Base Address.
2170 /// MAXPHYADDR: The bit position indicated by MAXPHYADDR depends on the
2171 /// maximum physical address range supported by the processor. It is
2172 /// reported by CPUID leaf function 80000008H. If CPUID does not support
2173 /// leaf 80000008H, the processor supports 36-bit physical address size,
2174 /// then bit PhysMask consists of bits 35:12, and bits 63:36 are reserved.
2176 UINT32 PhysBaseHi
:32;
2179 /// All bit fields as a 64-bit value
2182 } MSR_IA32_MTRR_PHYSBASE_REGISTER
;
2186 MTRRphysMaskn. See Section 11.11.2.3, "Variable Range MTRRs".
2187 If CPUID.01H: EDX.MTRR[12] = 1 and IA32_MTRRCAP[7:0] > n.
2189 @param ECX MSR_IA32_MTRR_PHYSMASKn
2190 @param EAX Lower 32-bits of MSR value.
2191 Described by the type MSR_IA32_MTRR_PHYSMASK_REGISTER.
2192 @param EDX Upper 32-bits of MSR value.
2193 Described by the type MSR_IA32_MTRR_PHYSMASK_REGISTER.
2195 <b>Example usage</b>
2197 MSR_IA32_MTRR_PHYSMASK_REGISTER Msr;
2199 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_PHYSMASK0);
2200 AsmWriteMsr64 (MSR_IA32_MTRR_PHYSMASK0, Msr.Uint64);
2202 @note MSR_IA32_MTRR_PHYSMASK0 is defined as IA32_MTRR_PHYSMASK0 in SDM.
2203 MSR_IA32_MTRR_PHYSMASK1 is defined as IA32_MTRR_PHYSMASK1 in SDM.
2204 MSR_IA32_MTRR_PHYSMASK2 is defined as IA32_MTRR_PHYSMASK2 in SDM.
2205 MSR_IA32_MTRR_PHYSMASK3 is defined as IA32_MTRR_PHYSMASK3 in SDM.
2206 MSR_IA32_MTRR_PHYSMASK4 is defined as IA32_MTRR_PHYSMASK4 in SDM.
2207 MSR_IA32_MTRR_PHYSMASK5 is defined as IA32_MTRR_PHYSMASK5 in SDM.
2208 MSR_IA32_MTRR_PHYSMASK6 is defined as IA32_MTRR_PHYSMASK6 in SDM.
2209 MSR_IA32_MTRR_PHYSMASK7 is defined as IA32_MTRR_PHYSMASK7 in SDM.
2210 MSR_IA32_MTRR_PHYSMASK8 is defined as IA32_MTRR_PHYSMASK8 in SDM.
2211 MSR_IA32_MTRR_PHYSMASK9 is defined as IA32_MTRR_PHYSMASK9 in SDM.
2214 #define MSR_IA32_MTRR_PHYSMASK0 0x00000201
2215 #define MSR_IA32_MTRR_PHYSMASK1 0x00000203
2216 #define MSR_IA32_MTRR_PHYSMASK2 0x00000205
2217 #define MSR_IA32_MTRR_PHYSMASK3 0x00000207
2218 #define MSR_IA32_MTRR_PHYSMASK4 0x00000209
2219 #define MSR_IA32_MTRR_PHYSMASK5 0x0000020B
2220 #define MSR_IA32_MTRR_PHYSMASK6 0x0000020D
2221 #define MSR_IA32_MTRR_PHYSMASK7 0x0000020F
2222 #define MSR_IA32_MTRR_PHYSMASK8 0x00000211
2223 #define MSR_IA32_MTRR_PHYSMASK9 0x00000213
2227 MSR information returned for MSR indexes #MSR_IA32_MTRR_PHYSMASK0 to
2228 #MSR_IA32_MTRR_PHYSMASK9
2232 /// Individual bit fields
2235 UINT32 Reserved1
:11;
2237 /// [Bit 11] Valid Enable range mask.
2241 /// [Bits 31:12] PhysMask. MTRR address range mask.
2245 /// [Bits MAXPHYSADDR:32] PhysMask. Upper bits of MTRR address range mask.
2246 /// MAXPHYADDR: The bit position indicated by MAXPHYADDR depends on the
2247 /// maximum physical address range supported by the processor. It is
2248 /// reported by CPUID leaf function 80000008H. If CPUID does not support
2249 /// leaf 80000008H, the processor supports 36-bit physical address size,
2250 /// then bit PhysMask consists of bits 35:12, and bits 63:36 are reserved.
2252 UINT32 PhysMaskHi
:32;
2255 /// All bit fields as a 64-bit value
2258 } MSR_IA32_MTRR_PHYSMASK_REGISTER
;
2262 MTRRfix64K_00000. If CPUID.01H: EDX.MTRR[12] =1.
2264 @param ECX MSR_IA32_MTRR_FIX64K_00000 (0x00000250)
2265 @param EAX Lower 32-bits of MSR value.
2266 @param EDX Upper 32-bits of MSR value.
2268 <b>Example usage</b>
2272 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX64K_00000);
2273 AsmWriteMsr64 (MSR_IA32_MTRR_FIX64K_00000, Msr);
2275 @note MSR_IA32_MTRR_FIX64K_00000 is defined as IA32_MTRR_FIX64K_00000 in SDM.
2277 #define MSR_IA32_MTRR_FIX64K_00000 0x00000250
2281 MTRRfix16K_80000. If CPUID.01H: EDX.MTRR[12] =1.
2283 @param ECX MSR_IA32_MTRR_FIX16K_80000 (0x00000258)
2284 @param EAX Lower 32-bits of MSR value.
2285 @param EDX Upper 32-bits of MSR value.
2287 <b>Example usage</b>
2291 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX16K_80000);
2292 AsmWriteMsr64 (MSR_IA32_MTRR_FIX16K_80000, Msr);
2294 @note MSR_IA32_MTRR_FIX16K_80000 is defined as IA32_MTRR_FIX16K_80000 in SDM.
2296 #define MSR_IA32_MTRR_FIX16K_80000 0x00000258
2300 MTRRfix16K_A0000. If CPUID.01H: EDX.MTRR[12] =1.
2302 @param ECX MSR_IA32_MTRR_FIX16K_A0000 (0x00000259)
2303 @param EAX Lower 32-bits of MSR value.
2304 @param EDX Upper 32-bits of MSR value.
2306 <b>Example usage</b>
2310 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX16K_A0000);
2311 AsmWriteMsr64 (MSR_IA32_MTRR_FIX16K_A0000, Msr);
2313 @note MSR_IA32_MTRR_FIX16K_A0000 is defined as IA32_MTRR_FIX16K_A0000 in SDM.
2315 #define MSR_IA32_MTRR_FIX16K_A0000 0x00000259
2319 See Section 11.11.2.2, "Fixed Range MTRRs.". If CPUID.01H: EDX.MTRR[12] =1.
2321 @param ECX MSR_IA32_MTRR_FIX4K_C0000 (0x00000268)
2322 @param EAX Lower 32-bits of MSR value.
2323 @param EDX Upper 32-bits of MSR value.
2325 <b>Example usage</b>
2329 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_C0000);
2330 AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_C0000, Msr);
2332 @note MSR_IA32_MTRR_FIX4K_C0000 is defined as IA32_MTRR_FIX4K_C0000 in SDM.
2334 #define MSR_IA32_MTRR_FIX4K_C0000 0x00000268
2338 MTRRfix4K_C8000. If CPUID.01H: EDX.MTRR[12] =1.
2340 @param ECX MSR_IA32_MTRR_FIX4K_C8000 (0x00000269)
2341 @param EAX Lower 32-bits of MSR value.
2342 @param EDX Upper 32-bits of MSR value.
2344 <b>Example usage</b>
2348 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_C8000);
2349 AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_C8000, Msr);
2351 @note MSR_IA32_MTRR_FIX4K_C8000 is defined as IA32_MTRR_FIX4K_C8000 in SDM.
2353 #define MSR_IA32_MTRR_FIX4K_C8000 0x00000269
2357 MTRRfix4K_D0000. If CPUID.01H: EDX.MTRR[12] =1.
2359 @param ECX MSR_IA32_MTRR_FIX4K_D0000 (0x0000026A)
2360 @param EAX Lower 32-bits of MSR value.
2361 @param EDX Upper 32-bits of MSR value.
2363 <b>Example usage</b>
2367 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_D0000);
2368 AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_D0000, Msr);
2370 @note MSR_IA32_MTRR_FIX4K_D0000 is defined as IA32_MTRR_FIX4K_D0000 in SDM.
2372 #define MSR_IA32_MTRR_FIX4K_D0000 0x0000026A
2376 MTRRfix4K_D8000. If CPUID.01H: EDX.MTRR[12] =1.
2378 @param ECX MSR_IA32_MTRR_FIX4K_D8000 (0x0000026B)
2379 @param EAX Lower 32-bits of MSR value.
2380 @param EDX Upper 32-bits of MSR value.
2382 <b>Example usage</b>
2386 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_D8000);
2387 AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_D8000, Msr);
2389 @note MSR_IA32_MTRR_FIX4K_D8000 is defined as IA32_MTRR_FIX4K_D8000 in SDM.
2391 #define MSR_IA32_MTRR_FIX4K_D8000 0x0000026B
2395 MTRRfix4K_E0000. If CPUID.01H: EDX.MTRR[12] =1.
2397 @param ECX MSR_IA32_MTRR_FIX4K_E0000 (0x0000026C)
2398 @param EAX Lower 32-bits of MSR value.
2399 @param EDX Upper 32-bits of MSR value.
2401 <b>Example usage</b>
2405 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_E0000);
2406 AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_E0000, Msr);
2408 @note MSR_IA32_MTRR_FIX4K_E0000 is defined as IA32_MTRR_FIX4K_E0000 in SDM.
2410 #define MSR_IA32_MTRR_FIX4K_E0000 0x0000026C
2414 MTRRfix4K_E8000. If CPUID.01H: EDX.MTRR[12] =1.
2416 @param ECX MSR_IA32_MTRR_FIX4K_E8000 (0x0000026D)
2417 @param EAX Lower 32-bits of MSR value.
2418 @param EDX Upper 32-bits of MSR value.
2420 <b>Example usage</b>
2424 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_E8000);
2425 AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_E8000, Msr);
2427 @note MSR_IA32_MTRR_FIX4K_E8000 is defined as IA32_MTRR_FIX4K_E8000 in SDM.
2429 #define MSR_IA32_MTRR_FIX4K_E8000 0x0000026D
2433 MTRRfix4K_F0000. If CPUID.01H: EDX.MTRR[12] =1.
2435 @param ECX MSR_IA32_MTRR_FIX4K_F0000 (0x0000026E)
2436 @param EAX Lower 32-bits of MSR value.
2437 @param EDX Upper 32-bits of MSR value.
2439 <b>Example usage</b>
2443 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_F0000);
2444 AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_F0000, Msr);
2446 @note MSR_IA32_MTRR_FIX4K_F0000 is defined as IA32_MTRR_FIX4K_F0000 in SDM.
2448 #define MSR_IA32_MTRR_FIX4K_F0000 0x0000026E
2452 MTRRfix4K_F8000. If CPUID.01H: EDX.MTRR[12] =1.
2454 @param ECX MSR_IA32_MTRR_FIX4K_F8000 (0x0000026F)
2455 @param EAX Lower 32-bits of MSR value.
2456 @param EDX Upper 32-bits of MSR value.
2458 <b>Example usage</b>
2462 Msr = AsmReadMsr64 (MSR_IA32_MTRR_FIX4K_F8000);
2463 AsmWriteMsr64 (MSR_IA32_MTRR_FIX4K_F8000, Msr);
2465 @note MSR_IA32_MTRR_FIX4K_F8000 is defined as IA32_MTRR_FIX4K_F8000 in SDM.
2467 #define MSR_IA32_MTRR_FIX4K_F8000 0x0000026F
2471 IA32_PAT (R/W). If CPUID.01H: EDX.MTRR[16] =1.
2473 @param ECX MSR_IA32_PAT (0x00000277)
2474 @param EAX Lower 32-bits of MSR value.
2475 Described by the type MSR_IA32_PAT_REGISTER.
2476 @param EDX Upper 32-bits of MSR value.
2477 Described by the type MSR_IA32_PAT_REGISTER.
2479 <b>Example usage</b>
2481 MSR_IA32_PAT_REGISTER Msr;
2483 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PAT);
2484 AsmWriteMsr64 (MSR_IA32_PAT, Msr.Uint64);
2486 @note MSR_IA32_PAT is defined as IA32_PAT in SDM.
2488 #define MSR_IA32_PAT 0x00000277
2491 MSR information returned for MSR index #MSR_IA32_PAT
2495 /// Individual bit fields
2504 /// [Bits 10:8] PA1.
2509 /// [Bits 18:16] PA2.
2514 /// [Bits 26:24] PA3.
2519 /// [Bits 34:32] PA4.
2524 /// [Bits 42:40] PA5.
2529 /// [Bits 50:48] PA6.
2534 /// [Bits 58:56] PA7.
2540 /// All bit fields as a 64-bit value
2543 } MSR_IA32_PAT_REGISTER
;
2547 Provides the programming interface to use corrected MC error signaling
2548 capability (R/W). If IA32_MCG_CAP[10] = 1 && IA32_MCG_CAP[7:0] > n.
2550 @param ECX MSR_IA32_MCn_CTL2
2551 @param EAX Lower 32-bits of MSR value.
2552 Described by the type MSR_IA32_MC_CTL2_REGISTER.
2553 @param EDX Upper 32-bits of MSR value.
2554 Described by the type MSR_IA32_MC_CTL2_REGISTER.
2556 <b>Example usage</b>
2558 MSR_IA32_MC_CTL2_REGISTER Msr;
2560 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MC0_CTL2);
2561 AsmWriteMsr64 (MSR_IA32_MC0_CTL2, Msr.Uint64);
2563 @note MSR_IA32_MC0_CTL2 is defined as IA32_MC0_CTL2 in SDM.
2564 MSR_IA32_MC1_CTL2 is defined as IA32_MC1_CTL2 in SDM.
2565 MSR_IA32_MC2_CTL2 is defined as IA32_MC2_CTL2 in SDM.
2566 MSR_IA32_MC3_CTL2 is defined as IA32_MC3_CTL2 in SDM.
2567 MSR_IA32_MC4_CTL2 is defined as IA32_MC4_CTL2 in SDM.
2568 MSR_IA32_MC5_CTL2 is defined as IA32_MC5_CTL2 in SDM.
2569 MSR_IA32_MC6_CTL2 is defined as IA32_MC6_CTL2 in SDM.
2570 MSR_IA32_MC7_CTL2 is defined as IA32_MC7_CTL2 in SDM.
2571 MSR_IA32_MC8_CTL2 is defined as IA32_MC8_CTL2 in SDM.
2572 MSR_IA32_MC9_CTL2 is defined as IA32_MC9_CTL2 in SDM.
2573 MSR_IA32_MC10_CTL2 is defined as IA32_MC10_CTL2 in SDM.
2574 MSR_IA32_MC11_CTL2 is defined as IA32_MC11_CTL2 in SDM.
2575 MSR_IA32_MC12_CTL2 is defined as IA32_MC12_CTL2 in SDM.
2576 MSR_IA32_MC13_CTL2 is defined as IA32_MC13_CTL2 in SDM.
2577 MSR_IA32_MC14_CTL2 is defined as IA32_MC14_CTL2 in SDM.
2578 MSR_IA32_MC15_CTL2 is defined as IA32_MC15_CTL2 in SDM.
2579 MSR_IA32_MC16_CTL2 is defined as IA32_MC16_CTL2 in SDM.
2580 MSR_IA32_MC17_CTL2 is defined as IA32_MC17_CTL2 in SDM.
2581 MSR_IA32_MC18_CTL2 is defined as IA32_MC18_CTL2 in SDM.
2582 MSR_IA32_MC19_CTL2 is defined as IA32_MC19_CTL2 in SDM.
2583 MSR_IA32_MC20_CTL2 is defined as IA32_MC20_CTL2 in SDM.
2584 MSR_IA32_MC21_CTL2 is defined as IA32_MC21_CTL2 in SDM.
2585 MSR_IA32_MC22_CTL2 is defined as IA32_MC22_CTL2 in SDM.
2586 MSR_IA32_MC23_CTL2 is defined as IA32_MC23_CTL2 in SDM.
2587 MSR_IA32_MC24_CTL2 is defined as IA32_MC24_CTL2 in SDM.
2588 MSR_IA32_MC25_CTL2 is defined as IA32_MC25_CTL2 in SDM.
2589 MSR_IA32_MC26_CTL2 is defined as IA32_MC26_CTL2 in SDM.
2590 MSR_IA32_MC27_CTL2 is defined as IA32_MC27_CTL2 in SDM.
2591 MSR_IA32_MC28_CTL2 is defined as IA32_MC28_CTL2 in SDM.
2592 MSR_IA32_MC29_CTL2 is defined as IA32_MC29_CTL2 in SDM.
2593 MSR_IA32_MC30_CTL2 is defined as IA32_MC30_CTL2 in SDM.
2594 MSR_IA32_MC31_CTL2 is defined as IA32_MC31_CTL2 in SDM.
2597 #define MSR_IA32_MC0_CTL2 0x00000280
2598 #define MSR_IA32_MC1_CTL2 0x00000281
2599 #define MSR_IA32_MC2_CTL2 0x00000282
2600 #define MSR_IA32_MC3_CTL2 0x00000283
2601 #define MSR_IA32_MC4_CTL2 0x00000284
2602 #define MSR_IA32_MC5_CTL2 0x00000285
2603 #define MSR_IA32_MC6_CTL2 0x00000286
2604 #define MSR_IA32_MC7_CTL2 0x00000287
2605 #define MSR_IA32_MC8_CTL2 0x00000288
2606 #define MSR_IA32_MC9_CTL2 0x00000289
2607 #define MSR_IA32_MC10_CTL2 0x0000028A
2608 #define MSR_IA32_MC11_CTL2 0x0000028B
2609 #define MSR_IA32_MC12_CTL2 0x0000028C
2610 #define MSR_IA32_MC13_CTL2 0x0000028D
2611 #define MSR_IA32_MC14_CTL2 0x0000028E
2612 #define MSR_IA32_MC15_CTL2 0x0000028F
2613 #define MSR_IA32_MC16_CTL2 0x00000290
2614 #define MSR_IA32_MC17_CTL2 0x00000291
2615 #define MSR_IA32_MC18_CTL2 0x00000292
2616 #define MSR_IA32_MC19_CTL2 0x00000293
2617 #define MSR_IA32_MC20_CTL2 0x00000294
2618 #define MSR_IA32_MC21_CTL2 0x00000295
2619 #define MSR_IA32_MC22_CTL2 0x00000296
2620 #define MSR_IA32_MC23_CTL2 0x00000297
2621 #define MSR_IA32_MC24_CTL2 0x00000298
2622 #define MSR_IA32_MC25_CTL2 0x00000299
2623 #define MSR_IA32_MC26_CTL2 0x0000029A
2624 #define MSR_IA32_MC27_CTL2 0x0000029B
2625 #define MSR_IA32_MC28_CTL2 0x0000029C
2626 #define MSR_IA32_MC29_CTL2 0x0000029D
2627 #define MSR_IA32_MC30_CTL2 0x0000029E
2628 #define MSR_IA32_MC31_CTL2 0x0000029F
2632 MSR information returned for MSR indexes #MSR_IA32_MC0_CTL2
2633 to #MSR_IA32_MC31_CTL2
2637 /// Individual bit fields
2641 /// [Bits 14:0] Corrected error count threshold.
2643 UINT32 CorrectedErrorCountThreshold
:15;
2644 UINT32 Reserved1
:15;
2646 /// [Bit 30] CMCI_EN.
2650 UINT32 Reserved3
:32;
2653 /// All bit fields as a 32-bit value
2657 /// All bit fields as a 64-bit value
2660 } MSR_IA32_MC_CTL2_REGISTER
;
2664 MTRRdefType (R/W). If CPUID.01H: EDX.MTRR[12] =1.
2666 @param ECX MSR_IA32_MTRR_DEF_TYPE (0x000002FF)
2667 @param EAX Lower 32-bits of MSR value.
2668 Described by the type MSR_IA32_MTRR_DEF_TYPE_REGISTER.
2669 @param EDX Upper 32-bits of MSR value.
2670 Described by the type MSR_IA32_MTRR_DEF_TYPE_REGISTER.
2672 <b>Example usage</b>
2674 MSR_IA32_MTRR_DEF_TYPE_REGISTER Msr;
2676 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MTRR_DEF_TYPE);
2677 AsmWriteMsr64 (MSR_IA32_MTRR_DEF_TYPE, Msr.Uint64);
2679 @note MSR_IA32_MTRR_DEF_TYPE is defined as IA32_MTRR_DEF_TYPE in SDM.
2681 #define MSR_IA32_MTRR_DEF_TYPE 0x000002FF
2684 MSR information returned for MSR index #MSR_IA32_MTRR_DEF_TYPE
2688 /// Individual bit fields
2692 /// [Bits 2:0] Default Memory Type.
2697 /// [Bit 10] Fixed Range MTRR Enable.
2701 /// [Bit 11] MTRR Enable.
2704 UINT32 Reserved2
:20;
2705 UINT32 Reserved3
:32;
2708 /// All bit fields as a 32-bit value
2712 /// All bit fields as a 64-bit value
2715 } MSR_IA32_MTRR_DEF_TYPE_REGISTER
;
2719 Fixed-Function Performance Counter 0 (R/W): Counts Instr_Retired.Any. If
2720 CPUID.0AH: EDX[4:0] > 0.
2722 @param ECX MSR_IA32_FIXED_CTR0 (0x00000309)
2723 @param EAX Lower 32-bits of MSR value.
2724 @param EDX Upper 32-bits of MSR value.
2726 <b>Example usage</b>
2730 Msr = AsmReadMsr64 (MSR_IA32_FIXED_CTR0);
2731 AsmWriteMsr64 (MSR_IA32_FIXED_CTR0, Msr);
2733 @note MSR_IA32_FIXED_CTR0 is defined as IA32_FIXED_CTR0 in SDM.
2735 #define MSR_IA32_FIXED_CTR0 0x00000309
2739 Fixed-Function Performance Counter 1 (R/W): Counts CPU_CLK_Unhalted.Core. If
2740 CPUID.0AH: EDX[4:0] > 1.
2742 @param ECX MSR_IA32_FIXED_CTR1 (0x0000030A)
2743 @param EAX Lower 32-bits of MSR value.
2744 @param EDX Upper 32-bits of MSR value.
2746 <b>Example usage</b>
2750 Msr = AsmReadMsr64 (MSR_IA32_FIXED_CTR1);
2751 AsmWriteMsr64 (MSR_IA32_FIXED_CTR1, Msr);
2753 @note MSR_IA32_FIXED_CTR1 is defined as IA32_FIXED_CTR1 in SDM.
2755 #define MSR_IA32_FIXED_CTR1 0x0000030A
2759 Fixed-Function Performance Counter 2 (R/W): Counts CPU_CLK_Unhalted.Ref. If
2760 CPUID.0AH: EDX[4:0] > 2.
2762 @param ECX MSR_IA32_FIXED_CTR2 (0x0000030B)
2763 @param EAX Lower 32-bits of MSR value.
2764 @param EDX Upper 32-bits of MSR value.
2766 <b>Example usage</b>
2770 Msr = AsmReadMsr64 (MSR_IA32_FIXED_CTR2);
2771 AsmWriteMsr64 (MSR_IA32_FIXED_CTR2, Msr);
2773 @note MSR_IA32_FIXED_CTR2 is defined as IA32_FIXED_CTR2 in SDM.
2775 #define MSR_IA32_FIXED_CTR2 0x0000030B
2779 RO. If CPUID.01H: ECX[15] = 1.
2781 @param ECX MSR_IA32_PERF_CAPABILITIES (0x00000345)
2782 @param EAX Lower 32-bits of MSR value.
2783 Described by the type MSR_IA32_PERF_CAPABILITIES_REGISTER.
2784 @param EDX Upper 32-bits of MSR value.
2785 Described by the type MSR_IA32_PERF_CAPABILITIES_REGISTER.
2787 <b>Example usage</b>
2789 MSR_IA32_PERF_CAPABILITIES_REGISTER Msr;
2791 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_CAPABILITIES);
2792 AsmWriteMsr64 (MSR_IA32_PERF_CAPABILITIES, Msr.Uint64);
2794 @note MSR_IA32_PERF_CAPABILITIES is defined as IA32_PERF_CAPABILITIES in SDM.
2796 #define MSR_IA32_PERF_CAPABILITIES 0x00000345
2799 MSR information returned for MSR index #MSR_IA32_PERF_CAPABILITIES
2803 /// Individual bit fields
2807 /// [Bits 5:0] LBR format.
2811 /// [Bit 6] PEBS Trap.
2815 /// [Bit 7] PEBSSaveArchRegs.
2817 UINT32 PEBS_ARCH_REG
:1;
2819 /// [Bits 11:8] PEBS Record Format.
2821 UINT32 PEBS_REC_FMT
:4;
2823 /// [Bit 12] 1: Freeze while SMM is supported.
2825 UINT32 SMM_FREEZE
:1;
2827 /// [Bit 13] 1: Full width of counter writable via IA32_A_PMCx.
2830 UINT32 Reserved1
:18;
2831 UINT32 Reserved2
:32;
2834 /// All bit fields as a 32-bit value
2838 /// All bit fields as a 64-bit value
2841 } MSR_IA32_PERF_CAPABILITIES_REGISTER
;
2845 Fixed-Function Performance Counter Control (R/W) Counter increments while
2846 the results of ANDing respective enable bit in IA32_PERF_GLOBAL_CTRL with
2847 the corresponding OS or USR bits in this MSR is true. If CPUID.0AH: EAX[7:0]
2850 @param ECX MSR_IA32_FIXED_CTR_CTRL (0x0000038D)
2851 @param EAX Lower 32-bits of MSR value.
2852 Described by the type MSR_IA32_FIXED_CTR_CTRL_REGISTER.
2853 @param EDX Upper 32-bits of MSR value.
2854 Described by the type MSR_IA32_FIXED_CTR_CTRL_REGISTER.
2856 <b>Example usage</b>
2858 MSR_IA32_FIXED_CTR_CTRL_REGISTER Msr;
2860 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_FIXED_CTR_CTRL);
2861 AsmWriteMsr64 (MSR_IA32_FIXED_CTR_CTRL, Msr.Uint64);
2863 @note MSR_IA32_FIXED_CTR_CTRL is defined as IA32_FIXED_CTR_CTRL in SDM.
2865 #define MSR_IA32_FIXED_CTR_CTRL 0x0000038D
2868 MSR information returned for MSR index #MSR_IA32_FIXED_CTR_CTRL
2872 /// Individual bit fields
2876 /// [Bit 0] EN0_OS: Enable Fixed Counter 0 to count while CPL = 0.
2880 /// [Bit 1] EN0_Usr: Enable Fixed Counter 0 to count while CPL > 0.
2884 /// [Bit 2] AnyThread: When set to 1, it enables counting the associated
2885 /// event conditions occurring across all logical processors sharing a
2886 /// processor core. When set to 0, the counter only increments the
2887 /// associated event conditions occurring in the logical processor which
2888 /// programmed the MSR. If CPUID.0AH: EAX[7:0] > 2.
2890 UINT32 AnyThread0
:1;
2892 /// [Bit 3] EN0_PMI: Enable PMI when fixed counter 0 overflows.
2896 /// [Bit 4] EN1_OS: Enable Fixed Counter 1 to count while CPL = 0.
2900 /// [Bit 5] EN1_Usr: Enable Fixed Counter 1 to count while CPL > 0.
2904 /// [Bit 6] AnyThread: When set to 1, it enables counting the associated
2905 /// event conditions occurring across all logical processors sharing a
2906 /// processor core. When set to 0, the counter only increments the
2907 /// associated event conditions occurring in the logical processor which
2908 /// programmed the MSR. If CPUID.0AH: EAX[7:0] > 2.
2910 UINT32 AnyThread1
:1;
2912 /// [Bit 7] EN1_PMI: Enable PMI when fixed counter 1 overflows.
2916 /// [Bit 8] EN2_OS: Enable Fixed Counter 2 to count while CPL = 0.
2920 /// [Bit 9] EN2_Usr: Enable Fixed Counter 2 to count while CPL > 0.
2924 /// [Bit 10] AnyThread: When set to 1, it enables counting the associated
2925 /// event conditions occurring across all logical processors sharing a
2926 /// processor core. When set to 0, the counter only increments the
2927 /// associated event conditions occurring in the logical processor which
2928 /// programmed the MSR. If CPUID.0AH: EAX[7:0] > 2.
2930 UINT32 AnyThread2
:1;
2932 /// [Bit 11] EN2_PMI: Enable PMI when fixed counter 2 overflows.
2935 UINT32 Reserved1
:20;
2936 UINT32 Reserved2
:32;
2939 /// All bit fields as a 32-bit value
2943 /// All bit fields as a 64-bit value
2946 } MSR_IA32_FIXED_CTR_CTRL_REGISTER
;
2950 Global Performance Counter Status (RO). If CPUID.0AH: EAX[7:0] > 0.
2952 @param ECX MSR_IA32_PERF_GLOBAL_STATUS (0x0000038E)
2953 @param EAX Lower 32-bits of MSR value.
2954 Described by the type MSR_IA32_PERF_GLOBAL_STATUS_REGISTER.
2955 @param EDX Upper 32-bits of MSR value.
2956 Described by the type MSR_IA32_PERF_GLOBAL_STATUS_REGISTER.
2958 <b>Example usage</b>
2960 MSR_IA32_PERF_GLOBAL_STATUS_REGISTER Msr;
2962 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_STATUS);
2964 @note MSR_IA32_PERF_GLOBAL_STATUS is defined as IA32_PERF_GLOBAL_STATUS in SDM.
2966 #define MSR_IA32_PERF_GLOBAL_STATUS 0x0000038E
2969 MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_STATUS
2973 /// Individual bit fields
2977 /// [Bit 0] Ovf_PMC0: Overflow status of IA32_PMC0. If CPUID.0AH:
2982 /// [Bit 1] Ovf_PMC1: Overflow status of IA32_PMC1. If CPUID.0AH:
2987 /// [Bit 2] Ovf_PMC2: Overflow status of IA32_PMC2. If CPUID.0AH:
2992 /// [Bit 3] Ovf_PMC3: Overflow status of IA32_PMC3. If CPUID.0AH:
2996 UINT32 Reserved1
:28;
2998 /// [Bit 32] Ovf_FixedCtr0: Overflow status of IA32_FIXED_CTR0. If
2999 /// CPUID.0AH: EAX[7:0] > 1.
3001 UINT32 Ovf_FixedCtr0
:1;
3003 /// [Bit 33] Ovf_FixedCtr1: Overflow status of IA32_FIXED_CTR1. If
3004 /// CPUID.0AH: EAX[7:0] > 1.
3006 UINT32 Ovf_FixedCtr1
:1;
3008 /// [Bit 34] Ovf_FixedCtr2: Overflow status of IA32_FIXED_CTR2. If
3009 /// CPUID.0AH: EAX[7:0] > 1.
3011 UINT32 Ovf_FixedCtr2
:1;
3012 UINT32 Reserved2
:20;
3014 /// [Bit 55] Trace_ToPA_PMI: A PMI occurred due to a ToPA entry memory
3015 /// buffer was completely filled. If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1)
3016 /// && IA32_RTIT_CTL.ToPA = 1.
3018 UINT32 Trace_ToPA_PMI
:1;
3021 /// [Bit 58] LBR_Frz: LBRs are frozen due to -
3022 /// IA32_DEBUGCTL.FREEZE_LBR_ON_PMI=1, - The LBR stack overflowed. If
3023 /// CPUID.0AH: EAX[7:0] > 3.
3027 /// [Bit 59] CTR_Frz: Performance counters in the core PMU are frozen due
3028 /// to - IA32_DEBUGCTL.FREEZE_PERFMON_ON_ PMI=1, - one or more core PMU
3029 /// counters overflowed. If CPUID.0AH: EAX[7:0] > 3.
3033 /// [Bit 60] ASCI: Data in the performance counters in the core PMU may
3034 /// include contributions from the direct or indirect operation intel SGX
3035 /// to protect an enclave. If CPUID.(EAX=07H, ECX=0):EBX[2] = 1.
3039 /// [Bit 61] Ovf_Uncore: Uncore counter overflow status. If CPUID.0AH:
3042 UINT32 Ovf_Uncore
:1;
3044 /// [Bit 62] OvfBuf: DS SAVE area Buffer overflow status. If CPUID.0AH:
3049 /// [Bit 63] CondChgd: status bits of this register has changed. If
3050 /// CPUID.0AH: EAX[7:0] > 0.
3055 /// All bit fields as a 64-bit value
3058 } MSR_IA32_PERF_GLOBAL_STATUS_REGISTER
;
3062 Global Performance Counter Control (R/W) Counter increments while the result
3063 of ANDing respective enable bit in this MSR with the corresponding OS or USR
3064 bits in the general-purpose or fixed counter control MSR is true. If
3065 CPUID.0AH: EAX[7:0] > 0.
3067 @param ECX MSR_IA32_PERF_GLOBAL_CTRL (0x0000038F)
3068 @param EAX Lower 32-bits of MSR value.
3069 Described by the type MSR_IA32_PERF_GLOBAL_CTRL_REGISTER.
3070 @param EDX Upper 32-bits of MSR value.
3071 Described by the type MSR_IA32_PERF_GLOBAL_CTRL_REGISTER.
3073 <b>Example usage</b>
3075 MSR_IA32_PERF_GLOBAL_CTRL_REGISTER Msr;
3077 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_CTRL);
3078 AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_CTRL, Msr.Uint64);
3080 @note MSR_IA32_PERF_GLOBAL_CTRL is defined as IA32_PERF_GLOBAL_CTRL in SDM.
3082 #define MSR_IA32_PERF_GLOBAL_CTRL 0x0000038F
3085 MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_CTRL
3089 /// Individual bit fields
3093 /// [Bits 31:0] EN_PMCn. If CPUID.0AH: EAX[15:8] > n.
3094 /// Enable bitmask. Only the first n-1 bits are valid.
3095 /// Bits n..31 are reserved.
3099 /// [Bits 63:32] EN_FIXED_CTRn. If CPUID.0AH: EDX[4:0] > n.
3100 /// Enable bitmask. Only the first n-1 bits are valid.
3101 /// Bits 31:n are reserved.
3103 UINT32 EN_FIXED_CTRn
:32;
3106 /// All bit fields as a 64-bit value
3109 } MSR_IA32_PERF_GLOBAL_CTRL_REGISTER
;
3113 Global Performance Counter Overflow Control (R/W). If CPUID.0AH: EAX[7:0] >
3114 0 && CPUID.0AH: EAX[7:0] <= 3.
3116 @param ECX MSR_IA32_PERF_GLOBAL_OVF_CTRL (0x00000390)
3117 @param EAX Lower 32-bits of MSR value.
3118 Described by the type MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER.
3119 @param EDX Upper 32-bits of MSR value.
3120 Described by the type MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER.
3122 <b>Example usage</b>
3124 MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER Msr;
3126 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_OVF_CTRL);
3127 AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_OVF_CTRL, Msr.Uint64);
3129 @note MSR_IA32_PERF_GLOBAL_OVF_CTRL is defined as IA32_PERF_GLOBAL_OVF_CTRL in SDM.
3131 #define MSR_IA32_PERF_GLOBAL_OVF_CTRL 0x00000390
3134 MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_OVF_CTRL
3138 /// Individual bit fields
3142 /// [Bits 31:0] Set 1 to Clear Ovf_PMC0 bit. If CPUID.0AH: EAX[15:8] > n.
3143 /// Clear bitmask. Only the first n-1 bits are valid.
3144 /// Bits 31:n are reserved.
3148 /// [Bits 54:32] Set 1 to Clear Ovf_FIXED_CTR0 bit.
3149 /// If CPUID.0AH: EDX[4:0] > n.
3150 /// Clear bitmask. Only the first n-1 bits are valid.
3151 /// Bits 22:n are reserved.
3153 UINT32 Ovf_FIXED_CTRn
:23;
3155 /// [Bit 55] Set 1 to Clear Trace_ToPA_PMI bit. If (CPUID.(EAX=07H,
3156 /// ECX=0):EBX[25] = 1) && IA32_RTIT_CTL.ToPA = 1.
3158 UINT32 Trace_ToPA_PMI
:1;
3161 /// [Bit 61] Set 1 to Clear Ovf_Uncore bit. Introduced at Display Family /
3162 /// Display Model 06_2EH.
3164 UINT32 Ovf_Uncore
:1;
3166 /// [Bit 62] Set 1 to Clear OvfBuf: bit. If CPUID.0AH: EAX[7:0] > 0.
3170 /// [Bit 63] Set to 1to clear CondChgd: bit. If CPUID.0AH: EAX[7:0] > 0.
3175 /// All bit fields as a 64-bit value
3178 } MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER
;
3182 Global Performance Counter Overflow Reset Control (R/W). If CPUID.0AH:
3185 @param ECX MSR_IA32_PERF_GLOBAL_STATUS_RESET (0x00000390)
3186 @param EAX Lower 32-bits of MSR value.
3187 Described by the type MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER.
3188 @param EDX Upper 32-bits of MSR value.
3189 Described by the type MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER.
3191 <b>Example usage</b>
3193 MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER Msr;
3195 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_RESET);
3196 AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_RESET, Msr.Uint64);
3198 @note MSR_IA32_PERF_GLOBAL_STATUS_RESET is defined as IA32_PERF_GLOBAL_STATUS_RESET in SDM.
3200 #define MSR_IA32_PERF_GLOBAL_STATUS_RESET 0x00000390
3203 MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_STATUS_RESET
3207 /// Individual bit fields
3211 /// [Bits 31:0] Set 1 to Clear Ovf_PMC0 bit. If CPUID.0AH: EAX[15:8] > n.
3212 /// Clear bitmask. Only the first n-1 bits are valid.
3213 /// Bits 31:n are reserved.
3217 /// [Bits 54:32] Set 1 to Clear Ovf_FIXED_CTR0 bit.
3218 /// If CPUID.0AH: EDX[4:0] > n.
3219 /// Clear bitmask. Only the first n-1 bits are valid.
3220 /// Bits 22:n are reserved.
3222 UINT32 Ovf_FIXED_CTRn
:23;
3224 /// [Bit 55] Set 1 to Clear Trace_ToPA_PMI bit. If (CPUID.(EAX=07H,
3225 /// ECX=0):EBX[25] = 1) && IA32_RTIT_CTL.ToPA[8] = 1.
3227 UINT32 Trace_ToPA_PMI
:1;
3230 /// [Bit 58] Set 1 to Clear LBR_Frz bit. If CPUID.0AH: EAX[7:0] > 3.
3234 /// [Bit 59] Set 1 to Clear CTR_Frz bit. If CPUID.0AH: EAX[7:0] > 3.
3238 /// [Bit 60] Set 1 to Clear ASCI bit. If CPUID.0AH: EAX[7:0] > 3.
3242 /// [Bit 61] Set 1 to Clear Ovf_Uncore bit. Introduced at Display Family /
3243 /// Display Model 06_2EH.
3245 UINT32 Ovf_Uncore
:1;
3247 /// [Bit 62] Set 1 to Clear OvfBuf: bit. If CPUID.0AH: EAX[7:0] > 0.
3251 /// [Bit 63] Set to 1to clear CondChgd: bit. If CPUID.0AH: EAX[7:0] > 0.
3256 /// All bit fields as a 64-bit value
3259 } MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER
;
3263 Global Performance Counter Overflow Set Control (R/W). If CPUID.0AH:
3266 @param ECX MSR_IA32_PERF_GLOBAL_STATUS_SET (0x00000391)
3267 @param EAX Lower 32-bits of MSR value.
3268 Described by the type MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER.
3269 @param EDX Upper 32-bits of MSR value.
3270 Described by the type MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER.
3272 <b>Example usage</b>
3274 MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER Msr;
3276 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_SET);
3277 AsmWriteMsr64 (MSR_IA32_PERF_GLOBAL_STATUS_SET, Msr.Uint64);
3279 @note MSR_IA32_PERF_GLOBAL_STATUS_SET is defined as IA32_PERF_GLOBAL_STATUS_SET in SDM.
3281 #define MSR_IA32_PERF_GLOBAL_STATUS_SET 0x00000391
3284 MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_STATUS_SET
3288 /// Individual bit fields
3292 /// [Bits 31:0] Set 1 to cause Ovf_PMCn = 1. If CPUID.0AH: EAX[7:0] > n.
3293 /// Set bitmask. Only the first n-1 bits are valid.
3294 /// Bits 31:n are reserved.
3298 /// [Bits 54:32] Set 1 to cause Ovf_FIXED_CTRn = 1.
3299 /// If CPUID.0AH: EAX[7:0] > n.
3300 /// Set bitmask. Only the first n-1 bits are valid.
3301 /// Bits 22:n are reserved.
3303 UINT32 Ovf_FIXED_CTRn
:23;
3305 /// [Bit 55] Set 1 to cause Trace_ToPA_PMI = 1. If CPUID.0AH: EAX[7:0] > 3.
3307 UINT32 Trace_ToPA_PMI
:1;
3310 /// [Bit 58] Set 1 to cause LBR_Frz = 1. If CPUID.0AH: EAX[7:0] > 3.
3314 /// [Bit 59] Set 1 to cause CTR_Frz = 1. If CPUID.0AH: EAX[7:0] > 3.
3318 /// [Bit 60] Set 1 to cause ASCI = 1. If CPUID.0AH: EAX[7:0] > 3.
3322 /// [Bit 61] Set 1 to cause Ovf_Uncore = 1. If CPUID.0AH: EAX[7:0] > 3.
3324 UINT32 Ovf_Uncore
:1;
3326 /// [Bit 62] Set 1 to cause OvfBuf = 1. If CPUID.0AH: EAX[7:0] > 3.
3332 /// All bit fields as a 64-bit value
3335 } MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER
;
3339 Indicator of core perfmon interface is in use (RO). If CPUID.0AH: EAX[7:0] >
3342 @param ECX MSR_IA32_PERF_GLOBAL_INUSE (0x00000392)
3343 @param EAX Lower 32-bits of MSR value.
3344 Described by the type MSR_IA32_PERF_GLOBAL_INUSE_REGISTER.
3345 @param EDX Upper 32-bits of MSR value.
3346 Described by the type MSR_IA32_PERF_GLOBAL_INUSE_REGISTER.
3348 <b>Example usage</b>
3350 MSR_IA32_PERF_GLOBAL_INUSE_REGISTER Msr;
3352 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PERF_GLOBAL_INUSE);
3354 @note MSR_IA32_PERF_GLOBAL_INUSE is defined as IA32_PERF_GLOBAL_INUSE in SDM.
3356 #define MSR_IA32_PERF_GLOBAL_INUSE 0x00000392
3359 MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_INUSE
3363 /// Individual bit fields
3367 /// [Bits 31:0] IA32_PERFEVTSELn in use. If CPUID.0AH: EAX[7:0] > n.
3368 /// Status bitmask. Only the first n-1 bits are valid.
3369 /// Bits 31:n are reserved.
3371 UINT32 IA32_PERFEVTSELn
:32;
3373 /// [Bits 62:32] IA32_FIXED_CTRn in use.
3374 /// If CPUID.0AH: EAX[7:0] > n.
3375 /// Status bitmask. Only the first n-1 bits are valid.
3376 /// Bits 30:n are reserved.
3378 UINT32 IA32_FIXED_CTRn
:31;
3380 /// [Bit 63] PMI in use.
3385 /// All bit fields as a 64-bit value
3388 } MSR_IA32_PERF_GLOBAL_INUSE_REGISTER
;
3394 @param ECX MSR_IA32_PEBS_ENABLE (0x000003F1)
3395 @param EAX Lower 32-bits of MSR value.
3396 Described by the type MSR_IA32_PEBS_ENABLE_REGISTER.
3397 @param EDX Upper 32-bits of MSR value.
3398 Described by the type MSR_IA32_PEBS_ENABLE_REGISTER.
3400 <b>Example usage</b>
3402 MSR_IA32_PEBS_ENABLE_REGISTER Msr;
3404 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PEBS_ENABLE);
3405 AsmWriteMsr64 (MSR_IA32_PEBS_ENABLE, Msr.Uint64);
3407 @note MSR_IA32_PEBS_ENABLE is defined as IA32_PEBS_ENABLE in SDM.
3409 #define MSR_IA32_PEBS_ENABLE 0x000003F1
3412 MSR information returned for MSR index #MSR_IA32_PEBS_ENABLE
3416 /// Individual bit fields
3420 /// [Bit 0] Enable PEBS on IA32_PMC0. Introduced at Display Family /
3421 /// Display Model 06_0FH.
3425 /// [Bits 3:1] Reserved or Model specific.
3428 UINT32 Reserved2
:28;
3430 /// [Bits 35:32] Reserved or Model specific.
3433 UINT32 Reserved4
:28;
3436 /// All bit fields as a 64-bit value
3439 } MSR_IA32_PEBS_ENABLE_REGISTER
;
3443 MCn_CTL. If IA32_MCG_CAP.CNT > n.
3445 @param ECX MSR_IA32_MCn_CTL
3446 @param EAX Lower 32-bits of MSR value.
3447 @param EDX Upper 32-bits of MSR value.
3449 <b>Example usage</b>
3453 Msr = AsmReadMsr64 (MSR_IA32_MC0_CTL);
3454 AsmWriteMsr64 (MSR_IA32_MC0_CTL, Msr);
3456 @note MSR_IA32_MC0_CTL is defined as IA32_MC0_CTL in SDM.
3457 MSR_IA32_MC1_CTL is defined as IA32_MC1_CTL in SDM.
3458 MSR_IA32_MC2_CTL is defined as IA32_MC2_CTL in SDM.
3459 MSR_IA32_MC3_CTL is defined as IA32_MC3_CTL in SDM.
3460 MSR_IA32_MC4_CTL is defined as IA32_MC4_CTL in SDM.
3461 MSR_IA32_MC5_CTL is defined as IA32_MC5_CTL in SDM.
3462 MSR_IA32_MC6_CTL is defined as IA32_MC6_CTL in SDM.
3463 MSR_IA32_MC7_CTL is defined as IA32_MC7_CTL in SDM.
3464 MSR_IA32_MC8_CTL is defined as IA32_MC8_CTL in SDM.
3465 MSR_IA32_MC9_CTL is defined as IA32_MC9_CTL in SDM.
3466 MSR_IA32_MC10_CTL is defined as IA32_MC10_CTL in SDM.
3467 MSR_IA32_MC11_CTL is defined as IA32_MC11_CTL in SDM.
3468 MSR_IA32_MC12_CTL is defined as IA32_MC12_CTL in SDM.
3469 MSR_IA32_MC13_CTL is defined as IA32_MC13_CTL in SDM.
3470 MSR_IA32_MC14_CTL is defined as IA32_MC14_CTL in SDM.
3471 MSR_IA32_MC15_CTL is defined as IA32_MC15_CTL in SDM.
3472 MSR_IA32_MC16_CTL is defined as IA32_MC16_CTL in SDM.
3473 MSR_IA32_MC17_CTL is defined as IA32_MC17_CTL in SDM.
3474 MSR_IA32_MC18_CTL is defined as IA32_MC18_CTL in SDM.
3475 MSR_IA32_MC19_CTL is defined as IA32_MC19_CTL in SDM.
3476 MSR_IA32_MC20_CTL is defined as IA32_MC20_CTL in SDM.
3477 MSR_IA32_MC21_CTL is defined as IA32_MC21_CTL in SDM.
3478 MSR_IA32_MC22_CTL is defined as IA32_MC22_CTL in SDM.
3479 MSR_IA32_MC23_CTL is defined as IA32_MC23_CTL in SDM.
3480 MSR_IA32_MC24_CTL is defined as IA32_MC24_CTL in SDM.
3481 MSR_IA32_MC25_CTL is defined as IA32_MC25_CTL in SDM.
3482 MSR_IA32_MC26_CTL is defined as IA32_MC26_CTL in SDM.
3483 MSR_IA32_MC27_CTL is defined as IA32_MC27_CTL in SDM.
3484 MSR_IA32_MC28_CTL is defined as IA32_MC28_CTL in SDM.
3487 #define MSR_IA32_MC0_CTL 0x00000400
3488 #define MSR_IA32_MC1_CTL 0x00000404
3489 #define MSR_IA32_MC2_CTL 0x00000408
3490 #define MSR_IA32_MC3_CTL 0x0000040C
3491 #define MSR_IA32_MC4_CTL 0x00000410
3492 #define MSR_IA32_MC5_CTL 0x00000414
3493 #define MSR_IA32_MC6_CTL 0x00000418
3494 #define MSR_IA32_MC7_CTL 0x0000041C
3495 #define MSR_IA32_MC8_CTL 0x00000420
3496 #define MSR_IA32_MC9_CTL 0x00000424
3497 #define MSR_IA32_MC10_CTL 0x00000428
3498 #define MSR_IA32_MC11_CTL 0x0000042C
3499 #define MSR_IA32_MC12_CTL 0x00000430
3500 #define MSR_IA32_MC13_CTL 0x00000434
3501 #define MSR_IA32_MC14_CTL 0x00000438
3502 #define MSR_IA32_MC15_CTL 0x0000043C
3503 #define MSR_IA32_MC16_CTL 0x00000440
3504 #define MSR_IA32_MC17_CTL 0x00000444
3505 #define MSR_IA32_MC18_CTL 0x00000448
3506 #define MSR_IA32_MC19_CTL 0x0000044C
3507 #define MSR_IA32_MC20_CTL 0x00000450
3508 #define MSR_IA32_MC21_CTL 0x00000454
3509 #define MSR_IA32_MC22_CTL 0x00000458
3510 #define MSR_IA32_MC23_CTL 0x0000045C
3511 #define MSR_IA32_MC24_CTL 0x00000460
3512 #define MSR_IA32_MC25_CTL 0x00000464
3513 #define MSR_IA32_MC26_CTL 0x00000468
3514 #define MSR_IA32_MC27_CTL 0x0000046C
3515 #define MSR_IA32_MC28_CTL 0x00000470
3520 MCn_STATUS. If IA32_MCG_CAP.CNT > n.
3522 @param ECX MSR_IA32_MCn_STATUS
3523 @param EAX Lower 32-bits of MSR value.
3524 @param EDX Upper 32-bits of MSR value.
3526 <b>Example usage</b>
3530 Msr = AsmReadMsr64 (MSR_IA32_MC0_STATUS);
3531 AsmWriteMsr64 (MSR_IA32_MC0_STATUS, Msr);
3533 @note MSR_IA32_MC0_STATUS is defined as IA32_MC0_STATUS in SDM.
3534 MSR_IA32_MC1_STATUS is defined as IA32_MC1_STATUS in SDM.
3535 MSR_IA32_MC2_STATUS is defined as IA32_MC2_STATUS in SDM.
3536 MSR_IA32_MC3_STATUS is defined as IA32_MC3_STATUS in SDM.
3537 MSR_IA32_MC4_STATUS is defined as IA32_MC4_STATUS in SDM.
3538 MSR_IA32_MC5_STATUS is defined as IA32_MC5_STATUS in SDM.
3539 MSR_IA32_MC6_STATUS is defined as IA32_MC6_STATUS in SDM.
3540 MSR_IA32_MC7_STATUS is defined as IA32_MC7_STATUS in SDM.
3541 MSR_IA32_MC8_STATUS is defined as IA32_MC8_STATUS in SDM.
3542 MSR_IA32_MC9_STATUS is defined as IA32_MC9_STATUS in SDM.
3543 MSR_IA32_MC10_STATUS is defined as IA32_MC10_STATUS in SDM.
3544 MSR_IA32_MC11_STATUS is defined as IA32_MC11_STATUS in SDM.
3545 MSR_IA32_MC12_STATUS is defined as IA32_MC12_STATUS in SDM.
3546 MSR_IA32_MC13_STATUS is defined as IA32_MC13_STATUS in SDM.
3547 MSR_IA32_MC14_STATUS is defined as IA32_MC14_STATUS in SDM.
3548 MSR_IA32_MC15_STATUS is defined as IA32_MC15_STATUS in SDM.
3549 MSR_IA32_MC16_STATUS is defined as IA32_MC16_STATUS in SDM.
3550 MSR_IA32_MC17_STATUS is defined as IA32_MC17_STATUS in SDM.
3551 MSR_IA32_MC18_STATUS is defined as IA32_MC18_STATUS in SDM.
3552 MSR_IA32_MC19_STATUS is defined as IA32_MC19_STATUS in SDM.
3553 MSR_IA32_MC20_STATUS is defined as IA32_MC20_STATUS in SDM.
3554 MSR_IA32_MC21_STATUS is defined as IA32_MC21_STATUS in SDM.
3555 MSR_IA32_MC22_STATUS is defined as IA32_MC22_STATUS in SDM.
3556 MSR_IA32_MC23_STATUS is defined as IA32_MC23_STATUS in SDM.
3557 MSR_IA32_MC24_STATUS is defined as IA32_MC24_STATUS in SDM.
3558 MSR_IA32_MC25_STATUS is defined as IA32_MC25_STATUS in SDM.
3559 MSR_IA32_MC26_STATUS is defined as IA32_MC26_STATUS in SDM.
3560 MSR_IA32_MC27_STATUS is defined as IA32_MC27_STATUS in SDM.
3561 MSR_IA32_MC28_STATUS is defined as IA32_MC28_STATUS in SDM.
3564 #define MSR_IA32_MC0_STATUS 0x00000401
3565 #define MSR_IA32_MC1_STATUS 0x00000405
3566 #define MSR_IA32_MC2_STATUS 0x00000409
3567 #define MSR_IA32_MC3_STATUS 0x0000040D
3568 #define MSR_IA32_MC4_STATUS 0x00000411
3569 #define MSR_IA32_MC5_STATUS 0x00000415
3570 #define MSR_IA32_MC6_STATUS 0x00000419
3571 #define MSR_IA32_MC7_STATUS 0x0000041D
3572 #define MSR_IA32_MC8_STATUS 0x00000421
3573 #define MSR_IA32_MC9_STATUS 0x00000425
3574 #define MSR_IA32_MC10_STATUS 0x00000429
3575 #define MSR_IA32_MC11_STATUS 0x0000042D
3576 #define MSR_IA32_MC12_STATUS 0x00000431
3577 #define MSR_IA32_MC13_STATUS 0x00000435
3578 #define MSR_IA32_MC14_STATUS 0x00000439
3579 #define MSR_IA32_MC15_STATUS 0x0000043D
3580 #define MSR_IA32_MC16_STATUS 0x00000441
3581 #define MSR_IA32_MC17_STATUS 0x00000445
3582 #define MSR_IA32_MC18_STATUS 0x00000449
3583 #define MSR_IA32_MC19_STATUS 0x0000044D
3584 #define MSR_IA32_MC20_STATUS 0x00000451
3585 #define MSR_IA32_MC21_STATUS 0x00000455
3586 #define MSR_IA32_MC22_STATUS 0x00000459
3587 #define MSR_IA32_MC23_STATUS 0x0000045D
3588 #define MSR_IA32_MC24_STATUS 0x00000461
3589 #define MSR_IA32_MC25_STATUS 0x00000465
3590 #define MSR_IA32_MC26_STATUS 0x00000469
3591 #define MSR_IA32_MC27_STATUS 0x0000046D
3592 #define MSR_IA32_MC28_STATUS 0x00000471
3597 MCn_ADDR. If IA32_MCG_CAP.CNT > n.
3599 @param ECX MSR_IA32_MCn_ADDR
3600 @param EAX Lower 32-bits of MSR value.
3601 @param EDX Upper 32-bits of MSR value.
3603 <b>Example usage</b>
3607 Msr = AsmReadMsr64 (MSR_IA32_MC0_ADDR);
3608 AsmWriteMsr64 (MSR_IA32_MC0_ADDR, Msr);
3610 @note MSR_IA32_MC0_ADDR is defined as IA32_MC0_ADDR in SDM.
3611 MSR_IA32_MC1_ADDR is defined as IA32_MC1_ADDR in SDM.
3612 MSR_IA32_MC2_ADDR is defined as IA32_MC2_ADDR in SDM.
3613 MSR_IA32_MC3_ADDR is defined as IA32_MC3_ADDR in SDM.
3614 MSR_IA32_MC4_ADDR is defined as IA32_MC4_ADDR in SDM.
3615 MSR_IA32_MC5_ADDR is defined as IA32_MC5_ADDR in SDM.
3616 MSR_IA32_MC6_ADDR is defined as IA32_MC6_ADDR in SDM.
3617 MSR_IA32_MC7_ADDR is defined as IA32_MC7_ADDR in SDM.
3618 MSR_IA32_MC8_ADDR is defined as IA32_MC8_ADDR in SDM.
3619 MSR_IA32_MC9_ADDR is defined as IA32_MC9_ADDR in SDM.
3620 MSR_IA32_MC10_ADDR is defined as IA32_MC10_ADDR in SDM.
3621 MSR_IA32_MC11_ADDR is defined as IA32_MC11_ADDR in SDM.
3622 MSR_IA32_MC12_ADDR is defined as IA32_MC12_ADDR in SDM.
3623 MSR_IA32_MC13_ADDR is defined as IA32_MC13_ADDR in SDM.
3624 MSR_IA32_MC14_ADDR is defined as IA32_MC14_ADDR in SDM.
3625 MSR_IA32_MC15_ADDR is defined as IA32_MC15_ADDR in SDM.
3626 MSR_IA32_MC16_ADDR is defined as IA32_MC16_ADDR in SDM.
3627 MSR_IA32_MC17_ADDR is defined as IA32_MC17_ADDR in SDM.
3628 MSR_IA32_MC18_ADDR is defined as IA32_MC18_ADDR in SDM.
3629 MSR_IA32_MC19_ADDR is defined as IA32_MC19_ADDR in SDM.
3630 MSR_IA32_MC20_ADDR is defined as IA32_MC20_ADDR in SDM.
3631 MSR_IA32_MC21_ADDR is defined as IA32_MC21_ADDR in SDM.
3632 MSR_IA32_MC22_ADDR is defined as IA32_MC22_ADDR in SDM.
3633 MSR_IA32_MC23_ADDR is defined as IA32_MC23_ADDR in SDM.
3634 MSR_IA32_MC24_ADDR is defined as IA32_MC24_ADDR in SDM.
3635 MSR_IA32_MC25_ADDR is defined as IA32_MC25_ADDR in SDM.
3636 MSR_IA32_MC26_ADDR is defined as IA32_MC26_ADDR in SDM.
3637 MSR_IA32_MC27_ADDR is defined as IA32_MC27_ADDR in SDM.
3638 MSR_IA32_MC28_ADDR is defined as IA32_MC28_ADDR in SDM.
3641 #define MSR_IA32_MC0_ADDR 0x00000402
3642 #define MSR_IA32_MC1_ADDR 0x00000406
3643 #define MSR_IA32_MC2_ADDR 0x0000040A
3644 #define MSR_IA32_MC3_ADDR 0x0000040E
3645 #define MSR_IA32_MC4_ADDR 0x00000412
3646 #define MSR_IA32_MC5_ADDR 0x00000416
3647 #define MSR_IA32_MC6_ADDR 0x0000041A
3648 #define MSR_IA32_MC7_ADDR 0x0000041E
3649 #define MSR_IA32_MC8_ADDR 0x00000422
3650 #define MSR_IA32_MC9_ADDR 0x00000426
3651 #define MSR_IA32_MC10_ADDR 0x0000042A
3652 #define MSR_IA32_MC11_ADDR 0x0000042E
3653 #define MSR_IA32_MC12_ADDR 0x00000432
3654 #define MSR_IA32_MC13_ADDR 0x00000436
3655 #define MSR_IA32_MC14_ADDR 0x0000043A
3656 #define MSR_IA32_MC15_ADDR 0x0000043E
3657 #define MSR_IA32_MC16_ADDR 0x00000442
3658 #define MSR_IA32_MC17_ADDR 0x00000446
3659 #define MSR_IA32_MC18_ADDR 0x0000044A
3660 #define MSR_IA32_MC19_ADDR 0x0000044E
3661 #define MSR_IA32_MC20_ADDR 0x00000452
3662 #define MSR_IA32_MC21_ADDR 0x00000456
3663 #define MSR_IA32_MC22_ADDR 0x0000045A
3664 #define MSR_IA32_MC23_ADDR 0x0000045E
3665 #define MSR_IA32_MC24_ADDR 0x00000462
3666 #define MSR_IA32_MC25_ADDR 0x00000466
3667 #define MSR_IA32_MC26_ADDR 0x0000046A
3668 #define MSR_IA32_MC27_ADDR 0x0000046E
3669 #define MSR_IA32_MC28_ADDR 0x00000472
3674 MCn_MISC. If IA32_MCG_CAP.CNT > n.
3676 @param ECX MSR_IA32_MCn_MISC
3677 @param EAX Lower 32-bits of MSR value.
3678 @param EDX Upper 32-bits of MSR value.
3680 <b>Example usage</b>
3684 Msr = AsmReadMsr64 (MSR_IA32_MC0_MISC);
3685 AsmWriteMsr64 (MSR_IA32_MC0_MISC, Msr);
3687 @note MSR_IA32_MC0_MISC is defined as IA32_MC0_MISC in SDM.
3688 MSR_IA32_MC1_MISC is defined as IA32_MC1_MISC in SDM.
3689 MSR_IA32_MC2_MISC is defined as IA32_MC2_MISC in SDM.
3690 MSR_IA32_MC3_MISC is defined as IA32_MC3_MISC in SDM.
3691 MSR_IA32_MC4_MISC is defined as IA32_MC4_MISC in SDM.
3692 MSR_IA32_MC5_MISC is defined as IA32_MC5_MISC in SDM.
3693 MSR_IA32_MC6_MISC is defined as IA32_MC6_MISC in SDM.
3694 MSR_IA32_MC7_MISC is defined as IA32_MC7_MISC in SDM.
3695 MSR_IA32_MC8_MISC is defined as IA32_MC8_MISC in SDM.
3696 MSR_IA32_MC9_MISC is defined as IA32_MC9_MISC in SDM.
3697 MSR_IA32_MC10_MISC is defined as IA32_MC10_MISC in SDM.
3698 MSR_IA32_MC11_MISC is defined as IA32_MC11_MISC in SDM.
3699 MSR_IA32_MC12_MISC is defined as IA32_MC12_MISC in SDM.
3700 MSR_IA32_MC13_MISC is defined as IA32_MC13_MISC in SDM.
3701 MSR_IA32_MC14_MISC is defined as IA32_MC14_MISC in SDM.
3702 MSR_IA32_MC15_MISC is defined as IA32_MC15_MISC in SDM.
3703 MSR_IA32_MC16_MISC is defined as IA32_MC16_MISC in SDM.
3704 MSR_IA32_MC17_MISC is defined as IA32_MC17_MISC in SDM.
3705 MSR_IA32_MC18_MISC is defined as IA32_MC18_MISC in SDM.
3706 MSR_IA32_MC19_MISC is defined as IA32_MC19_MISC in SDM.
3707 MSR_IA32_MC20_MISC is defined as IA32_MC20_MISC in SDM.
3708 MSR_IA32_MC21_MISC is defined as IA32_MC21_MISC in SDM.
3709 MSR_IA32_MC22_MISC is defined as IA32_MC22_MISC in SDM.
3710 MSR_IA32_MC23_MISC is defined as IA32_MC23_MISC in SDM.
3711 MSR_IA32_MC24_MISC is defined as IA32_MC24_MISC in SDM.
3712 MSR_IA32_MC25_MISC is defined as IA32_MC25_MISC in SDM.
3713 MSR_IA32_MC26_MISC is defined as IA32_MC26_MISC in SDM.
3714 MSR_IA32_MC27_MISC is defined as IA32_MC27_MISC in SDM.
3715 MSR_IA32_MC28_MISC is defined as IA32_MC28_MISC in SDM.
3718 #define MSR_IA32_MC0_MISC 0x00000403
3719 #define MSR_IA32_MC1_MISC 0x00000407
3720 #define MSR_IA32_MC2_MISC 0x0000040B
3721 #define MSR_IA32_MC3_MISC 0x0000040F
3722 #define MSR_IA32_MC4_MISC 0x00000413
3723 #define MSR_IA32_MC5_MISC 0x00000417
3724 #define MSR_IA32_MC6_MISC 0x0000041B
3725 #define MSR_IA32_MC7_MISC 0x0000041F
3726 #define MSR_IA32_MC8_MISC 0x00000423
3727 #define MSR_IA32_MC9_MISC 0x00000427
3728 #define MSR_IA32_MC10_MISC 0x0000042B
3729 #define MSR_IA32_MC11_MISC 0x0000042F
3730 #define MSR_IA32_MC12_MISC 0x00000433
3731 #define MSR_IA32_MC13_MISC 0x00000437
3732 #define MSR_IA32_MC14_MISC 0x0000043B
3733 #define MSR_IA32_MC15_MISC 0x0000043F
3734 #define MSR_IA32_MC16_MISC 0x00000443
3735 #define MSR_IA32_MC17_MISC 0x00000447
3736 #define MSR_IA32_MC18_MISC 0x0000044B
3737 #define MSR_IA32_MC19_MISC 0x0000044F
3738 #define MSR_IA32_MC20_MISC 0x00000453
3739 #define MSR_IA32_MC21_MISC 0x00000457
3740 #define MSR_IA32_MC22_MISC 0x0000045B
3741 #define MSR_IA32_MC23_MISC 0x0000045F
3742 #define MSR_IA32_MC24_MISC 0x00000463
3743 #define MSR_IA32_MC25_MISC 0x00000467
3744 #define MSR_IA32_MC26_MISC 0x0000046B
3745 #define MSR_IA32_MC27_MISC 0x0000046F
3746 #define MSR_IA32_MC28_MISC 0x00000473
3751 Reporting Register of Basic VMX Capabilities (R/O) See Appendix A.1, "Basic
3752 VMX Information.". If CPUID.01H:ECX.[5] = 1.
3754 @param ECX MSR_IA32_VMX_BASIC (0x00000480)
3755 @param EAX Lower 32-bits of MSR value.
3756 @param EDX Upper 32-bits of MSR value.
3758 <b>Example usage</b>
3760 MSR_IA32_VMX_BASIC_REGISTER Msr;
3762 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_VMX_BASIC);
3764 @note MSR_IA32_VMX_BASIC is defined as IA32_VMX_BASIC in SDM.
3766 #define MSR_IA32_VMX_BASIC 0x00000480
3769 MSR information returned for MSR index #MSR_IA32_VMX_BASIC
3773 /// Individual bit fields
3777 /// [Bits 30:0] VMCS revision identifier used by the processor. Processors
3778 /// that use the same VMCS revision identifier use the same size for VMCS
3779 /// regions (see subsequent item on bits 44:32).
3781 /// @note Earlier versions of this manual specified that the VMCS revision
3782 /// identifier was a 32-bit field in bits 31:0 of this MSR. For all
3783 /// processors produced prior to this change, bit 31 of this MSR was read
3786 UINT32 VmcsRevisonId
:31;
3787 UINT32 MustBeZero
:1;
3789 /// [Bit 44:32] Reports the number of bytes that software should allocate
3790 /// for the VMXON region and any VMCS region. It is a value greater than
3791 /// 0 and at most 4096(bit 44 is set if and only if bits 43:32 are clear).
3796 /// [Bit 48] Indicates the width of the physical addresses that may be used
3797 /// for the VMXON region, each VMCS, and data structures referenced by
3798 /// pointers in a VMCS (I/O bitmaps, virtual-APIC page, MSR areas for VMX
3799 /// transitions). If the bit is 0, these addresses are limited to the
3800 /// processor's physical-address width. If the bit is 1, these addresses
3801 /// are limited to 32 bits. This bit is always 0 for processors that
3802 /// support Intel 64 architecture.
3804 /// @note On processors that support Intel 64 architecture, the pointer
3805 /// must not set bits beyond the processor's physical address width.
3807 UINT32 VmcsAddressWidth
:1;
3809 /// [Bit 49] If bit 49 is read as 1, the logical processor supports the
3810 /// dual-monitor treatment of system-management interrupts and
3811 /// system-management mode. See Section 34.15 for details of this treatment.
3813 UINT32 DualMonitor
:1;
3815 /// [Bit 53:50] report the memory type that should be used for the VMCS,
3816 /// for data structures referenced by pointers in the VMCS (I/O bitmaps,
3817 /// virtual-APIC page, MSR areas for VMX transitions), and for the MSEG
3818 /// header. If software needs to access these data structures (e.g., to
3819 /// modify the contents of the MSR bitmaps), it can configure the paging
3820 /// structures to map them into the linear-address space. If it does so,
3821 /// it should establish mappings that use the memory type reported bits
3822 /// 53:50 in this MSR.
3824 /// As of this writing, all processors that support VMX operation indicate
3825 /// the write-back type.
3827 /// If software needs to access these data structures (e.g., to modify
3828 /// the contents of the MSR bitmaps), it can configure the paging
3829 /// structures to map them into the linear-address space. If it does so,
3830 /// it should establish mappings that use the memory type reported in this
3833 /// @note Alternatively, software may map any of these regions or
3834 /// structures with the UC memory type. (This may be necessary for the MSEG
3835 /// header.) Doing so is discouraged unless necessary as it will cause the
3836 /// performance of software accesses to those structures to suffer.
3839 UINT32 MemoryType
:4;
3841 /// [Bit 54] If bit 54 is read as 1, the processor reports information in
3842 /// the VM-exit instruction-information field on VM exitsdue to execution
3843 /// of the INS and OUTS instructions (see Section 27.2.4). This reporting
3844 /// is done only if this bit is read as 1.
3846 UINT32 InsOutsReporting
:1;
3848 /// [Bit 55] Bit 55 is read as 1 if any VMX controls that default to 1 may
3849 /// be cleared to 0. See Appendix A.2 for details. It also reports support
3850 /// for the VMX capability MSRs IA32_VMX_TRUE_PINBASED_CTLS,
3851 /// IA32_VMX_TRUE_PROCBASED_CTLS, IA32_VMX_TRUE_EXIT_CTLS, and
3852 /// IA32_VMX_TRUE_ENTRY_CTLS. See Appendix A.3.1, Appendix A.3.2,
3853 /// Appendix A.4, and Appendix A.5 for details.
3855 UINT32 VmxControls
:1;
3859 /// All bit fields as a 64-bit value
3862 } MSR_IA32_VMX_BASIC_REGISTER
;
3865 /// @{ Define value for bit field MSR_IA32_VMX_BASIC_REGISTER.MemoryType
3867 #define MSR_IA32_VMX_BASIC_REGISTER_MEMORY_TYPE_UNCACHEABLE 0x00
3868 #define MSR_IA32_VMX_BASIC_REGISTER_MEMORY_TYPE_WRITE_BACK 0x06
3875 Capability Reporting Register of Pinbased VM-execution Controls (R/O) See
3876 Appendix A.3.1, "Pin-Based VMExecution Controls.". If CPUID.01H:ECX.[5] = 1.
3878 @param ECX MSR_IA32_VMX_PINBASED_CTLS (0x00000481)
3879 @param EAX Lower 32-bits of MSR value.
3880 @param EDX Upper 32-bits of MSR value.
3882 <b>Example usage</b>
3886 Msr = AsmReadMsr64 (MSR_IA32_VMX_PINBASED_CTLS);
3888 @note MSR_IA32_VMX_PINBASED_CTLS is defined as IA32_VMX_PINBASED_CTLS in SDM.
3890 #define MSR_IA32_VMX_PINBASED_CTLS 0x00000481
3894 Capability Reporting Register of Primary Processor-based VM-execution
3895 Controls (R/O) See Appendix A.3.2, "Primary Processor- Based VM-Execution
3896 Controls.". If CPUID.01H:ECX.[5] = 1.
3898 @param ECX MSR_IA32_VMX_PROCBASED_CTLS (0x00000482)
3899 @param EAX Lower 32-bits of MSR value.
3900 @param EDX Upper 32-bits of MSR value.
3902 <b>Example usage</b>
3906 Msr = AsmReadMsr64 (MSR_IA32_VMX_PROCBASED_CTLS);
3908 @note MSR_IA32_VMX_PROCBASED_CTLS is defined as IA32_VMX_PROCBASED_CTLS in SDM.
3910 #define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482
3914 Capability Reporting Register of VM-exit Controls (R/O) See Appendix A.4,
3915 "VM-Exit Controls.". If CPUID.01H:ECX.[5] = 1.
3917 @param ECX MSR_IA32_VMX_EXIT_CTLS (0x00000483)
3918 @param EAX Lower 32-bits of MSR value.
3919 @param EDX Upper 32-bits of MSR value.
3921 <b>Example usage</b>
3925 Msr = AsmReadMsr64 (MSR_IA32_VMX_EXIT_CTLS);
3927 @note MSR_IA32_VMX_EXIT_CTLS is defined as IA32_VMX_EXIT_CTLS in SDM.
3929 #define MSR_IA32_VMX_EXIT_CTLS 0x00000483
3933 Capability Reporting Register of VMentry Controls (R/O) See Appendix A.5,
3934 "VM-Entry Controls.". If CPUID.01H:ECX.[5] = 1.
3936 @param ECX MSR_IA32_VMX_ENTRY_CTLS (0x00000484)
3937 @param EAX Lower 32-bits of MSR value.
3938 @param EDX Upper 32-bits of MSR value.
3940 <b>Example usage</b>
3944 Msr = AsmReadMsr64 (MSR_IA32_VMX_ENTRY_CTLS);
3946 @note MSR_IA32_VMX_ENTRY_CTLS is defined as IA32_VMX_ENTRY_CTLS in SDM.
3948 #define MSR_IA32_VMX_ENTRY_CTLS 0x00000484
3952 Reporting Register of Miscellaneous VMX Capabilities (R/O) See Appendix A.6,
3953 "Miscellaneous Data.". If CPUID.01H:ECX.[5] = 1.
3955 @param ECX MSR_IA32_VMX_MISC (0x00000485)
3956 @param EAX Lower 32-bits of MSR value.
3957 @param EDX Upper 32-bits of MSR value.
3959 <b>Example usage</b>
3961 IA32_VMX_MISC_REGISTER Msr;
3963 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_VMX_MISC);
3965 @note MSR_IA32_VMX_MISC is defined as IA32_VMX_MISC in SDM.
3967 #define MSR_IA32_VMX_MISC 0x00000485
3970 MSR information returned for MSR index #IA32_VMX_MISC
3974 /// Individual bit fields
3978 /// [Bits 4:0] Reports a value X that specifies the relationship between the
3979 /// rate of the VMX-preemption timer and that of the timestamp counter (TSC).
3980 /// Specifically, the VMX-preemption timer (if it is active) counts down by
3981 /// 1 every time bit X in the TSC changes due to a TSC increment.
3983 UINT32 VmxTimerRatio
:5;
3985 /// [Bit 5] If bit 5 is read as 1, VM exits store the value of IA32_EFER.LMA
3986 /// into the "IA-32e mode guest" VM-entry control;see Section 27.2 for more
3987 /// details. This bit is read as 1 on any logical processor that supports
3988 /// the 1-setting of the "unrestricted guest" VM-execution control.
3990 UINT32 VmExitEferLma
:1;
3992 /// [Bit 6] reports (if set) the support for activity state 1 (HLT).
3994 UINT32 HltActivityStateSupported
:1;
3996 /// [Bit 7] reports (if set) the support for activity state 2 (shutdown).
3998 UINT32 ShutdownActivityStateSupported
:1;
4000 /// [Bit 8] reports (if set) the support for activity state 3 (wait-for-SIPI).
4002 UINT32 WaitForSipiActivityStateSupported
:1;
4005 /// [Bit 14] If read as 1, Intel(R) Processor Trace (Intel PT) can be used
4006 /// in VMX operation. If the processor supports Intel PT but does not allow
4007 /// it to be used in VMX operation, execution of VMXON clears
4008 /// IA32_RTIT_CTL.TraceEn (see "VMXON-Enter VMX Operation" in Chapter 30);
4009 /// any attempt to set that bit while in VMX operation (including VMX root
4010 /// operation) using the WRMSR instruction causes a general-protection
4013 UINT32 ProcessorTraceSupported
:1;
4015 /// [Bit 15] If read as 1, the RDMSR instruction can be used in system-
4016 /// management mode (SMM) to read the IA32_SMBASE MSR (MSR address 9EH).
4017 /// See Section 34.15.6.3.
4019 UINT32 SmBaseMsrSupported
:1;
4021 /// [Bits 24:16] Indicate the number of CR3-target values supported by the
4022 /// processor. This number is a value between 0 and 256, inclusive (bit 24
4023 /// is set if and only if bits 23:16 are clear).
4025 UINT32 NumberOfCr3TargetValues
:9;
4027 /// [Bit 27:25] Bits 27:25 is used to compute the recommended maximum
4028 /// number of MSRs that should appear in the VM-exit MSR-store list, the
4029 /// VM-exit MSR-load list, or the VM-entry MSR-load list. Specifically, if
4030 /// the value bits 27:25 of IA32_VMX_MISC is N, then 512 * (N + 1) is the
4031 /// recommended maximum number of MSRs to be included in each list. If the
4032 /// limit is exceeded, undefined processor behavior may result (including a
4033 /// machine check during the VMX transition).
4035 UINT32 MsrStoreListMaximum
:3;
4037 /// [Bit 28] If read as 1, bit 2 of the IA32_SMM_MONITOR_CTL can be set
4038 /// to 1. VMXOFF unblocks SMIs unless IA32_SMM_MONITOR_CTL[bit 2] is 1
4039 /// (see Section 34.14.4).
4041 UINT32 BlockSmiSupported
:1;
4043 /// [Bit 29] read as 1, software can use VMWRITE to write to any supported
4044 /// field in the VMCS; otherwise, VMWRITE cannot be used to modify VM-exit
4045 /// information fields.
4047 UINT32 VmWriteSupported
:1;
4049 /// [Bit 30] If read as 1, VM entry allows injection of a software
4050 /// interrupt, software exception, or privileged software exception with an
4051 /// instruction length of 0.
4053 UINT32 VmInjectSupported
:1;
4056 /// [Bits 63:32] Reports the 32-bit MSEG revision identifier used by the
4059 UINT32 MsegRevisionIdentifier
:32;
4062 /// All bit fields as a 64-bit value
4065 } IA32_VMX_MISC_REGISTER
;
4069 Capability Reporting Register of CR0 Bits Fixed to 0 (R/O) See Appendix A.7,
4070 "VMX-Fixed Bits in CR0.". If CPUID.01H:ECX.[5] = 1.
4072 @param ECX MSR_IA32_VMX_CR0_FIXED0 (0x00000486)
4073 @param EAX Lower 32-bits of MSR value.
4074 @param EDX Upper 32-bits of MSR value.
4076 <b>Example usage</b>
4080 Msr = AsmReadMsr64 (MSR_IA32_VMX_CR0_FIXED0);
4082 @note MSR_IA32_VMX_CR0_FIXED0 is defined as IA32_VMX_CR0_FIXED0 in SDM.
4084 #define MSR_IA32_VMX_CR0_FIXED0 0x00000486
4088 Capability Reporting Register of CR0 Bits Fixed to 1 (R/O) See Appendix A.7,
4089 "VMX-Fixed Bits in CR0.". If CPUID.01H:ECX.[5] = 1.
4091 @param ECX MSR_IA32_VMX_CR0_FIXED1 (0x00000487)
4092 @param EAX Lower 32-bits of MSR value.
4093 @param EDX Upper 32-bits of MSR value.
4095 <b>Example usage</b>
4099 Msr = AsmReadMsr64 (MSR_IA32_VMX_CR0_FIXED1);
4101 @note MSR_IA32_VMX_CR0_FIXED1 is defined as IA32_VMX_CR0_FIXED1 in SDM.
4103 #define MSR_IA32_VMX_CR0_FIXED1 0x00000487
4107 Capability Reporting Register of CR4 Bits Fixed to 0 (R/O) See Appendix A.8,
4108 "VMX-Fixed Bits in CR4.". If CPUID.01H:ECX.[5] = 1.
4110 @param ECX MSR_IA32_VMX_CR4_FIXED0 (0x00000488)
4111 @param EAX Lower 32-bits of MSR value.
4112 @param EDX Upper 32-bits of MSR value.
4114 <b>Example usage</b>
4118 Msr = AsmReadMsr64 (MSR_IA32_VMX_CR4_FIXED0);
4120 @note MSR_IA32_VMX_CR4_FIXED0 is defined as IA32_VMX_CR4_FIXED0 in SDM.
4122 #define MSR_IA32_VMX_CR4_FIXED0 0x00000488
4126 Capability Reporting Register of CR4 Bits Fixed to 1 (R/O) See Appendix A.8,
4127 "VMX-Fixed Bits in CR4.". If CPUID.01H:ECX.[5] = 1.
4129 @param ECX MSR_IA32_VMX_CR4_FIXED1 (0x00000489)
4130 @param EAX Lower 32-bits of MSR value.
4131 @param EDX Upper 32-bits of MSR value.
4133 <b>Example usage</b>
4137 Msr = AsmReadMsr64 (MSR_IA32_VMX_CR4_FIXED1);
4139 @note MSR_IA32_VMX_CR4_FIXED1 is defined as IA32_VMX_CR4_FIXED1 in SDM.
4141 #define MSR_IA32_VMX_CR4_FIXED1 0x00000489
4145 Capability Reporting Register of VMCS Field Enumeration (R/O) See Appendix
4146 A.9, "VMCS Enumeration.". If CPUID.01H:ECX.[5] = 1.
4148 @param ECX MSR_IA32_VMX_VMCS_ENUM (0x0000048A)
4149 @param EAX Lower 32-bits of MSR value.
4150 @param EDX Upper 32-bits of MSR value.
4152 <b>Example usage</b>
4156 Msr = AsmReadMsr64 (MSR_IA32_VMX_VMCS_ENUM);
4158 @note MSR_IA32_VMX_VMCS_ENUM is defined as IA32_VMX_VMCS_ENUM in SDM.
4160 #define MSR_IA32_VMX_VMCS_ENUM 0x0000048A
4164 Capability Reporting Register of Secondary Processor-based VM-execution
4165 Controls (R/O) See Appendix A.3.3, "Secondary Processor- Based VM-Execution
4166 Controls.". If ( CPUID.01H:ECX.[5] && IA32_VMX_PROCBASED_C TLS[63]).
4168 @param ECX MSR_IA32_VMX_PROCBASED_CTLS2 (0x0000048B)
4169 @param EAX Lower 32-bits of MSR value.
4170 @param EDX Upper 32-bits of MSR value.
4172 <b>Example usage</b>
4176 Msr = AsmReadMsr64 (MSR_IA32_VMX_PROCBASED_CTLS2);
4178 @note MSR_IA32_VMX_PROCBASED_CTLS2 is defined as IA32_VMX_PROCBASED_CTLS2 in SDM.
4180 #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048B
4184 Capability Reporting Register of EPT and VPID (R/O) See Appendix A.10,
4185 "VPID and EPT Capabilities.". If ( CPUID.01H:ECX.[5] && IA32_VMX_PROCBASED_C
4186 TLS[63] && ( IA32_VMX_PROCBASED_C TLS2[33] IA32_VMX_PROCBASED_C TLS2[37]) ).
4188 @param ECX MSR_IA32_VMX_EPT_VPID_CAP (0x0000048C)
4189 @param EAX Lower 32-bits of MSR value.
4190 @param EDX Upper 32-bits of MSR value.
4192 <b>Example usage</b>
4196 Msr = AsmReadMsr64 (MSR_IA32_VMX_EPT_VPID_CAP);
4198 @note MSR_IA32_VMX_EPT_VPID_CAP is defined as IA32_VMX_EPT_VPID_CAP in SDM.
4200 #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048C
4204 Capability Reporting Register of Pinbased VM-execution Flex Controls (R/O)
4205 See Appendix A.3.1, "Pin-Based VMExecution Controls.". If (
4206 CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ).
4208 @param ECX MSR_IA32_VMX_TRUE_PINBASED_CTLS (0x0000048D)
4209 @param EAX Lower 32-bits of MSR value.
4210 @param EDX Upper 32-bits of MSR value.
4212 <b>Example usage</b>
4216 Msr = AsmReadMsr64 (MSR_IA32_VMX_TRUE_PINBASED_CTLS);
4218 @note MSR_IA32_VMX_TRUE_PINBASED_CTLS is defined as IA32_VMX_TRUE_PINBASED_CTLS in SDM.
4220 #define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048D
4224 Capability Reporting Register of Primary Processor-based VM-execution Flex
4225 Controls (R/O) See Appendix A.3.2, "Primary Processor- Based VM-Execution
4226 Controls.". If( CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ).
4228 @param ECX MSR_IA32_VMX_TRUE_PROCBASED_CTLS (0x0000048E)
4229 @param EAX Lower 32-bits of MSR value.
4230 @param EDX Upper 32-bits of MSR value.
4232 <b>Example usage</b>
4236 Msr = AsmReadMsr64 (MSR_IA32_VMX_TRUE_PROCBASED_CTLS);
4238 @note MSR_IA32_VMX_TRUE_PROCBASED_CTLS is defined as IA32_VMX_TRUE_PROCBASED_CTLS in SDM.
4240 #define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048E
4244 Capability Reporting Register of VM-exit Flex Controls (R/O) See Appendix
4245 A.4, "VM-Exit Controls.". If( CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ).
4247 @param ECX MSR_IA32_VMX_TRUE_EXIT_CTLS (0x0000048F)
4248 @param EAX Lower 32-bits of MSR value.
4249 @param EDX Upper 32-bits of MSR value.
4251 <b>Example usage</b>
4255 Msr = AsmReadMsr64 (MSR_IA32_VMX_TRUE_EXIT_CTLS);
4257 @note MSR_IA32_VMX_TRUE_EXIT_CTLS is defined as IA32_VMX_TRUE_EXIT_CTLS in SDM.
4259 #define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048F
4263 Capability Reporting Register of VMentry Flex Controls (R/O) See Appendix
4264 A.5, "VM-Entry Controls.". If( CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ).
4266 @param ECX MSR_IA32_VMX_TRUE_ENTRY_CTLS (0x00000490)
4267 @param EAX Lower 32-bits of MSR value.
4268 @param EDX Upper 32-bits of MSR value.
4270 <b>Example usage</b>
4274 Msr = AsmReadMsr64 (MSR_IA32_VMX_TRUE_ENTRY_CTLS);
4276 @note MSR_IA32_VMX_TRUE_ENTRY_CTLS is defined as IA32_VMX_TRUE_ENTRY_CTLS in SDM.
4278 #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490
4282 Capability Reporting Register of VMfunction Controls (R/O). If(
4283 CPUID.01H:ECX.[5] = 1 && IA32_VMX_BASIC[55] ).
4285 @param ECX MSR_IA32_VMX_VMFUNC (0x00000491)
4286 @param EAX Lower 32-bits of MSR value.
4287 @param EDX Upper 32-bits of MSR value.
4289 <b>Example usage</b>
4293 Msr = AsmReadMsr64 (MSR_IA32_VMX_VMFUNC);
4295 @note MSR_IA32_VMX_VMFUNC is defined as IA32_VMX_VMFUNC in SDM.
4297 #define MSR_IA32_VMX_VMFUNC 0x00000491
4301 Full Width Writable IA32_PMCn Alias (R/W). (If CPUID.0AH: EAX[15:8] > n) &&
4302 IA32_PERF_CAPABILITIES[ 13] = 1.
4304 @param ECX MSR_IA32_A_PMCn
4305 @param EAX Lower 32-bits of MSR value.
4306 @param EDX Upper 32-bits of MSR value.
4308 <b>Example usage</b>
4312 Msr = AsmReadMsr64 (MSR_IA32_A_PMC0);
4313 AsmWriteMsr64 (MSR_IA32_A_PMC0, Msr);
4315 @note MSR_IA32_A_PMC0 is defined as IA32_A_PMC0 in SDM.
4316 MSR_IA32_A_PMC1 is defined as IA32_A_PMC1 in SDM.
4317 MSR_IA32_A_PMC2 is defined as IA32_A_PMC2 in SDM.
4318 MSR_IA32_A_PMC3 is defined as IA32_A_PMC3 in SDM.
4319 MSR_IA32_A_PMC4 is defined as IA32_A_PMC4 in SDM.
4320 MSR_IA32_A_PMC5 is defined as IA32_A_PMC5 in SDM.
4321 MSR_IA32_A_PMC6 is defined as IA32_A_PMC6 in SDM.
4322 MSR_IA32_A_PMC7 is defined as IA32_A_PMC7 in SDM.
4325 #define MSR_IA32_A_PMC0 0x000004C1
4326 #define MSR_IA32_A_PMC1 0x000004C2
4327 #define MSR_IA32_A_PMC2 0x000004C3
4328 #define MSR_IA32_A_PMC3 0x000004C4
4329 #define MSR_IA32_A_PMC4 0x000004C5
4330 #define MSR_IA32_A_PMC5 0x000004C6
4331 #define MSR_IA32_A_PMC6 0x000004C7
4332 #define MSR_IA32_A_PMC7 0x000004C8
4337 (R/W). If IA32_MCG_CAP.LMCE_P =1.
4339 @param ECX MSR_IA32_MCG_EXT_CTL (0x000004D0)
4340 @param EAX Lower 32-bits of MSR value.
4341 Described by the type MSR_IA32_MCG_EXT_CTL_REGISTER.
4342 @param EDX Upper 32-bits of MSR value.
4343 Described by the type MSR_IA32_MCG_EXT_CTL_REGISTER.
4345 <b>Example usage</b>
4347 MSR_IA32_MCG_EXT_CTL_REGISTER Msr;
4349 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_MCG_EXT_CTL);
4350 AsmWriteMsr64 (MSR_IA32_MCG_EXT_CTL, Msr.Uint64);
4352 @note MSR_IA32_MCG_EXT_CTL is defined as IA32_MCG_EXT_CTL in SDM.
4354 #define MSR_IA32_MCG_EXT_CTL 0x000004D0
4357 MSR information returned for MSR index #MSR_IA32_MCG_EXT_CTL
4361 /// Individual bit fields
4365 /// [Bit 0] LMCE_EN.
4368 UINT32 Reserved1
:31;
4369 UINT32 Reserved2
:32;
4372 /// All bit fields as a 32-bit value
4376 /// All bit fields as a 64-bit value
4379 } MSR_IA32_MCG_EXT_CTL_REGISTER
;
4383 Status and SVN Threshold of SGX Support for ACM (RO). If CPUID.(EAX=07H,
4384 ECX=0H): EBX[2] = 1.
4386 @param ECX MSR_IA32_SGX_SVN_STATUS (0x00000500)
4387 @param EAX Lower 32-bits of MSR value.
4388 Described by the type MSR_IA32_SGX_SVN_STATUS_REGISTER.
4389 @param EDX Upper 32-bits of MSR value.
4390 Described by the type MSR_IA32_SGX_SVN_STATUS_REGISTER.
4392 <b>Example usage</b>
4394 MSR_IA32_SGX_SVN_STATUS_REGISTER Msr;
4396 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_SGX_SVN_STATUS);
4398 @note MSR_IA32_SGX_SVN_STATUS is defined as IA32_SGX_SVN_STATUS in SDM.
4400 #define MSR_IA32_SGX_SVN_STATUS 0x00000500
4403 MSR information returned for MSR index #MSR_IA32_SGX_SVN_STATUS
4407 /// Individual bit fields
4411 /// [Bit 0] Lock. See Section 41.11.3, "Interactions with Authenticated
4412 /// Code Modules (ACMs)".
4415 UINT32 Reserved1
:15;
4417 /// [Bits 23:16] SGX_SVN_SINIT. See Section 41.11.3, "Interactions with
4418 /// Authenticated Code Modules (ACMs)".
4420 UINT32 SGX_SVN_SINIT
:8;
4422 UINT32 Reserved3
:32;
4425 /// All bit fields as a 32-bit value
4429 /// All bit fields as a 64-bit value
4432 } MSR_IA32_SGX_SVN_STATUS_REGISTER
;
4436 Trace Output Base Register (R/W). If ((CPUID.(EAX=07H, ECX=0):EBX[25] = 1)
4437 && ( (CPUID.(EAX=14H,ECX=0): ECX[0] = 1) (CPUID.(EAX=14H,ECX=0): ECX[2] = 1)
4440 @param ECX MSR_IA32_RTIT_OUTPUT_BASE (0x00000560)
4441 @param EAX Lower 32-bits of MSR value.
4442 Described by the type MSR_IA32_RTIT_OUTPUT_BASE_REGISTER.
4443 @param EDX Upper 32-bits of MSR value.
4444 Described by the type MSR_IA32_RTIT_OUTPUT_BASE_REGISTER.
4446 <b>Example usage</b>
4448 MSR_IA32_RTIT_OUTPUT_BASE_REGISTER Msr;
4450 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_OUTPUT_BASE);
4451 AsmWriteMsr64 (MSR_IA32_RTIT_OUTPUT_BASE, Msr.Uint64);
4453 @note MSR_IA32_RTIT_OUTPUT_BASE is defined as IA32_RTIT_OUTPUT_BASE in SDM.
4455 #define MSR_IA32_RTIT_OUTPUT_BASE 0x00000560
4458 MSR information returned for MSR index #MSR_IA32_RTIT_OUTPUT_BASE
4462 /// Individual bit fields
4467 /// [Bits 31:7] Base physical address.
4471 /// [Bits 63:32] Base physical address.
4476 /// All bit fields as a 64-bit value
4479 } MSR_IA32_RTIT_OUTPUT_BASE_REGISTER
;
4483 Trace Output Mask Pointers Register (R/W). If ((CPUID.(EAX=07H,
4484 ECX=0):EBX[25] = 1) && ( (CPUID.(EAX=14H,ECX=0): ECX[0] = 1)
4485 (CPUID.(EAX=14H,ECX=0): ECX[2] = 1) ) ).
4487 @param ECX MSR_IA32_RTIT_OUTPUT_MASK_PTRS (0x00000561)
4488 @param EAX Lower 32-bits of MSR value.
4489 Described by the type MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER.
4490 @param EDX Upper 32-bits of MSR value.
4491 Described by the type MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER.
4493 <b>Example usage</b>
4495 MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER Msr;
4497 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_OUTPUT_MASK_PTRS);
4498 AsmWriteMsr64 (MSR_IA32_RTIT_OUTPUT_MASK_PTRS, Msr.Uint64);
4500 @note MSR_IA32_RTIT_OUTPUT_MASK_PTRS is defined as IA32_RTIT_OUTPUT_MASK_PTRS in SDM.
4502 #define MSR_IA32_RTIT_OUTPUT_MASK_PTRS 0x00000561
4505 MSR information returned for MSR index #MSR_IA32_RTIT_OUTPUT_MASK_PTRS
4509 /// Individual bit fields
4514 /// [Bits 31:7] MaskOrTableOffset.
4516 UINT32 MaskOrTableOffset
:25;
4518 /// [Bits 63:32] Output Offset.
4520 UINT32 OutputOffset
:32;
4523 /// All bit fields as a 64-bit value
4526 } MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER
;
4529 Format of ToPA table entries.
4533 /// Individual bit fields
4537 /// [Bit 0] END. See Section 35.2.6.2, "Table of Physical Addresses (ToPA)".
4542 /// [Bit 2] INT. See Section 35.2.6.2, "Table of Physical Addresses (ToPA)".
4547 /// [Bit 4] STOP. See Section 35.2.6.2, "Table of Physical Addresses (ToPA)".
4552 /// [Bit 6:9] Indicates the size of the associated output region. See Section
4553 /// 35.2.6.2, "Table of Physical Addresses (ToPA)".
4558 /// [Bit 12:31] Output Region Base Physical Address low part.
4559 /// [Bit 12:31] Output Region Base Physical Address [12:63] value to match.
4560 /// ATTENTION: The size of the address field is determined by the processor's
4561 /// physical-address width (MAXPHYADDR) in bits, as reported in
4562 /// CPUID.80000008H:EAX[7:0]. the above part of address reserved.
4563 /// True address field is [12:MAXPHYADDR-1], [MAXPHYADDR:63] is reserved part.
4564 /// Detail see Section 35.2.6.2, "Table of Physical Addresses (ToPA)".
4568 /// [Bit 32:63] Output Region Base Physical Address high part.
4569 /// [Bit 32:63] Output Region Base Physical Address [12:63] value to match.
4570 /// ATTENTION: The size of the address field is determined by the processor's
4571 /// physical-address width (MAXPHYADDR) in bits, as reported in
4572 /// CPUID.80000008H:EAX[7:0]. the above part of address reserved.
4573 /// True address field is [12:MAXPHYADDR-1], [MAXPHYADDR:63] is reserved part.
4574 /// Detail see Section 35.2.6.2, "Table of Physical Addresses (ToPA)".
4579 /// All bit fields as a 64-bit value
4582 } RTIT_TOPA_TABLE_ENTRY
;
4585 /// The size of the associated output region usd by Topa.
4588 RtitTopaMemorySize4K
= 0,
4589 RtitTopaMemorySize8K
,
4590 RtitTopaMemorySize16K
,
4591 RtitTopaMemorySize32K
,
4592 RtitTopaMemorySize64K
,
4593 RtitTopaMemorySize128K
,
4594 RtitTopaMemorySize256K
,
4595 RtitTopaMemorySize512K
,
4596 RtitTopaMemorySize1M
,
4597 RtitTopaMemorySize2M
,
4598 RtitTopaMemorySize4M
,
4599 RtitTopaMemorySize8M
,
4600 RtitTopaMemorySize16M
,
4601 RtitTopaMemorySize32M
,
4602 RtitTopaMemorySize64M
,
4603 RtitTopaMemorySize128M
4604 } RTIT_TOPA_MEMORY_SIZE
;
4607 Trace Control Register (R/W). If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1).
4609 @param ECX MSR_IA32_RTIT_CTL (0x00000570)
4610 @param EAX Lower 32-bits of MSR value.
4611 Described by the type MSR_IA32_RTIT_CTL_REGISTER.
4612 @param EDX Upper 32-bits of MSR value.
4613 Described by the type MSR_IA32_RTIT_CTL_REGISTER.
4615 <b>Example usage</b>
4617 MSR_IA32_RTIT_CTL_REGISTER Msr;
4619 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_CTL);
4620 AsmWriteMsr64 (MSR_IA32_RTIT_CTL, Msr.Uint64);
4622 @note MSR_IA32_RTIT_CTL is defined as IA32_RTIT_CTL in SDM.
4624 #define MSR_IA32_RTIT_CTL 0x00000570
4627 MSR information returned for MSR index #MSR_IA32_RTIT_CTL
4631 /// Individual bit fields
4635 /// [Bit 0] TraceEn.
4639 /// [Bit 1] CYCEn. If (CPUID.(EAX=07H, ECX=0):EBX[1] = 1).
4652 /// [Bit 6] FabricEn. If (CPUID.(EAX=07H, ECX=0):ECX[3] = 1).
4656 /// [Bit 7] CR3 filter.
4664 /// [Bit 9] MTCEn. If (CPUID.(EAX=07H, ECX=0):EBX[3] = 1).
4672 /// [Bit 11] DisRETC.
4677 /// [Bit 13] BranchEn.
4681 /// [Bits 17:14] MTCFreq. If (CPUID.(EAX=07H, ECX=0):EBX[3] = 1).
4686 /// [Bits 22:19] CYCThresh. If (CPUID.(EAX=07H, ECX=0):EBX[1] = 1).
4691 /// [Bits 27:24] PSBFreq. If (CPUID.(EAX=07H, ECX=0):EBX[1] = 1).
4696 /// [Bits 35:32] ADDR0_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 0).
4700 /// [Bits 39:36] ADDR1_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 1).
4704 /// [Bits 43:40] ADDR2_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 2).
4708 /// [Bits 47:44] ADDR3_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 3).
4711 UINT32 Reserved6
:16;
4714 /// All bit fields as a 64-bit value
4717 } MSR_IA32_RTIT_CTL_REGISTER
;
4721 Tracing Status Register (R/W). If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1).
4723 @param ECX MSR_IA32_RTIT_STATUS (0x00000571)
4724 @param EAX Lower 32-bits of MSR value.
4725 Described by the type MSR_IA32_RTIT_STATUS_REGISTER.
4726 @param EDX Upper 32-bits of MSR value.
4727 Described by the type MSR_IA32_RTIT_STATUS_REGISTER.
4729 <b>Example usage</b>
4731 MSR_IA32_RTIT_STATUS_REGISTER Msr;
4733 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_STATUS);
4734 AsmWriteMsr64 (MSR_IA32_RTIT_STATUS, Msr.Uint64);
4736 @note MSR_IA32_RTIT_STATUS is defined as IA32_RTIT_STATUS in SDM.
4738 #define MSR_IA32_RTIT_STATUS 0x00000571
4741 MSR information returned for MSR index #MSR_IA32_RTIT_STATUS
4745 /// Individual bit fields
4749 /// [Bit 0] FilterEn, (writes ignored).
4750 /// If (CPUID.(EAX=07H, ECX=0):EBX[2] = 1).
4754 /// [Bit 1] ContexEn, (writes ignored).
4758 /// [Bit 2] TriggerEn, (writes ignored).
4767 /// [Bit 5] Stopped.
4770 UINT32 Reserved2
:26;
4772 /// [Bits 48:32] PacketByteCnt. If (CPUID.(EAX=07H, ECX=0):EBX[1] > 3).
4774 UINT32 PacketByteCnt
:17;
4775 UINT32 Reserved3
:15;
4778 /// All bit fields as a 64-bit value
4781 } MSR_IA32_RTIT_STATUS_REGISTER
;
4785 Trace Filter CR3 Match Register (R/W).
4786 If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1).
4788 @param ECX MSR_IA32_RTIT_CR3_MATCH (0x00000572)
4789 @param EAX Lower 32-bits of MSR value.
4790 Described by the type MSR_IA32_RTIT_CR3_MATCH_REGISTER.
4791 @param EDX Upper 32-bits of MSR value.
4792 Described by the type MSR_IA32_RTIT_CR3_MATCH_REGISTER.
4794 <b>Example usage</b>
4796 MSR_IA32_RTIT_CR3_MATCH_REGISTER Msr;
4798 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_CR3_MATCH);
4799 AsmWriteMsr64 (MSR_IA32_RTIT_CR3_MATCH, Msr.Uint64);
4801 @note MSR_IA32_RTIT_CR3_MATCH is defined as IA32_RTIT_CR3_MATCH in SDM.
4803 #define MSR_IA32_RTIT_CR3_MATCH 0x00000572
4806 MSR information returned for MSR index #MSR_IA32_RTIT_CR3_MATCH
4810 /// Individual bit fields
4815 /// [Bits 31:5] CR3[63:5] value to match.
4819 /// [Bits 63:32] CR3[63:5] value to match.
4824 /// All bit fields as a 64-bit value
4827 } MSR_IA32_RTIT_CR3_MATCH_REGISTER
;
4831 Region n Start Address (R/W). If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > n).
4833 @param ECX MSR_IA32_RTIT_ADDRn_A
4834 @param EAX Lower 32-bits of MSR value.
4835 Described by the type MSR_IA32_RTIT_ADDR_REGISTER.
4836 @param EDX Upper 32-bits of MSR value.
4837 Described by the type MSR_IA32_RTIT_ADDR_REGISTER.
4839 <b>Example usage</b>
4841 MSR_IA32_RTIT_ADDR_REGISTER Msr;
4843 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_ADDR0_A);
4844 AsmWriteMsr64 (MSR_IA32_RTIT_ADDR0_A, Msr.Uint64);
4846 @note MSR_IA32_RTIT_ADDR0_A is defined as IA32_RTIT_ADDR0_A in SDM.
4847 MSR_IA32_RTIT_ADDR1_A is defined as IA32_RTIT_ADDR1_A in SDM.
4848 MSR_IA32_RTIT_ADDR2_A is defined as IA32_RTIT_ADDR2_A in SDM.
4849 MSR_IA32_RTIT_ADDR3_A is defined as IA32_RTIT_ADDR3_A in SDM.
4852 #define MSR_IA32_RTIT_ADDR0_A 0x00000580
4853 #define MSR_IA32_RTIT_ADDR1_A 0x00000582
4854 #define MSR_IA32_RTIT_ADDR2_A 0x00000584
4855 #define MSR_IA32_RTIT_ADDR3_A 0x00000586
4860 Region n End Address (R/W). If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > n).
4862 @param ECX MSR_IA32_RTIT_ADDRn_B
4863 @param EAX Lower 32-bits of MSR value.
4864 Described by the type MSR_IA32_RTIT_ADDR_REGISTER.
4865 @param EDX Upper 32-bits of MSR value.
4866 Described by the type MSR_IA32_RTIT_ADDR_REGISTER.
4868 <b>Example usage</b>
4870 MSR_IA32_RTIT_ADDR_REGISTER Msr;
4872 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_RTIT_ADDR0_B);
4873 AsmWriteMsr64 (MSR_IA32_RTIT_ADDR0_B, Msr.Uint64);
4875 @note MSR_IA32_RTIT_ADDR0_B is defined as IA32_RTIT_ADDR0_B in SDM.
4876 MSR_IA32_RTIT_ADDR1_B is defined as IA32_RTIT_ADDR1_B in SDM.
4877 MSR_IA32_RTIT_ADDR2_B is defined as IA32_RTIT_ADDR2_B in SDM.
4878 MSR_IA32_RTIT_ADDR3_B is defined as IA32_RTIT_ADDR3_B in SDM.
4881 #define MSR_IA32_RTIT_ADDR0_B 0x00000581
4882 #define MSR_IA32_RTIT_ADDR1_B 0x00000583
4883 #define MSR_IA32_RTIT_ADDR2_B 0x00000585
4884 #define MSR_IA32_RTIT_ADDR3_B 0x00000587
4889 MSR information returned for MSR indexes
4890 #MSR_IA32_RTIT_ADDR0_A to #MSR_IA32_RTIT_ADDR3_A and
4891 #MSR_IA32_RTIT_ADDR0_B to #MSR_IA32_RTIT_ADDR3_B
4895 /// Individual bit fields
4899 /// [Bits 31:0] Virtual Address.
4901 UINT32 VirtualAddress
:32;
4903 /// [Bits 47:32] Virtual Address.
4905 UINT32 VirtualAddressHi
:16;
4907 /// [Bits 63:48] SignExt_VA.
4909 UINT32 SignExt_VA
:16;
4912 /// All bit fields as a 64-bit value
4915 } MSR_IA32_RTIT_ADDR_REGISTER
;
4919 DS Save Area (R/W) Points to the linear address of the first byte of the DS
4920 buffer management area, which is used to manage the BTS and PEBS buffers.
4921 See Section 18.6.3.4, "Debug Store (DS) Mechanism.". If(
4922 CPUID.01H:EDX.DS[21] = 1. The linear address of the first byte of the DS
4923 buffer management area, if IA-32e mode is active.
4925 @param ECX MSR_IA32_DS_AREA (0x00000600)
4926 @param EAX Lower 32-bits of MSR value.
4927 Described by the type MSR_IA32_DS_AREA_REGISTER.
4928 @param EDX Upper 32-bits of MSR value.
4929 Described by the type MSR_IA32_DS_AREA_REGISTER.
4931 <b>Example usage</b>
4935 Msr = AsmReadMsr64 (MSR_IA32_DS_AREA);
4936 AsmWriteMsr64 (MSR_IA32_DS_AREA, Msr);
4938 @note MSR_IA32_DS_AREA is defined as IA32_DS_AREA in SDM.
4940 #define MSR_IA32_DS_AREA 0x00000600
4944 TSC Target of Local APIC's TSC Deadline Mode (R/W). If CPUID.01H:ECX.[24] =
4947 @param ECX MSR_IA32_TSC_DEADLINE (0x000006E0)
4948 @param EAX Lower 32-bits of MSR value.
4949 @param EDX Upper 32-bits of MSR value.
4951 <b>Example usage</b>
4955 Msr = AsmReadMsr64 (MSR_IA32_TSC_DEADLINE);
4956 AsmWriteMsr64 (MSR_IA32_TSC_DEADLINE, Msr);
4958 @note MSR_IA32_TSC_DEADLINE is defined as IA32_TSC_DEADLINE in SDM.
4960 #define MSR_IA32_TSC_DEADLINE 0x000006E0
4964 Enable/disable HWP (R/W). If CPUID.06H:EAX.[7] = 1.
4966 @param ECX MSR_IA32_PM_ENABLE (0x00000770)
4967 @param EAX Lower 32-bits of MSR value.
4968 Described by the type MSR_IA32_PM_ENABLE_REGISTER.
4969 @param EDX Upper 32-bits of MSR value.
4970 Described by the type MSR_IA32_PM_ENABLE_REGISTER.
4972 <b>Example usage</b>
4974 MSR_IA32_PM_ENABLE_REGISTER Msr;
4976 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PM_ENABLE);
4977 AsmWriteMsr64 (MSR_IA32_PM_ENABLE, Msr.Uint64);
4979 @note MSR_IA32_PM_ENABLE is defined as IA32_PM_ENABLE in SDM.
4981 #define MSR_IA32_PM_ENABLE 0x00000770
4984 MSR information returned for MSR index #MSR_IA32_PM_ENABLE
4988 /// Individual bit fields
4992 /// [Bit 0] HWP_ENABLE (R/W1-Once). See Section 14.4.2, "Enabling HWP". If
4993 /// CPUID.06H:EAX.[7] = 1.
4995 UINT32 HWP_ENABLE
:1;
4996 UINT32 Reserved1
:31;
4997 UINT32 Reserved2
:32;
5000 /// All bit fields as a 32-bit value
5004 /// All bit fields as a 64-bit value
5007 } MSR_IA32_PM_ENABLE_REGISTER
;
5011 HWP Performance Range Enumeration (RO). If CPUID.06H:EAX.[7] = 1.
5013 @param ECX MSR_IA32_HWP_CAPABILITIES (0x00000771)
5014 @param EAX Lower 32-bits of MSR value.
5015 Described by the type MSR_IA32_HWP_CAPABILITIES_REGISTER.
5016 @param EDX Upper 32-bits of MSR value.
5017 Described by the type MSR_IA32_HWP_CAPABILITIES_REGISTER.
5019 <b>Example usage</b>
5021 MSR_IA32_HWP_CAPABILITIES_REGISTER Msr;
5023 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_CAPABILITIES);
5025 @note MSR_IA32_HWP_CAPABILITIES is defined as IA32_HWP_CAPABILITIES in SDM.
5027 #define MSR_IA32_HWP_CAPABILITIES 0x00000771
5030 MSR information returned for MSR index #MSR_IA32_HWP_CAPABILITIES
5034 /// Individual bit fields
5038 /// [Bits 7:0] Highest_Performance See Section 14.4.3, "HWP Performance
5039 /// Range and Dynamic Capabilities". If CPUID.06H:EAX.[7] = 1.
5041 UINT32 Highest_Performance
:8;
5043 /// [Bits 15:8] Guaranteed_Performance See Section 14.4.3, "HWP
5044 /// Performance Range and Dynamic Capabilities". If CPUID.06H:EAX.[7] = 1.
5046 UINT32 Guaranteed_Performance
:8;
5048 /// [Bits 23:16] Most_Efficient_Performance See Section 14.4.3, "HWP
5049 /// Performance Range and Dynamic Capabilities". If CPUID.06H:EAX.[7] = 1.
5051 UINT32 Most_Efficient_Performance
:8;
5053 /// [Bits 31:24] Lowest_Performance See Section 14.4.3, "HWP Performance
5054 /// Range and Dynamic Capabilities". If CPUID.06H:EAX.[7] = 1.
5056 UINT32 Lowest_Performance
:8;
5060 /// All bit fields as a 32-bit value
5064 /// All bit fields as a 64-bit value
5067 } MSR_IA32_HWP_CAPABILITIES_REGISTER
;
5071 Power Management Control Hints for All Logical Processors in a Package
5072 (R/W). If CPUID.06H:EAX.[11] = 1.
5074 @param ECX MSR_IA32_HWP_REQUEST_PKG (0x00000772)
5075 @param EAX Lower 32-bits of MSR value.
5076 Described by the type MSR_IA32_HWP_REQUEST_PKG_REGISTER.
5077 @param EDX Upper 32-bits of MSR value.
5078 Described by the type MSR_IA32_HWP_REQUEST_PKG_REGISTER.
5080 <b>Example usage</b>
5082 MSR_IA32_HWP_REQUEST_PKG_REGISTER Msr;
5084 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_REQUEST_PKG);
5085 AsmWriteMsr64 (MSR_IA32_HWP_REQUEST_PKG, Msr.Uint64);
5087 @note MSR_IA32_HWP_REQUEST_PKG is defined as IA32_HWP_REQUEST_PKG in SDM.
5089 #define MSR_IA32_HWP_REQUEST_PKG 0x00000772
5092 MSR information returned for MSR index #MSR_IA32_HWP_REQUEST_PKG
5096 /// Individual bit fields
5100 /// [Bits 7:0] Minimum_Performance See Section 14.4.4, "Managing HWP". If
5101 /// CPUID.06H:EAX.[11] = 1.
5103 UINT32 Minimum_Performance
:8;
5105 /// [Bits 15:8] Maximum_Performance See Section 14.4.4, "Managing HWP". If
5106 /// CPUID.06H:EAX.[11] = 1.
5108 UINT32 Maximum_Performance
:8;
5110 /// [Bits 23:16] Desired_Performance See Section 14.4.4, "Managing HWP".
5111 /// If CPUID.06H:EAX.[11] = 1.
5113 UINT32 Desired_Performance
:8;
5115 /// [Bits 31:24] Energy_Performance_Preference See Section 14.4.4,
5116 /// "Managing HWP". If CPUID.06H:EAX.[11] = 1 && CPUID.06H:EAX.[10] = 1.
5118 UINT32 Energy_Performance_Preference
:8;
5120 /// [Bits 41:32] Activity_Window See Section 14.4.4, "Managing HWP". If
5121 /// CPUID.06H:EAX.[11] = 1 && CPUID.06H:EAX.[9] = 1.
5123 UINT32 Activity_Window
:10;
5127 /// All bit fields as a 64-bit value
5130 } MSR_IA32_HWP_REQUEST_PKG_REGISTER
;
5134 Control HWP Native Interrupts (R/W). If CPUID.06H:EAX.[8] = 1.
5136 @param ECX MSR_IA32_HWP_INTERRUPT (0x00000773)
5137 @param EAX Lower 32-bits of MSR value.
5138 Described by the type MSR_IA32_HWP_INTERRUPT_REGISTER.
5139 @param EDX Upper 32-bits of MSR value.
5140 Described by the type MSR_IA32_HWP_INTERRUPT_REGISTER.
5142 <b>Example usage</b>
5144 MSR_IA32_HWP_INTERRUPT_REGISTER Msr;
5146 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_INTERRUPT);
5147 AsmWriteMsr64 (MSR_IA32_HWP_INTERRUPT, Msr.Uint64);
5149 @note MSR_IA32_HWP_INTERRUPT is defined as IA32_HWP_INTERRUPT in SDM.
5151 #define MSR_IA32_HWP_INTERRUPT 0x00000773
5154 MSR information returned for MSR index #MSR_IA32_HWP_INTERRUPT
5158 /// Individual bit fields
5162 /// [Bit 0] EN_Guaranteed_Performance_Change. See Section 14.4.6, "HWP
5163 /// Notifications". If CPUID.06H:EAX.[8] = 1.
5165 UINT32 EN_Guaranteed_Performance_Change
:1;
5167 /// [Bit 1] EN_Excursion_Minimum. See Section 14.4.6, "HWP Notifications".
5168 /// If CPUID.06H:EAX.[8] = 1.
5170 UINT32 EN_Excursion_Minimum
:1;
5171 UINT32 Reserved1
:30;
5172 UINT32 Reserved2
:32;
5175 /// All bit fields as a 32-bit value
5179 /// All bit fields as a 64-bit value
5182 } MSR_IA32_HWP_INTERRUPT_REGISTER
;
5186 Power Management Control Hints to a Logical Processor (R/W). If
5187 CPUID.06H:EAX.[7] = 1.
5189 @param ECX MSR_IA32_HWP_REQUEST (0x00000774)
5190 @param EAX Lower 32-bits of MSR value.
5191 Described by the type MSR_IA32_HWP_REQUEST_REGISTER.
5192 @param EDX Upper 32-bits of MSR value.
5193 Described by the type MSR_IA32_HWP_REQUEST_REGISTER.
5195 <b>Example usage</b>
5197 MSR_IA32_HWP_REQUEST_REGISTER Msr;
5199 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_REQUEST);
5200 AsmWriteMsr64 (MSR_IA32_HWP_REQUEST, Msr.Uint64);
5202 @note MSR_IA32_HWP_REQUEST is defined as IA32_HWP_REQUEST in SDM.
5204 #define MSR_IA32_HWP_REQUEST 0x00000774
5207 MSR information returned for MSR index #MSR_IA32_HWP_REQUEST
5211 /// Individual bit fields
5215 /// [Bits 7:0] Minimum_Performance See Section 14.4.4, "Managing HWP". If
5216 /// CPUID.06H:EAX.[7] = 1.
5218 UINT32 Minimum_Performance
:8;
5220 /// [Bits 15:8] Maximum_Performance See Section 14.4.4, "Managing HWP". If
5221 /// CPUID.06H:EAX.[7] = 1.
5223 UINT32 Maximum_Performance
:8;
5225 /// [Bits 23:16] Desired_Performance See Section 14.4.4, "Managing HWP".
5226 /// If CPUID.06H:EAX.[7] = 1.
5228 UINT32 Desired_Performance
:8;
5230 /// [Bits 31:24] Energy_Performance_Preference See Section 14.4.4,
5231 /// "Managing HWP". If CPUID.06H:EAX.[7] = 1 && CPUID.06H:EAX.[10] = 1.
5233 UINT32 Energy_Performance_Preference
:8;
5235 /// [Bits 41:32] Activity_Window See Section 14.4.4, "Managing HWP". If
5236 /// CPUID.06H:EAX.[7] = 1 && CPUID.06H:EAX.[9] = 1.
5238 UINT32 Activity_Window
:10;
5240 /// [Bit 42] Package_Control See Section 14.4.4, "Managing HWP". If
5241 /// CPUID.06H:EAX.[7] = 1 && CPUID.06H:EAX.[11] = 1.
5243 UINT32 Package_Control
:1;
5247 /// All bit fields as a 64-bit value
5250 } MSR_IA32_HWP_REQUEST_REGISTER
;
5254 Log bits indicating changes to Guaranteed & excursions to Minimum (R/W). If
5255 CPUID.06H:EAX.[7] = 1.
5257 @param ECX MSR_IA32_HWP_STATUS (0x00000777)
5258 @param EAX Lower 32-bits of MSR value.
5259 Described by the type MSR_IA32_HWP_STATUS_REGISTER.
5260 @param EDX Upper 32-bits of MSR value.
5261 Described by the type MSR_IA32_HWP_STATUS_REGISTER.
5263 <b>Example usage</b>
5265 MSR_IA32_HWP_STATUS_REGISTER Msr;
5267 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_HWP_STATUS);
5268 AsmWriteMsr64 (MSR_IA32_HWP_STATUS, Msr.Uint64);
5270 @note MSR_IA32_HWP_STATUS is defined as IA32_HWP_STATUS in SDM.
5272 #define MSR_IA32_HWP_STATUS 0x00000777
5275 MSR information returned for MSR index #MSR_IA32_HWP_STATUS
5279 /// Individual bit fields
5283 /// [Bit 0] Guaranteed_Performance_Change (R/WC0). See Section 14.4.5,
5284 /// "HWP Feedback". If CPUID.06H:EAX.[7] = 1.
5286 UINT32 Guaranteed_Performance_Change
:1;
5289 /// [Bit 2] Excursion_To_Minimum (R/WC0). See Section 14.4.5, "HWP
5290 /// Feedback". If CPUID.06H:EAX.[7] = 1.
5292 UINT32 Excursion_To_Minimum
:1;
5293 UINT32 Reserved2
:29;
5294 UINT32 Reserved3
:32;
5297 /// All bit fields as a 32-bit value
5301 /// All bit fields as a 64-bit value
5304 } MSR_IA32_HWP_STATUS_REGISTER
;
5308 x2APIC ID Register (R/O) See x2APIC Specification. If CPUID.01H:ECX[21] = 1
5309 && IA32_APIC_BASE.[10] = 1.
5311 @param ECX MSR_IA32_X2APIC_APICID (0x00000802)
5312 @param EAX Lower 32-bits of MSR value.
5313 @param EDX Upper 32-bits of MSR value.
5315 <b>Example usage</b>
5319 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_APICID);
5321 @note MSR_IA32_X2APIC_APICID is defined as IA32_X2APIC_APICID in SDM.
5323 #define MSR_IA32_X2APIC_APICID 0x00000802
5327 x2APIC Version Register (R/O). If CPUID.01H:ECX.[21] = 1 &&
5328 IA32_APIC_BASE.[10] = 1.
5330 @param ECX MSR_IA32_X2APIC_VERSION (0x00000803)
5331 @param EAX Lower 32-bits of MSR value.
5332 @param EDX Upper 32-bits of MSR value.
5334 <b>Example usage</b>
5338 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_VERSION);
5340 @note MSR_IA32_X2APIC_VERSION is defined as IA32_X2APIC_VERSION in SDM.
5342 #define MSR_IA32_X2APIC_VERSION 0x00000803
5346 x2APIC Task Priority Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
5347 IA32_APIC_BASE.[10] = 1.
5349 @param ECX MSR_IA32_X2APIC_TPR (0x00000808)
5350 @param EAX Lower 32-bits of MSR value.
5351 @param EDX Upper 32-bits of MSR value.
5353 <b>Example usage</b>
5357 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_TPR);
5358 AsmWriteMsr64 (MSR_IA32_X2APIC_TPR, Msr);
5360 @note MSR_IA32_X2APIC_TPR is defined as IA32_X2APIC_TPR in SDM.
5362 #define MSR_IA32_X2APIC_TPR 0x00000808
5366 x2APIC Processor Priority Register (R/O). If CPUID.01H:ECX.[21] = 1 &&
5367 IA32_APIC_BASE.[10] = 1.
5369 @param ECX MSR_IA32_X2APIC_PPR (0x0000080A)
5370 @param EAX Lower 32-bits of MSR value.
5371 @param EDX Upper 32-bits of MSR value.
5373 <b>Example usage</b>
5377 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_PPR);
5379 @note MSR_IA32_X2APIC_PPR is defined as IA32_X2APIC_PPR in SDM.
5381 #define MSR_IA32_X2APIC_PPR 0x0000080A
5385 x2APIC EOI Register (W/O). If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10]
5388 @param ECX MSR_IA32_X2APIC_EOI (0x0000080B)
5389 @param EAX Lower 32-bits of MSR value.
5390 @param EDX Upper 32-bits of MSR value.
5392 <b>Example usage</b>
5397 AsmWriteMsr64 (MSR_IA32_X2APIC_EOI, Msr);
5399 @note MSR_IA32_X2APIC_EOI is defined as IA32_X2APIC_EOI in SDM.
5401 #define MSR_IA32_X2APIC_EOI 0x0000080B
5405 x2APIC Logical Destination Register (R/O). If CPUID.01H:ECX.[21] = 1 &&
5406 IA32_APIC_BASE.[10] = 1.
5408 @param ECX MSR_IA32_X2APIC_LDR (0x0000080D)
5409 @param EAX Lower 32-bits of MSR value.
5410 @param EDX Upper 32-bits of MSR value.
5412 <b>Example usage</b>
5416 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LDR);
5418 @note MSR_IA32_X2APIC_LDR is defined as IA32_X2APIC_LDR in SDM.
5420 #define MSR_IA32_X2APIC_LDR 0x0000080D
5424 x2APIC Spurious Interrupt Vector Register (R/W). If CPUID.01H:ECX.[21] = 1
5425 && IA32_APIC_BASE.[10] = 1.
5427 @param ECX MSR_IA32_X2APIC_SIVR (0x0000080F)
5428 @param EAX Lower 32-bits of MSR value.
5429 @param EDX Upper 32-bits of MSR value.
5431 <b>Example usage</b>
5435 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_SIVR);
5436 AsmWriteMsr64 (MSR_IA32_X2APIC_SIVR, Msr);
5438 @note MSR_IA32_X2APIC_SIVR is defined as IA32_X2APIC_SIVR in SDM.
5440 #define MSR_IA32_X2APIC_SIVR 0x0000080F
5444 x2APIC In-Service Register Bits (n * 32 + 31):(n * 32) (R/O).
5445 If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.
5447 @param ECX MSR_IA32_X2APIC_ISRn
5448 @param EAX Lower 32-bits of MSR value.
5449 @param EDX Upper 32-bits of MSR value.
5451 <b>Example usage</b>
5455 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_ISR0);
5457 @note MSR_IA32_X2APIC_ISR0 is defined as IA32_X2APIC_ISR0 in SDM.
5458 MSR_IA32_X2APIC_ISR1 is defined as IA32_X2APIC_ISR1 in SDM.
5459 MSR_IA32_X2APIC_ISR2 is defined as IA32_X2APIC_ISR2 in SDM.
5460 MSR_IA32_X2APIC_ISR3 is defined as IA32_X2APIC_ISR3 in SDM.
5461 MSR_IA32_X2APIC_ISR4 is defined as IA32_X2APIC_ISR4 in SDM.
5462 MSR_IA32_X2APIC_ISR5 is defined as IA32_X2APIC_ISR5 in SDM.
5463 MSR_IA32_X2APIC_ISR6 is defined as IA32_X2APIC_ISR6 in SDM.
5464 MSR_IA32_X2APIC_ISR7 is defined as IA32_X2APIC_ISR7 in SDM.
5467 #define MSR_IA32_X2APIC_ISR0 0x00000810
5468 #define MSR_IA32_X2APIC_ISR1 0x00000811
5469 #define MSR_IA32_X2APIC_ISR2 0x00000812
5470 #define MSR_IA32_X2APIC_ISR3 0x00000813
5471 #define MSR_IA32_X2APIC_ISR4 0x00000814
5472 #define MSR_IA32_X2APIC_ISR5 0x00000815
5473 #define MSR_IA32_X2APIC_ISR6 0x00000816
5474 #define MSR_IA32_X2APIC_ISR7 0x00000817
5479 x2APIC Trigger Mode Register Bits (n * 32 + ):(n * 32) (R/O).
5480 If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.
5482 @param ECX MSR_IA32_X2APIC_TMRn
5483 @param EAX Lower 32-bits of MSR value.
5484 @param EDX Upper 32-bits of MSR value.
5486 <b>Example usage</b>
5490 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_TMR0);
5492 @note MSR_IA32_X2APIC_TMR0 is defined as IA32_X2APIC_TMR0 in SDM.
5493 MSR_IA32_X2APIC_TMR1 is defined as IA32_X2APIC_TMR1 in SDM.
5494 MSR_IA32_X2APIC_TMR2 is defined as IA32_X2APIC_TMR2 in SDM.
5495 MSR_IA32_X2APIC_TMR3 is defined as IA32_X2APIC_TMR3 in SDM.
5496 MSR_IA32_X2APIC_TMR4 is defined as IA32_X2APIC_TMR4 in SDM.
5497 MSR_IA32_X2APIC_TMR5 is defined as IA32_X2APIC_TMR5 in SDM.
5498 MSR_IA32_X2APIC_TMR6 is defined as IA32_X2APIC_TMR6 in SDM.
5499 MSR_IA32_X2APIC_TMR7 is defined as IA32_X2APIC_TMR7 in SDM.
5502 #define MSR_IA32_X2APIC_TMR0 0x00000818
5503 #define MSR_IA32_X2APIC_TMR1 0x00000819
5504 #define MSR_IA32_X2APIC_TMR2 0x0000081A
5505 #define MSR_IA32_X2APIC_TMR3 0x0000081B
5506 #define MSR_IA32_X2APIC_TMR4 0x0000081C
5507 #define MSR_IA32_X2APIC_TMR5 0x0000081D
5508 #define MSR_IA32_X2APIC_TMR6 0x0000081E
5509 #define MSR_IA32_X2APIC_TMR7 0x0000081F
5514 x2APIC Interrupt Request Register Bits (n* 32 + 31):(n * 32) (R/O).
5515 If CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.
5517 @param ECX MSR_IA32_X2APIC_IRRn
5518 @param EAX Lower 32-bits of MSR value.
5519 @param EDX Upper 32-bits of MSR value.
5521 <b>Example usage</b>
5525 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_IRR0);
5527 @note MSR_IA32_X2APIC_IRR0 is defined as IA32_X2APIC_IRR0 in SDM.
5528 MSR_IA32_X2APIC_IRR1 is defined as IA32_X2APIC_IRR1 in SDM.
5529 MSR_IA32_X2APIC_IRR2 is defined as IA32_X2APIC_IRR2 in SDM.
5530 MSR_IA32_X2APIC_IRR3 is defined as IA32_X2APIC_IRR3 in SDM.
5531 MSR_IA32_X2APIC_IRR4 is defined as IA32_X2APIC_IRR4 in SDM.
5532 MSR_IA32_X2APIC_IRR5 is defined as IA32_X2APIC_IRR5 in SDM.
5533 MSR_IA32_X2APIC_IRR6 is defined as IA32_X2APIC_IRR6 in SDM.
5534 MSR_IA32_X2APIC_IRR7 is defined as IA32_X2APIC_IRR7 in SDM.
5537 #define MSR_IA32_X2APIC_IRR0 0x00000820
5538 #define MSR_IA32_X2APIC_IRR1 0x00000821
5539 #define MSR_IA32_X2APIC_IRR2 0x00000822
5540 #define MSR_IA32_X2APIC_IRR3 0x00000823
5541 #define MSR_IA32_X2APIC_IRR4 0x00000824
5542 #define MSR_IA32_X2APIC_IRR5 0x00000825
5543 #define MSR_IA32_X2APIC_IRR6 0x00000826
5544 #define MSR_IA32_X2APIC_IRR7 0x00000827
5549 x2APIC Error Status Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
5550 IA32_APIC_BASE.[10] = 1.
5552 @param ECX MSR_IA32_X2APIC_ESR (0x00000828)
5553 @param EAX Lower 32-bits of MSR value.
5554 @param EDX Upper 32-bits of MSR value.
5556 <b>Example usage</b>
5560 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_ESR);
5561 AsmWriteMsr64 (MSR_IA32_X2APIC_ESR, Msr);
5563 @note MSR_IA32_X2APIC_ESR is defined as IA32_X2APIC_ESR in SDM.
5565 #define MSR_IA32_X2APIC_ESR 0x00000828
5569 x2APIC LVT Corrected Machine Check Interrupt Register (R/W). If
5570 CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.
5572 @param ECX MSR_IA32_X2APIC_LVT_CMCI (0x0000082F)
5573 @param EAX Lower 32-bits of MSR value.
5574 @param EDX Upper 32-bits of MSR value.
5576 <b>Example usage</b>
5580 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_CMCI);
5581 AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_CMCI, Msr);
5583 @note MSR_IA32_X2APIC_LVT_CMCI is defined as IA32_X2APIC_LVT_CMCI in SDM.
5585 #define MSR_IA32_X2APIC_LVT_CMCI 0x0000082F
5589 x2APIC Interrupt Command Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
5590 IA32_APIC_BASE.[10] = 1.
5592 @param ECX MSR_IA32_X2APIC_ICR (0x00000830)
5593 @param EAX Lower 32-bits of MSR value.
5594 @param EDX Upper 32-bits of MSR value.
5596 <b>Example usage</b>
5600 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_ICR);
5601 AsmWriteMsr64 (MSR_IA32_X2APIC_ICR, Msr);
5603 @note MSR_IA32_X2APIC_ICR is defined as IA32_X2APIC_ICR in SDM.
5605 #define MSR_IA32_X2APIC_ICR 0x00000830
5609 x2APIC LVT Timer Interrupt Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
5610 IA32_APIC_BASE.[10] = 1.
5612 @param ECX MSR_IA32_X2APIC_LVT_TIMER (0x00000832)
5613 @param EAX Lower 32-bits of MSR value.
5614 @param EDX Upper 32-bits of MSR value.
5616 <b>Example usage</b>
5620 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_TIMER);
5621 AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_TIMER, Msr);
5623 @note MSR_IA32_X2APIC_LVT_TIMER is defined as IA32_X2APIC_LVT_TIMER in SDM.
5625 #define MSR_IA32_X2APIC_LVT_TIMER 0x00000832
5629 x2APIC LVT Thermal Sensor Interrupt Register (R/W). If CPUID.01H:ECX.[21] =
5630 1 && IA32_APIC_BASE.[10] = 1.
5632 @param ECX MSR_IA32_X2APIC_LVT_THERMAL (0x00000833)
5633 @param EAX Lower 32-bits of MSR value.
5634 @param EDX Upper 32-bits of MSR value.
5636 <b>Example usage</b>
5640 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_THERMAL);
5641 AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_THERMAL, Msr);
5643 @note MSR_IA32_X2APIC_LVT_THERMAL is defined as IA32_X2APIC_LVT_THERMAL in SDM.
5645 #define MSR_IA32_X2APIC_LVT_THERMAL 0x00000833
5649 x2APIC LVT Performance Monitor Interrupt Register (R/W). If
5650 CPUID.01H:ECX.[21] = 1 && IA32_APIC_BASE.[10] = 1.
5652 @param ECX MSR_IA32_X2APIC_LVT_PMI (0x00000834)
5653 @param EAX Lower 32-bits of MSR value.
5654 @param EDX Upper 32-bits of MSR value.
5656 <b>Example usage</b>
5660 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_PMI);
5661 AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_PMI, Msr);
5663 @note MSR_IA32_X2APIC_LVT_PMI is defined as IA32_X2APIC_LVT_PMI in SDM.
5665 #define MSR_IA32_X2APIC_LVT_PMI 0x00000834
5669 x2APIC LVT LINT0 Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
5670 IA32_APIC_BASE.[10] = 1.
5672 @param ECX MSR_IA32_X2APIC_LVT_LINT0 (0x00000835)
5673 @param EAX Lower 32-bits of MSR value.
5674 @param EDX Upper 32-bits of MSR value.
5676 <b>Example usage</b>
5680 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_LINT0);
5681 AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_LINT0, Msr);
5683 @note MSR_IA32_X2APIC_LVT_LINT0 is defined as IA32_X2APIC_LVT_LINT0 in SDM.
5685 #define MSR_IA32_X2APIC_LVT_LINT0 0x00000835
5689 x2APIC LVT LINT1 Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
5690 IA32_APIC_BASE.[10] = 1.
5692 @param ECX MSR_IA32_X2APIC_LVT_LINT1 (0x00000836)
5693 @param EAX Lower 32-bits of MSR value.
5694 @param EDX Upper 32-bits of MSR value.
5696 <b>Example usage</b>
5700 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_LINT1);
5701 AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_LINT1, Msr);
5703 @note MSR_IA32_X2APIC_LVT_LINT1 is defined as IA32_X2APIC_LVT_LINT1 in SDM.
5705 #define MSR_IA32_X2APIC_LVT_LINT1 0x00000836
5709 x2APIC LVT Error Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
5710 IA32_APIC_BASE.[10] = 1.
5712 @param ECX MSR_IA32_X2APIC_LVT_ERROR (0x00000837)
5713 @param EAX Lower 32-bits of MSR value.
5714 @param EDX Upper 32-bits of MSR value.
5716 <b>Example usage</b>
5720 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_LVT_ERROR);
5721 AsmWriteMsr64 (MSR_IA32_X2APIC_LVT_ERROR, Msr);
5723 @note MSR_IA32_X2APIC_LVT_ERROR is defined as IA32_X2APIC_LVT_ERROR in SDM.
5725 #define MSR_IA32_X2APIC_LVT_ERROR 0x00000837
5729 x2APIC Initial Count Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
5730 IA32_APIC_BASE.[10] = 1.
5732 @param ECX MSR_IA32_X2APIC_INIT_COUNT (0x00000838)
5733 @param EAX Lower 32-bits of MSR value.
5734 @param EDX Upper 32-bits of MSR value.
5736 <b>Example usage</b>
5740 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_INIT_COUNT);
5741 AsmWriteMsr64 (MSR_IA32_X2APIC_INIT_COUNT, Msr);
5743 @note MSR_IA32_X2APIC_INIT_COUNT is defined as IA32_X2APIC_INIT_COUNT in SDM.
5745 #define MSR_IA32_X2APIC_INIT_COUNT 0x00000838
5749 x2APIC Current Count Register (R/O). If CPUID.01H:ECX.[21] = 1 &&
5750 IA32_APIC_BASE.[10] = 1.
5752 @param ECX MSR_IA32_X2APIC_CUR_COUNT (0x00000839)
5753 @param EAX Lower 32-bits of MSR value.
5754 @param EDX Upper 32-bits of MSR value.
5756 <b>Example usage</b>
5760 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_CUR_COUNT);
5762 @note MSR_IA32_X2APIC_CUR_COUNT is defined as IA32_X2APIC_CUR_COUNT in SDM.
5764 #define MSR_IA32_X2APIC_CUR_COUNT 0x00000839
5768 x2APIC Divide Configuration Register (R/W). If CPUID.01H:ECX.[21] = 1 &&
5769 IA32_APIC_BASE.[10] = 1.
5771 @param ECX MSR_IA32_X2APIC_DIV_CONF (0x0000083E)
5772 @param EAX Lower 32-bits of MSR value.
5773 @param EDX Upper 32-bits of MSR value.
5775 <b>Example usage</b>
5779 Msr = AsmReadMsr64 (MSR_IA32_X2APIC_DIV_CONF);
5780 AsmWriteMsr64 (MSR_IA32_X2APIC_DIV_CONF, Msr);
5782 @note MSR_IA32_X2APIC_DIV_CONF is defined as IA32_X2APIC_DIV_CONF in SDM.
5784 #define MSR_IA32_X2APIC_DIV_CONF 0x0000083E
5788 x2APIC Self IPI Register (W/O). If CPUID.01H:ECX.[21] = 1 &&
5789 IA32_APIC_BASE.[10] = 1.
5791 @param ECX MSR_IA32_X2APIC_SELF_IPI (0x0000083F)
5792 @param EAX Lower 32-bits of MSR value.
5793 @param EDX Upper 32-bits of MSR value.
5795 <b>Example usage</b>
5800 AsmWriteMsr64 (MSR_IA32_X2APIC_SELF_IPI, Msr);
5802 @note MSR_IA32_X2APIC_SELF_IPI is defined as IA32_X2APIC_SELF_IPI in SDM.
5804 #define MSR_IA32_X2APIC_SELF_IPI 0x0000083F
5808 Silicon Debug Feature Control (R/W). If CPUID.01H:ECX.[11] = 1.
5810 @param ECX MSR_IA32_DEBUG_INTERFACE (0x00000C80)
5811 @param EAX Lower 32-bits of MSR value.
5812 Described by the type MSR_IA32_DEBUG_INTERFACE_REGISTER.
5813 @param EDX Upper 32-bits of MSR value.
5814 Described by the type MSR_IA32_DEBUG_INTERFACE_REGISTER.
5816 <b>Example usage</b>
5818 MSR_IA32_DEBUG_INTERFACE_REGISTER Msr;
5820 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_DEBUG_INTERFACE);
5821 AsmWriteMsr64 (MSR_IA32_DEBUG_INTERFACE, Msr.Uint64);
5823 @note MSR_IA32_DEBUG_INTERFACE is defined as IA32_DEBUG_INTERFACE in SDM.
5825 #define MSR_IA32_DEBUG_INTERFACE 0x00000C80
5828 MSR information returned for MSR index #MSR_IA32_DEBUG_INTERFACE
5832 /// Individual bit fields
5836 /// [Bit 0] Enable (R/W) BIOS set 1 to enable Silicon debug features.
5837 /// Default is 0. If CPUID.01H:ECX.[11] = 1.
5840 UINT32 Reserved1
:29;
5842 /// [Bit 30] Lock (R/W): If 1, locks any further change to the MSR. The
5843 /// lock bit is set automatically on the first SMI assertion even if not
5844 /// explicitly set by BIOS. Default is 0. If CPUID.01H:ECX.[11] = 1.
5848 /// [Bit 31] Debug Occurred (R/O): This "sticky bit" is set by hardware to
5849 /// indicate the status of bit 0. Default is 0. If CPUID.01H:ECX.[11] = 1.
5851 UINT32 DebugOccurred
:1;
5852 UINT32 Reserved2
:32;
5855 /// All bit fields as a 32-bit value
5859 /// All bit fields as a 64-bit value
5862 } MSR_IA32_DEBUG_INTERFACE_REGISTER
;
5866 L3 QOS Configuration (R/W). If ( CPUID.(EAX=10H, ECX=1):ECX.[2] = 1 ).
5868 @param ECX MSR_IA32_L3_QOS_CFG (0x00000C81)
5869 @param EAX Lower 32-bits of MSR value.
5870 Described by the type MSR_IA32_L3_QOS_CFG_REGISTER.
5871 @param EDX Upper 32-bits of MSR value.
5872 Described by the type MSR_IA32_L3_QOS_CFG_REGISTER.
5874 <b>Example usage</b>
5876 MSR_IA32_L3_QOS_CFG_REGISTER Msr;
5878 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_L3_QOS_CFG);
5879 AsmWriteMsr64 (MSR_IA32_L3_QOS_CFG, Msr.Uint64);
5881 @note MSR_IA32_L3_QOS_CFG is defined as IA32_L3_QOS_CFG in SDM.
5883 #define MSR_IA32_L3_QOS_CFG 0x00000C81
5886 MSR information returned for MSR index #MSR_IA32_L3_QOS_CFG
5890 /// Individual bit fields
5894 /// [Bit 0] Enable (R/W) Set 1 to enable L3 CAT masks and COS to operate
5895 /// in Code and Data Prioritization (CDP) mode.
5898 UINT32 Reserved1
:31;
5899 UINT32 Reserved2
:32;
5902 /// All bit fields as a 32-bit value
5906 /// All bit fields as a 64-bit value
5909 } MSR_IA32_L3_QOS_CFG_REGISTER
;
5913 Monitoring Event Select Register (R/W). If ( CPUID.(EAX=07H, ECX=0):EBX.[12]
5916 @param ECX MSR_IA32_QM_EVTSEL (0x00000C8D)
5917 @param EAX Lower 32-bits of MSR value.
5918 Described by the type MSR_IA32_QM_EVTSEL_REGISTER.
5919 @param EDX Upper 32-bits of MSR value.
5920 Described by the type MSR_IA32_QM_EVTSEL_REGISTER.
5922 <b>Example usage</b>
5924 MSR_IA32_QM_EVTSEL_REGISTER Msr;
5926 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_QM_EVTSEL);
5927 AsmWriteMsr64 (MSR_IA32_QM_EVTSEL, Msr.Uint64);
5929 @note MSR_IA32_QM_EVTSEL is defined as IA32_QM_EVTSEL in SDM.
5931 #define MSR_IA32_QM_EVTSEL 0x00000C8D
5934 MSR information returned for MSR index #MSR_IA32_QM_EVTSEL
5938 /// Individual bit fields
5942 /// [Bits 7:0] Event ID: ID of a supported monitoring event to report via
5948 /// [Bits 63:32] Resource Monitoring ID: ID for monitoring hardware to
5949 /// report monitored data via IA32_QM_CTR. N = Ceil (Log:sub:`2` (
5950 /// CPUID.(EAX= 0FH, ECX=0H).EBX[31:0] +1)).
5952 UINT32 ResourceMonitoringID
:32;
5955 /// All bit fields as a 64-bit value
5958 } MSR_IA32_QM_EVTSEL_REGISTER
;
5962 Monitoring Counter Register (R/O). If ( CPUID.(EAX=07H, ECX=0):EBX.[12] = 1
5965 @param ECX MSR_IA32_QM_CTR (0x00000C8E)
5966 @param EAX Lower 32-bits of MSR value.
5967 Described by the type MSR_IA32_QM_CTR_REGISTER.
5968 @param EDX Upper 32-bits of MSR value.
5969 Described by the type MSR_IA32_QM_CTR_REGISTER.
5971 <b>Example usage</b>
5973 MSR_IA32_QM_CTR_REGISTER Msr;
5975 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_QM_CTR);
5977 @note MSR_IA32_QM_CTR is defined as IA32_QM_CTR in SDM.
5979 #define MSR_IA32_QM_CTR 0x00000C8E
5982 MSR information returned for MSR index #MSR_IA32_QM_CTR
5986 /// Individual bit fields
5990 /// [Bits 31:0] Resource Monitored Data.
5992 UINT32 ResourceMonitoredData
:32;
5994 /// [Bits 61:32] Resource Monitored Data.
5996 UINT32 ResourceMonitoredDataHi
:30;
5998 /// [Bit 62] Unavailable: If 1, indicates data for this RMID is not
5999 /// available or not monitored for this resource or RMID.
6001 UINT32 Unavailable
:1;
6003 /// [Bit 63] Error: If 1, indicates and unsupported RMID or event type was
6004 /// written to IA32_PQR_QM_EVTSEL.
6009 /// All bit fields as a 64-bit value
6012 } MSR_IA32_QM_CTR_REGISTER
;
6016 Resource Association Register (R/W). If ( (CPUID.(EAX=07H, ECX=0):EBX[12]
6017 =1) or (CPUID.(EAX=07H, ECX=0):EBX[15] =1 ) ).
6019 @param ECX MSR_IA32_PQR_ASSOC (0x00000C8F)
6020 @param EAX Lower 32-bits of MSR value.
6021 Described by the type MSR_IA32_PQR_ASSOC_REGISTER.
6022 @param EDX Upper 32-bits of MSR value.
6023 Described by the type MSR_IA32_PQR_ASSOC_REGISTER.
6025 <b>Example usage</b>
6027 MSR_IA32_PQR_ASSOC_REGISTER Msr;
6029 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PQR_ASSOC);
6030 AsmWriteMsr64 (MSR_IA32_PQR_ASSOC, Msr.Uint64);
6032 @note MSR_IA32_PQR_ASSOC is defined as IA32_PQR_ASSOC in SDM.
6034 #define MSR_IA32_PQR_ASSOC 0x00000C8F
6037 MSR information returned for MSR index #MSR_IA32_PQR_ASSOC
6041 /// Individual bit fields
6045 /// [Bits 31:0] Resource Monitoring ID (R/W): ID for monitoring hardware
6046 /// to track internal operation, e.g. memory access. N = Ceil (Log:sub:`2`
6047 /// ( CPUID.(EAX= 0FH, ECX=0H).EBX[31:0] +1)).
6049 UINT32 ResourceMonitoringID
:32;
6051 /// [Bits 63:32] COS (R/W). The class of service (COS) to enforce (on
6052 /// writes); returns the current COS when read. If ( CPUID.(EAX=07H,
6053 /// ECX=0):EBX.[15] = 1 ).
6058 /// All bit fields as a 64-bit value
6061 } MSR_IA32_PQR_ASSOC_REGISTER
;
6065 Supervisor State of MPX Configuration. (R/W). If (CPUID.(EAX=07H,
6066 ECX=0H):EBX[14] = 1).
6068 @param ECX MSR_IA32_BNDCFGS (0x00000D90)
6069 @param EAX Lower 32-bits of MSR value.
6070 Described by the type MSR_IA32_BNDCFGS_REGISTER.
6071 @param EDX Upper 32-bits of MSR value.
6072 Described by the type MSR_IA32_BNDCFGS_REGISTER.
6074 <b>Example usage</b>
6076 MSR_IA32_BNDCFGS_REGISTER Msr;
6078 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_BNDCFGS);
6079 AsmWriteMsr64 (MSR_IA32_BNDCFGS, Msr.Uint64);
6081 @note MSR_IA32_BNDCFGS is defined as IA32_BNDCFGS in SDM.
6083 #define MSR_IA32_BNDCFGS 0x00000D90
6086 MSR information returned for MSR index #MSR_IA32_BNDCFGS
6090 /// Individual bit fields
6094 /// [Bit 0] EN: Enable Intel MPX in supervisor mode.
6098 /// [Bit 1] BNDPRESERVE: Preserve the bounds registers for near branch
6099 /// instructions in the absence of the BND prefix.
6101 UINT32 BNDPRESERVE
:1;
6104 /// [Bits 31:12] Base Address of Bound Directory.
6108 /// [Bits 63:32] Base Address of Bound Directory.
6113 /// All bit fields as a 64-bit value
6116 } MSR_IA32_BNDCFGS_REGISTER
;
6120 Extended Supervisor State Mask (R/W). If( CPUID.(0DH, 1):EAX.[3] = 1.
6122 @param ECX MSR_IA32_XSS (0x00000DA0)
6123 @param EAX Lower 32-bits of MSR value.
6124 Described by the type MSR_IA32_XSS_REGISTER.
6125 @param EDX Upper 32-bits of MSR value.
6126 Described by the type MSR_IA32_XSS_REGISTER.
6128 <b>Example usage</b>
6130 MSR_IA32_XSS_REGISTER Msr;
6132 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_XSS);
6133 AsmWriteMsr64 (MSR_IA32_XSS, Msr.Uint64);
6135 @note MSR_IA32_XSS is defined as IA32_XSS in SDM.
6137 #define MSR_IA32_XSS 0x00000DA0
6140 MSR information returned for MSR index #MSR_IA32_XSS
6144 /// Individual bit fields
6149 /// [Bit 8] Trace Packet Configuration State (R/W).
6151 UINT32 TracePacketConfigurationState
:1;
6152 UINT32 Reserved2
:23;
6153 UINT32 Reserved3
:32;
6156 /// All bit fields as a 32-bit value
6160 /// All bit fields as a 64-bit value
6163 } MSR_IA32_XSS_REGISTER
;
6167 Package Level Enable/disable HDC (R/W). If CPUID.06H:EAX.[13] = 1.
6169 @param ECX MSR_IA32_PKG_HDC_CTL (0x00000DB0)
6170 @param EAX Lower 32-bits of MSR value.
6171 Described by the type MSR_IA32_PKG_HDC_CTL_REGISTER.
6172 @param EDX Upper 32-bits of MSR value.
6173 Described by the type MSR_IA32_PKG_HDC_CTL_REGISTER.
6175 <b>Example usage</b>
6177 MSR_IA32_PKG_HDC_CTL_REGISTER Msr;
6179 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PKG_HDC_CTL);
6180 AsmWriteMsr64 (MSR_IA32_PKG_HDC_CTL, Msr.Uint64);
6182 @note MSR_IA32_PKG_HDC_CTL is defined as IA32_PKG_HDC_CTL in SDM.
6184 #define MSR_IA32_PKG_HDC_CTL 0x00000DB0
6187 MSR information returned for MSR index #MSR_IA32_PKG_HDC_CTL
6191 /// Individual bit fields
6195 /// [Bit 0] HDC_Pkg_Enable (R/W) Force HDC idling or wake up HDC-idled
6196 /// logical processors in the package. See Section 14.5.2, "Package level
6197 /// Enabling HDC". If CPUID.06H:EAX.[13] = 1.
6199 UINT32 HDC_Pkg_Enable
:1;
6200 UINT32 Reserved1
:31;
6201 UINT32 Reserved2
:32;
6204 /// All bit fields as a 32-bit value
6208 /// All bit fields as a 64-bit value
6211 } MSR_IA32_PKG_HDC_CTL_REGISTER
;
6215 Enable/disable HWP (R/W). If CPUID.06H:EAX.[13] = 1.
6217 @param ECX MSR_IA32_PM_CTL1 (0x00000DB1)
6218 @param EAX Lower 32-bits of MSR value.
6219 Described by the type MSR_IA32_PM_CTL1_REGISTER.
6220 @param EDX Upper 32-bits of MSR value.
6221 Described by the type MSR_IA32_PM_CTL1_REGISTER.
6223 <b>Example usage</b>
6225 MSR_IA32_PM_CTL1_REGISTER Msr;
6227 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_PM_CTL1);
6228 AsmWriteMsr64 (MSR_IA32_PM_CTL1, Msr.Uint64);
6230 @note MSR_IA32_PM_CTL1 is defined as IA32_PM_CTL1 in SDM.
6232 #define MSR_IA32_PM_CTL1 0x00000DB1
6235 MSR information returned for MSR index #MSR_IA32_PM_CTL1
6239 /// Individual bit fields
6243 /// [Bit 0] HDC_Allow_Block (R/W) Allow/Block this logical processor for
6244 /// package level HDC control. See Section 14.5.3.
6245 /// If CPUID.06H:EAX.[13] = 1.
6247 UINT32 HDC_Allow_Block
:1;
6248 UINT32 Reserved1
:31;
6249 UINT32 Reserved2
:32;
6252 /// All bit fields as a 32-bit value
6256 /// All bit fields as a 64-bit value
6259 } MSR_IA32_PM_CTL1_REGISTER
;
6263 Per-Logical_Processor HDC Idle Residency (R/0). If CPUID.06H:EAX.[13] = 1.
6264 Stall_Cycle_Cnt (R/W) Stalled cycles due to HDC forced idle on this logical
6265 processor. See Section 14.5.4.1. If CPUID.06H:EAX.[13] = 1.
6267 @param ECX MSR_IA32_THREAD_STALL (0x00000DB2)
6268 @param EAX Lower 32-bits of MSR value.
6269 @param EDX Upper 32-bits of MSR value.
6271 <b>Example usage</b>
6275 Msr = AsmReadMsr64 (MSR_IA32_THREAD_STALL);
6277 @note MSR_IA32_THREAD_STALL is defined as IA32_THREAD_STALL in SDM.
6279 #define MSR_IA32_THREAD_STALL 0x00000DB2
6283 Extended Feature Enables. If ( CPUID.80000001H:EDX.[2 0]
6284 CPUID.80000001H:EDX.[2 9]).
6286 @param ECX MSR_IA32_EFER (0xC0000080)
6287 @param EAX Lower 32-bits of MSR value.
6288 Described by the type MSR_IA32_EFER_REGISTER.
6289 @param EDX Upper 32-bits of MSR value.
6290 Described by the type MSR_IA32_EFER_REGISTER.
6292 <b>Example usage</b>
6294 MSR_IA32_EFER_REGISTER Msr;
6296 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_EFER);
6297 AsmWriteMsr64 (MSR_IA32_EFER, Msr.Uint64);
6299 @note MSR_IA32_EFER is defined as IA32_EFER in SDM.
6301 #define MSR_IA32_EFER 0xC0000080
6304 MSR information returned for MSR index #MSR_IA32_EFER
6308 /// Individual bit fields
6312 /// [Bit 0] SYSCALL Enable: IA32_EFER.SCE (R/W) Enables SYSCALL/SYSRET
6313 /// instructions in 64-bit mode.
6318 /// [Bit 8] IA-32e Mode Enable: IA32_EFER.LME (R/W) Enables IA-32e mode
6324 /// [Bit 10] IA-32e Mode Active: IA32_EFER.LMA (R) Indicates IA-32e mode
6325 /// is active when set.
6329 /// [Bit 11] Execute Disable Bit Enable: IA32_EFER.NXE (R/W).
6332 UINT32 Reserved3
:20;
6333 UINT32 Reserved4
:32;
6336 /// All bit fields as a 32-bit value
6340 /// All bit fields as a 64-bit value
6343 } MSR_IA32_EFER_REGISTER
;
6347 System Call Target Address (R/W). If CPUID.80000001:EDX.[29] = 1.
6349 @param ECX MSR_IA32_STAR (0xC0000081)
6350 @param EAX Lower 32-bits of MSR value.
6351 @param EDX Upper 32-bits of MSR value.
6353 <b>Example usage</b>
6357 Msr = AsmReadMsr64 (MSR_IA32_STAR);
6358 AsmWriteMsr64 (MSR_IA32_STAR, Msr);
6360 @note MSR_IA32_STAR is defined as IA32_STAR in SDM.
6362 #define MSR_IA32_STAR 0xC0000081
6366 IA-32e Mode System Call Target Address (R/W). If CPUID.80000001:EDX.[29] = 1.
6368 @param ECX MSR_IA32_LSTAR (0xC0000082)
6369 @param EAX Lower 32-bits of MSR value.
6370 @param EDX Upper 32-bits of MSR value.
6372 <b>Example usage</b>
6376 Msr = AsmReadMsr64 (MSR_IA32_LSTAR);
6377 AsmWriteMsr64 (MSR_IA32_LSTAR, Msr);
6379 @note MSR_IA32_LSTAR is defined as IA32_LSTAR in SDM.
6381 #define MSR_IA32_LSTAR 0xC0000082
6385 System Call Flag Mask (R/W). If CPUID.80000001:EDX.[29] = 1.
6387 @param ECX MSR_IA32_FMASK (0xC0000084)
6388 @param EAX Lower 32-bits of MSR value.
6389 @param EDX Upper 32-bits of MSR value.
6391 <b>Example usage</b>
6395 Msr = AsmReadMsr64 (MSR_IA32_FMASK);
6396 AsmWriteMsr64 (MSR_IA32_FMASK, Msr);
6398 @note MSR_IA32_FMASK is defined as IA32_FMASK in SDM.
6400 #define MSR_IA32_FMASK 0xC0000084
6404 Map of BASE Address of FS (R/W). If CPUID.80000001:EDX.[29] = 1.
6406 @param ECX MSR_IA32_FS_BASE (0xC0000100)
6407 @param EAX Lower 32-bits of MSR value.
6408 @param EDX Upper 32-bits of MSR value.
6410 <b>Example usage</b>
6414 Msr = AsmReadMsr64 (MSR_IA32_FS_BASE);
6415 AsmWriteMsr64 (MSR_IA32_FS_BASE, Msr);
6417 @note MSR_IA32_FS_BASE is defined as IA32_FS_BASE in SDM.
6419 #define MSR_IA32_FS_BASE 0xC0000100
6423 Map of BASE Address of GS (R/W). If CPUID.80000001:EDX.[29] = 1.
6425 @param ECX MSR_IA32_GS_BASE (0xC0000101)
6426 @param EAX Lower 32-bits of MSR value.
6427 @param EDX Upper 32-bits of MSR value.
6429 <b>Example usage</b>
6433 Msr = AsmReadMsr64 (MSR_IA32_GS_BASE);
6434 AsmWriteMsr64 (MSR_IA32_GS_BASE, Msr);
6436 @note MSR_IA32_GS_BASE is defined as IA32_GS_BASE in SDM.
6438 #define MSR_IA32_GS_BASE 0xC0000101
6442 Swap Target of BASE Address of GS (R/W). If CPUID.80000001:EDX.[29] = 1.
6444 @param ECX MSR_IA32_KERNEL_GS_BASE (0xC0000102)
6445 @param EAX Lower 32-bits of MSR value.
6446 @param EDX Upper 32-bits of MSR value.
6448 <b>Example usage</b>
6452 Msr = AsmReadMsr64 (MSR_IA32_KERNEL_GS_BASE);
6453 AsmWriteMsr64 (MSR_IA32_KERNEL_GS_BASE, Msr);
6455 @note MSR_IA32_KERNEL_GS_BASE is defined as IA32_KERNEL_GS_BASE in SDM.
6457 #define MSR_IA32_KERNEL_GS_BASE 0xC0000102
6461 Auxiliary TSC (RW). If CPUID.80000001H: EDX[27] = 1.
6463 @param ECX MSR_IA32_TSC_AUX (0xC0000103)
6464 @param EAX Lower 32-bits of MSR value.
6465 Described by the type MSR_IA32_TSC_AUX_REGISTER.
6466 @param EDX Upper 32-bits of MSR value.
6467 Described by the type MSR_IA32_TSC_AUX_REGISTER.
6469 <b>Example usage</b>
6471 MSR_IA32_TSC_AUX_REGISTER Msr;
6473 Msr.Uint64 = AsmReadMsr64 (MSR_IA32_TSC_AUX);
6474 AsmWriteMsr64 (MSR_IA32_TSC_AUX, Msr.Uint64);
6476 @note MSR_IA32_TSC_AUX is defined as IA32_TSC_AUX in SDM.
6478 #define MSR_IA32_TSC_AUX 0xC0000103
6481 MSR information returned for MSR index #MSR_IA32_TSC_AUX
6485 /// Individual bit fields
6489 /// [Bits 31:0] AUX: Auxiliary signature of TSC.
6495 /// All bit fields as a 32-bit value
6499 /// All bit fields as a 64-bit value
6502 } MSR_IA32_TSC_AUX_REGISTER
;