2 IA32 Local APIC Definitions.
4 Copyright (c) 2010 - 2011, Intel Corporation. All rights reserved.<BR>
5 This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
15 #ifndef __LOCAL_APIC_H__
16 #define __LOCAL_APIC_H__
19 // Definitions for IA32 architectural MSRs
21 #define MSR_IA32_APIC_BASE_ADDRESS 0x1B
24 // Definitions for CPUID instruction
26 #define CPUID_VERSION_INFO 0x1
27 #define CPUID_EXTENDED_FUNCTION 0x80000000
28 #define CPUID_VIR_PHY_ADDRESS_SIZE 0x80000008
31 // Definition for Local APIC registers and related values
33 #define XAPIC_ID_OFFSET 0x20
34 #define XAPIC_VERSION_OFFSET 0x30
35 #define XAPIC_EOI_OFFSET 0x0b0
36 #define XAPIC_ICR_DFR_OFFSET 0x0e0
37 #define XAPIC_SPURIOUS_VECTOR_OFFSET 0x0f0
38 #define XAPIC_ICR_LOW_OFFSET 0x300
39 #define XAPIC_ICR_HIGH_OFFSET 0x310
40 #define XAPIC_LVT_TIMER_OFFSET 0x320
41 #define XAPIC_LVT_LINT0_OFFSET 0x350
42 #define XAPIC_LVT_LINT1_OFFSET 0x360
43 #define XAPIC_TIMER_INIT_COUNT_OFFSET 0x380
44 #define XAPIC_TIMER_CURRENT_COUNT_OFFSET 0x390
45 #define XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET 0x3E0
47 #define X2APIC_MSR_BASE_ADDRESS 0x800
48 #define X2APIC_MSR_ICR_ADDRESS 0x830
50 #define LOCAL_APIC_DELIVERY_MODE_FIXED 0
51 #define LOCAL_APIC_DELIVERY_MODE_LOWEST_PRIORITY 1
52 #define LOCAL_APIC_DELIVERY_MODE_SMI 2
53 #define LOCAL_APIC_DELIVERY_MODE_NMI 4
54 #define LOCAL_APIC_DELIVERY_MODE_INIT 5
55 #define LOCAL_APIC_DELIVERY_MODE_STARTUP 6
56 #define LOCAL_APIC_DELIVERY_MODE_EXTINT 7
58 #define LOCAL_APIC_DESTINATION_SHORTHAND_NO_SHORTHAND 0
59 #define LOCAL_APIC_DESTINATION_SHORTHAND_SELF 1
60 #define LOCAL_APIC_DESTINATION_SHORTHAND_ALL_INCLUDING_SELF 2
61 #define LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF 3
65 UINT32 Reserved0
:8; ///< Reserved.
66 UINT32 Bsp
:1; ///< Processor is BSP.
67 UINT32 Reserved1
:1; ///< Reserved.
68 UINT32 Extd
:1; ///< Enable x2APIC mode.
69 UINT32 En
:1; ///< xAPIC global enable/disable.
70 UINT32 ApicBaseLow
:20; ///< APIC Base physical address. The actual field width depends on physical address width.
71 UINT32 ApicBaseHigh
:32;
77 // Local APIC Version Register.
81 UINT32 Version
:8; ///< The version numbers of the local APIC.
82 UINT32 Reserved0
:8; ///< Reserved.
83 UINT32 MaxLvtEntry
:8; ///< Number of LVT entries minus 1.
84 UINT32 EoiBroadcastSuppression
:1; ///< 1 if EOI-broadcast suppression supported.
85 UINT32 Reserved1
:7; ///< Reserved.
91 // Low half of Interrupt Command Register (ICR).
95 UINT32 Vector
:8; ///< The vector number of the interrupt being sent.
96 UINT32 DeliveryMode
:3; ///< Specifies the type of IPI to be sent.
97 UINT32 DestinationMode
:1; ///< 0: physical destination mode, 1: logical destination mode.
98 UINT32 DeliveryStatus
:1; ///< Indicates the IPI delivery status. This field is reserved in x2APIC mode.
99 UINT32 Reserved0
:1; ///< Reserved.
100 UINT32 Level
:1; ///< 0 for the INIT level de-assert delivery mode. Otherwise 1.
101 UINT32 TriggerMode
:1; ///< 0: edge, 1: level when using the INIT level de-assert delivery mode.
102 UINT32 Reserved1
:2; ///< Reserved.
103 UINT32 DestinationShorthand
:2; ///< A shorthand notation to specify the destination of the interrupt.
104 UINT32 Reserved2
:12; ///< Reserved.
107 } LOCAL_APIC_ICR_LOW
;
110 // High half of Interrupt Command Register (ICR)
114 UINT32 Reserved0
:24; ///< Reserved.
115 UINT32 Destination
:8; ///< Specifies the target processor or processors in xAPIC mode.
117 UINT32 Uint32
; ///< Destination field expanded to 32-bit in x2APIC mode.
118 } LOCAL_APIC_ICR_HIGH
;
121 // Spurious-Interrupt Vector Register (SVR)
125 UINT32 SpuriousVector
:8; ///< Spurious Vector.
126 UINT32 SoftwareEnable
:1; ///< APIC Software Enable/Disable.
127 UINT32 FocusProcessorChecking
:1; ///< Focus Processor Checking.
128 UINT32 Reserved0
:2; ///< Reserved.
129 UINT32 EoiBroadcastSuppression
:1; ///< EOI-Broadcast Suppression.
130 UINT32 Reserved1
:19; ///< Reserved.
136 // Divide Configuration Register (DCR)
140 UINT32 DivideValue1
:2; ///< Low 2 bits of the divide value.
141 UINT32 Reserved0
:1; ///< Always 0.
142 UINT32 DivideValue2
:1; ///< Highest 1 bit of the divide value.
143 UINT32 Reserved1
:28; ///< Reserved.
149 // LVT Timer Register
153 UINT32 Vector
:8; ///< The vector number of the interrupt being sent.
154 UINT32 Reserved0
:4; ///< Reserved.
155 UINT32 DeliveryStatus
:1; ///< 0: Idle, 1: send pending.
156 UINT32 Reserved1
:3; ///< Reserved.
157 UINT32 Mask
:1; ///< 0: Not masked, 1: Masked.
158 UINT32 TimerMode
:1; ///< 0: One-shot, 1: Periodic.
159 UINT32 Reserved2
:14; ///< Reserved.
162 } LOCAL_APIC_LVT_TIMER
;
165 // LVT LINT0/LINT1 Register
169 UINT32 Vector
:8; ///< The vector number of the interrupt being sent.
170 UINT32 DeliveryMode
:3; ///< Specifies the type of interrupt to be sent.
171 UINT32 Reserved0
:1; ///< Reserved.
172 UINT32 DeliveryStatus
:1; ///< 0: Idle, 1: send pending.
173 UINT32 InputPinPolarity
:1; ///< Interrupt Input Pin Polarity.
174 UINT32 RemoteIrr
:1; ///< RO. Set when the local APIC accepts the interrupt and reset when an EOI is received.
175 UINT32 TriggerMode
:1; ///< 0:edge, 1:level.
176 UINT32 Mask
:1; ///< 0: Not masked, 1: Masked.
177 UINT32 Reserved1
:15; ///< Reserved.
180 } LOCAL_APIC_LVT_LINT
;
183 // MSI Address Register
187 UINT32 Reserved0
:2; ///< Reserved
188 UINT32 DestinationMode
:1; ///< Specifies the Destination Mode.
189 UINT32 RedirectionHint
:1; ///< Specifies the Redirection Hint.
190 UINT32 Reserved1
:8; ///< Reserved.
191 UINT32 DestinationId
:8; ///< Specifies the Destination ID.
192 UINT32 BaseAddress
:12; ///< Must be 0FEEH
195 } LOCAL_APIC_MSI_ADDRESS
;
198 // MSI Address Register
202 UINT32 Vector
:8; ///< Interrupt vector in range 010h..0FEH
203 UINT32 DeliveryMode
:3; ///< Specifies the type of interrupt to be sent.
204 UINT32 Reserved0
:3; ///< Reserved.
205 UINT32 Level
:1; ///< 0:Deassert, 1:Assert. Ignored for Edge triggered interrupts.
206 UINT32 TriggerMode
:1; ///< 0:Edge, 1:Level.
207 UINT32 Reserved1
:16; ///< Reserved.
208 UINT32 Reserved2
:32; ///< Reserved.
211 } LOCAL_APIC_MSI_DATA
;