2 MSR Definitions for Intel(R) Xeon(R) Processor Series 5600.
4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures
5 are provided for MSRs that contain one or more bit fields. If the MSR value
6 returned is a single 32-bit or 64-bit value, then a data structure is not
9 Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
10 This program and the accompanying materials
11 are licensed and made available under the terms and conditions of the BSD License
12 which accompanies this distribution. The full text of the license may be found at
13 http://opensource.org/licenses/bsd-license.php
15 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
16 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 @par Specification Reference:
19 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
20 December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-6.
24 #ifndef __XEON_5600_MSR_H__
25 #define __XEON_5600_MSR_H__
27 #include <Register/ArchitecturalMsr.h>
30 Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP
31 handler to handle unsuccessful read of this MSR.
33 @param ECX MSR_XEON_5600_FEATURE_CONFIG (0x0000013C)
34 @param EAX Lower 32-bits of MSR value.
35 Described by the type MSR_XEON_5600_FEATURE_CONFIG_REGISTER.
36 @param EDX Upper 32-bits of MSR value.
37 Described by the type MSR_XEON_5600_FEATURE_CONFIG_REGISTER.
41 MSR_XEON_5600_FEATURE_CONFIG_REGISTER Msr;
43 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_5600_FEATURE_CONFIG);
44 AsmWriteMsr64 (MSR_XEON_5600_FEATURE_CONFIG, Msr.Uint64);
46 @note MSR_XEON_5600_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM.
48 #define MSR_XEON_5600_FEATURE_CONFIG 0x0000013C
51 MSR information returned for MSR index #MSR_XEON_5600_FEATURE_CONFIG
55 /// Individual bit fields
59 /// [Bits 1:0] AES Configuration (RW-L) Upon a successful read of this
60 /// MSR, the configuration of AES instruction set availability is as
61 /// follows: 11b: AES instructions are not available until next RESET.
62 /// otherwise, AES instructions are available. Note, AES instruction set
63 /// is not available if read is unsuccessful. If the configuration is not
64 /// 01b, AES instruction can be mis-configured if a privileged agent
65 /// unintentionally writes 11b.
67 UINT32 AESConfiguration
:2;
72 /// All bit fields as a 32-bit value
76 /// All bit fields as a 64-bit value
79 } MSR_XEON_5600_FEATURE_CONFIG_REGISTER
;
83 Thread. Offcore Response Event Select Register (R/W).
85 @param ECX MSR_XEON_5600_OFFCORE_RSP_1 (0x000001A7)
86 @param EAX Lower 32-bits of MSR value.
87 @param EDX Upper 32-bits of MSR value.
93 Msr = AsmReadMsr64 (MSR_XEON_5600_OFFCORE_RSP_1);
94 AsmWriteMsr64 (MSR_XEON_5600_OFFCORE_RSP_1, Msr);
96 @note MSR_XEON_5600_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM.
98 #define MSR_XEON_5600_OFFCORE_RSP_1 0x000001A7
102 Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
103 RW if MSR_PLATFORM_INFO.[28] = 1.
105 @param ECX MSR_XEON_5600_TURBO_RATIO_LIMIT (0x000001AD)
106 @param EAX Lower 32-bits of MSR value.
107 Described by the type MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER.
108 @param EDX Upper 32-bits of MSR value.
109 Described by the type MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER.
113 MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER Msr;
115 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_5600_TURBO_RATIO_LIMIT);
117 @note MSR_XEON_5600_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.
119 #define MSR_XEON_5600_TURBO_RATIO_LIMIT 0x000001AD
122 MSR information returned for MSR index #MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER
126 /// Individual bit fields
130 /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio
131 /// limit of 1 core active.
135 /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio
136 /// limit of 2 core active.
140 /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio
141 /// limit of 3 core active.
145 /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio
146 /// limit of 4 core active.
150 /// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio
151 /// limit of 5 core active.
155 /// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio
156 /// limit of 6 core active.
162 /// All bit fields as a 64-bit value
165 } MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER
;
169 Package. See Table 35-2.
171 @param ECX MSR_XEON_5600_IA32_ENERGY_PERF_BIAS (0x000001B0)
172 @param EAX Lower 32-bits of MSR value.
173 @param EDX Upper 32-bits of MSR value.
179 Msr = AsmReadMsr64 (MSR_XEON_5600_IA32_ENERGY_PERF_BIAS);
180 AsmWriteMsr64 (MSR_XEON_5600_IA32_ENERGY_PERF_BIAS, Msr);
182 @note MSR_XEON_5600_IA32_ENERGY_PERF_BIAS is defined as IA32_ENERGY_PERF_BIAS in SDM.
184 #define MSR_XEON_5600_IA32_ENERGY_PERF_BIAS 0x000001B0