UefiCpuPkg/Include/Register/Msr/Xeon5600Msr.h

   1 /** @file
   2   MSR Definitions for Intel(R) Xeon(R) Processor Series 5600.
   3
   4   Provides defines for Machine Specific Registers(MSR) indexes. Data structures
   5   are provided for MSRs that contain one or more bit fields.  If the MSR value
   6   returned is a single 32-bit or 64-bit value, then a data structure is not
   7   provided for that MSR.
   8
   9   Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
  10   This program and the accompanying materials
  11   are licensed and made available under the terms and conditions of the BSD License
  12   which accompanies this distribution.  The full text of the license may be found at
  13   http://opensource.org/licenses/bsd-license.php
  14
  15   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  16   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  17
  18   @par Specification Reference:
  19   Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,
  20   December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-6.
  21
  22 **/
  23
  24 #ifndef __XEON_5600_MSR_H__
  25 #define __XEON_5600_MSR_H__
  26
  27 #include <Register/ArchitecturalMsr.h>
  28
  29 /**
  30   Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP
  31   handler to handle unsuccessful read of this MSR.
  32
  33   @param  ECX  MSR_XEON_5600_FEATURE_CONFIG (0x0000013C)
  34   @param  EAX  Lower 32-bits of MSR value.
  35                Described by the type MSR_XEON_5600_FEATURE_CONFIG_REGISTER.
  36   @param  EDX  Upper 32-bits of MSR value.
  37                Described by the type MSR_XEON_5600_FEATURE_CONFIG_REGISTER.
  38
  39   <b>Example usage</b>
  40   @code
  41   MSR_XEON_5600_FEATURE_CONFIG_REGISTER  Msr;
  42
  43   Msr.Uint64 = AsmReadMsr64 (MSR_XEON_5600_FEATURE_CONFIG);
  44   AsmWriteMsr64 (MSR_XEON_5600_FEATURE_CONFIG, Msr.Uint64);
  45   @endcode
  46   @note MSR_XEON_5600_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM.
  47 **/
  48 #define MSR_XEON_5600_FEATURE_CONFIG             0x0000013C
  49
  50 /**
  51   MSR information returned for MSR index #MSR_XEON_5600_FEATURE_CONFIG
  52 **/
  53 typedef union {
  54   ///
  55   /// Individual bit fields
  56   ///
  57   struct {
  58     ///
  59     /// [Bits 1:0] AES Configuration (RW-L)  Upon a successful read of this
  60     /// MSR, the configuration of AES instruction set availability is as
  61     /// follows: 11b: AES instructions are not available until next RESET.
  62     /// otherwise, AES instructions are available. Note, AES instruction set
  63     /// is not available if read is unsuccessful. If the configuration is not
  64     /// 01b, AES instruction can be mis-configured if a privileged agent
  65     /// unintentionally writes 11b.
  66     ///
  67     UINT32  AESConfiguration:2;
  68     UINT32  Reserved1:30;
  69     UINT32  Reserved2:32;
  70   } Bits;
  71   ///
  72   /// All bit fields as a 32-bit value
  73   ///
  74   UINT32  Uint32;
  75   ///
  76   /// All bit fields as a 64-bit value
  77   ///
  78   UINT64  Uint64;
  79 } MSR_XEON_5600_FEATURE_CONFIG_REGISTER;
  80
  81
  82 /**
  83   Thread. Offcore Response Event Select Register (R/W).
  84
  85   @param  ECX  MSR_XEON_5600_OFFCORE_RSP_1 (0x000001A7)
  86   @param  EAX  Lower 32-bits of MSR value.
  87   @param  EDX  Upper 32-bits of MSR value.
  88
  89   <b>Example usage</b>
  90   @code
  91   UINT64  Msr;
  92
  93   Msr = AsmReadMsr64 (MSR_XEON_5600_OFFCORE_RSP_1);
  94   AsmWriteMsr64 (MSR_XEON_5600_OFFCORE_RSP_1, Msr);
  95   @endcode
  96   @note MSR_XEON_5600_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM.
  97 **/
  98 #define MSR_XEON_5600_OFFCORE_RSP_1              0x000001A7
  99
 100
 101 /**
 102   Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
 103   RW if MSR_PLATFORM_INFO.[28] = 1.
 104
 105   @param  ECX  MSR_XEON_5600_TURBO_RATIO_LIMIT (0x000001AD)
 106   @param  EAX  Lower 32-bits of MSR value.
 107                Described by the type MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER.
 108   @param  EDX  Upper 32-bits of MSR value.
 109                Described by the type MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER.
 110
 111   <b>Example usage</b>
 112   @code
 113   MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER  Msr;
 114
 115   Msr.Uint64 = AsmReadMsr64 (MSR_XEON_5600_TURBO_RATIO_LIMIT);
 116   @endcode
 117   @note MSR_XEON_5600_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.
 118 **/
 119 #define MSR_XEON_5600_TURBO_RATIO_LIMIT          0x000001AD
 120
 121 /**
 122   MSR information returned for MSR index #MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER
 123 **/
 124 typedef union {
 125   ///
 126   /// Individual bit fields
 127   ///
 128   struct {
 129     ///
 130     /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio
 131     /// limit of 1 core active.
 132     ///
 133     UINT32  Maximum1C:8;
 134     ///
 135     /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio
 136     /// limit of 2 core active.
 137     ///
 138     UINT32  Maximum2C:8;
 139     ///
 140     /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio
 141     /// limit of 3 core active.
 142     ///
 143     UINT32  Maximum3C:8;
 144     ///
 145     /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio
 146     /// limit of 4 core active.
 147     ///
 148     UINT32  Maximum4C:8;
 149     ///
 150     /// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio
 151     /// limit of 5 core active.
 152     ///
 153     UINT32  Maximum5C:8;
 154     ///
 155     /// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio
 156     /// limit of 6 core active.
 157     ///
 158     UINT32  Maximum6C:8;
 159     UINT32  Reserved:16;
 160   } Bits;
 161   ///
 162   /// All bit fields as a 64-bit value
 163   ///
 164   UINT64  Uint64;
 165 } MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER;
 166
 167
 168 /**
 169   Package. See Table 35-2.
 170
 171   @param  ECX  MSR_XEON_5600_IA32_ENERGY_PERF_BIAS (0x000001B0)
 172   @param  EAX  Lower 32-bits of MSR value.
 173   @param  EDX  Upper 32-bits of MSR value.
 174
 175   <b>Example usage</b>
 176   @code
 177   UINT64  Msr;
 178
 179   Msr = AsmReadMsr64 (MSR_XEON_5600_IA32_ENERGY_PERF_BIAS);
 180   AsmWriteMsr64 (MSR_XEON_5600_IA32_ENERGY_PERF_BIAS, Msr);
 181   @endcode
 182   @note MSR_XEON_5600_IA32_ENERGY_PERF_BIAS is defined as IA32_ENERGY_PERF_BIAS in SDM.
 183 **/
 184 #define MSR_XEON_5600_IA32_ENERGY_PERF_BIAS      0x000001B0
 185
 186 #endif