4 This local APIC library instance supports xAPIC mode only.
6 Copyright (c) 2010 - 2019, Intel Corporation. All rights reserved.<BR>
7 Copyright (c) 2017 - 2020, AMD Inc. All rights reserved.<BR>
9 SPDX-License-Identifier: BSD-2-Clause-Patent
13 #include <Register/Intel/Cpuid.h>
14 #include <Register/Amd/Cpuid.h>
15 #include <Register/Intel/Msr.h>
16 #include <Register/Intel/LocalApic.h>
18 #include <Library/BaseLib.h>
19 #include <Library/DebugLib.h>
20 #include <Library/LocalApicLib.h>
21 #include <Library/IoLib.h>
22 #include <Library/TimerLib.h>
23 #include <Library/PcdLib.h>
24 #include <Library/UefiCpuLib.h>
27 // Library internal functions
31 Determine if the CPU supports the Local APIC Base Address MSR.
33 @retval TRUE The CPU supports the Local APIC Base Address MSR.
34 @retval FALSE The CPU does not support the Local APIC Base Address MSR.
38 LocalApicBaseAddressMsrSupported (
45 AsmCpuid (1, &RegEax
, NULL
, NULL
, NULL
);
46 FamilyId
= BitFieldRead32 (RegEax
, 8, 11);
47 if ((FamilyId
== 0x04) || (FamilyId
== 0x05)) {
49 // CPUs with a FamilyId of 0x04 or 0x05 do not support the
50 // Local APIC Base Address MSR
59 Retrieve the base address of local APIC.
61 @return The base address of local APIC.
66 GetLocalApicBaseAddress (
70 MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr
;
72 if (!LocalApicBaseAddressMsrSupported ()) {
74 // If CPU does not support Local APIC Base Address MSR, then retrieve
75 // Local APIC Base Address from PCD
77 return PcdGet32 (PcdCpuLocalApicBaseAddress
);
80 ApicBaseMsr
.Uint64
= AsmReadMsr64 (MSR_IA32_APIC_BASE
);
82 return (UINTN
)(LShiftU64 ((UINT64
)ApicBaseMsr
.Bits
.ApicBaseHi
, 32)) +
83 (((UINTN
)ApicBaseMsr
.Bits
.ApicBase
) << 12);
87 Set the base address of local APIC.
89 If BaseAddress is not aligned on a 4KB boundary, then ASSERT().
91 @param[in] BaseAddress Local APIC base address to be set.
96 SetLocalApicBaseAddress (
100 MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr
;
102 ASSERT ((BaseAddress
& (SIZE_4KB
- 1)) == 0);
104 if (!LocalApicBaseAddressMsrSupported ()) {
106 // Ignore set request if the CPU does not support APIC Base Address MSR
111 ApicBaseMsr
.Uint64
= AsmReadMsr64 (MSR_IA32_APIC_BASE
);
113 ApicBaseMsr
.Bits
.ApicBase
= (UINT32
)(BaseAddress
>> 12);
114 ApicBaseMsr
.Bits
.ApicBaseHi
= (UINT32
)(RShiftU64 ((UINT64
)BaseAddress
, 32));
116 AsmWriteMsr64 (MSR_IA32_APIC_BASE
, ApicBaseMsr
.Uint64
);
120 Read from a local APIC register.
122 This function reads from a local APIC register either in xAPIC or x2APIC mode.
123 It is required that in xAPIC mode wider registers (64-bit or 256-bit) must be
124 accessed using multiple 32-bit loads or stores, so this function only performs
127 @param MmioOffset The MMIO offset of the local APIC register in xAPIC mode.
128 It must be 16-byte aligned.
130 @return 32-bit Value read from the register.
138 ASSERT ((MmioOffset
& 0xf) == 0);
139 ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC
);
141 return MmioRead32 (GetLocalApicBaseAddress () + MmioOffset
);
145 Write to a local APIC register.
147 This function writes to a local APIC register either in xAPIC or x2APIC mode.
148 It is required that in xAPIC mode wider registers (64-bit or 256-bit) must be
149 accessed using multiple 32-bit loads or stores, so this function only performs
152 if the register index is invalid or unsupported in current APIC mode, then ASSERT.
154 @param MmioOffset The MMIO offset of the local APIC register in xAPIC mode.
155 It must be 16-byte aligned.
156 @param Value Value to be written to the register.
165 ASSERT ((MmioOffset
& 0xf) == 0);
166 ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC
);
168 MmioWrite32 (GetLocalApicBaseAddress () + MmioOffset
, Value
);
172 Send an IPI by writing to ICR.
174 This function returns after the IPI has been accepted by the target processor.
176 @param IcrLow 32-bit value to be written to the low half of ICR.
177 @param ApicId APIC ID of the target processor if this IPI is targeted for a specific processor.
185 LOCAL_APIC_ICR_LOW IcrLowReg
;
187 BOOLEAN InterruptState
;
189 ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC
);
190 ASSERT (ApicId
<= 0xff);
192 InterruptState
= SaveAndDisableInterrupts ();
195 // Save existing contents of ICR high 32 bits
197 IcrHigh
= ReadLocalApicReg (XAPIC_ICR_HIGH_OFFSET
);
200 // Wait for DeliveryStatus clear in case a previous IPI
201 // is still being sent
204 IcrLowReg
.Uint32
= ReadLocalApicReg (XAPIC_ICR_LOW_OFFSET
);
205 } while (IcrLowReg
.Bits
.DeliveryStatus
!= 0);
208 // For xAPIC, the act of writing to the low doubleword of the ICR causes the IPI to be sent.
210 WriteLocalApicReg (XAPIC_ICR_HIGH_OFFSET
, ApicId
<< 24);
211 WriteLocalApicReg (XAPIC_ICR_LOW_OFFSET
, IcrLow
);
214 // Wait for DeliveryStatus clear again
217 IcrLowReg
.Uint32
= ReadLocalApicReg (XAPIC_ICR_LOW_OFFSET
);
218 } while (IcrLowReg
.Bits
.DeliveryStatus
!= 0);
221 // And restore old contents of ICR high
223 WriteLocalApicReg (XAPIC_ICR_HIGH_OFFSET
, IcrHigh
);
225 SetInterruptState (InterruptState
);
229 // Library API implementation functions
233 Get the current local APIC mode.
235 If local APIC is disabled, then ASSERT.
237 @retval LOCAL_APIC_MODE_XAPIC current APIC mode is xAPIC.
238 @retval LOCAL_APIC_MODE_X2APIC current APIC mode is x2APIC.
248 MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr
;
251 // Check to see if the CPU supports the APIC Base Address MSR
253 if (LocalApicBaseAddressMsrSupported ()) {
254 ApicBaseMsr
.Uint64
= AsmReadMsr64 (MSR_IA32_APIC_BASE
);
256 // Local APIC should have been enabled
258 ASSERT (ApicBaseMsr
.Bits
.EN
!= 0);
259 ASSERT (ApicBaseMsr
.Bits
.EXTD
== 0);
263 return LOCAL_APIC_MODE_XAPIC
;
267 Set the current local APIC mode.
269 If the specified local APIC mode is not valid, then ASSERT.
270 If the specified local APIC mode can't be set as current, then ASSERT.
272 @param ApicMode APIC mode to be set.
274 @note This API must not be called from an interrupt handler or SMI handler.
275 It may result in unpredictable behavior.
283 ASSERT (ApicMode
== LOCAL_APIC_MODE_XAPIC
);
284 ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC
);
288 Get the initial local APIC ID of the executing processor assigned by hardware upon power on or reset.
290 In xAPIC mode, the initial local APIC ID may be different from current APIC ID.
291 In x2APIC mode, the local APIC ID can't be changed and there is no concept of initial APIC ID. In this case,
292 the 32-bit local APIC ID is returned as initial APIC ID.
294 @return 32-bit initial local APIC ID of the executing processor.
303 UINT32 MaxCpuIdIndex
;
306 ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC
);
309 // Get the max index of basic CPUID
311 AsmCpuid (CPUID_SIGNATURE
, &MaxCpuIdIndex
, NULL
, NULL
, NULL
);
314 // If CPUID Leaf B is supported,
315 // And CPUID.0BH:EBX[15:0] reports a non-zero value,
316 // Then the initial 32-bit APIC ID = CPUID.0BH:EDX
317 // Else the initial 8-bit APIC ID = CPUID.1:EBX[31:24]
319 if (MaxCpuIdIndex
>= CPUID_EXTENDED_TOPOLOGY
) {
320 AsmCpuidEx (CPUID_EXTENDED_TOPOLOGY
, 0, NULL
, &RegEbx
, NULL
, &ApicId
);
321 if ((RegEbx
& (BIT16
- 1)) != 0) {
326 AsmCpuid (CPUID_VERSION_INFO
, NULL
, &RegEbx
, NULL
, NULL
);
331 Get the local APIC ID of the executing processor.
333 @return 32-bit local APIC ID of the executing processor.
343 ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC
);
345 if ((ApicId
= GetInitialApicId ()) < 0x100) {
347 // If the initial local APIC ID is less 0x100, read APIC ID from
348 // XAPIC_ID_OFFSET, otherwise return the initial local APIC ID.
350 ApicId
= ReadLocalApicReg (XAPIC_ID_OFFSET
);
358 Get the value of the local APIC version register.
360 @return the value of the local APIC version register.
368 return ReadLocalApicReg (XAPIC_VERSION_OFFSET
);
372 Send a Fixed IPI to a specified target processor.
374 This function returns after the IPI has been accepted by the target processor.
376 @param ApicId The local APIC ID of the target processor.
377 @param Vector The vector number of the interrupt being sent.
386 LOCAL_APIC_ICR_LOW IcrLow
;
389 IcrLow
.Bits
.DeliveryMode
= LOCAL_APIC_DELIVERY_MODE_FIXED
;
390 IcrLow
.Bits
.Level
= 1;
391 IcrLow
.Bits
.Vector
= Vector
;
392 SendIpi (IcrLow
.Uint32
, ApicId
);
396 Send a Fixed IPI to all processors excluding self.
398 This function returns after the IPI has been accepted by the target processors.
400 @param Vector The vector number of the interrupt being sent.
404 SendFixedIpiAllExcludingSelf (
408 LOCAL_APIC_ICR_LOW IcrLow
;
411 IcrLow
.Bits
.DeliveryMode
= LOCAL_APIC_DELIVERY_MODE_FIXED
;
412 IcrLow
.Bits
.Level
= 1;
413 IcrLow
.Bits
.DestinationShorthand
= LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF
;
414 IcrLow
.Bits
.Vector
= Vector
;
415 SendIpi (IcrLow
.Uint32
, 0);
419 Send a SMI IPI to a specified target processor.
421 This function returns after the IPI has been accepted by the target processor.
423 @param ApicId Specify the local APIC ID of the target processor.
431 LOCAL_APIC_ICR_LOW IcrLow
;
434 IcrLow
.Bits
.DeliveryMode
= LOCAL_APIC_DELIVERY_MODE_SMI
;
435 IcrLow
.Bits
.Level
= 1;
436 SendIpi (IcrLow
.Uint32
, ApicId
);
440 Send a SMI IPI to all processors excluding self.
442 This function returns after the IPI has been accepted by the target processors.
446 SendSmiIpiAllExcludingSelf (
450 LOCAL_APIC_ICR_LOW IcrLow
;
453 IcrLow
.Bits
.DeliveryMode
= LOCAL_APIC_DELIVERY_MODE_SMI
;
454 IcrLow
.Bits
.Level
= 1;
455 IcrLow
.Bits
.DestinationShorthand
= LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF
;
456 SendIpi (IcrLow
.Uint32
, 0);
460 Send an INIT IPI to a specified target processor.
462 This function returns after the IPI has been accepted by the target processor.
464 @param ApicId Specify the local APIC ID of the target processor.
472 LOCAL_APIC_ICR_LOW IcrLow
;
475 IcrLow
.Bits
.DeliveryMode
= LOCAL_APIC_DELIVERY_MODE_INIT
;
476 IcrLow
.Bits
.Level
= 1;
477 SendIpi (IcrLow
.Uint32
, ApicId
);
481 Send an INIT IPI to all processors excluding self.
483 This function returns after the IPI has been accepted by the target processors.
487 SendInitIpiAllExcludingSelf (
491 LOCAL_APIC_ICR_LOW IcrLow
;
494 IcrLow
.Bits
.DeliveryMode
= LOCAL_APIC_DELIVERY_MODE_INIT
;
495 IcrLow
.Bits
.Level
= 1;
496 IcrLow
.Bits
.DestinationShorthand
= LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF
;
497 SendIpi (IcrLow
.Uint32
, 0);
501 Send an INIT-Start-up-Start-up IPI sequence to a specified target processor.
503 This function returns after the IPI has been accepted by the target processor.
505 if StartupRoutine >= 1M, then ASSERT.
506 if StartupRoutine is not multiple of 4K, then ASSERT.
508 @param ApicId Specify the local APIC ID of the target processor.
509 @param StartupRoutine Points to a start-up routine which is below 1M physical
510 address and 4K aligned.
516 IN UINT32 StartupRoutine
519 LOCAL_APIC_ICR_LOW IcrLow
;
521 ASSERT (StartupRoutine
< 0x100000);
522 ASSERT ((StartupRoutine
& 0xfff) == 0);
524 SendInitIpi (ApicId
);
525 MicroSecondDelay (PcdGet32 (PcdCpuInitIpiDelayInMicroSeconds
));
527 IcrLow
.Bits
.Vector
= (StartupRoutine
>> 12);
528 IcrLow
.Bits
.DeliveryMode
= LOCAL_APIC_DELIVERY_MODE_STARTUP
;
529 IcrLow
.Bits
.Level
= 1;
530 SendIpi (IcrLow
.Uint32
, ApicId
);
531 if (!StandardSignatureIsAuthenticAMD ()) {
532 MicroSecondDelay (200);
533 SendIpi (IcrLow
.Uint32
, ApicId
);
538 Send an INIT-Start-up-Start-up IPI sequence to all processors excluding self.
540 This function returns after the IPI has been accepted by the target processors.
542 if StartupRoutine >= 1M, then ASSERT.
543 if StartupRoutine is not multiple of 4K, then ASSERT.
545 @param StartupRoutine Points to a start-up routine which is below 1M physical
546 address and 4K aligned.
550 SendInitSipiSipiAllExcludingSelf (
551 IN UINT32 StartupRoutine
554 LOCAL_APIC_ICR_LOW IcrLow
;
556 ASSERT (StartupRoutine
< 0x100000);
557 ASSERT ((StartupRoutine
& 0xfff) == 0);
559 SendInitIpiAllExcludingSelf ();
560 MicroSecondDelay (PcdGet32 (PcdCpuInitIpiDelayInMicroSeconds
));
562 IcrLow
.Bits
.Vector
= (StartupRoutine
>> 12);
563 IcrLow
.Bits
.DeliveryMode
= LOCAL_APIC_DELIVERY_MODE_STARTUP
;
564 IcrLow
.Bits
.Level
= 1;
565 IcrLow
.Bits
.DestinationShorthand
= LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF
;
566 SendIpi (IcrLow
.Uint32
, 0);
567 if (!StandardSignatureIsAuthenticAMD ()) {
568 MicroSecondDelay (200);
569 SendIpi (IcrLow
.Uint32
, 0);
574 Initialize the state of the SoftwareEnable bit in the Local APIC
575 Spurious Interrupt Vector register.
577 @param Enable If TRUE, then set SoftwareEnable to 1
578 If FALSE, then set SoftwareEnable to 0.
583 InitializeLocalApicSoftwareEnable (
590 // Set local APIC software-enabled bit.
592 Svr
.Uint32
= ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET
);
594 if (Svr
.Bits
.SoftwareEnable
== 0) {
595 Svr
.Bits
.SoftwareEnable
= 1;
596 WriteLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET
, Svr
.Uint32
);
599 if (Svr
.Bits
.SoftwareEnable
== 1) {
600 Svr
.Bits
.SoftwareEnable
= 0;
601 WriteLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET
, Svr
.Uint32
);
607 Programming Virtual Wire Mode.
609 This function programs the local APIC for virtual wire mode following
610 the example described in chapter A.3 of the MP 1.4 spec.
612 IOxAPIC is not involved in this type of virtual wire mode.
616 ProgramVirtualWireMode (
621 LOCAL_APIC_LVT_LINT Lint
;
624 // Enable the APIC via SVR and set the spurious interrupt to use Int 00F.
626 Svr
.Uint32
= ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET
);
627 Svr
.Bits
.SpuriousVector
= 0xf;
628 Svr
.Bits
.SoftwareEnable
= 1;
629 WriteLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET
, Svr
.Uint32
);
632 // Program the LINT0 vector entry as ExtInt. Not masked, edge, active high.
634 Lint
.Uint32
= ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET
);
635 Lint
.Bits
.DeliveryMode
= LOCAL_APIC_DELIVERY_MODE_EXTINT
;
636 Lint
.Bits
.InputPinPolarity
= 0;
637 Lint
.Bits
.TriggerMode
= 0;
639 WriteLocalApicReg (XAPIC_LVT_LINT0_OFFSET
, Lint
.Uint32
);
642 // Program the LINT0 vector entry as NMI. Not masked, edge, active high.
644 Lint
.Uint32
= ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET
);
645 Lint
.Bits
.DeliveryMode
= LOCAL_APIC_DELIVERY_MODE_NMI
;
646 Lint
.Bits
.InputPinPolarity
= 0;
647 Lint
.Bits
.TriggerMode
= 0;
649 WriteLocalApicReg (XAPIC_LVT_LINT1_OFFSET
, Lint
.Uint32
);
653 Disable LINT0 & LINT1 interrupts.
655 This function sets the mask flag in the LVT LINT0 & LINT1 registers.
659 DisableLvtInterrupts (
663 LOCAL_APIC_LVT_LINT LvtLint
;
665 LvtLint
.Uint32
= ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET
);
666 LvtLint
.Bits
.Mask
= 1;
667 WriteLocalApicReg (XAPIC_LVT_LINT0_OFFSET
, LvtLint
.Uint32
);
669 LvtLint
.Uint32
= ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET
);
670 LvtLint
.Bits
.Mask
= 1;
671 WriteLocalApicReg (XAPIC_LVT_LINT1_OFFSET
, LvtLint
.Uint32
);
675 Read the initial count value from the init-count register.
677 @return The initial count value read from the init-count register.
681 GetApicTimerInitCount (
685 return ReadLocalApicReg (XAPIC_TIMER_INIT_COUNT_OFFSET
);
689 Read the current count value from the current-count register.
691 @return The current count value read from the current-count register.
695 GetApicTimerCurrentCount (
699 return ReadLocalApicReg (XAPIC_TIMER_CURRENT_COUNT_OFFSET
);
703 Initialize the local APIC timer.
705 The local APIC timer is initialized and enabled.
707 @param DivideValue The divide value for the DCR. It is one of 1,2,4,8,16,32,64,128.
708 If it is 0, then use the current divide value in the DCR.
709 @param InitCount The initial count value.
710 @param PeriodicMode If TRUE, timer mode is peridoic. Othewise, timer mode is one-shot.
711 @param Vector The timer interrupt vector number.
715 InitializeApicTimer (
716 IN UINTN DivideValue
,
718 IN BOOLEAN PeriodicMode
,
723 LOCAL_APIC_LVT_TIMER LvtTimer
;
727 // Ensure local APIC is in software-enabled state.
729 InitializeLocalApicSoftwareEnable (TRUE
);
732 // Program init-count register.
734 WriteLocalApicReg (XAPIC_TIMER_INIT_COUNT_OFFSET
, InitCount
);
736 if (DivideValue
!= 0) {
737 ASSERT (DivideValue
<= 128);
738 ASSERT (DivideValue
== GetPowerOfTwo32 ((UINT32
)DivideValue
));
739 Divisor
= (UINT32
)((HighBitSet32 ((UINT32
)DivideValue
) - 1) & 0x7);
741 Dcr
.Uint32
= ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET
);
742 Dcr
.Bits
.DivideValue1
= (Divisor
& 0x3);
743 Dcr
.Bits
.DivideValue2
= (Divisor
>> 2);
744 WriteLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET
, Dcr
.Uint32
);
748 // Enable APIC timer interrupt with specified timer mode.
750 LvtTimer
.Uint32
= ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET
);
752 LvtTimer
.Bits
.TimerMode
= 1;
754 LvtTimer
.Bits
.TimerMode
= 0;
757 LvtTimer
.Bits
.Mask
= 0;
758 LvtTimer
.Bits
.Vector
= Vector
;
759 WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET
, LvtTimer
.Uint32
);
763 Get the state of the local APIC timer.
765 This function will ASSERT if the local APIC is not software enabled.
767 @param DivideValue Return the divide value for the DCR. It is one of 1,2,4,8,16,32,64,128.
768 @param PeriodicMode Return the timer mode. If TRUE, timer mode is peridoic. Othewise, timer mode is one-shot.
769 @param Vector Return the timer interrupt vector number.
774 OUT UINTN
*DivideValue OPTIONAL
,
775 OUT BOOLEAN
*PeriodicMode OPTIONAL
,
776 OUT UINT8
*Vector OPTIONAL
781 LOCAL_APIC_LVT_TIMER LvtTimer
;
784 // Check the APIC Software Enable/Disable bit (bit 8) in Spurious-Interrupt
786 // This bit will be 1, if local APIC is software enabled.
788 ASSERT ((ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET
) & BIT8
) != 0);
790 if (DivideValue
!= NULL
) {
791 Dcr
.Uint32
= ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET
);
792 Divisor
= Dcr
.Bits
.DivideValue1
| (Dcr
.Bits
.DivideValue2
<< 2);
793 Divisor
= (Divisor
+ 1) & 0x7;
794 *DivideValue
= ((UINTN
)1) << Divisor
;
797 if ((PeriodicMode
!= NULL
) || (Vector
!= NULL
)) {
798 LvtTimer
.Uint32
= ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET
);
799 if (PeriodicMode
!= NULL
) {
800 if (LvtTimer
.Bits
.TimerMode
== 1) {
801 *PeriodicMode
= TRUE
;
803 *PeriodicMode
= FALSE
;
807 if (Vector
!= NULL
) {
808 *Vector
= (UINT8
)LvtTimer
.Bits
.Vector
;
814 Enable the local APIC timer interrupt.
818 EnableApicTimerInterrupt (
822 LOCAL_APIC_LVT_TIMER LvtTimer
;
824 LvtTimer
.Uint32
= ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET
);
825 LvtTimer
.Bits
.Mask
= 0;
826 WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET
, LvtTimer
.Uint32
);
830 Disable the local APIC timer interrupt.
834 DisableApicTimerInterrupt (
838 LOCAL_APIC_LVT_TIMER LvtTimer
;
840 LvtTimer
.Uint32
= ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET
);
841 LvtTimer
.Bits
.Mask
= 1;
842 WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET
, LvtTimer
.Uint32
);
846 Get the local APIC timer interrupt state.
848 @retval TRUE The local APIC timer interrupt is enabled.
849 @retval FALSE The local APIC timer interrupt is disabled.
853 GetApicTimerInterruptState (
857 LOCAL_APIC_LVT_TIMER LvtTimer
;
859 LvtTimer
.Uint32
= ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET
);
860 return (BOOLEAN
)(LvtTimer
.Bits
.Mask
== 0);
864 Send EOI to the local APIC.
872 WriteLocalApicReg (XAPIC_EOI_OFFSET
, 0);
876 Get the 32-bit address that a device should use to send a Message Signaled
877 Interrupt (MSI) to the Local APIC of the currently executing processor.
879 @return 32-bit address used to send an MSI to the Local APIC.
887 LOCAL_APIC_MSI_ADDRESS MsiAddress
;
890 // Return address for an MSI interrupt to be delivered only to the APIC ID
891 // of the currently executing processor.
893 MsiAddress
.Uint32
= 0;
894 MsiAddress
.Bits
.BaseAddress
= 0xFEE;
895 MsiAddress
.Bits
.DestinationId
= GetApicId ();
896 return MsiAddress
.Uint32
;
900 Get the 64-bit data value that a device should use to send a Message Signaled
901 Interrupt (MSI) to the Local APIC of the currently executing processor.
903 If Vector is not in range 0x10..0xFE, then ASSERT().
904 If DeliveryMode is not supported, then ASSERT().
906 @param Vector The 8-bit interrupt vector associated with the MSI.
907 Must be in the range 0x10..0xFE
908 @param DeliveryMode A 3-bit value that specifies how the recept of the MSI
909 is handled. The only supported values are:
910 0: LOCAL_APIC_DELIVERY_MODE_FIXED
911 1: LOCAL_APIC_DELIVERY_MODE_LOWEST_PRIORITY
912 2: LOCAL_APIC_DELIVERY_MODE_SMI
913 4: LOCAL_APIC_DELIVERY_MODE_NMI
914 5: LOCAL_APIC_DELIVERY_MODE_INIT
915 7: LOCAL_APIC_DELIVERY_MODE_EXTINT
917 @param LevelTriggered TRUE specifies a level triggered interrupt.
918 FALSE specifies an edge triggered interrupt.
919 @param AssertionLevel Ignored if LevelTriggered is FALSE.
920 TRUE specifies a level triggered interrupt that active
921 when the interrupt line is asserted.
922 FALSE specifies a level triggered interrupt that active
923 when the interrupt line is deasserted.
925 @return 64-bit data value used to send an MSI to the Local APIC.
931 IN UINTN DeliveryMode
,
932 IN BOOLEAN LevelTriggered
,
933 IN BOOLEAN AssertionLevel
936 LOCAL_APIC_MSI_DATA MsiData
;
938 ASSERT (Vector
>= 0x10 && Vector
<= 0xFE);
939 ASSERT (DeliveryMode
< 8 && DeliveryMode
!= 6 && DeliveryMode
!= 3);
942 MsiData
.Bits
.Vector
= Vector
;
943 MsiData
.Bits
.DeliveryMode
= (UINT32
)DeliveryMode
;
944 if (LevelTriggered
) {
945 MsiData
.Bits
.TriggerMode
= 1;
946 if (AssertionLevel
) {
947 MsiData
.Bits
.Level
= 1;
951 return MsiData
.Uint64
;
955 Get Package ID/Core ID/Thread ID of a processor.
957 The algorithm assumes the target system has symmetry across physical
958 package boundaries with respect to the number of logical processors
959 per package, number of cores per package.
961 @param[in] InitialApicId Initial APIC ID of the target logical processor.
962 @param[out] Package Returns the processor package ID.
963 @param[out] Core Returns the processor core ID.
964 @param[out] Thread Returns the processor thread ID.
968 GetProcessorLocationByApicId (
969 IN UINT32 InitialApicId
,
970 OUT UINT32
*Package OPTIONAL
,
971 OUT UINT32
*Core OPTIONAL
,
972 OUT UINT32
*Thread OPTIONAL
975 BOOLEAN TopologyLeafSupported
;
976 CPUID_VERSION_INFO_EBX VersionInfoEbx
;
977 CPUID_VERSION_INFO_EDX VersionInfoEdx
;
978 CPUID_CACHE_PARAMS_EAX CacheParamsEax
;
979 CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax
;
980 CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx
;
981 CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx
;
982 CPUID_AMD_EXTENDED_CPU_SIG_ECX AmdExtendedCpuSigEcx
;
983 CPUID_AMD_PROCESSOR_TOPOLOGY_EBX AmdProcessorTopologyEbx
;
984 CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX AmdVirPhyAddressSizeEcx
;
985 UINT32 MaxStandardCpuIdIndex
;
986 UINT32 MaxExtendedCpuIdIndex
;
989 UINT32 MaxLogicProcessorsPerPackage
;
990 UINT32 MaxCoresPerPackage
;
995 // Check if the processor is capable of supporting more than one logical processor.
997 AsmCpuid (CPUID_VERSION_INFO
, NULL
, NULL
, NULL
, &VersionInfoEdx
.Uint32
);
998 if (VersionInfoEdx
.Bits
.HTT
== 0) {
999 if (Thread
!= NULL
) {
1007 if (Package
!= NULL
) {
1015 // Assume three-level mapping of APIC ID: Package|Core|Thread.
1021 // Get max index of CPUID
1023 AsmCpuid (CPUID_SIGNATURE
, &MaxStandardCpuIdIndex
, NULL
, NULL
, NULL
);
1024 AsmCpuid (CPUID_EXTENDED_FUNCTION
, &MaxExtendedCpuIdIndex
, NULL
, NULL
, NULL
);
1027 // If the extended topology enumeration leaf is available, it
1028 // is the preferred mechanism for enumerating topology.
1030 TopologyLeafSupported
= FALSE
;
1031 if (MaxStandardCpuIdIndex
>= CPUID_EXTENDED_TOPOLOGY
) {
1033 CPUID_EXTENDED_TOPOLOGY
,
1035 &ExtendedTopologyEax
.Uint32
,
1036 &ExtendedTopologyEbx
.Uint32
,
1037 &ExtendedTopologyEcx
.Uint32
,
1041 // If CPUID.(EAX=0BH, ECX=0H):EBX returns zero and maximum input value for
1042 // basic CPUID information is greater than 0BH, then CPUID.0BH leaf is not
1043 // supported on that processor.
1045 if (ExtendedTopologyEbx
.Uint32
!= 0) {
1046 TopologyLeafSupported
= TRUE
;
1049 // Sub-leaf index 0 (ECX= 0 as input) provides enumeration parameters to extract
1050 // the SMT sub-field of x2APIC ID.
1052 LevelType
= ExtendedTopologyEcx
.Bits
.LevelType
;
1053 ASSERT (LevelType
== CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT
);
1054 ThreadBits
= ExtendedTopologyEax
.Bits
.ApicIdShift
;
1057 // Software must not assume any "level type" encoding
1058 // value to be related to any sub-leaf index, except sub-leaf 0.
1063 CPUID_EXTENDED_TOPOLOGY
,
1065 &ExtendedTopologyEax
.Uint32
,
1067 &ExtendedTopologyEcx
.Uint32
,
1070 LevelType
= ExtendedTopologyEcx
.Bits
.LevelType
;
1071 if (LevelType
== CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE
) {
1072 CoreBits
= ExtendedTopologyEax
.Bits
.ApicIdShift
- ThreadBits
;
1077 } while (LevelType
!= CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID
);
1081 if (!TopologyLeafSupported
) {
1083 // Get logical processor count
1085 AsmCpuid (CPUID_VERSION_INFO
, NULL
, &VersionInfoEbx
.Uint32
, NULL
, NULL
);
1086 MaxLogicProcessorsPerPackage
= VersionInfoEbx
.Bits
.MaximumAddressableIdsForLogicalProcessors
;
1089 // Assume single-core processor
1091 MaxCoresPerPackage
= 1;
1094 // Check for topology extensions on AMD processor
1096 if (StandardSignatureIsAuthenticAMD ()) {
1097 if (MaxExtendedCpuIdIndex
>= CPUID_AMD_PROCESSOR_TOPOLOGY
) {
1098 AsmCpuid (CPUID_EXTENDED_CPU_SIG
, NULL
, NULL
, &AmdExtendedCpuSigEcx
.Uint32
, NULL
);
1099 if (AmdExtendedCpuSigEcx
.Bits
.TopologyExtensions
!= 0) {
1101 // Account for max possible thread count to decode ApicId
1103 AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE
, NULL
, NULL
, &AmdVirPhyAddressSizeEcx
.Uint32
, NULL
);
1104 MaxLogicProcessorsPerPackage
= 1 << AmdVirPhyAddressSizeEcx
.Bits
.ApicIdCoreIdSize
;
1107 // Get cores per processor package
1109 AsmCpuid (CPUID_AMD_PROCESSOR_TOPOLOGY
, NULL
, &AmdProcessorTopologyEbx
.Uint32
, NULL
, NULL
);
1110 MaxCoresPerPackage
= MaxLogicProcessorsPerPackage
/ (AmdProcessorTopologyEbx
.Bits
.ThreadsPerCore
+ 1);
1115 // Extract core count based on CACHE information
1117 if (MaxStandardCpuIdIndex
>= CPUID_CACHE_PARAMS
) {
1118 AsmCpuidEx (CPUID_CACHE_PARAMS
, 0, &CacheParamsEax
.Uint32
, NULL
, NULL
, NULL
);
1119 if (CacheParamsEax
.Uint32
!= 0) {
1120 MaxCoresPerPackage
= CacheParamsEax
.Bits
.MaximumAddressableIdsForLogicalProcessors
+ 1;
1125 ThreadBits
= (UINTN
)(HighBitSet32 (MaxLogicProcessorsPerPackage
/ MaxCoresPerPackage
- 1) + 1);
1126 CoreBits
= (UINTN
)(HighBitSet32 (MaxCoresPerPackage
- 1) + 1);
1129 if (Thread
!= NULL
) {
1130 *Thread
= InitialApicId
& ((1 << ThreadBits
) - 1);
1134 *Core
= (InitialApicId
>> ThreadBits
) & ((1 << CoreBits
) - 1);
1137 if (Package
!= NULL
) {
1138 *Package
= (InitialApicId
>> (ThreadBits
+ CoreBits
));
1143 Get Package ID/Die ID/Tile ID/Module ID/Core ID/Thread ID of a processor.
1145 The algorithm assumes the target system has symmetry across physical
1146 package boundaries with respect to the number of threads per core, number of
1147 cores per module, number of modules per tile, number of tiles per die, number
1148 of dies per package.
1150 @param[in] InitialApicId Initial APIC ID of the target logical processor.
1151 @param[out] Package Returns the processor package ID.
1152 @param[out] Die Returns the processor die ID.
1153 @param[out] Tile Returns the processor tile ID.
1154 @param[out] Module Returns the processor module ID.
1155 @param[out] Core Returns the processor core ID.
1156 @param[out] Thread Returns the processor thread ID.
1160 GetProcessorLocation2ByApicId (
1161 IN UINT32 InitialApicId
,
1162 OUT UINT32
*Package OPTIONAL
,
1163 OUT UINT32
*Die OPTIONAL
,
1164 OUT UINT32
*Tile OPTIONAL
,
1165 OUT UINT32
*Module OPTIONAL
,
1166 OUT UINT32
*Core OPTIONAL
,
1167 OUT UINT32
*Thread OPTIONAL
1170 CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax
;
1171 CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx
;
1172 UINT32 MaxStandardCpuIdIndex
;
1175 UINT32 Bits
[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE
+ 2];
1176 UINT32
*Location
[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE
+ 2];
1178 for (LevelType
= 0; LevelType
< ARRAY_SIZE (Bits
); LevelType
++) {
1179 Bits
[LevelType
] = 0;
1183 // Get max index of CPUID
1185 AsmCpuid (CPUID_SIGNATURE
, &MaxStandardCpuIdIndex
, NULL
, NULL
, NULL
);
1186 if (MaxStandardCpuIdIndex
< CPUID_V2_EXTENDED_TOPOLOGY
) {
1195 if (Module
!= NULL
) {
1199 GetProcessorLocationByApicId (InitialApicId
, Package
, Core
, Thread
);
1204 // If the V2 extended topology enumeration leaf is available, it
1205 // is the preferred mechanism for enumerating topology.
1207 for (Index
= 0; ; Index
++) {
1209 CPUID_V2_EXTENDED_TOPOLOGY
,
1211 &ExtendedTopologyEax
.Uint32
,
1213 &ExtendedTopologyEcx
.Uint32
,
1217 LevelType
= ExtendedTopologyEcx
.Bits
.LevelType
;
1220 // first level reported should be SMT.
1222 ASSERT ((Index
!= 0) || (LevelType
== CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT
));
1223 if (LevelType
== CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID
) {
1227 ASSERT (LevelType
< ARRAY_SIZE (Bits
));
1228 Bits
[LevelType
] = ExtendedTopologyEax
.Bits
.ApicIdShift
;
1231 for (LevelType
= CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE
; LevelType
< ARRAY_SIZE (Bits
); LevelType
++) {
1233 // If there are more levels between level-1 (low-level) and level-2 (high-level), the unknown levels will be ignored
1234 // and treated as an extension of the last known level (i.e., level-1 in this case).
1236 if (Bits
[LevelType
] == 0) {
1237 Bits
[LevelType
] = Bits
[LevelType
- 1];
1241 Location
[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE
+ 1] = Package
;
1242 Location
[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE
] = Die
;
1243 Location
[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_TILE
] = Tile
;
1244 Location
[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_MODULE
] = Module
;
1245 Location
[CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE
] = Core
;
1246 Location
[CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT
] = Thread
;
1248 Bits
[CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE
+ 1] = 32;
1250 for ( LevelType
= CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT
1251 ; LevelType
<= CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE
+ 1
1255 if (Location
[LevelType
] != NULL
) {
1257 // Bits[i] holds the number of bits to shift right on x2APIC ID to get a unique
1258 // topology ID of the next level type.
1260 *Location
[LevelType
] = InitialApicId
>> Bits
[LevelType
- 1];
1263 // Bits[i] - Bits[i-1] holds the number of bits for the next ONE level type.
1265 *Location
[LevelType
] &= (1 << (Bits
[LevelType
] - Bits
[LevelType
- 1])) - 1;