1 ;------------------------------------------------------------------------------ ;
2 ; Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
3 ; This program and the accompanying materials
4 ; are licensed and made available under the terms and conditions of the BSD License
5 ; which accompanies this distribution. The full text of the license may be found at
6 ; http://opensource.org/licenses/bsd-license.php.
8 ; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
9 ; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
17 ; Code template of the SMI handler for a particular processor
19 ;-------------------------------------------------------------------------------
22 ; Variables referenced by C code
24 EXTERNDEF SmiRendezvous:PROC
25 EXTERNDEF CpuSmmDebugEntry:PROC
26 EXTERNDEF CpuSmmDebugExit:PROC
27 EXTERNDEF gcStmSmiHandlerTemplate:BYTE
28 EXTERNDEF gcStmSmiHandlerSize:WORD
29 EXTERNDEF gcStmSmiHandlerOffset:WORD
30 EXTERNDEF gStmSmiCr3:DWORD
31 EXTERNDEF gStmSmiStack:DWORD
32 EXTERNDEF gStmSmbase:DWORD
33 EXTERNDEF gStmXdSupported:BYTE
34 EXTERNDEF gStmSmiHandlerIdtr:FWORD
36 MSR_IA32_MISC_ENABLE EQU 1A0h
37 MSR_EFER EQU 0c0000080h
41 ; Constants relating to TXT_PROCESSOR_SMM_DESCRIPTOR
51 ; Constants relating to CPU State Save Area
56 PROTECT_MODE_CS EQU 08h
57 PROTECT_MODE_DS EQU 20h
64 gcStmSmiHandlerTemplate LABEL BYTE
68 ; The encoding of BX in 16-bit addressing mode is the same as of RDI in 64-
69 ; bit addressing mode. And that coincidence has been used in the following
70 ; "64-bit like" 16-bit code. Be aware that once RDI is referenced as a
71 ; base address register, it is actually BX that is referenced.
73 DB 0bbh ; mov bx, imm16
74 DW offset _StmGdtDesc - _StmSmiEntryPoint + 8000h ; bx = GdtDesc offset
76 DB 2eh, 0a1h ; mov ax, cs:[offset16]
77 DW DSC_OFFSET + DSC_GDTSIZ
80 mov [rdi], eax ; mov cs:[bx], ax
81 DB 66h, 2eh, 0a1h ; mov eax, cs:[offset16]
82 DW DSC_OFFSET + DSC_GDTPTR
84 mov [rdi + 2], ax ; mov cs:[bx + 2], eax
86 lgdt fword ptr [rdi] ; lgdt fword ptr cs:[bx]
87 ; Patch ProtectedMode Segment
88 DB 0b8h ; mov ax, imm16
89 DW PROTECT_MODE_CS ; set AX for segment directly
91 mov [rdi - 2], eax ; mov cs:[bx - 2], ax
92 ; Patch ProtectedMode entry
93 DB 66h, 0bfh ; mov edi, SMBASE
95 lea ax, [edi + (@ProtectedMode - _StmSmiEntryPoint) + 8000h]
97 mov [rdi - 6], ax ; mov cs:[bx - 6], eax
98 ; Switch into @ProtectedMode
112 mov ax, PROTECT_MODE_DS
118 DB 0bch ; mov esp, imm32
123 DB 0b8h ; mov eax, offset gStmSmiCr3
126 mov eax, 668h ; as cr4.PGE is not set here, refresh cr3
127 mov cr4, rax ; in PreModifyMtrrs() to flush TLB.
129 sub esp, 8 ; reserve room in stack
131 mov eax, [rsp + 2] ; eax = GDT base
134 mov [rax + TSS_SEGMENT + 5], dl ; clear busy flag
138 ; enable NXE if supported
139 DB 0b0h ; mov al, imm8
144 ; Check XD disable bit
146 mov ecx, MSR_IA32_MISC_ENABLE
149 push rdx ; save MSR_IA32_MISC_ENABLE[63-32]
150 test edx, BIT2 ; MSR_IA32_MISC_ENABLE[34]
152 and dx, 0FFFBh ; clear XD Disable bit if it is set
157 or ax, MSR_EFER_XD ; enable NXE
164 ; Switch into @LongMode
165 push LONG_MODE_CS ; push cs hardcore here
166 call Base ; push return address for retf later
168 add dword ptr [rsp], @LongMode - Base; offset for far retf, seg is the 1st arg
172 or ah, 1 ; enable LME
175 or ebx, 080010023h ; enable paging + WP + NE + MP + PE
178 @LongMode: ; long mode (64-bit code) starts here
179 mov rax, offset gStmSmiHandlerIdtr
181 lea ebx, [rdi + DSC_OFFSET]
182 mov ax, [rbx + DSC_DS]
184 mov ax, [rbx + DSC_OTHERSEG]
188 mov ax, [rbx + DSC_SS]
192 mov rbx, [rsp + 0x08] ; rbx <- CpuIndex
204 mov rax, CpuSmmDebugEntry
208 mov rax, SmiRendezvous ; rax <- absolute addr of SmiRedezvous
212 mov rax, CpuSmmDebugExit
218 ; Restore FP registers
225 mov rax, offset ASM_PFX(gStmXdSupported)
229 pop rdx ; get saved MSR_IA32_MISC_ENABLE[63-32]
232 mov ecx, MSR_IA32_MISC_ENABLE
234 or dx, BIT2 ; set XD Disable bit if it was set before entering into SMM
242 ; Check XD disable bit
245 mov rax, offset ASM_PFX(gStmXdSupported)
249 mov ecx, MSR_IA32_MISC_ENABLE
251 mov r8, rdx ; save MSR_IA32_MISC_ENABLE[63-32]
252 test edx, BIT2 ; MSR_IA32_MISC_ENABLE[34]
254 and dx, 0FFFBh ; clear XD Disable bit if it is set
259 or ax, MSR_EFER_XD ; enable NXE
264 ; below step is needed, because STM does not run above code.
265 ; we have to run below code to set IDT/CR0/CR4
266 mov rax, offset gStmSmiHandlerIdtr
270 or eax, 80010023h ; enable paging + WP + NE + MP + PE
273 mov eax, 668h ; as cr4.PGE is not set here, refresh cr3
274 mov cr4, rax ; in PreModifyMtrrs() to flush TLB.
278 gcStmSmiHandlerSize DW $ - _StmSmiEntryPoint
279 gcStmSmiHandlerOffset DW _StmSmiHandler - _StmSmiEntryPoint