1 ;------------------------------------------------------------------------------ ;
2 ; Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
3 ; This program and the accompanying materials
4 ; are licensed and made available under the terms and conditions of the BSD License
5 ; which accompanies this distribution. The full text of the license may be found at
6 ; http://opensource.org/licenses/bsd-license.php.
8 ; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
9 ; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
17 ; Code template of the SMI handler for a particular processor
19 ;-------------------------------------------------------------------------------
25 MSR_IA32_MISC_ENABLE EQU 1A0h
26 MSR_EFER EQU 0c0000080h
30 ; Constants relating to PROCESSOR_SMM_DESCRIPTOR
40 PROTECT_MODE_CS EQU 08h
41 PROTECT_MODE_DS EQU 20h
45 CpuSmmDebugEntry PROTO C
46 CpuSmmDebugExit PROTO C
48 EXTERNDEF gcSmiHandlerTemplate:BYTE
49 EXTERNDEF gcSmiHandlerSize:WORD
50 EXTERNDEF gSmiCr3:DWORD
51 EXTERNDEF gSmiStack:DWORD
52 EXTERNDEF gSmbase:DWORD
53 EXTERNDEF mXdSupported:BYTE
54 EXTERNDEF FeaturePcdGet (PcdCpuSmmStackGuard):BYTE
55 EXTERNDEF gSmiHandlerIdtr:FWORD
59 gcSmiHandlerTemplate LABEL BYTE
62 DB 0bbh ; mov bx, imm16
63 DW offset _GdtDesc - _SmiEntryPoint + 8000h
64 DB 2eh, 0a1h ; mov ax, cs:[offset16]
65 DW DSC_OFFSET + DSC_GDTSIZ
67 mov cs:[edi], eax ; mov cs:[bx], ax
68 DB 66h, 2eh, 0a1h ; mov eax, cs:[offset16]
69 DW DSC_OFFSET + DSC_GDTPTR
70 mov cs:[edi + 2], ax ; mov cs:[bx + 2], eax
71 mov bp, ax ; ebp = GDT base
73 lgdt fword ptr cs:[edi] ; lgdt fword ptr cs:[bx]
74 ; Patch ProtectedMode Segment
75 DB 0b8h ; mov ax, imm16
76 DW PROTECT_MODE_CS ; set AX for segment directly
77 mov cs:[edi - 2], eax ; mov cs:[bx - 2], ax
78 ; Patch ProtectedMode entry
79 DB 66h, 0bfh ; mov edi, SMBASE
82 lea ax, [edi + (@32bit - _SmiEntryPoint) + 8000h]
83 mov cs:[edi - 6], ax ; mov cs:[bx - 6], eax
96 mov ax, PROTECT_MODE_DS
102 DB 0bch ; mov esp, imm32
104 mov eax, offset gSmiHandlerIdtr
109 DB 0b8h ; mov eax, imm32
113 ; Need to test for CR4 specific bit support
116 cpuid ; use CPUID to determine if specific CR4 bits are supported
117 xor eax, eax ; Clear EAX
118 test edx, BIT2 ; Check for DE capabilities
122 test edx, BIT6 ; Check for PAE capabilities
126 test edx, BIT7 ; Check for MCE capabilities
130 test edx, BIT24 ; Check for FXSR capabilities
134 test edx, BIT25 ; Check for SSE capabilities
137 @@: ; as cr4.PGE is not set here, refresh cr3
138 mov cr4, eax ; in PreModifyMtrrs() to flush TLB.
140 cmp FeaturePcdGet (PcdCpuSmmStackGuard), 0
143 mov byte ptr [ebp + TSS_SEGMENT + 5], 89h ; clear busy flag
148 ; enable NXE if supported
149 DB 0b0h ; mov al, imm8
154 ; Check XD disable bit
156 mov ecx, MSR_IA32_MISC_ENABLE
158 push edx ; save MSR_IA32_MISC_ENABLE[63-32]
159 test edx, BIT2 ; MSR_IA32_MISC_ENABLE[34]
161 and dx, 0FFFBh ; clear XD Disable bit if it is set
166 or ax, MSR_EFER_XD ; enable NXE
174 or ebx, 080010023h ; enable paging + WP + NE + MP + PE
176 lea ebx, [edi + DSC_OFFSET]
177 mov ax, [ebx + DSC_DS]
179 mov ax, [ebx + DSC_OTHERSEG]
183 mov ax, [ebx + DSC_SS]
186 ; jmp _SmiHandler ; instruction is not needed
189 mov ebx, [esp + 4] ; CPU Index
191 mov eax, CpuSmmDebugEntry
196 mov eax, SmiRendezvous
201 mov eax, CpuSmmDebugExit
205 mov eax, offset mXdSupported
209 pop edx ; get saved MSR_IA32_MISC_ENABLE[63-32]
212 mov ecx, MSR_IA32_MISC_ENABLE
214 or dx, BIT2 ; set XD Disable bit if it was set before entering into SMM
221 gcSmiHandlerSize DW $ - _SmiEntryPoint