1 ;------------------------------------------------------------------------------ ;
2 ; Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
3 ; This program and the accompanying materials
4 ; are licensed and made available under the terms and conditions of the BSD License
5 ; which accompanies this distribution. The full text of the license may be found at
6 ; http://opensource.org/licenses/bsd-license.php.
8 ; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
9 ; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
17 ; Code template of the SMI handler for a particular processor
19 ;-------------------------------------------------------------------------------
21 %define MSR_IA32_MISC_ENABLE 0x1A0
22 %define MSR_EFER 0xc0000080
23 %define MSR_EFER_XD 0x800
26 ; Constants relating to PROCESSOR_SMM_DESCRIPTOR
28 %define DSC_OFFSET 0xfb00
29 %define DSC_GDTPTR 0x30
30 %define DSC_GDTSIZ 0x38
34 %define DSC_OTHERSEG 20
36 %define PROTECT_MODE_CS 0x8
37 %define PROTECT_MODE_DS 0x20
38 %define TSS_SEGMENT 0x40
40 extern ASM_PFX(SmiRendezvous)
41 extern ASM_PFX(FeaturePcdGet (PcdCpuSmmStackGuard))
42 extern ASM_PFX(CpuSmmDebugEntry)
43 extern ASM_PFX(CpuSmmDebugExit)
45 global ASM_PFX(gcSmiHandlerTemplate)
46 global ASM_PFX(gcSmiHandlerSize)
47 global ASM_PFX(gSmiCr3)
48 global ASM_PFX(gSmiStack)
49 global ASM_PFX(gSmbase)
50 global ASM_PFX(mXdSupported)
51 extern ASM_PFX(gSmiHandlerIdtr)
56 ASM_PFX(gcSmiHandlerTemplate):
58 mov bx, _GdtDesc - _SmiEntryPoint + 0x8000
59 mov ax,[cs:DSC_OFFSET + DSC_GDTSIZ]
62 mov eax, [cs:DSC_OFFSET + DSC_GDTPTR]
64 mov ebp, eax ; ebp = GDT base
65 o32 lgdt [cs:bx] ; lgdt fword ptr cs:[bx]
66 mov ax, PROTECT_MODE_CS
68 DB 0x66, 0xbf ; mov edi, SMBASE
69 ASM_PFX(gSmbase): DD 0
70 lea eax, [edi + (@32bit - _SmiEntryPoint) + 0x8000]
83 mov ax, PROTECT_MODE_DS
89 DB 0xbc ; mov esp, imm32
90 ASM_PFX(gSmiStack): DD 0
91 mov eax, ASM_PFX(gSmiHandlerIdtr)
96 DB 0xb8 ; mov eax, imm32
97 ASM_PFX(gSmiCr3): DD 0
100 ; Need to test for CR4 specific bit support
103 cpuid ; use CPUID to determine if specific CR4 bits are supported
104 xor eax, eax ; Clear EAX
105 test edx, BIT2 ; Check for DE capabilities
109 test edx, BIT6 ; Check for PAE capabilities
113 test edx, BIT7 ; Check for MCE capabilities
117 test edx, BIT24 ; Check for FXSR capabilities
121 test edx, BIT25 ; Check for SSE capabilities
124 .4: ; as cr4.PGE is not set here, refresh cr3
125 mov cr4, eax ; in PreModifyMtrrs() to flush TLB.
127 cmp byte [dword ASM_PFX(FeaturePcdGet (PcdCpuSmmStackGuard))], 0
130 mov byte [ebp + TSS_SEGMENT + 5], 0x89 ; clear busy flag
135 ; enable NXE if supported
136 DB 0b0h ; mov al, imm8
137 ASM_PFX(mXdSupported): DB 1
141 ; Check XD disable bit
143 mov ecx, MSR_IA32_MISC_ENABLE
145 push edx ; save MSR_IA32_MISC_ENABLE[63-32]
146 test edx, BIT2 ; MSR_IA32_MISC_ENABLE[34]
148 and dx, 0xFFFB ; clear XD Disable bit if it is set
153 or ax, MSR_EFER_XD ; enable NXE
161 or ebx, 0x80010023 ; enable paging + WP + NE + MP + PE
163 lea ebx, [edi + DSC_OFFSET]
164 mov ax, [ebx + DSC_DS]
166 mov ax, [ebx + DSC_OTHERSEG]
170 mov ax, [ebx + DSC_SS]
173 ; jmp _SmiHandler ; instruction is not needed
175 global ASM_PFX(SmiHandler)
177 mov ebx, [esp + 4] ; CPU Index
179 mov eax, ASM_PFX(CpuSmmDebugEntry)
184 mov eax, ASM_PFX(SmiRendezvous)
189 mov eax, ASM_PFX(CpuSmmDebugExit)
193 mov eax, ASM_PFX(mXdSupported)
197 pop edx ; get saved MSR_IA32_MISC_ENABLE[63-32]
200 mov ecx, MSR_IA32_MISC_ENABLE
202 or dx, BIT2 ; set XD Disable bit if it was set before entering into SMM
208 ASM_PFX(gcSmiHandlerSize): DW $ - _SmiEntryPoint
210 global ASM_PFX(PiSmmCpuSmiEntryFixupAddress)
211 ASM_PFX(PiSmmCpuSmiEntryFixupAddress):