UefiCpuPkg/PiSmmCpuDxeSmm: remove unneeded DBs from IA32 SmmStartup()

The SmmStartup() executes in SMM, which is very similar to real mode. Add
"BITS 16" before it and "BITS 32" after it (just before the @32bit label).

Remove the manual 0x66 operand-size override prefixes, for selecting
32-bit operands -- the sizes of our operands trigger NASM to insert the
prefixes automatically in almost every spot. The one place where we have
to add it back manually is the LGDT instruction. (The 0x67 address-size
override prefix is also auto-generated.)

This patch causes NASM to generate byte-identical object code (determined
by disassembling both the pre-patch and post-patch versions, and comparing
the listings), except:

> @@ -158,7 +158,7 @@
>  00000142  6689D3            mov ebx,edx
>  00000145  66B800000000      mov eax,0x0
>  0000014B  0F22D8            mov cr3,eax
> -0000014E  67662E0F0155F6    o32 lgdt [cs:ebp-0xa]
> +0000014E  2E66670F0155F6    o32 lgdt [cs:ebp-0xa]
>  00000155  66B800000000      mov eax,0x0
>  0000015B  0F22E0            mov cr4,eax
>  0000015E  66B9800000C0      mov ecx,0xc0000080

The only difference is the prefix list order, it changes from:

- 0x67, 0x66, 0x2E

to

- 0x2E, 0x66, 0x67

(0x2E is "CS segment override").

Cc: Eric Dong <eric.dong@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=866
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm
index 08534dba64b71cc11065638f5d3af7bd67b9710f..9231aa5b3deda5fefdbcd4f3c772a0e60bd98633 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm
@@ -41,24 +41,21 @@ ASM_PFX(gcSmiInitGdtr):
             DQ      0\r
 \r
 global ASM_PFX(SmmStartup)\r
+\r
+BITS 16\r
 ASM_PFX(SmmStartup):\r
-    DB      0x66\r
     mov     eax, 0x80000001             ; read capability\r
     cpuid\r
-    DB      0x66\r
     mov     ebx, edx                    ; rdmsr will change edx. keep it in ebx.\r
     DB      0x66, 0xb8                  ; mov eax, imm32\r
 ASM_PFX(gSmmCr3): DD 0\r
     mov     cr3, eax\r
-    DB      0x67, 0x66\r
-    lgdt    [cs:ebp + (ASM_PFX(gcSmiInitGdtr) - ASM_PFX(SmmStartup))]\r
+o32 lgdt    [cs:ebp + (ASM_PFX(gcSmiInitGdtr) - ASM_PFX(SmmStartup))]\r
     DB      0x66, 0xb8                  ; mov eax, imm32\r
 ASM_PFX(gSmmCr4): DD 0\r
     mov     cr4, eax\r
-    DB      0x66\r
     mov     ecx, 0xc0000080             ; IA32_EFER MSR\r
     rdmsr\r
-    DB      0x66\r
     test    ebx, BIT20                  ; check NXE capability\r
     jz      .1\r
     or      ah, BIT3                    ; set NXE bit\r
@@ -66,12 +63,14 @@ ASM_PFX(gSmmCr4): DD 0
 .1:\r
     DB      0x66, 0xb8                  ; mov eax, imm32\r
 ASM_PFX(gSmmCr0): DD 0\r
-    DB      0xbf, PROTECT_MODE_DS, 0    ; mov di, PROTECT_MODE_DS\r
+    mov     di, PROTECT_MODE_DS\r
     mov     cr0, eax\r
     DB      0x66, 0xea                  ; jmp far [ptr48]\r
 ASM_PFX(gSmmJmpAddr):\r
     DD      @32bit\r
     DW      PROTECT_MODE_CS\r
+\r
+BITS 32\r
 @32bit:\r
     mov     ds, edi\r
     mov     es, edi\r