2 Agent Module to load other modules to deploy SMM Entry Vector for X86 CPU.
4 Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
5 This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
15 #include "PiSmmCpuDxeSmm.h"
18 // SMM CPU Private Data structure that contains SMM Configuration Protocol
19 // along its supporting fields.
21 SMM_CPU_PRIVATE_DATA mSmmCpuPrivateData
= {
22 SMM_CPU_PRIVATE_DATA_SIGNATURE
, // Signature
24 NULL
, // Pointer to ProcessorInfo array
25 NULL
, // Pointer to Operation array
26 NULL
, // Pointer to CpuSaveStateSize array
27 NULL
, // Pointer to CpuSaveState array
28 { {0} }, // SmmReservedSmramRegion
30 SmmStartupThisAp
, // SmmCoreEntryContext.SmmStartupThisAp
31 0, // SmmCoreEntryContext.CurrentlyExecutingCpu
32 0, // SmmCoreEntryContext.NumberOfCpus
33 NULL
, // SmmCoreEntryContext.CpuSaveStateSize
34 NULL
// SmmCoreEntryContext.CpuSaveState
38 mSmmCpuPrivateData
.SmmReservedSmramRegion
, // SmmConfiguration.SmramReservedRegions
39 RegisterSmmEntry
// SmmConfiguration.RegisterSmmEntry
43 CPU_HOT_PLUG_DATA mCpuHotPlugData
= {
44 CPU_HOT_PLUG_DATA_REVISION_1
, // Revision
45 0, // Array Length of SmBase and APIC ID
46 NULL
, // Pointer to APIC ID array
47 NULL
, // Pointer to SMBASE array
54 // Global pointer used to access mSmmCpuPrivateData from outside and inside SMM
56 SMM_CPU_PRIVATE_DATA
*gSmmCpuPrivate
= &mSmmCpuPrivateData
;
59 // SMM Relocation variables
61 volatile BOOLEAN
*mRebased
;
62 volatile BOOLEAN mIsBsp
;
65 /// Handle for the SMM CPU Protocol
67 EFI_HANDLE mSmmCpuHandle
= NULL
;
70 /// SMM CPU Protocol instance
72 EFI_SMM_CPU_PROTOCOL mSmmCpu
= {
77 EFI_CPU_INTERRUPT_HANDLER mExternalVectorTable
[EXCEPTION_VECTOR_NUMBER
];
80 // SMM stack information
82 UINTN mSmmStackArrayBase
;
83 UINTN mSmmStackArrayEnd
;
86 UINTN mMaxNumberOfCpus
= 1;
87 UINTN mNumberOfCpus
= 1;
90 // SMM ready to lock flag
92 BOOLEAN mSmmReadyToLock
= FALSE
;
95 // Global used to cache PCD for SMM Code Access Check enable
97 BOOLEAN mSmmCodeAccessCheckEnable
= FALSE
;
100 // Spin lock used to serialize setting of SMM Code Access Check feature
102 SPIN_LOCK
*mConfigSmmCodeAccessCheckLock
= NULL
;
105 Initialize IDT to setup exception handlers for SMM.
114 BOOLEAN InterruptState
;
115 IA32_DESCRIPTOR DxeIdtr
;
117 // Disable Interrupt and save DXE IDT table
119 InterruptState
= SaveAndDisableInterrupts ();
120 AsmReadIdtr (&DxeIdtr
);
122 // Load SMM temporary IDT table
124 AsmWriteIdtr (&gcSmiIdtr
);
126 // Setup SMM default exception handlers, SMM IDT table
127 // will be updated and saved in gcSmiIdtr
129 Status
= InitializeCpuExceptionHandlers (NULL
);
130 ASSERT_EFI_ERROR (Status
);
132 // Restore DXE IDT table and CPU interrupt
134 AsmWriteIdtr ((IA32_DESCRIPTOR
*) &DxeIdtr
);
135 SetInterruptState (InterruptState
);
139 Search module name by input IP address and output it.
141 @param CallerIpAddress Caller instruction pointer.
146 IN UINTN CallerIpAddress
150 EFI_IMAGE_DOS_HEADER
*DosHdr
;
151 EFI_IMAGE_OPTIONAL_HEADER_PTR_UNION Hdr
;
153 UINT64 DumpIpAddress
;
158 Pe32Data
= CallerIpAddress
& ~(SIZE_4KB
- 1);
159 while (Pe32Data
!= 0) {
160 DosHdr
= (EFI_IMAGE_DOS_HEADER
*) Pe32Data
;
161 if (DosHdr
->e_magic
== EFI_IMAGE_DOS_SIGNATURE
) {
163 // DOS image header is present, so read the PE header after the DOS image header.
165 Hdr
.Pe32
= (EFI_IMAGE_NT_HEADERS32
*)(Pe32Data
+ (UINTN
) ((DosHdr
->e_lfanew
) & 0x0ffff));
167 // Make sure PE header address does not overflow and is less than the initial address.
169 if (((UINTN
)Hdr
.Pe32
> Pe32Data
) && ((UINTN
)Hdr
.Pe32
< CallerIpAddress
)) {
170 if (Hdr
.Pe32
->Signature
== EFI_IMAGE_NT_SIGNATURE
) {
180 // Not found the image base, check the previous aligned address
182 Pe32Data
-= SIZE_4KB
;
185 DumpIpAddress
= CallerIpAddress
;
186 DEBUG ((EFI_D_ERROR
, "It is invoked from the instruction before IP(0x%lx)", DumpIpAddress
));
189 PdbPointer
= PeCoffLoaderGetPdbPointer ((VOID
*) Pe32Data
);
190 if (PdbPointer
!= NULL
) {
191 DEBUG ((EFI_D_ERROR
, " in module (%a)", PdbPointer
));
197 Read information from the CPU save state.
199 @param This EFI_SMM_CPU_PROTOCOL instance
200 @param Width The number of bytes to read from the CPU save state.
201 @param Register Specifies the CPU register to read form the save state.
202 @param CpuIndex Specifies the zero-based index of the CPU save state.
203 @param Buffer Upon return, this holds the CPU register value read from the save state.
205 @retval EFI_SUCCESS The register was read from Save State
206 @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor
207 @retval EFI_INVALID_PARAMTER This or Buffer is NULL.
213 IN CONST EFI_SMM_CPU_PROTOCOL
*This
,
215 IN EFI_SMM_SAVE_STATE_REGISTER Register
,
223 // Retrieve pointer to the specified CPU's SMM Save State buffer
225 if ((CpuIndex
>= gSmst
->NumberOfCpus
) || (Buffer
== NULL
)) {
226 return EFI_INVALID_PARAMETER
;
230 // Check for special EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID
232 if (Register
== EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID
) {
234 // The pseudo-register only supports the 64-bit size specified by Width.
236 if (Width
!= sizeof (UINT64
)) {
237 return EFI_INVALID_PARAMETER
;
240 // If the processor is in SMM at the time the SMI occurred,
241 // the pseudo register value for EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID is returned in Buffer.
242 // Otherwise, EFI_NOT_FOUND is returned.
244 if (*(mSmmMpSyncData
->CpuData
[CpuIndex
].Present
)) {
245 *(UINT64
*)Buffer
= gSmmCpuPrivate
->ProcessorInfo
[CpuIndex
].ProcessorId
;
248 return EFI_NOT_FOUND
;
252 if (!(*(mSmmMpSyncData
->CpuData
[CpuIndex
].Present
))) {
253 return EFI_INVALID_PARAMETER
;
256 Status
= SmmCpuFeaturesReadSaveStateRegister (CpuIndex
, Register
, Width
, Buffer
);
257 if (Status
== EFI_UNSUPPORTED
) {
258 Status
= ReadSaveStateRegister (CpuIndex
, Register
, Width
, Buffer
);
264 Write data to the CPU save state.
266 @param This EFI_SMM_CPU_PROTOCOL instance
267 @param Width The number of bytes to read from the CPU save state.
268 @param Register Specifies the CPU register to write to the save state.
269 @param CpuIndex Specifies the zero-based index of the CPU save state
270 @param Buffer Upon entry, this holds the new CPU register value.
272 @retval EFI_SUCCESS The register was written from Save State
273 @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor
274 @retval EFI_INVALID_PARAMTER ProcessorIndex or Width is not correct
280 IN CONST EFI_SMM_CPU_PROTOCOL
*This
,
282 IN EFI_SMM_SAVE_STATE_REGISTER Register
,
284 IN CONST VOID
*Buffer
290 // Retrieve pointer to the specified CPU's SMM Save State buffer
292 if ((CpuIndex
>= gSmst
->NumberOfCpus
) || (Buffer
== NULL
)) {
293 return EFI_INVALID_PARAMETER
;
297 // Writes to EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID are ignored
299 if (Register
== EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID
) {
303 if (!mSmmMpSyncData
->CpuData
[CpuIndex
].Present
) {
304 return EFI_INVALID_PARAMETER
;
307 Status
= SmmCpuFeaturesWriteSaveStateRegister (CpuIndex
, Register
, Width
, Buffer
);
308 if (Status
== EFI_UNSUPPORTED
) {
309 Status
= WriteSaveStateRegister (CpuIndex
, Register
, Width
, Buffer
);
316 C function for SMI handler. To change all processor's SMMBase Register.
329 // Update SMM IDT entries' code segment and load IDT
331 AsmWriteIdtr (&gcSmiIdtr
);
332 ApicId
= GetApicId ();
334 ASSERT (mNumberOfCpus
<= PcdGet32 (PcdCpuMaxLogicalProcessorNumber
));
336 for (Index
= 0; Index
< mNumberOfCpus
; Index
++) {
337 if (ApicId
== (UINT32
)gSmmCpuPrivate
->ProcessorInfo
[Index
].ProcessorId
) {
339 // Initialize SMM specific features on the currently executing CPU
341 SmmCpuFeaturesInitializeProcessor (
344 gSmmCpuPrivate
->ProcessorInfo
,
350 // Check XD and BTS features on each processor on normal boot
352 CheckFeatureSupported ();
357 // BSP rebase is already done above.
358 // Initialize private data during S3 resume
360 InitializeMpSyncData ();
364 // Hook return after RSM to set SMM re-based flag
366 SemaphoreHook (Index
, &mRebased
[Index
]);
375 Relocate SmmBases for each processor.
377 Execute on first boot and all S3 resumes
386 UINT8 BakBuf
[BACK_BUF_SIZE
];
387 SMRAM_SAVE_STATE_MAP BakBuf2
;
388 SMRAM_SAVE_STATE_MAP
*CpuStatePtr
;
395 // Make sure the reserved size is large enough for procedure SmmInitTemplate.
397 ASSERT (sizeof (BakBuf
) >= gcSmmInitSize
);
400 // Patch ASM code template with current CR0, CR3, and CR4 values
402 gSmmCr0
= (UINT32
)AsmReadCr0 ();
403 gSmmCr3
= (UINT32
)AsmReadCr3 ();
404 gSmmCr4
= (UINT32
)AsmReadCr4 ();
407 // Patch GDTR for SMM base relocation
409 gcSmiInitGdtr
.Base
= gcSmiGdtr
.Base
;
410 gcSmiInitGdtr
.Limit
= gcSmiGdtr
.Limit
;
412 U8Ptr
= (UINT8
*)(UINTN
)(SMM_DEFAULT_SMBASE
+ SMM_HANDLER_OFFSET
);
413 CpuStatePtr
= (SMRAM_SAVE_STATE_MAP
*)(UINTN
)(SMM_DEFAULT_SMBASE
+ SMRAM_SAVE_STATE_MAP_OFFSET
);
416 // Backup original contents at address 0x38000
418 CopyMem (BakBuf
, U8Ptr
, sizeof (BakBuf
));
419 CopyMem (&BakBuf2
, CpuStatePtr
, sizeof (BakBuf2
));
422 // Load image for relocation
424 CopyMem (U8Ptr
, gcSmmInitTemplate
, gcSmmInitSize
);
427 // Retrieve the local APIC ID of current processor
429 ApicId
= GetApicId ();
432 // Relocate SM bases for all APs
433 // This is APs' 1st SMI - rebase will be done here, and APs' default SMI handler will be overridden by gcSmmInitTemplate
436 BspIndex
= (UINTN
)-1;
437 for (Index
= 0; Index
< mNumberOfCpus
; Index
++) {
438 mRebased
[Index
] = FALSE
;
439 if (ApicId
!= (UINT32
)gSmmCpuPrivate
->ProcessorInfo
[Index
].ProcessorId
) {
440 SendSmiIpi ((UINT32
)gSmmCpuPrivate
->ProcessorInfo
[Index
].ProcessorId
);
442 // Wait for this AP to finish its 1st SMI
444 while (!mRebased
[Index
]);
447 // BSP will be Relocated later
454 // Relocate BSP's SMM base
456 ASSERT (BspIndex
!= (UINTN
)-1);
460 // Wait for the BSP to finish its 1st SMI
462 while (!mRebased
[BspIndex
]);
465 // Restore contents at address 0x38000
467 CopyMem (CpuStatePtr
, &BakBuf2
, sizeof (BakBuf2
));
468 CopyMem (U8Ptr
, BakBuf
, sizeof (BakBuf
));
472 SMM Ready To Lock event notification handler.
474 The CPU S3 data is copied to SMRAM for security and mSmmReadyToLock is set to
475 perform additional lock actions that must be performed from SMM on the next SMI.
477 @param[in] Protocol Points to the protocol's unique identifier.
478 @param[in] Interface Points to the interface instance.
479 @param[in] Handle The handle on which the interface was installed.
481 @retval EFI_SUCCESS Notification handler runs successfully.
485 SmmReadyToLockEventNotify (
486 IN CONST EFI_GUID
*Protocol
,
494 // Set SMM ready to lock flag and return
496 mSmmReadyToLock
= TRUE
;
501 The module Entry Point of the CPU SMM driver.
503 @param ImageHandle The firmware allocated handle for the EFI image.
504 @param SystemTable A pointer to the EFI System Table.
506 @retval EFI_SUCCESS The entry point is executed successfully.
507 @retval Other Some error occurs when executing this entry point.
513 IN EFI_HANDLE ImageHandle
,
514 IN EFI_SYSTEM_TABLE
*SystemTable
518 EFI_MP_SERVICES_PROTOCOL
*MpServices
;
519 UINTN NumberOfEnabledProcessors
;
535 // Initialize Debug Agent to support source level debug in SMM code
537 InitializeDebugAgent (DEBUG_AGENT_INIT_SMM
, NULL
, NULL
);
540 // Report the start of CPU SMM initialization.
544 EFI_COMPUTING_UNIT_HOST_PROCESSOR
| EFI_CU_HP_PC_SMM_INIT
548 // Fix segment address of the long-mode-switch jump
550 if (sizeof (UINTN
) == sizeof (UINT64
)) {
551 gSmmJmpAddr
.Segment
= LONG_MODE_CODE_SEGMENT
;
555 // Find out SMRR Base and SMRR Size
557 FindSmramInfo (&mCpuHotPlugData
.SmrrBase
, &mCpuHotPlugData
.SmrrSize
);
560 // Get MP Services Protocol
562 Status
= SystemTable
->BootServices
->LocateProtocol (&gEfiMpServiceProtocolGuid
, NULL
, (VOID
**)&MpServices
);
563 ASSERT_EFI_ERROR (Status
);
566 // Use MP Services Protocol to retrieve the number of processors and number of enabled processors
568 Status
= MpServices
->GetNumberOfProcessors (MpServices
, &mNumberOfCpus
, &NumberOfEnabledProcessors
);
569 ASSERT_EFI_ERROR (Status
);
570 ASSERT (mNumberOfCpus
<= PcdGet32 (PcdCpuMaxLogicalProcessorNumber
));
573 // If support CPU hot plug, PcdCpuSmmEnableBspElection should be set to TRUE.
574 // A constant BSP index makes no sense because it may be hot removed.
577 if (FeaturePcdGet (PcdCpuHotPlugSupport
)) {
579 ASSERT (FeaturePcdGet (PcdCpuSmmEnableBspElection
));
584 // Save the PcdCpuSmmCodeAccessCheckEnable value into a global variable.
586 mSmmCodeAccessCheckEnable
= PcdGetBool (PcdCpuSmmCodeAccessCheckEnable
);
587 DEBUG ((EFI_D_INFO
, "PcdCpuSmmCodeAccessCheckEnable = %d\n", mSmmCodeAccessCheckEnable
));
590 // If support CPU hot plug, we need to allocate resources for possibly hot-added processors
592 if (FeaturePcdGet (PcdCpuHotPlugSupport
)) {
593 mMaxNumberOfCpus
= PcdGet32 (PcdCpuMaxLogicalProcessorNumber
);
595 mMaxNumberOfCpus
= mNumberOfCpus
;
597 gSmmCpuPrivate
->SmmCoreEntryContext
.NumberOfCpus
= mMaxNumberOfCpus
;
600 // The CPU save state and code for the SMI entry point are tiled within an SMRAM
601 // allocated buffer. The minimum size of this buffer for a uniprocessor system
602 // is 32 KB, because the entry point is SMBASE + 32KB, and CPU save state area
603 // just below SMBASE + 64KB. If more than one CPU is present in the platform,
604 // then the SMI entry point and the CPU save state areas can be tiles to minimize
605 // the total amount SMRAM required for all the CPUs. The tile size can be computed
606 // by adding the // CPU save state size, any extra CPU specific context, and
607 // the size of code that must be placed at the SMI entry point to transfer
608 // control to a C function in the native SMM execution mode. This size is
609 // rounded up to the nearest power of 2 to give the tile size for a each CPU.
610 // The total amount of memory required is the maximum number of CPUs that
611 // platform supports times the tile size. The picture below shows the tiling,
612 // where m is the number of tiles that fit in 32KB.
614 // +-----------------------------+ <-- 2^n offset from Base of allocated buffer
615 // | CPU m+1 Save State |
616 // +-----------------------------+
617 // | CPU m+1 Extra Data |
618 // +-----------------------------+
620 // +-----------------------------+
621 // | CPU 2m SMI Entry |
622 // +#############################+ <-- Base of allocated buffer + 64 KB
623 // | CPU m-1 Save State |
624 // +-----------------------------+
625 // | CPU m-1 Extra Data |
626 // +-----------------------------+
628 // +-----------------------------+
629 // | CPU 2m-1 SMI Entry |
630 // +=============================+ <-- 2^n offset from Base of allocated buffer
631 // | . . . . . . . . . . . . |
632 // +=============================+ <-- 2^n offset from Base of allocated buffer
633 // | CPU 2 Save State |
634 // +-----------------------------+
635 // | CPU 2 Extra Data |
636 // +-----------------------------+
638 // +-----------------------------+
639 // | CPU m+1 SMI Entry |
640 // +=============================+ <-- Base of allocated buffer + 32 KB
641 // | CPU 1 Save State |
642 // +-----------------------------+
643 // | CPU 1 Extra Data |
644 // +-----------------------------+
646 // +-----------------------------+
647 // | CPU m SMI Entry |
648 // +#############################+ <-- Base of allocated buffer + 32 KB == CPU 0 SMBASE + 64 KB
649 // | CPU 0 Save State |
650 // +-----------------------------+
651 // | CPU 0 Extra Data |
652 // +-----------------------------+
654 // +-----------------------------+
655 // | CPU m-1 SMI Entry |
656 // +=============================+ <-- 2^n offset from Base of allocated buffer
657 // | . . . . . . . . . . . . |
658 // +=============================+ <-- 2^n offset from Base of allocated buffer
660 // +-----------------------------+
661 // | CPU 1 SMI Entry |
662 // +=============================+ <-- 2^n offset from Base of allocated buffer
664 // +-----------------------------+
665 // | CPU 0 SMI Entry |
666 // +#############################+ <-- Base of allocated buffer == CPU 0 SMBASE + 32 KB
670 // Retrieve CPU Family
672 AsmCpuid (CPUID_VERSION_INFO
, &RegEax
, NULL
, NULL
, NULL
);
673 FamilyId
= (RegEax
>> 8) & 0xf;
674 ModelId
= (RegEax
>> 4) & 0xf;
675 if (FamilyId
== 0x06 || FamilyId
== 0x0f) {
676 ModelId
= ModelId
| ((RegEax
>> 12) & 0xf0);
680 AsmCpuid (CPUID_EXTENDED_FUNCTION
, &RegEax
, NULL
, NULL
, NULL
);
681 if (RegEax
>= CPUID_EXTENDED_CPU_SIG
) {
682 AsmCpuid (CPUID_EXTENDED_CPU_SIG
, NULL
, NULL
, NULL
, &RegEdx
);
685 // Determine the mode of the CPU at the time an SMI occurs
686 // Intel(R) 64 and IA-32 Architectures Software Developer's Manual
687 // Volume 3C, Section 34.4.1.1
689 mSmmSaveStateRegisterLma
= EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT
;
690 if ((RegEdx
& BIT29
) != 0) {
691 mSmmSaveStateRegisterLma
= EFI_SMM_SAVE_STATE_REGISTER_LMA_64BIT
;
693 if (FamilyId
== 0x06) {
694 if (ModelId
== 0x17 || ModelId
== 0x0f || ModelId
== 0x1c) {
695 mSmmSaveStateRegisterLma
= EFI_SMM_SAVE_STATE_REGISTER_LMA_64BIT
;
700 // Compute tile size of buffer required to hold the CPU SMRAM Save State Map, extra CPU
701 // specific context in a PROCESSOR_SMM_DESCRIPTOR, and the SMI entry point. This size
702 // is rounded up to nearest power of 2.
704 TileCodeSize
= GetSmiHandlerSize ();
705 TileCodeSize
= ALIGN_VALUE(TileCodeSize
, SIZE_4KB
);
706 TileDataSize
= sizeof (SMRAM_SAVE_STATE_MAP
) + sizeof (PROCESSOR_SMM_DESCRIPTOR
);
707 TileDataSize
= ALIGN_VALUE(TileDataSize
, SIZE_4KB
);
708 TileSize
= TileDataSize
+ TileCodeSize
- 1;
709 TileSize
= 2 * GetPowerOfTwo32 ((UINT32
)TileSize
);
710 DEBUG ((EFI_D_INFO
, "SMRAM TileSize = 0x%08x (0x%08x, 0x%08x)\n", TileSize
, TileCodeSize
, TileDataSize
));
713 // If the TileSize is larger than space available for the SMI Handler of CPU[i],
714 // the PROCESSOR_SMM_DESCRIPTOR of CPU[i+1] and the SMRAM Save State Map of CPU[i+1],
715 // the ASSERT(). If this ASSERT() is triggered, then the SMI Handler size must be
718 ASSERT (TileSize
<= (SMRAM_SAVE_STATE_MAP_OFFSET
+ sizeof (SMRAM_SAVE_STATE_MAP
) - SMM_HANDLER_OFFSET
));
721 // Allocate buffer for all of the tiles.
723 // Intel(R) 64 and IA-32 Architectures Software Developer's Manual
724 // Volume 3C, Section 34.11 SMBASE Relocation
725 // For Pentium and Intel486 processors, the SMBASE values must be
726 // aligned on a 32-KByte boundary or the processor will enter shutdown
727 // state during the execution of a RSM instruction.
729 // Intel486 processors: FamilyId is 4
730 // Pentium processors : FamilyId is 5
732 BufferPages
= EFI_SIZE_TO_PAGES (SIZE_32KB
+ TileSize
* (mMaxNumberOfCpus
- 1));
733 if ((FamilyId
== 4) || (FamilyId
== 5)) {
734 Buffer
= AllocateAlignedPages (BufferPages
, SIZE_32KB
);
736 Buffer
= AllocateAlignedPages (BufferPages
, SIZE_4KB
);
738 ASSERT (Buffer
!= NULL
);
739 DEBUG ((EFI_D_INFO
, "SMRAM SaveState Buffer (0x%08x, 0x%08x)\n", Buffer
, EFI_PAGES_TO_SIZE(BufferPages
)));
742 // Allocate buffer for pointers to array in SMM_CPU_PRIVATE_DATA.
744 gSmmCpuPrivate
->ProcessorInfo
= (EFI_PROCESSOR_INFORMATION
*)AllocatePool (sizeof (EFI_PROCESSOR_INFORMATION
) * mMaxNumberOfCpus
);
745 ASSERT (gSmmCpuPrivate
->ProcessorInfo
!= NULL
);
747 gSmmCpuPrivate
->Operation
= (SMM_CPU_OPERATION
*)AllocatePool (sizeof (SMM_CPU_OPERATION
) * mMaxNumberOfCpus
);
748 ASSERT (gSmmCpuPrivate
->Operation
!= NULL
);
750 gSmmCpuPrivate
->CpuSaveStateSize
= (UINTN
*)AllocatePool (sizeof (UINTN
) * mMaxNumberOfCpus
);
751 ASSERT (gSmmCpuPrivate
->CpuSaveStateSize
!= NULL
);
753 gSmmCpuPrivate
->CpuSaveState
= (VOID
**)AllocatePool (sizeof (VOID
*) * mMaxNumberOfCpus
);
754 ASSERT (gSmmCpuPrivate
->CpuSaveState
!= NULL
);
756 mSmmCpuPrivateData
.SmmCoreEntryContext
.CpuSaveStateSize
= gSmmCpuPrivate
->CpuSaveStateSize
;
757 mSmmCpuPrivateData
.SmmCoreEntryContext
.CpuSaveState
= gSmmCpuPrivate
->CpuSaveState
;
760 // Allocate buffer for pointers to array in CPU_HOT_PLUG_DATA.
762 mCpuHotPlugData
.ApicId
= (UINT64
*)AllocatePool (sizeof (UINT64
) * mMaxNumberOfCpus
);
763 ASSERT (mCpuHotPlugData
.ApicId
!= NULL
);
764 mCpuHotPlugData
.SmBase
= (UINTN
*)AllocatePool (sizeof (UINTN
) * mMaxNumberOfCpus
);
765 ASSERT (mCpuHotPlugData
.SmBase
!= NULL
);
766 mCpuHotPlugData
.ArrayLength
= (UINT32
)mMaxNumberOfCpus
;
769 // Retrieve APIC ID of each enabled processor from the MP Services protocol.
770 // Also compute the SMBASE address, CPU Save State address, and CPU Save state
771 // size for each CPU in the platform
773 for (Index
= 0; Index
< mMaxNumberOfCpus
; Index
++) {
774 mCpuHotPlugData
.SmBase
[Index
] = (UINTN
)Buffer
+ Index
* TileSize
- SMM_HANDLER_OFFSET
;
775 gSmmCpuPrivate
->CpuSaveStateSize
[Index
] = sizeof(SMRAM_SAVE_STATE_MAP
);
776 gSmmCpuPrivate
->CpuSaveState
[Index
] = (VOID
*)(mCpuHotPlugData
.SmBase
[Index
] + SMRAM_SAVE_STATE_MAP_OFFSET
);
777 gSmmCpuPrivate
->Operation
[Index
] = SmmCpuNone
;
779 if (Index
< mNumberOfCpus
) {
780 Status
= MpServices
->GetProcessorInfo (MpServices
, Index
, &gSmmCpuPrivate
->ProcessorInfo
[Index
]);
781 ASSERT_EFI_ERROR (Status
);
782 mCpuHotPlugData
.ApicId
[Index
] = gSmmCpuPrivate
->ProcessorInfo
[Index
].ProcessorId
;
784 DEBUG ((EFI_D_INFO
, "CPU[%03x] APIC ID=%04x SMBASE=%08x SaveState=%08x Size=%08x\n",
786 (UINT32
)gSmmCpuPrivate
->ProcessorInfo
[Index
].ProcessorId
,
787 mCpuHotPlugData
.SmBase
[Index
],
788 gSmmCpuPrivate
->CpuSaveState
[Index
],
789 gSmmCpuPrivate
->CpuSaveStateSize
[Index
]
792 gSmmCpuPrivate
->ProcessorInfo
[Index
].ProcessorId
= INVALID_APIC_ID
;
793 mCpuHotPlugData
.ApicId
[Index
] = INVALID_APIC_ID
;
798 // Allocate SMI stacks for all processors.
800 if (FeaturePcdGet (PcdCpuSmmStackGuard
)) {
802 // 2 more pages is allocated for each processor.
803 // one is guard page and the other is known good stack.
805 // +-------------------------------------------+-----+-------------------------------------------+
806 // | Known Good Stack | Guard Page | SMM Stack | ... | Known Good Stack | Guard Page | SMM Stack |
807 // +-------------------------------------------+-----+-------------------------------------------+
809 // |<-------------- Processor 0 -------------->| |<-------------- Processor n -------------->|
811 mSmmStackSize
= EFI_PAGES_TO_SIZE (EFI_SIZE_TO_PAGES (PcdGet32 (PcdCpuSmmStackSize
)) + 2);
812 Stacks
= (UINT8
*) AllocatePages (gSmmCpuPrivate
->SmmCoreEntryContext
.NumberOfCpus
* (EFI_SIZE_TO_PAGES (PcdGet32 (PcdCpuSmmStackSize
)) + 2));
813 ASSERT (Stacks
!= NULL
);
814 mSmmStackArrayBase
= (UINTN
)Stacks
;
815 mSmmStackArrayEnd
= mSmmStackArrayBase
+ gSmmCpuPrivate
->SmmCoreEntryContext
.NumberOfCpus
* mSmmStackSize
- 1;
817 mSmmStackSize
= PcdGet32 (PcdCpuSmmStackSize
);
818 Stacks
= (UINT8
*) AllocatePages (EFI_SIZE_TO_PAGES (gSmmCpuPrivate
->SmmCoreEntryContext
.NumberOfCpus
* mSmmStackSize
));
819 ASSERT (Stacks
!= NULL
);
823 // Set SMI stack for SMM base relocation
825 gSmmInitStack
= (UINTN
) (Stacks
+ mSmmStackSize
- sizeof (UINTN
));
833 // Relocate SMM Base addresses to the ones allocated from SMRAM
835 mRebased
= (BOOLEAN
*)AllocateZeroPool (sizeof (BOOLEAN
) * mMaxNumberOfCpus
);
836 ASSERT (mRebased
!= NULL
);
840 // Call hook for BSP to perform extra actions in normal mode after all
841 // SMM base addresses have been relocated on all CPUs
843 SmmCpuFeaturesSmmRelocationComplete ();
846 // SMM Time initialization
848 InitializeSmmTimer ();
851 // Initialize MP globals
853 Cr3
= InitializeMpServiceData (Stacks
, mSmmStackSize
);
856 // Fill in SMM Reserved Regions
858 gSmmCpuPrivate
->SmmReservedSmramRegion
[0].SmramReservedStart
= 0;
859 gSmmCpuPrivate
->SmmReservedSmramRegion
[0].SmramReservedSize
= 0;
862 // Install the SMM Configuration Protocol onto a new handle on the handle database.
863 // The entire SMM Configuration Protocol is allocated from SMRAM, so only a pointer
864 // to an SMRAM address will be present in the handle database
866 Status
= SystemTable
->BootServices
->InstallMultipleProtocolInterfaces (
867 &gSmmCpuPrivate
->SmmCpuHandle
,
868 &gEfiSmmConfigurationProtocolGuid
, &gSmmCpuPrivate
->SmmConfiguration
,
871 ASSERT_EFI_ERROR (Status
);
874 // Install the SMM CPU Protocol into SMM protocol database
876 Status
= gSmst
->SmmInstallProtocolInterface (
878 &gEfiSmmCpuProtocolGuid
,
879 EFI_NATIVE_INTERFACE
,
882 ASSERT_EFI_ERROR (Status
);
885 // Expose address of CPU Hot Plug Data structure if CPU hot plug is supported.
887 if (FeaturePcdGet (PcdCpuHotPlugSupport
)) {
888 Status
= PcdSet64S (PcdCpuHotPlugDataAddress
, (UINT64
)(UINTN
)&mCpuHotPlugData
);
889 ASSERT_EFI_ERROR (Status
);
893 // Initialize SMM CPU Services Support
895 Status
= InitializeSmmCpuServices (mSmmCpuHandle
);
896 ASSERT_EFI_ERROR (Status
);
899 // register SMM Ready To Lock Protocol notification
901 Status
= gSmst
->SmmRegisterProtocolNotify (
902 &gEfiSmmReadyToLockProtocolGuid
,
903 SmmReadyToLockEventNotify
,
906 ASSERT_EFI_ERROR (Status
);
909 // Initialize SMM Profile feature
911 InitSmmProfile (Cr3
);
913 GetAcpiS3EnableFlag ();
914 InitSmmS3ResumeState (Cr3
);
916 DEBUG ((EFI_D_INFO
, "SMM CPU Module exit from SMRAM with EFI_SUCCESS\n"));
923 Find out SMRAM information including SMRR base and SMRR size.
925 @param SmrrBase SMRR base
926 @param SmrrSize SMRR size
931 OUT UINT32
*SmrrBase
,
937 EFI_SMM_ACCESS2_PROTOCOL
*SmmAccess
;
938 EFI_SMRAM_DESCRIPTOR
*CurrentSmramRange
;
939 EFI_SMRAM_DESCRIPTOR
*SmramRanges
;
940 UINTN SmramRangeCount
;
946 // Get SMM Access Protocol
948 Status
= gBS
->LocateProtocol (&gEfiSmmAccess2ProtocolGuid
, NULL
, (VOID
**)&SmmAccess
);
949 ASSERT_EFI_ERROR (Status
);
952 // Get SMRAM information
955 Status
= SmmAccess
->GetCapabilities (SmmAccess
, &Size
, NULL
);
956 ASSERT (Status
== EFI_BUFFER_TOO_SMALL
);
958 SmramRanges
= (EFI_SMRAM_DESCRIPTOR
*)AllocatePool (Size
);
959 ASSERT (SmramRanges
!= NULL
);
961 Status
= SmmAccess
->GetCapabilities (SmmAccess
, &Size
, SmramRanges
);
962 ASSERT_EFI_ERROR (Status
);
964 SmramRangeCount
= Size
/ sizeof (EFI_SMRAM_DESCRIPTOR
);
967 // Find the largest SMRAM range between 1MB and 4GB that is at least 256K - 4K in size
969 CurrentSmramRange
= NULL
;
970 for (Index
= 0, MaxSize
= SIZE_256KB
- EFI_PAGE_SIZE
; Index
< SmramRangeCount
; Index
++) {
972 // Skip any SMRAM region that is already allocated, needs testing, or needs ECC initialization
974 if ((SmramRanges
[Index
].RegionState
& (EFI_ALLOCATED
| EFI_NEEDS_TESTING
| EFI_NEEDS_ECC_INITIALIZATION
)) != 0) {
978 if (SmramRanges
[Index
].CpuStart
>= BASE_1MB
) {
979 if ((SmramRanges
[Index
].CpuStart
+ SmramRanges
[Index
].PhysicalSize
) <= BASE_4GB
) {
980 if (SmramRanges
[Index
].PhysicalSize
>= MaxSize
) {
981 MaxSize
= SmramRanges
[Index
].PhysicalSize
;
982 CurrentSmramRange
= &SmramRanges
[Index
];
988 ASSERT (CurrentSmramRange
!= NULL
);
990 *SmrrBase
= (UINT32
)CurrentSmramRange
->CpuStart
;
991 *SmrrSize
= (UINT32
)CurrentSmramRange
->PhysicalSize
;
995 for (Index
= 0; Index
< SmramRangeCount
; Index
++) {
996 if (SmramRanges
[Index
].CpuStart
< *SmrrBase
&& *SmrrBase
== (SmramRanges
[Index
].CpuStart
+ SmramRanges
[Index
].PhysicalSize
)) {
997 *SmrrBase
= (UINT32
)SmramRanges
[Index
].CpuStart
;
998 *SmrrSize
= (UINT32
)(*SmrrSize
+ SmramRanges
[Index
].PhysicalSize
);
1000 } else if ((*SmrrBase
+ *SmrrSize
) == SmramRanges
[Index
].CpuStart
&& SmramRanges
[Index
].PhysicalSize
> 0) {
1001 *SmrrSize
= (UINT32
)(*SmrrSize
+ SmramRanges
[Index
].PhysicalSize
);
1007 DEBUG ((EFI_D_INFO
, "SMRR Base: 0x%x, SMRR Size: 0x%x\n", *SmrrBase
, *SmrrSize
));
1011 Configure SMM Code Access Check feature on an AP.
1012 SMM Feature Control MSR will be locked after configuration.
1014 @param[in,out] Buffer Pointer to private data buffer.
1018 ConfigSmmCodeAccessCheckOnCurrentProcessor (
1023 UINT64 SmmFeatureControlMsr
;
1024 UINT64 NewSmmFeatureControlMsr
;
1027 // Retrieve the CPU Index from the context passed in
1029 CpuIndex
= *(UINTN
*)Buffer
;
1032 // Get the current SMM Feature Control MSR value
1034 SmmFeatureControlMsr
= SmmCpuFeaturesGetSmmRegister (CpuIndex
, SmmRegFeatureControl
);
1037 // Compute the new SMM Feature Control MSR value
1039 NewSmmFeatureControlMsr
= SmmFeatureControlMsr
;
1040 if (mSmmCodeAccessCheckEnable
) {
1041 NewSmmFeatureControlMsr
|= SMM_CODE_CHK_EN_BIT
;
1042 if (FeaturePcdGet (PcdCpuSmmFeatureControlMsrLock
)) {
1043 NewSmmFeatureControlMsr
|= SMM_FEATURE_CONTROL_LOCK_BIT
;
1048 // Only set the SMM Feature Control MSR value if the new value is different than the current value
1050 if (NewSmmFeatureControlMsr
!= SmmFeatureControlMsr
) {
1051 SmmCpuFeaturesSetSmmRegister (CpuIndex
, SmmRegFeatureControl
, NewSmmFeatureControlMsr
);
1055 // Release the spin lock user to serialize the updates to the SMM Feature Control MSR
1057 ReleaseSpinLock (mConfigSmmCodeAccessCheckLock
);
1061 Configure SMM Code Access Check feature for all processors.
1062 SMM Feature Control MSR will be locked after configuration.
1065 ConfigSmmCodeAccessCheck (
1073 // Check to see if the Feature Control MSR is supported on this CPU
1075 Index
= gSmmCpuPrivate
->SmmCoreEntryContext
.CurrentlyExecutingCpu
;
1076 if (!SmmCpuFeaturesIsSmmRegisterSupported (Index
, SmmRegFeatureControl
)) {
1077 mSmmCodeAccessCheckEnable
= FALSE
;
1082 // Check to see if the CPU supports the SMM Code Access Check feature
1083 // Do not access this MSR unless the CPU supports the SmmRegFeatureControl
1085 if ((AsmReadMsr64 (EFI_MSR_SMM_MCA_CAP
) & SMM_CODE_ACCESS_CHK_BIT
) == 0) {
1086 mSmmCodeAccessCheckEnable
= FALSE
;
1091 // Initialize the lock used to serialize the MSR programming in BSP and all APs
1093 InitializeSpinLock (mConfigSmmCodeAccessCheckLock
);
1096 // Acquire Config SMM Code Access Check spin lock. The BSP will release the
1097 // spin lock when it is done executing ConfigSmmCodeAccessCheckOnCurrentProcessor().
1099 AcquireSpinLock (mConfigSmmCodeAccessCheckLock
);
1102 // Enable SMM Code Access Check feature on the BSP.
1104 ConfigSmmCodeAccessCheckOnCurrentProcessor (&Index
);
1107 // Enable SMM Code Access Check feature for the APs.
1109 for (Index
= 0; Index
< gSmst
->NumberOfCpus
; Index
++) {
1110 if (Index
!= gSmmCpuPrivate
->SmmCoreEntryContext
.CurrentlyExecutingCpu
) {
1113 // Acquire Config SMM Code Access Check spin lock. The AP will release the
1114 // spin lock when it is done executing ConfigSmmCodeAccessCheckOnCurrentProcessor().
1116 AcquireSpinLock (mConfigSmmCodeAccessCheckLock
);
1119 // Call SmmStartupThisAp() to enable SMM Code Access Check on an AP.
1121 Status
= gSmst
->SmmStartupThisAp (ConfigSmmCodeAccessCheckOnCurrentProcessor
, Index
, &Index
);
1122 ASSERT_EFI_ERROR (Status
);
1125 // Wait for the AP to release the Config SMM Code Access Check spin lock.
1127 while (!AcquireSpinLockOrFail (mConfigSmmCodeAccessCheckLock
)) {
1132 // Release the Config SMM Code Access Check spin lock.
1134 ReleaseSpinLock (mConfigSmmCodeAccessCheckLock
);
1140 This API provides a way to allocate memory for page table.
1142 This API can be called more once to allocate memory for page tables.
1144 Allocates the number of 4KB pages of type EfiRuntimeServicesData and returns a pointer to the
1145 allocated buffer. The buffer returned is aligned on a 4KB boundary. If Pages is 0, then NULL
1146 is returned. If there is not enough memory remaining to satisfy the request, then NULL is
1149 @param Pages The number of 4 KB pages to allocate.
1151 @return A pointer to the allocated buffer or NULL if allocation fails.
1155 AllocatePageTableMemory (
1161 Buffer
= SmmCpuFeaturesAllocatePageTableMemory (Pages
);
1162 if (Buffer
!= NULL
) {
1165 return AllocatePages (Pages
);
1169 Perform the remaining tasks.
1173 PerformRemainingTasks (
1177 if (mSmmReadyToLock
) {
1179 // Start SMM Profile feature
1181 if (FeaturePcdGet (PcdCpuSmmProfileEnable
)) {
1185 // Create a mix of 2MB and 4KB page table. Update some memory ranges absent and execute-disable.
1189 // Configure SMM Code Access Check feature if available.
1191 ConfigSmmCodeAccessCheck ();
1193 SmmCpuFeaturesCompleteSmmReadyToLock ();
1196 // Clean SMM ready to lock flag
1198 mSmmReadyToLock
= FALSE
;
1203 Perform the pre tasks.
1211 RestoreSmmConfigurationInS3 ();