1 ;------------------------------------------------------------------------------ ;
2 ; Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>
3 ; This program and the accompanying materials
4 ; are licensed and made available under the terms and conditions of the BSD License
5 ; which accompanies this distribution. The full text of the license may be found at
6 ; http://opensource.org/licenses/bsd-license.php.
8 ; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
9 ; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
17 ; Exception handlers used in SM mode
19 ;-------------------------------------------------------------------------------
21 EXTERNDEF SmiPFHandler:PROC
22 EXTERNDEF gcSmiIdtr:FWORD
23 EXTERNDEF gcSmiGdtr:FWORD
28 NullSeg DQ 0 ; reserved by architecture
36 ProtModeCodeSeg32 LABEL QWORD
43 ProtModeSsSeg32 LABEL QWORD
78 ; TSS Segment for X64 specially
80 DW TSS_DESC_SIZE - 1 ; LimitLow
88 GDT_SIZE = $ - offset NullSeg
90 ; Create TSS Descriptor just after GDT
91 TssDescriptor LABEL BYTE
108 DW 0 ; I/O Map Base Address
109 TSS_DESC_SIZE = $ - offset TssDescriptor
112 ; This structure serves as a template for all processors.
126 DQ 0 ; fixed in InitializeMpServiceData()
132 PSD_SIZE = $ - offset gcPsd
135 ; CODE & DATA segments for SMM runtime
137 CODE_SEL = offset CodeSeg64 - offset NullSeg
138 DATA_SEL = offset DataSeg32 - offset NullSeg
139 CODE32_SEL = offset CodeSeg32 - offset NullSeg
141 gcSmiGdtr LABEL FWORD
145 gcSmiIdtr LABEL FWORD
151 ;------------------------------------------------------------------------------
152 ; _SmiExceptionEntryPoints is the collection of exception entry points followed
153 ; by a common exception handler.
155 ; Stack frame would be as follows as specified in IA32 manuals:
157 ; +---------------------+ <-- 16-byte aligned ensured by processor
159 ; +---------------------+
161 ; +---------------------+
163 ; +---------------------+
165 ; +---------------------+
167 ; +---------------------+
169 ; +---------------------+
171 ; +---------------------+
173 ; +---------------------+ <-- RBP, 16-byte aligned
175 ; RSP set to odd multiple of 8 at @CommonEntryPoint means ErrCode PRESENT
176 ;------------------------------------------------------------------------------
177 PageFaultIdtHandlerSmmProfile PROC
178 push 0eh ; Page Fault
179 test spl, 8 ; odd multiple of 8 => ErrCode present
181 push [rsp] ; duplicate INT# if no ErrCode
182 mov qword ptr [rsp + 8], 0
188 ; Since here the stack pointer is 16-byte aligned, so
189 ; EFI_FX_SAVE_STATE_X64 of EFI_SYSTEM_CONTEXT_x64
193 ;; UINT64 Rdi, Rsi, Rbp, Rsp, Rbx, Rdx, Rcx, Rax;
194 ;; UINT64 R8, R9, R10, R11, R12, R13, R14, R15;
207 push qword ptr [rbp + 48] ; RSP
208 push qword ptr [rbp] ; RBP
212 ;; UINT64 Gs, Fs, Es, Ds, Cs, Ss; insure high 16 bits of each is zero
213 movzx rax, word ptr [rbp + 56]
215 movzx rax, word ptr [rbp + 32]
227 push qword ptr [rbp + 24]
229 ;; UINT64 Gdtr[2], Idtr[2];
243 push qword ptr [rbp + 40]
245 ;; UINT64 Cr0, Cr1, Cr2, Cr3, Cr4, Cr8;
261 ;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
275 ;; FX_SAVE_STATE_X64 FxSaveState;
279 db 0fh, 0aeh, 00000111y ;fxsave [rdi]
281 ; UEFI calling convention for x64 requires that Direction flag in EFLAGs is clear
284 ;; UINT32 ExceptionData;
285 push qword ptr [rbp + 16]
287 ;; call into exception handler
289 mov rax, SmiPFHandler
291 ;; Prepare parameter and call
294 ; Per X64 calling convention, allocate maximum parameter stack space
295 ; and make sure RSP is 16-byte aligned
303 ;; UINT64 ExceptionData;
306 ;; FX_SAVE_STATE_X64 FxSaveState;
309 db 0fh, 0aeh, 00001110y ; fxrstor [rsi]
312 ;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;
313 ;; Skip restoration of DRx registers to support debuggers
314 ;; that set breakpoints in interrupt/exception context
317 ;; UINT64 Cr0, Cr1, Cr2, Cr3, Cr4, Cr8;
320 add rsp, 8 ; not for Cr1
331 pop qword ptr [rbp + 40]
334 ;; UINT64 Gdtr[2], Idtr[2];
335 ;; Best not let anyone mess with these particular registers...
339 pop qword ptr [rbp + 24]
341 ;; UINT64 Gs, Fs, Es, Ds, Cs, Ss;
343 ; mov gs, rax ; not for gs
345 ; mov fs, rax ; not for fs
346 ; (X64 will not use fs and gs, so we do not restore it)
351 pop qword ptr [rbp + 32] ; for cs
352 pop qword ptr [rbp + 56] ; for ss
354 ;; UINT64 Rdi, Rsi, Rbp, Rsp, Rbx, Rdx, Rcx, Rax;
355 ;; UINT64 R8, R9, R10, R11, R12, R13, R14, R15;
358 add rsp, 8 ; not for rbp
359 pop qword ptr [rbp + 48] ; for rsp
375 ; Enable TF bit after page fault handler runs
376 bts dword ptr [rsp + 40], 8 ;RFLAGS
379 add rsp, 16 ; skip INT# & ErrCode
381 PageFaultIdtHandlerSmmProfile ENDP