2 SSDT for RhProxy Driver.
4 Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
5 This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
15 DefinitionBlock ("RHPX.aml", "SSDT", 1, "MSFT", "RHPROXY", 1)
20 // Test peripheral device node for MinnowBoardMax
24 Name(_HID, "MSFT8000")
25 Name(_CID, "MSFT8000")
28 Name(_CRS, ResourceTemplate()
31 SPISerialBus( // Pin 5, 7, 9 , 11 of JP1 for SIO_SPI
32 1, // Device selection
33 PolarityLow, // Device selection polarity
34 FourWireMode, // wiremode
36 ControllerInitiated, // slave mode
37 8000000, // Connection speed
38 ClockPolarityLow, // Clock polarity
39 ClockPhaseSecond, // clock phase
40 "\\_SB.SPI1", // ResourceSource: SPI bus controller name
41 0, // ResourceSourceIndex
42 ResourceConsumer, // Resource usage
43 JSPI, // DescriptorName: creates name for offset of resource descriptor
47 I2CSerialBus( // Pin 13, 15 of JP1, for SIO_I2C5 (signal)
48 0xFF, // SlaveAddress: bus address (TBD)
49 , // SlaveMode: default to ControllerInitiated
50 400000, // ConnectionSpeed: in Hz
51 , // Addressing Mode: default to 7 bit
52 "\\_SB.I2C6", // ResourceSource: I2C bus controller name (For MinnowBoard Max, hardware I2C5(0-based) is reported as ACPI I2C6(1-based))
55 JI2C, // Descriptor Name: creates name for offset of resource descriptor
59 UARTSerialBus( // Pin 17, 19 of JP1, for SIO_UART2
60 115200, // InitialBaudRate: in bits ber second
61 , // BitsPerByte: default to 8 bits
62 , // StopBits: Defaults to one bit
63 0xfc, // LinesInUse: 8 1-bit flags to declare line enabled
64 , // IsBigEndian: default to LittleEndian
65 , // Parity: Defaults to no parity
66 , // FlowControl: Defaults to no flow control
67 32, // ReceiveBufferSize
68 32, // TransmitBufferSize
69 "\\_SB.URT2", // ResourceSource: UART bus controller name
72 UAR2, // DescriptorName: creates name for offset of resource descriptor
76 GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO2",) {0} // Pin 21 of JP1 (GPIO_S5[00])
78 GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO2",) {0}
81 GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO2",) {1} // Pin 23 of JP1 (GPIO_S5[01])
83 GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO2",) {1}
86 GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO2",) {2} // Pin 25 of JP1 (GPIO_S5[02])
88 GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO2",) {2}
91 UARTSerialBus( // Pin 6, 8, 10, 12 of JP1, for SIO_UART1
92 115200, // InitialBaudRate: in bits ber second
93 , // BitsPerByte: default to 8 bits
94 , // StopBits: Defaults to one bit
95 0xfc, // LinesInUse: 8 1-bit flags to declare line enabled
96 , // IsBigEndian: default to LittleEndian
97 , // Parity: Defaults to no parity
98 FlowControlHardware, // FlowControl: Defaults to no flow control
99 32, // ReceiveBufferSize
100 32, // TransmitBufferSize
101 "\\_SB.URT1", // ResourceSource: UART bus controller name
104 UAR1, // DescriptorName: creates name for offset of resource descriptor
108 GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {62} // Pin 14 of JP1 (GPIO_SC[62])
110 GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {62}
113 GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {63} // Pin 16 of JP1 (GPIO_SC[63])
115 GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {63}
118 GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {65} // Pin 18 of JP1 (GPIO_SC[65])
120 GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {65}
123 GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {64} // Pin 20 of JP1 (GPIO_SC[64])
125 GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {64}
128 GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {94} // Pin 22 of JP1 (GPIO_SC[94])
130 GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {94}
133 GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {95} // Pin 24 of JP1 (GPIO_SC[95])
135 GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {95}
138 GpioIo (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPO0",) {54} // Pin 26 of JP1 (GPIO_SC[54])
140 GpioInt(Edge, ActiveBoth, SharedAndWake, PullNone, 0,"\\_SB.GPO0",) {54}
145 ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
149 Package(2) { "bus-SPI-SPI0", Package() { 0 }},
151 // TODO: Intel will need to provide the right value for SPI0 properties
152 Package(2) { "SPI0-MinClockInHz", 100000 },
153 Package(2) { "SPI0-MaxClockInHz", 15000000 },
154 // SupportedDataBitLengths takes a list of support data bit length
155 // Example : Package(2) { "SPI0-SupportedDataBitLengths", Package() { 8, 7, 16 }},
156 Package(2) { "SPI0-SupportedDataBitLengths", Package() { 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32 }},
158 Package(2) { "bus-I2C-I2C5", Package() { 1 }},
160 Package(2) { "bus-UART-UART2", Package() { 2 }},
161 Package(2) { "bus-UART-UART1", Package() { 9 }},