Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/AcpiTables/Ssdt/Cpu0Ist.asl

   1 /*-----------------------------------------------------------------------------
   2 -------------------------------------------------------------------------------
   3
   4
   5  Intel Silvermont Processor Power Management BIOS Reference Code
   6
   7  Copyright (c) 2006 - 2014, Intel Corporation
   8
   9   This program and the accompanying materials are licensed and made available under
  10   the terms and conditions of the BSD License that accompanies this distribution.
  11   The full text of the license may be found at
  12   http://opensource.org/licenses/bsd-license.php.
  13
  14   THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  15   WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  16
  17
  18  Filename:    CPU0IST.ASL
  19
  20  Revision:    Refer to Readme
  21
  22  Date:        Refer to Readme
  23
  24 --------------------------------------------------------------------------------
  25 -------------------------------------------------------------------------------
  26
  27  This Processor Power Management BIOS Source Code is furnished under license
  28  and may only be used or copied in accordance with the terms of the license.
  29  The information in this document is furnished for informational use only, is
  30  subject to change without notice, and should not be construed as a commitment
  31  by Intel Corporation. Intel Corporation assumes no responsibility or liability
  32  for any errors or inaccuracies that may appear in this document or any
  33  software that may be provided in association with this document.
  34
  35  Except as permitted by such license, no part of this document may be
  36  reproduced, stored in a retrieval system, or transmitted in any form or by
  37  any means without the express written consent of Intel Corporation.
  38
  39  WARNING: You are authorized and licensed to install and use this BIOS code
  40  ONLY on an IST PC. This utility may damage any system that does not
  41  meet these requirements.
  42
  43     An IST PC is a computer which
  44     (1) Is capable of seamlessly and automatically transitioning among
  45     multiple performance states (potentially operating at different
  46     efficiency ratings) based upon power source changes, END user
  47     preference, processor performance demand, and thermal conditions; and
  48     (2) Includes an Intel Pentium II processors, Intel Pentium III
  49     processor, Mobile Intel Pentium III Processor-M, Mobile Intel Pentium 4
  50     Processor-M, Intel Pentium M Processor, or any other future Intel
  51     processors that incorporates the capability to transition between
  52     different performance states by altering some, or any combination of,
  53     the following processor attributes: core voltage, core frequency, bus
  54     frequency, number of processor cores available, or any other attribute
  55     that changes the efficiency (instructions/unit time-power) at which the
  56     processor operates.
  57
  58 -------------------------------------------------------------------------------
  59 -------------------------------------------------------------------------------
  60
  61 NOTES:
  62     (1) <TODO> - IF the trap range and port definitions do not match those
  63     specified by this reference code, this file must be modified IAW the
  64     individual implmentation.
  65
  66 --------------------------------------------------------------------------------
  67 ------------------------------------------------------------------------------*/
  68
  69
  70 DefinitionBlock (
  71     "CPU0IST.aml",
  72     "SSDT",
  73     0x01,
  74     "PmRef",
  75     "Cpu0Ist",
  76     0x3000
  77     )
  78 {
  79     External (\_PR.CPU0, DeviceObj)
  80     External (PDC0)
  81     External (CFGD)
  82
  83     Scope(\_PR.CPU0)
  84     {
  85         //OperationRegion (DEB0, SystemIO, 0x80, 1)    //DBG
  86         //Field (DEB0, ByteAcc,NoLock,Preserve)        //DBG
  87         //{ DBG8, 8,}                                  //DBG
  88
  89         Name(_PPC, 0)        // Initialize as All States Available.
  90
  91         // NOTE:  For CMP systems; this table is not loaded unless
  92         //      the required driver support is present.
  93         //      So, we do not check for those cases here.
  94         //
  95         //   CFGD[0] = GV3 Capable/Enabled
  96         //   PDCx[0]  = OS Capable of Hardware P-State control
  97         //
  98         Method(_PCT,0)
  99         {
 100             If(LAnd(And(CFGD,0x0001), And(PDC0,0x0001)))
 101             {
 102                 //Store(0xA0,DBG8) //DBG
 103                 Return(Package()    // Native Mode
 104                 {
 105                     ResourceTemplate(){Register(FfixedHW, 0, 0, 0)},
 106                     ResourceTemplate(){Register(FfixedHW, 0, 0, 0)}
 107                 })
 108             }
 109             // @NOTE: IO Trap is not supported. Therefore should not expose any IO interface for _PCT
 110             // For all other cases, report control through the
 111             // SMI interface.  (The port used for SMM control is fixed up
 112             // by the initialization code.)
 113             //
 114             Return(Package()        // SMM Mode
 115             {
 116                ResourceTemplate(){Register(FfixedHW, 0, 0, 0)},
 117                ResourceTemplate(){Register(FfixedHW, 0, 0, 0)}
 118             })
 119         }
 120
 121
 122         // NOTE:  For CMP systems; this table is not loaded if MP
 123         //      driver support is not present or P-State are disabled.
 124         //
 125         Method(_PSS,0)
 126         {
 127             //
 128             // Report NSPP if:
 129             //   (1) GV3 capable (Not checked, see above.)
 130             //   (2) Driver support direct hardware control
 131             //   (3) MP driver support present (Not checked, see above.)
 132             // else;
 133             //   Report SPSS
 134             //
 135             //   PDCx[0]  = OS Capable of Hardware P-State control
 136             //
 137             If(And(PDC0,0x0001)){
 138                 //Store(0xB0,DBG8) //DBG
 139                 Return(NPSS)
 140             }
 141             //Store(0xBF,DBG8) //DBG
 142             // Otherwise, report SMM mode
 143             //
 144             Return(SPSS)
 145
 146         }
 147
 148         Name(SPSS,Package()
 149         {
 150             Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
 151             Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
 152             Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
 153             Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
 154             Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
 155             Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
 156             Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
 157             Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
 158             Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
 159             Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
 160             Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
 161             Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
 162             Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
 163             Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
 164             Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
 165             Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}
 166         })
 167
 168         Name(NPSS,Package()
 169         {
 170             Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
 171             Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
 172             Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
 173             Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
 174             Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
 175             Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
 176             Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
 177             Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
 178             Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
 179             Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
 180             Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
 181             Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
 182             Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
 183             Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
 184             Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000},
 185             Package(){0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000, 0x80000000}
 186         })
 187
 188         // The _PSD object provides information to the OSPM related
 189         // to P-State coordination between processors in a multi-processor
 190         // configurations.
 191         //
 192         Method(_PSD,0)
 193         {
 194             //
 195             // IF CMP is supported/enabled
 196             //   IF quad core processor
 197             //     IF PDC[11]
 198             //         Report 4 processors and HW_ALL as the coordination type
 199             //     ELSE
 200             //         Report 4 processors and SW_ALL as the coordination type
 201             //   ELSE
 202             //     IF PDC[11]
 203             //         Report 2 processors and HW_ALL as the coordination type
 204             //     ELSE
 205             //         Report 2 processors and SW_ALL as the coordination type
 206             // ELSE
 207             //    Report 1 processor and SW_ALL as the coordination type
 208             //    (Domain 0)
 209             //
 210             //   CFGD[24] = Two or more cores enabled
 211             //   CFGD[23] = Four cores enabled
 212             //   PDCx[11] = Hardware coordination with hardware feedback
 213             //
 214
 215             If(And(CFGD,0x1000000))    // CMP Enabled.
 216             {
 217               If(And(CFGD,0x800000))    // 2 or 4 process.
 218                 {
 219                   If(And(PDC0,0x0800))
 220                   {
 221                       Return(Package(){    // HW_ALL
 222                         Package(){
 223                             5,              // # entries.
 224                             0,              // Revision.
 225                             0,              // Domain #.
 226                             0xFE,           // Coord Type- HW_ALL.
 227                             4               // # processors.
 228                         }
 229                       })
 230                   } // If(And(PDC0,0x0800))
 231                    Return(Package(){        // SW_ALL
 232                      Package(){
 233                         5,                  // # entries.
 234                         0,                  // Revision.
 235                         0,                  // Domain #.
 236                         0xFC,               // Coord Type- SW_ALL.
 237                         4                   // # processors.
 238                      }
 239                     })
 240                 } else {
 241                   Return(Package(){        // HW_ALL
 242                       Package(){
 243                           5,                  // # entries.
 244                           0,                  // Revision.
 245                           0,                  // Domain #.
 246                           0xFE,               // Coord Type- HW_ALL.
 247                           2                   // # processors.
 248                       }
 249                   })
 250                 }
 251             }    // If(And(CFGD,0x1000000))    // CMP Enabled.
 252
 253             Return(Package(){              // SW_ALL
 254                 Package(){
 255                     5,                        // # entries.
 256                     0,                        // Revision.
 257                     0,                        // Domain #.
 258                     0xFC,                     // Coord Type- SW_ALL.
 259                     1                         // # processors.
 260                 }
 261             })
 262         } // Method(_PSD,0)
 263     } // Scope(\_PR.CPU0)
 264 } // End of Definition Block
 265
 266